1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
33 def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
37 def SDTX86BrCond : SDTypeProfile<0, 3,
38 [SDTCisVT<0, OtherVT>,
39 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
41 def SDTX86SetCC : SDTypeProfile<1, 2,
43 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
47 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
49 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
50 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
51 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
53 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
54 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
57 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
59 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
63 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
65 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
67 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
69 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
71 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
73 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
75 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
77 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
78 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
79 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
80 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
82 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
84 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
86 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
87 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
89 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
91 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
92 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
94 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
95 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
97 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
98 [SDNPHasChain, SDNPMayStore,
99 SDNPMayLoad, SDNPMemOperand]>;
100 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
101 [SDNPHasChain, SDNPMayStore,
102 SDNPMayLoad, SDNPMemOperand]>;
103 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
104 [SDNPHasChain, SDNPMayStore,
105 SDNPMayLoad, SDNPMemOperand]>;
106 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
107 [SDNPHasChain, SDNPMayStore,
108 SDNPMayLoad, SDNPMemOperand]>;
109 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
110 [SDNPHasChain, SDNPMayStore,
111 SDNPMayLoad, SDNPMemOperand]>;
112 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
113 [SDNPHasChain, SDNPMayStore,
114 SDNPMayLoad, SDNPMemOperand]>;
115 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
116 [SDNPHasChain, SDNPMayStore,
117 SDNPMayLoad, SDNPMemOperand]>;
118 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
119 [SDNPHasChain, SDNPOptInFlag]>;
121 def X86vastart_save_xmm_regs :
122 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
123 SDT_X86VASTART_SAVE_XMM_REGS,
126 def X86callseq_start :
127 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
128 [SDNPHasChain, SDNPOutFlag]>;
130 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
131 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
133 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
134 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
136 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
137 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
138 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
139 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
142 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
143 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
145 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
146 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
148 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
149 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
150 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
151 SDT_X86SegmentBaseAddress, []>;
153 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
156 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
157 [SDNPHasChain, SDNPOptInFlag]>;
159 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags>;
160 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
161 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags>;
162 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>;
163 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
164 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
166 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
168 //===----------------------------------------------------------------------===//
169 // X86 Operand Definitions.
172 def i32imm_pcrel : Operand<i32> {
173 let PrintMethod = "print_pcrel_imm";
176 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
177 // the index operand of an address, to conform to x86 encoding restrictions.
178 def ptr_rc_nosp : PointerLikeRegClass<1>;
180 // *mem - Operand definitions for the funky X86 addressing mode operands.
182 def X86MemAsmOperand : AsmOperandClass {
186 class X86MemOperand<string printMethod> : Operand<iPTR> {
187 let PrintMethod = printMethod;
188 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
189 let ParserMatchClass = X86MemAsmOperand;
192 def i8mem : X86MemOperand<"printi8mem">;
193 def i16mem : X86MemOperand<"printi16mem">;
194 def i32mem : X86MemOperand<"printi32mem">;
195 def i64mem : X86MemOperand<"printi64mem">;
196 def i128mem : X86MemOperand<"printi128mem">;
197 def i256mem : X86MemOperand<"printi256mem">;
198 def f32mem : X86MemOperand<"printf32mem">;
199 def f64mem : X86MemOperand<"printf64mem">;
200 def f80mem : X86MemOperand<"printf80mem">;
201 def f128mem : X86MemOperand<"printf128mem">;
202 def f256mem : X86MemOperand<"printf256mem">;
204 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
205 // plain GR64, so that it doesn't potentially require a REX prefix.
206 def i8mem_NOREX : Operand<i64> {
207 let PrintMethod = "printi8mem";
208 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
209 let ParserMatchClass = X86MemAsmOperand;
212 def lea32mem : Operand<i32> {
213 let PrintMethod = "printlea32mem";
214 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
215 let ParserMatchClass = X86MemAsmOperand;
218 def SSECC : Operand<i8> {
219 let PrintMethod = "printSSECC";
222 def piclabel: Operand<i32> {
223 let PrintMethod = "printPICLabel";
226 def ImmSExt8AsmOperand : AsmOperandClass {
227 let Name = "ImmSExt8";
228 let SuperClass = ImmAsmOperand;
231 // A couple of more descriptive operand definitions.
232 // 16-bits but only 8 bits are significant.
233 def i16i8imm : Operand<i16> {
234 let ParserMatchClass = ImmSExt8AsmOperand;
236 // 32-bits but only 8 bits are significant.
237 def i32i8imm : Operand<i32> {
238 let ParserMatchClass = ImmSExt8AsmOperand;
241 // Branch targets have OtherVT type and print as pc-relative values.
242 def brtarget : Operand<OtherVT> {
243 let PrintMethod = "print_pcrel_imm";
246 def brtarget8 : Operand<OtherVT> {
247 let PrintMethod = "print_pcrel_imm";
250 //===----------------------------------------------------------------------===//
251 // X86 Complex Pattern Definitions.
254 // Define X86 specific addressing mode.
255 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
256 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
257 [add, sub, mul, X86mul_imm, shl, or, frameindex],
259 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
260 [tglobaltlsaddr], []>;
262 //===----------------------------------------------------------------------===//
263 // X86 Instruction Predicate Definitions.
264 def HasMMX : Predicate<"Subtarget->hasMMX()">;
265 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
266 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
267 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
268 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
269 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
270 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
271 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
272 def HasAVX : Predicate<"Subtarget->hasAVX()">;
273 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
274 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
275 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
276 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
277 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
278 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
279 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
280 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
281 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
282 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
283 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
284 "TM.getCodeModel() != CodeModel::Kernel">;
285 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
286 "TM.getCodeModel() == CodeModel::Kernel">;
287 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
288 def OptForSpeed : Predicate<"!OptForSize">;
289 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
290 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
292 //===----------------------------------------------------------------------===//
293 // X86 Instruction Format Definitions.
296 include "X86InstrFormats.td"
298 //===----------------------------------------------------------------------===//
299 // Pattern fragments...
302 // X86 specific condition code. These correspond to CondCode in
303 // X86InstrInfo.h. They must be kept in synch.
304 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
305 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
306 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
307 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
308 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
309 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
310 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
311 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
312 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
313 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
314 def X86_COND_NO : PatLeaf<(i8 10)>;
315 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
316 def X86_COND_NS : PatLeaf<(i8 12)>;
317 def X86_COND_O : PatLeaf<(i8 13)>;
318 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
319 def X86_COND_S : PatLeaf<(i8 15)>;
321 def i16immSExt8 : PatLeaf<(i16 imm), [{
322 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
323 // sign extended field.
324 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
327 def i32immSExt8 : PatLeaf<(i32 imm), [{
328 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
329 // sign extended field.
330 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
333 // Helper fragments for loads.
334 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
335 // known to be 32-bit aligned or better. Ditto for i8 to i16.
336 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
337 LoadSDNode *LD = cast<LoadSDNode>(N);
338 if (const Value *Src = LD->getSrcValue())
339 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
340 if (PT->getAddressSpace() > 255)
342 ISD::LoadExtType ExtType = LD->getExtensionType();
343 if (ExtType == ISD::NON_EXTLOAD)
345 if (ExtType == ISD::EXTLOAD)
346 return LD->getAlignment() >= 2 && !LD->isVolatile();
350 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
351 LoadSDNode *LD = cast<LoadSDNode>(N);
352 if (const Value *Src = LD->getSrcValue())
353 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
354 if (PT->getAddressSpace() > 255)
356 ISD::LoadExtType ExtType = LD->getExtensionType();
357 if (ExtType == ISD::EXTLOAD)
358 return LD->getAlignment() >= 2 && !LD->isVolatile();
362 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
363 LoadSDNode *LD = cast<LoadSDNode>(N);
364 if (const Value *Src = LD->getSrcValue())
365 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
366 if (PT->getAddressSpace() > 255)
368 ISD::LoadExtType ExtType = LD->getExtensionType();
369 if (ExtType == ISD::NON_EXTLOAD)
371 if (ExtType == ISD::EXTLOAD)
372 return LD->getAlignment() >= 4 && !LD->isVolatile();
376 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
377 LoadSDNode *LD = cast<LoadSDNode>(N);
378 if (const Value *Src = LD->getSrcValue())
379 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
380 if (PT->getAddressSpace() > 255)
382 if (LD->isVolatile())
384 ISD::LoadExtType ExtType = LD->getExtensionType();
385 if (ExtType == ISD::NON_EXTLOAD)
387 if (ExtType == ISD::EXTLOAD)
388 return LD->getAlignment() >= 4;
392 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
393 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
394 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
395 return PT->getAddressSpace() == 256;
399 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
400 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
401 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
402 return PT->getAddressSpace() == 257;
406 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{
407 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
408 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
409 if (PT->getAddressSpace() > 255)
413 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{
414 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
415 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
416 if (PT->getAddressSpace() > 255)
421 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{
422 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
423 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
424 if (PT->getAddressSpace() > 255)
428 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{
429 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
430 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
431 if (PT->getAddressSpace() > 255)
435 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{
436 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
437 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
438 if (PT->getAddressSpace() > 255)
443 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
444 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
445 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
447 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
448 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
449 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
450 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
451 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
452 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
454 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
455 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
456 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
457 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
458 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
459 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
462 // An 'and' node with a single use.
463 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
464 return N->hasOneUse();
466 // An 'srl' node with a single use.
467 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
468 return N->hasOneUse();
470 // An 'trunc' node with a single use.
471 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
472 return N->hasOneUse();
475 // 'shld' and 'shrd' instruction patterns. Note that even though these have
476 // the srl and shl in their patterns, the C++ code must still check for them,
477 // because predicates are tested before children nodes are explored.
479 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
480 (or (srl node:$src1, node:$amt1),
481 (shl node:$src2, node:$amt2)), [{
482 assert(N->getOpcode() == ISD::OR);
483 return N->getOperand(0).getOpcode() == ISD::SRL &&
484 N->getOperand(1).getOpcode() == ISD::SHL &&
485 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
486 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
487 N->getOperand(0).getConstantOperandVal(1) ==
488 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
491 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
492 (or (shl node:$src1, node:$amt1),
493 (srl node:$src2, node:$amt2)), [{
494 assert(N->getOpcode() == ISD::OR);
495 return N->getOperand(0).getOpcode() == ISD::SHL &&
496 N->getOperand(1).getOpcode() == ISD::SRL &&
497 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
498 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
499 N->getOperand(0).getConstantOperandVal(1) ==
500 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
503 //===----------------------------------------------------------------------===//
504 // Instruction list...
507 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
508 // a stack adjustment and the codegen must know that they may modify the stack
509 // pointer before prolog-epilog rewriting occurs.
510 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
511 // sub / add which can clobber EFLAGS.
512 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
513 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
515 [(X86callseq_start timm:$amt)]>,
516 Requires<[In32BitMode]>;
517 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
519 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
520 Requires<[In32BitMode]>;
523 // x86-64 va_start lowering magic.
524 let usesCustomDAGSchedInserter = 1 in
525 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
528 i64imm:$regsavefi, i64imm:$offset,
530 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
531 [(X86vastart_save_xmm_regs GR8:$al,
536 let neverHasSideEffects = 1 in {
537 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
538 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
539 "nopl\t$zero", []>, TB;
543 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int 3", []>;
544 def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
547 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
548 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
552 //===----------------------------------------------------------------------===//
553 // Control Flow Instructions...
556 // Return instructions.
557 let isTerminator = 1, isReturn = 1, isBarrier = 1,
558 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
559 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
562 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
564 [(X86retflag imm:$amt)]>;
567 // All branches are RawFrm, Void, Branch, and Terminators
568 let isBranch = 1, isTerminator = 1 in
569 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
570 I<opcode, RawFrm, (outs), ins, asm, pattern>;
572 let isBranch = 1, isBarrier = 1 in {
573 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
574 def JMP8 : IBr<0xEB, (ins brtarget8:$dst), "jmp\t$dst", []>;
578 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
579 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
580 [(brind GR32:$dst)]>;
581 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
582 [(brind (loadi32 addr:$dst))]>;
585 // Conditional branches
586 let Uses = [EFLAGS] in {
587 // Short conditional jumps
588 def JO8 : IBr<0x70, (ins brtarget8:$dst), "jo\t$dst", []>;
589 def JNO8 : IBr<0x71, (ins brtarget8:$dst), "jno\t$dst", []>;
590 def JB8 : IBr<0x72, (ins brtarget8:$dst), "jb\t$dst", []>;
591 def JAE8 : IBr<0x73, (ins brtarget8:$dst), "jae\t$dst", []>;
592 def JE8 : IBr<0x74, (ins brtarget8:$dst), "je\t$dst", []>;
593 def JNE8 : IBr<0x75, (ins brtarget8:$dst), "jne\t$dst", []>;
594 def JBE8 : IBr<0x76, (ins brtarget8:$dst), "jbe\t$dst", []>;
595 def JA8 : IBr<0x77, (ins brtarget8:$dst), "ja\t$dst", []>;
596 def JS8 : IBr<0x78, (ins brtarget8:$dst), "js\t$dst", []>;
597 def JNS8 : IBr<0x79, (ins brtarget8:$dst), "jns\t$dst", []>;
598 def JP8 : IBr<0x7A, (ins brtarget8:$dst), "jp\t$dst", []>;
599 def JNP8 : IBr<0x7B, (ins brtarget8:$dst), "jnp\t$dst", []>;
600 def JL8 : IBr<0x7C, (ins brtarget8:$dst), "jl\t$dst", []>;
601 def JGE8 : IBr<0x7D, (ins brtarget8:$dst), "jge\t$dst", []>;
602 def JLE8 : IBr<0x7E, (ins brtarget8:$dst), "jle\t$dst", []>;
603 def JG8 : IBr<0x7F, (ins brtarget8:$dst), "jg\t$dst", []>;
605 def JCXZ8 : IBr<0xE3, (ins brtarget8:$dst), "jcxz\t$dst", []>;
607 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
608 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
609 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
610 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
611 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
612 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
613 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
614 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
615 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
616 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
617 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
618 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
620 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
621 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
622 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
623 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
624 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
625 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
626 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
627 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
629 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
630 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
631 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
632 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
633 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
634 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
635 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
636 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
637 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
638 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
639 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
640 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
643 //===----------------------------------------------------------------------===//
644 // Call Instructions...
647 // All calls clobber the non-callee saved registers. ESP is marked as
648 // a use to prevent stack-pointer assignments that appear immediately
649 // before calls from potentially appearing dead. Uses for argument
650 // registers are added manually.
651 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
652 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
653 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
654 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
656 def CALLpcrel32 : Ii32<0xE8, RawFrm,
657 (outs), (ins i32imm_pcrel:$dst,variable_ops),
659 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
660 "call\t{*}$dst", [(X86call GR32:$dst)]>;
661 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
662 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
667 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
668 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops),
669 "#TC_RETURN $dst $offset",
672 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
673 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops),
674 "#TC_RETURN $dst $offset",
677 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
679 def TAILJMPd : IBr<0xE9, (ins i32imm_pcrel:$dst), "jmp\t$dst # TAILCALL",
681 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
682 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
684 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
685 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
686 "jmp\t{*}$dst # TAILCALL", []>;
688 //===----------------------------------------------------------------------===//
689 // Miscellaneous Instructions...
691 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
692 def LEAVE : I<0xC9, RawFrm,
693 (outs), (ins), "leave", []>;
695 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
697 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
700 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
703 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
704 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
705 "push{l}\t$imm", []>;
706 def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
707 "push{l}\t$imm", []>;
708 def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
709 "push{l}\t$imm", []>;
712 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
713 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
714 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
715 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
717 let isTwoAddress = 1 in // GR32 = bswap GR32
718 def BSWAP32r : I<0xC8, AddRegFrm,
719 (outs GR32:$dst), (ins GR32:$src),
721 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
724 // Bit scan instructions.
725 let Defs = [EFLAGS] in {
726 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
727 "bsf{w}\t{$src, $dst|$dst, $src}",
728 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
729 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
730 "bsf{w}\t{$src, $dst|$dst, $src}",
731 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
732 (implicit EFLAGS)]>, TB;
733 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
734 "bsf{l}\t{$src, $dst|$dst, $src}",
735 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
736 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
737 "bsf{l}\t{$src, $dst|$dst, $src}",
738 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
739 (implicit EFLAGS)]>, TB;
741 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
742 "bsr{w}\t{$src, $dst|$dst, $src}",
743 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
744 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
745 "bsr{w}\t{$src, $dst|$dst, $src}",
746 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
747 (implicit EFLAGS)]>, TB;
748 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
749 "bsr{l}\t{$src, $dst|$dst, $src}",
750 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
751 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
752 "bsr{l}\t{$src, $dst|$dst, $src}",
753 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
754 (implicit EFLAGS)]>, TB;
757 let neverHasSideEffects = 1 in
758 def LEA16r : I<0x8D, MRMSrcMem,
759 (outs GR16:$dst), (ins i32mem:$src),
760 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
761 let isReMaterializable = 1 in
762 def LEA32r : I<0x8D, MRMSrcMem,
763 (outs GR32:$dst), (ins lea32mem:$src),
764 "lea{l}\t{$src|$dst}, {$dst|$src}",
765 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
767 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
768 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
769 [(X86rep_movs i8)]>, REP;
770 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
771 [(X86rep_movs i16)]>, REP, OpSize;
772 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
773 [(X86rep_movs i32)]>, REP;
776 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
777 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
778 [(X86rep_stos i8)]>, REP;
779 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
780 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
781 [(X86rep_stos i16)]>, REP, OpSize;
782 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
783 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
784 [(X86rep_stos i32)]>, REP;
786 let Defs = [RAX, RDX] in
787 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
790 let isBarrier = 1, hasCtrlDep = 1 in {
791 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
794 def SYSCALL : I<0x05, RawFrm,
795 (outs), (ins), "syscall", []>, TB;
796 def SYSRET : I<0x07, RawFrm,
797 (outs), (ins), "sysret", []>, TB;
798 def SYSENTER : I<0x34, RawFrm,
799 (outs), (ins), "sysenter", []>, TB;
800 def SYSEXIT : I<0x35, RawFrm,
801 (outs), (ins), "sysexit", []>, TB;
805 //===----------------------------------------------------------------------===//
806 // Input/Output Instructions...
808 let Defs = [AL], Uses = [DX] in
809 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
810 "in{b}\t{%dx, %al|%AL, %DX}", []>;
811 let Defs = [AX], Uses = [DX] in
812 def IN16rr : I<0xED, RawFrm, (outs), (ins),
813 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
814 let Defs = [EAX], Uses = [DX] in
815 def IN32rr : I<0xED, RawFrm, (outs), (ins),
816 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
819 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
820 "in{b}\t{$port, %al|%AL, $port}", []>;
822 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
823 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
825 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
826 "in{l}\t{$port, %eax|%EAX, $port}", []>;
828 let Uses = [DX, AL] in
829 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
830 "out{b}\t{%al, %dx|%DX, %AL}", []>;
831 let Uses = [DX, AX] in
832 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
833 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
834 let Uses = [DX, EAX] in
835 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
836 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
839 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
840 "out{b}\t{%al, $port|$port, %AL}", []>;
842 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
843 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
845 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
846 "out{l}\t{%eax, $port|$port, %EAX}", []>;
848 //===----------------------------------------------------------------------===//
849 // Move Instructions...
851 let neverHasSideEffects = 1 in {
852 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
853 "mov{b}\t{$src, $dst|$dst, $src}", []>;
854 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
855 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
856 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
857 "mov{l}\t{$src, $dst|$dst, $src}", []>;
859 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
860 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
861 "mov{b}\t{$src, $dst|$dst, $src}",
862 [(set GR8:$dst, imm:$src)]>;
863 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
864 "mov{w}\t{$src, $dst|$dst, $src}",
865 [(set GR16:$dst, imm:$src)]>, OpSize;
866 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
867 "mov{l}\t{$src, $dst|$dst, $src}",
868 [(set GR32:$dst, imm:$src)]>;
870 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
871 "mov{b}\t{$src, $dst|$dst, $src}",
872 [(store (i8 imm:$src), addr:$dst)]>;
873 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
874 "mov{w}\t{$src, $dst|$dst, $src}",
875 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
876 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
877 "mov{l}\t{$src, $dst|$dst, $src}",
878 [(store (i32 imm:$src), addr:$dst)]>;
880 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
881 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
882 "mov{b}\t{$src, $dst|$dst, $src}",
883 [(set GR8:$dst, (loadi8 addr:$src))]>;
884 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
885 "mov{w}\t{$src, $dst|$dst, $src}",
886 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
887 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
888 "mov{l}\t{$src, $dst|$dst, $src}",
889 [(set GR32:$dst, (loadi32 addr:$src))]>;
892 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
893 "mov{b}\t{$src, $dst|$dst, $src}",
894 [(store GR8:$src, addr:$dst)]>;
895 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
896 "mov{w}\t{$src, $dst|$dst, $src}",
897 [(store GR16:$src, addr:$dst)]>, OpSize;
898 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
899 "mov{l}\t{$src, $dst|$dst, $src}",
900 [(store GR32:$src, addr:$dst)]>;
902 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
903 // that they can be used for copying and storing h registers, which can't be
904 // encoded when a REX prefix is present.
905 let neverHasSideEffects = 1 in
906 def MOV8rr_NOREX : I<0x88, MRMDestReg,
907 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
908 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
910 def MOV8mr_NOREX : I<0x88, MRMDestMem,
911 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
912 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
914 canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
915 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
916 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
917 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
919 //===----------------------------------------------------------------------===//
920 // Fixed-Register Multiplication and Division Instructions...
923 // Extra precision multiplication
924 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
925 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
926 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
927 // This probably ought to be moved to a def : Pat<> if the
928 // syntax can be accepted.
929 [(set AL, (mul AL, GR8:$src)),
930 (implicit EFLAGS)]>; // AL,AH = AL*GR8
932 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
933 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
935 []>, OpSize; // AX,DX = AX*GR16
937 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
938 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
940 []>; // EAX,EDX = EAX*GR32
942 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
943 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
945 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
946 // This probably ought to be moved to a def : Pat<> if the
947 // syntax can be accepted.
948 [(set AL, (mul AL, (loadi8 addr:$src))),
949 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
951 let mayLoad = 1, neverHasSideEffects = 1 in {
952 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
953 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
955 []>, OpSize; // AX,DX = AX*[mem16]
957 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
958 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
960 []>; // EAX,EDX = EAX*[mem32]
963 let neverHasSideEffects = 1 in {
964 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
965 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
967 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
968 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
969 OpSize; // AX,DX = AX*GR16
970 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
971 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
972 // EAX,EDX = EAX*GR32
974 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
975 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
976 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
977 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
978 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
979 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
980 let Defs = [EAX,EDX], Uses = [EAX] in
981 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
982 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
984 } // neverHasSideEffects
986 // unsigned division/remainder
987 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
988 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
990 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
991 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
992 "div{w}\t$src", []>, OpSize;
993 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
994 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
997 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
998 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1000 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1001 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1002 "div{w}\t$src", []>, OpSize;
1003 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1004 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
1005 "div{l}\t$src", []>;
1008 // Signed division/remainder.
1009 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1010 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1011 "idiv{b}\t$src", []>;
1012 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1013 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1014 "idiv{w}\t$src", []>, OpSize;
1015 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1016 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1017 "idiv{l}\t$src", []>;
1018 let mayLoad = 1, mayLoad = 1 in {
1019 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1020 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1021 "idiv{b}\t$src", []>;
1022 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1023 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1024 "idiv{w}\t$src", []>, OpSize;
1025 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1026 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
1027 "idiv{l}\t$src", []>;
1030 //===----------------------------------------------------------------------===//
1031 // Two address Instructions.
1033 let isTwoAddress = 1 in {
1035 // Conditional moves
1036 let Uses = [EFLAGS] in {
1038 // X86 doesn't have 8-bit conditional moves. Use a customDAGSchedInserter to
1039 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1040 // however that requires promoting the operands, and can induce additional
1041 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1042 // clobber EFLAGS, because if one of the operands is zero, the expansion
1043 // could involve an xor.
1044 let usesCustomDAGSchedInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in
1045 def CMOV_GR8 : I<0, Pseudo,
1046 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1047 "#CMOV_GR8 PSEUDO!",
1048 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1049 imm:$cond, EFLAGS))]>;
1051 let isCommutable = 1 in {
1052 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1053 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1054 "cmovb\t{$src2, $dst|$dst, $src2}",
1055 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1056 X86_COND_B, EFLAGS))]>,
1058 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1059 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1060 "cmovb\t{$src2, $dst|$dst, $src2}",
1061 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1062 X86_COND_B, EFLAGS))]>,
1064 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1065 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1066 "cmovae\t{$src2, $dst|$dst, $src2}",
1067 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1068 X86_COND_AE, EFLAGS))]>,
1070 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1071 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1072 "cmovae\t{$src2, $dst|$dst, $src2}",
1073 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1074 X86_COND_AE, EFLAGS))]>,
1076 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1077 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1078 "cmove\t{$src2, $dst|$dst, $src2}",
1079 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1080 X86_COND_E, EFLAGS))]>,
1082 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1083 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1084 "cmove\t{$src2, $dst|$dst, $src2}",
1085 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1086 X86_COND_E, EFLAGS))]>,
1088 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1089 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1090 "cmovne\t{$src2, $dst|$dst, $src2}",
1091 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1092 X86_COND_NE, EFLAGS))]>,
1094 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1095 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1096 "cmovne\t{$src2, $dst|$dst, $src2}",
1097 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1098 X86_COND_NE, EFLAGS))]>,
1100 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1101 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1102 "cmovbe\t{$src2, $dst|$dst, $src2}",
1103 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1104 X86_COND_BE, EFLAGS))]>,
1106 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1107 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1108 "cmovbe\t{$src2, $dst|$dst, $src2}",
1109 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1110 X86_COND_BE, EFLAGS))]>,
1112 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1113 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1114 "cmova\t{$src2, $dst|$dst, $src2}",
1115 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1116 X86_COND_A, EFLAGS))]>,
1118 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1119 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1120 "cmova\t{$src2, $dst|$dst, $src2}",
1121 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1122 X86_COND_A, EFLAGS))]>,
1124 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1125 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1126 "cmovl\t{$src2, $dst|$dst, $src2}",
1127 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1128 X86_COND_L, EFLAGS))]>,
1130 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1131 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1132 "cmovl\t{$src2, $dst|$dst, $src2}",
1133 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1134 X86_COND_L, EFLAGS))]>,
1136 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1137 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1138 "cmovge\t{$src2, $dst|$dst, $src2}",
1139 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1140 X86_COND_GE, EFLAGS))]>,
1142 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1143 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1144 "cmovge\t{$src2, $dst|$dst, $src2}",
1145 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1146 X86_COND_GE, EFLAGS))]>,
1148 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1149 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1150 "cmovle\t{$src2, $dst|$dst, $src2}",
1151 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1152 X86_COND_LE, EFLAGS))]>,
1154 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1155 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1156 "cmovle\t{$src2, $dst|$dst, $src2}",
1157 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1158 X86_COND_LE, EFLAGS))]>,
1160 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1161 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1162 "cmovg\t{$src2, $dst|$dst, $src2}",
1163 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1164 X86_COND_G, EFLAGS))]>,
1166 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1167 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1168 "cmovg\t{$src2, $dst|$dst, $src2}",
1169 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1170 X86_COND_G, EFLAGS))]>,
1172 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1173 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1174 "cmovs\t{$src2, $dst|$dst, $src2}",
1175 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1176 X86_COND_S, EFLAGS))]>,
1178 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1179 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1180 "cmovs\t{$src2, $dst|$dst, $src2}",
1181 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1182 X86_COND_S, EFLAGS))]>,
1184 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1185 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1186 "cmovns\t{$src2, $dst|$dst, $src2}",
1187 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1188 X86_COND_NS, EFLAGS))]>,
1190 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1191 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1192 "cmovns\t{$src2, $dst|$dst, $src2}",
1193 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1194 X86_COND_NS, EFLAGS))]>,
1196 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1197 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1198 "cmovp\t{$src2, $dst|$dst, $src2}",
1199 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1200 X86_COND_P, EFLAGS))]>,
1202 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1203 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1204 "cmovp\t{$src2, $dst|$dst, $src2}",
1205 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1206 X86_COND_P, EFLAGS))]>,
1208 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1209 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1210 "cmovnp\t{$src2, $dst|$dst, $src2}",
1211 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1212 X86_COND_NP, EFLAGS))]>,
1214 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1215 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1216 "cmovnp\t{$src2, $dst|$dst, $src2}",
1217 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1218 X86_COND_NP, EFLAGS))]>,
1220 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1221 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1222 "cmovo\t{$src2, $dst|$dst, $src2}",
1223 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1224 X86_COND_O, EFLAGS))]>,
1226 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1227 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1228 "cmovo\t{$src2, $dst|$dst, $src2}",
1229 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1230 X86_COND_O, EFLAGS))]>,
1232 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1233 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1234 "cmovno\t{$src2, $dst|$dst, $src2}",
1235 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1236 X86_COND_NO, EFLAGS))]>,
1238 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1239 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1240 "cmovno\t{$src2, $dst|$dst, $src2}",
1241 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1242 X86_COND_NO, EFLAGS))]>,
1244 } // isCommutable = 1
1246 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1247 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1248 "cmovb\t{$src2, $dst|$dst, $src2}",
1249 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1250 X86_COND_B, EFLAGS))]>,
1252 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1253 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1254 "cmovb\t{$src2, $dst|$dst, $src2}",
1255 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1256 X86_COND_B, EFLAGS))]>,
1258 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1259 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1260 "cmovae\t{$src2, $dst|$dst, $src2}",
1261 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1262 X86_COND_AE, EFLAGS))]>,
1264 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1265 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1266 "cmovae\t{$src2, $dst|$dst, $src2}",
1267 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1268 X86_COND_AE, EFLAGS))]>,
1270 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1271 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1272 "cmove\t{$src2, $dst|$dst, $src2}",
1273 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1274 X86_COND_E, EFLAGS))]>,
1276 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1277 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1278 "cmove\t{$src2, $dst|$dst, $src2}",
1279 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1280 X86_COND_E, EFLAGS))]>,
1282 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1283 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1284 "cmovne\t{$src2, $dst|$dst, $src2}",
1285 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1286 X86_COND_NE, EFLAGS))]>,
1288 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1289 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1290 "cmovne\t{$src2, $dst|$dst, $src2}",
1291 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1292 X86_COND_NE, EFLAGS))]>,
1294 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1295 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1296 "cmovbe\t{$src2, $dst|$dst, $src2}",
1297 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1298 X86_COND_BE, EFLAGS))]>,
1300 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1301 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1302 "cmovbe\t{$src2, $dst|$dst, $src2}",
1303 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1304 X86_COND_BE, EFLAGS))]>,
1306 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1307 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1308 "cmova\t{$src2, $dst|$dst, $src2}",
1309 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1310 X86_COND_A, EFLAGS))]>,
1312 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1313 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1314 "cmova\t{$src2, $dst|$dst, $src2}",
1315 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1316 X86_COND_A, EFLAGS))]>,
1318 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1319 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1320 "cmovl\t{$src2, $dst|$dst, $src2}",
1321 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1322 X86_COND_L, EFLAGS))]>,
1324 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1325 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1326 "cmovl\t{$src2, $dst|$dst, $src2}",
1327 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1328 X86_COND_L, EFLAGS))]>,
1330 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1331 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1332 "cmovge\t{$src2, $dst|$dst, $src2}",
1333 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1334 X86_COND_GE, EFLAGS))]>,
1336 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1337 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1338 "cmovge\t{$src2, $dst|$dst, $src2}",
1339 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1340 X86_COND_GE, EFLAGS))]>,
1342 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1343 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1344 "cmovle\t{$src2, $dst|$dst, $src2}",
1345 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1346 X86_COND_LE, EFLAGS))]>,
1348 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1349 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1350 "cmovle\t{$src2, $dst|$dst, $src2}",
1351 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1352 X86_COND_LE, EFLAGS))]>,
1354 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1355 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1356 "cmovg\t{$src2, $dst|$dst, $src2}",
1357 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1358 X86_COND_G, EFLAGS))]>,
1360 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1361 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1362 "cmovg\t{$src2, $dst|$dst, $src2}",
1363 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1364 X86_COND_G, EFLAGS))]>,
1366 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1367 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1368 "cmovs\t{$src2, $dst|$dst, $src2}",
1369 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1370 X86_COND_S, EFLAGS))]>,
1372 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1373 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1374 "cmovs\t{$src2, $dst|$dst, $src2}",
1375 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1376 X86_COND_S, EFLAGS))]>,
1378 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1379 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1380 "cmovns\t{$src2, $dst|$dst, $src2}",
1381 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1382 X86_COND_NS, EFLAGS))]>,
1384 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1385 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1386 "cmovns\t{$src2, $dst|$dst, $src2}",
1387 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1388 X86_COND_NS, EFLAGS))]>,
1390 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1391 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1392 "cmovp\t{$src2, $dst|$dst, $src2}",
1393 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1394 X86_COND_P, EFLAGS))]>,
1396 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1397 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1398 "cmovp\t{$src2, $dst|$dst, $src2}",
1399 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1400 X86_COND_P, EFLAGS))]>,
1402 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1403 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1404 "cmovnp\t{$src2, $dst|$dst, $src2}",
1405 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1406 X86_COND_NP, EFLAGS))]>,
1408 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1409 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1410 "cmovnp\t{$src2, $dst|$dst, $src2}",
1411 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1412 X86_COND_NP, EFLAGS))]>,
1414 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1415 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1416 "cmovo\t{$src2, $dst|$dst, $src2}",
1417 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1418 X86_COND_O, EFLAGS))]>,
1420 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1421 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1422 "cmovo\t{$src2, $dst|$dst, $src2}",
1423 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1424 X86_COND_O, EFLAGS))]>,
1426 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1427 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1428 "cmovno\t{$src2, $dst|$dst, $src2}",
1429 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1430 X86_COND_NO, EFLAGS))]>,
1432 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1433 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1434 "cmovno\t{$src2, $dst|$dst, $src2}",
1435 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1436 X86_COND_NO, EFLAGS))]>,
1438 } // Uses = [EFLAGS]
1441 // unary instructions
1442 let CodeSize = 2 in {
1443 let Defs = [EFLAGS] in {
1444 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1445 [(set GR8:$dst, (ineg GR8:$src)),
1446 (implicit EFLAGS)]>;
1447 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1448 [(set GR16:$dst, (ineg GR16:$src)),
1449 (implicit EFLAGS)]>, OpSize;
1450 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1451 [(set GR32:$dst, (ineg GR32:$src)),
1452 (implicit EFLAGS)]>;
1453 let isTwoAddress = 0 in {
1454 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1455 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1456 (implicit EFLAGS)]>;
1457 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1458 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1459 (implicit EFLAGS)]>, OpSize;
1460 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1461 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1462 (implicit EFLAGS)]>;
1464 } // Defs = [EFLAGS]
1466 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1467 let AddedComplexity = 15 in {
1468 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1469 [(set GR8:$dst, (not GR8:$src))]>;
1470 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1471 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1472 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1473 [(set GR32:$dst, (not GR32:$src))]>;
1475 let isTwoAddress = 0 in {
1476 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1477 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1478 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1479 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1480 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1481 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1485 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1486 let Defs = [EFLAGS] in {
1488 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1489 [(set GR8:$dst, (add GR8:$src, 1)),
1490 (implicit EFLAGS)]>;
1491 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1492 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1493 [(set GR16:$dst, (add GR16:$src, 1)),
1494 (implicit EFLAGS)]>,
1495 OpSize, Requires<[In32BitMode]>;
1496 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1497 [(set GR32:$dst, (add GR32:$src, 1)),
1498 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1500 let isTwoAddress = 0, CodeSize = 2 in {
1501 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1502 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1503 (implicit EFLAGS)]>;
1504 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1505 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1506 (implicit EFLAGS)]>,
1507 OpSize, Requires<[In32BitMode]>;
1508 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1509 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1510 (implicit EFLAGS)]>,
1511 Requires<[In32BitMode]>;
1515 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1516 [(set GR8:$dst, (add GR8:$src, -1)),
1517 (implicit EFLAGS)]>;
1518 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1519 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1520 [(set GR16:$dst, (add GR16:$src, -1)),
1521 (implicit EFLAGS)]>,
1522 OpSize, Requires<[In32BitMode]>;
1523 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1524 [(set GR32:$dst, (add GR32:$src, -1)),
1525 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1528 let isTwoAddress = 0, CodeSize = 2 in {
1529 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1530 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1531 (implicit EFLAGS)]>;
1532 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1533 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1534 (implicit EFLAGS)]>,
1535 OpSize, Requires<[In32BitMode]>;
1536 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1537 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1538 (implicit EFLAGS)]>,
1539 Requires<[In32BitMode]>;
1541 } // Defs = [EFLAGS]
1543 // Logical operators...
1544 let Defs = [EFLAGS] in {
1545 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1546 def AND8rr : I<0x20, MRMDestReg,
1547 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1548 "and{b}\t{$src2, $dst|$dst, $src2}",
1549 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
1550 (implicit EFLAGS)]>;
1551 def AND16rr : I<0x21, MRMDestReg,
1552 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1553 "and{w}\t{$src2, $dst|$dst, $src2}",
1554 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
1555 (implicit EFLAGS)]>, OpSize;
1556 def AND32rr : I<0x21, MRMDestReg,
1557 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1558 "and{l}\t{$src2, $dst|$dst, $src2}",
1559 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
1560 (implicit EFLAGS)]>;
1563 def AND8rm : I<0x22, MRMSrcMem,
1564 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1565 "and{b}\t{$src2, $dst|$dst, $src2}",
1566 [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
1567 (implicit EFLAGS)]>;
1568 def AND16rm : I<0x23, MRMSrcMem,
1569 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1570 "and{w}\t{$src2, $dst|$dst, $src2}",
1571 [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
1572 (implicit EFLAGS)]>, OpSize;
1573 def AND32rm : I<0x23, MRMSrcMem,
1574 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1575 "and{l}\t{$src2, $dst|$dst, $src2}",
1576 [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
1577 (implicit EFLAGS)]>;
1579 def AND8ri : Ii8<0x80, MRM4r,
1580 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1581 "and{b}\t{$src2, $dst|$dst, $src2}",
1582 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
1583 (implicit EFLAGS)]>;
1584 def AND16ri : Ii16<0x81, MRM4r,
1585 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1586 "and{w}\t{$src2, $dst|$dst, $src2}",
1587 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
1588 (implicit EFLAGS)]>, OpSize;
1589 def AND32ri : Ii32<0x81, MRM4r,
1590 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1591 "and{l}\t{$src2, $dst|$dst, $src2}",
1592 [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
1593 (implicit EFLAGS)]>;
1594 def AND16ri8 : Ii8<0x83, MRM4r,
1595 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1596 "and{w}\t{$src2, $dst|$dst, $src2}",
1597 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
1598 (implicit EFLAGS)]>,
1600 def AND32ri8 : Ii8<0x83, MRM4r,
1601 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1602 "and{l}\t{$src2, $dst|$dst, $src2}",
1603 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
1604 (implicit EFLAGS)]>;
1606 let isTwoAddress = 0 in {
1607 def AND8mr : I<0x20, MRMDestMem,
1608 (outs), (ins i8mem :$dst, GR8 :$src),
1609 "and{b}\t{$src, $dst|$dst, $src}",
1610 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1611 (implicit EFLAGS)]>;
1612 def AND16mr : I<0x21, MRMDestMem,
1613 (outs), (ins i16mem:$dst, GR16:$src),
1614 "and{w}\t{$src, $dst|$dst, $src}",
1615 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1616 (implicit EFLAGS)]>,
1618 def AND32mr : I<0x21, MRMDestMem,
1619 (outs), (ins i32mem:$dst, GR32:$src),
1620 "and{l}\t{$src, $dst|$dst, $src}",
1621 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1622 (implicit EFLAGS)]>;
1623 def AND8mi : Ii8<0x80, MRM4m,
1624 (outs), (ins i8mem :$dst, i8imm :$src),
1625 "and{b}\t{$src, $dst|$dst, $src}",
1626 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1627 (implicit EFLAGS)]>;
1628 def AND16mi : Ii16<0x81, MRM4m,
1629 (outs), (ins i16mem:$dst, i16imm:$src),
1630 "and{w}\t{$src, $dst|$dst, $src}",
1631 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1632 (implicit EFLAGS)]>,
1634 def AND32mi : Ii32<0x81, MRM4m,
1635 (outs), (ins i32mem:$dst, i32imm:$src),
1636 "and{l}\t{$src, $dst|$dst, $src}",
1637 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1638 (implicit EFLAGS)]>;
1639 def AND16mi8 : Ii8<0x83, MRM4m,
1640 (outs), (ins i16mem:$dst, i16i8imm :$src),
1641 "and{w}\t{$src, $dst|$dst, $src}",
1642 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1643 (implicit EFLAGS)]>,
1645 def AND32mi8 : Ii8<0x83, MRM4m,
1646 (outs), (ins i32mem:$dst, i32i8imm :$src),
1647 "and{l}\t{$src, $dst|$dst, $src}",
1648 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1649 (implicit EFLAGS)]>;
1653 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1654 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1655 "or{b}\t{$src2, $dst|$dst, $src2}",
1656 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
1657 (implicit EFLAGS)]>;
1658 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1659 "or{w}\t{$src2, $dst|$dst, $src2}",
1660 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
1661 (implicit EFLAGS)]>, OpSize;
1662 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1663 "or{l}\t{$src2, $dst|$dst, $src2}",
1664 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
1665 (implicit EFLAGS)]>;
1667 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1668 "or{b}\t{$src2, $dst|$dst, $src2}",
1669 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
1670 (implicit EFLAGS)]>;
1671 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1672 "or{w}\t{$src2, $dst|$dst, $src2}",
1673 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
1674 (implicit EFLAGS)]>, OpSize;
1675 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1676 "or{l}\t{$src2, $dst|$dst, $src2}",
1677 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
1678 (implicit EFLAGS)]>;
1680 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1681 "or{b}\t{$src2, $dst|$dst, $src2}",
1682 [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
1683 (implicit EFLAGS)]>;
1684 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1685 "or{w}\t{$src2, $dst|$dst, $src2}",
1686 [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
1687 (implicit EFLAGS)]>, OpSize;
1688 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1689 "or{l}\t{$src2, $dst|$dst, $src2}",
1690 [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
1691 (implicit EFLAGS)]>;
1693 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1694 "or{w}\t{$src2, $dst|$dst, $src2}",
1695 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
1696 (implicit EFLAGS)]>, OpSize;
1697 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1698 "or{l}\t{$src2, $dst|$dst, $src2}",
1699 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
1700 (implicit EFLAGS)]>;
1701 let isTwoAddress = 0 in {
1702 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1703 "or{b}\t{$src, $dst|$dst, $src}",
1704 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1705 (implicit EFLAGS)]>;
1706 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1707 "or{w}\t{$src, $dst|$dst, $src}",
1708 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1709 (implicit EFLAGS)]>, OpSize;
1710 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1711 "or{l}\t{$src, $dst|$dst, $src}",
1712 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1713 (implicit EFLAGS)]>;
1714 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1715 "or{b}\t{$src, $dst|$dst, $src}",
1716 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1717 (implicit EFLAGS)]>;
1718 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1719 "or{w}\t{$src, $dst|$dst, $src}",
1720 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1721 (implicit EFLAGS)]>,
1723 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1724 "or{l}\t{$src, $dst|$dst, $src}",
1725 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1726 (implicit EFLAGS)]>;
1727 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1728 "or{w}\t{$src, $dst|$dst, $src}",
1729 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1730 (implicit EFLAGS)]>,
1732 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1733 "or{l}\t{$src, $dst|$dst, $src}",
1734 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1735 (implicit EFLAGS)]>;
1736 } // isTwoAddress = 0
1739 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1740 def XOR8rr : I<0x30, MRMDestReg,
1741 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1742 "xor{b}\t{$src2, $dst|$dst, $src2}",
1743 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
1744 (implicit EFLAGS)]>;
1745 def XOR16rr : I<0x31, MRMDestReg,
1746 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1747 "xor{w}\t{$src2, $dst|$dst, $src2}",
1748 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
1749 (implicit EFLAGS)]>, OpSize;
1750 def XOR32rr : I<0x31, MRMDestReg,
1751 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1752 "xor{l}\t{$src2, $dst|$dst, $src2}",
1753 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
1754 (implicit EFLAGS)]>;
1755 } // isCommutable = 1
1757 def XOR8rm : I<0x32, MRMSrcMem ,
1758 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1759 "xor{b}\t{$src2, $dst|$dst, $src2}",
1760 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
1761 (implicit EFLAGS)]>;
1762 def XOR16rm : I<0x33, MRMSrcMem ,
1763 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1764 "xor{w}\t{$src2, $dst|$dst, $src2}",
1765 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
1766 (implicit EFLAGS)]>,
1768 def XOR32rm : I<0x33, MRMSrcMem ,
1769 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1770 "xor{l}\t{$src2, $dst|$dst, $src2}",
1771 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
1772 (implicit EFLAGS)]>;
1774 def XOR8ri : Ii8<0x80, MRM6r,
1775 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1776 "xor{b}\t{$src2, $dst|$dst, $src2}",
1777 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
1778 (implicit EFLAGS)]>;
1779 def XOR16ri : Ii16<0x81, MRM6r,
1780 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1781 "xor{w}\t{$src2, $dst|$dst, $src2}",
1782 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
1783 (implicit EFLAGS)]>, OpSize;
1784 def XOR32ri : Ii32<0x81, MRM6r,
1785 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1786 "xor{l}\t{$src2, $dst|$dst, $src2}",
1787 [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
1788 (implicit EFLAGS)]>;
1789 def XOR16ri8 : Ii8<0x83, MRM6r,
1790 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1791 "xor{w}\t{$src2, $dst|$dst, $src2}",
1792 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
1793 (implicit EFLAGS)]>,
1795 def XOR32ri8 : Ii8<0x83, MRM6r,
1796 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1797 "xor{l}\t{$src2, $dst|$dst, $src2}",
1798 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
1799 (implicit EFLAGS)]>;
1801 let isTwoAddress = 0 in {
1802 def XOR8mr : I<0x30, MRMDestMem,
1803 (outs), (ins i8mem :$dst, GR8 :$src),
1804 "xor{b}\t{$src, $dst|$dst, $src}",
1805 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
1806 (implicit EFLAGS)]>;
1807 def XOR16mr : I<0x31, MRMDestMem,
1808 (outs), (ins i16mem:$dst, GR16:$src),
1809 "xor{w}\t{$src, $dst|$dst, $src}",
1810 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
1811 (implicit EFLAGS)]>,
1813 def XOR32mr : I<0x31, MRMDestMem,
1814 (outs), (ins i32mem:$dst, GR32:$src),
1815 "xor{l}\t{$src, $dst|$dst, $src}",
1816 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
1817 (implicit EFLAGS)]>;
1818 def XOR8mi : Ii8<0x80, MRM6m,
1819 (outs), (ins i8mem :$dst, i8imm :$src),
1820 "xor{b}\t{$src, $dst|$dst, $src}",
1821 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
1822 (implicit EFLAGS)]>;
1823 def XOR16mi : Ii16<0x81, MRM6m,
1824 (outs), (ins i16mem:$dst, i16imm:$src),
1825 "xor{w}\t{$src, $dst|$dst, $src}",
1826 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
1827 (implicit EFLAGS)]>,
1829 def XOR32mi : Ii32<0x81, MRM6m,
1830 (outs), (ins i32mem:$dst, i32imm:$src),
1831 "xor{l}\t{$src, $dst|$dst, $src}",
1832 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
1833 (implicit EFLAGS)]>;
1834 def XOR16mi8 : Ii8<0x83, MRM6m,
1835 (outs), (ins i16mem:$dst, i16i8imm :$src),
1836 "xor{w}\t{$src, $dst|$dst, $src}",
1837 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
1838 (implicit EFLAGS)]>,
1840 def XOR32mi8 : Ii8<0x83, MRM6m,
1841 (outs), (ins i32mem:$dst, i32i8imm :$src),
1842 "xor{l}\t{$src, $dst|$dst, $src}",
1843 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
1844 (implicit EFLAGS)]>;
1845 } // isTwoAddress = 0
1846 } // Defs = [EFLAGS]
1848 // Shift instructions
1849 let Defs = [EFLAGS] in {
1850 let Uses = [CL] in {
1851 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1852 "shl{b}\t{%cl, $dst|$dst, CL}",
1853 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1854 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1855 "shl{w}\t{%cl, $dst|$dst, CL}",
1856 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1857 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1858 "shl{l}\t{%cl, $dst|$dst, CL}",
1859 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1862 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1863 "shl{b}\t{$src2, $dst|$dst, $src2}",
1864 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1865 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1866 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1867 "shl{w}\t{$src2, $dst|$dst, $src2}",
1868 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1869 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1870 "shl{l}\t{$src2, $dst|$dst, $src2}",
1871 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1872 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1874 } // isConvertibleToThreeAddress = 1
1876 let isTwoAddress = 0 in {
1877 let Uses = [CL] in {
1878 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1879 "shl{b}\t{%cl, $dst|$dst, CL}",
1880 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1881 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1882 "shl{w}\t{%cl, $dst|$dst, CL}",
1883 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1884 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1885 "shl{l}\t{%cl, $dst|$dst, CL}",
1886 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1888 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1889 "shl{b}\t{$src, $dst|$dst, $src}",
1890 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1891 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1892 "shl{w}\t{$src, $dst|$dst, $src}",
1893 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1895 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1896 "shl{l}\t{$src, $dst|$dst, $src}",
1897 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1900 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1902 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1903 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1905 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1907 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1909 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1912 let Uses = [CL] in {
1913 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1914 "shr{b}\t{%cl, $dst|$dst, CL}",
1915 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1916 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1917 "shr{w}\t{%cl, $dst|$dst, CL}",
1918 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1919 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1920 "shr{l}\t{%cl, $dst|$dst, CL}",
1921 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1924 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1925 "shr{b}\t{$src2, $dst|$dst, $src2}",
1926 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1927 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1928 "shr{w}\t{$src2, $dst|$dst, $src2}",
1929 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1930 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1931 "shr{l}\t{$src2, $dst|$dst, $src2}",
1932 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1935 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1937 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1938 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1940 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1941 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1943 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1945 let isTwoAddress = 0 in {
1946 let Uses = [CL] in {
1947 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1948 "shr{b}\t{%cl, $dst|$dst, CL}",
1949 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1950 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1951 "shr{w}\t{%cl, $dst|$dst, CL}",
1952 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1954 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1955 "shr{l}\t{%cl, $dst|$dst, CL}",
1956 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1958 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1959 "shr{b}\t{$src, $dst|$dst, $src}",
1960 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1961 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1962 "shr{w}\t{$src, $dst|$dst, $src}",
1963 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1965 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1966 "shr{l}\t{$src, $dst|$dst, $src}",
1967 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1970 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1972 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1973 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1975 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1976 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1978 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1981 let Uses = [CL] in {
1982 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1983 "sar{b}\t{%cl, $dst|$dst, CL}",
1984 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1985 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1986 "sar{w}\t{%cl, $dst|$dst, CL}",
1987 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1988 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1989 "sar{l}\t{%cl, $dst|$dst, CL}",
1990 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1993 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1994 "sar{b}\t{$src2, $dst|$dst, $src2}",
1995 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1996 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1997 "sar{w}\t{$src2, $dst|$dst, $src2}",
1998 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2000 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2001 "sar{l}\t{$src2, $dst|$dst, $src2}",
2002 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2005 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2007 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2008 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2010 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2011 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2013 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2015 let isTwoAddress = 0 in {
2016 let Uses = [CL] in {
2017 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2018 "sar{b}\t{%cl, $dst|$dst, CL}",
2019 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2020 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2021 "sar{w}\t{%cl, $dst|$dst, CL}",
2022 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2023 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2024 "sar{l}\t{%cl, $dst|$dst, CL}",
2025 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2027 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2028 "sar{b}\t{$src, $dst|$dst, $src}",
2029 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2030 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2031 "sar{w}\t{$src, $dst|$dst, $src}",
2032 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2034 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2035 "sar{l}\t{$src, $dst|$dst, $src}",
2036 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2039 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2041 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2042 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2044 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2046 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2048 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2051 // Rotate instructions
2052 // FIXME: provide shorter instructions when imm8 == 1
2053 let Uses = [CL] in {
2054 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
2055 "rol{b}\t{%cl, $dst|$dst, CL}",
2056 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
2057 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
2058 "rol{w}\t{%cl, $dst|$dst, CL}",
2059 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
2060 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
2061 "rol{l}\t{%cl, $dst|$dst, CL}",
2062 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2065 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2066 "rol{b}\t{$src2, $dst|$dst, $src2}",
2067 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2068 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2069 "rol{w}\t{$src2, $dst|$dst, $src2}",
2070 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2071 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2072 "rol{l}\t{$src2, $dst|$dst, $src2}",
2073 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2076 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2078 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2079 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2081 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2082 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2084 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2086 let isTwoAddress = 0 in {
2087 let Uses = [CL] in {
2088 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2089 "rol{b}\t{%cl, $dst|$dst, CL}",
2090 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2091 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2092 "rol{w}\t{%cl, $dst|$dst, CL}",
2093 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2094 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2095 "rol{l}\t{%cl, $dst|$dst, CL}",
2096 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2098 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2099 "rol{b}\t{$src, $dst|$dst, $src}",
2100 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2101 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2102 "rol{w}\t{$src, $dst|$dst, $src}",
2103 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2105 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2106 "rol{l}\t{$src, $dst|$dst, $src}",
2107 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2110 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2112 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2113 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2115 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2117 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2119 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2122 let Uses = [CL] in {
2123 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2124 "ror{b}\t{%cl, $dst|$dst, CL}",
2125 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2126 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2127 "ror{w}\t{%cl, $dst|$dst, CL}",
2128 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2129 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2130 "ror{l}\t{%cl, $dst|$dst, CL}",
2131 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2134 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2135 "ror{b}\t{$src2, $dst|$dst, $src2}",
2136 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2137 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2138 "ror{w}\t{$src2, $dst|$dst, $src2}",
2139 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2140 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2141 "ror{l}\t{$src2, $dst|$dst, $src2}",
2142 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2145 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2147 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2148 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2150 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2151 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2153 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2155 let isTwoAddress = 0 in {
2156 let Uses = [CL] in {
2157 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2158 "ror{b}\t{%cl, $dst|$dst, CL}",
2159 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2160 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2161 "ror{w}\t{%cl, $dst|$dst, CL}",
2162 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2163 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2164 "ror{l}\t{%cl, $dst|$dst, CL}",
2165 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2167 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2168 "ror{b}\t{$src, $dst|$dst, $src}",
2169 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2170 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2171 "ror{w}\t{$src, $dst|$dst, $src}",
2172 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2174 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2175 "ror{l}\t{$src, $dst|$dst, $src}",
2176 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2179 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2181 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2182 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2184 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2186 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2188 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2193 // Double shift instructions (generalizations of rotate)
2194 let Uses = [CL] in {
2195 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2196 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2197 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2198 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2199 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2200 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2201 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2202 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2203 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2205 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2206 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2207 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2211 let isCommutable = 1 in { // These instructions commute to each other.
2212 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2213 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2214 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2215 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2218 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2219 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2220 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2221 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2224 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2225 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2226 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2227 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2230 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2231 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2232 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2233 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2238 let isTwoAddress = 0 in {
2239 let Uses = [CL] in {
2240 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2241 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2242 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2244 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2245 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2246 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2249 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2250 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2251 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2252 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2253 (i8 imm:$src3)), addr:$dst)]>,
2255 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2256 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2257 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2258 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2259 (i8 imm:$src3)), addr:$dst)]>,
2262 let Uses = [CL] in {
2263 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2264 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2265 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2266 addr:$dst)]>, TB, OpSize;
2267 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2268 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2269 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2270 addr:$dst)]>, TB, OpSize;
2272 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2273 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2274 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2275 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2276 (i8 imm:$src3)), addr:$dst)]>,
2278 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2279 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2280 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2281 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2282 (i8 imm:$src3)), addr:$dst)]>,
2285 } // Defs = [EFLAGS]
2289 let Defs = [EFLAGS] in {
2290 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2291 // Register-Register Addition
2292 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2293 (ins GR8 :$src1, GR8 :$src2),
2294 "add{b}\t{$src2, $dst|$dst, $src2}",
2295 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
2296 (implicit EFLAGS)]>;
2298 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2299 // Register-Register Addition
2300 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2301 (ins GR16:$src1, GR16:$src2),
2302 "add{w}\t{$src2, $dst|$dst, $src2}",
2303 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2304 (implicit EFLAGS)]>, OpSize;
2305 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2306 (ins GR32:$src1, GR32:$src2),
2307 "add{l}\t{$src2, $dst|$dst, $src2}",
2308 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2309 (implicit EFLAGS)]>;
2310 } // end isConvertibleToThreeAddress
2311 } // end isCommutable
2313 // Register-Memory Addition
2314 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2315 (ins GR8 :$src1, i8mem :$src2),
2316 "add{b}\t{$src2, $dst|$dst, $src2}",
2317 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2318 (implicit EFLAGS)]>;
2319 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2320 (ins GR16:$src1, i16mem:$src2),
2321 "add{w}\t{$src2, $dst|$dst, $src2}",
2322 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2323 (implicit EFLAGS)]>, OpSize;
2324 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2325 (ins GR32:$src1, i32mem:$src2),
2326 "add{l}\t{$src2, $dst|$dst, $src2}",
2327 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2328 (implicit EFLAGS)]>;
2330 // Register-Integer Addition
2331 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2332 "add{b}\t{$src2, $dst|$dst, $src2}",
2333 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2334 (implicit EFLAGS)]>;
2336 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2337 // Register-Integer Addition
2338 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2339 (ins GR16:$src1, i16imm:$src2),
2340 "add{w}\t{$src2, $dst|$dst, $src2}",
2341 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2342 (implicit EFLAGS)]>, OpSize;
2343 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2344 (ins GR32:$src1, i32imm:$src2),
2345 "add{l}\t{$src2, $dst|$dst, $src2}",
2346 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2347 (implicit EFLAGS)]>;
2348 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2349 (ins GR16:$src1, i16i8imm:$src2),
2350 "add{w}\t{$src2, $dst|$dst, $src2}",
2351 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2352 (implicit EFLAGS)]>, OpSize;
2353 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2354 (ins GR32:$src1, i32i8imm:$src2),
2355 "add{l}\t{$src2, $dst|$dst, $src2}",
2356 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2357 (implicit EFLAGS)]>;
2360 let isTwoAddress = 0 in {
2361 // Memory-Register Addition
2362 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2363 "add{b}\t{$src2, $dst|$dst, $src2}",
2364 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2365 (implicit EFLAGS)]>;
2366 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2367 "add{w}\t{$src2, $dst|$dst, $src2}",
2368 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2369 (implicit EFLAGS)]>, OpSize;
2370 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2371 "add{l}\t{$src2, $dst|$dst, $src2}",
2372 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2373 (implicit EFLAGS)]>;
2374 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2375 "add{b}\t{$src2, $dst|$dst, $src2}",
2376 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2377 (implicit EFLAGS)]>;
2378 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2379 "add{w}\t{$src2, $dst|$dst, $src2}",
2380 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2381 (implicit EFLAGS)]>, OpSize;
2382 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2383 "add{l}\t{$src2, $dst|$dst, $src2}",
2384 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2385 (implicit EFLAGS)]>;
2386 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2387 "add{w}\t{$src2, $dst|$dst, $src2}",
2388 [(store (add (load addr:$dst), i16immSExt8:$src2),
2390 (implicit EFLAGS)]>, OpSize;
2391 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2392 "add{l}\t{$src2, $dst|$dst, $src2}",
2393 [(store (add (load addr:$dst), i32immSExt8:$src2),
2395 (implicit EFLAGS)]>;
2398 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2399 "add\t{$src, %al|%al, $src}", []>;
2400 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2401 "add\t{$src, %ax|%ax, $src}", []>, OpSize;
2402 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2403 "add\t{$src, %eax|%eax, $src}", []>;
2406 let Uses = [EFLAGS] in {
2407 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2408 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2409 "adc{b}\t{$src2, $dst|$dst, $src2}",
2410 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2411 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2412 (ins GR16:$src1, GR16:$src2),
2413 "adc{w}\t{$src2, $dst|$dst, $src2}",
2414 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2415 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2416 (ins GR32:$src1, GR32:$src2),
2417 "adc{l}\t{$src2, $dst|$dst, $src2}",
2418 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2420 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2421 (ins GR8:$src1, i8mem:$src2),
2422 "adc{b}\t{$src2, $dst|$dst, $src2}",
2423 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2424 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2425 (ins GR16:$src1, i16mem:$src2),
2426 "adc{w}\t{$src2, $dst|$dst, $src2}",
2427 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2429 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2430 (ins GR32:$src1, i32mem:$src2),
2431 "adc{l}\t{$src2, $dst|$dst, $src2}",
2432 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2433 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2434 "adc{b}\t{$src2, $dst|$dst, $src2}",
2435 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2436 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2437 (ins GR16:$src1, i16imm:$src2),
2438 "adc{w}\t{$src2, $dst|$dst, $src2}",
2439 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2440 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2441 (ins GR16:$src1, i16i8imm:$src2),
2442 "adc{w}\t{$src2, $dst|$dst, $src2}",
2443 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2445 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2446 (ins GR32:$src1, i32imm:$src2),
2447 "adc{l}\t{$src2, $dst|$dst, $src2}",
2448 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2449 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2450 (ins GR32:$src1, i32i8imm:$src2),
2451 "adc{l}\t{$src2, $dst|$dst, $src2}",
2452 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2454 let isTwoAddress = 0 in {
2455 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2456 "adc{b}\t{$src2, $dst|$dst, $src2}",
2457 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2458 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2459 "adc{w}\t{$src2, $dst|$dst, $src2}",
2460 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2462 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2463 "adc{l}\t{$src2, $dst|$dst, $src2}",
2464 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2465 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2466 "adc{b}\t{$src2, $dst|$dst, $src2}",
2467 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2468 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2469 "adc{w}\t{$src2, $dst|$dst, $src2}",
2470 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2472 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2473 "adc{w}\t{$src2, $dst|$dst, $src2}",
2474 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2476 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2477 "adc{l}\t{$src2, $dst|$dst, $src2}",
2478 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2479 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2480 "adc{l}\t{$src2, $dst|$dst, $src2}",
2481 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2483 } // Uses = [EFLAGS]
2485 // Register-Register Subtraction
2486 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2487 "sub{b}\t{$src2, $dst|$dst, $src2}",
2488 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2489 (implicit EFLAGS)]>;
2490 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2491 "sub{w}\t{$src2, $dst|$dst, $src2}",
2492 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2493 (implicit EFLAGS)]>, OpSize;
2494 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2495 "sub{l}\t{$src2, $dst|$dst, $src2}",
2496 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2497 (implicit EFLAGS)]>;
2499 // Register-Memory Subtraction
2500 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2501 (ins GR8 :$src1, i8mem :$src2),
2502 "sub{b}\t{$src2, $dst|$dst, $src2}",
2503 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2504 (implicit EFLAGS)]>;
2505 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2506 (ins GR16:$src1, i16mem:$src2),
2507 "sub{w}\t{$src2, $dst|$dst, $src2}",
2508 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2509 (implicit EFLAGS)]>, OpSize;
2510 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2511 (ins GR32:$src1, i32mem:$src2),
2512 "sub{l}\t{$src2, $dst|$dst, $src2}",
2513 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2514 (implicit EFLAGS)]>;
2516 // Register-Integer Subtraction
2517 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2518 (ins GR8:$src1, i8imm:$src2),
2519 "sub{b}\t{$src2, $dst|$dst, $src2}",
2520 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2521 (implicit EFLAGS)]>;
2522 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2523 (ins GR16:$src1, i16imm:$src2),
2524 "sub{w}\t{$src2, $dst|$dst, $src2}",
2525 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2526 (implicit EFLAGS)]>, OpSize;
2527 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2528 (ins GR32:$src1, i32imm:$src2),
2529 "sub{l}\t{$src2, $dst|$dst, $src2}",
2530 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2531 (implicit EFLAGS)]>;
2532 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2533 (ins GR16:$src1, i16i8imm:$src2),
2534 "sub{w}\t{$src2, $dst|$dst, $src2}",
2535 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2536 (implicit EFLAGS)]>, OpSize;
2537 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2538 (ins GR32:$src1, i32i8imm:$src2),
2539 "sub{l}\t{$src2, $dst|$dst, $src2}",
2540 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2541 (implicit EFLAGS)]>;
2543 let isTwoAddress = 0 in {
2544 // Memory-Register Subtraction
2545 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2546 "sub{b}\t{$src2, $dst|$dst, $src2}",
2547 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2548 (implicit EFLAGS)]>;
2549 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2550 "sub{w}\t{$src2, $dst|$dst, $src2}",
2551 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2552 (implicit EFLAGS)]>, OpSize;
2553 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2554 "sub{l}\t{$src2, $dst|$dst, $src2}",
2555 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2556 (implicit EFLAGS)]>;
2558 // Memory-Integer Subtraction
2559 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2560 "sub{b}\t{$src2, $dst|$dst, $src2}",
2561 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2562 (implicit EFLAGS)]>;
2563 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2564 "sub{w}\t{$src2, $dst|$dst, $src2}",
2565 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2566 (implicit EFLAGS)]>, OpSize;
2567 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2568 "sub{l}\t{$src2, $dst|$dst, $src2}",
2569 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2570 (implicit EFLAGS)]>;
2571 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2572 "sub{w}\t{$src2, $dst|$dst, $src2}",
2573 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2575 (implicit EFLAGS)]>, OpSize;
2576 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2577 "sub{l}\t{$src2, $dst|$dst, $src2}",
2578 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2580 (implicit EFLAGS)]>;
2583 let Uses = [EFLAGS] in {
2584 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
2585 (ins GR8:$src1, GR8:$src2),
2586 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2587 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
2588 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
2589 (ins GR16:$src1, GR16:$src2),
2590 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2591 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
2592 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
2593 (ins GR32:$src1, GR32:$src2),
2594 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2595 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2597 let isTwoAddress = 0 in {
2598 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2599 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2600 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
2601 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2602 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2603 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
2605 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2606 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2607 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2608 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2609 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2610 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2611 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
2612 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2613 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2615 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2616 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2617 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2619 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2620 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2621 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2622 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2623 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2624 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2626 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
2627 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2628 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
2629 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
2630 (ins GR16:$src1, i16mem:$src2),
2631 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2632 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
2634 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
2635 (ins GR32:$src1, i32mem:$src2),
2636 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2637 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2638 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2639 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2640 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
2641 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
2642 (ins GR16:$src1, i16imm:$src2),
2643 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2644 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
2645 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
2646 (ins GR16:$src1, i16i8imm:$src2),
2647 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2648 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
2650 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
2651 (ins GR32:$src1, i32imm:$src2),
2652 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2653 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2654 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
2655 (ins GR32:$src1, i32i8imm:$src2),
2656 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2657 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2658 } // Uses = [EFLAGS]
2659 } // Defs = [EFLAGS]
2661 let Defs = [EFLAGS] in {
2662 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2663 // Register-Register Signed Integer Multiply
2664 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2665 "imul{w}\t{$src2, $dst|$dst, $src2}",
2666 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
2667 (implicit EFLAGS)]>, TB, OpSize;
2668 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2669 "imul{l}\t{$src2, $dst|$dst, $src2}",
2670 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
2671 (implicit EFLAGS)]>, TB;
2674 // Register-Memory Signed Integer Multiply
2675 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
2676 (ins GR16:$src1, i16mem:$src2),
2677 "imul{w}\t{$src2, $dst|$dst, $src2}",
2678 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
2679 (implicit EFLAGS)]>, TB, OpSize;
2680 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2681 "imul{l}\t{$src2, $dst|$dst, $src2}",
2682 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
2683 (implicit EFLAGS)]>, TB;
2684 } // Defs = [EFLAGS]
2685 } // end Two Address instructions
2687 // Suprisingly enough, these are not two address instructions!
2688 let Defs = [EFLAGS] in {
2689 // Register-Integer Signed Integer Multiply
2690 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2691 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2692 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2693 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
2694 (implicit EFLAGS)]>, OpSize;
2695 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2696 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2697 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2698 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
2699 (implicit EFLAGS)]>;
2700 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2701 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2702 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2703 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
2704 (implicit EFLAGS)]>, OpSize;
2705 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2706 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2707 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2708 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
2709 (implicit EFLAGS)]>;
2711 // Memory-Integer Signed Integer Multiply
2712 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2713 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2714 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2715 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
2716 (implicit EFLAGS)]>, OpSize;
2717 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2718 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2719 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2720 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
2721 (implicit EFLAGS)]>;
2722 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2723 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2724 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2725 [(set GR16:$dst, (mul (load addr:$src1),
2726 i16immSExt8:$src2)),
2727 (implicit EFLAGS)]>, OpSize;
2728 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2729 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2730 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2731 [(set GR32:$dst, (mul (load addr:$src1),
2732 i32immSExt8:$src2)),
2733 (implicit EFLAGS)]>;
2734 } // Defs = [EFLAGS]
2736 //===----------------------------------------------------------------------===//
2737 // Test instructions are just like AND, except they don't generate a result.
2739 let Defs = [EFLAGS] in {
2740 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2741 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2742 "test{b}\t{$src2, $src1|$src1, $src2}",
2743 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
2744 (implicit EFLAGS)]>;
2745 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2746 "test{w}\t{$src2, $src1|$src1, $src2}",
2747 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
2748 (implicit EFLAGS)]>,
2750 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2751 "test{l}\t{$src2, $src1|$src1, $src2}",
2752 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
2753 (implicit EFLAGS)]>;
2756 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
2757 "test{b}\t{$src, %al|%al, $src}", []>;
2758 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
2759 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2760 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
2761 "test{l}\t{$src, %eax|%eax, $src}", []>;
2763 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2764 "test{b}\t{$src2, $src1|$src1, $src2}",
2765 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2766 (implicit EFLAGS)]>;
2767 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2768 "test{w}\t{$src2, $src1|$src1, $src2}",
2769 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2770 (implicit EFLAGS)]>, OpSize;
2771 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2772 "test{l}\t{$src2, $src1|$src1, $src2}",
2773 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2774 (implicit EFLAGS)]>;
2776 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2777 (outs), (ins GR8:$src1, i8imm:$src2),
2778 "test{b}\t{$src2, $src1|$src1, $src2}",
2779 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
2780 (implicit EFLAGS)]>;
2781 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2782 (outs), (ins GR16:$src1, i16imm:$src2),
2783 "test{w}\t{$src2, $src1|$src1, $src2}",
2784 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
2785 (implicit EFLAGS)]>, OpSize;
2786 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2787 (outs), (ins GR32:$src1, i32imm:$src2),
2788 "test{l}\t{$src2, $src1|$src1, $src2}",
2789 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
2790 (implicit EFLAGS)]>;
2792 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2793 (outs), (ins i8mem:$src1, i8imm:$src2),
2794 "test{b}\t{$src2, $src1|$src1, $src2}",
2795 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2796 (implicit EFLAGS)]>;
2797 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2798 (outs), (ins i16mem:$src1, i16imm:$src2),
2799 "test{w}\t{$src2, $src1|$src1, $src2}",
2800 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2801 (implicit EFLAGS)]>, OpSize;
2802 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2803 (outs), (ins i32mem:$src1, i32imm:$src2),
2804 "test{l}\t{$src2, $src1|$src1, $src2}",
2805 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2806 (implicit EFLAGS)]>;
2807 } // Defs = [EFLAGS]
2810 // Condition code ops, incl. set if equal/not equal/...
2811 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2812 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2813 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2814 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2816 let Uses = [EFLAGS] in {
2817 def SETEr : I<0x94, MRM0r,
2818 (outs GR8 :$dst), (ins),
2820 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2822 def SETEm : I<0x94, MRM0m,
2823 (outs), (ins i8mem:$dst),
2825 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2828 def SETNEr : I<0x95, MRM0r,
2829 (outs GR8 :$dst), (ins),
2831 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2833 def SETNEm : I<0x95, MRM0m,
2834 (outs), (ins i8mem:$dst),
2836 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2839 def SETLr : I<0x9C, MRM0r,
2840 (outs GR8 :$dst), (ins),
2842 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2843 TB; // GR8 = < signed
2844 def SETLm : I<0x9C, MRM0m,
2845 (outs), (ins i8mem:$dst),
2847 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2848 TB; // [mem8] = < signed
2850 def SETGEr : I<0x9D, MRM0r,
2851 (outs GR8 :$dst), (ins),
2853 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2854 TB; // GR8 = >= signed
2855 def SETGEm : I<0x9D, MRM0m,
2856 (outs), (ins i8mem:$dst),
2858 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2859 TB; // [mem8] = >= signed
2861 def SETLEr : I<0x9E, MRM0r,
2862 (outs GR8 :$dst), (ins),
2864 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2865 TB; // GR8 = <= signed
2866 def SETLEm : I<0x9E, MRM0m,
2867 (outs), (ins i8mem:$dst),
2869 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2870 TB; // [mem8] = <= signed
2872 def SETGr : I<0x9F, MRM0r,
2873 (outs GR8 :$dst), (ins),
2875 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2876 TB; // GR8 = > signed
2877 def SETGm : I<0x9F, MRM0m,
2878 (outs), (ins i8mem:$dst),
2880 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2881 TB; // [mem8] = > signed
2883 def SETBr : I<0x92, MRM0r,
2884 (outs GR8 :$dst), (ins),
2886 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2887 TB; // GR8 = < unsign
2888 def SETBm : I<0x92, MRM0m,
2889 (outs), (ins i8mem:$dst),
2891 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
2892 TB; // [mem8] = < unsign
2894 def SETAEr : I<0x93, MRM0r,
2895 (outs GR8 :$dst), (ins),
2897 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
2898 TB; // GR8 = >= unsign
2899 def SETAEm : I<0x93, MRM0m,
2900 (outs), (ins i8mem:$dst),
2902 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
2903 TB; // [mem8] = >= unsign
2905 def SETBEr : I<0x96, MRM0r,
2906 (outs GR8 :$dst), (ins),
2908 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
2909 TB; // GR8 = <= unsign
2910 def SETBEm : I<0x96, MRM0m,
2911 (outs), (ins i8mem:$dst),
2913 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
2914 TB; // [mem8] = <= unsign
2916 def SETAr : I<0x97, MRM0r,
2917 (outs GR8 :$dst), (ins),
2919 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
2920 TB; // GR8 = > signed
2921 def SETAm : I<0x97, MRM0m,
2922 (outs), (ins i8mem:$dst),
2924 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
2925 TB; // [mem8] = > signed
2927 def SETSr : I<0x98, MRM0r,
2928 (outs GR8 :$dst), (ins),
2930 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
2931 TB; // GR8 = <sign bit>
2932 def SETSm : I<0x98, MRM0m,
2933 (outs), (ins i8mem:$dst),
2935 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
2936 TB; // [mem8] = <sign bit>
2937 def SETNSr : I<0x99, MRM0r,
2938 (outs GR8 :$dst), (ins),
2940 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
2941 TB; // GR8 = !<sign bit>
2942 def SETNSm : I<0x99, MRM0m,
2943 (outs), (ins i8mem:$dst),
2945 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
2946 TB; // [mem8] = !<sign bit>
2948 def SETPr : I<0x9A, MRM0r,
2949 (outs GR8 :$dst), (ins),
2951 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
2953 def SETPm : I<0x9A, MRM0m,
2954 (outs), (ins i8mem:$dst),
2956 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
2957 TB; // [mem8] = parity
2958 def SETNPr : I<0x9B, MRM0r,
2959 (outs GR8 :$dst), (ins),
2961 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
2962 TB; // GR8 = not parity
2963 def SETNPm : I<0x9B, MRM0m,
2964 (outs), (ins i8mem:$dst),
2966 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
2967 TB; // [mem8] = not parity
2969 def SETOr : I<0x90, MRM0r,
2970 (outs GR8 :$dst), (ins),
2972 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
2973 TB; // GR8 = overflow
2974 def SETOm : I<0x90, MRM0m,
2975 (outs), (ins i8mem:$dst),
2977 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
2978 TB; // [mem8] = overflow
2979 def SETNOr : I<0x91, MRM0r,
2980 (outs GR8 :$dst), (ins),
2982 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
2983 TB; // GR8 = not overflow
2984 def SETNOm : I<0x91, MRM0m,
2985 (outs), (ins i8mem:$dst),
2987 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
2988 TB; // [mem8] = not overflow
2989 } // Uses = [EFLAGS]
2992 // Integer comparisons
2993 let Defs = [EFLAGS] in {
2994 def CMP8rr : I<0x38, MRMDestReg,
2995 (outs), (ins GR8 :$src1, GR8 :$src2),
2996 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2997 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2998 def CMP16rr : I<0x39, MRMDestReg,
2999 (outs), (ins GR16:$src1, GR16:$src2),
3000 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3001 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
3002 def CMP32rr : I<0x39, MRMDestReg,
3003 (outs), (ins GR32:$src1, GR32:$src2),
3004 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3005 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
3006 def CMP8mr : I<0x38, MRMDestMem,
3007 (outs), (ins i8mem :$src1, GR8 :$src2),
3008 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3009 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
3010 (implicit EFLAGS)]>;
3011 def CMP16mr : I<0x39, MRMDestMem,
3012 (outs), (ins i16mem:$src1, GR16:$src2),
3013 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3014 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
3015 (implicit EFLAGS)]>, OpSize;
3016 def CMP32mr : I<0x39, MRMDestMem,
3017 (outs), (ins i32mem:$src1, GR32:$src2),
3018 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3019 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
3020 (implicit EFLAGS)]>;
3021 def CMP8rm : I<0x3A, MRMSrcMem,
3022 (outs), (ins GR8 :$src1, i8mem :$src2),
3023 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3024 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
3025 (implicit EFLAGS)]>;
3026 def CMP16rm : I<0x3B, MRMSrcMem,
3027 (outs), (ins GR16:$src1, i16mem:$src2),
3028 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3029 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
3030 (implicit EFLAGS)]>, OpSize;
3031 def CMP32rm : I<0x3B, MRMSrcMem,
3032 (outs), (ins GR32:$src1, i32mem:$src2),
3033 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3034 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
3035 (implicit EFLAGS)]>;
3036 def CMP8ri : Ii8<0x80, MRM7r,
3037 (outs), (ins GR8:$src1, i8imm:$src2),
3038 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3039 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
3040 def CMP16ri : Ii16<0x81, MRM7r,
3041 (outs), (ins GR16:$src1, i16imm:$src2),
3042 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3043 [(X86cmp GR16:$src1, imm:$src2),
3044 (implicit EFLAGS)]>, OpSize;
3045 def CMP32ri : Ii32<0x81, MRM7r,
3046 (outs), (ins GR32:$src1, i32imm:$src2),
3047 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3048 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
3049 def CMP8mi : Ii8 <0x80, MRM7m,
3050 (outs), (ins i8mem :$src1, i8imm :$src2),
3051 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3052 [(X86cmp (loadi8 addr:$src1), imm:$src2),
3053 (implicit EFLAGS)]>;
3054 def CMP16mi : Ii16<0x81, MRM7m,
3055 (outs), (ins i16mem:$src1, i16imm:$src2),
3056 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3057 [(X86cmp (loadi16 addr:$src1), imm:$src2),
3058 (implicit EFLAGS)]>, OpSize;
3059 def CMP32mi : Ii32<0x81, MRM7m,
3060 (outs), (ins i32mem:$src1, i32imm:$src2),
3061 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3062 [(X86cmp (loadi32 addr:$src1), imm:$src2),
3063 (implicit EFLAGS)]>;
3064 def CMP16ri8 : Ii8<0x83, MRM7r,
3065 (outs), (ins GR16:$src1, i16i8imm:$src2),
3066 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3067 [(X86cmp GR16:$src1, i16immSExt8:$src2),
3068 (implicit EFLAGS)]>, OpSize;
3069 def CMP16mi8 : Ii8<0x83, MRM7m,
3070 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3071 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3072 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
3073 (implicit EFLAGS)]>, OpSize;
3074 def CMP32mi8 : Ii8<0x83, MRM7m,
3075 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3076 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3077 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
3078 (implicit EFLAGS)]>;
3079 def CMP32ri8 : Ii8<0x83, MRM7r,
3080 (outs), (ins GR32:$src1, i32i8imm:$src2),
3081 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3082 [(X86cmp GR32:$src1, i32immSExt8:$src2),
3083 (implicit EFLAGS)]>;
3084 } // Defs = [EFLAGS]
3087 // TODO: BTC, BTR, and BTS
3088 let Defs = [EFLAGS] in {
3089 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3090 "bt{w}\t{$src2, $src1|$src1, $src2}",
3091 [(X86bt GR16:$src1, GR16:$src2),
3092 (implicit EFLAGS)]>, OpSize, TB;
3093 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3094 "bt{l}\t{$src2, $src1|$src1, $src2}",
3095 [(X86bt GR32:$src1, GR32:$src2),
3096 (implicit EFLAGS)]>, TB;
3098 // Unlike with the register+register form, the memory+register form of the
3099 // bt instruction does not ignore the high bits of the index. From ISel's
3100 // perspective, this is pretty bizarre. Disable these instructions for now.
3101 //def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3102 // "bt{w}\t{$src2, $src1|$src1, $src2}",
3103 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3104 // (implicit EFLAGS)]>, OpSize, TB, Requires<[FastBTMem]>;
3105 //def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3106 // "bt{l}\t{$src2, $src1|$src1, $src2}",
3107 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3108 // (implicit EFLAGS)]>, TB, Requires<[FastBTMem]>;
3110 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3111 "bt{w}\t{$src2, $src1|$src1, $src2}",
3112 [(X86bt GR16:$src1, i16immSExt8:$src2),
3113 (implicit EFLAGS)]>, OpSize, TB;
3114 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3115 "bt{l}\t{$src2, $src1|$src1, $src2}",
3116 [(X86bt GR32:$src1, i32immSExt8:$src2),
3117 (implicit EFLAGS)]>, TB;
3118 // Note that these instructions don't need FastBTMem because that
3119 // only applies when the other operand is in a register. When it's
3120 // an immediate, bt is still fast.
3121 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3122 "bt{w}\t{$src2, $src1|$src1, $src2}",
3123 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
3124 (implicit EFLAGS)]>, OpSize, TB;
3125 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3126 "bt{l}\t{$src2, $src1|$src1, $src2}",
3127 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
3128 (implicit EFLAGS)]>, TB;
3129 } // Defs = [EFLAGS]
3131 // Sign/Zero extenders
3132 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3133 // of the register here. This has a smaller encoding and avoids a
3134 // partial-register update.
3135 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3136 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3137 [(set GR16:$dst, (sext GR8:$src))]>, TB;
3138 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3139 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3140 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3141 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3142 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3143 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3144 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3145 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3146 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3147 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3148 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3149 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3150 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3151 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3152 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3154 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3155 // of the register here. This has a smaller encoding and avoids a
3156 // partial-register update.
3157 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3158 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3159 [(set GR16:$dst, (zext GR8:$src))]>, TB;
3160 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3161 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3162 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3163 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3164 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3165 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3166 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3167 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3168 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3169 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3170 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3171 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3172 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3173 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3174 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3176 // These are the same as the regular regular MOVZX32rr8 and MOVZX32rm8
3177 // except that they use GR32_NOREX for the output operand register class
3178 // instead of GR32. This allows them to operate on h registers on x86-64.
3179 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3180 (outs GR32_NOREX:$dst), (ins GR8:$src),
3181 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3184 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3185 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3186 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3189 let neverHasSideEffects = 1 in {
3190 let Defs = [AX], Uses = [AL] in
3191 def CBW : I<0x98, RawFrm, (outs), (ins),
3192 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3193 let Defs = [EAX], Uses = [AX] in
3194 def CWDE : I<0x98, RawFrm, (outs), (ins),
3195 "{cwtl|cwde}", []>; // EAX = signext(AX)
3197 let Defs = [AX,DX], Uses = [AX] in
3198 def CWD : I<0x99, RawFrm, (outs), (ins),
3199 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3200 let Defs = [EAX,EDX], Uses = [EAX] in
3201 def CDQ : I<0x99, RawFrm, (outs), (ins),
3202 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3205 //===----------------------------------------------------------------------===//
3206 // Alias Instructions
3207 //===----------------------------------------------------------------------===//
3209 // Alias instructions that map movr0 to xor.
3210 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3211 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3212 isCodeGenOnly = 1 in {
3213 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
3214 "xor{b}\t$dst, $dst",
3215 [(set GR8:$dst, 0)]>;
3216 // Use xorl instead of xorw since we don't care about the high 16 bits,
3217 // it's smaller, and it avoids a partial-register update.
3218 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3219 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
3220 [(set GR16:$dst, 0)]>;
3221 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
3222 "xor{l}\t$dst, $dst",
3223 [(set GR32:$dst, 0)]>;
3226 //===----------------------------------------------------------------------===//
3227 // Thread Local Storage Instructions
3230 // All calls clobber the non-callee saved registers. ESP is marked as
3231 // a use to prevent stack-pointer assignments that appear immediately
3232 // before calls from potentially appearing dead.
3233 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3234 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3235 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3236 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3238 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3239 "leal\t$sym, %eax; "
3240 "call\t___tls_get_addr@PLT",
3241 [(X86tlsaddr tls32addr:$sym)]>,
3242 Requires<[In32BitMode]>;
3244 let AddedComplexity = 5, isCodeGenOnly = 1 in
3245 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3246 "movl\t%gs:$src, $dst",
3247 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3249 let AddedComplexity = 5, isCodeGenOnly = 1 in
3250 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3251 "movl\t%fs:$src, $dst",
3252 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3254 //===----------------------------------------------------------------------===//
3255 // DWARF Pseudo Instructions
3258 def DWARF_LOC : I<0, Pseudo, (outs),
3259 (ins i32imm:$line, i32imm:$col, i32imm:$file),
3260 ".loc\t$file $line $col",
3261 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
3264 //===----------------------------------------------------------------------===//
3265 // EH Pseudo Instructions
3267 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3268 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3269 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3270 "ret\t#eh_return, addr: $addr",
3271 [(X86ehret GR32:$addr)]>;
3275 //===----------------------------------------------------------------------===//
3279 // Atomic swap. These are just normal xchg instructions. But since a memory
3280 // operand is referenced, the atomicity is ensured.
3281 let Constraints = "$val = $dst" in {
3282 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3283 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3284 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3285 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3286 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3287 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3289 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3290 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3291 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3294 // Atomic compare and swap.
3295 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3296 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3298 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3299 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3301 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3302 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
3305 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3308 let Defs = [AX, EFLAGS], Uses = [AX] in {
3309 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3311 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3312 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3314 let Defs = [AL, EFLAGS], Uses = [AL] in {
3315 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3317 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3318 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3321 // Atomic exchange and add
3322 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3323 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3325 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3326 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3328 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3330 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3331 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3333 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3335 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3336 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3340 // Optimized codegen when the non-memory output is not used.
3341 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3342 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3344 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3345 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3347 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3348 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3350 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3351 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3353 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3354 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3356 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3357 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3359 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3360 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3362 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3363 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3365 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3367 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3369 "inc{b}\t$dst", []>, LOCK;
3370 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3372 "inc{w}\t$dst", []>, OpSize, LOCK;
3373 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3375 "inc{l}\t$dst", []>, LOCK;
3377 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3379 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3380 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3382 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3383 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3385 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3386 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3388 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3389 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3391 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3392 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3394 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3395 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3397 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3398 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3400 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3402 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3404 "dec{b}\t$dst", []>, LOCK;
3405 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3407 "dec{w}\t$dst", []>, OpSize, LOCK;
3408 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3410 "dec{l}\t$dst", []>, LOCK;
3412 // Atomic exchange, and, or, xor
3413 let Constraints = "$val = $dst", Defs = [EFLAGS],
3414 usesCustomDAGSchedInserter = 1 in {
3415 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3416 "#ATOMAND32 PSEUDO!",
3417 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3418 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3419 "#ATOMOR32 PSEUDO!",
3420 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
3421 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3422 "#ATOMXOR32 PSEUDO!",
3423 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
3424 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3425 "#ATOMNAND32 PSEUDO!",
3426 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
3427 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3428 "#ATOMMIN32 PSEUDO!",
3429 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
3430 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3431 "#ATOMMAX32 PSEUDO!",
3432 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
3433 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3434 "#ATOMUMIN32 PSEUDO!",
3435 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
3436 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3437 "#ATOMUMAX32 PSEUDO!",
3438 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
3440 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3441 "#ATOMAND16 PSEUDO!",
3442 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
3443 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3444 "#ATOMOR16 PSEUDO!",
3445 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
3446 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3447 "#ATOMXOR16 PSEUDO!",
3448 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
3449 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3450 "#ATOMNAND16 PSEUDO!",
3451 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
3452 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3453 "#ATOMMIN16 PSEUDO!",
3454 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
3455 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3456 "#ATOMMAX16 PSEUDO!",
3457 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
3458 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3459 "#ATOMUMIN16 PSEUDO!",
3460 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
3461 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3462 "#ATOMUMAX16 PSEUDO!",
3463 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
3465 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3466 "#ATOMAND8 PSEUDO!",
3467 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
3468 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3470 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
3471 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3472 "#ATOMXOR8 PSEUDO!",
3473 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
3474 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3475 "#ATOMNAND8 PSEUDO!",
3476 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
3479 let Constraints = "$val1 = $dst1, $val2 = $dst2",
3480 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
3481 Uses = [EAX, EBX, ECX, EDX],
3482 mayLoad = 1, mayStore = 1,
3483 usesCustomDAGSchedInserter = 1 in {
3484 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3485 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3486 "#ATOMAND6432 PSEUDO!", []>;
3487 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3488 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3489 "#ATOMOR6432 PSEUDO!", []>;
3490 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3491 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3492 "#ATOMXOR6432 PSEUDO!", []>;
3493 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3494 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3495 "#ATOMNAND6432 PSEUDO!", []>;
3496 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3497 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3498 "#ATOMADD6432 PSEUDO!", []>;
3499 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3500 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3501 "#ATOMSUB6432 PSEUDO!", []>;
3502 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3503 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3504 "#ATOMSWAP6432 PSEUDO!", []>;
3507 //===----------------------------------------------------------------------===//
3508 // Non-Instruction Patterns
3509 //===----------------------------------------------------------------------===//
3511 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
3512 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
3513 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
3514 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
3515 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
3516 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
3518 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
3519 (ADD32ri GR32:$src1, tconstpool:$src2)>;
3520 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
3521 (ADD32ri GR32:$src1, tjumptable:$src2)>;
3522 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
3523 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
3524 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
3525 (ADD32ri GR32:$src1, texternalsym:$src2)>;
3527 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
3528 (MOV32mi addr:$dst, tglobaladdr:$src)>;
3529 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
3530 (MOV32mi addr:$dst, texternalsym:$src)>;
3534 def : Pat<(X86tcret GR32:$dst, imm:$off),
3535 (TCRETURNri GR32:$dst, imm:$off)>;
3537 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
3538 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3540 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
3541 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3543 // Normal calls, with various flavors of addresses.
3544 def : Pat<(X86call (i32 tglobaladdr:$dst)),
3545 (CALLpcrel32 tglobaladdr:$dst)>;
3546 def : Pat<(X86call (i32 texternalsym:$dst)),
3547 (CALLpcrel32 texternalsym:$dst)>;
3548 def : Pat<(X86call (i32 imm:$dst)),
3549 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
3551 // X86 specific add which produces a flag.
3552 def : Pat<(addc GR32:$src1, GR32:$src2),
3553 (ADD32rr GR32:$src1, GR32:$src2)>;
3554 def : Pat<(addc GR32:$src1, (load addr:$src2)),
3555 (ADD32rm GR32:$src1, addr:$src2)>;
3556 def : Pat<(addc GR32:$src1, imm:$src2),
3557 (ADD32ri GR32:$src1, imm:$src2)>;
3558 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
3559 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3561 def : Pat<(subc GR32:$src1, GR32:$src2),
3562 (SUB32rr GR32:$src1, GR32:$src2)>;
3563 def : Pat<(subc GR32:$src1, (load addr:$src2)),
3564 (SUB32rm GR32:$src1, addr:$src2)>;
3565 def : Pat<(subc GR32:$src1, imm:$src2),
3566 (SUB32ri GR32:$src1, imm:$src2)>;
3567 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
3568 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3572 // TEST R,R is smaller than CMP R,0
3573 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
3574 (TEST8rr GR8:$src1, GR8:$src1)>;
3575 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
3576 (TEST16rr GR16:$src1, GR16:$src1)>;
3577 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
3578 (TEST32rr GR32:$src1, GR32:$src1)>;
3580 // Conditional moves with folded loads with operands swapped and conditions
3582 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
3583 (CMOVAE16rm GR16:$src2, addr:$src1)>;
3584 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
3585 (CMOVAE32rm GR32:$src2, addr:$src1)>;
3586 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
3587 (CMOVB16rm GR16:$src2, addr:$src1)>;
3588 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
3589 (CMOVB32rm GR32:$src2, addr:$src1)>;
3590 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
3591 (CMOVNE16rm GR16:$src2, addr:$src1)>;
3592 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
3593 (CMOVNE32rm GR32:$src2, addr:$src1)>;
3594 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
3595 (CMOVE16rm GR16:$src2, addr:$src1)>;
3596 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
3597 (CMOVE32rm GR32:$src2, addr:$src1)>;
3598 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
3599 (CMOVA16rm GR16:$src2, addr:$src1)>;
3600 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
3601 (CMOVA32rm GR32:$src2, addr:$src1)>;
3602 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
3603 (CMOVBE16rm GR16:$src2, addr:$src1)>;
3604 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
3605 (CMOVBE32rm GR32:$src2, addr:$src1)>;
3606 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
3607 (CMOVGE16rm GR16:$src2, addr:$src1)>;
3608 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
3609 (CMOVGE32rm GR32:$src2, addr:$src1)>;
3610 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
3611 (CMOVL16rm GR16:$src2, addr:$src1)>;
3612 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
3613 (CMOVL32rm GR32:$src2, addr:$src1)>;
3614 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
3615 (CMOVG16rm GR16:$src2, addr:$src1)>;
3616 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
3617 (CMOVG32rm GR32:$src2, addr:$src1)>;
3618 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
3619 (CMOVLE16rm GR16:$src2, addr:$src1)>;
3620 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
3621 (CMOVLE32rm GR32:$src2, addr:$src1)>;
3622 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
3623 (CMOVNP16rm GR16:$src2, addr:$src1)>;
3624 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
3625 (CMOVNP32rm GR32:$src2, addr:$src1)>;
3626 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
3627 (CMOVP16rm GR16:$src2, addr:$src1)>;
3628 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
3629 (CMOVP32rm GR32:$src2, addr:$src1)>;
3630 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
3631 (CMOVNS16rm GR16:$src2, addr:$src1)>;
3632 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
3633 (CMOVNS32rm GR32:$src2, addr:$src1)>;
3634 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
3635 (CMOVS16rm GR16:$src2, addr:$src1)>;
3636 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
3637 (CMOVS32rm GR32:$src2, addr:$src1)>;
3638 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
3639 (CMOVNO16rm GR16:$src2, addr:$src1)>;
3640 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
3641 (CMOVNO32rm GR32:$src2, addr:$src1)>;
3642 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
3643 (CMOVO16rm GR16:$src2, addr:$src1)>;
3644 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
3645 (CMOVO32rm GR32:$src2, addr:$src1)>;
3647 // zextload bool -> zextload byte
3648 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3649 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3650 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3652 // extload bool -> extload byte
3653 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3654 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3655 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3656 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
3657 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
3658 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
3660 // anyext. Define these to do an explicit zero-extend to
3661 // avoid partial-register updates.
3662 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
3663 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
3664 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
3666 // (and (i32 load), 255) -> (zextload i8)
3667 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
3668 (MOVZX32rm8 addr:$src)>;
3669 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
3670 (MOVZX32rm16 addr:$src)>;
3672 //===----------------------------------------------------------------------===//
3674 //===----------------------------------------------------------------------===//
3676 // Odd encoding trick: -128 fits into an 8-bit immediate field while
3677 // +128 doesn't, so in this special case use a sub instead of an add.
3678 def : Pat<(add GR16:$src1, 128),
3679 (SUB16ri8 GR16:$src1, -128)>;
3680 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
3681 (SUB16mi8 addr:$dst, -128)>;
3682 def : Pat<(add GR32:$src1, 128),
3683 (SUB32ri8 GR32:$src1, -128)>;
3684 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
3685 (SUB32mi8 addr:$dst, -128)>;
3687 // r & (2^16-1) ==> movz
3688 def : Pat<(and GR32:$src1, 0xffff),
3689 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
3690 // r & (2^8-1) ==> movz
3691 def : Pat<(and GR32:$src1, 0xff),
3692 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src1, GR32_ABCD),
3694 Requires<[In32BitMode]>;
3695 // r & (2^8-1) ==> movz
3696 def : Pat<(and GR16:$src1, 0xff),
3697 (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD),
3699 Requires<[In32BitMode]>;
3701 // sext_inreg patterns
3702 def : Pat<(sext_inreg GR32:$src, i16),
3703 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
3704 def : Pat<(sext_inreg GR32:$src, i8),
3705 (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3707 Requires<[In32BitMode]>;
3708 def : Pat<(sext_inreg GR16:$src, i8),
3709 (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3711 Requires<[In32BitMode]>;
3714 def : Pat<(i16 (trunc GR32:$src)),
3715 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
3716 def : Pat<(i8 (trunc GR32:$src)),
3717 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3719 Requires<[In32BitMode]>;
3720 def : Pat<(i8 (trunc GR16:$src)),
3721 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3723 Requires<[In32BitMode]>;
3725 // h-register tricks
3726 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
3727 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3728 x86_subreg_8bit_hi)>,
3729 Requires<[In32BitMode]>;
3730 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
3731 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3732 x86_subreg_8bit_hi)>,
3733 Requires<[In32BitMode]>;
3734 def : Pat<(srl_su GR16:$src, (i8 8)),
3737 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3738 x86_subreg_8bit_hi)),
3740 Requires<[In32BitMode]>;
3741 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
3742 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3743 x86_subreg_8bit_hi))>,
3744 Requires<[In32BitMode]>;
3745 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
3746 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3747 x86_subreg_8bit_hi))>,
3748 Requires<[In32BitMode]>;
3749 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
3750 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3751 x86_subreg_8bit_hi))>,
3752 Requires<[In32BitMode]>;
3754 // (shl x, 1) ==> (add x, x)
3755 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
3756 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
3757 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
3759 // (shl x (and y, 31)) ==> (shl x, y)
3760 def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
3761 (SHL8rCL GR8:$src1)>;
3762 def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
3763 (SHL16rCL GR16:$src1)>;
3764 def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
3765 (SHL32rCL GR32:$src1)>;
3766 def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3767 (SHL8mCL addr:$dst)>;
3768 def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3769 (SHL16mCL addr:$dst)>;
3770 def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3771 (SHL32mCL addr:$dst)>;
3773 def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
3774 (SHR8rCL GR8:$src1)>;
3775 def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
3776 (SHR16rCL GR16:$src1)>;
3777 def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
3778 (SHR32rCL GR32:$src1)>;
3779 def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3780 (SHR8mCL addr:$dst)>;
3781 def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3782 (SHR16mCL addr:$dst)>;
3783 def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3784 (SHR32mCL addr:$dst)>;
3786 def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
3787 (SAR8rCL GR8:$src1)>;
3788 def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
3789 (SAR16rCL GR16:$src1)>;
3790 def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
3791 (SAR32rCL GR32:$src1)>;
3792 def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3793 (SAR8mCL addr:$dst)>;
3794 def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3795 (SAR16mCL addr:$dst)>;
3796 def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3797 (SAR32mCL addr:$dst)>;
3799 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
3800 def : Pat<(or (srl GR32:$src1, CL:$amt),
3801 (shl GR32:$src2, (sub 32, CL:$amt))),
3802 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3804 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
3805 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3806 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3808 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
3809 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3810 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3812 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3813 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3815 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3817 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3818 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3820 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
3821 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3822 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3824 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
3825 def : Pat<(or (shl GR32:$src1, CL:$amt),
3826 (srl GR32:$src2, (sub 32, CL:$amt))),
3827 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3829 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
3830 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3831 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3833 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
3834 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3835 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3837 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3838 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3840 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3842 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3843 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3845 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
3846 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3847 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3849 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
3850 def : Pat<(or (srl GR16:$src1, CL:$amt),
3851 (shl GR16:$src2, (sub 16, CL:$amt))),
3852 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3854 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
3855 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3856 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3858 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
3859 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3860 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3862 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3863 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3865 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3867 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3868 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3870 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
3871 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3872 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3874 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
3875 def : Pat<(or (shl GR16:$src1, CL:$amt),
3876 (srl GR16:$src2, (sub 16, CL:$amt))),
3877 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3879 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
3880 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3881 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3883 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
3884 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3885 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3887 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3888 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3890 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3892 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3893 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3895 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
3896 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3897 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3899 //===----------------------------------------------------------------------===//
3900 // EFLAGS-defining Patterns
3901 //===----------------------------------------------------------------------===//
3903 // Register-Register Addition with EFLAGS result
3904 def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
3906 (ADD8rr GR8:$src1, GR8:$src2)>;
3907 def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
3909 (ADD16rr GR16:$src1, GR16:$src2)>;
3910 def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
3912 (ADD32rr GR32:$src1, GR32:$src2)>;
3914 // Register-Memory Addition with EFLAGS result
3915 def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
3917 (ADD8rm GR8:$src1, addr:$src2)>;
3918 def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
3920 (ADD16rm GR16:$src1, addr:$src2)>;
3921 def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
3923 (ADD32rm GR32:$src1, addr:$src2)>;
3925 // Register-Integer Addition with EFLAGS result
3926 def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
3928 (ADD8ri GR8:$src1, imm:$src2)>;
3929 def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
3931 (ADD16ri GR16:$src1, imm:$src2)>;
3932 def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
3934 (ADD32ri GR32:$src1, imm:$src2)>;
3935 def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
3937 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
3938 def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
3940 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3942 // Memory-Register Addition with EFLAGS result
3943 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
3946 (ADD8mr addr:$dst, GR8:$src2)>;
3947 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
3950 (ADD16mr addr:$dst, GR16:$src2)>;
3951 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
3954 (ADD32mr addr:$dst, GR32:$src2)>;
3956 // Memory-Integer Addition with EFLAGS result
3957 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
3960 (ADD8mi addr:$dst, imm:$src2)>;
3961 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
3964 (ADD16mi addr:$dst, imm:$src2)>;
3965 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
3968 (ADD32mi addr:$dst, imm:$src2)>;
3969 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
3972 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
3973 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
3976 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
3978 // Register-Register Subtraction with EFLAGS result
3979 def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
3981 (SUB8rr GR8:$src1, GR8:$src2)>;
3982 def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
3984 (SUB16rr GR16:$src1, GR16:$src2)>;
3985 def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
3987 (SUB32rr GR32:$src1, GR32:$src2)>;
3989 // Register-Memory Subtraction with EFLAGS result
3990 def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
3992 (SUB8rm GR8:$src1, addr:$src2)>;
3993 def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
3995 (SUB16rm GR16:$src1, addr:$src2)>;
3996 def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
3998 (SUB32rm GR32:$src1, addr:$src2)>;
4000 // Register-Integer Subtraction with EFLAGS result
4001 def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
4003 (SUB8ri GR8:$src1, imm:$src2)>;
4004 def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
4006 (SUB16ri GR16:$src1, imm:$src2)>;
4007 def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
4009 (SUB32ri GR32:$src1, imm:$src2)>;
4010 def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
4012 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4013 def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
4015 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4017 // Memory-Register Subtraction with EFLAGS result
4018 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
4021 (SUB8mr addr:$dst, GR8:$src2)>;
4022 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
4025 (SUB16mr addr:$dst, GR16:$src2)>;
4026 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
4029 (SUB32mr addr:$dst, GR32:$src2)>;
4031 // Memory-Integer Subtraction with EFLAGS result
4032 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
4035 (SUB8mi addr:$dst, imm:$src2)>;
4036 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
4039 (SUB16mi addr:$dst, imm:$src2)>;
4040 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
4043 (SUB32mi addr:$dst, imm:$src2)>;
4044 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4047 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
4048 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4051 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
4054 // Register-Register Signed Integer Multiply with EFLAGS result
4055 def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
4057 (IMUL16rr GR16:$src1, GR16:$src2)>;
4058 def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
4060 (IMUL32rr GR32:$src1, GR32:$src2)>;
4062 // Register-Memory Signed Integer Multiply with EFLAGS result
4063 def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
4065 (IMUL16rm GR16:$src1, addr:$src2)>;
4066 def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
4068 (IMUL32rm GR32:$src1, addr:$src2)>;
4070 // Register-Integer Signed Integer Multiply with EFLAGS result
4071 def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
4073 (IMUL16rri GR16:$src1, imm:$src2)>;
4074 def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
4076 (IMUL32rri GR32:$src1, imm:$src2)>;
4077 def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
4079 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4080 def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
4082 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4084 // Memory-Integer Signed Integer Multiply with EFLAGS result
4085 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
4087 (IMUL16rmi addr:$src1, imm:$src2)>;
4088 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
4090 (IMUL32rmi addr:$src1, imm:$src2)>;
4091 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
4093 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4094 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
4096 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4098 // Optimize multiply by 2 with EFLAGS result.
4099 let AddedComplexity = 2 in {
4100 def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
4102 (ADD16rr GR16:$src1, GR16:$src1)>;
4104 def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
4106 (ADD32rr GR32:$src1, GR32:$src1)>;
4109 // INC and DEC with EFLAGS result. Note that these do not set CF.
4110 def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
4112 def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
4115 def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
4117 def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
4121 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
4122 (INC16r GR16:$src)>, Requires<[In32BitMode]>;
4123 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
4125 (INC16m addr:$dst)>, Requires<[In32BitMode]>;
4126 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
4127 (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
4128 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
4130 (DEC16m addr:$dst)>, Requires<[In32BitMode]>;
4132 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
4133 (INC32r GR32:$src)>, Requires<[In32BitMode]>;
4134 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
4136 (INC32m addr:$dst)>, Requires<[In32BitMode]>;
4137 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
4138 (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
4139 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
4141 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
4143 //===----------------------------------------------------------------------===//
4144 // Floating Point Stack Support
4145 //===----------------------------------------------------------------------===//
4147 include "X86InstrFPStack.td"
4149 //===----------------------------------------------------------------------===//
4151 //===----------------------------------------------------------------------===//
4153 include "X86Instr64bit.td"
4155 //===----------------------------------------------------------------------===//
4156 // XMM Floating point support (requires SSE / SSE2)
4157 //===----------------------------------------------------------------------===//
4159 include "X86InstrSSE.td"
4161 //===----------------------------------------------------------------------===//
4162 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
4163 //===----------------------------------------------------------------------===//
4165 include "X86InstrMMX.td"