1 //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
30 def SDTX86BrCond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>;
33 def SDTX86SetCC : SDTypeProfile<1, 1,
34 [SDTCisVT<0, i8>, SDTCisVT<1, i8>]>;
36 def SDTX86Ret : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>;
38 def SDT_X86CallSeqStart : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
39 def SDT_X86CallSeqEnd : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>,
42 def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
44 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
46 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
48 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
50 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
51 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
53 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest,
54 [SDNPHasChain, SDNPOutFlag]>;
56 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov,
57 [SDNPInFlag, SDNPOutFlag]>;
58 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
59 [SDNPHasChain, SDNPInFlag]>;
60 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC,
61 [SDNPInFlag, SDNPOutFlag]>;
63 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
64 [SDNPHasChain, SDNPOptInFlag]>;
66 def X86callseq_start :
67 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
68 [SDNPHasChain, SDNPOutFlag]>;
70 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
71 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
73 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
74 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
76 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
77 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
79 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
80 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
81 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
82 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
84 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
85 [SDNPHasChain, SDNPOutFlag]>;
87 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
88 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
90 //===----------------------------------------------------------------------===//
91 // X86 Operand Definitions.
94 // *mem - Operand definitions for the funky X86 addressing mode operands.
96 class X86MemOperand<string printMethod> : Operand<iPTR> {
97 let PrintMethod = printMethod;
98 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
101 def i8mem : X86MemOperand<"printi8mem">;
102 def i16mem : X86MemOperand<"printi16mem">;
103 def i32mem : X86MemOperand<"printi32mem">;
104 def i64mem : X86MemOperand<"printi64mem">;
105 def i128mem : X86MemOperand<"printi128mem">;
106 def f32mem : X86MemOperand<"printf32mem">;
107 def f64mem : X86MemOperand<"printf64mem">;
108 def f128mem : X86MemOperand<"printf128mem">;
110 def lea32mem : Operand<i32> {
111 let PrintMethod = "printi32mem";
112 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
115 def SSECC : Operand<i8> {
116 let PrintMethod = "printSSECC";
119 def piclabel: Operand<i32> {
120 let PrintMethod = "printPICLabel";
123 // A couple of more descriptive operand definitions.
124 // 16-bits but only 8 bits are significant.
125 def i16i8imm : Operand<i16>;
126 // 32-bits but only 8 bits are significant.
127 def i32i8imm : Operand<i32>;
129 // Branch targets have OtherVT type.
130 def brtarget : Operand<OtherVT>;
132 //===----------------------------------------------------------------------===//
133 // X86 Complex Pattern Definitions.
136 // Define X86 specific addressing mode.
137 def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
138 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
139 [add, mul, shl, or, frameindex], []>;
141 //===----------------------------------------------------------------------===//
142 // X86 Instruction Format Definitions.
145 // Format specifies the encoding used by the instruction. This is part of the
146 // ad-hoc solution used to emit machine instruction encodings by our machine
148 class Format<bits<6> val> {
152 def Pseudo : Format<0>; def RawFrm : Format<1>;
153 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
154 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
155 def MRMSrcMem : Format<6>;
156 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
157 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
158 def MRM6r : Format<22>; def MRM7r : Format<23>;
159 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
160 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
161 def MRM6m : Format<30>; def MRM7m : Format<31>;
162 def MRMInitReg : Format<32>;
164 //===----------------------------------------------------------------------===//
165 // X86 Instruction Predicate Definitions.
166 def HasMMX : Predicate<"Subtarget->hasMMX()">;
167 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
168 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
169 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
170 def FPStack : Predicate<"!Subtarget->hasSSE2()">;
171 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
172 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
173 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
174 def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
175 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
177 //===----------------------------------------------------------------------===//
178 // X86 specific pattern fragments.
181 // ImmType - This specifies the immediate type used by an instruction. This is
182 // part of the ad-hoc solution used to emit machine instruction encodings by our
183 // machine code emitter.
184 class ImmType<bits<3> val> {
187 def NoImm : ImmType<0>;
188 def Imm8 : ImmType<1>;
189 def Imm16 : ImmType<2>;
190 def Imm32 : ImmType<3>;
191 def Imm64 : ImmType<4>;
193 // FPFormat - This specifies what form this FP instruction has. This is used by
194 // the Floating-Point stackifier pass.
195 class FPFormat<bits<3> val> {
198 def NotFP : FPFormat<0>;
199 def ZeroArgFP : FPFormat<1>;
200 def OneArgFP : FPFormat<2>;
201 def OneArgFPRW : FPFormat<3>;
202 def TwoArgFP : FPFormat<4>;
203 def CompareFP : FPFormat<5>;
204 def CondMovFP : FPFormat<6>;
205 def SpecialFP : FPFormat<7>;
208 class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr>
210 let Namespace = "X86";
212 bits<8> Opcode = opcod;
214 bits<6> FormBits = Form.Value;
216 bits<3> ImmTypeBits = ImmT.Value;
218 dag OperandList = ops;
219 string AsmString = AsmStr;
222 // Attributes specific to X86 instructions...
224 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
225 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
227 bits<4> Prefix = 0; // Which prefix byte does this inst have?
228 bit hasREX_WPrefix = 0; // Does this inst requires the REX.W prefix?
229 FPFormat FPForm; // What flavor of FP instruction is this?
230 bits<3> FPFormBits = 0;
234 // Prefix byte classes which are used to indicate to the ad-hoc machine code
235 // emitter that various prefix bytes are required.
236 class OpSize { bit hasOpSizePrefix = 1; }
237 class AdSize { bit hasAdSizePrefix = 1; }
238 class REX_W { bit hasREX_WPrefix = 1; }
239 class TB { bits<4> Prefix = 1; }
240 class REP { bits<4> Prefix = 2; }
241 class D8 { bits<4> Prefix = 3; }
242 class D9 { bits<4> Prefix = 4; }
243 class DA { bits<4> Prefix = 5; }
244 class DB { bits<4> Prefix = 6; }
245 class DC { bits<4> Prefix = 7; }
246 class DD { bits<4> Prefix = 8; }
247 class DE { bits<4> Prefix = 9; }
248 class DF { bits<4> Prefix = 10; }
249 class XD { bits<4> Prefix = 11; }
250 class XS { bits<4> Prefix = 12; }
253 //===----------------------------------------------------------------------===//
254 // Pattern fragments...
257 // X86 specific condition code. These correspond to CondCode in
258 // X86ISelLowering.h. They must be kept in synch.
259 def X86_COND_A : PatLeaf<(i8 0)>;
260 def X86_COND_AE : PatLeaf<(i8 1)>;
261 def X86_COND_B : PatLeaf<(i8 2)>;
262 def X86_COND_BE : PatLeaf<(i8 3)>;
263 def X86_COND_E : PatLeaf<(i8 4)>;
264 def X86_COND_G : PatLeaf<(i8 5)>;
265 def X86_COND_GE : PatLeaf<(i8 6)>;
266 def X86_COND_L : PatLeaf<(i8 7)>;
267 def X86_COND_LE : PatLeaf<(i8 8)>;
268 def X86_COND_NE : PatLeaf<(i8 9)>;
269 def X86_COND_NO : PatLeaf<(i8 10)>;
270 def X86_COND_NP : PatLeaf<(i8 11)>;
271 def X86_COND_NS : PatLeaf<(i8 12)>;
272 def X86_COND_O : PatLeaf<(i8 13)>;
273 def X86_COND_P : PatLeaf<(i8 14)>;
274 def X86_COND_S : PatLeaf<(i8 15)>;
276 def i16immSExt8 : PatLeaf<(i16 imm), [{
277 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
278 // sign extended field.
279 return (int16_t)N->getValue() == (int8_t)N->getValue();
282 def i32immSExt8 : PatLeaf<(i32 imm), [{
283 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
284 // sign extended field.
285 return (int32_t)N->getValue() == (int8_t)N->getValue();
288 // Helper fragments for loads.
289 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
290 def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>;
291 def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>;
292 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
294 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
295 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
297 def sextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (sextloadi1 node:$ptr))>;
298 def sextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (sextloadi1 node:$ptr))>;
299 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
300 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
301 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
303 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
304 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
305 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
306 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
307 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
308 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
310 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
311 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
312 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
313 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
314 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
315 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
317 //===----------------------------------------------------------------------===//
318 // Instruction templates...
321 class I<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
322 : X86Inst<o, f, NoImm, ops, asm> {
323 let Pattern = pattern;
326 class Ii8 <bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
327 : X86Inst<o, f, Imm8 , ops, asm> {
328 let Pattern = pattern;
331 class Ii16<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
332 : X86Inst<o, f, Imm16, ops, asm> {
333 let Pattern = pattern;
336 class Ii32<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
337 : X86Inst<o, f, Imm32, ops, asm> {
338 let Pattern = pattern;
342 //===----------------------------------------------------------------------===//
343 // Instruction list...
346 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
347 // a stack adjustment and the codegen must know that they may modify the stack
348 // pointer before prolog-epilog rewriting occurs.
349 def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN",
350 [(X86callseq_start imm:$amt)]>, Imp<[ESP],[ESP]>;
351 def ADJCALLSTACKUP : I<0, Pseudo, (ops i32imm:$amt1, i32imm:$amt2),
353 [(X86callseq_end imm:$amt1, imm:$amt2)]>,
355 def IMPLICIT_USE : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE", []>;
356 def IMPLICIT_DEF : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF", []>;
357 def IMPLICIT_DEF_GR8 : I<0, Pseudo, (ops GR8:$dst),
358 "#IMPLICIT_DEF $dst",
359 [(set GR8:$dst, (undef))]>;
360 def IMPLICIT_DEF_GR16 : I<0, Pseudo, (ops GR16:$dst),
361 "#IMPLICIT_DEF $dst",
362 [(set GR16:$dst, (undef))]>;
363 def IMPLICIT_DEF_GR32 : I<0, Pseudo, (ops GR32:$dst),
364 "#IMPLICIT_DEF $dst",
365 [(set GR32:$dst, (undef))]>;
368 def NOOP : I<0x90, RawFrm, (ops), "nop", []>;
371 def TRUNC_32_to8 : I<0x88, MRMDestReg, (ops GR8:$dst, GR32_:$src),
372 "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}", []>;
373 def TRUNC_16_to8 : I<0x88, MRMDestReg, (ops GR8:$dst, GR16_:$src),
374 "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}}", []>;
375 def TRUNC_32to16 : I<0x89, MRMDestReg, (ops GR16:$dst, GR32:$src),
376 "mov{w} {${src:subreg16}, $dst|$dst, ${src:subreg16}}",
377 [(set GR16:$dst, (trunc GR32:$src))]>;
379 //===----------------------------------------------------------------------===//
380 // Control Flow Instructions...
383 // Return instructions.
384 let isTerminator = 1, isReturn = 1, isBarrier = 1,
385 hasCtrlDep = 1, noResults = 1 in {
386 def RET : I<0xC3, RawFrm, (ops), "ret", [(X86retflag 0)]>;
387 def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt",
388 [(X86retflag imm:$amt)]>;
391 // All branches are RawFrm, Void, Branch, and Terminators
392 let isBranch = 1, isTerminator = 1, noResults = 1 in
393 class IBr<bits<8> opcode, dag ops, string asm, list<dag> pattern> :
394 I<opcode, RawFrm, ops, asm, pattern>;
397 let isBranch = 1, isBarrier = 1 in
398 def JMP : IBr<0xE9, (ops brtarget:$dst), "jmp $dst", [(br bb:$dst)]>;
400 let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in {
401 def JMP32r : I<0xFF, MRM4r, (ops GR32:$dst), "jmp{l} {*}$dst",
402 [(brind GR32:$dst)]>;
403 def JMP32m : I<0xFF, MRM4m, (ops i32mem:$dst), "jmp{l} {*}$dst",
404 [(brind (loadi32 addr:$dst))]>;
407 // Conditional branches
408 def JE : IBr<0x84, (ops brtarget:$dst), "je $dst",
409 [(X86brcond bb:$dst, X86_COND_E)]>, TB;
410 def JNE : IBr<0x85, (ops brtarget:$dst), "jne $dst",
411 [(X86brcond bb:$dst, X86_COND_NE)]>, TB;
412 def JL : IBr<0x8C, (ops brtarget:$dst), "jl $dst",
413 [(X86brcond bb:$dst, X86_COND_L)]>, TB;
414 def JLE : IBr<0x8E, (ops brtarget:$dst), "jle $dst",
415 [(X86brcond bb:$dst, X86_COND_LE)]>, TB;
416 def JG : IBr<0x8F, (ops brtarget:$dst), "jg $dst",
417 [(X86brcond bb:$dst, X86_COND_G)]>, TB;
418 def JGE : IBr<0x8D, (ops brtarget:$dst), "jge $dst",
419 [(X86brcond bb:$dst, X86_COND_GE)]>, TB;
421 def JB : IBr<0x82, (ops brtarget:$dst), "jb $dst",
422 [(X86brcond bb:$dst, X86_COND_B)]>, TB;
423 def JBE : IBr<0x86, (ops brtarget:$dst), "jbe $dst",
424 [(X86brcond bb:$dst, X86_COND_BE)]>, TB;
425 def JA : IBr<0x87, (ops brtarget:$dst), "ja $dst",
426 [(X86brcond bb:$dst, X86_COND_A)]>, TB;
427 def JAE : IBr<0x83, (ops brtarget:$dst), "jae $dst",
428 [(X86brcond bb:$dst, X86_COND_AE)]>, TB;
430 def JS : IBr<0x88, (ops brtarget:$dst), "js $dst",
431 [(X86brcond bb:$dst, X86_COND_S)]>, TB;
432 def JNS : IBr<0x89, (ops brtarget:$dst), "jns $dst",
433 [(X86brcond bb:$dst, X86_COND_NS)]>, TB;
434 def JP : IBr<0x8A, (ops brtarget:$dst), "jp $dst",
435 [(X86brcond bb:$dst, X86_COND_P)]>, TB;
436 def JNP : IBr<0x8B, (ops brtarget:$dst), "jnp $dst",
437 [(X86brcond bb:$dst, X86_COND_NP)]>, TB;
438 def JO : IBr<0x80, (ops brtarget:$dst), "jo $dst",
439 [(X86brcond bb:$dst, X86_COND_O)]>, TB;
440 def JNO : IBr<0x81, (ops brtarget:$dst), "jno $dst",
441 [(X86brcond bb:$dst, X86_COND_NO)]>, TB;
443 //===----------------------------------------------------------------------===//
444 // Call Instructions...
446 let isCall = 1, noResults = 1 in
447 // All calls clobber the non-callee saved registers...
448 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
449 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in {
450 def CALLpcrel32 : I<0xE8, RawFrm, (ops i32imm:$dst, variable_ops),
451 "call ${dst:call}", []>;
452 def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
453 "call {*}$dst", [(X86call GR32:$dst)]>;
454 def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst, variable_ops),
459 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
460 def TAILJMPd : IBr<0xE9, (ops i32imm:$dst), "jmp ${dst:call} # TAIL CALL",
462 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
463 def TAILJMPr : I<0xFF, MRM4r, (ops GR32:$dst), "jmp {*}$dst # TAIL CALL",
465 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
466 def TAILJMPm : I<0xFF, MRM4m, (ops i32mem:$dst),
467 "jmp {*}$dst # TAIL CALL", []>;
469 //===----------------------------------------------------------------------===//
470 // Miscellaneous Instructions...
472 def LEAVE : I<0xC9, RawFrm,
473 (ops), "leave", []>, Imp<[EBP,ESP],[EBP,ESP]>;
474 def POP32r : I<0x58, AddRegFrm,
475 (ops GR32:$reg), "pop{l} $reg", []>, Imp<[ESP],[ESP]>;
477 def MovePCtoStack : I<0, Pseudo, (ops piclabel:$label),
480 let isTwoAddress = 1 in // GR32 = bswap GR32
481 def BSWAP32r : I<0xC8, AddRegFrm,
482 (ops GR32:$dst, GR32:$src),
484 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
486 def XCHG8rr : I<0x86, MRMDestReg, // xchg GR8, GR8
487 (ops GR8:$src1, GR8:$src2),
488 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
489 def XCHG16rr : I<0x87, MRMDestReg, // xchg GR16, GR16
490 (ops GR16:$src1, GR16:$src2),
491 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
492 def XCHG32rr : I<0x87, MRMDestReg, // xchg GR32, GR32
493 (ops GR32:$src1, GR32:$src2),
494 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
496 def XCHG8mr : I<0x86, MRMDestMem,
497 (ops i8mem:$src1, GR8:$src2),
498 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
499 def XCHG16mr : I<0x87, MRMDestMem,
500 (ops i16mem:$src1, GR16:$src2),
501 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
502 def XCHG32mr : I<0x87, MRMDestMem,
503 (ops i32mem:$src1, GR32:$src2),
504 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
505 def XCHG8rm : I<0x86, MRMSrcMem,
506 (ops GR8:$src1, i8mem:$src2),
507 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
508 def XCHG16rm : I<0x87, MRMSrcMem,
509 (ops GR16:$src1, i16mem:$src2),
510 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
511 def XCHG32rm : I<0x87, MRMSrcMem,
512 (ops GR32:$src1, i32mem:$src2),
513 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
515 def LEA16r : I<0x8D, MRMSrcMem,
516 (ops GR16:$dst, i32mem:$src),
517 "lea{w} {$src|$dst}, {$dst|$src}", []>, OpSize;
518 def LEA32r : I<0x8D, MRMSrcMem,
519 (ops GR32:$dst, lea32mem:$src),
520 "lea{l} {$src|$dst}, {$dst|$src}",
521 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
523 def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}",
525 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
526 def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}",
527 [(X86rep_movs i16)]>,
528 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize;
529 def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsl|rep movsd}",
530 [(X86rep_movs i32)]>,
531 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
533 def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}",
535 Imp<[AL,ECX,EDI], [ECX,EDI]>, REP;
536 def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}",
537 [(X86rep_stos i16)]>,
538 Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize;
539 def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}",
540 [(X86rep_stos i32)]>,
541 Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP;
543 def RDTSC : I<0x31, RawFrm, (ops), "rdtsc", [(X86rdtsc)]>,
544 TB, Imp<[],[RAX,RDX]>;
546 //===----------------------------------------------------------------------===//
547 // Input/Output Instructions...
549 def IN8rr : I<0xEC, RawFrm, (ops),
550 "in{b} {%dx, %al|%AL, %DX}",
551 []>, Imp<[DX], [AL]>;
552 def IN16rr : I<0xED, RawFrm, (ops),
553 "in{w} {%dx, %ax|%AX, %DX}",
554 []>, Imp<[DX], [AX]>, OpSize;
555 def IN32rr : I<0xED, RawFrm, (ops),
556 "in{l} {%dx, %eax|%EAX, %DX}",
557 []>, Imp<[DX],[EAX]>;
559 def IN8ri : Ii8<0xE4, RawFrm, (ops i16i8imm:$port),
560 "in{b} {$port, %al|%AL, $port}",
563 def IN16ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port),
564 "in{w} {$port, %ax|%AX, $port}",
566 Imp<[], [AX]>, OpSize;
567 def IN32ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port),
568 "in{l} {$port, %eax|%EAX, $port}",
572 def OUT8rr : I<0xEE, RawFrm, (ops),
573 "out{b} {%al, %dx|%DX, %AL}",
574 []>, Imp<[DX, AL], []>;
575 def OUT16rr : I<0xEF, RawFrm, (ops),
576 "out{w} {%ax, %dx|%DX, %AX}",
577 []>, Imp<[DX, AX], []>, OpSize;
578 def OUT32rr : I<0xEF, RawFrm, (ops),
579 "out{l} {%eax, %dx|%DX, %EAX}",
580 []>, Imp<[DX, EAX], []>;
582 def OUT8ir : Ii8<0xE6, RawFrm, (ops i16i8imm:$port),
583 "out{b} {%al, $port|$port, %AL}",
586 def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
587 "out{w} {%ax, $port|$port, %AX}",
589 Imp<[AX], []>, OpSize;
590 def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
591 "out{l} {%eax, $port|$port, %EAX}",
595 //===----------------------------------------------------------------------===//
596 // Move Instructions...
598 def MOV8rr : I<0x88, MRMDestReg, (ops GR8 :$dst, GR8 :$src),
599 "mov{b} {$src, $dst|$dst, $src}", []>;
600 def MOV16rr : I<0x89, MRMDestReg, (ops GR16:$dst, GR16:$src),
601 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
602 def MOV32rr : I<0x89, MRMDestReg, (ops GR32:$dst, GR32:$src),
603 "mov{l} {$src, $dst|$dst, $src}", []>;
604 def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops GR8 :$dst, i8imm :$src),
605 "mov{b} {$src, $dst|$dst, $src}",
606 [(set GR8:$dst, imm:$src)]>;
607 def MOV16ri : Ii16<0xB8, AddRegFrm, (ops GR16:$dst, i16imm:$src),
608 "mov{w} {$src, $dst|$dst, $src}",
609 [(set GR16:$dst, imm:$src)]>, OpSize;
610 def MOV32ri : Ii32<0xB8, AddRegFrm, (ops GR32:$dst, i32imm:$src),
611 "mov{l} {$src, $dst|$dst, $src}",
612 [(set GR32:$dst, imm:$src)]>;
613 def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src),
614 "mov{b} {$src, $dst|$dst, $src}",
615 [(store (i8 imm:$src), addr:$dst)]>;
616 def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src),
617 "mov{w} {$src, $dst|$dst, $src}",
618 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
619 def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src),
620 "mov{l} {$src, $dst|$dst, $src}",
621 [(store (i32 imm:$src), addr:$dst)]>;
623 def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src),
624 "mov{b} {$src, $dst|$dst, $src}",
625 [(set GR8:$dst, (load addr:$src))]>;
626 def MOV16rm : I<0x8B, MRMSrcMem, (ops GR16:$dst, i16mem:$src),
627 "mov{w} {$src, $dst|$dst, $src}",
628 [(set GR16:$dst, (load addr:$src))]>, OpSize;
629 def MOV32rm : I<0x8B, MRMSrcMem, (ops GR32:$dst, i32mem:$src),
630 "mov{l} {$src, $dst|$dst, $src}",
631 [(set GR32:$dst, (load addr:$src))]>;
633 def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, GR8 :$src),
634 "mov{b} {$src, $dst|$dst, $src}",
635 [(store GR8:$src, addr:$dst)]>;
636 def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, GR16:$src),
637 "mov{w} {$src, $dst|$dst, $src}",
638 [(store GR16:$src, addr:$dst)]>, OpSize;
639 def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, GR32:$src),
640 "mov{l} {$src, $dst|$dst, $src}",
641 [(store GR32:$src, addr:$dst)]>;
643 //===----------------------------------------------------------------------===//
644 // Fixed-Register Multiplication and Division Instructions...
647 // Extra precision multiplication
648 def MUL8r : I<0xF6, MRM4r, (ops GR8:$src), "mul{b} $src",
649 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
650 // This probably ought to be moved to a def : Pat<> if the
651 // syntax can be accepted.
652 [(set AL, (mul AL, GR8:$src))]>,
653 Imp<[AL],[AX]>; // AL,AH = AL*GR8
654 def MUL16r : I<0xF7, MRM4r, (ops GR16:$src), "mul{w} $src", []>,
655 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16
656 def MUL32r : I<0xF7, MRM4r, (ops GR32:$src), "mul{l} $src", []>,
657 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*GR32
658 def MUL8m : I<0xF6, MRM4m, (ops i8mem :$src),
660 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
661 // This probably ought to be moved to a def : Pat<> if the
662 // syntax can be accepted.
663 [(set AL, (mul AL, (loadi8 addr:$src)))]>,
664 Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
665 def MUL16m : I<0xF7, MRM4m, (ops i16mem:$src),
666 "mul{w} $src", []>, Imp<[AX],[AX,DX]>,
667 OpSize; // AX,DX = AX*[mem16]
668 def MUL32m : I<0xF7, MRM4m, (ops i32mem:$src),
669 "mul{l} $src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32]
671 def IMUL8r : I<0xF6, MRM5r, (ops GR8:$src), "imul{b} $src", []>,
672 Imp<[AL],[AX]>; // AL,AH = AL*GR8
673 def IMUL16r : I<0xF7, MRM5r, (ops GR16:$src), "imul{w} $src", []>,
674 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16
675 def IMUL32r : I<0xF7, MRM5r, (ops GR32:$src), "imul{l} $src", []>,
676 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*GR32
677 def IMUL8m : I<0xF6, MRM5m, (ops i8mem :$src),
678 "imul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
679 def IMUL16m : I<0xF7, MRM5m, (ops i16mem:$src),
680 "imul{w} $src", []>, Imp<[AX],[AX,DX]>,
681 OpSize; // AX,DX = AX*[mem16]
682 def IMUL32m : I<0xF7, MRM5m, (ops i32mem:$src),
684 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
686 // unsigned division/remainder
687 def DIV8r : I<0xF6, MRM6r, (ops GR8:$src), // AX/r8 = AL,AH
688 "div{b} $src", []>, Imp<[AX],[AX]>;
689 def DIV16r : I<0xF7, MRM6r, (ops GR16:$src), // DX:AX/r16 = AX,DX
690 "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
691 def DIV32r : I<0xF7, MRM6r, (ops GR32:$src), // EDX:EAX/r32 = EAX,EDX
692 "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
693 def DIV8m : I<0xF6, MRM6m, (ops i8mem:$src), // AX/[mem8] = AL,AH
694 "div{b} $src", []>, Imp<[AX],[AX]>;
695 def DIV16m : I<0xF7, MRM6m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX
696 "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
697 def DIV32m : I<0xF7, MRM6m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
698 "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
700 // Signed division/remainder.
701 def IDIV8r : I<0xF6, MRM7r, (ops GR8:$src), // AX/r8 = AL,AH
702 "idiv{b} $src", []>, Imp<[AX],[AX]>;
703 def IDIV16r: I<0xF7, MRM7r, (ops GR16:$src), // DX:AX/r16 = AX,DX
704 "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
705 def IDIV32r: I<0xF7, MRM7r, (ops GR32:$src), // EDX:EAX/r32 = EAX,EDX
706 "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
707 def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src), // AX/[mem8] = AL,AH
708 "idiv{b} $src", []>, Imp<[AX],[AX]>;
709 def IDIV16m: I<0xF7, MRM7m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX
710 "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
711 def IDIV32m: I<0xF7, MRM7m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
712 "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
715 //===----------------------------------------------------------------------===//
716 // Two address Instructions...
718 let isTwoAddress = 1 in {
721 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
722 (ops GR16:$dst, GR16:$src1, GR16:$src2),
723 "cmovb {$src2, $dst|$dst, $src2}",
724 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
727 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
728 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
729 "cmovb {$src2, $dst|$dst, $src2}",
730 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
733 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
734 (ops GR32:$dst, GR32:$src1, GR32:$src2),
735 "cmovb {$src2, $dst|$dst, $src2}",
736 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
739 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
740 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
741 "cmovb {$src2, $dst|$dst, $src2}",
742 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
746 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
747 (ops GR16:$dst, GR16:$src1, GR16:$src2),
748 "cmovae {$src2, $dst|$dst, $src2}",
749 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
752 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
753 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
754 "cmovae {$src2, $dst|$dst, $src2}",
755 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
758 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
759 (ops GR32:$dst, GR32:$src1, GR32:$src2),
760 "cmovae {$src2, $dst|$dst, $src2}",
761 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
764 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
765 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
766 "cmovae {$src2, $dst|$dst, $src2}",
767 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
771 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
772 (ops GR16:$dst, GR16:$src1, GR16:$src2),
773 "cmove {$src2, $dst|$dst, $src2}",
774 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
777 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
778 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
779 "cmove {$src2, $dst|$dst, $src2}",
780 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
783 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
784 (ops GR32:$dst, GR32:$src1, GR32:$src2),
785 "cmove {$src2, $dst|$dst, $src2}",
786 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
789 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
790 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
791 "cmove {$src2, $dst|$dst, $src2}",
792 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
796 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
797 (ops GR16:$dst, GR16:$src1, GR16:$src2),
798 "cmovne {$src2, $dst|$dst, $src2}",
799 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
802 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
803 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
804 "cmovne {$src2, $dst|$dst, $src2}",
805 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
808 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
809 (ops GR32:$dst, GR32:$src1, GR32:$src2),
810 "cmovne {$src2, $dst|$dst, $src2}",
811 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
814 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
815 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
816 "cmovne {$src2, $dst|$dst, $src2}",
817 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
821 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
822 (ops GR16:$dst, GR16:$src1, GR16:$src2),
823 "cmovbe {$src2, $dst|$dst, $src2}",
824 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
827 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
828 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
829 "cmovbe {$src2, $dst|$dst, $src2}",
830 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
833 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
834 (ops GR32:$dst, GR32:$src1, GR32:$src2),
835 "cmovbe {$src2, $dst|$dst, $src2}",
836 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
839 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
840 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
841 "cmovbe {$src2, $dst|$dst, $src2}",
842 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
846 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
847 (ops GR16:$dst, GR16:$src1, GR16:$src2),
848 "cmova {$src2, $dst|$dst, $src2}",
849 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
852 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
853 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
854 "cmova {$src2, $dst|$dst, $src2}",
855 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
858 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
859 (ops GR32:$dst, GR32:$src1, GR32:$src2),
860 "cmova {$src2, $dst|$dst, $src2}",
861 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
864 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
865 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
866 "cmova {$src2, $dst|$dst, $src2}",
867 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
871 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
872 (ops GR16:$dst, GR16:$src1, GR16:$src2),
873 "cmovl {$src2, $dst|$dst, $src2}",
874 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
877 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
878 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
879 "cmovl {$src2, $dst|$dst, $src2}",
880 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
883 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
884 (ops GR32:$dst, GR32:$src1, GR32:$src2),
885 "cmovl {$src2, $dst|$dst, $src2}",
886 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
889 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
890 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
891 "cmovl {$src2, $dst|$dst, $src2}",
892 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
896 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
897 (ops GR16:$dst, GR16:$src1, GR16:$src2),
898 "cmovge {$src2, $dst|$dst, $src2}",
899 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
902 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
903 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
904 "cmovge {$src2, $dst|$dst, $src2}",
905 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
908 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
909 (ops GR32:$dst, GR32:$src1, GR32:$src2),
910 "cmovge {$src2, $dst|$dst, $src2}",
911 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
914 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
915 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
916 "cmovge {$src2, $dst|$dst, $src2}",
917 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
921 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
922 (ops GR16:$dst, GR16:$src1, GR16:$src2),
923 "cmovle {$src2, $dst|$dst, $src2}",
924 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
927 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
928 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
929 "cmovle {$src2, $dst|$dst, $src2}",
930 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
933 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
934 (ops GR32:$dst, GR32:$src1, GR32:$src2),
935 "cmovle {$src2, $dst|$dst, $src2}",
936 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
939 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
940 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
941 "cmovle {$src2, $dst|$dst, $src2}",
942 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
946 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
947 (ops GR16:$dst, GR16:$src1, GR16:$src2),
948 "cmovg {$src2, $dst|$dst, $src2}",
949 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
952 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
953 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
954 "cmovg {$src2, $dst|$dst, $src2}",
955 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
958 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
959 (ops GR32:$dst, GR32:$src1, GR32:$src2),
960 "cmovg {$src2, $dst|$dst, $src2}",
961 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
964 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
965 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
966 "cmovg {$src2, $dst|$dst, $src2}",
967 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
971 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
972 (ops GR16:$dst, GR16:$src1, GR16:$src2),
973 "cmovs {$src2, $dst|$dst, $src2}",
974 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
977 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
978 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
979 "cmovs {$src2, $dst|$dst, $src2}",
980 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
983 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
984 (ops GR32:$dst, GR32:$src1, GR32:$src2),
985 "cmovs {$src2, $dst|$dst, $src2}",
986 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
989 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
990 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
991 "cmovs {$src2, $dst|$dst, $src2}",
992 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
996 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
997 (ops GR16:$dst, GR16:$src1, GR16:$src2),
998 "cmovns {$src2, $dst|$dst, $src2}",
999 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1002 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1003 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1004 "cmovns {$src2, $dst|$dst, $src2}",
1005 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1008 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1009 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1010 "cmovns {$src2, $dst|$dst, $src2}",
1011 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1014 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1015 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1016 "cmovns {$src2, $dst|$dst, $src2}",
1017 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1021 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1022 (ops GR16:$dst, GR16:$src1, GR16:$src2),
1023 "cmovp {$src2, $dst|$dst, $src2}",
1024 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1027 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1028 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1029 "cmovp {$src2, $dst|$dst, $src2}",
1030 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1033 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1034 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1035 "cmovp {$src2, $dst|$dst, $src2}",
1036 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1039 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1040 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1041 "cmovp {$src2, $dst|$dst, $src2}",
1042 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1046 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1047 (ops GR16:$dst, GR16:$src1, GR16:$src2),
1048 "cmovnp {$src2, $dst|$dst, $src2}",
1049 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1052 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1053 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1054 "cmovnp {$src2, $dst|$dst, $src2}",
1055 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1058 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1059 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1060 "cmovnp {$src2, $dst|$dst, $src2}",
1061 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1064 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1065 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1066 "cmovnp {$src2, $dst|$dst, $src2}",
1067 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1072 // unary instructions
1073 let CodeSize = 2 in {
1074 def NEG8r : I<0xF6, MRM3r, (ops GR8 :$dst, GR8 :$src), "neg{b} $dst",
1075 [(set GR8:$dst, (ineg GR8:$src))]>;
1076 def NEG16r : I<0xF7, MRM3r, (ops GR16:$dst, GR16:$src), "neg{w} $dst",
1077 [(set GR16:$dst, (ineg GR16:$src))]>, OpSize;
1078 def NEG32r : I<0xF7, MRM3r, (ops GR32:$dst, GR32:$src), "neg{l} $dst",
1079 [(set GR32:$dst, (ineg GR32:$src))]>;
1080 let isTwoAddress = 0 in {
1081 def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst",
1082 [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
1083 def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg{w} $dst",
1084 [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1085 def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg{l} $dst",
1086 [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
1090 def NOT8r : I<0xF6, MRM2r, (ops GR8 :$dst, GR8 :$src), "not{b} $dst",
1091 [(set GR8:$dst, (not GR8:$src))]>;
1092 def NOT16r : I<0xF7, MRM2r, (ops GR16:$dst, GR16:$src), "not{w} $dst",
1093 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1094 def NOT32r : I<0xF7, MRM2r, (ops GR32:$dst, GR32:$src), "not{l} $dst",
1095 [(set GR32:$dst, (not GR32:$src))]>;
1096 let isTwoAddress = 0 in {
1097 def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst",
1098 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1099 def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not{w} $dst",
1100 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1101 def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst",
1102 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1106 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1108 def INC8r : I<0xFE, MRM0r, (ops GR8 :$dst, GR8 :$src), "inc{b} $dst",
1109 [(set GR8:$dst, (add GR8:$src, 1))]>;
1110 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1111 def INC16r : I<0x40, AddRegFrm, (ops GR16:$dst, GR16:$src), "inc{w} $dst",
1112 [(set GR16:$dst, (add GR16:$src, 1))]>,
1113 OpSize, Requires<[In32BitMode]>;
1114 def INC32r : I<0x40, AddRegFrm, (ops GR32:$dst, GR32:$src), "inc{l} $dst",
1115 [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>;
1117 let isTwoAddress = 0, CodeSize = 2 in {
1118 def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst",
1119 [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
1120 def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst",
1121 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>, OpSize;
1122 def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst",
1123 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>;
1127 def DEC8r : I<0xFE, MRM1r, (ops GR8 :$dst, GR8 :$src), "dec{b} $dst",
1128 [(set GR8:$dst, (add GR8:$src, -1))]>;
1129 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1130 def DEC16r : I<0x48, AddRegFrm, (ops GR16:$dst, GR16:$src), "dec{w} $dst",
1131 [(set GR16:$dst, (add GR16:$src, -1))]>,
1132 OpSize, Requires<[In32BitMode]>;
1133 def DEC32r : I<0x48, AddRegFrm, (ops GR32:$dst, GR32:$src), "dec{l} $dst",
1134 [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>;
1137 let isTwoAddress = 0, CodeSize = 2 in {
1138 def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst",
1139 [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
1140 def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst",
1141 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>, OpSize;
1142 def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst",
1143 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>;
1146 // Logical operators...
1147 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1148 def AND8rr : I<0x20, MRMDestReg,
1149 (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1150 "and{b} {$src2, $dst|$dst, $src2}",
1151 [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>;
1152 def AND16rr : I<0x21, MRMDestReg,
1153 (ops GR16:$dst, GR16:$src1, GR16:$src2),
1154 "and{w} {$src2, $dst|$dst, $src2}",
1155 [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize;
1156 def AND32rr : I<0x21, MRMDestReg,
1157 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1158 "and{l} {$src2, $dst|$dst, $src2}",
1159 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
1162 def AND8rm : I<0x22, MRMSrcMem,
1163 (ops GR8 :$dst, GR8 :$src1, i8mem :$src2),
1164 "and{b} {$src2, $dst|$dst, $src2}",
1165 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>;
1166 def AND16rm : I<0x23, MRMSrcMem,
1167 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1168 "and{w} {$src2, $dst|$dst, $src2}",
1169 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize;
1170 def AND32rm : I<0x23, MRMSrcMem,
1171 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1172 "and{l} {$src2, $dst|$dst, $src2}",
1173 [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>;
1175 def AND8ri : Ii8<0x80, MRM4r,
1176 (ops GR8 :$dst, GR8 :$src1, i8imm :$src2),
1177 "and{b} {$src2, $dst|$dst, $src2}",
1178 [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>;
1179 def AND16ri : Ii16<0x81, MRM4r,
1180 (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1181 "and{w} {$src2, $dst|$dst, $src2}",
1182 [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize;
1183 def AND32ri : Ii32<0x81, MRM4r,
1184 (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1185 "and{l} {$src2, $dst|$dst, $src2}",
1186 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
1187 def AND16ri8 : Ii8<0x83, MRM4r,
1188 (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1189 "and{w} {$src2, $dst|$dst, $src2}",
1190 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>,
1192 def AND32ri8 : Ii8<0x83, MRM4r,
1193 (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1194 "and{l} {$src2, $dst|$dst, $src2}",
1195 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>;
1197 let isTwoAddress = 0 in {
1198 def AND8mr : I<0x20, MRMDestMem,
1199 (ops i8mem :$dst, GR8 :$src),
1200 "and{b} {$src, $dst|$dst, $src}",
1201 [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>;
1202 def AND16mr : I<0x21, MRMDestMem,
1203 (ops i16mem:$dst, GR16:$src),
1204 "and{w} {$src, $dst|$dst, $src}",
1205 [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>,
1207 def AND32mr : I<0x21, MRMDestMem,
1208 (ops i32mem:$dst, GR32:$src),
1209 "and{l} {$src, $dst|$dst, $src}",
1210 [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>;
1211 def AND8mi : Ii8<0x80, MRM4m,
1212 (ops i8mem :$dst, i8imm :$src),
1213 "and{b} {$src, $dst|$dst, $src}",
1214 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1215 def AND16mi : Ii16<0x81, MRM4m,
1216 (ops i16mem:$dst, i16imm:$src),
1217 "and{w} {$src, $dst|$dst, $src}",
1218 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1220 def AND32mi : Ii32<0x81, MRM4m,
1221 (ops i32mem:$dst, i32imm:$src),
1222 "and{l} {$src, $dst|$dst, $src}",
1223 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1224 def AND16mi8 : Ii8<0x83, MRM4m,
1225 (ops i16mem:$dst, i16i8imm :$src),
1226 "and{w} {$src, $dst|$dst, $src}",
1227 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1229 def AND32mi8 : Ii8<0x83, MRM4m,
1230 (ops i32mem:$dst, i32i8imm :$src),
1231 "and{l} {$src, $dst|$dst, $src}",
1232 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1236 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1237 def OR8rr : I<0x08, MRMDestReg, (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1238 "or{b} {$src2, $dst|$dst, $src2}",
1239 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
1240 def OR16rr : I<0x09, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1241 "or{w} {$src2, $dst|$dst, $src2}",
1242 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize;
1243 def OR32rr : I<0x09, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1244 "or{l} {$src2, $dst|$dst, $src2}",
1245 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
1247 def OR8rm : I<0x0A, MRMSrcMem , (ops GR8 :$dst, GR8 :$src1, i8mem :$src2),
1248 "or{b} {$src2, $dst|$dst, $src2}",
1249 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
1250 def OR16rm : I<0x0B, MRMSrcMem , (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1251 "or{w} {$src2, $dst|$dst, $src2}",
1252 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize;
1253 def OR32rm : I<0x0B, MRMSrcMem , (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1254 "or{l} {$src2, $dst|$dst, $src2}",
1255 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>;
1257 def OR8ri : Ii8 <0x80, MRM1r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1258 "or{b} {$src2, $dst|$dst, $src2}",
1259 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
1260 def OR16ri : Ii16<0x81, MRM1r, (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1261 "or{w} {$src2, $dst|$dst, $src2}",
1262 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize;
1263 def OR32ri : Ii32<0x81, MRM1r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1264 "or{l} {$src2, $dst|$dst, $src2}",
1265 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
1267 def OR16ri8 : Ii8<0x83, MRM1r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1268 "or{w} {$src2, $dst|$dst, $src2}",
1269 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1270 def OR32ri8 : Ii8<0x83, MRM1r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1271 "or{l} {$src2, $dst|$dst, $src2}",
1272 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>;
1273 let isTwoAddress = 0 in {
1274 def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, GR8:$src),
1275 "or{b} {$src, $dst|$dst, $src}",
1276 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
1277 def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, GR16:$src),
1278 "or{w} {$src, $dst|$dst, $src}",
1279 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize;
1280 def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, GR32:$src),
1281 "or{l} {$src, $dst|$dst, $src}",
1282 [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>;
1283 def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src),
1284 "or{b} {$src, $dst|$dst, $src}",
1285 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1286 def OR16mi : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src),
1287 "or{w} {$src, $dst|$dst, $src}",
1288 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1290 def OR32mi : Ii32<0x81, MRM1m, (ops i32mem:$dst, i32imm:$src),
1291 "or{l} {$src, $dst|$dst, $src}",
1292 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1293 def OR16mi8 : Ii8<0x83, MRM1m, (ops i16mem:$dst, i16i8imm:$src),
1294 "or{w} {$src, $dst|$dst, $src}",
1295 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1297 def OR32mi8 : Ii8<0x83, MRM1m, (ops i32mem:$dst, i32i8imm:$src),
1298 "or{l} {$src, $dst|$dst, $src}",
1299 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1303 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1304 def XOR8rr : I<0x30, MRMDestReg,
1305 (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1306 "xor{b} {$src2, $dst|$dst, $src2}",
1307 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>;
1308 def XOR16rr : I<0x31, MRMDestReg,
1309 (ops GR16:$dst, GR16:$src1, GR16:$src2),
1310 "xor{w} {$src2, $dst|$dst, $src2}",
1311 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize;
1312 def XOR32rr : I<0x31, MRMDestReg,
1313 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1314 "xor{l} {$src2, $dst|$dst, $src2}",
1315 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
1318 def XOR8rm : I<0x32, MRMSrcMem ,
1319 (ops GR8 :$dst, GR8:$src1, i8mem :$src2),
1320 "xor{b} {$src2, $dst|$dst, $src2}",
1321 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>;
1322 def XOR16rm : I<0x33, MRMSrcMem ,
1323 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1324 "xor{w} {$src2, $dst|$dst, $src2}",
1325 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>, OpSize;
1326 def XOR32rm : I<0x33, MRMSrcMem ,
1327 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1328 "xor{l} {$src2, $dst|$dst, $src2}",
1329 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>;
1331 def XOR8ri : Ii8<0x80, MRM6r,
1332 (ops GR8:$dst, GR8:$src1, i8imm:$src2),
1333 "xor{b} {$src2, $dst|$dst, $src2}",
1334 [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>;
1335 def XOR16ri : Ii16<0x81, MRM6r,
1336 (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1337 "xor{w} {$src2, $dst|$dst, $src2}",
1338 [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize;
1339 def XOR32ri : Ii32<0x81, MRM6r,
1340 (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1341 "xor{l} {$src2, $dst|$dst, $src2}",
1342 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
1343 def XOR16ri8 : Ii8<0x83, MRM6r,
1344 (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1345 "xor{w} {$src2, $dst|$dst, $src2}",
1346 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>,
1348 def XOR32ri8 : Ii8<0x83, MRM6r,
1349 (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1350 "xor{l} {$src2, $dst|$dst, $src2}",
1351 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>;
1352 let isTwoAddress = 0 in {
1353 def XOR8mr : I<0x30, MRMDestMem,
1354 (ops i8mem :$dst, GR8 :$src),
1355 "xor{b} {$src, $dst|$dst, $src}",
1356 [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>;
1357 def XOR16mr : I<0x31, MRMDestMem,
1358 (ops i16mem:$dst, GR16:$src),
1359 "xor{w} {$src, $dst|$dst, $src}",
1360 [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>,
1362 def XOR32mr : I<0x31, MRMDestMem,
1363 (ops i32mem:$dst, GR32:$src),
1364 "xor{l} {$src, $dst|$dst, $src}",
1365 [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>;
1366 def XOR8mi : Ii8<0x80, MRM6m,
1367 (ops i8mem :$dst, i8imm :$src),
1368 "xor{b} {$src, $dst|$dst, $src}",
1369 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1370 def XOR16mi : Ii16<0x81, MRM6m,
1371 (ops i16mem:$dst, i16imm:$src),
1372 "xor{w} {$src, $dst|$dst, $src}",
1373 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1375 def XOR32mi : Ii32<0x81, MRM6m,
1376 (ops i32mem:$dst, i32imm:$src),
1377 "xor{l} {$src, $dst|$dst, $src}",
1378 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1379 def XOR16mi8 : Ii8<0x83, MRM6m,
1380 (ops i16mem:$dst, i16i8imm :$src),
1381 "xor{w} {$src, $dst|$dst, $src}",
1382 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1384 def XOR32mi8 : Ii8<0x83, MRM6m,
1385 (ops i32mem:$dst, i32i8imm :$src),
1386 "xor{l} {$src, $dst|$dst, $src}",
1387 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1390 // Shift instructions
1391 def SHL8rCL : I<0xD2, MRM4r, (ops GR8 :$dst, GR8 :$src),
1392 "shl{b} {%cl, $dst|$dst, %CL}",
1393 [(set GR8:$dst, (shl GR8:$src, CL))]>, Imp<[CL],[]>;
1394 def SHL16rCL : I<0xD3, MRM4r, (ops GR16:$dst, GR16:$src),
1395 "shl{w} {%cl, $dst|$dst, %CL}",
1396 [(set GR16:$dst, (shl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1397 def SHL32rCL : I<0xD3, MRM4r, (ops GR32:$dst, GR32:$src),
1398 "shl{l} {%cl, $dst|$dst, %CL}",
1399 [(set GR32:$dst, (shl GR32:$src, CL))]>, Imp<[CL],[]>;
1401 def SHL8ri : Ii8<0xC0, MRM4r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1402 "shl{b} {$src2, $dst|$dst, $src2}",
1403 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1404 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1405 def SHL16ri : Ii8<0xC1, MRM4r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1406 "shl{w} {$src2, $dst|$dst, $src2}",
1407 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1408 def SHL32ri : Ii8<0xC1, MRM4r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1409 "shl{l} {$src2, $dst|$dst, $src2}",
1410 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1413 // Shift left by one. Not used because (add x, x) is slightly cheaper.
1414 def SHL8r1 : I<0xD0, MRM4r, (ops GR8 :$dst, GR8 :$src1),
1416 def SHL16r1 : I<0xD1, MRM4r, (ops GR16:$dst, GR16:$src1),
1417 "shl{w} $dst", []>, OpSize;
1418 def SHL32r1 : I<0xD1, MRM4r, (ops GR32:$dst, GR32:$src1),
1421 let isTwoAddress = 0 in {
1422 def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst),
1423 "shl{b} {%cl, $dst|$dst, %CL}",
1424 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>,
1426 def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst),
1427 "shl{w} {%cl, $dst|$dst, %CL}",
1428 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>,
1429 Imp<[CL],[]>, OpSize;
1430 def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst),
1431 "shl{l} {%cl, $dst|$dst, %CL}",
1432 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>,
1434 def SHL8mi : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src),
1435 "shl{b} {$src, $dst|$dst, $src}",
1436 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1437 def SHL16mi : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src),
1438 "shl{w} {$src, $dst|$dst, $src}",
1439 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1441 def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src),
1442 "shl{l} {$src, $dst|$dst, $src}",
1443 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1446 def SHL8m1 : I<0xD0, MRM4m, (ops i8mem :$dst),
1448 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1449 def SHL16m1 : I<0xD1, MRM4m, (ops i16mem:$dst),
1451 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1453 def SHL32m1 : I<0xD1, MRM4m, (ops i32mem:$dst),
1455 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1458 def SHR8rCL : I<0xD2, MRM5r, (ops GR8 :$dst, GR8 :$src),
1459 "shr{b} {%cl, $dst|$dst, %CL}",
1460 [(set GR8:$dst, (srl GR8:$src, CL))]>, Imp<[CL],[]>;
1461 def SHR16rCL : I<0xD3, MRM5r, (ops GR16:$dst, GR16:$src),
1462 "shr{w} {%cl, $dst|$dst, %CL}",
1463 [(set GR16:$dst, (srl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1464 def SHR32rCL : I<0xD3, MRM5r, (ops GR32:$dst, GR32:$src),
1465 "shr{l} {%cl, $dst|$dst, %CL}",
1466 [(set GR32:$dst, (srl GR32:$src, CL))]>, Imp<[CL],[]>;
1468 def SHR8ri : Ii8<0xC0, MRM5r, (ops GR8:$dst, GR8:$src1, i8imm:$src2),
1469 "shr{b} {$src2, $dst|$dst, $src2}",
1470 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1471 def SHR16ri : Ii8<0xC1, MRM5r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1472 "shr{w} {$src2, $dst|$dst, $src2}",
1473 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1474 def SHR32ri : Ii8<0xC1, MRM5r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1475 "shr{l} {$src2, $dst|$dst, $src2}",
1476 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1479 def SHR8r1 : I<0xD0, MRM5r, (ops GR8:$dst, GR8:$src1),
1481 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1482 def SHR16r1 : I<0xD1, MRM5r, (ops GR16:$dst, GR16:$src1),
1484 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1485 def SHR32r1 : I<0xD1, MRM5r, (ops GR32:$dst, GR32:$src1),
1487 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1489 let isTwoAddress = 0 in {
1490 def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst),
1491 "shr{b} {%cl, $dst|$dst, %CL}",
1492 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>,
1494 def SHR16mCL : I<0xD3, MRM5m, (ops i16mem:$dst),
1495 "shr{w} {%cl, $dst|$dst, %CL}",
1496 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1497 Imp<[CL],[]>, OpSize;
1498 def SHR32mCL : I<0xD3, MRM5m, (ops i32mem:$dst),
1499 "shr{l} {%cl, $dst|$dst, %CL}",
1500 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>,
1502 def SHR8mi : Ii8<0xC0, MRM5m, (ops i8mem :$dst, i8imm:$src),
1503 "shr{b} {$src, $dst|$dst, $src}",
1504 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1505 def SHR16mi : Ii8<0xC1, MRM5m, (ops i16mem:$dst, i8imm:$src),
1506 "shr{w} {$src, $dst|$dst, $src}",
1507 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1509 def SHR32mi : Ii8<0xC1, MRM5m, (ops i32mem:$dst, i8imm:$src),
1510 "shr{l} {$src, $dst|$dst, $src}",
1511 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1514 def SHR8m1 : I<0xD0, MRM5m, (ops i8mem :$dst),
1516 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1517 def SHR16m1 : I<0xD1, MRM5m, (ops i16mem:$dst),
1519 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1520 def SHR32m1 : I<0xD1, MRM5m, (ops i32mem:$dst),
1522 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1525 def SAR8rCL : I<0xD2, MRM7r, (ops GR8 :$dst, GR8 :$src),
1526 "sar{b} {%cl, $dst|$dst, %CL}",
1527 [(set GR8:$dst, (sra GR8:$src, CL))]>, Imp<[CL],[]>;
1528 def SAR16rCL : I<0xD3, MRM7r, (ops GR16:$dst, GR16:$src),
1529 "sar{w} {%cl, $dst|$dst, %CL}",
1530 [(set GR16:$dst, (sra GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1531 def SAR32rCL : I<0xD3, MRM7r, (ops GR32:$dst, GR32:$src),
1532 "sar{l} {%cl, $dst|$dst, %CL}",
1533 [(set GR32:$dst, (sra GR32:$src, CL))]>, Imp<[CL],[]>;
1535 def SAR8ri : Ii8<0xC0, MRM7r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1536 "sar{b} {$src2, $dst|$dst, $src2}",
1537 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1538 def SAR16ri : Ii8<0xC1, MRM7r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1539 "sar{w} {$src2, $dst|$dst, $src2}",
1540 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1542 def SAR32ri : Ii8<0xC1, MRM7r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1543 "sar{l} {$src2, $dst|$dst, $src2}",
1544 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1547 def SAR8r1 : I<0xD0, MRM7r, (ops GR8 :$dst, GR8 :$src1),
1549 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1550 def SAR16r1 : I<0xD1, MRM7r, (ops GR16:$dst, GR16:$src1),
1552 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1553 def SAR32r1 : I<0xD1, MRM7r, (ops GR32:$dst, GR32:$src1),
1555 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1557 let isTwoAddress = 0 in {
1558 def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst),
1559 "sar{b} {%cl, $dst|$dst, %CL}",
1560 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>,
1562 def SAR16mCL : I<0xD3, MRM7m, (ops i16mem:$dst),
1563 "sar{w} {%cl, $dst|$dst, %CL}",
1564 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>,
1565 Imp<[CL],[]>, OpSize;
1566 def SAR32mCL : I<0xD3, MRM7m, (ops i32mem:$dst),
1567 "sar{l} {%cl, $dst|$dst, %CL}",
1568 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>,
1570 def SAR8mi : Ii8<0xC0, MRM7m, (ops i8mem :$dst, i8imm:$src),
1571 "sar{b} {$src, $dst|$dst, $src}",
1572 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1573 def SAR16mi : Ii8<0xC1, MRM7m, (ops i16mem:$dst, i8imm:$src),
1574 "sar{w} {$src, $dst|$dst, $src}",
1575 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1577 def SAR32mi : Ii8<0xC1, MRM7m, (ops i32mem:$dst, i8imm:$src),
1578 "sar{l} {$src, $dst|$dst, $src}",
1579 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1582 def SAR8m1 : I<0xD0, MRM7m, (ops i8mem :$dst),
1584 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1585 def SAR16m1 : I<0xD1, MRM7m, (ops i16mem:$dst),
1587 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1589 def SAR32m1 : I<0xD1, MRM7m, (ops i32mem:$dst),
1591 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1594 // Rotate instructions
1595 // FIXME: provide shorter instructions when imm8 == 1
1596 def ROL8rCL : I<0xD2, MRM0r, (ops GR8 :$dst, GR8 :$src),
1597 "rol{b} {%cl, $dst|$dst, %CL}",
1598 [(set GR8:$dst, (rotl GR8:$src, CL))]>, Imp<[CL],[]>;
1599 def ROL16rCL : I<0xD3, MRM0r, (ops GR16:$dst, GR16:$src),
1600 "rol{w} {%cl, $dst|$dst, %CL}",
1601 [(set GR16:$dst, (rotl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1602 def ROL32rCL : I<0xD3, MRM0r, (ops GR32:$dst, GR32:$src),
1603 "rol{l} {%cl, $dst|$dst, %CL}",
1604 [(set GR32:$dst, (rotl GR32:$src, CL))]>, Imp<[CL],[]>;
1606 def ROL8ri : Ii8<0xC0, MRM0r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1607 "rol{b} {$src2, $dst|$dst, $src2}",
1608 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1609 def ROL16ri : Ii8<0xC1, MRM0r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1610 "rol{w} {$src2, $dst|$dst, $src2}",
1611 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1612 def ROL32ri : Ii8<0xC1, MRM0r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1613 "rol{l} {$src2, $dst|$dst, $src2}",
1614 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1617 def ROL8r1 : I<0xD0, MRM0r, (ops GR8 :$dst, GR8 :$src1),
1619 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1620 def ROL16r1 : I<0xD1, MRM0r, (ops GR16:$dst, GR16:$src1),
1622 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1623 def ROL32r1 : I<0xD1, MRM0r, (ops GR32:$dst, GR32:$src1),
1625 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1627 let isTwoAddress = 0 in {
1628 def ROL8mCL : I<0xD2, MRM0m, (ops i8mem :$dst),
1629 "rol{b} {%cl, $dst|$dst, %CL}",
1630 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>,
1632 def ROL16mCL : I<0xD3, MRM0m, (ops i16mem:$dst),
1633 "rol{w} {%cl, $dst|$dst, %CL}",
1634 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>,
1635 Imp<[CL],[]>, OpSize;
1636 def ROL32mCL : I<0xD3, MRM0m, (ops i32mem:$dst),
1637 "rol{l} {%cl, $dst|$dst, %CL}",
1638 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>,
1640 def ROL8mi : Ii8<0xC0, MRM0m, (ops i8mem :$dst, i8imm:$src),
1641 "rol{b} {$src, $dst|$dst, $src}",
1642 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1643 def ROL16mi : Ii8<0xC1, MRM0m, (ops i16mem:$dst, i8imm:$src),
1644 "rol{w} {$src, $dst|$dst, $src}",
1645 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1647 def ROL32mi : Ii8<0xC1, MRM0m, (ops i32mem:$dst, i8imm:$src),
1648 "rol{l} {$src, $dst|$dst, $src}",
1649 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1652 def ROL8m1 : I<0xD0, MRM0m, (ops i8mem :$dst),
1654 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1655 def ROL16m1 : I<0xD1, MRM0m, (ops i16mem:$dst),
1657 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1659 def ROL32m1 : I<0xD1, MRM0m, (ops i32mem:$dst),
1661 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1664 def ROR8rCL : I<0xD2, MRM1r, (ops GR8 :$dst, GR8 :$src),
1665 "ror{b} {%cl, $dst|$dst, %CL}",
1666 [(set GR8:$dst, (rotr GR8:$src, CL))]>, Imp<[CL],[]>;
1667 def ROR16rCL : I<0xD3, MRM1r, (ops GR16:$dst, GR16:$src),
1668 "ror{w} {%cl, $dst|$dst, %CL}",
1669 [(set GR16:$dst, (rotr GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1670 def ROR32rCL : I<0xD3, MRM1r, (ops GR32:$dst, GR32:$src),
1671 "ror{l} {%cl, $dst|$dst, %CL}",
1672 [(set GR32:$dst, (rotr GR32:$src, CL))]>, Imp<[CL],[]>;
1674 def ROR8ri : Ii8<0xC0, MRM1r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1675 "ror{b} {$src2, $dst|$dst, $src2}",
1676 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
1677 def ROR16ri : Ii8<0xC1, MRM1r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1678 "ror{w} {$src2, $dst|$dst, $src2}",
1679 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1680 def ROR32ri : Ii8<0xC1, MRM1r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1681 "ror{l} {$src2, $dst|$dst, $src2}",
1682 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
1685 def ROR8r1 : I<0xD0, MRM1r, (ops GR8 :$dst, GR8 :$src1),
1687 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
1688 def ROR16r1 : I<0xD1, MRM1r, (ops GR16:$dst, GR16:$src1),
1690 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
1691 def ROR32r1 : I<0xD1, MRM1r, (ops GR32:$dst, GR32:$src1),
1693 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
1695 let isTwoAddress = 0 in {
1696 def ROR8mCL : I<0xD2, MRM1m, (ops i8mem :$dst),
1697 "ror{b} {%cl, $dst|$dst, %CL}",
1698 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>,
1700 def ROR16mCL : I<0xD3, MRM1m, (ops i16mem:$dst),
1701 "ror{w} {%cl, $dst|$dst, %CL}",
1702 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>,
1703 Imp<[CL],[]>, OpSize;
1704 def ROR32mCL : I<0xD3, MRM1m, (ops i32mem:$dst),
1705 "ror{l} {%cl, $dst|$dst, %CL}",
1706 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>,
1708 def ROR8mi : Ii8<0xC0, MRM1m, (ops i8mem :$dst, i8imm:$src),
1709 "ror{b} {$src, $dst|$dst, $src}",
1710 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1711 def ROR16mi : Ii8<0xC1, MRM1m, (ops i16mem:$dst, i8imm:$src),
1712 "ror{w} {$src, $dst|$dst, $src}",
1713 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1715 def ROR32mi : Ii8<0xC1, MRM1m, (ops i32mem:$dst, i8imm:$src),
1716 "ror{l} {$src, $dst|$dst, $src}",
1717 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1720 def ROR8m1 : I<0xD0, MRM1m, (ops i8mem :$dst),
1722 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1723 def ROR16m1 : I<0xD1, MRM1m, (ops i16mem:$dst),
1725 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1727 def ROR32m1 : I<0xD1, MRM1m, (ops i32mem:$dst),
1729 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1734 // Double shift instructions (generalizations of rotate)
1735 def SHLD32rrCL : I<0xA5, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1736 "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1737 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>,
1739 def SHRD32rrCL : I<0xAD, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1740 "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1741 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>,
1743 def SHLD16rrCL : I<0xA5, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1744 "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1745 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
1746 Imp<[CL],[]>, TB, OpSize;
1747 def SHRD16rrCL : I<0xAD, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1748 "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1749 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
1750 Imp<[CL],[]>, TB, OpSize;
1752 let isCommutable = 1 in { // These instructions commute to each other.
1753 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
1754 (ops GR32:$dst, GR32:$src1, GR32:$src2, i8imm:$src3),
1755 "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1756 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
1759 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
1760 (ops GR32:$dst, GR32:$src1, GR32:$src2, i8imm:$src3),
1761 "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1762 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
1765 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
1766 (ops GR16:$dst, GR16:$src1, GR16:$src2, i8imm:$src3),
1767 "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1768 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
1771 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
1772 (ops GR16:$dst, GR16:$src1, GR16:$src2, i8imm:$src3),
1773 "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1774 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
1779 let isTwoAddress = 0 in {
1780 def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1781 "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1782 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
1785 def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1786 "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1787 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
1790 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
1791 (ops i32mem:$dst, GR32:$src2, i8imm:$src3),
1792 "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1793 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
1794 (i8 imm:$src3)), addr:$dst)]>,
1796 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
1797 (ops i32mem:$dst, GR32:$src2, i8imm:$src3),
1798 "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1799 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
1800 (i8 imm:$src3)), addr:$dst)]>,
1803 def SHLD16mrCL : I<0xA5, MRMDestMem, (ops i16mem:$dst, GR16:$src2),
1804 "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1805 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
1807 Imp<[CL],[]>, TB, OpSize;
1808 def SHRD16mrCL : I<0xAD, MRMDestMem, (ops i16mem:$dst, GR16:$src2),
1809 "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1810 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
1812 Imp<[CL],[]>, TB, OpSize;
1813 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
1814 (ops i16mem:$dst, GR16:$src2, i8imm:$src3),
1815 "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1816 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
1817 (i8 imm:$src3)), addr:$dst)]>,
1819 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
1820 (ops i16mem:$dst, GR16:$src2, i8imm:$src3),
1821 "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1822 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
1823 (i8 imm:$src3)), addr:$dst)]>,
1829 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1830 def ADD8rr : I<0x00, MRMDestReg, (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1831 "add{b} {$src2, $dst|$dst, $src2}",
1832 [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>;
1833 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1834 def ADD16rr : I<0x01, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1835 "add{w} {$src2, $dst|$dst, $src2}",
1836 [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize;
1837 def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1838 "add{l} {$src2, $dst|$dst, $src2}",
1839 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
1840 } // end isConvertibleToThreeAddress
1841 } // end isCommutable
1842 def ADD8rm : I<0x02, MRMSrcMem, (ops GR8 :$dst, GR8 :$src1, i8mem :$src2),
1843 "add{b} {$src2, $dst|$dst, $src2}",
1844 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>;
1845 def ADD16rm : I<0x03, MRMSrcMem, (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1846 "add{w} {$src2, $dst|$dst, $src2}",
1847 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>, OpSize;
1848 def ADD32rm : I<0x03, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1849 "add{l} {$src2, $dst|$dst, $src2}",
1850 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>;
1852 def ADD8ri : Ii8<0x80, MRM0r, (ops GR8:$dst, GR8:$src1, i8imm:$src2),
1853 "add{b} {$src2, $dst|$dst, $src2}",
1854 [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>;
1856 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1857 def ADD16ri : Ii16<0x81, MRM0r, (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1858 "add{w} {$src2, $dst|$dst, $src2}",
1859 [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize;
1860 def ADD32ri : Ii32<0x81, MRM0r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1861 "add{l} {$src2, $dst|$dst, $src2}",
1862 [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>;
1863 def ADD16ri8 : Ii8<0x83, MRM0r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1864 "add{w} {$src2, $dst|$dst, $src2}",
1865 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>,
1867 def ADD32ri8 : Ii8<0x83, MRM0r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1868 "add{l} {$src2, $dst|$dst, $src2}",
1869 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>;
1872 let isTwoAddress = 0 in {
1873 def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, GR8 :$src2),
1874 "add{b} {$src2, $dst|$dst, $src2}",
1875 [(store (add (load addr:$dst), GR8:$src2), addr:$dst)]>;
1876 def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, GR16:$src2),
1877 "add{w} {$src2, $dst|$dst, $src2}",
1878 [(store (add (load addr:$dst), GR16:$src2), addr:$dst)]>,
1880 def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1881 "add{l} {$src2, $dst|$dst, $src2}",
1882 [(store (add (load addr:$dst), GR32:$src2), addr:$dst)]>;
1883 def ADD8mi : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2),
1884 "add{b} {$src2, $dst|$dst, $src2}",
1885 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1886 def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2),
1887 "add{w} {$src2, $dst|$dst, $src2}",
1888 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1890 def ADD32mi : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2),
1891 "add{l} {$src2, $dst|$dst, $src2}",
1892 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1893 def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i16i8imm :$src2),
1894 "add{w} {$src2, $dst|$dst, $src2}",
1895 [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1897 def ADD32mi8 : Ii8<0x83, MRM0m, (ops i32mem:$dst, i32i8imm :$src2),
1898 "add{l} {$src2, $dst|$dst, $src2}",
1899 [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1902 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1903 def ADC32rr : I<0x11, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1904 "adc{l} {$src2, $dst|$dst, $src2}",
1905 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
1907 def ADC32rm : I<0x13, MRMSrcMem , (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1908 "adc{l} {$src2, $dst|$dst, $src2}",
1909 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
1910 def ADC32ri : Ii32<0x81, MRM2r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1911 "adc{l} {$src2, $dst|$dst, $src2}",
1912 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
1913 def ADC32ri8 : Ii8<0x83, MRM2r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1914 "adc{l} {$src2, $dst|$dst, $src2}",
1915 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
1917 let isTwoAddress = 0 in {
1918 def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1919 "adc{l} {$src2, $dst|$dst, $src2}",
1920 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
1921 def ADC32mi : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2),
1922 "adc{l} {$src2, $dst|$dst, $src2}",
1923 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1924 def ADC32mi8 : Ii8<0x83, MRM2m, (ops i32mem:$dst, i32i8imm :$src2),
1925 "adc{l} {$src2, $dst|$dst, $src2}",
1926 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1929 def SUB8rr : I<0x28, MRMDestReg, (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1930 "sub{b} {$src2, $dst|$dst, $src2}",
1931 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2))]>;
1932 def SUB16rr : I<0x29, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1933 "sub{w} {$src2, $dst|$dst, $src2}",
1934 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2))]>, OpSize;
1935 def SUB32rr : I<0x29, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1936 "sub{l} {$src2, $dst|$dst, $src2}",
1937 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
1938 def SUB8rm : I<0x2A, MRMSrcMem, (ops GR8 :$dst, GR8 :$src1, i8mem :$src2),
1939 "sub{b} {$src2, $dst|$dst, $src2}",
1940 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2)))]>;
1941 def SUB16rm : I<0x2B, MRMSrcMem, (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1942 "sub{w} {$src2, $dst|$dst, $src2}",
1943 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2)))]>, OpSize;
1944 def SUB32rm : I<0x2B, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1945 "sub{l} {$src2, $dst|$dst, $src2}",
1946 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2)))]>;
1948 def SUB8ri : Ii8 <0x80, MRM5r, (ops GR8:$dst, GR8:$src1, i8imm:$src2),
1949 "sub{b} {$src2, $dst|$dst, $src2}",
1950 [(set GR8:$dst, (sub GR8:$src1, imm:$src2))]>;
1951 def SUB16ri : Ii16<0x81, MRM5r, (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1952 "sub{w} {$src2, $dst|$dst, $src2}",
1953 [(set GR16:$dst, (sub GR16:$src1, imm:$src2))]>, OpSize;
1954 def SUB32ri : Ii32<0x81, MRM5r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1955 "sub{l} {$src2, $dst|$dst, $src2}",
1956 [(set GR32:$dst, (sub GR32:$src1, imm:$src2))]>;
1957 def SUB16ri8 : Ii8<0x83, MRM5r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1958 "sub{w} {$src2, $dst|$dst, $src2}",
1959 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2))]>,
1961 def SUB32ri8 : Ii8<0x83, MRM5r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1962 "sub{l} {$src2, $dst|$dst, $src2}",
1963 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2))]>;
1964 let isTwoAddress = 0 in {
1965 def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, GR8 :$src2),
1966 "sub{b} {$src2, $dst|$dst, $src2}",
1967 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst)]>;
1968 def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, GR16:$src2),
1969 "sub{w} {$src2, $dst|$dst, $src2}",
1970 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst)]>,
1972 def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1973 "sub{l} {$src2, $dst|$dst, $src2}",
1974 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst)]>;
1975 def SUB8mi : Ii8<0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2),
1976 "sub{b} {$src2, $dst|$dst, $src2}",
1977 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1978 def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2),
1979 "sub{w} {$src2, $dst|$dst, $src2}",
1980 [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1982 def SUB32mi : Ii32<0x81, MRM5m, (ops i32mem:$dst, i32imm:$src2),
1983 "sub{l} {$src2, $dst|$dst, $src2}",
1984 [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1985 def SUB16mi8 : Ii8<0x83, MRM5m, (ops i16mem:$dst, i16i8imm :$src2),
1986 "sub{w} {$src2, $dst|$dst, $src2}",
1987 [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1989 def SUB32mi8 : Ii8<0x83, MRM5m, (ops i32mem:$dst, i32i8imm :$src2),
1990 "sub{l} {$src2, $dst|$dst, $src2}",
1991 [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1994 def SBB32rr : I<0x19, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1995 "sbb{l} {$src2, $dst|$dst, $src2}",
1996 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
1998 let isTwoAddress = 0 in {
1999 def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
2000 "sbb{l} {$src2, $dst|$dst, $src2}",
2001 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2002 def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2),
2003 "sbb{b} {$src2, $dst|$dst, $src2}",
2004 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2005 def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2),
2006 "sbb{l} {$src2, $dst|$dst, $src2}",
2007 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2008 def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i32i8imm :$src2),
2009 "sbb{l} {$src2, $dst|$dst, $src2}",
2010 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2012 def SBB32rm : I<0x1B, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2),
2013 "sbb{l} {$src2, $dst|$dst, $src2}",
2014 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2015 def SBB32ri : Ii32<0x81, MRM3r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
2016 "sbb{l} {$src2, $dst|$dst, $src2}",
2017 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2018 def SBB32ri8 : Ii8<0x83, MRM3r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
2019 "sbb{l} {$src2, $dst|$dst, $src2}",
2020 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2022 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2023 def IMUL16rr : I<0xAF, MRMSrcReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
2024 "imul{w} {$src2, $dst|$dst, $src2}",
2025 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2))]>, TB, OpSize;
2026 def IMUL32rr : I<0xAF, MRMSrcReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
2027 "imul{l} {$src2, $dst|$dst, $src2}",
2028 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>, TB;
2030 def IMUL16rm : I<0xAF, MRMSrcMem, (ops GR16:$dst, GR16:$src1, i16mem:$src2),
2031 "imul{w} {$src2, $dst|$dst, $src2}",
2032 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2)))]>,
2034 def IMUL32rm : I<0xAF, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2),
2035 "imul{l} {$src2, $dst|$dst, $src2}",
2036 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2)))]>, TB;
2038 } // end Two Address instructions
2040 // Suprisingly enough, these are not two address instructions!
2041 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2042 (ops GR16:$dst, GR16:$src1, i16imm:$src2),
2043 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
2044 [(set GR16:$dst, (mul GR16:$src1, imm:$src2))]>, OpSize;
2045 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2046 (ops GR32:$dst, GR32:$src1, i32imm:$src2),
2047 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
2048 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
2049 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2050 (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
2051 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
2052 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2))]>,
2054 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2055 (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
2056 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
2057 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2))]>;
2059 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2060 (ops GR16:$dst, i16mem:$src1, i16imm:$src2),
2061 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
2062 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2))]>,
2064 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2065 (ops GR32:$dst, i32mem:$src1, i32imm:$src2),
2066 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
2067 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2))]>;
2068 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2069 (ops GR16:$dst, i16mem:$src1, i16i8imm :$src2),
2070 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
2071 [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>,
2073 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2074 (ops GR32:$dst, i32mem:$src1, i32i8imm: $src2),
2075 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
2076 [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>;
2078 //===----------------------------------------------------------------------===//
2079 // Test instructions are just like AND, except they don't generate a result.
2081 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2082 def TEST8rr : I<0x84, MRMDestReg, (ops GR8:$src1, GR8:$src2),
2083 "test{b} {$src2, $src1|$src1, $src2}",
2084 [(X86cmp (and GR8:$src1, GR8:$src2), 0)]>;
2085 def TEST16rr : I<0x85, MRMDestReg, (ops GR16:$src1, GR16:$src2),
2086 "test{w} {$src2, $src1|$src1, $src2}",
2087 [(X86cmp (and GR16:$src1, GR16:$src2), 0)]>, OpSize;
2088 def TEST32rr : I<0x85, MRMDestReg, (ops GR32:$src1, GR32:$src2),
2089 "test{l} {$src2, $src1|$src1, $src2}",
2090 [(X86cmp (and GR32:$src1, GR32:$src2), 0)]>;
2093 def TEST8rm : I<0x84, MRMSrcMem, (ops GR8 :$src1, i8mem :$src2),
2094 "test{b} {$src2, $src1|$src1, $src2}",
2095 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0)]>;
2096 def TEST16rm : I<0x85, MRMSrcMem, (ops GR16:$src1, i16mem:$src2),
2097 "test{w} {$src2, $src1|$src1, $src2}",
2098 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0)]>,
2100 def TEST32rm : I<0x85, MRMSrcMem, (ops GR32:$src1, i32mem:$src2),
2101 "test{l} {$src2, $src1|$src1, $src2}",
2102 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0)]>;
2104 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2105 (ops GR8:$src1, i8imm:$src2),
2106 "test{b} {$src2, $src1|$src1, $src2}",
2107 [(X86cmp (and GR8:$src1, imm:$src2), 0)]>;
2108 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2109 (ops GR16:$src1, i16imm:$src2),
2110 "test{w} {$src2, $src1|$src1, $src2}",
2111 [(X86cmp (and GR16:$src1, imm:$src2), 0)]>, OpSize;
2112 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2113 (ops GR32:$src1, i32imm:$src2),
2114 "test{l} {$src2, $src1|$src1, $src2}",
2115 [(X86cmp (and GR32:$src1, imm:$src2), 0)]>;
2117 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2118 (ops i8mem:$src1, i8imm:$src2),
2119 "test{b} {$src2, $src1|$src1, $src2}",
2120 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0)]>;
2121 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2122 (ops i16mem:$src1, i16imm:$src2),
2123 "test{w} {$src2, $src1|$src1, $src2}",
2124 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0)]>,
2126 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2127 (ops i32mem:$src1, i32imm:$src2),
2128 "test{l} {$src2, $src1|$src1, $src2}",
2129 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0)]>;
2132 // Condition code ops, incl. set if equal/not equal/...
2133 def SAHF : I<0x9E, RawFrm, (ops), "sahf", []>, Imp<[AH],[]>; // flags = AH
2134 def LAHF : I<0x9F, RawFrm, (ops), "lahf", []>, Imp<[],[AH]>; // AH = flags
2136 def SETEr : I<0x94, MRM0r,
2139 [(set GR8:$dst, (X86setcc X86_COND_E))]>,
2141 def SETEm : I<0x94, MRM0m,
2144 [(store (X86setcc X86_COND_E), addr:$dst)]>,
2146 def SETNEr : I<0x95, MRM0r,
2149 [(set GR8:$dst, (X86setcc X86_COND_NE))]>,
2151 def SETNEm : I<0x95, MRM0m,
2154 [(store (X86setcc X86_COND_NE), addr:$dst)]>,
2156 def SETLr : I<0x9C, MRM0r,
2159 [(set GR8:$dst, (X86setcc X86_COND_L))]>,
2160 TB; // GR8 = < signed
2161 def SETLm : I<0x9C, MRM0m,
2164 [(store (X86setcc X86_COND_L), addr:$dst)]>,
2165 TB; // [mem8] = < signed
2166 def SETGEr : I<0x9D, MRM0r,
2169 [(set GR8:$dst, (X86setcc X86_COND_GE))]>,
2170 TB; // GR8 = >= signed
2171 def SETGEm : I<0x9D, MRM0m,
2174 [(store (X86setcc X86_COND_GE), addr:$dst)]>,
2175 TB; // [mem8] = >= signed
2176 def SETLEr : I<0x9E, MRM0r,
2179 [(set GR8:$dst, (X86setcc X86_COND_LE))]>,
2180 TB; // GR8 = <= signed
2181 def SETLEm : I<0x9E, MRM0m,
2184 [(store (X86setcc X86_COND_LE), addr:$dst)]>,
2185 TB; // [mem8] = <= signed
2186 def SETGr : I<0x9F, MRM0r,
2189 [(set GR8:$dst, (X86setcc X86_COND_G))]>,
2190 TB; // GR8 = > signed
2191 def SETGm : I<0x9F, MRM0m,
2194 [(store (X86setcc X86_COND_G), addr:$dst)]>,
2195 TB; // [mem8] = > signed
2197 def SETBr : I<0x92, MRM0r,
2200 [(set GR8:$dst, (X86setcc X86_COND_B))]>,
2201 TB; // GR8 = < unsign
2202 def SETBm : I<0x92, MRM0m,
2205 [(store (X86setcc X86_COND_B), addr:$dst)]>,
2206 TB; // [mem8] = < unsign
2207 def SETAEr : I<0x93, MRM0r,
2210 [(set GR8:$dst, (X86setcc X86_COND_AE))]>,
2211 TB; // GR8 = >= unsign
2212 def SETAEm : I<0x93, MRM0m,
2215 [(store (X86setcc X86_COND_AE), addr:$dst)]>,
2216 TB; // [mem8] = >= unsign
2217 def SETBEr : I<0x96, MRM0r,
2220 [(set GR8:$dst, (X86setcc X86_COND_BE))]>,
2221 TB; // GR8 = <= unsign
2222 def SETBEm : I<0x96, MRM0m,
2225 [(store (X86setcc X86_COND_BE), addr:$dst)]>,
2226 TB; // [mem8] = <= unsign
2227 def SETAr : I<0x97, MRM0r,
2230 [(set GR8:$dst, (X86setcc X86_COND_A))]>,
2231 TB; // GR8 = > signed
2232 def SETAm : I<0x97, MRM0m,
2235 [(store (X86setcc X86_COND_A), addr:$dst)]>,
2236 TB; // [mem8] = > signed
2238 def SETSr : I<0x98, MRM0r,
2241 [(set GR8:$dst, (X86setcc X86_COND_S))]>,
2242 TB; // GR8 = <sign bit>
2243 def SETSm : I<0x98, MRM0m,
2246 [(store (X86setcc X86_COND_S), addr:$dst)]>,
2247 TB; // [mem8] = <sign bit>
2248 def SETNSr : I<0x99, MRM0r,
2251 [(set GR8:$dst, (X86setcc X86_COND_NS))]>,
2252 TB; // GR8 = !<sign bit>
2253 def SETNSm : I<0x99, MRM0m,
2256 [(store (X86setcc X86_COND_NS), addr:$dst)]>,
2257 TB; // [mem8] = !<sign bit>
2258 def SETPr : I<0x9A, MRM0r,
2261 [(set GR8:$dst, (X86setcc X86_COND_P))]>,
2263 def SETPm : I<0x9A, MRM0m,
2266 [(store (X86setcc X86_COND_P), addr:$dst)]>,
2267 TB; // [mem8] = parity
2268 def SETNPr : I<0x9B, MRM0r,
2271 [(set GR8:$dst, (X86setcc X86_COND_NP))]>,
2272 TB; // GR8 = not parity
2273 def SETNPm : I<0x9B, MRM0m,
2276 [(store (X86setcc X86_COND_NP), addr:$dst)]>,
2277 TB; // [mem8] = not parity
2279 // Integer comparisons
2280 def CMP8rr : I<0x38, MRMDestReg,
2281 (ops GR8 :$src1, GR8 :$src2),
2282 "cmp{b} {$src2, $src1|$src1, $src2}",
2283 [(X86cmp GR8:$src1, GR8:$src2)]>;
2284 def CMP16rr : I<0x39, MRMDestReg,
2285 (ops GR16:$src1, GR16:$src2),
2286 "cmp{w} {$src2, $src1|$src1, $src2}",
2287 [(X86cmp GR16:$src1, GR16:$src2)]>, OpSize;
2288 def CMP32rr : I<0x39, MRMDestReg,
2289 (ops GR32:$src1, GR32:$src2),
2290 "cmp{l} {$src2, $src1|$src1, $src2}",
2291 [(X86cmp GR32:$src1, GR32:$src2)]>;
2292 def CMP8mr : I<0x38, MRMDestMem,
2293 (ops i8mem :$src1, GR8 :$src2),
2294 "cmp{b} {$src2, $src1|$src1, $src2}",
2295 [(X86cmp (loadi8 addr:$src1), GR8:$src2)]>;
2296 def CMP16mr : I<0x39, MRMDestMem,
2297 (ops i16mem:$src1, GR16:$src2),
2298 "cmp{w} {$src2, $src1|$src1, $src2}",
2299 [(X86cmp (loadi16 addr:$src1), GR16:$src2)]>, OpSize;
2300 def CMP32mr : I<0x39, MRMDestMem,
2301 (ops i32mem:$src1, GR32:$src2),
2302 "cmp{l} {$src2, $src1|$src1, $src2}",
2303 [(X86cmp (loadi32 addr:$src1), GR32:$src2)]>;
2304 def CMP8rm : I<0x3A, MRMSrcMem,
2305 (ops GR8 :$src1, i8mem :$src2),
2306 "cmp{b} {$src2, $src1|$src1, $src2}",
2307 [(X86cmp GR8:$src1, (loadi8 addr:$src2))]>;
2308 def CMP16rm : I<0x3B, MRMSrcMem,
2309 (ops GR16:$src1, i16mem:$src2),
2310 "cmp{w} {$src2, $src1|$src1, $src2}",
2311 [(X86cmp GR16:$src1, (loadi16 addr:$src2))]>, OpSize;
2312 def CMP32rm : I<0x3B, MRMSrcMem,
2313 (ops GR32:$src1, i32mem:$src2),
2314 "cmp{l} {$src2, $src1|$src1, $src2}",
2315 [(X86cmp GR32:$src1, (loadi32 addr:$src2))]>;
2316 def CMP8ri : Ii8<0x80, MRM7r,
2317 (ops GR8:$src1, i8imm:$src2),
2318 "cmp{b} {$src2, $src1|$src1, $src2}",
2319 [(X86cmp GR8:$src1, imm:$src2)]>;
2320 def CMP16ri : Ii16<0x81, MRM7r,
2321 (ops GR16:$src1, i16imm:$src2),
2322 "cmp{w} {$src2, $src1|$src1, $src2}",
2323 [(X86cmp GR16:$src1, imm:$src2)]>, OpSize;
2324 def CMP32ri : Ii32<0x81, MRM7r,
2325 (ops GR32:$src1, i32imm:$src2),
2326 "cmp{l} {$src2, $src1|$src1, $src2}",
2327 [(X86cmp GR32:$src1, imm:$src2)]>;
2328 def CMP8mi : Ii8 <0x80, MRM7m,
2329 (ops i8mem :$src1, i8imm :$src2),
2330 "cmp{b} {$src2, $src1|$src1, $src2}",
2331 [(X86cmp (loadi8 addr:$src1), imm:$src2)]>;
2332 def CMP16mi : Ii16<0x81, MRM7m,
2333 (ops i16mem:$src1, i16imm:$src2),
2334 "cmp{w} {$src2, $src1|$src1, $src2}",
2335 [(X86cmp (loadi16 addr:$src1), imm:$src2)]>, OpSize;
2336 def CMP32mi : Ii32<0x81, MRM7m,
2337 (ops i32mem:$src1, i32imm:$src2),
2338 "cmp{l} {$src2, $src1|$src1, $src2}",
2339 [(X86cmp (loadi32 addr:$src1), imm:$src2)]>;
2340 def CMP16ri8 : Ii8<0x83, MRM7r,
2341 (ops GR16:$src1, i16i8imm:$src2),
2342 "cmp{w} {$src2, $src1|$src1, $src2}",
2343 [(X86cmp GR16:$src1, i16immSExt8:$src2)]>, OpSize;
2344 def CMP16mi8 : Ii8<0x83, MRM7m,
2345 (ops i16mem:$src1, i16i8imm:$src2),
2346 "cmp{w} {$src2, $src1|$src1, $src2}",
2347 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2)]>, OpSize;
2348 def CMP32mi8 : Ii8<0x83, MRM7m,
2349 (ops i32mem:$src1, i32i8imm:$src2),
2350 "cmp{l} {$src2, $src1|$src1, $src2}",
2351 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2)]>;
2352 def CMP32ri8 : Ii8<0x83, MRM7r,
2353 (ops GR32:$src1, i32i8imm:$src2),
2354 "cmp{l} {$src2, $src1|$src1, $src2}",
2355 [(X86cmp GR32:$src1, i32immSExt8:$src2)]>;
2357 // Sign/Zero extenders
2358 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops GR16:$dst, GR8 :$src),
2359 "movs{bw|x} {$src, $dst|$dst, $src}",
2360 [(set GR16:$dst, (sext GR8:$src))]>, TB, OpSize;
2361 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (ops GR16:$dst, i8mem :$src),
2362 "movs{bw|x} {$src, $dst|$dst, $src}",
2363 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize;
2364 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops GR32:$dst, GR8 :$src),
2365 "movs{bl|x} {$src, $dst|$dst, $src}",
2366 [(set GR32:$dst, (sext GR8:$src))]>, TB;
2367 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (ops GR32:$dst, i8mem :$src),
2368 "movs{bl|x} {$src, $dst|$dst, $src}",
2369 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
2370 def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops GR32:$dst, GR16:$src),
2371 "movs{wl|x} {$src, $dst|$dst, $src}",
2372 [(set GR32:$dst, (sext GR16:$src))]>, TB;
2373 def MOVSX32rm16: I<0xBF, MRMSrcMem, (ops GR32:$dst, i16mem:$src),
2374 "movs{wl|x} {$src, $dst|$dst, $src}",
2375 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
2377 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops GR16:$dst, GR8 :$src),
2378 "movz{bw|x} {$src, $dst|$dst, $src}",
2379 [(set GR16:$dst, (zext GR8:$src))]>, TB, OpSize;
2380 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (ops GR16:$dst, i8mem :$src),
2381 "movz{bw|x} {$src, $dst|$dst, $src}",
2382 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize;
2383 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops GR32:$dst, GR8 :$src),
2384 "movz{bl|x} {$src, $dst|$dst, $src}",
2385 [(set GR32:$dst, (zext GR8:$src))]>, TB;
2386 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (ops GR32:$dst, i8mem :$src),
2387 "movz{bl|x} {$src, $dst|$dst, $src}",
2388 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
2389 def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops GR32:$dst, GR16:$src),
2390 "movz{wl|x} {$src, $dst|$dst, $src}",
2391 [(set GR32:$dst, (zext GR16:$src))]>, TB;
2392 def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops GR32:$dst, i16mem:$src),
2393 "movz{wl|x} {$src, $dst|$dst, $src}",
2394 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
2396 def CBW : I<0x98, RawFrm, (ops),
2397 "{cbtw|cbw}", []>, Imp<[AL],[AX]>; // AX = signext(AL)
2398 def CWDE : I<0x98, RawFrm, (ops),
2399 "{cwtl|cwde}", []>, Imp<[AX],[EAX]>; // EAX = signext(AX)
2401 def CWD : I<0x99, RawFrm, (ops),
2402 "{cwtd|cwd}", []>, Imp<[AX],[AX,DX]>; // DX:AX = signext(AX)
2403 def CDQ : I<0x99, RawFrm, (ops),
2404 "{cltd|cdq}", []>, Imp<[EAX],[EAX,EDX]>; // EDX:EAX = signext(EAX)
2407 //===----------------------------------------------------------------------===//
2408 // Alias Instructions
2409 //===----------------------------------------------------------------------===//
2411 // Alias instructions that map movr0 to xor.
2412 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2413 def MOV8r0 : I<0x30, MRMInitReg, (ops GR8 :$dst),
2414 "xor{b} $dst, $dst",
2415 [(set GR8:$dst, 0)]>;
2416 def MOV16r0 : I<0x31, MRMInitReg, (ops GR16:$dst),
2417 "xor{w} $dst, $dst",
2418 [(set GR16:$dst, 0)]>, OpSize;
2419 def MOV32r0 : I<0x31, MRMInitReg, (ops GR32:$dst),
2420 "xor{l} $dst, $dst",
2421 [(set GR32:$dst, 0)]>;
2423 // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
2424 // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
2425 def MOV16to16_ : I<0x89, MRMDestReg, (ops GR16_:$dst, GR16:$src),
2426 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
2427 def MOV32to32_ : I<0x89, MRMDestReg, (ops GR32_:$dst, GR32:$src),
2428 "mov{l} {$src, $dst|$dst, $src}", []>;
2430 def MOV16_rr : I<0x89, MRMDestReg, (ops GR16_:$dst, GR16_:$src),
2431 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
2432 def MOV32_rr : I<0x89, MRMDestReg, (ops GR32_:$dst, GR32_:$src),
2433 "mov{l} {$src, $dst|$dst, $src}", []>;
2434 def MOV16_rm : I<0x8B, MRMSrcMem, (ops GR16_:$dst, i16mem:$src),
2435 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
2436 def MOV32_rm : I<0x8B, MRMSrcMem, (ops GR32_:$dst, i32mem:$src),
2437 "mov{l} {$src, $dst|$dst, $src}", []>;
2438 def MOV16_mr : I<0x89, MRMDestMem, (ops i16mem:$dst, GR16_:$src),
2439 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
2440 def MOV32_mr : I<0x89, MRMDestMem, (ops i32mem:$dst, GR32_:$src),
2441 "mov{l} {$src, $dst|$dst, $src}", []>;
2443 //===----------------------------------------------------------------------===//
2444 // DWARF Pseudo Instructions
2447 def DWARF_LOC : I<0, Pseudo, (ops i32imm:$line, i32imm:$col, i32imm:$file),
2448 "; .loc $file, $line, $col",
2449 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
2452 def DWARF_LABEL : I<0, Pseudo, (ops i32imm:$id),
2453 "\n${:private}debug_loc${id:debug}:",
2454 [(dwarf_label (i32 imm:$id))]>;
2456 //===----------------------------------------------------------------------===//
2457 // Non-Instruction Patterns
2458 //===----------------------------------------------------------------------===//
2460 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
2461 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
2462 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
2463 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
2464 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
2466 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
2467 (ADD32ri GR32:$src1, tconstpool:$src2)>;
2468 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
2469 (ADD32ri GR32:$src1, tjumptable:$src2)>;
2470 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
2471 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
2472 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
2473 (ADD32ri GR32:$src1, texternalsym:$src2)>;
2475 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
2476 (MOV32mi addr:$dst, tglobaladdr:$src)>;
2477 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
2478 (MOV32mi addr:$dst, texternalsym:$src)>;
2481 def : Pat<(X86tailcall GR32:$dst),
2482 (CALL32r GR32:$dst)>;
2484 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
2485 (CALLpcrel32 tglobaladdr:$dst)>;
2486 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
2487 (CALLpcrel32 texternalsym:$dst)>;
2489 def : Pat<(X86call (i32 tglobaladdr:$dst)),
2490 (CALLpcrel32 tglobaladdr:$dst)>;
2491 def : Pat<(X86call (i32 texternalsym:$dst)),
2492 (CALLpcrel32 texternalsym:$dst)>;
2494 // X86 specific add which produces a flag.
2495 def : Pat<(addc GR32:$src1, GR32:$src2),
2496 (ADD32rr GR32:$src1, GR32:$src2)>;
2497 def : Pat<(addc GR32:$src1, (load addr:$src2)),
2498 (ADD32rm GR32:$src1, addr:$src2)>;
2499 def : Pat<(addc GR32:$src1, imm:$src2),
2500 (ADD32ri GR32:$src1, imm:$src2)>;
2501 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
2502 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
2504 def : Pat<(subc GR32:$src1, GR32:$src2),
2505 (SUB32rr GR32:$src1, GR32:$src2)>;
2506 def : Pat<(subc GR32:$src1, (load addr:$src2)),
2507 (SUB32rm GR32:$src1, addr:$src2)>;
2508 def : Pat<(subc GR32:$src1, imm:$src2),
2509 (SUB32ri GR32:$src1, imm:$src2)>;
2510 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
2511 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
2513 def : Pat<(truncstorei1 (i8 imm:$src), addr:$dst),
2514 (MOV8mi addr:$dst, imm:$src)>;
2515 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
2516 (MOV8mr addr:$dst, GR8:$src)>;
2520 // TEST R,R is smaller than CMP R,0
2521 def : Pat<(X86cmp GR8:$src1, 0),
2522 (TEST8rr GR8:$src1, GR8:$src1)>;
2523 def : Pat<(X86cmp GR16:$src1, 0),
2524 (TEST16rr GR16:$src1, GR16:$src1)>;
2525 def : Pat<(X86cmp GR32:$src1, 0),
2526 (TEST32rr GR32:$src1, GR32:$src1)>;
2528 // {s|z}extload bool -> {s|z}extload byte
2529 def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>;
2530 def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>;
2531 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2532 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2533 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2535 // extload bool -> extload byte
2536 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2537 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2538 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2539 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
2540 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
2541 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
2544 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
2545 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
2546 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
2547 def : Pat<(i16 (anyext (loadi8 addr:$src))), (MOVZX16rm8 addr:$src)>;
2548 def : Pat<(i32 (anyext (loadi8 addr:$src))), (MOVZX32rm8 addr:$src)>;
2549 def : Pat<(i32 (anyext (loadi16 addr:$src))), (MOVZX32rm16 addr:$src)>;
2551 //===----------------------------------------------------------------------===//
2553 //===----------------------------------------------------------------------===//
2555 // (shl x, 1) ==> (add x, x)
2556 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
2557 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
2558 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
2560 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
2561 def : Pat<(or (srl GR32:$src1, CL:$amt),
2562 (shl GR32:$src2, (sub 32, CL:$amt))),
2563 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
2565 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
2566 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2567 (SHRD32mrCL addr:$dst, GR32:$src2)>;
2569 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
2570 def : Pat<(or (shl GR32:$src1, CL:$amt),
2571 (srl GR32:$src2, (sub 32, CL:$amt))),
2572 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
2574 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
2575 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2576 (SHLD32mrCL addr:$dst, GR32:$src2)>;
2578 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
2579 def : Pat<(or (srl GR16:$src1, CL:$amt),
2580 (shl GR16:$src2, (sub 16, CL:$amt))),
2581 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
2583 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
2584 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2585 (SHRD16mrCL addr:$dst, GR16:$src2)>;
2587 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
2588 def : Pat<(or (shl GR16:$src1, CL:$amt),
2589 (srl GR16:$src2, (sub 16, CL:$amt))),
2590 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
2592 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
2593 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2594 (SHLD16mrCL addr:$dst, GR16:$src2)>;
2597 //===----------------------------------------------------------------------===//
2598 // Floating Point Stack Support
2599 //===----------------------------------------------------------------------===//
2601 include "X86InstrFPStack.td"
2603 //===----------------------------------------------------------------------===//
2604 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
2605 //===----------------------------------------------------------------------===//
2607 include "X86InstrMMX.td"
2609 //===----------------------------------------------------------------------===//
2610 // XMM Floating point support (requires SSE / SSE2)
2611 //===----------------------------------------------------------------------===//
2613 include "X86InstrSSE.td"
2615 //===----------------------------------------------------------------------===//
2617 //===----------------------------------------------------------------------===//
2619 include "X86InstrX86-64.td"