1 //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // This file describes the X86 instruction set, defining the instructions, and
4 // properties of the instructions which are needed for code generation, machine
5 // code emission, and analysis.
7 //===----------------------------------------------------------------------===//
9 // Format specifies the encoding used by the instruction. This is part of the
10 // ad-hoc solution used to emit machine instruction encodings by our machine
12 class Format<bits<5> val> {
16 def Pseudo : Format<0>; def RawFrm : Format<1>;
17 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
18 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
19 def MRMSrcMem : Format<6>;
20 def MRMS0r : Format<16>; def MRMS1r : Format<17>; def MRMS2r : Format<18>;
21 def MRMS3r : Format<19>; def MRMS4r : Format<20>; def MRMS5r : Format<21>;
22 def MRMS6r : Format<22>; def MRMS7r : Format<23>;
23 def MRMS0m : Format<24>; def MRMS1m : Format<25>; def MRMS2m : Format<26>;
24 def MRMS3m : Format<27>; def MRMS4m : Format<28>; def MRMS5m : Format<29>;
25 def MRMS6m : Format<30>; def MRMS7m : Format<31>;
27 // ArgType - This specifies the argument type used by an instruction. This is
28 // part of the ad-hoc solution used to emit machine instruction encodings by our
29 // machine code emitter.
30 class ArgType<bits<3> val> {
33 def NoArg : ArgType<0>;
34 def Arg8 : ArgType<1>;
35 def Arg16 : ArgType<2>;
36 def Arg32 : ArgType<3>;
37 def Arg64 : ArgType<4>; // 64 bit int argument for FILD64
38 def ArgF32 : ArgType<5>;
39 def ArgF64 : ArgType<6>;
40 def ArgF80 : ArgType<6>;
42 // FPFormat - This specifies what form this FP instruction has. This is used by
43 // the Floating-Point stackifier pass.
44 class FPFormat<bits<3> val> {
47 def NotFP : FPFormat<0>;
48 def ZeroArgFP : FPFormat<1>;
49 def OneArgFP : FPFormat<2>;
50 def OneArgFPRW : FPFormat<3>;
51 def TwoArgFP : FPFormat<4>;
52 def SpecialFP : FPFormat<5>;
55 class X86Inst<string nam, bits<8> opcod, Format f, ArgType a> : Instruction {
56 let Namespace = "X86";
59 bits<8> Opcode = opcod;
61 bits<5> FormBits = Form.Value;
63 bits<3> TypeBits = Type.Value;
65 // Attributes specific to X86 instructions...
66 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
67 bit printImplicitUses = 0; // Should we print implicit uses of this inst?
69 bits<4> Prefix = 0; // Which prefix byte does this inst have?
70 FPFormat FPForm; // What flavor of FP instruction is this?
71 bits<3> FPFormBits = 0;
74 class Imp<list<Register> uses, list<Register> defs> {
75 list<Register> Uses = uses;
76 list<Register> Defs = defs;
79 class Pattern<dag P> {
84 // Prefix byte classes which are used to indicate to the ad-hoc machine code
85 // emitter that various prefix bytes are required.
86 class OpSize { bit hasOpSizePrefix = 1; }
87 class TB { bits<4> Prefix = 1; }
88 class D8 { bits<4> Prefix = 2; }
89 class D9 { bits<4> Prefix = 3; }
90 class DA { bits<4> Prefix = 4; }
91 class DB { bits<4> Prefix = 5; }
92 class DC { bits<4> Prefix = 6; }
93 class DD { bits<4> Prefix = 7; }
94 class DE { bits<4> Prefix = 8; }
95 class DF { bits<4> Prefix = 9; }
99 //===----------------------------------------------------------------------===//
100 // Instruction list...
103 def PHI : X86Inst<"PHI", 0, Pseudo, NoArg>; // PHI node...
105 def NOOP : X86Inst<"nop", 0x90, RawFrm, NoArg>; // nop
107 def ADJCALLSTACKDOWN : X86Inst<"ADJCALLSTACKDOWN", 0, Pseudo, NoArg>;
108 def ADJCALLSTACKUP : X86Inst<"ADJCALLSTACKUP", 0, Pseudo, NoArg>;
109 def IMPLICIT_USE : X86Inst<"IMPLICIT_USE", 0, Pseudo, NoArg>;
110 def IMPLICIT_DEF : X86Inst<"IMPLICIT_DEF", 0, Pseudo, NoArg>;
112 //===----------------------------------------------------------------------===//
113 // Control Flow Instructions...
116 // Return instruction...
117 let isTerminator = 1, isReturn = 1 in
118 def RET : X86Inst<"ret", 0xC3, RawFrm, NoArg>, Pattern<(retvoid)>;
120 // All branches are RawFrm, Void, Branch, and Terminators
121 let isBranch = 1, isTerminator = 1 in
122 class IBr<string name, bits<8> opcode> : X86Inst<name, opcode, RawFrm, NoArg>;
124 def JMP : IBr<"jmp", 0xE9>, Pattern<(br basicblock)>;
125 def JB : IBr<"jb" , 0x82>, TB;
126 def JAE : IBr<"jae", 0x83>, TB;
127 def JE : IBr<"je" , 0x84>, TB, Pattern<(isVoid (unspec1 basicblock))>;
128 def JNE : IBr<"jne", 0x85>, TB;
129 def JBE : IBr<"jbe", 0x86>, TB;
130 def JA : IBr<"ja" , 0x87>, TB;
131 def JL : IBr<"jl" , 0x8C>, TB;
132 def JGE : IBr<"jge", 0x8D>, TB;
133 def JLE : IBr<"jle", 0x8E>, TB;
134 def JG : IBr<"jg" , 0x8F>, TB;
137 //===----------------------------------------------------------------------===//
138 // Call Instructions...
141 // All calls clobber the non-callee saved registers...
142 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6] in {
143 def CALLpcrel32 : X86Inst<"call", 0xE8, RawFrm, NoArg>;
144 def CALLr32 : X86Inst<"call", 0xFF, MRMS2r, Arg32>;
145 def CALLm32 : X86Inst<"call", 0xFF, MRMS2m, Arg32>;
149 //===----------------------------------------------------------------------===//
150 // Miscellaneous Instructions...
152 def LEAVE : X86Inst<"leave", 0xC9, RawFrm, NoArg>, Imp<[EBP], [EBP]>;
154 let isTwoAddress = 1 in // R32 = bswap R32
155 def BSWAPr32 : X86Inst<"bswap", 0xC8, AddRegFrm, Arg32>, TB;
157 def XCHGrr8 : X86Inst<"xchg", 0x86, MRMDestReg, Arg8>; // xchg R8, R8
158 def XCHGrr16 : X86Inst<"xchg", 0x87, MRMDestReg, Arg16>, OpSize;// xchg R16, R16
159 def XCHGrr32 : X86Inst<"xchg", 0x87, MRMDestReg, Arg32>; // xchg R32, R32
161 def LEAr16 : X86Inst<"lea", 0x8D, MRMSrcMem, Arg16>, OpSize; // R16 = lea [mem]
162 def LEAr32 : X86Inst<"lea", 0x8D, MRMSrcMem, Arg32>; // R32 = lea [mem]
164 //===----------------------------------------------------------------------===//
165 // Move Instructions...
167 def MOVrr8 : X86Inst<"mov", 0x88, MRMDestReg, Arg8>, Pattern<(set R8 , R8 )>;
168 def MOVrr16 : X86Inst<"mov", 0x89, MRMDestReg, Arg16>, OpSize, Pattern<(set R16, R16)>;
169 def MOVrr32 : X86Inst<"mov", 0x89, MRMDestReg, Arg32>, Pattern<(set R32, R32)>;
170 def MOVir8 : X86Inst<"mov", 0xB0, AddRegFrm , Arg8>, Pattern<(set R8 , imm )>;
171 def MOVir16 : X86Inst<"mov", 0xB8, AddRegFrm , Arg16>, OpSize, Pattern<(set R16, imm)>;
172 def MOVir32 : X86Inst<"mov", 0xB8, AddRegFrm , Arg32>, Pattern<(set R32, imm)>;
173 def MOVim8 : X86Inst<"mov", 0xC6, MRMS0m , Arg8>; // [mem] = imm8
174 def MOVim16 : X86Inst<"mov", 0xC7, MRMS0m , Arg16>, OpSize; // [mem] = imm16
175 def MOVim32 : X86Inst<"mov", 0xC7, MRMS0m , Arg32>; // [mem] = imm32
177 def MOVmr8 : X86Inst<"mov", 0x8A, MRMSrcMem , Arg8>; // R8 = [mem]
178 def MOVmr16 : X86Inst<"mov", 0x8B, MRMSrcMem , Arg16>, OpSize, // R16 = [mem]
179 Pattern<(set R16, (load (plus R32, (plus (times imm, R32), imm))))>;
180 def MOVmr32 : X86Inst<"mov", 0x8B, MRMSrcMem , Arg32>, // R32 = [mem]
181 Pattern<(set R32, (load (plus R32, (plus (times imm, R32), imm))))>;
183 def MOVrm8 : X86Inst<"mov", 0x88, MRMDestMem, Arg8>; // [mem] = R8
184 def MOVrm16 : X86Inst<"mov", 0x89, MRMDestMem, Arg16>, OpSize; // [mem] = R16
185 def MOVrm32 : X86Inst<"mov", 0x89, MRMDestMem, Arg32>; // [mem] = R32
187 //===----------------------------------------------------------------------===//
188 // Fixed-Register Multiplication and Division Instructions...
191 // Extra precision multiplication
192 def MULr8 : X86Inst<"mul", 0xF6, MRMS4r, Arg8 >, Imp<[AL],[AX]>; // AL,AH = AL*R8
193 def MULr16 : X86Inst<"mul", 0xF7, MRMS4r, Arg16>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
194 def MULr32 : X86Inst<"mul", 0xF7, MRMS4r, Arg32>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
196 // unsigned division/remainder
197 def DIVr8 : X86Inst<"div", 0xF6, MRMS6r, Arg8 >, Imp<[AX],[AX]>; // AX/r8 = AL,AH
198 def DIVr16 : X86Inst<"div", 0xF7, MRMS6r, Arg16>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
199 def DIVr32 : X86Inst<"div", 0xF7, MRMS6r, Arg32>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
201 // signed division/remainder
202 def IDIVr8 : X86Inst<"idiv",0xF6, MRMS7r, Arg8 >, Imp<[AX],[AX]>; // AX/r8 = AL,AH
203 def IDIVr16: X86Inst<"idiv",0xF7, MRMS7r, Arg16>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
204 def IDIVr32: X86Inst<"idiv",0xF7, MRMS7r, Arg32>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
206 // Sign-extenders for division
207 def CBW : X86Inst<"cbw", 0x98, RawFrm, Arg8 >, Imp<[AL],[AH]>; // AX = signext(AL)
208 def CWD : X86Inst<"cwd", 0x99, RawFrm, Arg8 >, Imp<[AX],[DX]>; // DX:AX = signext(AX)
209 def CDQ : X86Inst<"cdq", 0x99, RawFrm, Arg8 >, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX)
212 //===----------------------------------------------------------------------===//
213 // Two address Instructions...
215 let isTwoAddress = 1 in { // Define some helper classes to make defs shorter.
216 class I2A8 <string n, bits<8> o, Format F> : X86Inst<n, o, F, Arg8>;
217 class I2A16<string n, bits<8> o, Format F> : X86Inst<n, o, F, Arg16>;
218 class I2A32<string n, bits<8> o, Format F> : X86Inst<n, o, F, Arg32>;
222 def ADDrr8 : I2A8 <"add", 0x00, MRMDestReg>, Pattern<(set R8 , (plus R8 , R8 ))>;
223 def ADDrr16 : I2A16<"add", 0x01, MRMDestReg>, OpSize, Pattern<(set R16, (plus R16, R16))>;
224 def ADDrr32 : I2A32<"add", 0x01, MRMDestReg>, Pattern<(set R32, (plus R32, R32))>;
225 def ADDri8 : I2A8 <"add", 0x80, MRMS0r >, Pattern<(set R8 , (plus R8 , imm))>;
226 def ADDri16 : I2A16<"add", 0x81, MRMS0r >, OpSize, Pattern<(set R16, (plus R16, imm))>;
227 def ADDri32 : I2A32<"add", 0x81, MRMS0r >, Pattern<(set R32, (plus R32, imm))>;
229 def ADCrr32 : I2A32<"adc", 0x11, MRMDestReg>; // R32 += imm32+Carry
231 def SUBrr8 : I2A8 <"sub", 0x28, MRMDestReg>, Pattern<(set R8 , (minus R8 , R8 ))>;
232 def SUBrr16 : I2A16<"sub", 0x29, MRMDestReg>, OpSize, Pattern<(set R16, (minus R16, R16))>;
233 def SUBrr32 : I2A32<"sub", 0x29, MRMDestReg>, Pattern<(set R32, (minus R32, R32))>;
234 def SUBri8 : I2A8 <"sub", 0x80, MRMS5r >, Pattern<(set R8 , (minus R8 , imm))>;
235 def SUBri16 : I2A16<"sub", 0x81, MRMS5r >, OpSize, Pattern<(set R16, (minus R16, imm))>;
236 def SUBri32 : I2A32<"sub", 0x81, MRMS5r >, Pattern<(set R32, (minus R32, imm))>;
238 def SBBrr32 : I2A32<"sbb", 0x19, MRMDestReg>; // R32 -= R32+Carry
240 def IMULr16 : I2A16<"imul", 0xAF, MRMSrcReg>, TB, OpSize, Pattern<(set R16, (times R16, R16))>;
241 def IMULr32 : I2A32<"imul", 0xAF, MRMSrcReg>, TB , Pattern<(set R32, (times R32, R32))>;
243 // Logical operators...
244 def ANDrr8 : I2A8 <"and", 0x20, MRMDestReg>, Pattern<(set R8 , (and R8 , R8 ))>;
245 def ANDrr16 : I2A16<"and", 0x21, MRMDestReg>, OpSize, Pattern<(set R16, (and R16, R16))>;
246 def ANDrr32 : I2A32<"and", 0x21, MRMDestReg>, Pattern<(set R32, (and R32, R32))>;
247 def ANDri8 : I2A8 <"and", 0x80, MRMS4r >, Pattern<(set R8 , (and R8 , imm))>;
248 def ANDri16 : I2A16<"and", 0x81, MRMS4r >, OpSize, Pattern<(set R16, (and R16, imm))>;
249 def ANDri32 : I2A32<"and", 0x81, MRMS4r >, Pattern<(set R32, (and R32, imm))>;
251 def ORrr8 : I2A8 <"or" , 0x08, MRMDestReg>, Pattern<(set R8 , (or R8 , R8 ))>;
252 def ORrr16 : I2A16<"or" , 0x09, MRMDestReg>, OpSize, Pattern<(set R16, (or R16, R16))>;
253 def ORrr32 : I2A32<"or" , 0x09, MRMDestReg>, Pattern<(set R32, (or R32, R32))>;
254 def ORri8 : I2A8 <"or" , 0x80, MRMS1r >, Pattern<(set R8 , (or R8 , imm))>;
255 def ORri16 : I2A16<"or" , 0x81, MRMS1r >, OpSize, Pattern<(set R16, (or R16, imm))>;
256 def ORri32 : I2A32<"or" , 0x81, MRMS1r >, Pattern<(set R32, (or R32, imm))>;
258 def XORrr8 : I2A8 <"xor", 0x30, MRMDestReg>, Pattern<(set R8 , (xor R8 , R8 ))>;
259 def XORrr16 : I2A16<"xor", 0x31, MRMDestReg>, OpSize, Pattern<(set R16, (xor R16, R16))>;
260 def XORrr32 : I2A32<"xor", 0x31, MRMDestReg>, Pattern<(set R32, (xor R32, R32))>;
261 def XORri8 : I2A8 <"xor", 0x80, MRMS6r >, Pattern<(set R8 , (xor R8 , imm))>;
262 def XORri16 : I2A16<"xor", 0x81, MRMS6r >, OpSize, Pattern<(set R16, (xor R16, imm))>;
263 def XORri32 : I2A32<"xor", 0x81, MRMS6r >, Pattern<(set R32, (xor R32, imm))>;
265 // Test instructions are just like AND, except they don't generate a result.
266 def TESTrr8 : X86Inst<"test", 0x84, MRMDestReg, Arg8 >; // flags = R8 & R8
267 def TESTrr16 : X86Inst<"test", 0x85, MRMDestReg, Arg16>, OpSize; // flags = R16 & R16
268 def TESTrr32 : X86Inst<"test", 0x85, MRMDestReg, Arg32>; // flags = R32 & R32
269 def TESTri8 : X86Inst<"test", 0xF6, MRMS0r , Arg8 >; // flags = R8 & imm8
270 def TESTri16 : X86Inst<"test", 0xF7, MRMS0r , Arg16>, OpSize; // flags = R16 & imm16
271 def TESTri32 : X86Inst<"test", 0xF7, MRMS0r , Arg32>; // flags = R32 & imm32
273 // Shift instructions
274 class UsesCL { list<Register> Uses = [CL]; bit printImplicitUses = 1; }
276 def SHLrr8 : I2A8 <"shl", 0xD2, MRMS4r > , UsesCL; // R8 <<= cl
277 def SHLrr16 : I2A8 <"shl", 0xD3, MRMS4r >, OpSize, UsesCL; // R16 <<= cl
278 def SHLrr32 : I2A8 <"shl", 0xD3, MRMS4r > , UsesCL; // R32 <<= cl
279 def SHLir8 : I2A8 <"shl", 0xC0, MRMS4r >; // R8 <<= imm8
280 def SHLir16 : I2A8 <"shl", 0xC1, MRMS4r >, OpSize; // R16 <<= imm16
281 def SHLir32 : I2A8 <"shl", 0xC1, MRMS4r >; // R32 <<= imm32
282 def SHRrr8 : I2A8 <"shr", 0xD2, MRMS5r > , UsesCL; // R8 >>= cl
283 def SHRrr16 : I2A8 <"shr", 0xD3, MRMS5r >, OpSize, UsesCL; // R16 >>= cl
284 def SHRrr32 : I2A8 <"shr", 0xD3, MRMS5r > , UsesCL; // R32 >>= cl
285 def SHRir8 : I2A8 <"shr", 0xC0, MRMS5r >; // R8 >>= imm8
286 def SHRir16 : I2A8 <"shr", 0xC1, MRMS5r >, OpSize; // R16 >>= imm16
287 def SHRir32 : I2A8 <"shr", 0xC1, MRMS5r >; // R32 >>= imm32
288 def SARrr8 : I2A8 <"sar", 0xD2, MRMS7r > , UsesCL; // R8 >>>= cl
289 def SARrr16 : I2A8 <"sar", 0xD3, MRMS7r >, OpSize, UsesCL; // R16 >>>= cl
290 def SARrr32 : I2A8 <"sar", 0xD3, MRMS7r > , UsesCL; // R32 >>>= cl
291 def SARir8 : I2A8 <"sar", 0xC0, MRMS7r >; // R8 >>>= imm8
292 def SARir16 : I2A8 <"sar", 0xC1, MRMS7r >, OpSize; // R16 >>>= imm16
293 def SARir32 : I2A8 <"sar", 0xC1, MRMS7r >; // R32 >>>= imm32
295 def SHLDrr32 : I2A8 <"shld", 0xA5, MRMDestReg>, TB, UsesCL; // R32 <<= R32,R32 cl
296 def SHLDir32 : I2A8 <"shld", 0xA4, MRMDestReg>, TB; // R32 <<= R32,R32 imm8
297 def SHRDrr32 : I2A8 <"shrd", 0xAD, MRMDestReg>, TB, UsesCL; // R32 >>= R32,R32 cl
298 def SHRDir32 : I2A8 <"shrd", 0xAC, MRMDestReg>, TB; // R32 >>= R32,R32 imm8
300 // Condition code ops, incl. set if equal/not equal/...
301 def SAHF : X86Inst<"sahf" , 0x9E, RawFrm, Arg8>, Imp<[AH],[]>; // flags = AH
302 def SETBr : X86Inst<"setb" , 0x92, MRMS0r, Arg8>, TB; // R8 = < unsign
303 def SETAEr : X86Inst<"setae", 0x93, MRMS0r, Arg8>, TB; // R8 = >= unsign
304 def SETEr : X86Inst<"sete" , 0x94, MRMS0r, Arg8>, TB; // R8 = ==
305 def SETNEr : X86Inst<"setne", 0x95, MRMS0r, Arg8>, TB; // R8 = !=
306 def SETBEr : X86Inst<"setbe", 0x96, MRMS0r, Arg8>, TB; // R8 = <= unsign
307 def SETAr : X86Inst<"seta" , 0x97, MRMS0r, Arg8>, TB; // R8 = > signed
308 def SETLr : X86Inst<"setl" , 0x9C, MRMS0r, Arg8>, TB; // R8 = < signed
309 def SETGEr : X86Inst<"setge", 0x9D, MRMS0r, Arg8>, TB; // R8 = >= signed
310 def SETLEr : X86Inst<"setle", 0x9E, MRMS0r, Arg8>, TB; // R8 = <= signed
311 def SETGr : X86Inst<"setg" , 0x9F, MRMS0r, Arg8>, TB; // R8 = < signed
313 // Conditional moves. These are modelled as X = cmovXX Y, Z. Eventually
314 // register allocated to cmovXX XY, Z
315 def CMOVErr16 : I2A16<"cmove", 0x44, MRMSrcReg>, TB, OpSize; // if ==, R16 = R16
316 def CMOVNErr32: I2A32<"cmovne",0x45, MRMSrcReg>, TB; // if !=, R32 = R32
318 // Integer comparisons
319 def CMPrr8 : X86Inst<"cmp", 0x38, MRMDestReg, Arg8 >; // compare R8, R8
320 def CMPrr16 : X86Inst<"cmp", 0x39, MRMDestReg, Arg16>, OpSize; // compare R16, R16
321 def CMPrr32 : X86Inst<"cmp", 0x39, MRMDestReg, Arg32>, // compare R32, R32
322 Pattern<(isVoid (unspec2 R32, R32))>;
323 def CMPri8 : X86Inst<"cmp", 0x80, MRMS7r , Arg8 >; // compare R8, imm8
324 def CMPri16 : X86Inst<"cmp", 0x81, MRMS7r , Arg16>, OpSize; // compare R16, imm16
325 def CMPri32 : X86Inst<"cmp", 0x81, MRMS7r , Arg32>; // compare R32, imm32
327 // Sign/Zero extenders
328 def MOVSXr16r8 : X86Inst<"movsx", 0xBE, MRMSrcReg, Arg8>, TB, OpSize; // R16 = signext(R8)
329 def MOVSXr32r8 : X86Inst<"movsx", 0xBE, MRMSrcReg, Arg8>, TB; // R32 = signext(R8)
330 def MOVSXr32r16: X86Inst<"movsx", 0xBF, MRMSrcReg, Arg8>, TB; // R32 = signext(R16)
331 def MOVZXr16r8 : X86Inst<"movzx", 0xB6, MRMSrcReg, Arg8>, TB, OpSize; // R16 = zeroext(R8)
332 def MOVZXr32r8 : X86Inst<"movzx", 0xB6, MRMSrcReg, Arg8>, TB; // R32 = zeroext(R8)
333 def MOVZXr32r16: X86Inst<"movzx", 0xB7, MRMSrcReg, Arg8>, TB; // R32 = zeroext(R16)
336 //===----------------------------------------------------------------------===//
337 // Floating point support
338 //===----------------------------------------------------------------------===//
340 // FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP'
342 // Floating point pseudo instructions...
343 class FPInst<string n, bits<8> o, Format F, ArgType t, FPFormat fp>
344 : X86Inst<n, o, F, t> { let FPForm = fp; let FPFormBits = FPForm.Value; }
346 def FpMOV : FPInst<"FMOV", 0, Pseudo, ArgF80, SpecialFP>; // f1 = fmov f2
347 def FpADD : FPInst<"FADD", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fadd f2, f3
348 def FpSUB : FPInst<"FSUB", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fsub f2, f3
349 def FpMUL : FPInst<"FMUL", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fmul f2, f3
350 def FpDIV : FPInst<"FDIV", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fdiv f2, f3
352 def FpUCOM : FPInst<"FUCOM", 0, Pseudo, ArgF80, TwoArgFP>; // FPSW = fucom f1, f2
354 def FpGETRESULT : FPInst<"FGETRESULT",0, Pseudo, ArgF80, SpecialFP>; // FPR = ST(0)
356 def FpSETRESULT : FPInst<"FSETRESULT",0, Pseudo, ArgF80, SpecialFP>; // ST(0) = FPR
358 // Floating point loads & stores...
359 def FLDrr : FPInst<"fld" , 0xC0, AddRegFrm, ArgF80, NotFP>, D9; // push(ST(i))
360 def FLDr32 : FPInst<"fld" , 0xD9, MRMS0m , ArgF32, ZeroArgFP>; // load float
361 def FLDr64 : FPInst<"fld" , 0xDD, MRMS0m , ArgF64, ZeroArgFP>; // load double
362 def FLDr80 : FPInst<"fld" , 0xDB, MRMS5m , ArgF80, ZeroArgFP>; // load extended
363 def FILDr16 : FPInst<"fild" , 0xDF, MRMS0m , Arg16 , ZeroArgFP>; // load signed short
364 def FILDr32 : FPInst<"fild" , 0xDB, MRMS0m , Arg32 , ZeroArgFP>; // load signed int
365 def FILDr64 : FPInst<"fild" , 0xDF, MRMS5m , Arg64 , ZeroArgFP>; // load signed long
367 def FSTr32 : FPInst<"fst" , 0xD9, MRMS2m , ArgF32, OneArgFP>; // store float
368 def FSTr64 : FPInst<"fst" , 0xDD, MRMS2m , ArgF64, OneArgFP>; // store double
369 def FSTPr32 : FPInst<"fstp", 0xD9, MRMS3m , ArgF32, OneArgFP>; // store float, pop
370 def FSTPr64 : FPInst<"fstp", 0xDD, MRMS3m , ArgF64, OneArgFP>; // store double, pop
371 def FSTPr80 : FPInst<"fstp", 0xDB, MRMS7m , ArgF80, OneArgFP>; // store extended, pop
372 def FSTrr : FPInst<"fst" , 0xD0, AddRegFrm, ArgF80, NotFP >, DD; // ST(i) = ST(0)
373 def FSTPrr : FPInst<"fstp", 0xD8, AddRegFrm, ArgF80, NotFP >, DD; // ST(i) = ST(0), pop
375 def FISTr16 : FPInst<"fist", 0xDF, MRMS2m, Arg16 , OneArgFP>; // store signed short
376 def FISTr32 : FPInst<"fist", 0xDB, MRMS2m, Arg32 , OneArgFP>; // store signed int
377 def FISTPr16 : FPInst<"fistp", 0xDF, MRMS3m, Arg16 , NotFP >; // store signed short, pop
378 def FISTPr32 : FPInst<"fistp", 0xDB, MRMS3m, Arg32 , NotFP >; // store signed int, pop
379 def FISTPr64 : FPInst<"fistpll", 0xDF, MRMS7m, Arg64 , OneArgFP>; // store signed long, pop
381 def FXCH : FPInst<"fxch", 0xC8, AddRegFrm, ArgF80, NotFP>, D9; // fxch ST(i), ST(0)
383 // Floating point constant loads...
384 def FLD0 : FPInst<"fldz", 0xEE, RawFrm, ArgF80, ZeroArgFP>, D9;
385 def FLD1 : FPInst<"fld1", 0xE8, RawFrm, ArgF80, ZeroArgFP>, D9;
387 // Binary arithmetic operations...
388 class FPST0rInst<string n, bits<8> o>
389 : X86Inst<n, o, AddRegFrm, ArgF80>, D8 {
390 list<Register> Uses = [ST0];
391 list<Register> Defs = [ST0];
393 class FPrST0Inst<string n, bits<8> o>
394 : X86Inst<n, o, AddRegFrm, ArgF80>, DC {
395 bit printImplicitUses = 1;
396 list<Register> Uses = [ST0];
398 class FPrST0PInst<string n, bits<8> o>
399 : X86Inst<n, o, AddRegFrm, ArgF80>, DE {
400 list<Register> Uses = [ST0];
403 def FADDST0r : FPST0rInst <"fadd", 0xC0>;
404 def FADDrST0 : FPrST0Inst <"fadd", 0xC0>;
405 def FADDPrST0 : FPrST0PInst<"faddp", 0xC0>;
407 def FSUBRST0r : FPST0rInst <"fsubr", 0xE8>;
408 def FSUBrST0 : FPrST0Inst <"fsub", 0xE8>;
409 def FSUBPrST0 : FPrST0PInst<"fsubp", 0xE8>;
411 def FSUBST0r : FPST0rInst <"fsub", 0xE0>;
412 def FSUBRrST0 : FPrST0Inst <"fsubr", 0xE0>;
413 def FSUBRPrST0 : FPrST0PInst<"fsubrp", 0xE0>;
415 def FMULST0r : FPST0rInst <"fmul", 0xC8>;
416 def FMULrST0 : FPrST0Inst <"fmul", 0xC8>;
417 def FMULPrST0 : FPrST0PInst<"fmulp", 0xC8>;
419 def FDIVRST0r : FPST0rInst <"fdivr", 0xF8>;
420 def FDIVrST0 : FPrST0Inst <"fdiv", 0xF8>;
421 def FDIVPrST0 : FPrST0PInst<"fdivp", 0xF8>;
423 def FDIVST0r : FPST0rInst <"fdiv", 0xF0>; // ST(0) = ST(0) / ST(i)
424 def FDIVRrST0 : FPrST0Inst <"fdivr", 0xF0>; // ST(i) = ST(0) / ST(i)
425 def FDIVRPrST0 : FPrST0PInst<"fdivrp", 0xF0>; // ST(i) = ST(0) / ST(i), pop
427 // Floating point compares
428 def FUCOMr : X86Inst<"fucom" , 0xE0, AddRegFrm, ArgF80>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i)
429 def FUCOMPr : X86Inst<"fucomp" , 0xE8, AddRegFrm, ArgF80>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i), pop
430 def FUCOMPPr : X86Inst<"fucompp", 0xE9, RawFrm , ArgF80>, DA, Imp<[ST0],[]>; // compare ST(0) with ST(1), pop, pop
432 // Floating point flag ops
433 def FNSTSWr8 : X86Inst<"fnstsw" , 0xE0, RawFrm , ArgF80>, DF, Imp<[],[AX]>; // AX = fp flags
434 def FNSTCWm16 : X86Inst<"fnstcw" , 0xD9, MRMS7m , Arg16 >; // [mem16] = X87 control world
435 def FLDCWm16 : X86Inst<"fldcw" , 0xD9, MRMS5m , Arg16 >; // X87 control world = [mem16]
438 //===----------------------------------------------------------------------===//
439 // Instruction Expanders
442 def RET_R32 : Expander<(ret R32:$reg),
443 [(MOVrr32 EAX, R32:$reg),
446 // FIXME: This should eventually just be implemented by defining a frameidx as a
447 // value address for a load.
448 def LOAD_FI16 : Expander<(set R16:$dest, (load frameidx:$fi)),
449 [(MOVmr16 R16:$dest, frameidx:$fi, 1, 0/*NoReg*/, 0)]>;
451 def LOAD_FI32 : Expander<(set R32:$dest, (load frameidx:$fi)),
452 [(MOVmr32 R32:$dest, frameidx:$fi, 1, 0/*NoReg*/, 0)]>;
455 def LOAD_R16 : Expander<(set R16:$dest, (load R32:$src)),
456 [(MOVmr16 R16:$dest, R32:$src, 1, 0/*NoReg*/, 0)]>;
458 def LOAD_R32 : Expander<(set R32:$dest, (load R32:$src)),
459 [(MOVmr32 R32:$dest, R32:$src, 1, 0/*NoReg*/, 0)]>;
461 def BR_EQ : Expander<(brcond (seteq R32:$a1, R32:$a2),
462 basicblock:$d1, basicblock:$d2),
463 [(CMPrr32 R32:$a1, R32:$a2),
465 (JMP basicblock:$d2)]>;