1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 //def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
36 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
41 SDTCisInt<0>, SDTCisVT<1, i32>]>;
43 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
44 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
50 // RES1, RES2, FLAGS = op LHS, RHS
51 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
55 SDTCisInt<0>, SDTCisVT<1, i32>]>;
56 def SDTX86BrCond : SDTypeProfile<0, 3,
57 [SDTCisVT<0, OtherVT>,
58 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
60 def SDTX86SetCC : SDTypeProfile<1, 2,
62 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
63 def SDTX86SetCC_C : SDTypeProfile<1, 2,
65 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
67 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
69 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
71 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
73 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
75 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
76 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
77 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
79 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
80 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
83 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
85 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
89 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
95 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
97 def SDTX86Void : SDTypeProfile<0, 0, []>;
99 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
101 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
103 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
105 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
107 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
109 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
111 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
113 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
115 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
117 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
118 [SDNPHasChain,SDNPSideEffect]>;
119 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
121 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
123 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
127 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
128 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
129 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
130 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
132 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
133 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
135 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
136 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
138 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
139 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
141 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
143 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
144 [SDNPHasChain, SDNPSideEffect]>;
146 def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand,
147 [SDNPHasChain, SDNPSideEffect]>;
149 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
150 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
151 SDNPMayLoad, SDNPMemOperand]>;
152 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
153 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
154 SDNPMayLoad, SDNPMemOperand]>;
155 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
156 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
157 SDNPMayLoad, SDNPMemOperand]>;
159 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
160 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
162 def X86vastart_save_xmm_regs :
163 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
164 SDT_X86VASTART_SAVE_XMM_REGS,
165 [SDNPHasChain, SDNPVariadic]>;
167 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
168 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
170 def X86callseq_start :
171 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
172 [SDNPHasChain, SDNPOutGlue]>;
174 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
175 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
177 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
178 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
181 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
182 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
183 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
184 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
187 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
188 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
189 def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void,
190 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
191 def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void,
192 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
194 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
195 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
197 def X86RecoverFrameAlloc : SDNode<"ISD::FRAME_ALLOC_RECOVER",
198 SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
201 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
202 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
204 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
205 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
207 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
210 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
211 SDTypeProfile<1, 1, [SDTCisInt<0>,
213 [SDNPHasChain, SDNPSideEffect]>;
214 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
215 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
216 [SDNPHasChain, SDNPSideEffect]>;
218 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
219 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
221 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
223 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
224 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
226 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
228 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
229 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
231 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
232 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
233 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
235 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
237 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
240 def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>;
242 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
244 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
245 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
247 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
250 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
251 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
253 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL,
254 [SDNPHasChain, SDNPOutGlue]>;
256 //===----------------------------------------------------------------------===//
257 // X86 Operand Definitions.
260 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
261 // the index operand of an address, to conform to x86 encoding restrictions.
262 def ptr_rc_nosp : PointerLikeRegClass<1>;
264 // *mem - Operand definitions for the funky X86 addressing mode operands.
266 def X86MemAsmOperand : AsmOperandClass {
269 let RenderMethod = "addMemOperands" in {
270 def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; }
271 def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; }
272 def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; }
273 def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; }
274 def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; }
275 def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; }
276 def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; }
277 def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; }
278 // Gather mem operands
279 def X86MemVX32Operand : AsmOperandClass { let Name = "MemVX32"; }
280 def X86MemVY32Operand : AsmOperandClass { let Name = "MemVY32"; }
281 def X86MemVZ32Operand : AsmOperandClass { let Name = "MemVZ32"; }
282 def X86MemVX64Operand : AsmOperandClass { let Name = "MemVX64"; }
283 def X86MemVY64Operand : AsmOperandClass { let Name = "MemVY64"; }
284 def X86MemVZ64Operand : AsmOperandClass { let Name = "MemVZ64"; }
285 def X86MemVX32XOperand : AsmOperandClass { let Name = "MemVX32X"; }
286 def X86MemVY32XOperand : AsmOperandClass { let Name = "MemVY32X"; }
287 def X86MemVX64XOperand : AsmOperandClass { let Name = "MemVX64X"; }
288 def X86MemVY64XOperand : AsmOperandClass { let Name = "MemVY64X"; }
291 def X86AbsMemAsmOperand : AsmOperandClass {
293 let SuperClasses = [X86MemAsmOperand];
296 class X86MemOperand<string printMethod,
297 AsmOperandClass parserMatchClass = X86MemAsmOperand> : Operand<iPTR> {
298 let PrintMethod = printMethod;
299 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
300 let ParserMatchClass = parserMatchClass;
301 let OperandType = "OPERAND_MEMORY";
304 // Gather mem operands
305 class X86VMemOperand<RegisterClass RC, string printMethod,
306 AsmOperandClass parserMatchClass>
307 : X86MemOperand<printMethod, parserMatchClass> {
308 let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, i8imm);
311 def anymem : X86MemOperand<"printanymem">;
313 def opaque32mem : X86MemOperand<"printopaquemem">;
314 def opaque48mem : X86MemOperand<"printopaquemem">;
315 def opaque80mem : X86MemOperand<"printopaquemem">;
316 def opaque512mem : X86MemOperand<"printopaquemem">;
318 def i8mem : X86MemOperand<"printi8mem", X86Mem8AsmOperand>;
319 def i16mem : X86MemOperand<"printi16mem", X86Mem16AsmOperand>;
320 def i32mem : X86MemOperand<"printi32mem", X86Mem32AsmOperand>;
321 def i64mem : X86MemOperand<"printi64mem", X86Mem64AsmOperand>;
322 def i128mem : X86MemOperand<"printi128mem", X86Mem128AsmOperand>;
323 def i256mem : X86MemOperand<"printi256mem", X86Mem256AsmOperand>;
324 def i512mem : X86MemOperand<"printi512mem", X86Mem512AsmOperand>;
325 def f32mem : X86MemOperand<"printf32mem", X86Mem32AsmOperand>;
326 def f64mem : X86MemOperand<"printf64mem", X86Mem64AsmOperand>;
327 def f80mem : X86MemOperand<"printf80mem", X86Mem80AsmOperand>;
328 def f128mem : X86MemOperand<"printf128mem", X86Mem128AsmOperand>;
329 def f256mem : X86MemOperand<"printf256mem", X86Mem256AsmOperand>;
330 def f512mem : X86MemOperand<"printf512mem", X86Mem512AsmOperand>;
332 def v512mem : X86VMemOperand<VR512, "printf512mem", X86Mem512AsmOperand>;
334 // Gather mem operands
335 def vx32mem : X86VMemOperand<VR128, "printi32mem", X86MemVX32Operand>;
336 def vy32mem : X86VMemOperand<VR256, "printi32mem", X86MemVY32Operand>;
337 def vx64mem : X86VMemOperand<VR128, "printi64mem", X86MemVX64Operand>;
338 def vy64mem : X86VMemOperand<VR256, "printi64mem", X86MemVY64Operand>;
340 def vx32xmem : X86VMemOperand<VR128X, "printi32mem", X86MemVX32XOperand>;
341 def vx64xmem : X86VMemOperand<VR128X, "printi32mem", X86MemVX64XOperand>;
342 def vy32xmem : X86VMemOperand<VR256X, "printi32mem", X86MemVY32XOperand>;
343 def vy64xmem : X86VMemOperand<VR256X, "printi64mem", X86MemVY64XOperand>;
344 def vz32mem : X86VMemOperand<VR512, "printi32mem", X86MemVZ32Operand>;
345 def vz64mem : X86VMemOperand<VR512, "printi64mem", X86MemVZ64Operand>;
347 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
348 // plain GR64, so that it doesn't potentially require a REX prefix.
349 def i8mem_NOREX : Operand<i64> {
350 let PrintMethod = "printi8mem";
351 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
352 let ParserMatchClass = X86Mem8AsmOperand;
353 let OperandType = "OPERAND_MEMORY";
356 // GPRs available for tailcall.
357 // It represents GR32_TC, GR64_TC or GR64_TCW64.
358 def ptr_rc_tailcall : PointerLikeRegClass<2>;
360 // Special i32mem for addresses of load folding tail calls. These are not
361 // allowed to use callee-saved registers since they must be scheduled
362 // after callee-saved register are popped.
363 def i32mem_TC : Operand<i32> {
364 let PrintMethod = "printi32mem";
365 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
367 let ParserMatchClass = X86Mem32AsmOperand;
368 let OperandType = "OPERAND_MEMORY";
371 // Special i64mem for addresses of load folding tail calls. These are not
372 // allowed to use callee-saved registers since they must be scheduled
373 // after callee-saved register are popped.
374 def i64mem_TC : Operand<i64> {
375 let PrintMethod = "printi64mem";
376 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
377 ptr_rc_tailcall, i32imm, i8imm);
378 let ParserMatchClass = X86Mem64AsmOperand;
379 let OperandType = "OPERAND_MEMORY";
382 let OperandType = "OPERAND_PCREL",
383 ParserMatchClass = X86AbsMemAsmOperand,
384 PrintMethod = "printPCRelImm" in {
385 def i32imm_pcrel : Operand<i32>;
386 def i16imm_pcrel : Operand<i16>;
388 // Branch targets have OtherVT type and print as pc-relative values.
389 def brtarget : Operand<OtherVT>;
390 def brtarget8 : Operand<OtherVT>;
394 // Special parser to detect 16-bit mode to select 16-bit displacement.
395 def X86AbsMem16AsmOperand : AsmOperandClass {
396 let Name = "AbsMem16";
397 let RenderMethod = "addAbsMemOperands";
398 let SuperClasses = [X86AbsMemAsmOperand];
401 // Branch targets have OtherVT type and print as pc-relative values.
402 let OperandType = "OPERAND_PCREL",
403 PrintMethod = "printPCRelImm" in {
404 let ParserMatchClass = X86AbsMem16AsmOperand in
405 def brtarget16 : Operand<OtherVT>;
406 let ParserMatchClass = X86AbsMemAsmOperand in
407 def brtarget32 : Operand<OtherVT>;
410 let RenderMethod = "addSrcIdxOperands" in {
411 def X86SrcIdx8Operand : AsmOperandClass {
412 let Name = "SrcIdx8";
413 let SuperClasses = [X86Mem8AsmOperand];
415 def X86SrcIdx16Operand : AsmOperandClass {
416 let Name = "SrcIdx16";
417 let SuperClasses = [X86Mem16AsmOperand];
419 def X86SrcIdx32Operand : AsmOperandClass {
420 let Name = "SrcIdx32";
421 let SuperClasses = [X86Mem32AsmOperand];
423 def X86SrcIdx64Operand : AsmOperandClass {
424 let Name = "SrcIdx64";
425 let SuperClasses = [X86Mem64AsmOperand];
427 } // RenderMethod = "addSrcIdxOperands"
429 let RenderMethod = "addDstIdxOperands" in {
430 def X86DstIdx8Operand : AsmOperandClass {
431 let Name = "DstIdx8";
432 let SuperClasses = [X86Mem8AsmOperand];
434 def X86DstIdx16Operand : AsmOperandClass {
435 let Name = "DstIdx16";
436 let SuperClasses = [X86Mem16AsmOperand];
438 def X86DstIdx32Operand : AsmOperandClass {
439 let Name = "DstIdx32";
440 let SuperClasses = [X86Mem32AsmOperand];
442 def X86DstIdx64Operand : AsmOperandClass {
443 let Name = "DstIdx64";
444 let SuperClasses = [X86Mem64AsmOperand];
446 } // RenderMethod = "addDstIdxOperands"
448 let RenderMethod = "addMemOffsOperands" in {
449 def X86MemOffs16_8AsmOperand : AsmOperandClass {
450 let Name = "MemOffs16_8";
451 let SuperClasses = [X86Mem8AsmOperand];
453 def X86MemOffs16_16AsmOperand : AsmOperandClass {
454 let Name = "MemOffs16_16";
455 let SuperClasses = [X86Mem16AsmOperand];
457 def X86MemOffs16_32AsmOperand : AsmOperandClass {
458 let Name = "MemOffs16_32";
459 let SuperClasses = [X86Mem32AsmOperand];
461 def X86MemOffs32_8AsmOperand : AsmOperandClass {
462 let Name = "MemOffs32_8";
463 let SuperClasses = [X86Mem8AsmOperand];
465 def X86MemOffs32_16AsmOperand : AsmOperandClass {
466 let Name = "MemOffs32_16";
467 let SuperClasses = [X86Mem16AsmOperand];
469 def X86MemOffs32_32AsmOperand : AsmOperandClass {
470 let Name = "MemOffs32_32";
471 let SuperClasses = [X86Mem32AsmOperand];
473 def X86MemOffs32_64AsmOperand : AsmOperandClass {
474 let Name = "MemOffs32_64";
475 let SuperClasses = [X86Mem64AsmOperand];
477 def X86MemOffs64_8AsmOperand : AsmOperandClass {
478 let Name = "MemOffs64_8";
479 let SuperClasses = [X86Mem8AsmOperand];
481 def X86MemOffs64_16AsmOperand : AsmOperandClass {
482 let Name = "MemOffs64_16";
483 let SuperClasses = [X86Mem16AsmOperand];
485 def X86MemOffs64_32AsmOperand : AsmOperandClass {
486 let Name = "MemOffs64_32";
487 let SuperClasses = [X86Mem32AsmOperand];
489 def X86MemOffs64_64AsmOperand : AsmOperandClass {
490 let Name = "MemOffs64_64";
491 let SuperClasses = [X86Mem64AsmOperand];
493 } // RenderMethod = "addMemOffsOperands"
495 class X86SrcIdxOperand<string printMethod, AsmOperandClass parserMatchClass>
496 : X86MemOperand<printMethod, parserMatchClass> {
497 let MIOperandInfo = (ops ptr_rc, i8imm);
500 class X86DstIdxOperand<string printMethod, AsmOperandClass parserMatchClass>
501 : X86MemOperand<printMethod, parserMatchClass> {
502 let MIOperandInfo = (ops ptr_rc);
505 def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>;
506 def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>;
507 def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>;
508 def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>;
509 def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>;
510 def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>;
511 def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>;
512 def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>;
514 class X86MemOffsOperand<Operand immOperand, string printMethod,
515 AsmOperandClass parserMatchClass>
516 : X86MemOperand<printMethod, parserMatchClass> {
517 let MIOperandInfo = (ops immOperand, i8imm);
520 def offset16_8 : X86MemOffsOperand<i16imm, "printMemOffs8",
521 X86MemOffs16_8AsmOperand>;
522 def offset16_16 : X86MemOffsOperand<i16imm, "printMemOffs16",
523 X86MemOffs16_16AsmOperand>;
524 def offset16_32 : X86MemOffsOperand<i16imm, "printMemOffs32",
525 X86MemOffs16_32AsmOperand>;
526 def offset32_8 : X86MemOffsOperand<i32imm, "printMemOffs8",
527 X86MemOffs32_8AsmOperand>;
528 def offset32_16 : X86MemOffsOperand<i32imm, "printMemOffs16",
529 X86MemOffs32_16AsmOperand>;
530 def offset32_32 : X86MemOffsOperand<i32imm, "printMemOffs32",
531 X86MemOffs32_32AsmOperand>;
532 def offset32_64 : X86MemOffsOperand<i32imm, "printMemOffs64",
533 X86MemOffs32_64AsmOperand>;
534 def offset64_8 : X86MemOffsOperand<i64imm, "printMemOffs8",
535 X86MemOffs64_8AsmOperand>;
536 def offset64_16 : X86MemOffsOperand<i64imm, "printMemOffs16",
537 X86MemOffs64_16AsmOperand>;
538 def offset64_32 : X86MemOffsOperand<i64imm, "printMemOffs32",
539 X86MemOffs64_32AsmOperand>;
540 def offset64_64 : X86MemOffsOperand<i64imm, "printMemOffs64",
541 X86MemOffs64_64AsmOperand>;
543 def SSECC : Operand<i8> {
544 let PrintMethod = "printSSEAVXCC";
545 let OperandType = "OPERAND_IMMEDIATE";
548 def i8immZExt3 : ImmLeaf<i8, [{
549 return Imm >= 0 && Imm < 8;
552 def AVXCC : Operand<i8> {
553 let PrintMethod = "printSSEAVXCC";
554 let OperandType = "OPERAND_IMMEDIATE";
557 def i8immZExt5 : ImmLeaf<i8, [{
558 return Imm >= 0 && Imm < 32;
561 def AVX512ICC : Operand<i8> {
562 let PrintMethod = "printSSEAVXCC";
563 let OperandType = "OPERAND_IMMEDIATE";
566 def XOPCC : Operand<i8> {
567 let PrintMethod = "printXOPCC";
568 let OperandType = "OPERAND_IMMEDIATE";
571 class ImmSExtAsmOperandClass : AsmOperandClass {
572 let SuperClasses = [ImmAsmOperand];
573 let RenderMethod = "addImmOperands";
576 def X86GR32orGR64AsmOperand : AsmOperandClass {
577 let Name = "GR32orGR64";
580 def GR32orGR64 : RegisterOperand<GR32> {
581 let ParserMatchClass = X86GR32orGR64AsmOperand;
583 def AVX512RCOperand : AsmOperandClass {
584 let Name = "AVX512RC";
586 def AVX512RC : Operand<i32> {
587 let PrintMethod = "printRoundingControl";
588 let OperandType = "OPERAND_IMMEDIATE";
589 let ParserMatchClass = AVX512RCOperand;
592 // Sign-extended immediate classes. We don't need to define the full lattice
593 // here because there is no instruction with an ambiguity between ImmSExti64i32
596 // The strange ranges come from the fact that the assembler always works with
597 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
598 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
601 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
602 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
603 let Name = "ImmSExti64i32";
606 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
607 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
608 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
609 let Name = "ImmSExti16i8";
610 let SuperClasses = [ImmSExti64i32AsmOperand];
613 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
614 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
615 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
616 let Name = "ImmSExti32i8";
620 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
621 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
622 let Name = "ImmSExti64i8";
623 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
624 ImmSExti64i32AsmOperand];
627 // Unsigned immediate used by SSE/AVX instructions
629 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
630 def ImmUnsignedi8AsmOperand : AsmOperandClass {
631 let Name = "ImmUnsignedi8";
632 let RenderMethod = "addImmOperands";
635 // A couple of more descriptive operand definitions.
636 // 16-bits but only 8 bits are significant.
637 def i16i8imm : Operand<i16> {
638 let ParserMatchClass = ImmSExti16i8AsmOperand;
639 let OperandType = "OPERAND_IMMEDIATE";
641 // 32-bits but only 8 bits are significant.
642 def i32i8imm : Operand<i32> {
643 let ParserMatchClass = ImmSExti32i8AsmOperand;
644 let OperandType = "OPERAND_IMMEDIATE";
647 // 64-bits but only 32 bits are significant.
648 def i64i32imm : Operand<i64> {
649 let ParserMatchClass = ImmSExti64i32AsmOperand;
650 let OperandType = "OPERAND_IMMEDIATE";
653 // 64-bits but only 8 bits are significant.
654 def i64i8imm : Operand<i64> {
655 let ParserMatchClass = ImmSExti64i8AsmOperand;
656 let OperandType = "OPERAND_IMMEDIATE";
659 // Unsigned 8-bit immediate used by SSE/AVX instructions.
660 def u8imm : Operand<i8> {
661 let PrintMethod = "printU8Imm";
662 let ParserMatchClass = ImmUnsignedi8AsmOperand;
663 let OperandType = "OPERAND_IMMEDIATE";
666 // 32-bit immediate but only 8-bits are significant and they are unsigned.
667 // Used by some SSE/AVX instructions that use intrinsics.
668 def i32u8imm : Operand<i32> {
669 let PrintMethod = "printU8Imm";
670 let ParserMatchClass = ImmUnsignedi8AsmOperand;
671 let OperandType = "OPERAND_IMMEDIATE";
674 // 64-bits but only 32 bits are significant, and those bits are treated as being
676 def i64i32imm_pcrel : Operand<i64> {
677 let PrintMethod = "printPCRelImm";
678 let ParserMatchClass = X86AbsMemAsmOperand;
679 let OperandType = "OPERAND_PCREL";
682 def lea64_32mem : Operand<i32> {
683 let PrintMethod = "printanymem";
684 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
685 let ParserMatchClass = X86MemAsmOperand;
688 // Memory operands that use 64-bit pointers in both ILP32 and LP64.
689 def lea64mem : Operand<i64> {
690 let PrintMethod = "printanymem";
691 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
692 let ParserMatchClass = X86MemAsmOperand;
696 //===----------------------------------------------------------------------===//
697 // X86 Complex Pattern Definitions.
700 // Define X86 specific addressing mode.
701 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
702 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
703 [add, sub, mul, X86mul_imm, shl, or, frameindex],
705 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
706 def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr",
707 [add, sub, mul, X86mul_imm, shl, or,
708 frameindex, X86WrapperRIP],
711 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
712 [tglobaltlsaddr], []>;
714 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
715 [tglobaltlsaddr], []>;
717 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
718 [add, sub, mul, X86mul_imm, shl, or, frameindex,
721 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
722 [tglobaltlsaddr], []>;
724 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
725 [tglobaltlsaddr], []>;
727 def vectoraddr : ComplexPattern<iPTR, 5, "SelectVectorAddr", [],[SDNPWantParent]>;
729 //===----------------------------------------------------------------------===//
730 // X86 Instruction Predicate Definitions.
731 def HasCMov : Predicate<"Subtarget->hasCMov()">;
732 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
734 def HasMMX : Predicate<"Subtarget->hasMMX()">;
735 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
736 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
737 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
738 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
739 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
740 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
741 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
742 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
743 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
744 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
745 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
746 def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">;
747 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
748 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
749 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
750 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
751 def HasAVX : Predicate<"Subtarget->hasAVX()">;
752 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
753 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
754 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">,
755 AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">;
756 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
757 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
758 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
759 def HasCDI : Predicate<"Subtarget->hasCDI()">,
760 AssemblerPredicate<"FeatureCDI", "AVX-512 CD ISA">;
761 def HasPFI : Predicate<"Subtarget->hasPFI()">,
762 AssemblerPredicate<"FeaturePFI", "AVX-512 PF ISA">;
763 def HasERI : Predicate<"Subtarget->hasERI()">,
764 AssemblerPredicate<"FeatureERI", "AVX-512 ER ISA">;
765 def HasDQI : Predicate<"Subtarget->hasDQI()">,
766 AssemblerPredicate<"FeatureDQI", "AVX-512 DQ ISA">;
767 def NoDQI : Predicate<"!Subtarget->hasDQI()">;
768 def HasBWI : Predicate<"Subtarget->hasBWI()">,
769 AssemblerPredicate<"FeatureBWI", "AVX-512 BW ISA">;
770 def HasVLX : Predicate<"Subtarget->hasVLX()">,
771 AssemblerPredicate<"FeatureVLX", "AVX-512 VL ISA">;
772 def NoVLX : Predicate<"!Subtarget->hasVLX()">;
774 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
775 def HasAES : Predicate<"Subtarget->hasAES()">;
776 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
777 def HasFMA : Predicate<"Subtarget->hasFMA()">;
778 def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">;
779 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
780 def HasXOP : Predicate<"Subtarget->hasXOP()">;
781 def HasTBM : Predicate<"Subtarget->hasTBM()">;
782 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
783 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
784 def HasF16C : Predicate<"Subtarget->hasF16C()">;
785 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
786 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
787 def HasBMI : Predicate<"Subtarget->hasBMI()">;
788 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
789 def HasRTM : Predicate<"Subtarget->hasRTM()">;
790 def HasHLE : Predicate<"Subtarget->hasHLE()">;
791 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
792 def HasADX : Predicate<"Subtarget->hasADX()">;
793 def HasSHA : Predicate<"Subtarget->hasSHA()">;
794 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
795 def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
796 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
797 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
798 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
799 def HasMPX : Predicate<"Subtarget->hasMPX()">;
800 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
801 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
802 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
803 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
804 AssemblerPredicate<"Mode64Bit", "64-bit mode">;
805 def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">;
806 def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">;
807 def In16BitMode : Predicate<"Subtarget->is16Bit()">,
808 AssemblerPredicate<"Mode16Bit", "16-bit mode">;
809 def Not16BitMode : Predicate<"!Subtarget->is16Bit()">,
810 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">;
811 def In32BitMode : Predicate<"Subtarget->is32Bit()">,
812 AssemblerPredicate<"Mode32Bit", "32-bit mode">;
813 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
814 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
815 def IsPS4 : Predicate<"Subtarget->isTargetPS4()">;
816 def NotPS4 : Predicate<"!Subtarget->isTargetPS4()">;
817 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
818 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
819 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
820 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
821 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
822 "TM.getCodeModel() != CodeModel::Kernel">;
823 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
824 "TM.getCodeModel() == CodeModel::Kernel">;
825 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
826 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
827 def OptForSize : Predicate<"OptForSize">;
828 def OptForSpeed : Predicate<"!OptForSize">;
829 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
830 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
831 def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">;
832 def NotSlowIncDec : Predicate<"!Subtarget->slowIncDec()">;
833 def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">;
835 //===----------------------------------------------------------------------===//
836 // X86 Instruction Format Definitions.
839 include "X86InstrFormats.td"
841 //===----------------------------------------------------------------------===//
842 // Pattern fragments.
845 // X86 specific condition code. These correspond to CondCode in
846 // X86InstrInfo.h. They must be kept in synch.
847 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
848 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
849 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
850 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
851 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
852 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
853 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
854 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
855 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
856 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
857 def X86_COND_NO : PatLeaf<(i8 10)>;
858 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
859 def X86_COND_NS : PatLeaf<(i8 12)>;
860 def X86_COND_O : PatLeaf<(i8 13)>;
861 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
862 def X86_COND_S : PatLeaf<(i8 15)>;
864 // Predicate used to help when pattern matching LZCNT/TZCNT.
865 def X86_COND_E_OR_NE : ImmLeaf<i8, [{
866 return (Imm == X86::COND_E) || (Imm == X86::COND_NE);
870 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
871 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
872 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
875 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
878 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
880 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
882 def i64immZExt32SExt8 : ImmLeaf<i64, [{
883 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
886 // Helper fragments for loads.
887 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
888 // known to be 32-bit aligned or better. Ditto for i8 to i16.
889 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
890 LoadSDNode *LD = cast<LoadSDNode>(N);
891 ISD::LoadExtType ExtType = LD->getExtensionType();
892 if (ExtType == ISD::NON_EXTLOAD)
894 if (ExtType == ISD::EXTLOAD)
895 return LD->getAlignment() >= 2 && !LD->isVolatile();
899 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
900 LoadSDNode *LD = cast<LoadSDNode>(N);
901 ISD::LoadExtType ExtType = LD->getExtensionType();
902 if (ExtType == ISD::EXTLOAD)
903 return LD->getAlignment() >= 2 && !LD->isVolatile();
907 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
908 LoadSDNode *LD = cast<LoadSDNode>(N);
909 ISD::LoadExtType ExtType = LD->getExtensionType();
910 if (ExtType == ISD::NON_EXTLOAD)
912 if (ExtType == ISD::EXTLOAD)
913 return LD->getAlignment() >= 4 && !LD->isVolatile();
917 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
918 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
919 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
920 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
921 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
923 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
924 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
925 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
926 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
927 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
928 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
930 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
931 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
932 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
933 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
934 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
935 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
936 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
937 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
938 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
939 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
941 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
942 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
943 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
944 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
945 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
946 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
947 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
948 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
949 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
950 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
953 // An 'and' node with a single use.
954 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
955 return N->hasOneUse();
957 // An 'srl' node with a single use.
958 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
959 return N->hasOneUse();
961 // An 'trunc' node with a single use.
962 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
963 return N->hasOneUse();
966 //===----------------------------------------------------------------------===//
971 let hasSideEffects = 0, SchedRW = [WriteZero] in {
972 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
973 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero),
974 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
975 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero),
976 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
980 // Constructing a stack frame.
981 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
982 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
984 let SchedRW = [WriteALU] in {
985 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in
986 def LEAVE : I<0xC9, RawFrm,
987 (outs), (ins), "leave", [], IIC_LEAVE>,
988 Requires<[Not64BitMode]>;
990 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in
991 def LEAVE64 : I<0xC9, RawFrm,
992 (outs), (ins), "leave", [], IIC_LEAVE>,
993 Requires<[In64BitMode]>;
996 //===----------------------------------------------------------------------===//
997 // Miscellaneous Instructions.
1000 let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in {
1001 let mayLoad = 1, SchedRW = [WriteLoad] in {
1002 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
1003 IIC_POP_REG16>, OpSize16;
1004 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
1005 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
1006 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
1007 IIC_POP_REG>, OpSize16;
1008 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
1009 IIC_POP_MEM>, OpSize16;
1010 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
1011 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
1012 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
1013 IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>;
1014 } // mayLoad, SchedRW
1016 let mayStore = 1, SchedRW = [WriteStore] in {
1017 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
1018 IIC_PUSH_REG>, OpSize16;
1019 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
1020 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
1021 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
1022 IIC_PUSH_REG>, OpSize16;
1023 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
1024 IIC_PUSH_MEM>, OpSize16;
1025 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
1026 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
1027 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
1028 IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>;
1030 def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
1031 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1032 Requires<[Not64BitMode]>;
1033 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
1034 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1035 Requires<[Not64BitMode]>;
1036 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1037 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1038 Requires<[Not64BitMode]>;
1039 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
1040 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1041 Requires<[Not64BitMode]>;
1042 } // mayStore, SchedRW
1045 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
1046 SchedRW = [WriteLoad] in {
1047 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>,
1049 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
1050 OpSize32, Requires<[Not64BitMode]>;
1053 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0,
1054 SchedRW = [WriteStore] in {
1055 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
1057 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
1058 OpSize32, Requires<[Not64BitMode]>;
1061 let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in {
1062 let mayLoad = 1, SchedRW = [WriteLoad] in {
1063 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1064 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
1065 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1066 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
1067 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [],
1068 IIC_POP_MEM>, OpSize32, Requires<[In64BitMode]>;
1069 } // mayLoad, SchedRW
1070 let mayStore = 1, SchedRW = [WriteStore] in {
1071 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1072 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1073 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1074 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1075 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
1076 IIC_PUSH_MEM>, OpSize32, Requires<[In64BitMode]>;
1077 } // mayStore, SchedRW
1080 let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1,
1081 SchedRW = [WriteStore] in {
1082 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
1083 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
1084 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1085 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1086 Requires<[In64BitMode]>;
1087 def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
1088 "push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1089 Requires<[In64BitMode]>;
1092 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
1093 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
1094 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>;
1095 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in
1096 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
1097 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>;
1099 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
1100 mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in {
1101 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>,
1102 OpSize32, Requires<[Not64BitMode]>;
1103 def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>,
1104 OpSize16, Requires<[Not64BitMode]>;
1106 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
1107 mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
1108 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>,
1109 OpSize32, Requires<[Not64BitMode]>;
1110 def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>,
1111 OpSize16, Requires<[Not64BitMode]>;
1114 let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
1115 // GR32 = bswap GR32
1116 def BSWAP32r : I<0xC8, AddRegFrm,
1117 (outs GR32:$dst), (ins GR32:$src),
1119 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB;
1121 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
1123 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
1124 } // Constraints = "$src = $dst", SchedRW
1126 // Bit scan instructions.
1127 let Defs = [EFLAGS] in {
1128 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1129 "bsf{w}\t{$src, $dst|$dst, $src}",
1130 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
1131 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1132 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1133 "bsf{w}\t{$src, $dst|$dst, $src}",
1134 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
1135 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1136 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1137 "bsf{l}\t{$src, $dst|$dst, $src}",
1138 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
1139 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1140 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1141 "bsf{l}\t{$src, $dst|$dst, $src}",
1142 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
1143 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1144 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1145 "bsf{q}\t{$src, $dst|$dst, $src}",
1146 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
1147 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1148 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1149 "bsf{q}\t{$src, $dst|$dst, $src}",
1150 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
1151 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1153 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1154 "bsr{w}\t{$src, $dst|$dst, $src}",
1155 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))],
1156 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1157 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1158 "bsr{w}\t{$src, $dst|$dst, $src}",
1159 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
1160 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1161 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1162 "bsr{l}\t{$src, $dst|$dst, $src}",
1163 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
1164 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1165 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1166 "bsr{l}\t{$src, $dst|$dst, $src}",
1167 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
1168 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1169 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1170 "bsr{q}\t{$src, $dst|$dst, $src}",
1171 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))],
1172 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1173 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1174 "bsr{q}\t{$src, $dst|$dst, $src}",
1175 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
1176 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1177 } // Defs = [EFLAGS]
1179 let SchedRW = [WriteMicrocoded] in {
1180 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1181 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
1182 def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src),
1183 "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1184 def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src),
1185 "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16;
1186 def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src),
1187 "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize32;
1188 def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src),
1189 "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1192 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1193 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
1194 def STOSB : I<0xAA, RawFrmDst, (outs dstidx8:$dst), (ins),
1195 "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>;
1196 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
1197 def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins),
1198 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16;
1199 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
1200 def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins),
1201 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32;
1202 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
1203 def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins),
1204 "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>;
1206 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1207 let Defs = [EDI,EFLAGS], Uses = [AL,EDI,EFLAGS] in
1208 def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst),
1209 "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>;
1210 let Defs = [EDI,EFLAGS], Uses = [AX,EDI,EFLAGS] in
1211 def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst),
1212 "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16;
1213 let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,EFLAGS] in
1214 def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst),
1215 "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32;
1216 let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,EFLAGS] in
1217 def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst),
1218 "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>;
1220 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1221 let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,EFLAGS] in {
1222 def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src),
1223 "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1224 def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src),
1225 "cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16;
1226 def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src),
1227 "cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize32;
1228 def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src),
1229 "cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1233 //===----------------------------------------------------------------------===//
1234 // Move Instructions.
1236 let SchedRW = [WriteMove] in {
1237 let hasSideEffects = 0 in {
1238 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1239 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1240 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1241 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1242 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1243 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1244 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1245 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1248 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1249 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1250 "mov{b}\t{$src, $dst|$dst, $src}",
1251 [(set GR8:$dst, imm:$src)], IIC_MOV>;
1252 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1253 "mov{w}\t{$src, $dst|$dst, $src}",
1254 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize16;
1255 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1256 "mov{l}\t{$src, $dst|$dst, $src}",
1257 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize32;
1258 def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1259 "mov{q}\t{$src, $dst|$dst, $src}",
1260 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
1262 let isReMaterializable = 1 in {
1263 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
1264 "movabs{q}\t{$src, $dst|$dst, $src}",
1265 [(set GR64:$dst, imm:$src)], IIC_MOV>;
1268 // Longer forms that use a ModR/M byte. Needed for disassembler
1269 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1270 def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src),
1271 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1272 def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src),
1273 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1274 def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src),
1275 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1279 let SchedRW = [WriteStore] in {
1280 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1281 "mov{b}\t{$src, $dst|$dst, $src}",
1282 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
1283 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1284 "mov{w}\t{$src, $dst|$dst, $src}",
1285 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
1286 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1287 "mov{l}\t{$src, $dst|$dst, $src}",
1288 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32;
1289 def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1290 "mov{q}\t{$src, $dst|$dst, $src}",
1291 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
1294 let hasSideEffects = 0 in {
1296 /// Memory offset versions of moves. The immediate is an address mode sized
1297 /// offset from the segment base.
1298 let SchedRW = [WriteALU] in {
1299 let mayLoad = 1 in {
1301 def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src),
1302 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
1305 def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src),
1306 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1309 def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src),
1310 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1313 def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src),
1314 "mov{q}\t{$src, %rax|rax, $src}", [], IIC_MOV_MEM>,
1318 def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src),
1319 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, AdSize16;
1321 def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src),
1322 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1325 def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src),
1326 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1329 let mayStore = 1 in {
1331 def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs offset32_8:$dst), (ins),
1332 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize32;
1334 def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_16:$dst), (ins),
1335 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1338 def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_32:$dst), (ins),
1339 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1342 def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs offset32_64:$dst), (ins),
1343 "mov{q}\t{%rax, $dst|$dst, rax}", [], IIC_MOV_MEM>,
1347 def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs offset16_8:$dst), (ins),
1348 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize16;
1350 def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_16:$dst), (ins),
1351 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1354 def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_32:$dst), (ins),
1355 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1360 // These forms all have full 64-bit absolute addresses in their instructions
1361 // and use the movabs mnemonic to indicate this specific form.
1362 let mayLoad = 1 in {
1364 def MOV8ao64 : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src),
1365 "movabs{b}\t{$src, %al|al, $src}", []>, AdSize64;
1367 def MOV16ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src),
1368 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16, AdSize64;
1370 def MOV32ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src),
1371 "movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32,
1374 def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src),
1375 "movabs{q}\t{$src, %rax|rax, $src}", []>, AdSize64;
1378 let mayStore = 1 in {
1380 def MOV8o64a : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset64_8:$dst), (ins),
1381 "movabs{b}\t{%al, $dst|$dst, al}", []>, AdSize64;
1383 def MOV16o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_16:$dst), (ins),
1384 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16, AdSize64;
1386 def MOV32o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_32:$dst), (ins),
1387 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32,
1390 def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs offset64_64:$dst), (ins),
1391 "movabs{q}\t{%rax, $dst|$dst, rax}", []>, AdSize64;
1393 } // hasSideEffects = 0
1395 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
1396 SchedRW = [WriteMove] in {
1397 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1398 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1399 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1400 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1401 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1402 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1403 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1404 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1407 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1408 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1409 "mov{b}\t{$src, $dst|$dst, $src}",
1410 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1411 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1412 "mov{w}\t{$src, $dst|$dst, $src}",
1413 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize16;
1414 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1415 "mov{l}\t{$src, $dst|$dst, $src}",
1416 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32;
1417 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1418 "mov{q}\t{$src, $dst|$dst, $src}",
1419 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1422 let SchedRW = [WriteStore] in {
1423 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1424 "mov{b}\t{$src, $dst|$dst, $src}",
1425 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1426 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1427 "mov{w}\t{$src, $dst|$dst, $src}",
1428 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
1429 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1430 "mov{l}\t{$src, $dst|$dst, $src}",
1431 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32;
1432 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1433 "mov{q}\t{$src, $dst|$dst, $src}",
1434 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1437 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1438 // that they can be used for copying and storing h registers, which can't be
1439 // encoded when a REX prefix is present.
1440 let isCodeGenOnly = 1 in {
1441 let hasSideEffects = 0 in
1442 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1443 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1444 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
1446 let mayStore = 1, hasSideEffects = 0 in
1447 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1448 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1449 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1450 IIC_MOV_MEM>, Sched<[WriteStore]>;
1451 let mayLoad = 1, hasSideEffects = 0,
1452 canFoldAsLoad = 1, isReMaterializable = 1 in
1453 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1454 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1455 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1456 IIC_MOV_MEM>, Sched<[WriteLoad]>;
1460 // Condition code ops, incl. set if equal/not equal/...
1461 let SchedRW = [WriteALU] in {
1462 let Defs = [EFLAGS], Uses = [AH] in
1463 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1464 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
1465 let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in
1466 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1467 IIC_AHF>; // AH = flags
1470 //===----------------------------------------------------------------------===//
1471 // Bit tests instructions: BT, BTS, BTR, BTC.
1473 let Defs = [EFLAGS] in {
1474 let SchedRW = [WriteALU] in {
1475 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1476 "bt{w}\t{$src2, $src1|$src1, $src2}",
1477 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1479 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1480 "bt{l}\t{$src2, $src1|$src1, $src2}",
1481 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,
1483 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1484 "bt{q}\t{$src2, $src1|$src1, $src2}",
1485 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1488 // Unlike with the register+register form, the memory+register form of the
1489 // bt instruction does not ignore the high bits of the index. From ISel's
1490 // perspective, this is pretty bizarre. Make these instructions disassembly
1493 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
1494 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1495 "bt{w}\t{$src2, $src1|$src1, $src2}",
1496 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1497 // (implicit EFLAGS)]
1499 >, OpSize16, TB, Requires<[FastBTMem]>;
1500 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1501 "bt{l}\t{$src2, $src1|$src1, $src2}",
1502 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1503 // (implicit EFLAGS)]
1505 >, OpSize32, TB, Requires<[FastBTMem]>;
1506 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1507 "bt{q}\t{$src2, $src1|$src1, $src2}",
1508 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1509 // (implicit EFLAGS)]
1514 let SchedRW = [WriteALU] in {
1515 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1516 "bt{w}\t{$src2, $src1|$src1, $src2}",
1517 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1518 IIC_BT_RI>, OpSize16, TB;
1519 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1520 "bt{l}\t{$src2, $src1|$src1, $src2}",
1521 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1522 IIC_BT_RI>, OpSize32, TB;
1523 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1524 "bt{q}\t{$src2, $src1|$src1, $src2}",
1525 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1529 // Note that these instructions don't need FastBTMem because that
1530 // only applies when the other operand is in a register. When it's
1531 // an immediate, bt is still fast.
1532 let SchedRW = [WriteALU] in {
1533 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1534 "bt{w}\t{$src2, $src1|$src1, $src2}",
1535 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1536 ], IIC_BT_MI>, OpSize16, TB;
1537 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1538 "bt{l}\t{$src2, $src1|$src1, $src2}",
1539 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1540 ], IIC_BT_MI>, OpSize32, TB;
1541 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1542 "bt{q}\t{$src2, $src1|$src1, $src2}",
1543 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1544 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1547 let hasSideEffects = 0 in {
1548 let SchedRW = [WriteALU] in {
1549 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1550 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1552 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1553 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1555 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1556 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1559 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1560 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1561 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1563 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1564 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1566 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1567 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1570 let SchedRW = [WriteALU] in {
1571 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1572 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1574 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1575 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1577 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1578 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1581 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1582 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1583 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1585 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1586 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1588 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1589 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1592 let SchedRW = [WriteALU] in {
1593 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1594 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1596 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1597 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1599 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1600 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1603 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1604 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1605 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1607 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1608 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1610 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1611 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1614 let SchedRW = [WriteALU] in {
1615 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1616 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1618 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1619 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1621 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1622 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1625 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1626 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1627 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1629 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1630 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1632 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1633 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1636 let SchedRW = [WriteALU] in {
1637 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1638 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1640 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1641 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1643 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1644 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1647 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1648 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1649 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1651 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1652 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1654 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1655 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1658 let SchedRW = [WriteALU] in {
1659 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1660 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1662 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1663 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1665 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1666 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1669 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1670 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1671 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1673 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1674 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1676 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1677 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1679 } // hasSideEffects = 0
1680 } // Defs = [EFLAGS]
1683 //===----------------------------------------------------------------------===//
1687 // Atomic swap. These are just normal xchg instructions. But since a memory
1688 // operand is referenced, the atomicity is ensured.
1689 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
1690 InstrItinClass itin> {
1691 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
1692 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
1693 (ins GR8:$val, i8mem:$ptr),
1694 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
1697 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
1699 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
1700 (ins GR16:$val, i16mem:$ptr),
1701 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
1704 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
1706 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
1707 (ins GR32:$val, i32mem:$ptr),
1708 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
1711 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
1713 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
1714 (ins GR64:$val, i64mem:$ptr),
1715 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
1718 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
1723 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
1725 // Swap between registers.
1726 let SchedRW = [WriteALU] in {
1727 let Constraints = "$val = $dst" in {
1728 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1729 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1730 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1731 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1733 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1734 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1736 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1737 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1740 // Swap between EAX and other registers.
1741 let Uses = [AX], Defs = [AX] in
1742 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1743 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16;
1744 let Uses = [EAX], Defs = [EAX] in
1745 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1746 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1747 OpSize32, Requires<[Not64BitMode]>;
1748 let Uses = [EAX], Defs = [EAX] in
1749 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1750 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1751 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1752 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1753 OpSize32, Requires<[In64BitMode]>;
1754 let Uses = [RAX], Defs = [RAX] in
1755 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1756 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>;
1759 let SchedRW = [WriteALU] in {
1760 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1761 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1762 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1763 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1765 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1766 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1768 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1769 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1772 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1773 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1774 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1775 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1776 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1778 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1779 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1781 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1782 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1786 let SchedRW = [WriteALU] in {
1787 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1788 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1789 IIC_CMPXCHG_REG8>, TB;
1790 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1791 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1792 IIC_CMPXCHG_REG>, TB, OpSize16;
1793 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1794 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1795 IIC_CMPXCHG_REG>, TB, OpSize32;
1796 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1797 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1798 IIC_CMPXCHG_REG>, TB;
1801 let SchedRW = [WriteALULd, WriteRMW] in {
1802 let mayLoad = 1, mayStore = 1 in {
1803 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1804 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1805 IIC_CMPXCHG_MEM8>, TB;
1806 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1807 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1808 IIC_CMPXCHG_MEM>, TB, OpSize16;
1809 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1810 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1811 IIC_CMPXCHG_MEM>, TB, OpSize32;
1812 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1813 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1814 IIC_CMPXCHG_MEM>, TB;
1817 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1818 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1819 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1821 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1822 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1823 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1824 TB, Requires<[HasCmpxchg16b]>;
1828 // Lock instruction prefix
1829 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1831 // Rex64 instruction prefix
1832 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>,
1833 Requires<[In64BitMode]>;
1835 // Data16 instruction prefix
1836 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1838 // Repeat string operation instruction prefixes
1839 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1840 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1841 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1842 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1843 // Repeat while not equal (used with CMPS and SCAS)
1844 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1848 // String manipulation instructions
1849 let SchedRW = [WriteMicrocoded] in {
1850 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1851 let Defs = [AL,ESI], Uses = [ESI,EFLAGS] in
1852 def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src),
1853 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>;
1854 let Defs = [AX,ESI], Uses = [ESI,EFLAGS] in
1855 def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src),
1856 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16;
1857 let Defs = [EAX,ESI], Uses = [ESI,EFLAGS] in
1858 def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src),
1859 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32;
1860 let Defs = [RAX,ESI], Uses = [ESI,EFLAGS] in
1861 def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),
1862 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>;
1865 let SchedRW = [WriteSystem] in {
1866 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1867 let Defs = [ESI], Uses = [DX,ESI,EFLAGS] in {
1868 def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src),
1869 "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>;
1870 def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src),
1871 "outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16;
1872 def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src),
1873 "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32;
1876 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1877 let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in {
1878 def INSB : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins),
1879 "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
1880 def INSW : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins),
1881 "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
1882 def INSL : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins),
1883 "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32;
1887 // Flag instructions
1888 let SchedRW = [WriteALU] in {
1889 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1890 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1891 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1892 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1893 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1894 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1895 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1897 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1900 // Table lookup instructions
1901 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,
1904 let SchedRW = [WriteMicrocoded] in {
1905 // ASCII Adjust After Addition
1906 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1907 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1908 Requires<[Not64BitMode]>;
1910 // ASCII Adjust AX Before Division
1911 // sets AL, AH and EFLAGS and uses AL and AH
1912 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1913 "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>;
1915 // ASCII Adjust AX After Multiply
1916 // sets AL, AH and EFLAGS and uses AL
1917 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1918 "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>;
1920 // ASCII Adjust AL After Subtraction - sets
1921 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1922 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1923 Requires<[Not64BitMode]>;
1925 // Decimal Adjust AL after Addition
1926 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1927 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1928 Requires<[Not64BitMode]>;
1930 // Decimal Adjust AL after Subtraction
1931 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1932 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1933 Requires<[Not64BitMode]>;
1936 let SchedRW = [WriteSystem] in {
1937 // Check Array Index Against Bounds
1938 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1939 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,
1940 Requires<[Not64BitMode]>;
1941 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1942 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize32,
1943 Requires<[Not64BitMode]>;
1945 // Adjust RPL Field of Segment Selector
1946 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1947 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1948 Requires<[Not64BitMode]>;
1949 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1950 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1951 Requires<[Not64BitMode]>;
1954 //===----------------------------------------------------------------------===//
1955 // MOVBE Instructions
1957 let Predicates = [HasMOVBE] in {
1958 let SchedRW = [WriteALULd] in {
1959 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1960 "movbe{w}\t{$src, $dst|$dst, $src}",
1961 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1963 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1964 "movbe{l}\t{$src, $dst|$dst, $src}",
1965 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1967 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1968 "movbe{q}\t{$src, $dst|$dst, $src}",
1969 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
1972 let SchedRW = [WriteStore] in {
1973 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1974 "movbe{w}\t{$src, $dst|$dst, $src}",
1975 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1977 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1978 "movbe{l}\t{$src, $dst|$dst, $src}",
1979 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1981 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1982 "movbe{q}\t{$src, $dst|$dst, $src}",
1983 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
1988 //===----------------------------------------------------------------------===//
1989 // RDRAND Instruction
1991 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1992 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1994 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
1995 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1997 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, TB;
1998 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
2000 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
2003 //===----------------------------------------------------------------------===//
2004 // RDSEED Instruction
2006 let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
2007 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
2009 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
2010 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
2012 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB;
2013 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
2015 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
2018 //===----------------------------------------------------------------------===//
2019 // LZCNT Instruction
2021 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
2022 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2023 "lzcnt{w}\t{$src, $dst|$dst, $src}",
2024 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
2026 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2027 "lzcnt{w}\t{$src, $dst|$dst, $src}",
2028 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
2029 (implicit EFLAGS)]>, XS, OpSize16;
2031 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2032 "lzcnt{l}\t{$src, $dst|$dst, $src}",
2033 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS,
2035 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2036 "lzcnt{l}\t{$src, $dst|$dst, $src}",
2037 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
2038 (implicit EFLAGS)]>, XS, OpSize32;
2040 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2041 "lzcnt{q}\t{$src, $dst|$dst, $src}",
2042 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
2044 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2045 "lzcnt{q}\t{$src, $dst|$dst, $src}",
2046 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
2047 (implicit EFLAGS)]>, XS;
2050 let Predicates = [HasLZCNT] in {
2051 def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
2052 (X86cmp GR16:$src, (i16 0))),
2053 (LZCNT16rr GR16:$src)>;
2054 def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
2055 (X86cmp GR32:$src, (i32 0))),
2056 (LZCNT32rr GR32:$src)>;
2057 def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
2058 (X86cmp GR64:$src, (i64 0))),
2059 (LZCNT64rr GR64:$src)>;
2060 def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_E_OR_NE),
2061 (X86cmp GR16:$src, (i16 0))),
2062 (LZCNT16rr GR16:$src)>;
2063 def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_E_OR_NE),
2064 (X86cmp GR32:$src, (i32 0))),
2065 (LZCNT32rr GR32:$src)>;
2066 def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_E_OR_NE),
2067 (X86cmp GR64:$src, (i64 0))),
2068 (LZCNT64rr GR64:$src)>;
2070 def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
2071 (X86cmp (loadi16 addr:$src), (i16 0))),
2072 (LZCNT16rm addr:$src)>;
2073 def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
2074 (X86cmp (loadi32 addr:$src), (i32 0))),
2075 (LZCNT32rm addr:$src)>;
2076 def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
2077 (X86cmp (loadi64 addr:$src), (i64 0))),
2078 (LZCNT64rm addr:$src)>;
2079 def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
2080 (X86cmp (loadi16 addr:$src), (i16 0))),
2081 (LZCNT16rm addr:$src)>;
2082 def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
2083 (X86cmp (loadi32 addr:$src), (i32 0))),
2084 (LZCNT32rm addr:$src)>;
2085 def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
2086 (X86cmp (loadi64 addr:$src), (i64 0))),
2087 (LZCNT64rm addr:$src)>;
2090 //===----------------------------------------------------------------------===//
2093 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2094 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2095 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2096 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
2098 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2099 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2100 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
2101 (implicit EFLAGS)]>, XS, OpSize16;
2103 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2104 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2105 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS,
2107 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2108 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2109 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
2110 (implicit EFLAGS)]>, XS, OpSize32;
2112 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2113 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2114 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
2116 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2117 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2118 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
2119 (implicit EFLAGS)]>, XS;
2122 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
2123 RegisterClass RC, X86MemOperand x86memop> {
2124 let hasSideEffects = 0 in {
2125 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
2126 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2129 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
2130 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2135 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2136 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>;
2137 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
2138 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>;
2139 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W;
2140 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>;
2141 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W;
2144 //===----------------------------------------------------------------------===//
2145 // Pattern fragments to auto generate BMI instructions.
2146 //===----------------------------------------------------------------------===//
2148 let Predicates = [HasBMI] in {
2149 // FIXME: patterns for the load versions are not implemented
2150 def : Pat<(and GR32:$src, (add GR32:$src, -1)),
2151 (BLSR32rr GR32:$src)>;
2152 def : Pat<(and GR64:$src, (add GR64:$src, -1)),
2153 (BLSR64rr GR64:$src)>;
2155 def : Pat<(xor GR32:$src, (add GR32:$src, -1)),
2156 (BLSMSK32rr GR32:$src)>;
2157 def : Pat<(xor GR64:$src, (add GR64:$src, -1)),
2158 (BLSMSK64rr GR64:$src)>;
2160 def : Pat<(and GR32:$src, (ineg GR32:$src)),
2161 (BLSI32rr GR32:$src)>;
2162 def : Pat<(and GR64:$src, (ineg GR64:$src)),
2163 (BLSI64rr GR64:$src)>;
2166 let Predicates = [HasBMI] in {
2167 def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
2168 (X86cmp GR16:$src, (i16 0))),
2169 (TZCNT16rr GR16:$src)>;
2170 def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
2171 (X86cmp GR32:$src, (i32 0))),
2172 (TZCNT32rr GR32:$src)>;
2173 def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
2174 (X86cmp GR64:$src, (i64 0))),
2175 (TZCNT64rr GR64:$src)>;
2176 def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_E_OR_NE),
2177 (X86cmp GR16:$src, (i16 0))),
2178 (TZCNT16rr GR16:$src)>;
2179 def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_E_OR_NE),
2180 (X86cmp GR32:$src, (i32 0))),
2181 (TZCNT32rr GR32:$src)>;
2182 def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_E_OR_NE),
2183 (X86cmp GR64:$src, (i64 0))),
2184 (TZCNT64rr GR64:$src)>;
2186 def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
2187 (X86cmp (loadi16 addr:$src), (i16 0))),
2188 (TZCNT16rm addr:$src)>;
2189 def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
2190 (X86cmp (loadi32 addr:$src), (i32 0))),
2191 (TZCNT32rm addr:$src)>;
2192 def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
2193 (X86cmp (loadi64 addr:$src), (i64 0))),
2194 (TZCNT64rm addr:$src)>;
2195 def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
2196 (X86cmp (loadi16 addr:$src), (i16 0))),
2197 (TZCNT16rm addr:$src)>;
2198 def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
2199 (X86cmp (loadi32 addr:$src), (i32 0))),
2200 (TZCNT32rm addr:$src)>;
2201 def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
2202 (X86cmp (loadi64 addr:$src), (i64 0))),
2203 (TZCNT64rm addr:$src)>;
2207 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
2208 X86MemOperand x86memop, Intrinsic Int,
2210 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2211 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2212 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
2214 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
2215 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2216 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
2217 (implicit EFLAGS)]>, T8PS, VEX_4VOp3;
2220 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2221 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
2222 int_x86_bmi_bextr_32, loadi32>;
2223 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
2224 int_x86_bmi_bextr_64, loadi64>, VEX_W;
2227 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
2228 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
2229 int_x86_bmi_bzhi_32, loadi32>;
2230 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
2231 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
2235 def CountTrailingOnes : SDNodeXForm<imm, [{
2236 // Count the trailing ones in the immediate.
2237 return getI8Imm(countTrailingOnes(N->getZExtValue()), SDLoc(N));
2240 def BZHIMask : ImmLeaf<i64, [{
2241 return isMask_64(Imm) && (countTrailingOnes<uint64_t>(Imm) > 32);
2244 let Predicates = [HasBMI2] in {
2245 def : Pat<(and GR64:$src, BZHIMask:$mask),
2246 (BZHI64rr GR64:$src,
2247 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2248 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>;
2250 def : Pat<(and GR32:$src, (add (shl 1, GR8:$lz), -1)),
2251 (BZHI32rr GR32:$src,
2252 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2254 def : Pat<(and (loadi32 addr:$src), (add (shl 1, GR8:$lz), -1)),
2255 (BZHI32rm addr:$src,
2256 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2258 def : Pat<(and GR64:$src, (add (shl 1, GR8:$lz), -1)),
2259 (BZHI64rr GR64:$src,
2260 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2262 def : Pat<(and (loadi64 addr:$src), (add (shl 1, GR8:$lz), -1)),
2263 (BZHI64rm addr:$src,
2264 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2267 let Predicates = [HasBMI] in {
2268 def : Pat<(X86bextr GR32:$src1, GR32:$src2),
2269 (BEXTR32rr GR32:$src1, GR32:$src2)>;
2270 def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2),
2271 (BEXTR32rm addr:$src1, GR32:$src2)>;
2272 def : Pat<(X86bextr GR64:$src1, GR64:$src2),
2273 (BEXTR64rr GR64:$src1, GR64:$src2)>;
2274 def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2),
2275 (BEXTR64rm addr:$src1, GR64:$src2)>;
2278 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
2279 X86MemOperand x86memop, Intrinsic Int,
2281 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2282 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2283 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
2285 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2286 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2287 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
2290 let Predicates = [HasBMI2] in {
2291 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
2292 int_x86_bmi_pdep_32, loadi32>, T8XD;
2293 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
2294 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
2295 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
2296 int_x86_bmi_pext_32, loadi32>, T8XS;
2297 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
2298 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
2301 //===----------------------------------------------------------------------===//
2304 let Predicates = [HasTBM], Defs = [EFLAGS] in {
2306 multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr,
2307 X86MemOperand x86memop, PatFrag ld_frag,
2308 Intrinsic Int, Operand immtype,
2309 SDPatternOperator immoperator> {
2310 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
2311 !strconcat(OpcodeStr,
2312 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2313 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>,
2315 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst),
2316 (ins x86memop:$src1, immtype:$cntl),
2317 !strconcat(OpcodeStr,
2318 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2319 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>,
2323 defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32,
2324 int_x86_tbm_bextri_u32, i32imm, imm>;
2325 let ImmT = Imm32S in
2326 defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64,
2327 int_x86_tbm_bextri_u64, i64i32imm,
2328 i64immSExt32>, VEX_W;
2330 multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem,
2331 RegisterClass RC, string OpcodeStr,
2332 X86MemOperand x86memop, PatFrag ld_frag> {
2333 let hasSideEffects = 0 in {
2334 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src),
2335 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2338 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src),
2339 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2344 multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr,
2345 Format FormReg, Format FormMem> {
2346 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem,
2348 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem,
2352 defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
2353 defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>;
2354 defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>;
2355 defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>;
2356 defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>;
2357 defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>;
2358 defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>;
2359 defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>;
2360 defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>;
2363 //===----------------------------------------------------------------------===//
2364 // Pattern fragments to auto generate TBM instructions.
2365 //===----------------------------------------------------------------------===//
2367 let Predicates = [HasTBM] in {
2368 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)),
2369 (BEXTRI32ri GR32:$src1, imm:$src2)>;
2370 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)),
2371 (BEXTRI32mi addr:$src1, imm:$src2)>;
2372 def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2),
2373 (BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>;
2374 def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2),
2375 (BEXTRI64mi addr:$src1, i64immSExt32:$src2)>;
2377 // FIXME: patterns for the load versions are not implemented
2378 def : Pat<(and GR32:$src, (add GR32:$src, 1)),
2379 (BLCFILL32rr GR32:$src)>;
2380 def : Pat<(and GR64:$src, (add GR64:$src, 1)),
2381 (BLCFILL64rr GR64:$src)>;
2383 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
2384 (BLCI32rr GR32:$src)>;
2385 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
2386 (BLCI64rr GR64:$src)>;
2388 // Extra patterns because opt can optimize the above patterns to this.
2389 def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
2390 (BLCI32rr GR32:$src)>;
2391 def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
2392 (BLCI64rr GR64:$src)>;
2394 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
2395 (BLCIC32rr GR32:$src)>;
2396 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),
2397 (BLCIC64rr GR64:$src)>;
2399 def : Pat<(xor GR32:$src, (add GR32:$src, 1)),
2400 (BLCMSK32rr GR32:$src)>;
2401 def : Pat<(xor GR64:$src, (add GR64:$src, 1)),
2402 (BLCMSK64rr GR64:$src)>;
2404 def : Pat<(or GR32:$src, (add GR32:$src, 1)),
2405 (BLCS32rr GR32:$src)>;
2406 def : Pat<(or GR64:$src, (add GR64:$src, 1)),
2407 (BLCS64rr GR64:$src)>;
2409 def : Pat<(or GR32:$src, (add GR32:$src, -1)),
2410 (BLSFILL32rr GR32:$src)>;
2411 def : Pat<(or GR64:$src, (add GR64:$src, -1)),
2412 (BLSFILL64rr GR64:$src)>;
2414 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
2415 (BLSIC32rr GR32:$src)>;
2416 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)),
2417 (BLSIC64rr GR64:$src)>;
2419 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)),
2420 (T1MSKC32rr GR32:$src)>;
2421 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)),
2422 (T1MSKC64rr GR64:$src)>;
2424 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)),
2425 (TZMSK32rr GR32:$src)>;
2426 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)),
2427 (TZMSK64rr GR64:$src)>;
2430 //===----------------------------------------------------------------------===//
2431 // Memory Instructions
2434 def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2435 "clflushopt\t$src", []>, PD;
2436 def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", []>, PD;
2437 def PCOMMIT : I<0xAE, MRM_F8, (outs), (ins), "pcommit", []>, PD;
2440 //===----------------------------------------------------------------------===//
2442 //===----------------------------------------------------------------------===//
2444 include "X86InstrArithmetic.td"
2445 include "X86InstrCMovSetCC.td"
2446 include "X86InstrExtension.td"
2447 include "X86InstrControl.td"
2448 include "X86InstrShiftRotate.td"
2450 // X87 Floating Point Stack.
2451 include "X86InstrFPStack.td"
2453 // SIMD support (SSE, MMX and AVX)
2454 include "X86InstrFragmentsSIMD.td"
2456 // FMA - Fused Multiply-Add support (requires FMA)
2457 include "X86InstrFMA.td"
2460 include "X86InstrXOP.td"
2462 // SSE, MMX and 3DNow! vector support.
2463 include "X86InstrSSE.td"
2464 include "X86InstrAVX512.td"
2465 include "X86InstrMMX.td"
2466 include "X86Instr3DNow.td"
2469 include "X86InstrMPX.td"
2471 include "X86InstrVMX.td"
2472 include "X86InstrSVM.td"
2474 include "X86InstrTSX.td"
2475 include "X86InstrSGX.td"
2477 // System instructions.
2478 include "X86InstrSystem.td"
2480 // Compiler Pseudo Instructions and Pat Patterns
2481 include "X86InstrCompiler.td"
2483 //===----------------------------------------------------------------------===//
2484 // Assembler Mnemonic Aliases
2485 //===----------------------------------------------------------------------===//
2487 def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>;
2488 def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>;
2489 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;
2491 def : MnemonicAlias<"cbw", "cbtw", "att">;
2492 def : MnemonicAlias<"cwde", "cwtl", "att">;
2493 def : MnemonicAlias<"cwd", "cwtd", "att">;
2494 def : MnemonicAlias<"cdq", "cltd", "att">;
2495 def : MnemonicAlias<"cdqe", "cltq", "att">;
2496 def : MnemonicAlias<"cqo", "cqto", "att">;
2498 // In 64-bit mode lret maps to lretl; it is not ambiguous with lretq.
2499 def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>;
2500 def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>;
2502 def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>;
2503 def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>;
2505 def : MnemonicAlias<"loopz", "loope", "att">;
2506 def : MnemonicAlias<"loopnz", "loopne", "att">;
2508 def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>;
2509 def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>;
2510 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>;
2511 def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>;
2512 def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>;
2513 def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>;
2514 def : MnemonicAlias<"popfd", "popfl", "att">;
2516 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
2517 // all modes. However: "push (addr)" and "push $42" should default to
2518 // pushl/pushq depending on the current mode. Similar for "pop %bx"
2519 def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>;
2520 def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>;
2521 def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>;
2522 def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>;
2523 def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>;
2524 def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
2525 def : MnemonicAlias<"pushfd", "pushfl", "att">;
2527 def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>;
2528 def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>;
2529 def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>;
2530 def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>;
2531 def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>;
2532 def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>;
2534 def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>;
2535 def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>;
2536 def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>;
2537 def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>;
2539 def : MnemonicAlias<"repe", "rep", "att">;
2540 def : MnemonicAlias<"repz", "rep", "att">;
2541 def : MnemonicAlias<"repnz", "repne", "att">;
2543 def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>;
2544 def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>;
2545 def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>;
2547 def : MnemonicAlias<"salb", "shlb", "att">;
2548 def : MnemonicAlias<"salw", "shlw", "att">;
2549 def : MnemonicAlias<"sall", "shll", "att">;
2550 def : MnemonicAlias<"salq", "shlq", "att">;
2552 def : MnemonicAlias<"smovb", "movsb", "att">;
2553 def : MnemonicAlias<"smovw", "movsw", "att">;
2554 def : MnemonicAlias<"smovl", "movsl", "att">;
2555 def : MnemonicAlias<"smovq", "movsq", "att">;
2557 def : MnemonicAlias<"ud2a", "ud2", "att">;
2558 def : MnemonicAlias<"verrw", "verr", "att">;
2560 // System instruction aliases.
2561 def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>;
2562 def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>;
2563 def : MnemonicAlias<"sysret", "sysretl", "att">;
2564 def : MnemonicAlias<"sysexit", "sysexitl", "att">;
2566 def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>;
2567 def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>;
2568 def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>;
2569 def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>;
2570 def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>;
2571 def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>;
2572 def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>;
2573 def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>;
2574 def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>;
2575 def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>;
2576 def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>;
2577 def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>;
2580 // Floating point stack aliases.
2581 def : MnemonicAlias<"fcmovz", "fcmove", "att">;
2582 def : MnemonicAlias<"fcmova", "fcmovnbe", "att">;
2583 def : MnemonicAlias<"fcmovnae", "fcmovb", "att">;
2584 def : MnemonicAlias<"fcmovna", "fcmovbe", "att">;
2585 def : MnemonicAlias<"fcmovae", "fcmovnb", "att">;
2586 def : MnemonicAlias<"fcomip", "fcompi", "att">;
2587 def : MnemonicAlias<"fildq", "fildll", "att">;
2588 def : MnemonicAlias<"fistpq", "fistpll", "att">;
2589 def : MnemonicAlias<"fisttpq", "fisttpll", "att">;
2590 def : MnemonicAlias<"fldcww", "fldcw", "att">;
2591 def : MnemonicAlias<"fnstcww", "fnstcw", "att">;
2592 def : MnemonicAlias<"fnstsww", "fnstsw", "att">;
2593 def : MnemonicAlias<"fucomip", "fucompi", "att">;
2594 def : MnemonicAlias<"fwait", "wait">;
2596 def : MnemonicAlias<"fxsaveq", "fxsave64", "att">;
2597 def : MnemonicAlias<"fxrstorq", "fxrstor64", "att">;
2598 def : MnemonicAlias<"xsaveq", "xsave64", "att">;
2599 def : MnemonicAlias<"xrstorq", "xrstor64", "att">;
2600 def : MnemonicAlias<"xsaveoptq", "xsaveopt64", "att">;
2603 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond,
2605 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
2606 !strconcat(Prefix, NewCond, Suffix), VariantName>;
2608 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
2609 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
2610 /// example "setz" -> "sete".
2611 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix,
2613 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb
2614 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete
2615 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe
2616 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae
2617 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae
2618 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle
2619 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge
2620 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne
2621 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp
2622 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp
2624 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb
2625 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta
2626 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl
2627 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg
2630 // Aliases for set<CC>
2631 defm : IntegerCondCodeMnemonicAlias<"set", "">;
2632 // Aliases for j<CC>
2633 defm : IntegerCondCodeMnemonicAlias<"j", "">;
2634 // Aliases for cmov<CC>{w,l,q}
2635 defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">;
2636 defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">;
2637 defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">;
2638 // No size suffix for intel-style asm.
2639 defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">;
2642 //===----------------------------------------------------------------------===//
2643 // Assembler Instruction Aliases
2644 //===----------------------------------------------------------------------===//
2646 // aad/aam default to base 10 if no operand is specified.
2647 def : InstAlias<"aad", (AAD8i8 10)>;
2648 def : InstAlias<"aam", (AAM8i8 10)>;
2650 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
2651 // Likewise for btc/btr/bts.
2652 def : InstAlias<"bt {$imm, $mem|$mem, $imm}",
2653 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2654 def : InstAlias<"btc {$imm, $mem|$mem, $imm}",
2655 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2656 def : InstAlias<"btr {$imm, $mem|$mem, $imm}",
2657 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2658 def : InstAlias<"bts {$imm, $mem|$mem, $imm}",
2659 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2662 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>;
2663 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>;
2664 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>;
2665 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;
2667 // lods aliases. Accept the destination being omitted because it's implicit
2668 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2669 // in the destination.
2670 def : InstAlias<"lodsb $src", (LODSB srcidx8:$src), 0>;
2671 def : InstAlias<"lodsw $src", (LODSW srcidx16:$src), 0>;
2672 def : InstAlias<"lods{l|d} $src", (LODSL srcidx32:$src), 0>;
2673 def : InstAlias<"lodsq $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2674 def : InstAlias<"lods {$src, %al|al, $src}", (LODSB srcidx8:$src), 0>;
2675 def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>;
2676 def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>;
2677 def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2679 // stos aliases. Accept the source being omitted because it's implicit in
2680 // the mnemonic, or the mnemonic suffix being omitted because it's implicit
2682 def : InstAlias<"stosb $dst", (STOSB dstidx8:$dst), 0>;
2683 def : InstAlias<"stosw $dst", (STOSW dstidx16:$dst), 0>;
2684 def : InstAlias<"stos{l|d} $dst", (STOSL dstidx32:$dst), 0>;
2685 def : InstAlias<"stosq $dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2686 def : InstAlias<"stos {%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>;
2687 def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>;
2688 def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>;
2689 def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2691 // scas aliases. Accept the destination being omitted because it's implicit
2692 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2693 // in the destination.
2694 def : InstAlias<"scasb $dst", (SCASB dstidx8:$dst), 0>;
2695 def : InstAlias<"scasw $dst", (SCASW dstidx16:$dst), 0>;
2696 def : InstAlias<"scas{l|d} $dst", (SCASL dstidx32:$dst), 0>;
2697 def : InstAlias<"scasq $dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2698 def : InstAlias<"scas {$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>;
2699 def : InstAlias<"scas {$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>;
2700 def : InstAlias<"scas {$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>;
2701 def : InstAlias<"scas {$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2703 // div and idiv aliases for explicit A register.
2704 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
2705 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
2706 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>;
2707 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>;
2708 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>;
2709 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>;
2710 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>;
2711 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>;
2712 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>;
2713 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>;
2714 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>;
2715 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>;
2716 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>;
2717 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>;
2718 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;
2719 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;
2723 // Various unary fpstack operations default to operating on on ST1.
2724 // For example, "fxch" -> "fxch %st(1)"
2725 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
2726 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
2727 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
2728 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
2729 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
2730 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
2731 def : InstAlias<"fxch", (XCH_F ST1), 0>;
2732 def : InstAlias<"fcom", (COM_FST0r ST1), 0>;
2733 def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>;
2734 def : InstAlias<"fcomi", (COM_FIr ST1), 0>;
2735 def : InstAlias<"fcompi", (COM_FIPr ST1), 0>;
2736 def : InstAlias<"fucom", (UCOM_Fr ST1), 0>;
2737 def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>;
2738 def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>;
2739 def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>;
2741 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
2742 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
2743 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
2745 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
2746 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"),
2747 (Inst RST:$op), EmitAlias>;
2748 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"),
2749 (Inst ST0), EmitAlias>;
2752 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
2753 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
2754 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
2755 defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>;
2756 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
2757 defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>;
2758 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
2759 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
2760 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
2761 defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>;
2762 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
2763 defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>;
2764 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
2765 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
2766 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
2767 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
2770 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
2771 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
2772 // solely because gas supports it.
2773 def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>;
2774 def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>;
2775 def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>;
2776 def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>;
2777 def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>;
2778 def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>;
2780 // We accept "fnstsw %eax" even though it only writes %ax.
2781 def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>;
2782 def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>;
2783 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
2785 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
2786 // this is compatible with what GAS does.
2787 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2788 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2789 def : InstAlias<"lcall {*}$dst", (FARCALL32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2790 def : InstAlias<"ljmp {*}$dst", (FARJMP32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2791 def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2792 def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2793 def : InstAlias<"lcall {*}$dst", (FARCALL16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2794 def : InstAlias<"ljmp {*}$dst", (FARJMP16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2796 def : InstAlias<"call {*}$dst", (CALL64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
2797 def : InstAlias<"jmp {*}$dst", (JMP64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
2798 def : InstAlias<"call {*}$dst", (CALL32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
2799 def : InstAlias<"jmp {*}$dst", (JMP32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
2800 def : InstAlias<"call {*}$dst", (CALL16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2801 def : InstAlias<"jmp {*}$dst", (JMP16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2804 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
2805 def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>;
2806 def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>;
2807 def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>;
2808 def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>;
2809 def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>;
2810 def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>;
2812 // inb %dx -> inb %al, %dx
2813 def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;
2814 def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;
2815 def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>;
2816 def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>;
2817 def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>;
2818 def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>;
2821 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
2822 def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2823 def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2824 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2825 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2826 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
2827 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
2828 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2829 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2831 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
2832 // the move. All segment/mem forms are equivalent, this has the shortest
2834 def : InstAlias<"mov {$mem, $seg|$seg, $mem}", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem), 0>;
2835 def : InstAlias<"mov {$seg, $mem|$mem, $seg}", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg), 0>;
2837 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
2838 def : InstAlias<"movq {$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>;
2840 // Match 'movq GR64, MMX' as an alias for movd.
2841 def : InstAlias<"movq {$src, $dst|$dst, $src}",
2842 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
2843 def : InstAlias<"movq {$src, $dst|$dst, $src}",
2844 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
2847 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
2848 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
2849 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
2850 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
2851 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
2852 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
2853 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
2856 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
2857 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
2858 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
2859 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
2860 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
2861 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
2862 // Note: No GR32->GR64 movzx form.
2864 // outb %dx -> outb %al, %dx
2865 def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>;
2866 def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>;
2867 def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>;
2868 def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>;
2869 def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>;
2870 def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>;
2872 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
2873 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
2874 // errors, since its encoding is the most compact.
2875 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>;
2877 // shld/shrd op,op -> shld op, op, CL
2878 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;
2879 def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>;
2880 def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>;
2881 def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>;
2882 def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>;
2883 def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>;
2885 def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>;
2886 def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>;
2887 def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>;
2888 def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>;
2889 def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>;
2890 def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>;
2892 /* FIXME: This is disabled because the asm matcher is currently incapable of
2893 * matching a fixed immediate like $1.
2894 // "shl X, $1" is an alias for "shl X".
2895 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
2896 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2897 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
2898 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2899 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
2900 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2901 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
2902 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2903 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
2904 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2905 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
2906 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2907 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
2908 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2909 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
2910 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2911 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2914 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2915 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
2916 defm : ShiftRotateByOneAlias<"rol", "ROL">;
2917 defm : ShiftRotateByOneAlias<"ror", "ROR">;
2920 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
2921 def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}",
2922 (TEST8rm GR8 :$val, i8mem :$mem), 0>;
2923 def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}",
2924 (TEST16rm GR16:$val, i16mem:$mem), 0>;
2925 def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}",
2926 (TEST32rm GR32:$val, i32mem:$mem), 0>;
2927 def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}",
2928 (TEST64rm GR64:$val, i64mem:$mem), 0>;
2930 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
2931 def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}",
2932 (XCHG8rm GR8 :$val, i8mem :$mem), 0>;
2933 def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}",
2934 (XCHG16rm GR16:$val, i16mem:$mem), 0>;
2935 def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}",
2936 (XCHG32rm GR32:$val, i32mem:$mem), 0>;
2937 def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}",
2938 (XCHG64rm GR64:$val, i64mem:$mem), 0>;
2940 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
2941 def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>;
2942 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
2943 (XCHG32ar GR32:$src), 0>, Requires<[Not64BitMode]>;
2944 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
2945 (XCHG32ar64 GR32_NOAX:$src), 0>, Requires<[In64BitMode]>;
2946 def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>;