1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 //def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
36 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
41 SDTCisInt<0>, SDTCisVT<1, i32>]>;
43 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
44 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
50 // RES1, RES2, FLAGS = op LHS, RHS
51 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
55 SDTCisInt<0>, SDTCisVT<1, i32>]>;
56 def SDTX86BrCond : SDTypeProfile<0, 3,
57 [SDTCisVT<0, OtherVT>,
58 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
60 def SDTX86SetCC : SDTypeProfile<1, 2,
62 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
63 def SDTX86SetCC_C : SDTypeProfile<1, 2,
65 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
67 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
69 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
71 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
73 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
75 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
76 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
77 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
79 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
80 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
83 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
85 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
89 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
95 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
97 def SDTX86Void : SDTypeProfile<0, 0, []>;
99 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
101 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
103 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
105 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
107 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
109 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
111 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
113 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
115 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
117 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
118 [SDNPHasChain,SDNPSideEffect]>;
119 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
121 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
123 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
127 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
128 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
129 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
130 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
132 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
133 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
135 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
136 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
138 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
139 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
141 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
143 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
144 [SDNPHasChain, SDNPSideEffect]>;
146 def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand,
147 [SDNPHasChain, SDNPSideEffect]>;
149 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
150 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
151 SDNPMayLoad, SDNPMemOperand]>;
152 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
153 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
154 SDNPMayLoad, SDNPMemOperand]>;
155 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
156 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
157 SDNPMayLoad, SDNPMemOperand]>;
159 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
160 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
162 def X86vastart_save_xmm_regs :
163 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
164 SDT_X86VASTART_SAVE_XMM_REGS,
165 [SDNPHasChain, SDNPVariadic]>;
167 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
168 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
170 def X86callseq_start :
171 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
172 [SDNPHasChain, SDNPOutGlue]>;
174 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
175 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
177 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
178 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
181 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
182 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
183 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
184 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
187 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
188 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
189 def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void,
190 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
191 def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void,
192 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
194 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
195 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
197 def X86RecoverFrameAlloc : SDNode<"ISD::FRAME_ALLOC_RECOVER",
198 SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
201 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
202 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
204 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
205 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
207 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
210 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
211 SDTypeProfile<1, 1, [SDTCisInt<0>,
213 [SDNPHasChain, SDNPSideEffect]>;
214 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
215 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
216 [SDNPHasChain, SDNPSideEffect]>;
218 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
219 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
221 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
223 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
224 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
226 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
228 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
229 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
231 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
232 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
233 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
235 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
237 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
240 def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>;
242 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
244 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
245 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
247 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
250 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
251 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
253 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL,
254 [SDNPHasChain, SDNPOutGlue]>;
256 //===----------------------------------------------------------------------===//
257 // X86 Operand Definitions.
260 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
261 // the index operand of an address, to conform to x86 encoding restrictions.
262 def ptr_rc_nosp : PointerLikeRegClass<1>;
264 // *mem - Operand definitions for the funky X86 addressing mode operands.
266 def X86MemAsmOperand : AsmOperandClass {
269 let RenderMethod = "addMemOperands" in {
270 def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; }
271 def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; }
272 def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; }
273 def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; }
274 def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; }
275 def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; }
276 def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; }
277 def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; }
278 // Gather mem operands
279 def X86MemVX32Operand : AsmOperandClass { let Name = "MemVX32"; }
280 def X86MemVY32Operand : AsmOperandClass { let Name = "MemVY32"; }
281 def X86MemVZ32Operand : AsmOperandClass { let Name = "MemVZ32"; }
282 def X86MemVX64Operand : AsmOperandClass { let Name = "MemVX64"; }
283 def X86MemVY64Operand : AsmOperandClass { let Name = "MemVY64"; }
284 def X86MemVZ64Operand : AsmOperandClass { let Name = "MemVZ64"; }
287 def X86AbsMemAsmOperand : AsmOperandClass {
289 let SuperClasses = [X86MemAsmOperand];
292 class X86MemOperand<string printMethod,
293 AsmOperandClass parserMatchClass = X86MemAsmOperand> : Operand<iPTR> {
294 let PrintMethod = printMethod;
295 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
296 let ParserMatchClass = parserMatchClass;
297 let OperandType = "OPERAND_MEMORY";
300 // Gather mem operands
301 class X86VMemOperand<RegisterClass RC, string printMethod,
302 AsmOperandClass parserMatchClass>
303 : X86MemOperand<printMethod, parserMatchClass> {
304 let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, i8imm);
307 def anymem : X86MemOperand<"printanymem">;
309 def opaque32mem : X86MemOperand<"printopaquemem">;
310 def opaque48mem : X86MemOperand<"printopaquemem">;
311 def opaque80mem : X86MemOperand<"printopaquemem">;
312 def opaque512mem : X86MemOperand<"printopaquemem">;
314 def i8mem : X86MemOperand<"printi8mem", X86Mem8AsmOperand>;
315 def i16mem : X86MemOperand<"printi16mem", X86Mem16AsmOperand>;
316 def i32mem : X86MemOperand<"printi32mem", X86Mem32AsmOperand>;
317 def i64mem : X86MemOperand<"printi64mem", X86Mem64AsmOperand>;
318 def i128mem : X86MemOperand<"printi128mem", X86Mem128AsmOperand>;
319 def i256mem : X86MemOperand<"printi256mem", X86Mem256AsmOperand>;
320 def i512mem : X86MemOperand<"printi512mem", X86Mem512AsmOperand>;
321 def f32mem : X86MemOperand<"printf32mem", X86Mem32AsmOperand>;
322 def f64mem : X86MemOperand<"printf64mem", X86Mem64AsmOperand>;
323 def f80mem : X86MemOperand<"printf80mem", X86Mem80AsmOperand>;
324 def f128mem : X86MemOperand<"printf128mem", X86Mem128AsmOperand>;
325 def f256mem : X86MemOperand<"printf256mem", X86Mem256AsmOperand>;
326 def f512mem : X86MemOperand<"printf512mem", X86Mem512AsmOperand>;
328 def v512mem : X86VMemOperand<VR512, "printf512mem", X86Mem512AsmOperand>;
330 // Gather mem operands
331 def vx32mem : X86VMemOperand<VR128, "printi32mem", X86MemVX32Operand>;
332 def vy32mem : X86VMemOperand<VR256, "printi32mem", X86MemVY32Operand>;
333 def vx64mem : X86VMemOperand<VR128, "printi64mem", X86MemVX64Operand>;
334 def vy64mem : X86VMemOperand<VR256, "printi64mem", X86MemVY64Operand>;
335 def vy64xmem : X86VMemOperand<VR256X, "printi64mem", X86MemVY64Operand>;
336 def vz32mem : X86VMemOperand<VR512, "printi32mem", X86MemVZ32Operand>;
337 def vz64mem : X86VMemOperand<VR512, "printi64mem", X86MemVZ64Operand>;
339 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
340 // plain GR64, so that it doesn't potentially require a REX prefix.
341 def i8mem_NOREX : Operand<i64> {
342 let PrintMethod = "printi8mem";
343 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
344 let ParserMatchClass = X86Mem8AsmOperand;
345 let OperandType = "OPERAND_MEMORY";
348 // GPRs available for tailcall.
349 // It represents GR32_TC, GR64_TC or GR64_TCW64.
350 def ptr_rc_tailcall : PointerLikeRegClass<2>;
352 // Special i32mem for addresses of load folding tail calls. These are not
353 // allowed to use callee-saved registers since they must be scheduled
354 // after callee-saved register are popped.
355 def i32mem_TC : Operand<i32> {
356 let PrintMethod = "printi32mem";
357 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
359 let ParserMatchClass = X86Mem32AsmOperand;
360 let OperandType = "OPERAND_MEMORY";
363 // Special i64mem for addresses of load folding tail calls. These are not
364 // allowed to use callee-saved registers since they must be scheduled
365 // after callee-saved register are popped.
366 def i64mem_TC : Operand<i64> {
367 let PrintMethod = "printi64mem";
368 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
369 ptr_rc_tailcall, i32imm, i8imm);
370 let ParserMatchClass = X86Mem64AsmOperand;
371 let OperandType = "OPERAND_MEMORY";
374 let OperandType = "OPERAND_PCREL",
375 ParserMatchClass = X86AbsMemAsmOperand,
376 PrintMethod = "printPCRelImm" in {
377 def i32imm_pcrel : Operand<i32>;
378 def i16imm_pcrel : Operand<i16>;
380 // Branch targets have OtherVT type and print as pc-relative values.
381 def brtarget : Operand<OtherVT>;
382 def brtarget8 : Operand<OtherVT>;
386 // Special parser to detect 16-bit mode to select 16-bit displacement.
387 def X86AbsMem16AsmOperand : AsmOperandClass {
388 let Name = "AbsMem16";
389 let RenderMethod = "addAbsMemOperands";
390 let SuperClasses = [X86AbsMemAsmOperand];
393 // Branch targets have OtherVT type and print as pc-relative values.
394 let OperandType = "OPERAND_PCREL",
395 PrintMethod = "printPCRelImm" in {
396 let ParserMatchClass = X86AbsMem16AsmOperand in
397 def brtarget16 : Operand<OtherVT>;
398 let ParserMatchClass = X86AbsMemAsmOperand in
399 def brtarget32 : Operand<OtherVT>;
402 let RenderMethod = "addSrcIdxOperands" in {
403 def X86SrcIdx8Operand : AsmOperandClass {
404 let Name = "SrcIdx8";
405 let SuperClasses = [X86Mem8AsmOperand];
407 def X86SrcIdx16Operand : AsmOperandClass {
408 let Name = "SrcIdx16";
409 let SuperClasses = [X86Mem16AsmOperand];
411 def X86SrcIdx32Operand : AsmOperandClass {
412 let Name = "SrcIdx32";
413 let SuperClasses = [X86Mem32AsmOperand];
415 def X86SrcIdx64Operand : AsmOperandClass {
416 let Name = "SrcIdx64";
417 let SuperClasses = [X86Mem64AsmOperand];
419 } // RenderMethod = "addSrcIdxOperands"
421 let RenderMethod = "addDstIdxOperands" in {
422 def X86DstIdx8Operand : AsmOperandClass {
423 let Name = "DstIdx8";
424 let SuperClasses = [X86Mem8AsmOperand];
426 def X86DstIdx16Operand : AsmOperandClass {
427 let Name = "DstIdx16";
428 let SuperClasses = [X86Mem16AsmOperand];
430 def X86DstIdx32Operand : AsmOperandClass {
431 let Name = "DstIdx32";
432 let SuperClasses = [X86Mem32AsmOperand];
434 def X86DstIdx64Operand : AsmOperandClass {
435 let Name = "DstIdx64";
436 let SuperClasses = [X86Mem64AsmOperand];
438 } // RenderMethod = "addDstIdxOperands"
440 let RenderMethod = "addMemOffsOperands" in {
441 def X86MemOffs16_8AsmOperand : AsmOperandClass {
442 let Name = "MemOffs16_8";
443 let SuperClasses = [X86Mem8AsmOperand];
445 def X86MemOffs16_16AsmOperand : AsmOperandClass {
446 let Name = "MemOffs16_16";
447 let SuperClasses = [X86Mem16AsmOperand];
449 def X86MemOffs16_32AsmOperand : AsmOperandClass {
450 let Name = "MemOffs16_32";
451 let SuperClasses = [X86Mem32AsmOperand];
453 def X86MemOffs32_8AsmOperand : AsmOperandClass {
454 let Name = "MemOffs32_8";
455 let SuperClasses = [X86Mem8AsmOperand];
457 def X86MemOffs32_16AsmOperand : AsmOperandClass {
458 let Name = "MemOffs32_16";
459 let SuperClasses = [X86Mem16AsmOperand];
461 def X86MemOffs32_32AsmOperand : AsmOperandClass {
462 let Name = "MemOffs32_32";
463 let SuperClasses = [X86Mem32AsmOperand];
465 def X86MemOffs32_64AsmOperand : AsmOperandClass {
466 let Name = "MemOffs32_64";
467 let SuperClasses = [X86Mem64AsmOperand];
469 def X86MemOffs64_8AsmOperand : AsmOperandClass {
470 let Name = "MemOffs64_8";
471 let SuperClasses = [X86Mem8AsmOperand];
473 def X86MemOffs64_16AsmOperand : AsmOperandClass {
474 let Name = "MemOffs64_16";
475 let SuperClasses = [X86Mem16AsmOperand];
477 def X86MemOffs64_32AsmOperand : AsmOperandClass {
478 let Name = "MemOffs64_32";
479 let SuperClasses = [X86Mem32AsmOperand];
481 def X86MemOffs64_64AsmOperand : AsmOperandClass {
482 let Name = "MemOffs64_64";
483 let SuperClasses = [X86Mem64AsmOperand];
485 } // RenderMethod = "addMemOffsOperands"
487 class X86SrcIdxOperand<string printMethod, AsmOperandClass parserMatchClass>
488 : X86MemOperand<printMethod, parserMatchClass> {
489 let MIOperandInfo = (ops ptr_rc, i8imm);
492 class X86DstIdxOperand<string printMethod, AsmOperandClass parserMatchClass>
493 : X86MemOperand<printMethod, parserMatchClass> {
494 let MIOperandInfo = (ops ptr_rc);
497 def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>;
498 def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>;
499 def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>;
500 def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>;
501 def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>;
502 def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>;
503 def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>;
504 def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>;
506 class X86MemOffsOperand<Operand immOperand, string printMethod,
507 AsmOperandClass parserMatchClass>
508 : X86MemOperand<printMethod, parserMatchClass> {
509 let MIOperandInfo = (ops immOperand, i8imm);
512 def offset16_8 : X86MemOffsOperand<i16imm, "printMemOffs8",
513 X86MemOffs16_8AsmOperand>;
514 def offset16_16 : X86MemOffsOperand<i16imm, "printMemOffs16",
515 X86MemOffs16_16AsmOperand>;
516 def offset16_32 : X86MemOffsOperand<i16imm, "printMemOffs32",
517 X86MemOffs16_32AsmOperand>;
518 def offset32_8 : X86MemOffsOperand<i32imm, "printMemOffs8",
519 X86MemOffs32_8AsmOperand>;
520 def offset32_16 : X86MemOffsOperand<i32imm, "printMemOffs16",
521 X86MemOffs32_16AsmOperand>;
522 def offset32_32 : X86MemOffsOperand<i32imm, "printMemOffs32",
523 X86MemOffs32_32AsmOperand>;
524 def offset32_64 : X86MemOffsOperand<i32imm, "printMemOffs64",
525 X86MemOffs32_64AsmOperand>;
526 def offset64_8 : X86MemOffsOperand<i64imm, "printMemOffs8",
527 X86MemOffs64_8AsmOperand>;
528 def offset64_16 : X86MemOffsOperand<i64imm, "printMemOffs16",
529 X86MemOffs64_16AsmOperand>;
530 def offset64_32 : X86MemOffsOperand<i64imm, "printMemOffs32",
531 X86MemOffs64_32AsmOperand>;
532 def offset64_64 : X86MemOffsOperand<i64imm, "printMemOffs64",
533 X86MemOffs64_64AsmOperand>;
535 def SSECC : Operand<i8> {
536 let PrintMethod = "printSSEAVXCC";
537 let OperandType = "OPERAND_IMMEDIATE";
540 def i8immZExt3 : ImmLeaf<i8, [{
541 return Imm >= 0 && Imm < 8;
544 def AVXCC : Operand<i8> {
545 let PrintMethod = "printSSEAVXCC";
546 let OperandType = "OPERAND_IMMEDIATE";
549 def i8immZExt5 : ImmLeaf<i8, [{
550 return Imm >= 0 && Imm < 32;
553 def AVX512ICC : Operand<i8> {
554 let PrintMethod = "printSSEAVXCC";
555 let OperandType = "OPERAND_IMMEDIATE";
558 def XOPCC : Operand<i8> {
559 let PrintMethod = "printXOPCC";
560 let OperandType = "OPERAND_IMMEDIATE";
563 class ImmSExtAsmOperandClass : AsmOperandClass {
564 let SuperClasses = [ImmAsmOperand];
565 let RenderMethod = "addImmOperands";
568 def X86GR32orGR64AsmOperand : AsmOperandClass {
569 let Name = "GR32orGR64";
572 def GR32orGR64 : RegisterOperand<GR32> {
573 let ParserMatchClass = X86GR32orGR64AsmOperand;
575 def AVX512RCOperand : AsmOperandClass {
576 let Name = "AVX512RC";
578 def AVX512RC : Operand<i32> {
579 let PrintMethod = "printRoundingControl";
580 let OperandType = "OPERAND_IMMEDIATE";
581 let ParserMatchClass = AVX512RCOperand;
584 // Sign-extended immediate classes. We don't need to define the full lattice
585 // here because there is no instruction with an ambiguity between ImmSExti64i32
588 // The strange ranges come from the fact that the assembler always works with
589 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
590 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
593 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
594 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
595 let Name = "ImmSExti64i32";
598 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
599 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
600 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
601 let Name = "ImmSExti16i8";
602 let SuperClasses = [ImmSExti64i32AsmOperand];
605 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
606 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
607 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
608 let Name = "ImmSExti32i8";
612 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
613 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
614 let Name = "ImmSExti64i8";
615 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
616 ImmSExti64i32AsmOperand];
619 // Unsigned immediate used by SSE/AVX instructions
621 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
622 def ImmUnsignedi8AsmOperand : AsmOperandClass {
623 let Name = "ImmUnsignedi8";
624 let RenderMethod = "addImmOperands";
627 // A couple of more descriptive operand definitions.
628 // 16-bits but only 8 bits are significant.
629 def i16i8imm : Operand<i16> {
630 let ParserMatchClass = ImmSExti16i8AsmOperand;
631 let OperandType = "OPERAND_IMMEDIATE";
633 // 32-bits but only 8 bits are significant.
634 def i32i8imm : Operand<i32> {
635 let ParserMatchClass = ImmSExti32i8AsmOperand;
636 let OperandType = "OPERAND_IMMEDIATE";
639 // 64-bits but only 32 bits are significant.
640 def i64i32imm : Operand<i64> {
641 let ParserMatchClass = ImmSExti64i32AsmOperand;
642 let OperandType = "OPERAND_IMMEDIATE";
645 // 64-bits but only 8 bits are significant.
646 def i64i8imm : Operand<i64> {
647 let ParserMatchClass = ImmSExti64i8AsmOperand;
648 let OperandType = "OPERAND_IMMEDIATE";
651 // Unsigned 8-bit immediate used by SSE/AVX instructions.
652 def u8imm : Operand<i8> {
653 let PrintMethod = "printU8Imm";
654 let ParserMatchClass = ImmUnsignedi8AsmOperand;
655 let OperandType = "OPERAND_IMMEDIATE";
658 // 32-bit immediate but only 8-bits are significant and they are unsigned.
659 // Used by some SSE/AVX instructions that use intrinsics.
660 def i32u8imm : Operand<i32> {
661 let PrintMethod = "printU8Imm";
662 let ParserMatchClass = ImmUnsignedi8AsmOperand;
663 let OperandType = "OPERAND_IMMEDIATE";
666 // 64-bits but only 32 bits are significant, and those bits are treated as being
668 def i64i32imm_pcrel : Operand<i64> {
669 let PrintMethod = "printPCRelImm";
670 let ParserMatchClass = X86AbsMemAsmOperand;
671 let OperandType = "OPERAND_PCREL";
674 def lea64_32mem : Operand<i32> {
675 let PrintMethod = "printanymem";
676 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
677 let ParserMatchClass = X86MemAsmOperand;
680 // Memory operands that use 64-bit pointers in both ILP32 and LP64.
681 def lea64mem : Operand<i64> {
682 let PrintMethod = "printanymem";
683 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
684 let ParserMatchClass = X86MemAsmOperand;
688 //===----------------------------------------------------------------------===//
689 // X86 Complex Pattern Definitions.
692 // Define X86 specific addressing mode.
693 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
694 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
695 [add, sub, mul, X86mul_imm, shl, or, frameindex],
697 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
698 def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr",
699 [add, sub, mul, X86mul_imm, shl, or,
700 frameindex, X86WrapperRIP],
703 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
704 [tglobaltlsaddr], []>;
706 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
707 [tglobaltlsaddr], []>;
709 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
710 [add, sub, mul, X86mul_imm, shl, or, frameindex,
713 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
714 [tglobaltlsaddr], []>;
716 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
717 [tglobaltlsaddr], []>;
719 def vectoraddr : ComplexPattern<iPTR, 5, "SelectVectorAddr", [],[SDNPWantParent]>;
721 //===----------------------------------------------------------------------===//
722 // X86 Instruction Predicate Definitions.
723 def HasCMov : Predicate<"Subtarget->hasCMov()">;
724 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
726 def HasMMX : Predicate<"Subtarget->hasMMX()">;
727 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
728 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
729 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
730 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
731 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
732 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
733 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
734 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
735 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
736 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
737 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
738 def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">;
739 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
740 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
741 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
742 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
743 def HasAVX : Predicate<"Subtarget->hasAVX()">;
744 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
745 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
746 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">,
747 AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">;
748 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
749 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
750 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
751 def HasCDI : Predicate<"Subtarget->hasCDI()">,
752 AssemblerPredicate<"FeatureCDI", "AVX-512 CD ISA">;
753 def HasPFI : Predicate<"Subtarget->hasPFI()">,
754 AssemblerPredicate<"FeaturePFI", "AVX-512 PF ISA">;
755 def HasERI : Predicate<"Subtarget->hasERI()">,
756 AssemblerPredicate<"FeatureERI", "AVX-512 ER ISA">;
757 def HasDQI : Predicate<"Subtarget->hasDQI()">,
758 AssemblerPredicate<"FeatureDQI", "AVX-512 DQ ISA">;
759 def NoDQI : Predicate<"!Subtarget->hasDQI()">;
760 def HasBWI : Predicate<"Subtarget->hasBWI()">,
761 AssemblerPredicate<"FeatureBWI", "AVX-512 BW ISA">;
762 def HasVLX : Predicate<"Subtarget->hasVLX()">,
763 AssemblerPredicate<"FeatureVLX", "AVX-512 VL ISA">;
764 def NoVLX : Predicate<"!Subtarget->hasVLX()">;
766 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
767 def HasAES : Predicate<"Subtarget->hasAES()">;
768 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
769 def HasFMA : Predicate<"Subtarget->hasFMA()">;
770 def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">;
771 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
772 def HasXOP : Predicate<"Subtarget->hasXOP()">;
773 def HasTBM : Predicate<"Subtarget->hasTBM()">;
774 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
775 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
776 def HasF16C : Predicate<"Subtarget->hasF16C()">;
777 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
778 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
779 def HasBMI : Predicate<"Subtarget->hasBMI()">;
780 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
781 def HasRTM : Predicate<"Subtarget->hasRTM()">;
782 def HasHLE : Predicate<"Subtarget->hasHLE()">;
783 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
784 def HasADX : Predicate<"Subtarget->hasADX()">;
785 def HasSHA : Predicate<"Subtarget->hasSHA()">;
786 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
787 def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
788 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
789 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
790 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
791 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
792 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
793 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
794 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
795 AssemblerPredicate<"Mode64Bit", "64-bit mode">;
796 def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">;
797 def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">;
798 def In16BitMode : Predicate<"Subtarget->is16Bit()">,
799 AssemblerPredicate<"Mode16Bit", "16-bit mode">;
800 def Not16BitMode : Predicate<"!Subtarget->is16Bit()">,
801 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">;
802 def In32BitMode : Predicate<"Subtarget->is32Bit()">,
803 AssemblerPredicate<"Mode32Bit", "32-bit mode">;
804 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
805 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
806 def IsPS4 : Predicate<"Subtarget->isTargetPS4()">;
807 def NotPS4 : Predicate<"!Subtarget->isTargetPS4()">;
808 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
809 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
810 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
811 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
812 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
813 "TM.getCodeModel() != CodeModel::Kernel">;
814 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
815 "TM.getCodeModel() == CodeModel::Kernel">;
816 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
817 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
818 def OptForSize : Predicate<"OptForSize">;
819 def OptForSpeed : Predicate<"!OptForSize">;
820 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
821 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
822 def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">;
823 def NotSlowIncDec : Predicate<"!Subtarget->slowIncDec()">;
824 def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">;
826 //===----------------------------------------------------------------------===//
827 // X86 Instruction Format Definitions.
830 include "X86InstrFormats.td"
832 //===----------------------------------------------------------------------===//
833 // Pattern fragments.
836 // X86 specific condition code. These correspond to CondCode in
837 // X86InstrInfo.h. They must be kept in synch.
838 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
839 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
840 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
841 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
842 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
843 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
844 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
845 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
846 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
847 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
848 def X86_COND_NO : PatLeaf<(i8 10)>;
849 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
850 def X86_COND_NS : PatLeaf<(i8 12)>;
851 def X86_COND_O : PatLeaf<(i8 13)>;
852 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
853 def X86_COND_S : PatLeaf<(i8 15)>;
855 // Predicate used to help when pattern matching LZCNT/TZCNT.
856 def X86_COND_E_OR_NE : ImmLeaf<i8, [{
857 return (Imm == X86::COND_E) || (Imm == X86::COND_NE);
861 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
862 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
863 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
866 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
869 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
871 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
873 def i64immZExt32SExt8 : ImmLeaf<i64, [{
874 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
877 // Helper fragments for loads.
878 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
879 // known to be 32-bit aligned or better. Ditto for i8 to i16.
880 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
881 LoadSDNode *LD = cast<LoadSDNode>(N);
882 ISD::LoadExtType ExtType = LD->getExtensionType();
883 if (ExtType == ISD::NON_EXTLOAD)
885 if (ExtType == ISD::EXTLOAD)
886 return LD->getAlignment() >= 2 && !LD->isVolatile();
890 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
891 LoadSDNode *LD = cast<LoadSDNode>(N);
892 ISD::LoadExtType ExtType = LD->getExtensionType();
893 if (ExtType == ISD::EXTLOAD)
894 return LD->getAlignment() >= 2 && !LD->isVolatile();
898 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
899 LoadSDNode *LD = cast<LoadSDNode>(N);
900 ISD::LoadExtType ExtType = LD->getExtensionType();
901 if (ExtType == ISD::NON_EXTLOAD)
903 if (ExtType == ISD::EXTLOAD)
904 return LD->getAlignment() >= 4 && !LD->isVolatile();
908 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
909 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
910 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
911 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
912 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
914 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
915 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
916 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
917 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
918 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
919 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
921 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
922 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
923 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
924 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
925 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
926 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
927 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
928 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
929 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
930 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
932 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
933 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
934 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
935 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
936 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
937 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
938 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
939 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
940 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
941 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
944 // An 'and' node with a single use.
945 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
946 return N->hasOneUse();
948 // An 'srl' node with a single use.
949 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
950 return N->hasOneUse();
952 // An 'trunc' node with a single use.
953 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
954 return N->hasOneUse();
957 //===----------------------------------------------------------------------===//
962 let hasSideEffects = 0, SchedRW = [WriteZero] in {
963 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
964 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero),
965 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
966 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero),
967 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
971 // Constructing a stack frame.
972 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
973 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
975 let SchedRW = [WriteALU] in {
976 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in
977 def LEAVE : I<0xC9, RawFrm,
978 (outs), (ins), "leave", [], IIC_LEAVE>,
979 Requires<[Not64BitMode]>;
981 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in
982 def LEAVE64 : I<0xC9, RawFrm,
983 (outs), (ins), "leave", [], IIC_LEAVE>,
984 Requires<[In64BitMode]>;
987 //===----------------------------------------------------------------------===//
988 // Miscellaneous Instructions.
991 let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in {
992 let mayLoad = 1, SchedRW = [WriteLoad] in {
993 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
994 IIC_POP_REG16>, OpSize16;
995 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
996 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
997 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
998 IIC_POP_REG>, OpSize16;
999 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
1000 IIC_POP_MEM>, OpSize16;
1001 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
1002 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
1003 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
1004 IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>;
1005 } // mayLoad, SchedRW
1007 let mayStore = 1, SchedRW = [WriteStore] in {
1008 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
1009 IIC_PUSH_REG>, OpSize16;
1010 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
1011 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
1012 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
1013 IIC_PUSH_REG>, OpSize16;
1014 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
1015 IIC_PUSH_MEM>, OpSize16;
1016 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
1017 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
1018 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
1019 IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>;
1021 def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
1022 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1023 Requires<[Not64BitMode]>;
1024 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
1025 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1026 Requires<[Not64BitMode]>;
1027 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1028 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1029 Requires<[Not64BitMode]>;
1030 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
1031 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1032 Requires<[Not64BitMode]>;
1033 } // mayStore, SchedRW
1036 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
1037 SchedRW = [WriteLoad] in {
1038 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>,
1040 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
1041 OpSize32, Requires<[Not64BitMode]>;
1044 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0,
1045 SchedRW = [WriteStore] in {
1046 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
1048 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
1049 OpSize32, Requires<[Not64BitMode]>;
1052 let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in {
1053 let mayLoad = 1, SchedRW = [WriteLoad] in {
1054 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1055 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
1056 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1057 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
1058 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [],
1059 IIC_POP_MEM>, OpSize32, Requires<[In64BitMode]>;
1060 } // mayLoad, SchedRW
1061 let mayStore = 1, SchedRW = [WriteStore] in {
1062 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1063 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1064 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1065 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1066 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
1067 IIC_PUSH_MEM>, OpSize32, Requires<[In64BitMode]>;
1068 } // mayStore, SchedRW
1071 let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1,
1072 SchedRW = [WriteStore] in {
1073 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
1074 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
1075 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1076 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1077 Requires<[In64BitMode]>;
1078 def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
1079 "push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1080 Requires<[In64BitMode]>;
1083 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
1084 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
1085 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>;
1086 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in
1087 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
1088 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>;
1090 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
1091 mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in {
1092 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>,
1093 OpSize32, Requires<[Not64BitMode]>;
1094 def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>,
1095 OpSize16, Requires<[Not64BitMode]>;
1097 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
1098 mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
1099 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>,
1100 OpSize32, Requires<[Not64BitMode]>;
1101 def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>,
1102 OpSize16, Requires<[Not64BitMode]>;
1105 let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
1106 // GR32 = bswap GR32
1107 def BSWAP32r : I<0xC8, AddRegFrm,
1108 (outs GR32:$dst), (ins GR32:$src),
1110 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB;
1112 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
1114 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
1115 } // Constraints = "$src = $dst", SchedRW
1117 // Bit scan instructions.
1118 let Defs = [EFLAGS] in {
1119 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1120 "bsf{w}\t{$src, $dst|$dst, $src}",
1121 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
1122 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1123 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1124 "bsf{w}\t{$src, $dst|$dst, $src}",
1125 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
1126 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1127 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1128 "bsf{l}\t{$src, $dst|$dst, $src}",
1129 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
1130 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1131 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1132 "bsf{l}\t{$src, $dst|$dst, $src}",
1133 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
1134 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1135 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1136 "bsf{q}\t{$src, $dst|$dst, $src}",
1137 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
1138 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1139 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1140 "bsf{q}\t{$src, $dst|$dst, $src}",
1141 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
1142 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1144 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1145 "bsr{w}\t{$src, $dst|$dst, $src}",
1146 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))],
1147 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1148 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1149 "bsr{w}\t{$src, $dst|$dst, $src}",
1150 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
1151 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1152 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1153 "bsr{l}\t{$src, $dst|$dst, $src}",
1154 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
1155 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1156 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1157 "bsr{l}\t{$src, $dst|$dst, $src}",
1158 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
1159 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1160 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1161 "bsr{q}\t{$src, $dst|$dst, $src}",
1162 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))],
1163 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1164 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1165 "bsr{q}\t{$src, $dst|$dst, $src}",
1166 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
1167 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1168 } // Defs = [EFLAGS]
1170 let SchedRW = [WriteMicrocoded] in {
1171 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1172 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
1173 def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src),
1174 "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1175 def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src),
1176 "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16;
1177 def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src),
1178 "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize32;
1179 def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src),
1180 "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1183 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1184 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
1185 def STOSB : I<0xAA, RawFrmDst, (outs dstidx8:$dst), (ins),
1186 "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>;
1187 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
1188 def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins),
1189 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16;
1190 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
1191 def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins),
1192 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32;
1193 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
1194 def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins),
1195 "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>;
1197 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1198 let Defs = [EDI,EFLAGS], Uses = [AL,EDI,EFLAGS] in
1199 def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst),
1200 "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>;
1201 let Defs = [EDI,EFLAGS], Uses = [AX,EDI,EFLAGS] in
1202 def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst),
1203 "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16;
1204 let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,EFLAGS] in
1205 def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst),
1206 "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32;
1207 let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,EFLAGS] in
1208 def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst),
1209 "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>;
1211 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1212 let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,EFLAGS] in {
1213 def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src),
1214 "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1215 def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src),
1216 "cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16;
1217 def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src),
1218 "cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize32;
1219 def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src),
1220 "cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1224 //===----------------------------------------------------------------------===//
1225 // Move Instructions.
1227 let SchedRW = [WriteMove] in {
1228 let hasSideEffects = 0 in {
1229 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1230 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1231 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1232 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1233 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1234 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1235 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1236 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1239 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1240 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1241 "mov{b}\t{$src, $dst|$dst, $src}",
1242 [(set GR8:$dst, imm:$src)], IIC_MOV>;
1243 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1244 "mov{w}\t{$src, $dst|$dst, $src}",
1245 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize16;
1246 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1247 "mov{l}\t{$src, $dst|$dst, $src}",
1248 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize32;
1249 def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1250 "mov{q}\t{$src, $dst|$dst, $src}",
1251 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
1253 let isReMaterializable = 1 in {
1254 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
1255 "movabs{q}\t{$src, $dst|$dst, $src}",
1256 [(set GR64:$dst, imm:$src)], IIC_MOV>;
1259 // Longer forms that use a ModR/M byte. Needed for disassembler
1260 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1261 def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src),
1262 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1263 def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src),
1264 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1265 def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src),
1266 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1270 let SchedRW = [WriteStore] in {
1271 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1272 "mov{b}\t{$src, $dst|$dst, $src}",
1273 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
1274 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1275 "mov{w}\t{$src, $dst|$dst, $src}",
1276 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
1277 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1278 "mov{l}\t{$src, $dst|$dst, $src}",
1279 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32;
1280 def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1281 "mov{q}\t{$src, $dst|$dst, $src}",
1282 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
1285 let hasSideEffects = 0 in {
1287 /// Memory offset versions of moves. The immediate is an address mode sized
1288 /// offset from the segment base.
1289 let SchedRW = [WriteALU] in {
1290 let mayLoad = 1 in {
1292 def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src),
1293 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
1296 def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src),
1297 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1300 def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src),
1301 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1304 def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src),
1305 "mov{q}\t{$src, %rax|rax, $src}", [], IIC_MOV_MEM>,
1309 def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src),
1310 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, AdSize16;
1312 def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src),
1313 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1316 def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src),
1317 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1320 let mayStore = 1 in {
1322 def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs offset32_8:$dst), (ins),
1323 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize32;
1325 def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_16:$dst), (ins),
1326 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1329 def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_32:$dst), (ins),
1330 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1333 def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs offset32_64:$dst), (ins),
1334 "mov{q}\t{%rax, $dst|$dst, rax}", [], IIC_MOV_MEM>,
1338 def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs offset16_8:$dst), (ins),
1339 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize16;
1341 def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_16:$dst), (ins),
1342 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1345 def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_32:$dst), (ins),
1346 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1351 // These forms all have full 64-bit absolute addresses in their instructions
1352 // and use the movabs mnemonic to indicate this specific form.
1353 let mayLoad = 1 in {
1355 def MOV8ao64 : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src),
1356 "movabs{b}\t{$src, %al|al, $src}", []>, AdSize64;
1358 def MOV16ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src),
1359 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16, AdSize64;
1361 def MOV32ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src),
1362 "movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32,
1365 def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src),
1366 "movabs{q}\t{$src, %rax|rax, $src}", []>, AdSize64;
1369 let mayStore = 1 in {
1371 def MOV8o64a : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset64_8:$dst), (ins),
1372 "movabs{b}\t{%al, $dst|$dst, al}", []>, AdSize64;
1374 def MOV16o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_16:$dst), (ins),
1375 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16, AdSize64;
1377 def MOV32o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_32:$dst), (ins),
1378 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32,
1381 def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs offset64_64:$dst), (ins),
1382 "movabs{q}\t{%rax, $dst|$dst, rax}", []>, AdSize64;
1384 } // hasSideEffects = 0
1386 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
1387 SchedRW = [WriteMove] in {
1388 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1389 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1390 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1391 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1392 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1393 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1394 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1395 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1398 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1399 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1400 "mov{b}\t{$src, $dst|$dst, $src}",
1401 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1402 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1403 "mov{w}\t{$src, $dst|$dst, $src}",
1404 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize16;
1405 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1406 "mov{l}\t{$src, $dst|$dst, $src}",
1407 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32;
1408 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1409 "mov{q}\t{$src, $dst|$dst, $src}",
1410 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1413 let SchedRW = [WriteStore] in {
1414 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1415 "mov{b}\t{$src, $dst|$dst, $src}",
1416 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1417 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1418 "mov{w}\t{$src, $dst|$dst, $src}",
1419 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
1420 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1421 "mov{l}\t{$src, $dst|$dst, $src}",
1422 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32;
1423 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1424 "mov{q}\t{$src, $dst|$dst, $src}",
1425 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1428 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1429 // that they can be used for copying and storing h registers, which can't be
1430 // encoded when a REX prefix is present.
1431 let isCodeGenOnly = 1 in {
1432 let hasSideEffects = 0 in
1433 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1434 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1435 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
1437 let mayStore = 1, hasSideEffects = 0 in
1438 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1439 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1440 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1441 IIC_MOV_MEM>, Sched<[WriteStore]>;
1442 let mayLoad = 1, hasSideEffects = 0,
1443 canFoldAsLoad = 1, isReMaterializable = 1 in
1444 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1445 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1446 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1447 IIC_MOV_MEM>, Sched<[WriteLoad]>;
1451 // Condition code ops, incl. set if equal/not equal/...
1452 let SchedRW = [WriteALU] in {
1453 let Defs = [EFLAGS], Uses = [AH] in
1454 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1455 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
1456 let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in
1457 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1458 IIC_AHF>; // AH = flags
1461 //===----------------------------------------------------------------------===//
1462 // Bit tests instructions: BT, BTS, BTR, BTC.
1464 let Defs = [EFLAGS] in {
1465 let SchedRW = [WriteALU] in {
1466 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1467 "bt{w}\t{$src2, $src1|$src1, $src2}",
1468 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1470 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1471 "bt{l}\t{$src2, $src1|$src1, $src2}",
1472 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,
1474 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1475 "bt{q}\t{$src2, $src1|$src1, $src2}",
1476 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1479 // Unlike with the register+register form, the memory+register form of the
1480 // bt instruction does not ignore the high bits of the index. From ISel's
1481 // perspective, this is pretty bizarre. Make these instructions disassembly
1484 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
1485 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1486 "bt{w}\t{$src2, $src1|$src1, $src2}",
1487 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1488 // (implicit EFLAGS)]
1490 >, OpSize16, TB, Requires<[FastBTMem]>;
1491 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1492 "bt{l}\t{$src2, $src1|$src1, $src2}",
1493 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1494 // (implicit EFLAGS)]
1496 >, OpSize32, TB, Requires<[FastBTMem]>;
1497 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1498 "bt{q}\t{$src2, $src1|$src1, $src2}",
1499 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1500 // (implicit EFLAGS)]
1505 let SchedRW = [WriteALU] in {
1506 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1507 "bt{w}\t{$src2, $src1|$src1, $src2}",
1508 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1509 IIC_BT_RI>, OpSize16, TB;
1510 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1511 "bt{l}\t{$src2, $src1|$src1, $src2}",
1512 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1513 IIC_BT_RI>, OpSize32, TB;
1514 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1515 "bt{q}\t{$src2, $src1|$src1, $src2}",
1516 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1520 // Note that these instructions don't need FastBTMem because that
1521 // only applies when the other operand is in a register. When it's
1522 // an immediate, bt is still fast.
1523 let SchedRW = [WriteALU] in {
1524 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1525 "bt{w}\t{$src2, $src1|$src1, $src2}",
1526 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1527 ], IIC_BT_MI>, OpSize16, TB;
1528 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1529 "bt{l}\t{$src2, $src1|$src1, $src2}",
1530 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1531 ], IIC_BT_MI>, OpSize32, TB;
1532 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1533 "bt{q}\t{$src2, $src1|$src1, $src2}",
1534 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1535 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1538 let hasSideEffects = 0 in {
1539 let SchedRW = [WriteALU] in {
1540 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1541 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1543 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1544 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1546 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1547 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1550 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1551 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1552 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1554 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1555 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1557 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1558 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1561 let SchedRW = [WriteALU] in {
1562 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1563 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1565 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1566 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1568 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1569 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1572 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1573 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1574 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1576 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1577 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1579 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1580 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1583 let SchedRW = [WriteALU] in {
1584 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1585 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1587 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1588 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1590 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1591 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1594 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1595 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1596 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1598 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1599 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1601 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1602 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1605 let SchedRW = [WriteALU] in {
1606 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1607 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1609 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1610 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1612 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1613 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1616 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1617 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1618 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1620 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1621 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1623 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1624 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1627 let SchedRW = [WriteALU] in {
1628 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1629 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1631 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1632 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1634 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1635 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1638 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1639 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1640 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1642 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1643 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1645 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1646 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1649 let SchedRW = [WriteALU] in {
1650 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1651 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1653 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1654 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1656 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1657 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1660 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1661 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1662 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1664 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1665 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1667 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1668 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1670 } // hasSideEffects = 0
1671 } // Defs = [EFLAGS]
1674 //===----------------------------------------------------------------------===//
1678 // Atomic swap. These are just normal xchg instructions. But since a memory
1679 // operand is referenced, the atomicity is ensured.
1680 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
1681 InstrItinClass itin> {
1682 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
1683 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
1684 (ins GR8:$val, i8mem:$ptr),
1685 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
1688 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
1690 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
1691 (ins GR16:$val, i16mem:$ptr),
1692 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
1695 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
1697 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
1698 (ins GR32:$val, i32mem:$ptr),
1699 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
1702 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
1704 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
1705 (ins GR64:$val, i64mem:$ptr),
1706 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
1709 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
1714 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
1716 // Swap between registers.
1717 let SchedRW = [WriteALU] in {
1718 let Constraints = "$val = $dst" in {
1719 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1720 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1721 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1722 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1724 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1725 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1727 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1728 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1731 // Swap between EAX and other registers.
1732 let Uses = [AX], Defs = [AX] in
1733 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1734 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16;
1735 let Uses = [EAX], Defs = [EAX] in
1736 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1737 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1738 OpSize32, Requires<[Not64BitMode]>;
1739 let Uses = [EAX], Defs = [EAX] in
1740 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1741 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1742 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1743 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1744 OpSize32, Requires<[In64BitMode]>;
1745 let Uses = [RAX], Defs = [RAX] in
1746 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1747 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>;
1750 let SchedRW = [WriteALU] in {
1751 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1752 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1753 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1754 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1756 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1757 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1759 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1760 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1763 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1764 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1765 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1766 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1767 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1769 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1770 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1772 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1773 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1777 let SchedRW = [WriteALU] in {
1778 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1779 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1780 IIC_CMPXCHG_REG8>, TB;
1781 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1782 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1783 IIC_CMPXCHG_REG>, TB, OpSize16;
1784 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1785 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1786 IIC_CMPXCHG_REG>, TB, OpSize32;
1787 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1788 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1789 IIC_CMPXCHG_REG>, TB;
1792 let SchedRW = [WriteALULd, WriteRMW] in {
1793 let mayLoad = 1, mayStore = 1 in {
1794 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1795 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1796 IIC_CMPXCHG_MEM8>, TB;
1797 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1798 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1799 IIC_CMPXCHG_MEM>, TB, OpSize16;
1800 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1801 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1802 IIC_CMPXCHG_MEM>, TB, OpSize32;
1803 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1804 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1805 IIC_CMPXCHG_MEM>, TB;
1808 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1809 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1810 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1812 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1813 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1814 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1815 TB, Requires<[HasCmpxchg16b]>;
1819 // Lock instruction prefix
1820 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1822 // Rex64 instruction prefix
1823 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>,
1824 Requires<[In64BitMode]>;
1826 // Data16 instruction prefix
1827 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1829 // Repeat string operation instruction prefixes
1830 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1831 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1832 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1833 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1834 // Repeat while not equal (used with CMPS and SCAS)
1835 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1839 // String manipulation instructions
1840 let SchedRW = [WriteMicrocoded] in {
1841 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1842 let Defs = [AL,ESI], Uses = [ESI,EFLAGS] in
1843 def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src),
1844 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>;
1845 let Defs = [AX,ESI], Uses = [ESI,EFLAGS] in
1846 def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src),
1847 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16;
1848 let Defs = [EAX,ESI], Uses = [ESI,EFLAGS] in
1849 def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src),
1850 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32;
1851 let Defs = [RAX,ESI], Uses = [ESI,EFLAGS] in
1852 def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),
1853 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>;
1856 let SchedRW = [WriteSystem] in {
1857 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1858 let Defs = [ESI], Uses = [DX,ESI,EFLAGS] in {
1859 def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src),
1860 "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>;
1861 def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src),
1862 "outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16;
1863 def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src),
1864 "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32;
1867 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1868 let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in {
1869 def INSB : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins),
1870 "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
1871 def INSW : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins),
1872 "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
1873 def INSL : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins),
1874 "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32;
1878 // Flag instructions
1879 let SchedRW = [WriteALU] in {
1880 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1881 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1882 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1883 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1884 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1885 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1886 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1888 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1891 // Table lookup instructions
1892 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,
1895 let SchedRW = [WriteMicrocoded] in {
1896 // ASCII Adjust After Addition
1897 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1898 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1899 Requires<[Not64BitMode]>;
1901 // ASCII Adjust AX Before Division
1902 // sets AL, AH and EFLAGS and uses AL and AH
1903 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1904 "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>;
1906 // ASCII Adjust AX After Multiply
1907 // sets AL, AH and EFLAGS and uses AL
1908 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1909 "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>;
1911 // ASCII Adjust AL After Subtraction - sets
1912 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1913 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1914 Requires<[Not64BitMode]>;
1916 // Decimal Adjust AL after Addition
1917 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1918 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1919 Requires<[Not64BitMode]>;
1921 // Decimal Adjust AL after Subtraction
1922 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1923 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1924 Requires<[Not64BitMode]>;
1927 let SchedRW = [WriteSystem] in {
1928 // Check Array Index Against Bounds
1929 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1930 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,
1931 Requires<[Not64BitMode]>;
1932 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1933 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize32,
1934 Requires<[Not64BitMode]>;
1936 // Adjust RPL Field of Segment Selector
1937 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1938 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1939 Requires<[Not64BitMode]>;
1940 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1941 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1942 Requires<[Not64BitMode]>;
1945 //===----------------------------------------------------------------------===//
1946 // MOVBE Instructions
1948 let Predicates = [HasMOVBE] in {
1949 let SchedRW = [WriteALULd] in {
1950 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1951 "movbe{w}\t{$src, $dst|$dst, $src}",
1952 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1954 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1955 "movbe{l}\t{$src, $dst|$dst, $src}",
1956 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1958 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1959 "movbe{q}\t{$src, $dst|$dst, $src}",
1960 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
1963 let SchedRW = [WriteStore] in {
1964 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1965 "movbe{w}\t{$src, $dst|$dst, $src}",
1966 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1968 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1969 "movbe{l}\t{$src, $dst|$dst, $src}",
1970 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1972 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1973 "movbe{q}\t{$src, $dst|$dst, $src}",
1974 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
1979 //===----------------------------------------------------------------------===//
1980 // RDRAND Instruction
1982 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1983 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1985 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
1986 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1988 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, TB;
1989 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1991 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
1994 //===----------------------------------------------------------------------===//
1995 // RDSEED Instruction
1997 let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
1998 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
2000 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
2001 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
2003 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB;
2004 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
2006 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
2009 //===----------------------------------------------------------------------===//
2010 // LZCNT Instruction
2012 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
2013 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2014 "lzcnt{w}\t{$src, $dst|$dst, $src}",
2015 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
2017 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2018 "lzcnt{w}\t{$src, $dst|$dst, $src}",
2019 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
2020 (implicit EFLAGS)]>, XS, OpSize16;
2022 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2023 "lzcnt{l}\t{$src, $dst|$dst, $src}",
2024 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS,
2026 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2027 "lzcnt{l}\t{$src, $dst|$dst, $src}",
2028 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
2029 (implicit EFLAGS)]>, XS, OpSize32;
2031 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2032 "lzcnt{q}\t{$src, $dst|$dst, $src}",
2033 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
2035 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2036 "lzcnt{q}\t{$src, $dst|$dst, $src}",
2037 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
2038 (implicit EFLAGS)]>, XS;
2041 let Predicates = [HasLZCNT] in {
2042 def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
2043 (X86cmp GR16:$src, (i16 0))),
2044 (LZCNT16rr GR16:$src)>;
2045 def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
2046 (X86cmp GR32:$src, (i32 0))),
2047 (LZCNT32rr GR32:$src)>;
2048 def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
2049 (X86cmp GR64:$src, (i64 0))),
2050 (LZCNT64rr GR64:$src)>;
2051 def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_E_OR_NE),
2052 (X86cmp GR16:$src, (i16 0))),
2053 (LZCNT16rr GR16:$src)>;
2054 def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_E_OR_NE),
2055 (X86cmp GR32:$src, (i32 0))),
2056 (LZCNT32rr GR32:$src)>;
2057 def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_E_OR_NE),
2058 (X86cmp GR64:$src, (i64 0))),
2059 (LZCNT64rr GR64:$src)>;
2061 def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
2062 (X86cmp (loadi16 addr:$src), (i16 0))),
2063 (LZCNT16rm addr:$src)>;
2064 def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
2065 (X86cmp (loadi32 addr:$src), (i32 0))),
2066 (LZCNT32rm addr:$src)>;
2067 def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
2068 (X86cmp (loadi64 addr:$src), (i64 0))),
2069 (LZCNT64rm addr:$src)>;
2070 def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
2071 (X86cmp (loadi16 addr:$src), (i16 0))),
2072 (LZCNT16rm addr:$src)>;
2073 def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
2074 (X86cmp (loadi32 addr:$src), (i32 0))),
2075 (LZCNT32rm addr:$src)>;
2076 def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
2077 (X86cmp (loadi64 addr:$src), (i64 0))),
2078 (LZCNT64rm addr:$src)>;
2081 //===----------------------------------------------------------------------===//
2084 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2085 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2086 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2087 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
2089 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2090 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2091 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
2092 (implicit EFLAGS)]>, XS, OpSize16;
2094 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2095 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2096 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS,
2098 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2099 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2100 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
2101 (implicit EFLAGS)]>, XS, OpSize32;
2103 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2104 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2105 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
2107 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2108 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2109 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
2110 (implicit EFLAGS)]>, XS;
2113 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
2114 RegisterClass RC, X86MemOperand x86memop> {
2115 let hasSideEffects = 0 in {
2116 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
2117 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2120 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
2121 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2126 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2127 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>;
2128 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
2129 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>;
2130 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W;
2131 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>;
2132 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W;
2135 //===----------------------------------------------------------------------===//
2136 // Pattern fragments to auto generate BMI instructions.
2137 //===----------------------------------------------------------------------===//
2139 let Predicates = [HasBMI] in {
2140 // FIXME: patterns for the load versions are not implemented
2141 def : Pat<(and GR32:$src, (add GR32:$src, -1)),
2142 (BLSR32rr GR32:$src)>;
2143 def : Pat<(and GR64:$src, (add GR64:$src, -1)),
2144 (BLSR64rr GR64:$src)>;
2146 def : Pat<(xor GR32:$src, (add GR32:$src, -1)),
2147 (BLSMSK32rr GR32:$src)>;
2148 def : Pat<(xor GR64:$src, (add GR64:$src, -1)),
2149 (BLSMSK64rr GR64:$src)>;
2151 def : Pat<(and GR32:$src, (ineg GR32:$src)),
2152 (BLSI32rr GR32:$src)>;
2153 def : Pat<(and GR64:$src, (ineg GR64:$src)),
2154 (BLSI64rr GR64:$src)>;
2157 let Predicates = [HasBMI] in {
2158 def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
2159 (X86cmp GR16:$src, (i16 0))),
2160 (TZCNT16rr GR16:$src)>;
2161 def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
2162 (X86cmp GR32:$src, (i32 0))),
2163 (TZCNT32rr GR32:$src)>;
2164 def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
2165 (X86cmp GR64:$src, (i64 0))),
2166 (TZCNT64rr GR64:$src)>;
2167 def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_E_OR_NE),
2168 (X86cmp GR16:$src, (i16 0))),
2169 (TZCNT16rr GR16:$src)>;
2170 def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_E_OR_NE),
2171 (X86cmp GR32:$src, (i32 0))),
2172 (TZCNT32rr GR32:$src)>;
2173 def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_E_OR_NE),
2174 (X86cmp GR64:$src, (i64 0))),
2175 (TZCNT64rr GR64:$src)>;
2177 def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
2178 (X86cmp (loadi16 addr:$src), (i16 0))),
2179 (TZCNT16rm addr:$src)>;
2180 def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
2181 (X86cmp (loadi32 addr:$src), (i32 0))),
2182 (TZCNT32rm addr:$src)>;
2183 def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
2184 (X86cmp (loadi64 addr:$src), (i64 0))),
2185 (TZCNT64rm addr:$src)>;
2186 def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
2187 (X86cmp (loadi16 addr:$src), (i16 0))),
2188 (TZCNT16rm addr:$src)>;
2189 def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
2190 (X86cmp (loadi32 addr:$src), (i32 0))),
2191 (TZCNT32rm addr:$src)>;
2192 def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
2193 (X86cmp (loadi64 addr:$src), (i64 0))),
2194 (TZCNT64rm addr:$src)>;
2198 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
2199 X86MemOperand x86memop, Intrinsic Int,
2201 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2202 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2203 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
2205 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
2206 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2207 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
2208 (implicit EFLAGS)]>, T8PS, VEX_4VOp3;
2211 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2212 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
2213 int_x86_bmi_bextr_32, loadi32>;
2214 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
2215 int_x86_bmi_bextr_64, loadi64>, VEX_W;
2218 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
2219 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
2220 int_x86_bmi_bzhi_32, loadi32>;
2221 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
2222 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
2226 def CountTrailingOnes : SDNodeXForm<imm, [{
2227 // Count the trailing ones in the immediate.
2228 return getI8Imm(countTrailingOnes(N->getZExtValue()), SDLoc(N));
2231 def BZHIMask : ImmLeaf<i64, [{
2232 return isMask_64(Imm) && (countTrailingOnes<uint64_t>(Imm) > 32);
2235 let Predicates = [HasBMI2] in {
2236 def : Pat<(and GR64:$src, BZHIMask:$mask),
2237 (BZHI64rr GR64:$src,
2238 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2239 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>;
2241 def : Pat<(and GR32:$src, (add (shl 1, GR8:$lz), -1)),
2242 (BZHI32rr GR32:$src,
2243 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2245 def : Pat<(and (loadi32 addr:$src), (add (shl 1, GR8:$lz), -1)),
2246 (BZHI32rm addr:$src,
2247 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2249 def : Pat<(and GR64:$src, (add (shl 1, GR8:$lz), -1)),
2250 (BZHI64rr GR64:$src,
2251 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2253 def : Pat<(and (loadi64 addr:$src), (add (shl 1, GR8:$lz), -1)),
2254 (BZHI64rm addr:$src,
2255 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2258 let Predicates = [HasBMI] in {
2259 def : Pat<(X86bextr GR32:$src1, GR32:$src2),
2260 (BEXTR32rr GR32:$src1, GR32:$src2)>;
2261 def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2),
2262 (BEXTR32rm addr:$src1, GR32:$src2)>;
2263 def : Pat<(X86bextr GR64:$src1, GR64:$src2),
2264 (BEXTR64rr GR64:$src1, GR64:$src2)>;
2265 def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2),
2266 (BEXTR64rm addr:$src1, GR64:$src2)>;
2269 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
2270 X86MemOperand x86memop, Intrinsic Int,
2272 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2273 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2274 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
2276 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2277 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2278 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
2281 let Predicates = [HasBMI2] in {
2282 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
2283 int_x86_bmi_pdep_32, loadi32>, T8XD;
2284 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
2285 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
2286 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
2287 int_x86_bmi_pext_32, loadi32>, T8XS;
2288 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
2289 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
2292 //===----------------------------------------------------------------------===//
2295 let Predicates = [HasTBM], Defs = [EFLAGS] in {
2297 multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr,
2298 X86MemOperand x86memop, PatFrag ld_frag,
2299 Intrinsic Int, Operand immtype,
2300 SDPatternOperator immoperator> {
2301 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
2302 !strconcat(OpcodeStr,
2303 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2304 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>,
2306 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst),
2307 (ins x86memop:$src1, immtype:$cntl),
2308 !strconcat(OpcodeStr,
2309 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2310 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>,
2314 defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32,
2315 int_x86_tbm_bextri_u32, i32imm, imm>;
2316 let ImmT = Imm32S in
2317 defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64,
2318 int_x86_tbm_bextri_u64, i64i32imm,
2319 i64immSExt32>, VEX_W;
2321 multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem,
2322 RegisterClass RC, string OpcodeStr,
2323 X86MemOperand x86memop, PatFrag ld_frag> {
2324 let hasSideEffects = 0 in {
2325 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src),
2326 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2329 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src),
2330 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2335 multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr,
2336 Format FormReg, Format FormMem> {
2337 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem,
2339 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem,
2343 defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
2344 defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>;
2345 defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>;
2346 defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>;
2347 defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>;
2348 defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>;
2349 defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>;
2350 defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>;
2351 defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>;
2354 //===----------------------------------------------------------------------===//
2355 // Pattern fragments to auto generate TBM instructions.
2356 //===----------------------------------------------------------------------===//
2358 let Predicates = [HasTBM] in {
2359 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)),
2360 (BEXTRI32ri GR32:$src1, imm:$src2)>;
2361 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)),
2362 (BEXTRI32mi addr:$src1, imm:$src2)>;
2363 def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2),
2364 (BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>;
2365 def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2),
2366 (BEXTRI64mi addr:$src1, i64immSExt32:$src2)>;
2368 // FIXME: patterns for the load versions are not implemented
2369 def : Pat<(and GR32:$src, (add GR32:$src, 1)),
2370 (BLCFILL32rr GR32:$src)>;
2371 def : Pat<(and GR64:$src, (add GR64:$src, 1)),
2372 (BLCFILL64rr GR64:$src)>;
2374 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
2375 (BLCI32rr GR32:$src)>;
2376 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
2377 (BLCI64rr GR64:$src)>;
2379 // Extra patterns because opt can optimize the above patterns to this.
2380 def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
2381 (BLCI32rr GR32:$src)>;
2382 def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
2383 (BLCI64rr GR64:$src)>;
2385 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
2386 (BLCIC32rr GR32:$src)>;
2387 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),
2388 (BLCIC64rr GR64:$src)>;
2390 def : Pat<(xor GR32:$src, (add GR32:$src, 1)),
2391 (BLCMSK32rr GR32:$src)>;
2392 def : Pat<(xor GR64:$src, (add GR64:$src, 1)),
2393 (BLCMSK64rr GR64:$src)>;
2395 def : Pat<(or GR32:$src, (add GR32:$src, 1)),
2396 (BLCS32rr GR32:$src)>;
2397 def : Pat<(or GR64:$src, (add GR64:$src, 1)),
2398 (BLCS64rr GR64:$src)>;
2400 def : Pat<(or GR32:$src, (add GR32:$src, -1)),
2401 (BLSFILL32rr GR32:$src)>;
2402 def : Pat<(or GR64:$src, (add GR64:$src, -1)),
2403 (BLSFILL64rr GR64:$src)>;
2405 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
2406 (BLSIC32rr GR32:$src)>;
2407 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)),
2408 (BLSIC64rr GR64:$src)>;
2410 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)),
2411 (T1MSKC32rr GR32:$src)>;
2412 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)),
2413 (T1MSKC64rr GR64:$src)>;
2415 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)),
2416 (TZMSK32rr GR32:$src)>;
2417 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)),
2418 (TZMSK64rr GR64:$src)>;
2421 //===----------------------------------------------------------------------===//
2422 // Memory Instructions
2425 def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2426 "clflushopt\t$src", []>, PD;
2427 def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", []>, PD;
2428 def PCOMMIT : I<0xAE, MRM_F8, (outs), (ins), "pcommit", []>, PD;
2431 //===----------------------------------------------------------------------===//
2433 //===----------------------------------------------------------------------===//
2435 include "X86InstrArithmetic.td"
2436 include "X86InstrCMovSetCC.td"
2437 include "X86InstrExtension.td"
2438 include "X86InstrControl.td"
2439 include "X86InstrShiftRotate.td"
2441 // X87 Floating Point Stack.
2442 include "X86InstrFPStack.td"
2444 // SIMD support (SSE, MMX and AVX)
2445 include "X86InstrFragmentsSIMD.td"
2447 // FMA - Fused Multiply-Add support (requires FMA)
2448 include "X86InstrFMA.td"
2451 include "X86InstrXOP.td"
2453 // SSE, MMX and 3DNow! vector support.
2454 include "X86InstrSSE.td"
2455 include "X86InstrAVX512.td"
2456 include "X86InstrMMX.td"
2457 include "X86Instr3DNow.td"
2459 include "X86InstrVMX.td"
2460 include "X86InstrSVM.td"
2462 include "X86InstrTSX.td"
2463 include "X86InstrSGX.td"
2465 // System instructions.
2466 include "X86InstrSystem.td"
2468 // Compiler Pseudo Instructions and Pat Patterns
2469 include "X86InstrCompiler.td"
2471 //===----------------------------------------------------------------------===//
2472 // Assembler Mnemonic Aliases
2473 //===----------------------------------------------------------------------===//
2475 def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>;
2476 def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>;
2477 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;
2479 def : MnemonicAlias<"cbw", "cbtw", "att">;
2480 def : MnemonicAlias<"cwde", "cwtl", "att">;
2481 def : MnemonicAlias<"cwd", "cwtd", "att">;
2482 def : MnemonicAlias<"cdq", "cltd", "att">;
2483 def : MnemonicAlias<"cdqe", "cltq", "att">;
2484 def : MnemonicAlias<"cqo", "cqto", "att">;
2486 // In 64-bit mode lret maps to lretl; it is not ambiguous with lretq.
2487 def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>;
2488 def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>;
2490 def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>;
2491 def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>;
2493 def : MnemonicAlias<"loopz", "loope", "att">;
2494 def : MnemonicAlias<"loopnz", "loopne", "att">;
2496 def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>;
2497 def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>;
2498 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>;
2499 def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>;
2500 def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>;
2501 def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>;
2502 def : MnemonicAlias<"popfd", "popfl", "att">;
2504 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
2505 // all modes. However: "push (addr)" and "push $42" should default to
2506 // pushl/pushq depending on the current mode. Similar for "pop %bx"
2507 def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>;
2508 def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>;
2509 def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>;
2510 def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>;
2511 def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>;
2512 def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
2513 def : MnemonicAlias<"pushfd", "pushfl", "att">;
2515 def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>;
2516 def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>;
2517 def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>;
2518 def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>;
2519 def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>;
2520 def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>;
2522 def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>;
2523 def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>;
2524 def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>;
2525 def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>;
2527 def : MnemonicAlias<"repe", "rep", "att">;
2528 def : MnemonicAlias<"repz", "rep", "att">;
2529 def : MnemonicAlias<"repnz", "repne", "att">;
2531 def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>;
2532 def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>;
2533 def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>;
2535 def : MnemonicAlias<"salb", "shlb", "att">;
2536 def : MnemonicAlias<"salw", "shlw", "att">;
2537 def : MnemonicAlias<"sall", "shll", "att">;
2538 def : MnemonicAlias<"salq", "shlq", "att">;
2540 def : MnemonicAlias<"smovb", "movsb", "att">;
2541 def : MnemonicAlias<"smovw", "movsw", "att">;
2542 def : MnemonicAlias<"smovl", "movsl", "att">;
2543 def : MnemonicAlias<"smovq", "movsq", "att">;
2545 def : MnemonicAlias<"ud2a", "ud2", "att">;
2546 def : MnemonicAlias<"verrw", "verr", "att">;
2548 // System instruction aliases.
2549 def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>;
2550 def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>;
2551 def : MnemonicAlias<"sysret", "sysretl", "att">;
2552 def : MnemonicAlias<"sysexit", "sysexitl", "att">;
2554 def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>;
2555 def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>;
2556 def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>;
2557 def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>;
2558 def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>;
2559 def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>;
2560 def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>;
2561 def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>;
2562 def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>;
2563 def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>;
2564 def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>;
2565 def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>;
2568 // Floating point stack aliases.
2569 def : MnemonicAlias<"fcmovz", "fcmove", "att">;
2570 def : MnemonicAlias<"fcmova", "fcmovnbe", "att">;
2571 def : MnemonicAlias<"fcmovnae", "fcmovb", "att">;
2572 def : MnemonicAlias<"fcmovna", "fcmovbe", "att">;
2573 def : MnemonicAlias<"fcmovae", "fcmovnb", "att">;
2574 def : MnemonicAlias<"fcomip", "fcompi", "att">;
2575 def : MnemonicAlias<"fildq", "fildll", "att">;
2576 def : MnemonicAlias<"fistpq", "fistpll", "att">;
2577 def : MnemonicAlias<"fisttpq", "fisttpll", "att">;
2578 def : MnemonicAlias<"fldcww", "fldcw", "att">;
2579 def : MnemonicAlias<"fnstcww", "fnstcw", "att">;
2580 def : MnemonicAlias<"fnstsww", "fnstsw", "att">;
2581 def : MnemonicAlias<"fucomip", "fucompi", "att">;
2582 def : MnemonicAlias<"fwait", "wait">;
2584 def : MnemonicAlias<"fxsaveq", "fxsave64", "att">;
2585 def : MnemonicAlias<"fxrstorq", "fxrstor64", "att">;
2586 def : MnemonicAlias<"xsaveq", "xsave64", "att">;
2587 def : MnemonicAlias<"xrstorq", "xrstor64", "att">;
2588 def : MnemonicAlias<"xsaveoptq", "xsaveopt64", "att">;
2591 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond,
2593 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
2594 !strconcat(Prefix, NewCond, Suffix), VariantName>;
2596 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
2597 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
2598 /// example "setz" -> "sete".
2599 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix,
2601 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb
2602 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete
2603 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe
2604 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae
2605 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae
2606 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle
2607 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge
2608 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne
2609 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp
2610 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp
2612 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb
2613 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta
2614 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl
2615 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg
2618 // Aliases for set<CC>
2619 defm : IntegerCondCodeMnemonicAlias<"set", "">;
2620 // Aliases for j<CC>
2621 defm : IntegerCondCodeMnemonicAlias<"j", "">;
2622 // Aliases for cmov<CC>{w,l,q}
2623 defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">;
2624 defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">;
2625 defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">;
2626 // No size suffix for intel-style asm.
2627 defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">;
2630 //===----------------------------------------------------------------------===//
2631 // Assembler Instruction Aliases
2632 //===----------------------------------------------------------------------===//
2634 // aad/aam default to base 10 if no operand is specified.
2635 def : InstAlias<"aad", (AAD8i8 10)>;
2636 def : InstAlias<"aam", (AAM8i8 10)>;
2638 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
2639 // Likewise for btc/btr/bts.
2640 def : InstAlias<"bt {$imm, $mem|$mem, $imm}",
2641 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2642 def : InstAlias<"btc {$imm, $mem|$mem, $imm}",
2643 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2644 def : InstAlias<"btr {$imm, $mem|$mem, $imm}",
2645 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2646 def : InstAlias<"bts {$imm, $mem|$mem, $imm}",
2647 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2650 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>;
2651 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>;
2652 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>;
2653 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;
2655 // lods aliases. Accept the destination being omitted because it's implicit
2656 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2657 // in the destination.
2658 def : InstAlias<"lodsb $src", (LODSB srcidx8:$src), 0>;
2659 def : InstAlias<"lodsw $src", (LODSW srcidx16:$src), 0>;
2660 def : InstAlias<"lods{l|d} $src", (LODSL srcidx32:$src), 0>;
2661 def : InstAlias<"lodsq $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2662 def : InstAlias<"lods {$src, %al|al, $src}", (LODSB srcidx8:$src), 0>;
2663 def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>;
2664 def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>;
2665 def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2667 // stos aliases. Accept the source being omitted because it's implicit in
2668 // the mnemonic, or the mnemonic suffix being omitted because it's implicit
2670 def : InstAlias<"stosb $dst", (STOSB dstidx8:$dst), 0>;
2671 def : InstAlias<"stosw $dst", (STOSW dstidx16:$dst), 0>;
2672 def : InstAlias<"stos{l|d} $dst", (STOSL dstidx32:$dst), 0>;
2673 def : InstAlias<"stosq $dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2674 def : InstAlias<"stos {%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>;
2675 def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>;
2676 def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>;
2677 def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2679 // scas aliases. Accept the destination being omitted because it's implicit
2680 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2681 // in the destination.
2682 def : InstAlias<"scasb $dst", (SCASB dstidx8:$dst), 0>;
2683 def : InstAlias<"scasw $dst", (SCASW dstidx16:$dst), 0>;
2684 def : InstAlias<"scas{l|d} $dst", (SCASL dstidx32:$dst), 0>;
2685 def : InstAlias<"scasq $dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2686 def : InstAlias<"scas {$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>;
2687 def : InstAlias<"scas {$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>;
2688 def : InstAlias<"scas {$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>;
2689 def : InstAlias<"scas {$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2691 // div and idiv aliases for explicit A register.
2692 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
2693 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
2694 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>;
2695 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>;
2696 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>;
2697 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>;
2698 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>;
2699 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>;
2700 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>;
2701 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>;
2702 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>;
2703 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>;
2704 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>;
2705 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>;
2706 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;
2707 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;
2711 // Various unary fpstack operations default to operating on on ST1.
2712 // For example, "fxch" -> "fxch %st(1)"
2713 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
2714 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
2715 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
2716 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
2717 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
2718 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
2719 def : InstAlias<"fxch", (XCH_F ST1), 0>;
2720 def : InstAlias<"fcom", (COM_FST0r ST1), 0>;
2721 def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>;
2722 def : InstAlias<"fcomi", (COM_FIr ST1), 0>;
2723 def : InstAlias<"fcompi", (COM_FIPr ST1), 0>;
2724 def : InstAlias<"fucom", (UCOM_Fr ST1), 0>;
2725 def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>;
2726 def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>;
2727 def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>;
2729 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
2730 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
2731 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
2733 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
2734 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"),
2735 (Inst RST:$op), EmitAlias>;
2736 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"),
2737 (Inst ST0), EmitAlias>;
2740 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
2741 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
2742 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
2743 defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>;
2744 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
2745 defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>;
2746 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
2747 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
2748 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
2749 defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>;
2750 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
2751 defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>;
2752 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
2753 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
2754 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
2755 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
2758 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
2759 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
2760 // solely because gas supports it.
2761 def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>;
2762 def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>;
2763 def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>;
2764 def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>;
2765 def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>;
2766 def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>;
2768 // We accept "fnstsw %eax" even though it only writes %ax.
2769 def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>;
2770 def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>;
2771 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
2773 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
2774 // this is compatible with what GAS does.
2775 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2776 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2777 def : InstAlias<"lcall {*}$dst", (FARCALL32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2778 def : InstAlias<"ljmp {*}$dst", (FARJMP32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2779 def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2780 def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2781 def : InstAlias<"lcall {*}$dst", (FARCALL16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2782 def : InstAlias<"ljmp {*}$dst", (FARJMP16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2784 def : InstAlias<"call {*}$dst", (CALL64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
2785 def : InstAlias<"jmp {*}$dst", (JMP64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
2786 def : InstAlias<"call {*}$dst", (CALL32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
2787 def : InstAlias<"jmp {*}$dst", (JMP32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
2788 def : InstAlias<"call {*}$dst", (CALL16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2789 def : InstAlias<"jmp {*}$dst", (JMP16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2792 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
2793 def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>;
2794 def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>;
2795 def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>;
2796 def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>;
2797 def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>;
2798 def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>;
2800 // inb %dx -> inb %al, %dx
2801 def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;
2802 def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;
2803 def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>;
2804 def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>;
2805 def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>;
2806 def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>;
2809 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
2810 def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2811 def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2812 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2813 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2814 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
2815 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
2816 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2817 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2819 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
2820 // the move. All segment/mem forms are equivalent, this has the shortest
2822 def : InstAlias<"mov {$mem, $seg|$seg, $mem}", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem), 0>;
2823 def : InstAlias<"mov {$seg, $mem|$mem, $seg}", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg), 0>;
2825 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
2826 def : InstAlias<"movq {$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>;
2828 // Match 'movq GR64, MMX' as an alias for movd.
2829 def : InstAlias<"movq {$src, $dst|$dst, $src}",
2830 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
2831 def : InstAlias<"movq {$src, $dst|$dst, $src}",
2832 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
2835 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
2836 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
2837 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
2838 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
2839 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
2840 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
2841 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
2844 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
2845 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
2846 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
2847 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
2848 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
2849 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
2850 // Note: No GR32->GR64 movzx form.
2852 // outb %dx -> outb %al, %dx
2853 def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>;
2854 def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>;
2855 def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>;
2856 def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>;
2857 def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>;
2858 def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>;
2860 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
2861 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
2862 // errors, since its encoding is the most compact.
2863 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>;
2865 // shld/shrd op,op -> shld op, op, CL
2866 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;
2867 def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>;
2868 def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>;
2869 def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>;
2870 def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>;
2871 def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>;
2873 def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>;
2874 def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>;
2875 def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>;
2876 def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>;
2877 def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>;
2878 def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>;
2880 /* FIXME: This is disabled because the asm matcher is currently incapable of
2881 * matching a fixed immediate like $1.
2882 // "shl X, $1" is an alias for "shl X".
2883 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
2884 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2885 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
2886 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2887 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
2888 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2889 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
2890 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2891 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
2892 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2893 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
2894 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2895 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
2896 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2897 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
2898 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2899 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2902 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2903 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
2904 defm : ShiftRotateByOneAlias<"rol", "ROL">;
2905 defm : ShiftRotateByOneAlias<"ror", "ROR">;
2908 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
2909 def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}",
2910 (TEST8rm GR8 :$val, i8mem :$mem), 0>;
2911 def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}",
2912 (TEST16rm GR16:$val, i16mem:$mem), 0>;
2913 def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}",
2914 (TEST32rm GR32:$val, i32mem:$mem), 0>;
2915 def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}",
2916 (TEST64rm GR64:$val, i64mem:$mem), 0>;
2918 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
2919 def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}",
2920 (XCHG8rm GR8 :$val, i8mem :$mem), 0>;
2921 def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}",
2922 (XCHG16rm GR16:$val, i16mem:$mem), 0>;
2923 def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}",
2924 (XCHG32rm GR32:$val, i32mem:$mem), 0>;
2925 def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}",
2926 (XCHG64rm GR64:$val, i64mem:$mem), 0>;
2928 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
2929 def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>;
2930 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
2931 (XCHG32ar GR32:$src), 0>, Requires<[Not64BitMode]>;
2932 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
2933 (XCHG32ar64 GR32_NOAX:$src), 0>, Requires<[In64BitMode]>;
2934 def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>;