1 //===- X86InstrInfo.td - Main X86 Instruction Definition ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
32 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
34 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTX86BrCond : SDTypeProfile<0, 3,
39 [SDTCisVT<0, OtherVT>,
40 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
42 def SDTX86SetCC : SDTypeProfile<1, 2,
44 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86SetCC_C : SDTypeProfile<1, 2,
47 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
49 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
51 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
53 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
54 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
55 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
57 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
58 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
61 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
63 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
67 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
73 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
75 def SDTX86Void : SDTypeProfile<0, 0, []>;
77 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
79 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
81 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
83 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
85 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
87 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
88 def SDT_X86MEMBARRIERNoSSE : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
90 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
92 def X86MemBarrierNoSSE : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIERNoSSE,
94 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
96 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
98 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
102 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
103 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
104 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
105 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
107 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
108 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
110 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
111 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
113 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
114 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
116 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
117 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
118 SDNPMayLoad, SDNPMemOperand]>;
119 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
120 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
121 SDNPMayLoad, SDNPMemOperand]>;
122 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
123 [SDNPHasChain, SDNPMayStore,
124 SDNPMayLoad, SDNPMemOperand]>;
125 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
126 [SDNPHasChain, SDNPMayStore,
127 SDNPMayLoad, SDNPMemOperand]>;
128 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
129 [SDNPHasChain, SDNPMayStore,
130 SDNPMayLoad, SDNPMemOperand]>;
131 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
132 [SDNPHasChain, SDNPMayStore,
133 SDNPMayLoad, SDNPMemOperand]>;
134 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
135 [SDNPHasChain, SDNPMayStore,
136 SDNPMayLoad, SDNPMemOperand]>;
137 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
138 [SDNPHasChain, SDNPMayStore,
139 SDNPMayLoad, SDNPMemOperand]>;
140 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
141 [SDNPHasChain, SDNPMayStore,
142 SDNPMayLoad, SDNPMemOperand]>;
143 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
144 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
146 def X86vastart_save_xmm_regs :
147 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
148 SDT_X86VASTART_SAVE_XMM_REGS,
149 [SDNPHasChain, SDNPVariadic]>;
151 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
152 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
154 def X86callseq_start :
155 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
156 [SDNPHasChain, SDNPOutFlag]>;
158 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
159 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
161 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
162 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
165 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
166 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
167 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
168 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
171 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
172 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
174 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
175 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
177 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
178 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
180 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
183 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
184 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
186 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
188 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
189 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
191 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
194 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
195 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
196 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
198 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
200 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
203 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
205 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
206 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
208 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
211 //===----------------------------------------------------------------------===//
212 // X86 Operand Definitions.
215 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
216 // the index operand of an address, to conform to x86 encoding restrictions.
217 def ptr_rc_nosp : PointerLikeRegClass<1>;
219 // *mem - Operand definitions for the funky X86 addressing mode operands.
221 def X86MemAsmOperand : AsmOperandClass {
223 let SuperClasses = [];
225 def X86AbsMemAsmOperand : AsmOperandClass {
227 let SuperClasses = [X86MemAsmOperand];
229 class X86MemOperand<string printMethod> : Operand<iPTR> {
230 let PrintMethod = printMethod;
231 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
232 let ParserMatchClass = X86MemAsmOperand;
235 def opaque32mem : X86MemOperand<"printopaquemem">;
236 def opaque48mem : X86MemOperand<"printopaquemem">;
237 def opaque80mem : X86MemOperand<"printopaquemem">;
238 def opaque512mem : X86MemOperand<"printopaquemem">;
240 def i8mem : X86MemOperand<"printi8mem">;
241 def i16mem : X86MemOperand<"printi16mem">;
242 def i32mem : X86MemOperand<"printi32mem">;
243 def i64mem : X86MemOperand<"printi64mem">;
244 def i128mem : X86MemOperand<"printi128mem">;
245 def i256mem : X86MemOperand<"printi256mem">;
246 def f32mem : X86MemOperand<"printf32mem">;
247 def f64mem : X86MemOperand<"printf64mem">;
248 def f80mem : X86MemOperand<"printf80mem">;
249 def f128mem : X86MemOperand<"printf128mem">;
250 def f256mem : X86MemOperand<"printf256mem">;
252 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
253 // plain GR64, so that it doesn't potentially require a REX prefix.
254 def i8mem_NOREX : Operand<i64> {
255 let PrintMethod = "printi8mem";
256 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
257 let ParserMatchClass = X86MemAsmOperand;
260 // Special i32mem for addresses of load folding tail calls. These are not
261 // allowed to use callee-saved registers since they must be scheduled
262 // after callee-saved register are popped.
263 def i32mem_TC : Operand<i32> {
264 let PrintMethod = "printi32mem";
265 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
266 let ParserMatchClass = X86MemAsmOperand;
269 // Special i64mem for addresses of load folding tail calls. These are not
270 // allowed to use callee-saved registers since they must be scheduled
271 // after callee-saved register are popped.
272 def i64mem_TC : Operand<i64> {
273 let PrintMethod = "printi64mem";
274 let MIOperandInfo = (ops GR64_TC, i8imm, GR64_TC, i32imm, i8imm);
275 let ParserMatchClass = X86MemAsmOperand;
278 let ParserMatchClass = X86AbsMemAsmOperand,
279 PrintMethod = "print_pcrel_imm" in {
280 def i32imm_pcrel : Operand<i32>;
281 def i16imm_pcrel : Operand<i16>;
283 def offset8 : Operand<i64>;
284 def offset16 : Operand<i64>;
285 def offset32 : Operand<i64>;
286 def offset64 : Operand<i64>;
288 // Branch targets have OtherVT type and print as pc-relative values.
289 def brtarget : Operand<OtherVT>;
290 def brtarget8 : Operand<OtherVT>;
294 def SSECC : Operand<i8> {
295 let PrintMethod = "printSSECC";
298 class ImmSExtAsmOperandClass : AsmOperandClass {
299 let SuperClasses = [ImmAsmOperand];
300 let RenderMethod = "addImmOperands";
303 // Sign-extended immediate classes. We don't need to define the full lattice
304 // here because there is no instruction with an ambiguity between ImmSExti64i32
307 // The strange ranges come from the fact that the assembler always works with
308 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
309 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
312 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
313 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
314 let Name = "ImmSExti64i32";
317 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
318 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
319 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
320 let Name = "ImmSExti16i8";
321 let SuperClasses = [ImmSExti64i32AsmOperand];
324 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
325 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
326 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
327 let Name = "ImmSExti32i8";
331 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
332 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
333 let Name = "ImmSExti64i8";
334 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
335 ImmSExti64i32AsmOperand];
338 // A couple of more descriptive operand definitions.
339 // 16-bits but only 8 bits are significant.
340 def i16i8imm : Operand<i16> {
341 let ParserMatchClass = ImmSExti16i8AsmOperand;
343 // 32-bits but only 8 bits are significant.
344 def i32i8imm : Operand<i32> {
345 let ParserMatchClass = ImmSExti32i8AsmOperand;
348 // 64-bits but only 32 bits are significant.
349 def i64i32imm : Operand<i64> {
350 let ParserMatchClass = ImmSExti64i32AsmOperand;
353 // 64-bits but only 32 bits are significant, and those bits are treated as being
355 def i64i32imm_pcrel : Operand<i64> {
356 let PrintMethod = "print_pcrel_imm";
357 let ParserMatchClass = X86AbsMemAsmOperand;
360 // 64-bits but only 8 bits are significant.
361 def i64i8imm : Operand<i64> {
362 let ParserMatchClass = ImmSExti64i8AsmOperand;
365 def lea64_32mem : Operand<i32> {
366 let PrintMethod = "printi32mem";
367 let AsmOperandLowerMethod = "lower_lea64_32mem";
368 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm);
369 let ParserMatchClass = X86MemAsmOperand;
373 //===----------------------------------------------------------------------===//
374 // X86 Complex Pattern Definitions.
377 // Define X86 specific addressing mode.
378 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
379 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
380 [add, sub, mul, X86mul_imm, shl, or, frameindex],
382 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
383 [tglobaltlsaddr], []>;
385 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
386 [add, sub, mul, X86mul_imm, shl, or, frameindex,
389 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
390 [tglobaltlsaddr], []>;
392 //===----------------------------------------------------------------------===//
393 // X86 Instruction Predicate Definitions.
394 def HasCMov : Predicate<"Subtarget->hasCMov()">;
395 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
396 def HasMMX : Predicate<"Subtarget->hasMMX() && !Subtarget->hasAVX()">;
397 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
398 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
399 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
400 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
401 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
402 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
403 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
404 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
405 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
406 def HasAVX : Predicate<"Subtarget->hasAVX()">;
407 def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">;
408 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
409 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
410 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
411 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
412 def In32BitMode : Predicate<"!Subtarget->is64Bit()">, AssemblerPredicate;
413 def In64BitMode : Predicate<"Subtarget->is64Bit()">, AssemblerPredicate;
414 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
415 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
416 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
417 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
418 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
419 "TM.getCodeModel() != CodeModel::Kernel">;
420 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
421 "TM.getCodeModel() == CodeModel::Kernel">;
422 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
423 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
424 def OptForSize : Predicate<"OptForSize">;
425 def OptForSpeed : Predicate<"!OptForSize">;
426 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
427 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
428 def HasAES : Predicate<"Subtarget->hasAES()">;
430 //===----------------------------------------------------------------------===//
431 // X86 Instruction Format Definitions.
434 include "X86InstrFormats.td"
436 //===----------------------------------------------------------------------===//
437 // Pattern fragments...
440 // X86 specific condition code. These correspond to CondCode in
441 // X86InstrInfo.h. They must be kept in synch.
442 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
443 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
444 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
445 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
446 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
447 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
448 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
449 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
450 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
451 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
452 def X86_COND_NO : PatLeaf<(i8 10)>;
453 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
454 def X86_COND_NS : PatLeaf<(i8 12)>;
455 def X86_COND_O : PatLeaf<(i8 13)>;
456 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
457 def X86_COND_S : PatLeaf<(i8 15)>;
459 def immSext8 : PatLeaf<(imm), [{ return immSext8(N); }]>;
461 def i16immSExt8 : PatLeaf<(i16 immSext8)>;
462 def i32immSExt8 : PatLeaf<(i32 immSext8)>;
463 def i64immSExt8 : PatLeaf<(i64 immSext8)>;
464 def i64immSExt32 : PatLeaf<(i64 imm), [{ return i64immSExt32(N); }]>;
465 def i64immZExt32 : PatLeaf<(i64 imm), [{
466 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
467 // unsignedsign extended field.
468 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
471 def i64immZExt32SExt8 : PatLeaf<(i64 imm), [{
472 uint64_t v = N->getZExtValue();
473 return v == (uint32_t)v && (int32_t)v == (int8_t)v;
476 // Helper fragments for loads.
477 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
478 // known to be 32-bit aligned or better. Ditto for i8 to i16.
479 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
480 LoadSDNode *LD = cast<LoadSDNode>(N);
481 ISD::LoadExtType ExtType = LD->getExtensionType();
482 if (ExtType == ISD::NON_EXTLOAD)
484 if (ExtType == ISD::EXTLOAD)
485 return LD->getAlignment() >= 2 && !LD->isVolatile();
489 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
490 LoadSDNode *LD = cast<LoadSDNode>(N);
491 ISD::LoadExtType ExtType = LD->getExtensionType();
492 if (ExtType == ISD::EXTLOAD)
493 return LD->getAlignment() >= 2 && !LD->isVolatile();
497 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
498 LoadSDNode *LD = cast<LoadSDNode>(N);
499 ISD::LoadExtType ExtType = LD->getExtensionType();
500 if (ExtType == ISD::NON_EXTLOAD)
502 if (ExtType == ISD::EXTLOAD)
503 return LD->getAlignment() >= 4 && !LD->isVolatile();
507 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
508 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
509 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
510 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
511 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
513 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
514 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
515 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
516 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
517 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
518 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
520 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
521 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
522 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
523 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
524 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
525 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
526 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
527 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
528 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
529 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
531 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
532 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
533 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
534 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
535 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
536 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
537 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
538 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
539 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
540 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
543 // An 'and' node with a single use.
544 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
545 return N->hasOneUse();
547 // An 'srl' node with a single use.
548 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
549 return N->hasOneUse();
551 // An 'trunc' node with a single use.
552 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
553 return N->hasOneUse();
556 //===----------------------------------------------------------------------===//
561 let neverHasSideEffects = 1 in {
562 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
563 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
564 "nop{w}\t$zero", []>, TB, OpSize;
565 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
566 "nop{l}\t$zero", []>, TB;
570 // Constructing a stack frame.
571 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
572 "enter\t$len, $lvl", []>;
574 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
575 def LEAVE : I<0xC9, RawFrm,
576 (outs), (ins), "leave", []>, Requires<[In32BitMode]>;
578 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
579 def LEAVE64 : I<0xC9, RawFrm,
580 (outs), (ins), "leave", []>, Requires<[In64BitMode]>;
582 //===----------------------------------------------------------------------===//
583 // Miscellaneous Instructions.
586 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
588 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
590 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
591 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
593 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
595 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
596 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
598 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
599 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
600 Requires<[In32BitMode]>;
603 let mayStore = 1 in {
604 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
606 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
607 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
609 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
611 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
612 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
614 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
615 "push{l}\t$imm", []>;
616 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
617 "push{w}\t$imm", []>, OpSize;
618 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
619 "push{l}\t$imm", []>;
621 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
622 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
623 Requires<[In32BitMode]>;
628 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
630 def POP64r : I<0x58, AddRegFrm,
631 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
632 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
633 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
635 let mayStore = 1 in {
636 def PUSH64r : I<0x50, AddRegFrm,
637 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
638 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
639 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
643 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
644 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
645 "push{q}\t$imm", []>;
646 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
647 "push{q}\t$imm", []>;
648 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
649 "push{q}\t$imm", []>;
652 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
653 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>,
654 Requires<[In64BitMode]>;
655 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
656 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>,
657 Requires<[In64BitMode]>;
661 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
662 mayLoad=1, neverHasSideEffects=1 in {
663 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>,
664 Requires<[In32BitMode]>;
666 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
667 mayStore=1, neverHasSideEffects=1 in {
668 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>,
669 Requires<[In32BitMode]>;
672 let Constraints = "$src = $dst" in { // GR32 = bswap GR32
673 def BSWAP32r : I<0xC8, AddRegFrm,
674 (outs GR32:$dst), (ins GR32:$src),
676 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
678 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
680 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
681 } // Constraints = "$src = $dst"
683 // Bit scan instructions.
684 let Defs = [EFLAGS] in {
685 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
686 "bsf{w}\t{$src, $dst|$dst, $src}",
687 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
688 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
689 "bsf{w}\t{$src, $dst|$dst, $src}",
690 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
692 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
693 "bsf{l}\t{$src, $dst|$dst, $src}",
694 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
695 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
696 "bsf{l}\t{$src, $dst|$dst, $src}",
697 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
698 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
699 "bsf{q}\t{$src, $dst|$dst, $src}",
700 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, TB;
701 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
702 "bsf{q}\t{$src, $dst|$dst, $src}",
703 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, TB;
705 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
706 "bsr{w}\t{$src, $dst|$dst, $src}",
707 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
708 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
709 "bsr{w}\t{$src, $dst|$dst, $src}",
710 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
712 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
713 "bsr{l}\t{$src, $dst|$dst, $src}",
714 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
715 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
716 "bsr{l}\t{$src, $dst|$dst, $src}",
717 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
718 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
719 "bsr{q}\t{$src, $dst|$dst, $src}",
720 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, TB;
721 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
722 "bsr{q}\t{$src, $dst|$dst, $src}",
723 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, TB;
727 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
728 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
729 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
730 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
731 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
732 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", []>;
735 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
736 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
737 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
738 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
739 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
740 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
741 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
742 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
743 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", []>;
745 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
746 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
747 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
748 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", []>;
750 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
751 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
752 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
753 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", []>;
756 //===----------------------------------------------------------------------===//
757 // Move Instructions.
760 let neverHasSideEffects = 1 in {
761 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
762 "mov{b}\t{$src, $dst|$dst, $src}", []>;
763 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
764 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
765 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
766 "mov{l}\t{$src, $dst|$dst, $src}", []>;
767 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
768 "mov{q}\t{$src, $dst|$dst, $src}", []>;
770 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
771 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
772 "mov{b}\t{$src, $dst|$dst, $src}",
773 [(set GR8:$dst, imm:$src)]>;
774 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
775 "mov{w}\t{$src, $dst|$dst, $src}",
776 [(set GR16:$dst, imm:$src)]>, OpSize;
777 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
778 "mov{l}\t{$src, $dst|$dst, $src}",
779 [(set GR32:$dst, imm:$src)]>;
780 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
781 "movabs{q}\t{$src, $dst|$dst, $src}",
782 [(set GR64:$dst, imm:$src)]>;
783 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
784 "mov{q}\t{$src, $dst|$dst, $src}",
785 [(set GR64:$dst, i64immSExt32:$src)]>;
788 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
789 "mov{b}\t{$src, $dst|$dst, $src}",
790 [(store (i8 imm:$src), addr:$dst)]>;
791 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
792 "mov{w}\t{$src, $dst|$dst, $src}",
793 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
794 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
795 "mov{l}\t{$src, $dst|$dst, $src}",
796 [(store (i32 imm:$src), addr:$dst)]>;
797 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
798 "mov{q}\t{$src, $dst|$dst, $src}",
799 [(store i64immSExt32:$src, addr:$dst)]>;
801 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
802 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
803 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
804 "mov{b}\t{$src, %al|%al, $src}", []>,
805 Requires<[In32BitMode]>;
806 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
807 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize,
808 Requires<[In32BitMode]>;
809 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
810 "mov{l}\t{$src, %eax|%eax, $src}", []>,
811 Requires<[In32BitMode]>;
812 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
813 "mov{b}\t{%al, $dst|$dst, %al}", []>,
814 Requires<[In32BitMode]>;
815 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
816 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize,
817 Requires<[In32BitMode]>;
818 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
819 "mov{l}\t{%eax, $dst|$dst, %eax}", []>,
820 Requires<[In32BitMode]>;
822 // FIXME: These definitions are utterly broken
823 // Just leave them commented out for now because they're useless outside
824 // of the large code model, and most compilers won't generate the instructions
827 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
828 "mov{q}\t{$src, %rax|%rax, $src}", []>;
829 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
830 "mov{q}\t{$src, %rax|%rax, $src}", []>;
831 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
832 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
833 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
834 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
838 let isCodeGenOnly = 1 in {
839 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
840 "mov{b}\t{$src, $dst|$dst, $src}", []>;
841 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
842 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
843 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
844 "mov{l}\t{$src, $dst|$dst, $src}", []>;
845 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
846 "mov{q}\t{$src, $dst|$dst, $src}", []>;
849 let canFoldAsLoad = 1, isReMaterializable = 1 in {
850 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
851 "mov{b}\t{$src, $dst|$dst, $src}",
852 [(set GR8:$dst, (loadi8 addr:$src))]>;
853 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
854 "mov{w}\t{$src, $dst|$dst, $src}",
855 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
856 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
857 "mov{l}\t{$src, $dst|$dst, $src}",
858 [(set GR32:$dst, (loadi32 addr:$src))]>;
859 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
860 "mov{q}\t{$src, $dst|$dst, $src}",
861 [(set GR64:$dst, (load addr:$src))]>;
864 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
865 "mov{b}\t{$src, $dst|$dst, $src}",
866 [(store GR8:$src, addr:$dst)]>;
867 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
868 "mov{w}\t{$src, $dst|$dst, $src}",
869 [(store GR16:$src, addr:$dst)]>, OpSize;
870 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
871 "mov{l}\t{$src, $dst|$dst, $src}",
872 [(store GR32:$src, addr:$dst)]>;
873 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
874 "mov{q}\t{$src, $dst|$dst, $src}",
875 [(store GR64:$src, addr:$dst)]>;
877 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
878 // that they can be used for copying and storing h registers, which can't be
879 // encoded when a REX prefix is present.
880 let isCodeGenOnly = 1 in {
881 let neverHasSideEffects = 1 in
882 def MOV8rr_NOREX : I<0x88, MRMDestReg,
883 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
884 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
886 def MOV8mr_NOREX : I<0x88, MRMDestMem,
887 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
888 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
890 canFoldAsLoad = 1, isReMaterializable = 1 in
891 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
892 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
893 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
897 // Condition code ops, incl. set if equal/not equal/...
898 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
899 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
900 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
901 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
904 //===----------------------------------------------------------------------===//
905 // Bit tests instructions: BT, BTS, BTR, BTC.
907 let Defs = [EFLAGS] in {
908 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
909 "bt{w}\t{$src2, $src1|$src1, $src2}",
910 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
911 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
912 "bt{l}\t{$src2, $src1|$src1, $src2}",
913 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
914 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
915 "bt{q}\t{$src2, $src1|$src1, $src2}",
916 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB;
918 // Unlike with the register+register form, the memory+register form of the
919 // bt instruction does not ignore the high bits of the index. From ISel's
920 // perspective, this is pretty bizarre. Make these instructions disassembly
923 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
924 "bt{w}\t{$src2, $src1|$src1, $src2}",
925 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
926 // (implicit EFLAGS)]
928 >, OpSize, TB, Requires<[FastBTMem]>;
929 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
930 "bt{l}\t{$src2, $src1|$src1, $src2}",
931 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
932 // (implicit EFLAGS)]
934 >, TB, Requires<[FastBTMem]>;
935 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
936 "bt{q}\t{$src2, $src1|$src1, $src2}",
937 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
938 // (implicit EFLAGS)]
942 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
943 "bt{w}\t{$src2, $src1|$src1, $src2}",
944 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
946 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
947 "bt{l}\t{$src2, $src1|$src1, $src2}",
948 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
949 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
950 "bt{q}\t{$src2, $src1|$src1, $src2}",
951 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))]>, TB;
953 // Note that these instructions don't need FastBTMem because that
954 // only applies when the other operand is in a register. When it's
955 // an immediate, bt is still fast.
956 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
957 "bt{w}\t{$src2, $src1|$src1, $src2}",
958 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
960 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
961 "bt{l}\t{$src2, $src1|$src1, $src2}",
962 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
964 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
965 "bt{q}\t{$src2, $src1|$src1, $src2}",
966 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
967 i64immSExt8:$src2))]>, TB;
970 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
971 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
972 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
973 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
974 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
975 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
976 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
977 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
978 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
979 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
980 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
981 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
982 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
983 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
984 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
985 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
986 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
987 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
988 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
989 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
990 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
991 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
992 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
993 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
995 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
996 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
997 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
998 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
999 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1000 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1001 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1002 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1003 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1004 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1005 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1006 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1007 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1008 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1009 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1010 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1011 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1012 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1013 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1014 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1015 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1016 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1017 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1018 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1020 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1021 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1022 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1023 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1024 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1025 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1026 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1027 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1028 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1029 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1030 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1031 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1032 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1033 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1034 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1035 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1036 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1037 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1038 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1039 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1040 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1041 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1042 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1043 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1044 } // Defs = [EFLAGS]
1047 //===----------------------------------------------------------------------===//
1052 // Atomic swap. These are just normal xchg instructions. But since a memory
1053 // operand is referenced, the atomicity is ensured.
1054 let Constraints = "$val = $dst" in {
1055 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
1056 "xchg{b}\t{$val, $ptr|$ptr, $val}",
1057 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
1058 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),(ins GR16:$val, i16mem:$ptr),
1059 "xchg{w}\t{$val, $ptr|$ptr, $val}",
1060 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
1062 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),(ins GR32:$val, i32mem:$ptr),
1063 "xchg{l}\t{$val, $ptr|$ptr, $val}",
1064 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
1065 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),(ins GR64:$val,i64mem:$ptr),
1066 "xchg{q}\t{$val, $ptr|$ptr, $val}",
1067 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1069 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1070 "xchg{b}\t{$val, $src|$src, $val}", []>;
1071 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1072 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
1073 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1074 "xchg{l}\t{$val, $src|$src, $val}", []>;
1075 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1076 "xchg{q}\t{$val, $src|$src, $val}", []>;
1079 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1080 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1081 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1082 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
1083 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1084 "xchg{q}\t{$src, %rax|%rax, $src}", []>;
1088 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1089 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
1090 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1091 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1092 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1093 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
1094 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1095 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1097 let mayLoad = 1, mayStore = 1 in {
1098 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1099 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
1100 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1101 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1102 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1103 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
1104 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1105 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1109 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1110 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
1111 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1112 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1113 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1114 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
1115 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1116 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1118 let mayLoad = 1, mayStore = 1 in {
1119 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1120 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
1121 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1122 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1123 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1124 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
1125 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1126 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1129 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1130 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1131 "cmpxchg8b\t$dst", []>, TB;
1133 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1134 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1135 "cmpxchg16b\t$dst", []>, TB;
1139 // Lock instruction prefix
1140 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1142 // Rex64 instruction prefix
1143 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>;
1145 // Data16 instruction prefix
1146 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1148 // Repeat string operation instruction prefixes
1149 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1150 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1151 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1152 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1153 // Repeat while not equal (used with CMPS and SCAS)
1154 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1158 // String manipulation instructions
1159 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
1160 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
1161 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
1162 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
1164 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
1165 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
1166 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
1169 // Flag instructions
1170 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
1171 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
1172 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
1173 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
1174 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
1175 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
1176 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
1178 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
1180 // Table lookup instructions
1181 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
1183 // ASCII Adjust After Addition
1184 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1185 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", []>, Requires<[In32BitMode]>;
1187 // ASCII Adjust AX Before Division
1188 // sets AL, AH and EFLAGS and uses AL and AH
1189 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1190 "aad\t$src", []>, Requires<[In32BitMode]>;
1192 // ASCII Adjust AX After Multiply
1193 // sets AL, AH and EFLAGS and uses AL
1194 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1195 "aam\t$src", []>, Requires<[In32BitMode]>;
1197 // ASCII Adjust AL After Subtraction - sets
1198 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1199 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>, Requires<[In32BitMode]>;
1201 // Decimal Adjust AL after Addition
1202 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1203 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", []>, Requires<[In32BitMode]>;
1205 // Decimal Adjust AL after Subtraction
1206 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1207 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>, Requires<[In32BitMode]>;
1209 // Check Array Index Against Bounds
1210 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1211 "bound\t{$src, $dst|$dst, $src}", []>, OpSize,
1212 Requires<[In32BitMode]>;
1213 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1214 "bound\t{$src, $dst|$dst, $src}", []>,
1215 Requires<[In32BitMode]>;
1217 // Adjust RPL Field of Segment Selector
1218 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$src), (ins GR16:$dst),
1219 "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
1220 def ARPL16mr : I<0x63, MRMSrcMem, (outs GR16:$src), (ins i16mem:$dst),
1221 "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
1223 //===----------------------------------------------------------------------===//
1225 //===----------------------------------------------------------------------===//
1227 include "X86InstrArithmetic.td"
1228 include "X86InstrCMovSetCC.td"
1229 include "X86InstrExtension.td"
1230 include "X86InstrControl.td"
1231 include "X86InstrShiftRotate.td"
1233 // X87 Floating Point Stack.
1234 include "X86InstrFPStack.td"
1236 // SIMD support (SSE, MMX and AVX)
1237 include "X86InstrFragmentsSIMD.td"
1239 // FMA - Fused Multiply-Add support (requires FMA)
1240 include "X86InstrFMA.td"
1242 // SSE, MMX and 3DNow! vector support.
1243 include "X86InstrSSE.td"
1244 include "X86InstrMMX.td"
1245 include "X86Instr3DNow.td"
1247 include "X86InstrVMX.td"
1249 // System instructions.
1250 include "X86InstrSystem.td"
1252 // Compiler Pseudo Instructions and Pat Patterns
1253 include "X86InstrCompiler.td"
1255 //===----------------------------------------------------------------------===//
1256 // Assembler Mnemonic Aliases
1257 //===----------------------------------------------------------------------===//
1259 def : MnemonicAlias<"call", "calll">, Requires<[In32BitMode]>;
1260 def : MnemonicAlias<"call", "callq">, Requires<[In64BitMode]>;
1262 def : MnemonicAlias<"cbw", "cbtw">;
1263 def : MnemonicAlias<"cwd", "cwtd">;
1264 def : MnemonicAlias<"cdq", "cltd">;
1265 def : MnemonicAlias<"cwde", "cwtl">;
1266 def : MnemonicAlias<"cdqe", "cltq">;
1268 // lret maps to lretl, it is not ambiguous with lretq.
1269 def : MnemonicAlias<"lret", "lretl">;
1271 def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
1272 def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
1273 def : MnemonicAlias<"popf", "popfl">, Requires<[In32BitMode]>;
1274 def : MnemonicAlias<"popf", "popfq">, Requires<[In64BitMode]>;
1275 def : MnemonicAlias<"popfd", "popfl">;
1277 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
1278 // all modes. However: "push (addr)" and "push $42" should default to
1279 // pushl/pushq depending on the current mode. Similar for "pop %bx"
1280 def : MnemonicAlias<"push", "pushl">, Requires<[In32BitMode]>;
1281 def : MnemonicAlias<"push", "pushq">, Requires<[In64BitMode]>;
1282 def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
1283 def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1284 def : MnemonicAlias<"pushfd", "pushfl">;
1286 def : MnemonicAlias<"repe", "rep">;
1287 def : MnemonicAlias<"repz", "rep">;
1288 def : MnemonicAlias<"repnz", "repne">;
1290 def : MnemonicAlias<"retl", "ret">, Requires<[In32BitMode]>;
1291 def : MnemonicAlias<"retq", "ret">, Requires<[In64BitMode]>;
1293 def : MnemonicAlias<"salb", "shlb">;
1294 def : MnemonicAlias<"salw", "shlw">;
1295 def : MnemonicAlias<"sall", "shll">;
1296 def : MnemonicAlias<"salq", "shlq">;
1298 def : MnemonicAlias<"smovb", "movsb">;
1299 def : MnemonicAlias<"smovw", "movsw">;
1300 def : MnemonicAlias<"smovl", "movsl">;
1301 def : MnemonicAlias<"smovq", "movsq">;
1303 def : MnemonicAlias<"ud2a", "ud2">;
1304 def : MnemonicAlias<"verrw", "verr">;
1306 // System instruction aliases.
1307 def : MnemonicAlias<"iret", "iretl">;
1308 def : MnemonicAlias<"sysret", "sysretl">;
1310 def : MnemonicAlias<"lgdtl", "lgdt">, Requires<[In32BitMode]>;
1311 def : MnemonicAlias<"lgdtq", "lgdt">, Requires<[In64BitMode]>;
1312 def : MnemonicAlias<"lidtl", "lidt">, Requires<[In32BitMode]>;
1313 def : MnemonicAlias<"lidtq", "lidt">, Requires<[In64BitMode]>;
1314 def : MnemonicAlias<"sgdtl", "sgdt">, Requires<[In32BitMode]>;
1315 def : MnemonicAlias<"sgdtq", "sgdt">, Requires<[In64BitMode]>;
1316 def : MnemonicAlias<"sidtl", "sidt">, Requires<[In32BitMode]>;
1317 def : MnemonicAlias<"sidtq", "sidt">, Requires<[In64BitMode]>;
1320 // Floating point stack aliases.
1321 def : MnemonicAlias<"fcmovz", "fcmove">;
1322 def : MnemonicAlias<"fcmova", "fcmovnbe">;
1323 def : MnemonicAlias<"fcmovnae", "fcmovb">;
1324 def : MnemonicAlias<"fcmovna", "fcmovbe">;
1325 def : MnemonicAlias<"fcmovae", "fcmovnb">;
1326 def : MnemonicAlias<"fcomip", "fcompi">;
1327 def : MnemonicAlias<"fildq", "fildll">;
1328 def : MnemonicAlias<"fldcww", "fldcw">;
1329 def : MnemonicAlias<"fnstcww", "fnstcw">;
1330 def : MnemonicAlias<"fnstsww", "fnstsw">;
1331 def : MnemonicAlias<"fucomip", "fucompi">;
1332 def : MnemonicAlias<"fwait", "wait">;
1335 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond>
1336 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
1337 !strconcat(Prefix, NewCond, Suffix)>;
1339 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
1340 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
1341 /// example "setz" -> "sete".
1342 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix> {
1343 def C : CondCodeAlias<Prefix, Suffix, "c", "b">; // setc -> setb
1344 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e">; // setz -> sete
1345 def NA : CondCodeAlias<Prefix, Suffix, "na", "be">; // setna -> setbe
1346 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae">; // setnb -> setae
1347 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae">; // setnc -> setae
1348 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le">; // setng -> setle
1349 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge">; // setnl -> setge
1350 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne">; // setnz -> setne
1351 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p">; // setpe -> setp
1352 def PO : CondCodeAlias<Prefix, Suffix, "po", "np">; // setpo -> setnp
1354 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b">; // setnae -> setb
1355 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a">; // setnbe -> seta
1356 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l">; // setnge -> setl
1357 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g">; // setnle -> setg
1360 // Aliases for set<CC>
1361 defm : IntegerCondCodeMnemonicAlias<"set", "">;
1362 // Aliases for j<CC>
1363 defm : IntegerCondCodeMnemonicAlias<"j", "">;
1364 // Aliases for cmov<CC>{w,l,q}
1365 defm : IntegerCondCodeMnemonicAlias<"cmov", "w">;
1366 defm : IntegerCondCodeMnemonicAlias<"cmov", "l">;
1367 defm : IntegerCondCodeMnemonicAlias<"cmov", "q">;
1370 //===----------------------------------------------------------------------===//
1371 // Assembler Instruction Aliases
1372 //===----------------------------------------------------------------------===//
1374 // aad/aam default to base 10 if no operand is specified.
1375 def : InstAlias<"aad", (AAD8i8 10)>;
1376 def : InstAlias<"aam", (AAM8i8 10)>;
1379 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>;
1380 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>;
1381 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
1382 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
1384 // div and idiv aliases for explicit A register.
1385 def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>;
1386 def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>;
1387 def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>;
1388 def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>;
1389 def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>;
1390 def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>;
1391 def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>;
1392 def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>;
1393 def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>;
1394 def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>;
1395 def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>;
1396 def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>;
1397 def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>;
1398 def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>;
1399 def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>;
1400 def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>;
1404 // Various unary fpstack operations default to operating on on ST1.
1405 // For example, "fxch" -> "fxch %st(1)"
1406 def : InstAlias<"faddp", (ADD_FPrST0 ST1)>;
1407 def : InstAlias<"fsubp", (SUBR_FPrST0 ST1)>;
1408 def : InstAlias<"fsubrp", (SUB_FPrST0 ST1)>;
1409 def : InstAlias<"fmulp", (MUL_FPrST0 ST1)>;
1410 def : InstAlias<"fdivp", (DIVR_FPrST0 ST1)>;
1411 def : InstAlias<"fdivrp", (DIV_FPrST0 ST1)>;
1412 def : InstAlias<"fxch", (XCH_F ST1)>;
1413 def : InstAlias<"fcomi", (COM_FIr ST1)>;
1414 def : InstAlias<"fcompi", (COM_FIPr ST1)>;
1415 def : InstAlias<"fucom", (UCOM_Fr ST1)>;
1416 def : InstAlias<"fucomp", (UCOM_FPr ST1)>;
1417 def : InstAlias<"fucomi", (UCOM_FIr ST1)>;
1418 def : InstAlias<"fucompi", (UCOM_FIPr ST1)>;
1420 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
1421 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
1422 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
1424 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst> {
1425 def : InstAlias<!strconcat(Mnemonic, " $op, %st(0)"), (Inst RST:$op)>;
1426 def : InstAlias<!strconcat(Mnemonic, " %st(0), %st(0)"), (Inst ST0)>;
1429 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
1430 defm : FpUnaryAlias<"faddp", ADD_FPrST0>;
1431 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
1432 defm : FpUnaryAlias<"fsubp", SUBR_FPrST0>;
1433 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
1434 defm : FpUnaryAlias<"fsubrp", SUB_FPrST0>;
1435 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
1436 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
1437 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
1438 defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>;
1439 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
1440 defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>;
1441 defm : FpUnaryAlias<"fcomi", COM_FIr>;
1442 defm : FpUnaryAlias<"fucomi", UCOM_FIr>;
1443 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
1444 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
1447 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
1448 // commute. We also allow fdivrp/fsubrp even though they don't commute, solely
1449 // because gas supports it.
1450 def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op)>;
1451 def : InstAlias<"fmulp %st(0), $op", (MUL_FPrST0 RST:$op)>;
1452 def : InstAlias<"fsubrp %st(0), $op", (SUB_FPrST0 RST:$op)>;
1453 def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>;
1455 // We accepts "fnstsw %eax" even though it only writes %ax.
1456 def : InstAlias<"fnstsw %eax", (FNSTSW8r)>;
1457 def : InstAlias<"fnstsw %al" , (FNSTSW8r)>;
1458 def : InstAlias<"fnstsw" , (FNSTSW8r)>;
1460 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
1461 // this is compatible with what GAS does.
1462 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1463 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1464 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>;
1465 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>;
1467 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
1468 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
1469 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
1470 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
1471 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
1472 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
1473 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
1475 // inb %dx -> inb %al, %dx
1476 def : InstAlias<"inb %dx", (IN8rr)>;
1477 def : InstAlias<"inw %dx", (IN16rr)>;
1478 def : InstAlias<"inl %dx", (IN32rr)>;
1479 def : InstAlias<"inb $port", (IN8ri i8imm:$port)>;
1480 def : InstAlias<"inw $port", (IN16ri i8imm:$port)>;
1481 def : InstAlias<"inl $port", (IN32ri i8imm:$port)>;
1484 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
1485 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1486 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1487 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
1488 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
1489 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1490 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1492 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
1493 // the move. All segment/mem forms are equivalent, this has the shortest
1495 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
1496 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
1498 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
1499 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
1501 // Match 'movq GR64, MMX' as an alias for movd.
1502 def : InstAlias<"movq $src, $dst", (MMX_MOVD64to64rr VR64:$dst, GR64:$src)>;
1503 def : InstAlias<"movq $src, $dst", (MMX_MOVD64from64rr GR64:$dst, VR64:$src)>;
1505 // movsd with no operands (as opposed to the SSE scalar move of a double) is an
1506 // alias for movsl. (as in rep; movsd)
1507 def : InstAlias<"movsd", (MOVSD)>;
1510 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src)>;
1511 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8W GR16:$dst, i8mem:$src)>;
1512 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src)>;
1513 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src)>;
1514 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src)>;
1515 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src)>;
1516 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src)>;
1519 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8W GR16:$dst, GR8:$src)>;
1520 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8W GR16:$dst, i8mem:$src)>;
1521 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src)>;
1522 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src)>;
1523 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src)>;
1524 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src)>;
1525 // Note: No GR32->GR64 movzx form.
1527 // outb %dx -> outb %al, %dx
1528 def : InstAlias<"outb %dx", (OUT8rr)>;
1529 def : InstAlias<"outw %dx", (OUT16rr)>;
1530 def : InstAlias<"outl %dx", (OUT32rr)>;
1531 def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>;
1532 def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>;
1533 def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>;
1535 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
1536 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
1537 // errors, since its encoding is the most compact.
1538 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
1540 // shld/shrd op,op -> shld op, op, 1
1541 def : InstAlias<"shldw $r1, $r2", (SHLD16rri8 GR16:$r1, GR16:$r2, 1)>;
1542 def : InstAlias<"shldl $r1, $r2", (SHLD32rri8 GR32:$r1, GR32:$r2, 1)>;
1543 def : InstAlias<"shldq $r1, $r2", (SHLD64rri8 GR64:$r1, GR64:$r2, 1)>;
1544 def : InstAlias<"shrdw $r1, $r2", (SHRD16rri8 GR16:$r1, GR16:$r2, 1)>;
1545 def : InstAlias<"shrdl $r1, $r2", (SHRD32rri8 GR32:$r1, GR32:$r2, 1)>;
1546 def : InstAlias<"shrdq $r1, $r2", (SHRD64rri8 GR64:$r1, GR64:$r2, 1)>;
1548 def : InstAlias<"shldw $mem, $reg", (SHLD16mri8 i16mem:$mem, GR16:$reg, 1)>;
1549 def : InstAlias<"shldl $mem, $reg", (SHLD32mri8 i32mem:$mem, GR32:$reg, 1)>;
1550 def : InstAlias<"shldq $mem, $reg", (SHLD64mri8 i64mem:$mem, GR64:$reg, 1)>;
1551 def : InstAlias<"shrdw $mem, $reg", (SHRD16mri8 i16mem:$mem, GR16:$reg, 1)>;
1552 def : InstAlias<"shrdl $mem, $reg", (SHRD32mri8 i32mem:$mem, GR32:$reg, 1)>;
1553 def : InstAlias<"shrdq $mem, $reg", (SHRD64mri8 i64mem:$mem, GR64:$reg, 1)>;
1555 /* FIXME: This is disabled because the asm matcher is currently incapable of
1556 * matching a fixed immediate like $1.
1557 // "shl X, $1" is an alias for "shl X".
1558 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
1559 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
1560 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
1561 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
1562 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
1563 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
1564 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
1565 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
1566 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
1567 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
1568 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
1569 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
1570 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
1571 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
1572 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
1573 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
1574 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
1577 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
1578 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
1579 defm : ShiftRotateByOneAlias<"rol", "ROL">;
1580 defm : ShiftRotateByOneAlias<"ror", "ROR">;
1583 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
1584 def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>;
1585 def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>;
1586 def : InstAlias<"testl $val, $mem", (TEST32rm GR32:$val, i32mem:$mem)>;
1587 def : InstAlias<"testq $val, $mem", (TEST64rm GR64:$val, i64mem:$mem)>;
1589 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
1590 def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>;
1591 def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>;
1592 def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>;
1593 def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>;