1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 def SDTX86BrCond : SDTypeProfile<0, 3,
31 [SDTCisVT<0, OtherVT>,
32 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
34 def SDTX86SetCC : SDTypeProfile<1, 2,
36 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
38 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
40 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
42 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
43 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
44 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
46 def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
47 def SDT_X86CallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
50 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
52 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
54 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
56 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
58 def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
60 def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
62 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
64 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
66 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
67 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
68 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
69 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
71 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
73 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
74 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
76 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
78 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
79 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
81 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
82 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
84 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
85 [SDNPHasChain, SDNPMayStore,
86 SDNPMayLoad, SDNPMemOperand]>;
87 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
88 [SDNPHasChain, SDNPMayStore,
89 SDNPMayLoad, SDNPMemOperand]>;
90 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
91 [SDNPHasChain, SDNPMayStore,
92 SDNPMayLoad, SDNPMemOperand]>;
93 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
94 [SDNPHasChain, SDNPMayStore,
95 SDNPMayLoad, SDNPMemOperand]>;
96 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
97 [SDNPHasChain, SDNPMayStore,
98 SDNPMayLoad, SDNPMemOperand]>;
99 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
100 [SDNPHasChain, SDNPMayStore,
101 SDNPMayLoad, SDNPMemOperand]>;
102 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
103 [SDNPHasChain, SDNPMayStore,
104 SDNPMayLoad, SDNPMemOperand]>;
105 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
106 [SDNPHasChain, SDNPOptInFlag]>;
108 def X86callseq_start :
109 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
110 [SDNPHasChain, SDNPOutFlag]>;
112 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
113 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
115 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
116 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
118 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
119 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
121 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
122 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
123 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
124 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
127 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
128 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
130 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
131 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
133 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
134 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
135 def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
137 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
140 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
141 [SDNPHasChain, SDNPOptInFlag]>;
143 //===----------------------------------------------------------------------===//
144 // X86 Operand Definitions.
147 // *mem - Operand definitions for the funky X86 addressing mode operands.
149 class X86MemOperand<string printMethod> : Operand<iPTR> {
150 let PrintMethod = printMethod;
151 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
154 def i8mem : X86MemOperand<"printi8mem">;
155 def i16mem : X86MemOperand<"printi16mem">;
156 def i32mem : X86MemOperand<"printi32mem">;
157 def i64mem : X86MemOperand<"printi64mem">;
158 def i128mem : X86MemOperand<"printi128mem">;
159 def f32mem : X86MemOperand<"printf32mem">;
160 def f64mem : X86MemOperand<"printf64mem">;
161 def f80mem : X86MemOperand<"printf80mem">;
162 def f128mem : X86MemOperand<"printf128mem">;
164 def lea32mem : Operand<i32> {
165 let PrintMethod = "printi32mem";
166 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
169 def SSECC : Operand<i8> {
170 let PrintMethod = "printSSECC";
173 def piclabel: Operand<i32> {
174 let PrintMethod = "printPICLabel";
177 // A couple of more descriptive operand definitions.
178 // 16-bits but only 8 bits are significant.
179 def i16i8imm : Operand<i16>;
180 // 32-bits but only 8 bits are significant.
181 def i32i8imm : Operand<i32>;
183 // Branch targets have OtherVT type.
184 def brtarget : Operand<OtherVT>;
186 //===----------------------------------------------------------------------===//
187 // X86 Complex Pattern Definitions.
190 // Define X86 specific addressing mode.
191 def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
192 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
193 [add, mul, shl, or, frameindex], []>;
195 //===----------------------------------------------------------------------===//
196 // X86 Instruction Predicate Definitions.
197 def HasMMX : Predicate<"Subtarget->hasMMX()">;
198 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
199 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
200 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
201 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
202 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
203 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
204 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
205 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
206 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
207 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
208 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
209 def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
210 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
211 def OptForSpeed : Predicate<"!OptForSize">;
213 //===----------------------------------------------------------------------===//
214 // X86 Instruction Format Definitions.
217 include "X86InstrFormats.td"
219 //===----------------------------------------------------------------------===//
220 // Pattern fragments...
223 // X86 specific condition code. These correspond to CondCode in
224 // X86InstrInfo.h. They must be kept in synch.
225 def X86_COND_A : PatLeaf<(i8 0)>;
226 def X86_COND_AE : PatLeaf<(i8 1)>;
227 def X86_COND_B : PatLeaf<(i8 2)>;
228 def X86_COND_BE : PatLeaf<(i8 3)>;
229 def X86_COND_E : PatLeaf<(i8 4)>;
230 def X86_COND_G : PatLeaf<(i8 5)>;
231 def X86_COND_GE : PatLeaf<(i8 6)>;
232 def X86_COND_L : PatLeaf<(i8 7)>;
233 def X86_COND_LE : PatLeaf<(i8 8)>;
234 def X86_COND_NE : PatLeaf<(i8 9)>;
235 def X86_COND_NO : PatLeaf<(i8 10)>;
236 def X86_COND_NP : PatLeaf<(i8 11)>;
237 def X86_COND_NS : PatLeaf<(i8 12)>;
238 def X86_COND_O : PatLeaf<(i8 13)>;
239 def X86_COND_P : PatLeaf<(i8 14)>;
240 def X86_COND_S : PatLeaf<(i8 15)>;
242 def i16immSExt8 : PatLeaf<(i16 imm), [{
243 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
244 // sign extended field.
245 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
248 def i32immSExt8 : PatLeaf<(i32 imm), [{
249 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
250 // sign extended field.
251 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
254 // Helper fragments for loads.
255 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
256 // known to be 32-bit aligned or better. Ditto for i8 to i16.
257 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
258 LoadSDNode *LD = cast<LoadSDNode>(N);
259 ISD::LoadExtType ExtType = LD->getExtensionType();
260 if (ExtType == ISD::NON_EXTLOAD)
262 if (ExtType == ISD::EXTLOAD)
263 return LD->getAlignment() >= 2 && !LD->isVolatile();
267 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
268 LoadSDNode *LD = cast<LoadSDNode>(N);
269 ISD::LoadExtType ExtType = LD->getExtensionType();
270 if (ExtType == ISD::EXTLOAD)
271 return LD->getAlignment() >= 2 && !LD->isVolatile();
275 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
276 LoadSDNode *LD = cast<LoadSDNode>(N);
277 ISD::LoadExtType ExtType = LD->getExtensionType();
278 if (ExtType == ISD::NON_EXTLOAD)
280 if (ExtType == ISD::EXTLOAD)
281 return LD->getAlignment() >= 4 && !LD->isVolatile();
285 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
286 LoadSDNode *LD = cast<LoadSDNode>(N);
287 if (LD->isVolatile())
289 ISD::LoadExtType ExtType = LD->getExtensionType();
290 if (ExtType == ISD::NON_EXTLOAD)
292 if (ExtType == ISD::EXTLOAD)
293 return LD->getAlignment() >= 4;
297 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
298 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
300 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
301 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
302 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
304 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
305 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
306 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
308 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
309 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
310 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
311 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
312 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
313 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
315 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
316 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
317 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
318 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
319 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
320 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
323 // An 'and' node with a single use.
324 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
325 return N->hasOneUse();
328 //===----------------------------------------------------------------------===//
329 // Instruction list...
332 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
333 // a stack adjustment and the codegen must know that they may modify the stack
334 // pointer before prolog-epilog rewriting occurs.
335 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
336 // sub / add which can clobber EFLAGS.
337 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
338 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
340 [(X86callseq_start timm:$amt)]>,
341 Requires<[In32BitMode]>;
342 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
344 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
345 Requires<[In32BitMode]>;
349 let neverHasSideEffects = 1 in
350 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
353 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
354 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
355 "call\t$label\n\tpop{l}\t$reg", []>;
357 //===----------------------------------------------------------------------===//
358 // Control Flow Instructions...
361 // Return instructions.
362 let isTerminator = 1, isReturn = 1, isBarrier = 1,
363 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
364 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
367 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
369 [(X86retflag imm:$amt)]>;
372 // All branches are RawFrm, Void, Branch, and Terminators
373 let isBranch = 1, isTerminator = 1 in
374 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
375 I<opcode, RawFrm, (outs), ins, asm, pattern>;
377 let isBranch = 1, isBarrier = 1 in
378 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
381 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
382 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
383 [(brind GR32:$dst)]>;
384 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
385 [(brind (loadi32 addr:$dst))]>;
388 // Conditional branches
389 let Uses = [EFLAGS] in {
390 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
391 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
392 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
393 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
394 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
395 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
396 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
397 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
398 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
399 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
400 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
401 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
403 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
404 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
405 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
406 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
407 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
408 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
409 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
410 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
412 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
413 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
414 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
415 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
416 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
417 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
418 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
419 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
420 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
421 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
422 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
423 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
426 //===----------------------------------------------------------------------===//
427 // Call Instructions...
430 // All calls clobber the non-callee saved registers. ESP is marked as
431 // a use to prevent stack-pointer assignments that appear immediately
432 // before calls from potentially appearing dead. Uses for argument
433 // registers are added manually.
434 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
435 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
436 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, EFLAGS],
438 def CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:$dst,variable_ops),
439 "call\t${dst:call}", []>;
440 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
441 "call\t{*}$dst", [(X86call GR32:$dst)]>;
442 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
443 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
448 def TAILCALL : I<0, Pseudo, (outs), (ins),
452 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
453 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops),
454 "#TC_RETURN $dst $offset",
457 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
458 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops),
459 "#TC_RETURN $dst $offset",
462 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
464 def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAILCALL",
466 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
467 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
469 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
470 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
471 "jmp\t{*}$dst # TAILCALL", []>;
473 //===----------------------------------------------------------------------===//
474 // Miscellaneous Instructions...
476 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
477 def LEAVE : I<0xC9, RawFrm,
478 (outs), (ins), "leave", []>;
480 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
482 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
485 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
488 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
489 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
490 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
491 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
493 let isTwoAddress = 1 in // GR32 = bswap GR32
494 def BSWAP32r : I<0xC8, AddRegFrm,
495 (outs GR32:$dst), (ins GR32:$src),
497 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
500 // Bit scan instructions.
501 let Defs = [EFLAGS] in {
502 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
503 "bsf{w}\t{$src, $dst|$dst, $src}",
504 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
505 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
506 "bsf{w}\t{$src, $dst|$dst, $src}",
507 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
508 (implicit EFLAGS)]>, TB;
509 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
510 "bsf{l}\t{$src, $dst|$dst, $src}",
511 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
512 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
513 "bsf{l}\t{$src, $dst|$dst, $src}",
514 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
515 (implicit EFLAGS)]>, TB;
517 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
518 "bsr{w}\t{$src, $dst|$dst, $src}",
519 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
520 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
521 "bsr{w}\t{$src, $dst|$dst, $src}",
522 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
523 (implicit EFLAGS)]>, TB;
524 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
525 "bsr{l}\t{$src, $dst|$dst, $src}",
526 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
527 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
528 "bsr{l}\t{$src, $dst|$dst, $src}",
529 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
530 (implicit EFLAGS)]>, TB;
533 let neverHasSideEffects = 1 in
534 def LEA16r : I<0x8D, MRMSrcMem,
535 (outs GR16:$dst), (ins i32mem:$src),
536 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
537 let isReMaterializable = 1 in
538 def LEA32r : I<0x8D, MRMSrcMem,
539 (outs GR32:$dst), (ins lea32mem:$src),
540 "lea{l}\t{$src|$dst}, {$dst|$src}",
541 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
543 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
544 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
545 [(X86rep_movs i8)]>, REP;
546 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
547 [(X86rep_movs i16)]>, REP, OpSize;
548 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
549 [(X86rep_movs i32)]>, REP;
552 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
553 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
554 [(X86rep_stos i8)]>, REP;
555 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
556 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
557 [(X86rep_stos i16)]>, REP, OpSize;
558 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
559 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
560 [(X86rep_stos i32)]>, REP;
562 let Defs = [RAX, RDX] in
563 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
566 let isBarrier = 1, hasCtrlDep = 1 in {
567 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
570 //===----------------------------------------------------------------------===//
571 // Input/Output Instructions...
573 let Defs = [AL], Uses = [DX] in
574 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
575 "in{b}\t{%dx, %al|%AL, %DX}", []>;
576 let Defs = [AX], Uses = [DX] in
577 def IN16rr : I<0xED, RawFrm, (outs), (ins),
578 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
579 let Defs = [EAX], Uses = [DX] in
580 def IN32rr : I<0xED, RawFrm, (outs), (ins),
581 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
584 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
585 "in{b}\t{$port, %al|%AL, $port}", []>;
587 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
588 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
590 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
591 "in{l}\t{$port, %eax|%EAX, $port}", []>;
593 let Uses = [DX, AL] in
594 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
595 "out{b}\t{%al, %dx|%DX, %AL}", []>;
596 let Uses = [DX, AX] in
597 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
598 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
599 let Uses = [DX, EAX] in
600 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
601 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
604 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
605 "out{b}\t{%al, $port|$port, %AL}", []>;
607 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
608 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
610 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
611 "out{l}\t{%eax, $port|$port, %EAX}", []>;
613 //===----------------------------------------------------------------------===//
614 // Move Instructions...
616 let neverHasSideEffects = 1 in {
617 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
618 "mov{b}\t{$src, $dst|$dst, $src}", []>;
619 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
620 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
621 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
622 "mov{l}\t{$src, $dst|$dst, $src}", []>;
624 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
625 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
626 "mov{b}\t{$src, $dst|$dst, $src}",
627 [(set GR8:$dst, imm:$src)]>;
628 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
629 "mov{w}\t{$src, $dst|$dst, $src}",
630 [(set GR16:$dst, imm:$src)]>, OpSize;
631 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
632 "mov{l}\t{$src, $dst|$dst, $src}",
633 [(set GR32:$dst, imm:$src)]>;
635 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
636 "mov{b}\t{$src, $dst|$dst, $src}",
637 [(store (i8 imm:$src), addr:$dst)]>;
638 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
639 "mov{w}\t{$src, $dst|$dst, $src}",
640 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
641 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
642 "mov{l}\t{$src, $dst|$dst, $src}",
643 [(store (i32 imm:$src), addr:$dst)]>;
645 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
646 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
647 "mov{b}\t{$src, $dst|$dst, $src}",
648 [(set GR8:$dst, (load addr:$src))]>;
649 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
650 "mov{w}\t{$src, $dst|$dst, $src}",
651 [(set GR16:$dst, (load addr:$src))]>, OpSize;
652 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
653 "mov{l}\t{$src, $dst|$dst, $src}",
654 [(set GR32:$dst, (load addr:$src))]>;
657 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
658 "mov{b}\t{$src, $dst|$dst, $src}",
659 [(store GR8:$src, addr:$dst)]>;
660 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
661 "mov{w}\t{$src, $dst|$dst, $src}",
662 [(store GR16:$src, addr:$dst)]>, OpSize;
663 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
664 "mov{l}\t{$src, $dst|$dst, $src}",
665 [(store GR32:$src, addr:$dst)]>;
667 //===----------------------------------------------------------------------===//
668 // Fixed-Register Multiplication and Division Instructions...
671 // Extra precision multiplication
672 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
673 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
674 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
675 // This probably ought to be moved to a def : Pat<> if the
676 // syntax can be accepted.
677 [(set AL, (mul AL, GR8:$src))]>; // AL,AH = AL*GR8
678 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
679 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>,
680 OpSize; // AX,DX = AX*GR16
681 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
682 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l}\t$src", []>;
683 // EAX,EDX = EAX*GR32
684 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
685 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
687 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
688 // This probably ought to be moved to a def : Pat<> if the
689 // syntax can be accepted.
690 [(set AL, (mul AL, (loadi8 addr:$src)))]>; // AL,AH = AL*[mem8]
691 let mayLoad = 1, neverHasSideEffects = 1 in {
692 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
693 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
694 "mul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
695 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
696 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
697 "mul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
700 let neverHasSideEffects = 1 in {
701 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
702 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
704 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
705 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
706 OpSize; // AX,DX = AX*GR16
707 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
708 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
709 // EAX,EDX = EAX*GR32
711 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
712 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
713 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
714 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
715 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
716 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
717 let Defs = [EAX,EDX], Uses = [EAX] in
718 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
719 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
722 // unsigned division/remainder
723 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
724 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
726 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
727 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
728 "div{w}\t$src", []>, OpSize;
729 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
730 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
733 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
734 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
736 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
737 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
738 "div{w}\t$src", []>, OpSize;
739 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
740 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
744 // Signed division/remainder.
745 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
746 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
747 "idiv{b}\t$src", []>;
748 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
749 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
750 "idiv{w}\t$src", []>, OpSize;
751 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
752 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
753 "idiv{l}\t$src", []>;
754 let mayLoad = 1, mayLoad = 1 in {
755 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
756 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
757 "idiv{b}\t$src", []>;
758 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
759 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
760 "idiv{w}\t$src", []>, OpSize;
761 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
762 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
763 "idiv{l}\t$src", []>;
765 } // neverHasSideEffects
767 //===----------------------------------------------------------------------===//
768 // Two address Instructions.
770 let isTwoAddress = 1 in {
773 let Uses = [EFLAGS] in {
774 let isCommutable = 1 in {
775 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
776 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
777 "cmovb\t{$src2, $dst|$dst, $src2}",
778 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
779 X86_COND_B, EFLAGS))]>,
781 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
782 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
783 "cmovb\t{$src2, $dst|$dst, $src2}",
784 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
785 X86_COND_B, EFLAGS))]>,
788 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
789 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
790 "cmovae\t{$src2, $dst|$dst, $src2}",
791 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
792 X86_COND_AE, EFLAGS))]>,
794 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
795 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
796 "cmovae\t{$src2, $dst|$dst, $src2}",
797 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
798 X86_COND_AE, EFLAGS))]>,
800 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
801 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
802 "cmove\t{$src2, $dst|$dst, $src2}",
803 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
804 X86_COND_E, EFLAGS))]>,
806 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
807 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
808 "cmove\t{$src2, $dst|$dst, $src2}",
809 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
810 X86_COND_E, EFLAGS))]>,
812 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
813 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
814 "cmovne\t{$src2, $dst|$dst, $src2}",
815 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
816 X86_COND_NE, EFLAGS))]>,
818 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
819 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
820 "cmovne\t{$src2, $dst|$dst, $src2}",
821 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
822 X86_COND_NE, EFLAGS))]>,
824 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
825 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
826 "cmovbe\t{$src2, $dst|$dst, $src2}",
827 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
828 X86_COND_BE, EFLAGS))]>,
830 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
831 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
832 "cmovbe\t{$src2, $dst|$dst, $src2}",
833 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
834 X86_COND_BE, EFLAGS))]>,
836 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
837 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
838 "cmova\t{$src2, $dst|$dst, $src2}",
839 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
840 X86_COND_A, EFLAGS))]>,
842 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
843 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
844 "cmova\t{$src2, $dst|$dst, $src2}",
845 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
846 X86_COND_A, EFLAGS))]>,
848 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
849 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
850 "cmovl\t{$src2, $dst|$dst, $src2}",
851 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
852 X86_COND_L, EFLAGS))]>,
854 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
855 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
856 "cmovl\t{$src2, $dst|$dst, $src2}",
857 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
858 X86_COND_L, EFLAGS))]>,
860 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
861 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
862 "cmovge\t{$src2, $dst|$dst, $src2}",
863 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
864 X86_COND_GE, EFLAGS))]>,
866 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
867 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
868 "cmovge\t{$src2, $dst|$dst, $src2}",
869 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
870 X86_COND_GE, EFLAGS))]>,
872 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
873 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
874 "cmovle\t{$src2, $dst|$dst, $src2}",
875 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
876 X86_COND_LE, EFLAGS))]>,
878 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
879 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
880 "cmovle\t{$src2, $dst|$dst, $src2}",
881 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
882 X86_COND_LE, EFLAGS))]>,
884 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
885 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
886 "cmovg\t{$src2, $dst|$dst, $src2}",
887 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
888 X86_COND_G, EFLAGS))]>,
890 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
891 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
892 "cmovg\t{$src2, $dst|$dst, $src2}",
893 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
894 X86_COND_G, EFLAGS))]>,
896 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
897 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
898 "cmovs\t{$src2, $dst|$dst, $src2}",
899 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
900 X86_COND_S, EFLAGS))]>,
902 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
903 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
904 "cmovs\t{$src2, $dst|$dst, $src2}",
905 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
906 X86_COND_S, EFLAGS))]>,
908 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
909 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
910 "cmovns\t{$src2, $dst|$dst, $src2}",
911 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
912 X86_COND_NS, EFLAGS))]>,
914 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
915 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
916 "cmovns\t{$src2, $dst|$dst, $src2}",
917 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
918 X86_COND_NS, EFLAGS))]>,
920 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
921 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
922 "cmovp\t{$src2, $dst|$dst, $src2}",
923 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
924 X86_COND_P, EFLAGS))]>,
926 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
927 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
928 "cmovp\t{$src2, $dst|$dst, $src2}",
929 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
930 X86_COND_P, EFLAGS))]>,
932 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
933 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
934 "cmovnp\t{$src2, $dst|$dst, $src2}",
935 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
936 X86_COND_NP, EFLAGS))]>,
938 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
939 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
940 "cmovnp\t{$src2, $dst|$dst, $src2}",
941 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
942 X86_COND_NP, EFLAGS))]>,
944 } // isCommutable = 1
946 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
947 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
948 "cmovnp\t{$src2, $dst|$dst, $src2}",
949 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
950 X86_COND_NP, EFLAGS))]>,
953 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
954 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
955 "cmovb\t{$src2, $dst|$dst, $src2}",
956 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
957 X86_COND_B, EFLAGS))]>,
959 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
960 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
961 "cmovb\t{$src2, $dst|$dst, $src2}",
962 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
963 X86_COND_B, EFLAGS))]>,
965 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
966 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
967 "cmovae\t{$src2, $dst|$dst, $src2}",
968 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
969 X86_COND_AE, EFLAGS))]>,
971 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
972 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
973 "cmovae\t{$src2, $dst|$dst, $src2}",
974 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
975 X86_COND_AE, EFLAGS))]>,
977 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
978 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
979 "cmove\t{$src2, $dst|$dst, $src2}",
980 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
981 X86_COND_E, EFLAGS))]>,
983 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
984 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
985 "cmove\t{$src2, $dst|$dst, $src2}",
986 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
987 X86_COND_E, EFLAGS))]>,
989 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
990 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
991 "cmovne\t{$src2, $dst|$dst, $src2}",
992 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
993 X86_COND_NE, EFLAGS))]>,
995 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
996 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
997 "cmovne\t{$src2, $dst|$dst, $src2}",
998 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
999 X86_COND_NE, EFLAGS))]>,
1001 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1002 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1003 "cmovbe\t{$src2, $dst|$dst, $src2}",
1004 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1005 X86_COND_BE, EFLAGS))]>,
1007 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1008 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1009 "cmovbe\t{$src2, $dst|$dst, $src2}",
1010 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1011 X86_COND_BE, EFLAGS))]>,
1013 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1014 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1015 "cmova\t{$src2, $dst|$dst, $src2}",
1016 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1017 X86_COND_A, EFLAGS))]>,
1019 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1020 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1021 "cmova\t{$src2, $dst|$dst, $src2}",
1022 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1023 X86_COND_A, EFLAGS))]>,
1025 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1026 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1027 "cmovl\t{$src2, $dst|$dst, $src2}",
1028 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1029 X86_COND_L, EFLAGS))]>,
1031 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1032 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1033 "cmovl\t{$src2, $dst|$dst, $src2}",
1034 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1035 X86_COND_L, EFLAGS))]>,
1037 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1038 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1039 "cmovge\t{$src2, $dst|$dst, $src2}",
1040 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1041 X86_COND_GE, EFLAGS))]>,
1043 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1044 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1045 "cmovge\t{$src2, $dst|$dst, $src2}",
1046 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1047 X86_COND_GE, EFLAGS))]>,
1049 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1050 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1051 "cmovle\t{$src2, $dst|$dst, $src2}",
1052 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1053 X86_COND_LE, EFLAGS))]>,
1055 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1056 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1057 "cmovle\t{$src2, $dst|$dst, $src2}",
1058 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1059 X86_COND_LE, EFLAGS))]>,
1061 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1062 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1063 "cmovg\t{$src2, $dst|$dst, $src2}",
1064 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1065 X86_COND_G, EFLAGS))]>,
1067 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1068 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1069 "cmovg\t{$src2, $dst|$dst, $src2}",
1070 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1071 X86_COND_G, EFLAGS))]>,
1073 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1074 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1075 "cmovs\t{$src2, $dst|$dst, $src2}",
1076 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1077 X86_COND_S, EFLAGS))]>,
1079 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1080 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1081 "cmovs\t{$src2, $dst|$dst, $src2}",
1082 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1083 X86_COND_S, EFLAGS))]>,
1085 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1086 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1087 "cmovns\t{$src2, $dst|$dst, $src2}",
1088 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1089 X86_COND_NS, EFLAGS))]>,
1091 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1092 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1093 "cmovns\t{$src2, $dst|$dst, $src2}",
1094 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1095 X86_COND_NS, EFLAGS))]>,
1097 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1098 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1099 "cmovp\t{$src2, $dst|$dst, $src2}",
1100 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1101 X86_COND_P, EFLAGS))]>,
1103 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1104 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1105 "cmovp\t{$src2, $dst|$dst, $src2}",
1106 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1107 X86_COND_P, EFLAGS))]>,
1109 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1110 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1111 "cmovnp\t{$src2, $dst|$dst, $src2}",
1112 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1113 X86_COND_NP, EFLAGS))]>,
1115 } // Uses = [EFLAGS]
1118 // unary instructions
1119 let CodeSize = 2 in {
1120 let Defs = [EFLAGS] in {
1121 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1122 [(set GR8:$dst, (ineg GR8:$src))]>;
1123 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1124 [(set GR16:$dst, (ineg GR16:$src))]>, OpSize;
1125 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1126 [(set GR32:$dst, (ineg GR32:$src))]>;
1127 let isTwoAddress = 0 in {
1128 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1129 [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
1130 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1131 [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1132 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1133 [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
1136 } // Defs = [EFLAGS]
1138 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1139 [(set GR8:$dst, (not GR8:$src))]>;
1140 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1141 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1142 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1143 [(set GR32:$dst, (not GR32:$src))]>;
1144 let isTwoAddress = 0 in {
1145 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1146 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1147 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1148 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1149 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1150 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1154 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1155 let Defs = [EFLAGS] in {
1157 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1158 [(set GR8:$dst, (add GR8:$src, 1))]>;
1159 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1160 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1161 [(set GR16:$dst, (add GR16:$src, 1))]>,
1162 OpSize, Requires<[In32BitMode]>;
1163 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1164 [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>;
1166 let isTwoAddress = 0, CodeSize = 2 in {
1167 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1168 [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
1169 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1170 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>,
1171 OpSize, Requires<[In32BitMode]>;
1172 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1173 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>,
1174 Requires<[In32BitMode]>;
1178 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1179 [(set GR8:$dst, (add GR8:$src, -1))]>;
1180 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1181 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1182 [(set GR16:$dst, (add GR16:$src, -1))]>,
1183 OpSize, Requires<[In32BitMode]>;
1184 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1185 [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>;
1188 let isTwoAddress = 0, CodeSize = 2 in {
1189 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1190 [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
1191 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1192 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>,
1193 OpSize, Requires<[In32BitMode]>;
1194 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1195 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>,
1196 Requires<[In32BitMode]>;
1198 } // Defs = [EFLAGS]
1200 // Logical operators...
1201 let Defs = [EFLAGS] in {
1202 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1203 def AND8rr : I<0x20, MRMDestReg,
1204 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1205 "and{b}\t{$src2, $dst|$dst, $src2}",
1206 [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>;
1207 def AND16rr : I<0x21, MRMDestReg,
1208 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1209 "and{w}\t{$src2, $dst|$dst, $src2}",
1210 [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize;
1211 def AND32rr : I<0x21, MRMDestReg,
1212 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1213 "and{l}\t{$src2, $dst|$dst, $src2}",
1214 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
1217 def AND8rm : I<0x22, MRMSrcMem,
1218 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1219 "and{b}\t{$src2, $dst|$dst, $src2}",
1220 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>;
1221 def AND16rm : I<0x23, MRMSrcMem,
1222 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1223 "and{w}\t{$src2, $dst|$dst, $src2}",
1224 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize;
1225 def AND32rm : I<0x23, MRMSrcMem,
1226 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1227 "and{l}\t{$src2, $dst|$dst, $src2}",
1228 [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>;
1230 def AND8ri : Ii8<0x80, MRM4r,
1231 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1232 "and{b}\t{$src2, $dst|$dst, $src2}",
1233 [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>;
1234 def AND16ri : Ii16<0x81, MRM4r,
1235 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1236 "and{w}\t{$src2, $dst|$dst, $src2}",
1237 [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize;
1238 def AND32ri : Ii32<0x81, MRM4r,
1239 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1240 "and{l}\t{$src2, $dst|$dst, $src2}",
1241 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
1242 def AND16ri8 : Ii8<0x83, MRM4r,
1243 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1244 "and{w}\t{$src2, $dst|$dst, $src2}",
1245 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>,
1247 def AND32ri8 : Ii8<0x83, MRM4r,
1248 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1249 "and{l}\t{$src2, $dst|$dst, $src2}",
1250 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>;
1252 let isTwoAddress = 0 in {
1253 def AND8mr : I<0x20, MRMDestMem,
1254 (outs), (ins i8mem :$dst, GR8 :$src),
1255 "and{b}\t{$src, $dst|$dst, $src}",
1256 [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>;
1257 def AND16mr : I<0x21, MRMDestMem,
1258 (outs), (ins i16mem:$dst, GR16:$src),
1259 "and{w}\t{$src, $dst|$dst, $src}",
1260 [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>,
1262 def AND32mr : I<0x21, MRMDestMem,
1263 (outs), (ins i32mem:$dst, GR32:$src),
1264 "and{l}\t{$src, $dst|$dst, $src}",
1265 [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>;
1266 def AND8mi : Ii8<0x80, MRM4m,
1267 (outs), (ins i8mem :$dst, i8imm :$src),
1268 "and{b}\t{$src, $dst|$dst, $src}",
1269 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1270 def AND16mi : Ii16<0x81, MRM4m,
1271 (outs), (ins i16mem:$dst, i16imm:$src),
1272 "and{w}\t{$src, $dst|$dst, $src}",
1273 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1275 def AND32mi : Ii32<0x81, MRM4m,
1276 (outs), (ins i32mem:$dst, i32imm:$src),
1277 "and{l}\t{$src, $dst|$dst, $src}",
1278 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1279 def AND16mi8 : Ii8<0x83, MRM4m,
1280 (outs), (ins i16mem:$dst, i16i8imm :$src),
1281 "and{w}\t{$src, $dst|$dst, $src}",
1282 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1284 def AND32mi8 : Ii8<0x83, MRM4m,
1285 (outs), (ins i32mem:$dst, i32i8imm :$src),
1286 "and{l}\t{$src, $dst|$dst, $src}",
1287 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1291 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1292 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1293 "or{b}\t{$src2, $dst|$dst, $src2}",
1294 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
1295 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1296 "or{w}\t{$src2, $dst|$dst, $src2}",
1297 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize;
1298 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1299 "or{l}\t{$src2, $dst|$dst, $src2}",
1300 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
1302 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1303 "or{b}\t{$src2, $dst|$dst, $src2}",
1304 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
1305 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1306 "or{w}\t{$src2, $dst|$dst, $src2}",
1307 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize;
1308 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1309 "or{l}\t{$src2, $dst|$dst, $src2}",
1310 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>;
1312 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1313 "or{b}\t{$src2, $dst|$dst, $src2}",
1314 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
1315 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1316 "or{w}\t{$src2, $dst|$dst, $src2}",
1317 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize;
1318 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1319 "or{l}\t{$src2, $dst|$dst, $src2}",
1320 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
1322 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1323 "or{w}\t{$src2, $dst|$dst, $src2}",
1324 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1325 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1326 "or{l}\t{$src2, $dst|$dst, $src2}",
1327 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>;
1328 let isTwoAddress = 0 in {
1329 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1330 "or{b}\t{$src, $dst|$dst, $src}",
1331 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
1332 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1333 "or{w}\t{$src, $dst|$dst, $src}",
1334 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize;
1335 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1336 "or{l}\t{$src, $dst|$dst, $src}",
1337 [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>;
1338 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1339 "or{b}\t{$src, $dst|$dst, $src}",
1340 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1341 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1342 "or{w}\t{$src, $dst|$dst, $src}",
1343 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1345 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1346 "or{l}\t{$src, $dst|$dst, $src}",
1347 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1348 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1349 "or{w}\t{$src, $dst|$dst, $src}",
1350 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1352 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1353 "or{l}\t{$src, $dst|$dst, $src}",
1354 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1355 } // isTwoAddress = 0
1358 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1359 def XOR8rr : I<0x30, MRMDestReg,
1360 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1361 "xor{b}\t{$src2, $dst|$dst, $src2}",
1362 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>;
1363 def XOR16rr : I<0x31, MRMDestReg,
1364 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1365 "xor{w}\t{$src2, $dst|$dst, $src2}",
1366 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize;
1367 def XOR32rr : I<0x31, MRMDestReg,
1368 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1369 "xor{l}\t{$src2, $dst|$dst, $src2}",
1370 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
1371 } // isCommutable = 1
1373 def XOR8rm : I<0x32, MRMSrcMem ,
1374 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1375 "xor{b}\t{$src2, $dst|$dst, $src2}",
1376 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>;
1377 def XOR16rm : I<0x33, MRMSrcMem ,
1378 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1379 "xor{w}\t{$src2, $dst|$dst, $src2}",
1380 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>,
1382 def XOR32rm : I<0x33, MRMSrcMem ,
1383 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1384 "xor{l}\t{$src2, $dst|$dst, $src2}",
1385 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>;
1387 def XOR8ri : Ii8<0x80, MRM6r,
1388 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1389 "xor{b}\t{$src2, $dst|$dst, $src2}",
1390 [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>;
1391 def XOR16ri : Ii16<0x81, MRM6r,
1392 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1393 "xor{w}\t{$src2, $dst|$dst, $src2}",
1394 [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize;
1395 def XOR32ri : Ii32<0x81, MRM6r,
1396 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1397 "xor{l}\t{$src2, $dst|$dst, $src2}",
1398 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
1399 def XOR16ri8 : Ii8<0x83, MRM6r,
1400 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1401 "xor{w}\t{$src2, $dst|$dst, $src2}",
1402 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>,
1404 def XOR32ri8 : Ii8<0x83, MRM6r,
1405 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1406 "xor{l}\t{$src2, $dst|$dst, $src2}",
1407 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>;
1409 let isTwoAddress = 0 in {
1410 def XOR8mr : I<0x30, MRMDestMem,
1411 (outs), (ins i8mem :$dst, GR8 :$src),
1412 "xor{b}\t{$src, $dst|$dst, $src}",
1413 [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>;
1414 def XOR16mr : I<0x31, MRMDestMem,
1415 (outs), (ins i16mem:$dst, GR16:$src),
1416 "xor{w}\t{$src, $dst|$dst, $src}",
1417 [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>,
1419 def XOR32mr : I<0x31, MRMDestMem,
1420 (outs), (ins i32mem:$dst, GR32:$src),
1421 "xor{l}\t{$src, $dst|$dst, $src}",
1422 [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>;
1423 def XOR8mi : Ii8<0x80, MRM6m,
1424 (outs), (ins i8mem :$dst, i8imm :$src),
1425 "xor{b}\t{$src, $dst|$dst, $src}",
1426 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1427 def XOR16mi : Ii16<0x81, MRM6m,
1428 (outs), (ins i16mem:$dst, i16imm:$src),
1429 "xor{w}\t{$src, $dst|$dst, $src}",
1430 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1432 def XOR32mi : Ii32<0x81, MRM6m,
1433 (outs), (ins i32mem:$dst, i32imm:$src),
1434 "xor{l}\t{$src, $dst|$dst, $src}",
1435 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1436 def XOR16mi8 : Ii8<0x83, MRM6m,
1437 (outs), (ins i16mem:$dst, i16i8imm :$src),
1438 "xor{w}\t{$src, $dst|$dst, $src}",
1439 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1441 def XOR32mi8 : Ii8<0x83, MRM6m,
1442 (outs), (ins i32mem:$dst, i32i8imm :$src),
1443 "xor{l}\t{$src, $dst|$dst, $src}",
1444 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1445 } // isTwoAddress = 0
1446 } // Defs = [EFLAGS]
1448 // Shift instructions
1449 let Defs = [EFLAGS] in {
1450 let Uses = [CL] in {
1451 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1452 "shl{b}\t{%cl, $dst|$dst, %CL}",
1453 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1454 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1455 "shl{w}\t{%cl, $dst|$dst, %CL}",
1456 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1457 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1458 "shl{l}\t{%cl, $dst|$dst, %CL}",
1459 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1462 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1463 "shl{b}\t{$src2, $dst|$dst, $src2}",
1464 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1465 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1466 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1467 "shl{w}\t{$src2, $dst|$dst, $src2}",
1468 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1469 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1470 "shl{l}\t{$src2, $dst|$dst, $src2}",
1471 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1472 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1474 } // isConvertibleToThreeAddress = 1
1476 let isTwoAddress = 0 in {
1477 let Uses = [CL] in {
1478 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1479 "shl{b}\t{%cl, $dst|$dst, %CL}",
1480 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1481 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1482 "shl{w}\t{%cl, $dst|$dst, %CL}",
1483 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1484 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1485 "shl{l}\t{%cl, $dst|$dst, %CL}",
1486 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1488 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1489 "shl{b}\t{$src, $dst|$dst, $src}",
1490 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1491 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1492 "shl{w}\t{$src, $dst|$dst, $src}",
1493 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1495 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1496 "shl{l}\t{$src, $dst|$dst, $src}",
1497 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1500 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1502 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1503 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1505 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1507 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1509 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1512 let Uses = [CL] in {
1513 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1514 "shr{b}\t{%cl, $dst|$dst, %CL}",
1515 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1516 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1517 "shr{w}\t{%cl, $dst|$dst, %CL}",
1518 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1519 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1520 "shr{l}\t{%cl, $dst|$dst, %CL}",
1521 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1524 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1525 "shr{b}\t{$src2, $dst|$dst, $src2}",
1526 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1527 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1528 "shr{w}\t{$src2, $dst|$dst, $src2}",
1529 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1530 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1531 "shr{l}\t{$src2, $dst|$dst, $src2}",
1532 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1535 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1537 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1538 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1540 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1541 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1543 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1545 let isTwoAddress = 0 in {
1546 let Uses = [CL] in {
1547 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1548 "shr{b}\t{%cl, $dst|$dst, %CL}",
1549 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1550 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1551 "shr{w}\t{%cl, $dst|$dst, %CL}",
1552 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1554 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1555 "shr{l}\t{%cl, $dst|$dst, %CL}",
1556 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1558 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1559 "shr{b}\t{$src, $dst|$dst, $src}",
1560 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1561 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1562 "shr{w}\t{$src, $dst|$dst, $src}",
1563 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1565 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1566 "shr{l}\t{$src, $dst|$dst, $src}",
1567 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1570 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1572 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1573 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1575 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1576 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1578 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1581 let Uses = [CL] in {
1582 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1583 "sar{b}\t{%cl, $dst|$dst, %CL}",
1584 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1585 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1586 "sar{w}\t{%cl, $dst|$dst, %CL}",
1587 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1588 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1589 "sar{l}\t{%cl, $dst|$dst, %CL}",
1590 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1593 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1594 "sar{b}\t{$src2, $dst|$dst, $src2}",
1595 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1596 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1597 "sar{w}\t{$src2, $dst|$dst, $src2}",
1598 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1600 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1601 "sar{l}\t{$src2, $dst|$dst, $src2}",
1602 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1605 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1607 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1608 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1610 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1611 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1613 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1615 let isTwoAddress = 0 in {
1616 let Uses = [CL] in {
1617 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1618 "sar{b}\t{%cl, $dst|$dst, %CL}",
1619 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
1620 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1621 "sar{w}\t{%cl, $dst|$dst, %CL}",
1622 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1623 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1624 "sar{l}\t{%cl, $dst|$dst, %CL}",
1625 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1627 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1628 "sar{b}\t{$src, $dst|$dst, $src}",
1629 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1630 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1631 "sar{w}\t{$src, $dst|$dst, $src}",
1632 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1634 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1635 "sar{l}\t{$src, $dst|$dst, $src}",
1636 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1639 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1641 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1642 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1644 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1646 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
1648 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1651 // Rotate instructions
1652 // FIXME: provide shorter instructions when imm8 == 1
1653 let Uses = [CL] in {
1654 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
1655 "rol{b}\t{%cl, $dst|$dst, %CL}",
1656 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
1657 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
1658 "rol{w}\t{%cl, $dst|$dst, %CL}",
1659 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
1660 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
1661 "rol{l}\t{%cl, $dst|$dst, %CL}",
1662 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
1665 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1666 "rol{b}\t{$src2, $dst|$dst, $src2}",
1667 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1668 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1669 "rol{w}\t{$src2, $dst|$dst, $src2}",
1670 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1671 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1672 "rol{l}\t{$src2, $dst|$dst, $src2}",
1673 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1676 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1678 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1679 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
1681 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1682 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1684 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1686 let isTwoAddress = 0 in {
1687 let Uses = [CL] in {
1688 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
1689 "rol{b}\t{%cl, $dst|$dst, %CL}",
1690 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
1691 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
1692 "rol{w}\t{%cl, $dst|$dst, %CL}",
1693 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1694 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
1695 "rol{l}\t{%cl, $dst|$dst, %CL}",
1696 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
1698 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
1699 "rol{b}\t{$src, $dst|$dst, $src}",
1700 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1701 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
1702 "rol{w}\t{$src, $dst|$dst, $src}",
1703 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1705 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
1706 "rol{l}\t{$src, $dst|$dst, $src}",
1707 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1710 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
1712 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1713 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
1715 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1717 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
1719 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1722 let Uses = [CL] in {
1723 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
1724 "ror{b}\t{%cl, $dst|$dst, %CL}",
1725 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
1726 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
1727 "ror{w}\t{%cl, $dst|$dst, %CL}",
1728 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
1729 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
1730 "ror{l}\t{%cl, $dst|$dst, %CL}",
1731 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
1734 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1735 "ror{b}\t{$src2, $dst|$dst, $src2}",
1736 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
1737 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1738 "ror{w}\t{$src2, $dst|$dst, $src2}",
1739 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1740 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1741 "ror{l}\t{$src2, $dst|$dst, $src2}",
1742 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
1745 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1747 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
1748 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
1750 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
1751 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
1753 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
1755 let isTwoAddress = 0 in {
1756 let Uses = [CL] in {
1757 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
1758 "ror{b}\t{%cl, $dst|$dst, %CL}",
1759 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
1760 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
1761 "ror{w}\t{%cl, $dst|$dst, %CL}",
1762 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1763 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
1764 "ror{l}\t{%cl, $dst|$dst, %CL}",
1765 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
1767 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1768 "ror{b}\t{$src, $dst|$dst, $src}",
1769 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1770 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
1771 "ror{w}\t{$src, $dst|$dst, $src}",
1772 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1774 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
1775 "ror{l}\t{$src, $dst|$dst, $src}",
1776 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1779 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
1781 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1782 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
1784 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1786 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
1788 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1793 // Double shift instructions (generalizations of rotate)
1794 let Uses = [CL] in {
1795 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1796 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1797 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
1798 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1799 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1800 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
1801 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1802 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1803 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
1805 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1806 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1807 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
1811 let isCommutable = 1 in { // These instructions commute to each other.
1812 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
1813 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1814 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1815 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
1818 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
1819 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1820 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1821 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
1824 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
1825 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1826 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1827 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
1830 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
1831 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1832 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1833 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
1838 let isTwoAddress = 0 in {
1839 let Uses = [CL] in {
1840 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1841 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1842 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
1844 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1845 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1846 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
1849 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
1850 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1851 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1852 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
1853 (i8 imm:$src3)), addr:$dst)]>,
1855 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
1856 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1857 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1858 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
1859 (i8 imm:$src3)), addr:$dst)]>,
1862 let Uses = [CL] in {
1863 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1864 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1865 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
1866 addr:$dst)]>, TB, OpSize;
1867 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1868 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1869 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
1870 addr:$dst)]>, TB, OpSize;
1872 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
1873 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1874 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1875 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
1876 (i8 imm:$src3)), addr:$dst)]>,
1878 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
1879 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1880 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1881 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
1882 (i8 imm:$src3)), addr:$dst)]>,
1885 } // Defs = [EFLAGS]
1889 let Defs = [EFLAGS] in {
1890 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1891 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
1892 (ins GR8 :$src1, GR8 :$src2),
1893 "add{b}\t{$src2, $dst|$dst, $src2}",
1894 [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>;
1895 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1896 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
1897 (ins GR16:$src1, GR16:$src2),
1898 "add{w}\t{$src2, $dst|$dst, $src2}",
1899 [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize;
1900 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
1901 (ins GR32:$src1, GR32:$src2),
1902 "add{l}\t{$src2, $dst|$dst, $src2}",
1903 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
1904 } // end isConvertibleToThreeAddress
1905 } // end isCommutable
1906 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
1907 (ins GR8 :$src1, i8mem :$src2),
1908 "add{b}\t{$src2, $dst|$dst, $src2}",
1909 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>;
1910 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
1911 (ins GR16:$src1, i16mem:$src2),
1912 "add{w}\t{$src2, $dst|$dst, $src2}",
1913 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>,OpSize;
1914 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
1915 (ins GR32:$src1, i32mem:$src2),
1916 "add{l}\t{$src2, $dst|$dst, $src2}",
1917 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>;
1919 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1920 "add{b}\t{$src2, $dst|$dst, $src2}",
1921 [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>;
1923 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1924 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
1925 (ins GR16:$src1, i16imm:$src2),
1926 "add{w}\t{$src2, $dst|$dst, $src2}",
1927 [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize;
1928 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
1929 (ins GR32:$src1, i32imm:$src2),
1930 "add{l}\t{$src2, $dst|$dst, $src2}",
1931 [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>;
1932 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
1933 (ins GR16:$src1, i16i8imm:$src2),
1934 "add{w}\t{$src2, $dst|$dst, $src2}",
1935 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1936 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
1937 (ins GR32:$src1, i32i8imm:$src2),
1938 "add{l}\t{$src2, $dst|$dst, $src2}",
1939 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>;
1942 let isTwoAddress = 0 in {
1943 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1944 "add{b}\t{$src2, $dst|$dst, $src2}",
1945 [(store (add (load addr:$dst), GR8:$src2), addr:$dst)]>;
1946 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1947 "add{w}\t{$src2, $dst|$dst, $src2}",
1948 [(store (add (load addr:$dst), GR16:$src2), addr:$dst)]>,
1950 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1951 "add{l}\t{$src2, $dst|$dst, $src2}",
1952 [(store (add (load addr:$dst), GR32:$src2), addr:$dst)]>;
1953 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
1954 "add{b}\t{$src2, $dst|$dst, $src2}",
1955 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1956 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
1957 "add{w}\t{$src2, $dst|$dst, $src2}",
1958 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1960 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
1961 "add{l}\t{$src2, $dst|$dst, $src2}",
1962 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1963 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1964 "add{w}\t{$src2, $dst|$dst, $src2}",
1965 [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1967 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1968 "add{l}\t{$src2, $dst|$dst, $src2}",
1969 [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1972 let Uses = [EFLAGS] in {
1973 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1974 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1975 "adc{l}\t{$src2, $dst|$dst, $src2}",
1976 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
1978 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1979 "adc{l}\t{$src2, $dst|$dst, $src2}",
1980 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
1981 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1982 "adc{l}\t{$src2, $dst|$dst, $src2}",
1983 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
1984 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1985 "adc{l}\t{$src2, $dst|$dst, $src2}",
1986 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
1988 let isTwoAddress = 0 in {
1989 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1990 "adc{l}\t{$src2, $dst|$dst, $src2}",
1991 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
1992 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
1993 "adc{l}\t{$src2, $dst|$dst, $src2}",
1994 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1995 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1996 "adc{l}\t{$src2, $dst|$dst, $src2}",
1997 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1999 } // Uses = [EFLAGS]
2001 def SUB8rr : I<0x28, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
2002 "sub{b}\t{$src2, $dst|$dst, $src2}",
2003 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2))]>;
2004 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2005 "sub{w}\t{$src2, $dst|$dst, $src2}",
2006 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2))]>, OpSize;
2007 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2008 "sub{l}\t{$src2, $dst|$dst, $src2}",
2009 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
2010 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
2011 "sub{b}\t{$src2, $dst|$dst, $src2}",
2012 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2)))]>;
2013 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2014 "sub{w}\t{$src2, $dst|$dst, $src2}",
2015 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2)))]>, OpSize;
2016 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2017 "sub{l}\t{$src2, $dst|$dst, $src2}",
2018 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2)))]>;
2020 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2021 "sub{b}\t{$src2, $dst|$dst, $src2}",
2022 [(set GR8:$dst, (sub GR8:$src1, imm:$src2))]>;
2023 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2024 "sub{w}\t{$src2, $dst|$dst, $src2}",
2025 [(set GR16:$dst, (sub GR16:$src1, imm:$src2))]>, OpSize;
2026 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2027 "sub{l}\t{$src2, $dst|$dst, $src2}",
2028 [(set GR32:$dst, (sub GR32:$src1, imm:$src2))]>;
2029 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2030 "sub{w}\t{$src2, $dst|$dst, $src2}",
2031 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2))]>,
2033 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2034 "sub{l}\t{$src2, $dst|$dst, $src2}",
2035 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2))]>;
2036 let isTwoAddress = 0 in {
2037 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2038 "sub{b}\t{$src2, $dst|$dst, $src2}",
2039 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst)]>;
2040 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2041 "sub{w}\t{$src2, $dst|$dst, $src2}",
2042 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst)]>,
2044 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2045 "sub{l}\t{$src2, $dst|$dst, $src2}",
2046 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst)]>;
2047 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2048 "sub{b}\t{$src2, $dst|$dst, $src2}",
2049 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2050 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2051 "sub{w}\t{$src2, $dst|$dst, $src2}",
2052 [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2054 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2055 "sub{l}\t{$src2, $dst|$dst, $src2}",
2056 [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2057 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2058 "sub{w}\t{$src2, $dst|$dst, $src2}",
2059 [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2061 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2062 "sub{l}\t{$src2, $dst|$dst, $src2}",
2063 [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2066 let Uses = [EFLAGS] in {
2067 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2068 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2069 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2071 let isTwoAddress = 0 in {
2072 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2073 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2074 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2075 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2076 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2077 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2078 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2079 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2080 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2081 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2082 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2083 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2085 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2086 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2087 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2088 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2089 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2090 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2091 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2092 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2093 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2094 } // Uses = [EFLAGS]
2095 } // Defs = [EFLAGS]
2097 let Defs = [EFLAGS] in {
2098 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2099 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2100 "imul{w}\t{$src2, $dst|$dst, $src2}",
2101 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2))]>, TB, OpSize;
2102 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2103 "imul{l}\t{$src2, $dst|$dst, $src2}",
2104 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>, TB;
2106 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2107 "imul{w}\t{$src2, $dst|$dst, $src2}",
2108 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2)))]>,
2110 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2111 "imul{l}\t{$src2, $dst|$dst, $src2}",
2112 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2)))]>, TB;
2113 } // Defs = [EFLAGS]
2114 } // end Two Address instructions
2116 // Suprisingly enough, these are not two address instructions!
2117 let Defs = [EFLAGS] in {
2118 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2119 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2120 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2121 [(set GR16:$dst, (mul GR16:$src1, imm:$src2))]>, OpSize;
2122 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2123 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2124 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2125 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
2126 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2127 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2128 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2129 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2))]>,
2131 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2132 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2133 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2134 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2))]>;
2136 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2137 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2138 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2139 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2))]>,
2141 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2142 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2143 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2144 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2))]>;
2145 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2146 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2147 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2148 [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>,
2150 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2151 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2152 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2153 [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>;
2154 } // Defs = [EFLAGS]
2156 //===----------------------------------------------------------------------===//
2157 // Test instructions are just like AND, except they don't generate a result.
2159 let Defs = [EFLAGS] in {
2160 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2161 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2162 "test{b}\t{$src2, $src1|$src1, $src2}",
2163 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
2164 (implicit EFLAGS)]>;
2165 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2166 "test{w}\t{$src2, $src1|$src1, $src2}",
2167 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
2168 (implicit EFLAGS)]>,
2170 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2171 "test{l}\t{$src2, $src1|$src1, $src2}",
2172 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
2173 (implicit EFLAGS)]>;
2176 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2177 "test{b}\t{$src2, $src1|$src1, $src2}",
2178 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2179 (implicit EFLAGS)]>;
2180 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2181 "test{w}\t{$src2, $src1|$src1, $src2}",
2182 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2183 (implicit EFLAGS)]>, OpSize;
2184 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2185 "test{l}\t{$src2, $src1|$src1, $src2}",
2186 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2187 (implicit EFLAGS)]>;
2189 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2190 (outs), (ins GR8:$src1, i8imm:$src2),
2191 "test{b}\t{$src2, $src1|$src1, $src2}",
2192 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
2193 (implicit EFLAGS)]>;
2194 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2195 (outs), (ins GR16:$src1, i16imm:$src2),
2196 "test{w}\t{$src2, $src1|$src1, $src2}",
2197 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
2198 (implicit EFLAGS)]>, OpSize;
2199 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2200 (outs), (ins GR32:$src1, i32imm:$src2),
2201 "test{l}\t{$src2, $src1|$src1, $src2}",
2202 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
2203 (implicit EFLAGS)]>;
2205 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2206 (outs), (ins i8mem:$src1, i8imm:$src2),
2207 "test{b}\t{$src2, $src1|$src1, $src2}",
2208 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2209 (implicit EFLAGS)]>;
2210 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2211 (outs), (ins i16mem:$src1, i16imm:$src2),
2212 "test{w}\t{$src2, $src1|$src1, $src2}",
2213 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2214 (implicit EFLAGS)]>, OpSize;
2215 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2216 (outs), (ins i32mem:$src1, i32imm:$src2),
2217 "test{l}\t{$src2, $src1|$src1, $src2}",
2218 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2219 (implicit EFLAGS)]>;
2220 } // Defs = [EFLAGS]
2223 // Condition code ops, incl. set if equal/not equal/...
2224 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2225 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2226 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2227 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2229 let Uses = [EFLAGS] in {
2230 def SETEr : I<0x94, MRM0r,
2231 (outs GR8 :$dst), (ins),
2233 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2235 def SETEm : I<0x94, MRM0m,
2236 (outs), (ins i8mem:$dst),
2238 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2240 def SETNEr : I<0x95, MRM0r,
2241 (outs GR8 :$dst), (ins),
2243 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2245 def SETNEm : I<0x95, MRM0m,
2246 (outs), (ins i8mem:$dst),
2248 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2250 def SETLr : I<0x9C, MRM0r,
2251 (outs GR8 :$dst), (ins),
2253 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2254 TB; // GR8 = < signed
2255 def SETLm : I<0x9C, MRM0m,
2256 (outs), (ins i8mem:$dst),
2258 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2259 TB; // [mem8] = < signed
2260 def SETGEr : I<0x9D, MRM0r,
2261 (outs GR8 :$dst), (ins),
2263 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2264 TB; // GR8 = >= signed
2265 def SETGEm : I<0x9D, MRM0m,
2266 (outs), (ins i8mem:$dst),
2268 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2269 TB; // [mem8] = >= signed
2270 def SETLEr : I<0x9E, MRM0r,
2271 (outs GR8 :$dst), (ins),
2273 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2274 TB; // GR8 = <= signed
2275 def SETLEm : I<0x9E, MRM0m,
2276 (outs), (ins i8mem:$dst),
2278 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2279 TB; // [mem8] = <= signed
2280 def SETGr : I<0x9F, MRM0r,
2281 (outs GR8 :$dst), (ins),
2283 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2284 TB; // GR8 = > signed
2285 def SETGm : I<0x9F, MRM0m,
2286 (outs), (ins i8mem:$dst),
2288 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2289 TB; // [mem8] = > signed
2291 def SETBr : I<0x92, MRM0r,
2292 (outs GR8 :$dst), (ins),
2294 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2295 TB; // GR8 = < unsign
2296 def SETBm : I<0x92, MRM0m,
2297 (outs), (ins i8mem:$dst),
2299 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
2300 TB; // [mem8] = < unsign
2301 def SETAEr : I<0x93, MRM0r,
2302 (outs GR8 :$dst), (ins),
2304 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
2305 TB; // GR8 = >= unsign
2306 def SETAEm : I<0x93, MRM0m,
2307 (outs), (ins i8mem:$dst),
2309 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
2310 TB; // [mem8] = >= unsign
2311 def SETBEr : I<0x96, MRM0r,
2312 (outs GR8 :$dst), (ins),
2314 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
2315 TB; // GR8 = <= unsign
2316 def SETBEm : I<0x96, MRM0m,
2317 (outs), (ins i8mem:$dst),
2319 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
2320 TB; // [mem8] = <= unsign
2321 def SETAr : I<0x97, MRM0r,
2322 (outs GR8 :$dst), (ins),
2324 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
2325 TB; // GR8 = > signed
2326 def SETAm : I<0x97, MRM0m,
2327 (outs), (ins i8mem:$dst),
2329 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
2330 TB; // [mem8] = > signed
2332 def SETSr : I<0x98, MRM0r,
2333 (outs GR8 :$dst), (ins),
2335 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
2336 TB; // GR8 = <sign bit>
2337 def SETSm : I<0x98, MRM0m,
2338 (outs), (ins i8mem:$dst),
2340 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
2341 TB; // [mem8] = <sign bit>
2342 def SETNSr : I<0x99, MRM0r,
2343 (outs GR8 :$dst), (ins),
2345 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
2346 TB; // GR8 = !<sign bit>
2347 def SETNSm : I<0x99, MRM0m,
2348 (outs), (ins i8mem:$dst),
2350 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
2351 TB; // [mem8] = !<sign bit>
2352 def SETPr : I<0x9A, MRM0r,
2353 (outs GR8 :$dst), (ins),
2355 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
2357 def SETPm : I<0x9A, MRM0m,
2358 (outs), (ins i8mem:$dst),
2360 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
2361 TB; // [mem8] = parity
2362 def SETNPr : I<0x9B, MRM0r,
2363 (outs GR8 :$dst), (ins),
2365 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
2366 TB; // GR8 = not parity
2367 def SETNPm : I<0x9B, MRM0m,
2368 (outs), (ins i8mem:$dst),
2370 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
2371 TB; // [mem8] = not parity
2372 } // Uses = [EFLAGS]
2375 // Integer comparisons
2376 let Defs = [EFLAGS] in {
2377 def CMP8rr : I<0x38, MRMDestReg,
2378 (outs), (ins GR8 :$src1, GR8 :$src2),
2379 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2380 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2381 def CMP16rr : I<0x39, MRMDestReg,
2382 (outs), (ins GR16:$src1, GR16:$src2),
2383 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2384 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
2385 def CMP32rr : I<0x39, MRMDestReg,
2386 (outs), (ins GR32:$src1, GR32:$src2),
2387 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2388 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
2389 def CMP8mr : I<0x38, MRMDestMem,
2390 (outs), (ins i8mem :$src1, GR8 :$src2),
2391 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2392 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
2393 (implicit EFLAGS)]>;
2394 def CMP16mr : I<0x39, MRMDestMem,
2395 (outs), (ins i16mem:$src1, GR16:$src2),
2396 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2397 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
2398 (implicit EFLAGS)]>, OpSize;
2399 def CMP32mr : I<0x39, MRMDestMem,
2400 (outs), (ins i32mem:$src1, GR32:$src2),
2401 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2402 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
2403 (implicit EFLAGS)]>;
2404 def CMP8rm : I<0x3A, MRMSrcMem,
2405 (outs), (ins GR8 :$src1, i8mem :$src2),
2406 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2407 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
2408 (implicit EFLAGS)]>;
2409 def CMP16rm : I<0x3B, MRMSrcMem,
2410 (outs), (ins GR16:$src1, i16mem:$src2),
2411 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2412 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
2413 (implicit EFLAGS)]>, OpSize;
2414 def CMP32rm : I<0x3B, MRMSrcMem,
2415 (outs), (ins GR32:$src1, i32mem:$src2),
2416 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2417 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
2418 (implicit EFLAGS)]>;
2419 def CMP8ri : Ii8<0x80, MRM7r,
2420 (outs), (ins GR8:$src1, i8imm:$src2),
2421 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2422 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
2423 def CMP16ri : Ii16<0x81, MRM7r,
2424 (outs), (ins GR16:$src1, i16imm:$src2),
2425 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2426 [(X86cmp GR16:$src1, imm:$src2),
2427 (implicit EFLAGS)]>, OpSize;
2428 def CMP32ri : Ii32<0x81, MRM7r,
2429 (outs), (ins GR32:$src1, i32imm:$src2),
2430 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2431 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
2432 def CMP8mi : Ii8 <0x80, MRM7m,
2433 (outs), (ins i8mem :$src1, i8imm :$src2),
2434 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2435 [(X86cmp (loadi8 addr:$src1), imm:$src2),
2436 (implicit EFLAGS)]>;
2437 def CMP16mi : Ii16<0x81, MRM7m,
2438 (outs), (ins i16mem:$src1, i16imm:$src2),
2439 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2440 [(X86cmp (loadi16 addr:$src1), imm:$src2),
2441 (implicit EFLAGS)]>, OpSize;
2442 def CMP32mi : Ii32<0x81, MRM7m,
2443 (outs), (ins i32mem:$src1, i32imm:$src2),
2444 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2445 [(X86cmp (loadi32 addr:$src1), imm:$src2),
2446 (implicit EFLAGS)]>;
2447 def CMP16ri8 : Ii8<0x83, MRM7r,
2448 (outs), (ins GR16:$src1, i16i8imm:$src2),
2449 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2450 [(X86cmp GR16:$src1, i16immSExt8:$src2),
2451 (implicit EFLAGS)]>, OpSize;
2452 def CMP16mi8 : Ii8<0x83, MRM7m,
2453 (outs), (ins i16mem:$src1, i16i8imm:$src2),
2454 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2455 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
2456 (implicit EFLAGS)]>, OpSize;
2457 def CMP32mi8 : Ii8<0x83, MRM7m,
2458 (outs), (ins i32mem:$src1, i32i8imm:$src2),
2459 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2460 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
2461 (implicit EFLAGS)]>;
2462 def CMP32ri8 : Ii8<0x83, MRM7r,
2463 (outs), (ins GR32:$src1, i32i8imm:$src2),
2464 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2465 [(X86cmp GR32:$src1, i32immSExt8:$src2),
2466 (implicit EFLAGS)]>;
2467 } // Defs = [EFLAGS]
2469 // Sign/Zero extenders
2470 // Use movsbl intead of movsbw; we don't care about the high 16 bits
2471 // of the register here. This has a smaller encoding and avoids a
2472 // partial-register update.
2473 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2474 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2475 [(set GR16:$dst, (sext GR8:$src))]>, TB;
2476 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2477 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2478 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
2479 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2480 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2481 [(set GR32:$dst, (sext GR8:$src))]>, TB;
2482 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2483 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2484 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
2485 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2486 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2487 [(set GR32:$dst, (sext GR16:$src))]>, TB;
2488 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2489 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2490 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
2492 // Use movzbl intead of movzbw; we don't care about the high 16 bits
2493 // of the register here. This has a smaller encoding and avoids a
2494 // partial-register update.
2495 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2496 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2497 [(set GR16:$dst, (zext GR8:$src))]>, TB;
2498 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2499 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2500 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
2501 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2502 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2503 [(set GR32:$dst, (zext GR8:$src))]>, TB;
2504 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2505 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2506 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
2507 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2508 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2509 [(set GR32:$dst, (zext GR16:$src))]>, TB;
2510 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2511 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2512 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
2514 let neverHasSideEffects = 1 in {
2515 let Defs = [AX], Uses = [AL] in
2516 def CBW : I<0x98, RawFrm, (outs), (ins),
2517 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
2518 let Defs = [EAX], Uses = [AX] in
2519 def CWDE : I<0x98, RawFrm, (outs), (ins),
2520 "{cwtl|cwde}", []>; // EAX = signext(AX)
2522 let Defs = [AX,DX], Uses = [AX] in
2523 def CWD : I<0x99, RawFrm, (outs), (ins),
2524 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
2525 let Defs = [EAX,EDX], Uses = [EAX] in
2526 def CDQ : I<0x99, RawFrm, (outs), (ins),
2527 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
2530 //===----------------------------------------------------------------------===//
2531 // Alias Instructions
2532 //===----------------------------------------------------------------------===//
2534 // Alias instructions that map movr0 to xor.
2535 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2536 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1 in {
2537 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
2538 "xor{b}\t$dst, $dst",
2539 [(set GR8:$dst, 0)]>;
2540 // Use xorl instead of xorw since we don't care about the high 16 bits,
2541 // it's smaller, and it avoids a partial-register update.
2542 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
2543 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
2544 [(set GR16:$dst, 0)]>;
2545 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
2546 "xor{l}\t$dst, $dst",
2547 [(set GR32:$dst, 0)]>;
2550 // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
2551 // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
2552 let neverHasSideEffects = 1 in {
2553 def MOV16to16_ : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16:$src),
2554 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2555 def MOV32to32_ : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32:$src),
2556 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2558 def MOV16_rr : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16_:$src),
2559 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2560 def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src),
2561 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2562 } // neverHasSideEffects
2564 let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
2565 def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src),
2566 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2567 def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src),
2568 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2570 let mayStore = 1, neverHasSideEffects = 1 in {
2571 def MOV16_mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16_:$src),
2572 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2573 def MOV32_mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32_:$src),
2574 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2577 //===----------------------------------------------------------------------===//
2578 // Thread Local Storage Instructions
2582 def TLS_addr32 : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
2583 "leal\t${sym:mem}(,%ebx,1), $dst",
2584 [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
2586 let AddedComplexity = 10 in
2587 def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
2588 "movl\t%gs:($src), $dst",
2589 [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
2591 let AddedComplexity = 15 in
2592 def TLS_gs_ri : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
2593 "movl\t%gs:${src:mem}, $dst",
2595 (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>;
2597 def TLS_tp : I<0, Pseudo, (outs GR32:$dst), (ins),
2598 "movl\t%gs:0, $dst",
2599 [(set GR32:$dst, X86TLStp)]>;
2601 //===----------------------------------------------------------------------===//
2602 // DWARF Pseudo Instructions
2605 def DWARF_LOC : I<0, Pseudo, (outs),
2606 (ins i32imm:$line, i32imm:$col, i32imm:$file),
2607 ".loc\t${file:debug} ${line:debug} ${col:debug}",
2608 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
2611 //===----------------------------------------------------------------------===//
2612 // EH Pseudo Instructions
2614 let isTerminator = 1, isReturn = 1, isBarrier = 1,
2616 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
2617 "ret\t#eh_return, addr: $addr",
2618 [(X86ehret GR32:$addr)]>;
2622 //===----------------------------------------------------------------------===//
2626 // Atomic swap. These are just normal xchg instructions. But since a memory
2627 // operand is referenced, the atomicity is ensured.
2628 let Constraints = "$val = $dst" in {
2629 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2630 "xchg{l}\t{$val, $ptr|$ptr, $val}",
2631 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
2632 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2633 "xchg{w}\t{$val, $ptr|$ptr, $val}",
2634 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
2636 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2637 "xchg{b}\t{$val, $ptr|$ptr, $val}",
2638 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
2641 // Atomic compare and swap.
2642 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
2643 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
2644 "lock\n\tcmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
2645 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
2647 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
2648 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
2649 "lock\n\tcmpxchg8b\t$ptr",
2650 [(X86cas8 addr:$ptr)]>, TB, LOCK;
2653 let Defs = [AX, EFLAGS], Uses = [AX] in {
2654 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
2655 "lock\n\tcmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
2656 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
2658 let Defs = [AL, EFLAGS], Uses = [AL] in {
2659 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
2660 "lock\n\tcmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
2661 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
2664 // Atomic exchange and add
2665 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
2666 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2667 "lock\n\txadd{l}\t{$val, $ptr|$ptr, $val}",
2668 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
2670 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2671 "lock\n\txadd{w}\t{$val, $ptr|$ptr, $val}",
2672 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
2674 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2675 "lock\n\txadd{b}\t{$val, $ptr|$ptr, $val}",
2676 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
2680 // Atomic exchange, and, or, xor
2681 let Constraints = "$val = $dst", Defs = [EFLAGS],
2682 usesCustomDAGSchedInserter = 1 in {
2683 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2684 "#ATOMAND32 PSUEDO!",
2685 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
2686 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2687 "#ATOMOR32 PSUEDO!",
2688 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
2689 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2690 "#ATOMXOR32 PSUEDO!",
2691 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
2692 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2693 "#ATOMNAND32 PSUEDO!",
2694 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
2695 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2696 "#ATOMMIN32 PSUEDO!",
2697 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
2698 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2699 "#ATOMMAX32 PSUEDO!",
2700 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
2701 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2702 "#ATOMUMIN32 PSUEDO!",
2703 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
2704 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2705 "#ATOMUMAX32 PSUEDO!",
2706 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
2708 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2709 "#ATOMAND16 PSUEDO!",
2710 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
2711 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2712 "#ATOMOR16 PSUEDO!",
2713 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
2714 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2715 "#ATOMXOR16 PSUEDO!",
2716 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
2717 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2718 "#ATOMNAND16 PSUEDO!",
2719 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
2720 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2721 "#ATOMMIN16 PSUEDO!",
2722 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
2723 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2724 "#ATOMMAX16 PSUEDO!",
2725 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
2726 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2727 "#ATOMUMIN16 PSUEDO!",
2728 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
2729 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2730 "#ATOMUMAX16 PSUEDO!",
2731 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
2733 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
2734 "#ATOMAND8 PSUEDO!",
2735 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
2736 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
2738 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
2739 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
2740 "#ATOMXOR8 PSUEDO!",
2741 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
2742 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
2743 "#ATOMNAND8 PSUEDO!",
2744 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
2747 let Constraints = "$val1 = $dst1, $val2 = $dst2",
2748 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
2749 Uses = [EAX, EBX, ECX, EDX],
2750 mayLoad = 1, mayStore = 1,
2751 usesCustomDAGSchedInserter = 1 in {
2752 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2753 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2754 "#ATOMAND6432 PSUEDO!", []>;
2755 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2756 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2757 "#ATOMOR6432 PSUEDO!", []>;
2758 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2759 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2760 "#ATOMXOR6432 PSUEDO!", []>;
2761 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2762 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2763 "#ATOMNAND6432 PSUEDO!", []>;
2764 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2765 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2766 "#ATOMADD6432 PSUEDO!", []>;
2767 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2768 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2769 "#ATOMSUB6432 PSUEDO!", []>;
2770 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2771 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2772 "#ATOMSWAP6432 PSUEDO!", []>;
2775 //===----------------------------------------------------------------------===//
2776 // Non-Instruction Patterns
2777 //===----------------------------------------------------------------------===//
2779 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
2780 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
2781 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
2782 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
2783 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
2784 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
2786 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
2787 (ADD32ri GR32:$src1, tconstpool:$src2)>;
2788 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
2789 (ADD32ri GR32:$src1, tjumptable:$src2)>;
2790 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
2791 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
2792 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
2793 (ADD32ri GR32:$src1, texternalsym:$src2)>;
2795 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
2796 (MOV32mi addr:$dst, tglobaladdr:$src)>;
2797 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
2798 (MOV32mi addr:$dst, texternalsym:$src)>;
2802 def : Pat<(X86tailcall GR32:$dst),
2805 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
2807 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
2810 def : Pat<(X86tcret GR32:$dst, imm:$off),
2811 (TCRETURNri GR32:$dst, imm:$off)>;
2813 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
2814 (TCRETURNdi texternalsym:$dst, imm:$off)>;
2816 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
2817 (TCRETURNdi texternalsym:$dst, imm:$off)>;
2819 def : Pat<(X86call (i32 tglobaladdr:$dst)),
2820 (CALLpcrel32 tglobaladdr:$dst)>;
2821 def : Pat<(X86call (i32 texternalsym:$dst)),
2822 (CALLpcrel32 texternalsym:$dst)>;
2824 // X86 specific add which produces a flag.
2825 def : Pat<(addc GR32:$src1, GR32:$src2),
2826 (ADD32rr GR32:$src1, GR32:$src2)>;
2827 def : Pat<(addc GR32:$src1, (load addr:$src2)),
2828 (ADD32rm GR32:$src1, addr:$src2)>;
2829 def : Pat<(addc GR32:$src1, imm:$src2),
2830 (ADD32ri GR32:$src1, imm:$src2)>;
2831 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
2832 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
2834 def : Pat<(subc GR32:$src1, GR32:$src2),
2835 (SUB32rr GR32:$src1, GR32:$src2)>;
2836 def : Pat<(subc GR32:$src1, (load addr:$src2)),
2837 (SUB32rm GR32:$src1, addr:$src2)>;
2838 def : Pat<(subc GR32:$src1, imm:$src2),
2839 (SUB32ri GR32:$src1, imm:$src2)>;
2840 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
2841 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
2845 // TEST R,R is smaller than CMP R,0
2846 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
2847 (TEST8rr GR8:$src1, GR8:$src1)>;
2848 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
2849 (TEST16rr GR16:$src1, GR16:$src1)>;
2850 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
2851 (TEST32rr GR32:$src1, GR32:$src1)>;
2853 // zextload bool -> zextload byte
2854 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2855 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2856 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2858 // extload bool -> extload byte
2859 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2860 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>,
2861 Requires<[In32BitMode]>;
2862 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2863 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>,
2864 Requires<[In32BitMode]>;
2865 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
2866 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
2869 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>,
2870 Requires<[In32BitMode]>;
2871 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>,
2872 Requires<[In32BitMode]>;
2873 def : Pat<(i32 (anyext GR16:$src)),
2874 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
2876 // (and (i32 load), 255) -> (zextload i8)
2877 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
2878 (MOVZX32rm8 addr:$src)>;
2879 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
2880 (MOVZX32rm16 addr:$src)>;
2882 //===----------------------------------------------------------------------===//
2884 //===----------------------------------------------------------------------===//
2886 // r & (2^16-1) ==> movz
2887 def : Pat<(and GR32:$src1, 0xffff),
2888 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit)))>;
2889 // r & (2^8-1) ==> movz
2890 def : Pat<(and GR32:$src1, 0xff),
2891 (MOVZX32rr8 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src1),
2892 x86_subreg_8bit)))>,
2893 Requires<[In32BitMode]>;
2894 // r & (2^8-1) ==> movz
2895 def : Pat<(and GR16:$src1, 0xff),
2896 (MOVZX16rr8 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src1),
2897 x86_subreg_8bit)))>,
2898 Requires<[In32BitMode]>;
2900 // sext_inreg patterns
2901 def : Pat<(sext_inreg GR32:$src, i16),
2902 (MOVSX32rr16 (i16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)))>;
2903 def : Pat<(sext_inreg GR32:$src, i8),
2904 (MOVSX32rr8 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src),
2905 x86_subreg_8bit)))>,
2906 Requires<[In32BitMode]>;
2907 def : Pat<(sext_inreg GR16:$src, i8),
2908 (MOVSX16rr8 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src),
2909 x86_subreg_8bit)))>,
2910 Requires<[In32BitMode]>;
2913 def : Pat<(i16 (trunc GR32:$src)),
2914 (i16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
2915 def : Pat<(i8 (trunc GR32:$src)),
2916 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src), x86_subreg_8bit))>,
2917 Requires<[In32BitMode]>;
2918 def : Pat<(i8 (trunc GR16:$src)),
2919 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src), x86_subreg_8bit))>,
2920 Requires<[In32BitMode]>;
2922 // (shl x, 1) ==> (add x, x)
2923 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
2924 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
2925 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
2927 // (shl x (and y, 31)) ==> (shl x, y)
2928 def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
2929 (SHL8rCL GR8:$src1)>;
2930 def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
2931 (SHL16rCL GR16:$src1)>;
2932 def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
2933 (SHL32rCL GR32:$src1)>;
2934 def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
2935 (SHL8mCL addr:$dst)>;
2936 def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
2937 (SHL16mCL addr:$dst)>;
2938 def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
2939 (SHL32mCL addr:$dst)>;
2941 def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
2942 (SHR8rCL GR8:$src1)>;
2943 def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
2944 (SHR16rCL GR16:$src1)>;
2945 def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
2946 (SHR32rCL GR32:$src1)>;
2947 def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
2948 (SHR8mCL addr:$dst)>;
2949 def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
2950 (SHR16mCL addr:$dst)>;
2951 def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
2952 (SHR32mCL addr:$dst)>;
2954 def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
2955 (SAR8rCL GR8:$src1)>;
2956 def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
2957 (SAR16rCL GR16:$src1)>;
2958 def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
2959 (SAR32rCL GR32:$src1)>;
2960 def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
2961 (SAR8mCL addr:$dst)>;
2962 def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
2963 (SAR16mCL addr:$dst)>;
2964 def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
2965 (SAR32mCL addr:$dst)>;
2967 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
2968 def : Pat<(or (srl GR32:$src1, CL:$amt),
2969 (shl GR32:$src2, (sub 32, CL:$amt))),
2970 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
2972 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
2973 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2974 (SHRD32mrCL addr:$dst, GR32:$src2)>;
2976 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
2977 def : Pat<(or (shl GR32:$src1, CL:$amt),
2978 (srl GR32:$src2, (sub 32, CL:$amt))),
2979 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
2981 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
2982 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2983 (SHLD32mrCL addr:$dst, GR32:$src2)>;
2985 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
2986 def : Pat<(or (srl GR16:$src1, CL:$amt),
2987 (shl GR16:$src2, (sub 16, CL:$amt))),
2988 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
2990 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
2991 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2992 (SHRD16mrCL addr:$dst, GR16:$src2)>;
2994 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
2995 def : Pat<(or (shl GR16:$src1, CL:$amt),
2996 (srl GR16:$src2, (sub 16, CL:$amt))),
2997 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
2999 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
3000 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3001 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3003 //===----------------------------------------------------------------------===//
3004 // Floating Point Stack Support
3005 //===----------------------------------------------------------------------===//
3007 include "X86InstrFPStack.td"
3009 //===----------------------------------------------------------------------===//
3011 //===----------------------------------------------------------------------===//
3013 include "X86Instr64bit.td"
3015 //===----------------------------------------------------------------------===//
3016 // XMM Floating point support (requires SSE / SSE2)
3017 //===----------------------------------------------------------------------===//
3019 include "X86InstrSSE.td"
3021 //===----------------------------------------------------------------------===//
3022 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
3023 //===----------------------------------------------------------------------===//
3025 include "X86InstrMMX.td"