3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
33 def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
37 def SDTX86BrCond : SDTypeProfile<0, 3,
38 [SDTCisVT<0, OtherVT>,
39 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
41 def SDTX86SetCC : SDTypeProfile<1, 2,
43 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
44 def SDTX86SetCC_C : SDTypeProfile<1, 2,
46 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
48 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
50 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
52 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
53 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
54 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
56 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
57 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
60 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
62 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
66 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
68 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
70 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
72 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
74 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
76 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
78 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
80 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
81 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
82 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
83 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
85 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
87 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
89 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
90 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
92 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
93 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
95 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
96 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
98 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
99 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
101 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
102 [SDNPHasChain, SDNPMayStore,
103 SDNPMayLoad, SDNPMemOperand]>;
104 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
105 [SDNPHasChain, SDNPMayStore,
106 SDNPMayLoad, SDNPMemOperand]>;
107 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
108 [SDNPHasChain, SDNPMayStore,
109 SDNPMayLoad, SDNPMemOperand]>;
110 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
111 [SDNPHasChain, SDNPMayStore,
112 SDNPMayLoad, SDNPMemOperand]>;
113 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
114 [SDNPHasChain, SDNPMayStore,
115 SDNPMayLoad, SDNPMemOperand]>;
116 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
117 [SDNPHasChain, SDNPMayStore,
118 SDNPMayLoad, SDNPMemOperand]>;
119 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
120 [SDNPHasChain, SDNPMayStore,
121 SDNPMayLoad, SDNPMemOperand]>;
122 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
123 [SDNPHasChain, SDNPOptInFlag]>;
125 def X86vastart_save_xmm_regs :
126 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
127 SDT_X86VASTART_SAVE_XMM_REGS,
130 def X86callseq_start :
131 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
132 [SDNPHasChain, SDNPOutFlag]>;
134 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
135 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
137 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
138 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
140 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
141 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
142 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
143 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
146 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
147 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
149 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
150 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
152 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
153 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
154 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
155 SDT_X86SegmentBaseAddress, []>;
157 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
160 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
161 [SDNPHasChain, SDNPOptInFlag]>;
163 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
165 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
166 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
168 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
170 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
171 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
172 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
174 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
176 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
179 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
181 //===----------------------------------------------------------------------===//
182 // X86 Operand Definitions.
185 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
186 // the index operand of an address, to conform to x86 encoding restrictions.
187 def ptr_rc_nosp : PointerLikeRegClass<1>;
189 // *mem - Operand definitions for the funky X86 addressing mode operands.
191 def X86MemAsmOperand : AsmOperandClass {
195 def X86AbsMemAsmOperand : AsmOperandClass {
197 let SuperClass = X86MemAsmOperand;
199 def X86NoSegMemAsmOperand : AsmOperandClass {
200 let Name = "NoSegMem";
201 let SuperClass = X86MemAsmOperand;
203 class X86MemOperand<string printMethod> : Operand<iPTR> {
204 let PrintMethod = printMethod;
205 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
206 let ParserMatchClass = X86MemAsmOperand;
209 def opaque32mem : X86MemOperand<"printopaquemem">;
210 def opaque48mem : X86MemOperand<"printopaquemem">;
211 def opaque80mem : X86MemOperand<"printopaquemem">;
212 def opaque512mem : X86MemOperand<"printopaquemem">;
214 def i8mem : X86MemOperand<"printi8mem">;
215 def i16mem : X86MemOperand<"printi16mem">;
216 def i32mem : X86MemOperand<"printi32mem">;
217 def i64mem : X86MemOperand<"printi64mem">;
218 def i128mem : X86MemOperand<"printi128mem">;
219 //def i256mem : X86MemOperand<"printi256mem">;
220 def f32mem : X86MemOperand<"printf32mem">;
221 def f64mem : X86MemOperand<"printf64mem">;
222 def f80mem : X86MemOperand<"printf80mem">;
223 def f128mem : X86MemOperand<"printf128mem">;
224 //def f256mem : X86MemOperand<"printf256mem">;
226 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
227 // plain GR64, so that it doesn't potentially require a REX prefix.
228 def i8mem_NOREX : Operand<i64> {
229 let PrintMethod = "printi8mem";
230 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
231 let ParserMatchClass = X86MemAsmOperand;
234 def lea32mem : Operand<i32> {
235 let PrintMethod = "printlea32mem";
236 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
237 let ParserMatchClass = X86NoSegMemAsmOperand;
240 let ParserMatchClass = X86AbsMemAsmOperand,
241 PrintMethod = "print_pcrel_imm" in {
242 def i32imm_pcrel : Operand<i32>;
244 def offset8 : Operand<i64>;
245 def offset16 : Operand<i64>;
246 def offset32 : Operand<i64>;
247 def offset64 : Operand<i64>;
249 // Branch targets have OtherVT type and print as pc-relative values.
250 def brtarget : Operand<OtherVT>;
251 def brtarget8 : Operand<OtherVT>;
255 def SSECC : Operand<i8> {
256 let PrintMethod = "printSSECC";
259 def ImmSExt8AsmOperand : AsmOperandClass {
260 let Name = "ImmSExt8";
261 let SuperClass = ImmAsmOperand;
264 // A couple of more descriptive operand definitions.
265 // 16-bits but only 8 bits are significant.
266 def i16i8imm : Operand<i16> {
267 let ParserMatchClass = ImmSExt8AsmOperand;
269 // 32-bits but only 8 bits are significant.
270 def i32i8imm : Operand<i32> {
271 let ParserMatchClass = ImmSExt8AsmOperand;
274 //===----------------------------------------------------------------------===//
275 // X86 Complex Pattern Definitions.
278 // Define X86 specific addressing mode.
279 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
280 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
281 [add, sub, mul, X86mul_imm, shl, or, frameindex],
283 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
284 [tglobaltlsaddr], []>;
286 //===----------------------------------------------------------------------===//
287 // X86 Instruction Predicate Definitions.
288 def HasMMX : Predicate<"Subtarget->hasMMX()">;
289 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
290 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
291 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
292 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
293 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
294 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
295 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
296 def HasAVX : Predicate<"Subtarget->hasAVX()">;
297 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
298 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
299 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
300 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
301 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
302 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
303 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
304 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
305 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
306 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
307 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
308 "TM.getCodeModel() != CodeModel::Kernel">;
309 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
310 "TM.getCodeModel() == CodeModel::Kernel">;
311 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
312 def OptForSize : Predicate<"OptForSize">;
313 def OptForSpeed : Predicate<"!OptForSize">;
314 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
315 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
317 //===----------------------------------------------------------------------===//
318 // X86 Instruction Format Definitions.
321 include "X86InstrFormats.td"
323 //===----------------------------------------------------------------------===//
324 // Pattern fragments...
327 // X86 specific condition code. These correspond to CondCode in
328 // X86InstrInfo.h. They must be kept in synch.
329 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
330 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
331 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
332 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
333 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
334 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
335 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
336 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
337 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
338 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
339 def X86_COND_NO : PatLeaf<(i8 10)>;
340 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
341 def X86_COND_NS : PatLeaf<(i8 12)>;
342 def X86_COND_O : PatLeaf<(i8 13)>;
343 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
344 def X86_COND_S : PatLeaf<(i8 15)>;
346 def i16immSExt8 : PatLeaf<(i16 imm), [{
347 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
348 // sign extended field.
349 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
352 def i32immSExt8 : PatLeaf<(i32 imm), [{
353 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
354 // sign extended field.
355 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
358 // Helper fragments for loads.
359 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
360 // known to be 32-bit aligned or better. Ditto for i8 to i16.
361 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
362 LoadSDNode *LD = cast<LoadSDNode>(N);
363 if (const Value *Src = LD->getSrcValue())
364 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
365 if (PT->getAddressSpace() > 255)
367 ISD::LoadExtType ExtType = LD->getExtensionType();
368 if (ExtType == ISD::NON_EXTLOAD)
370 if (ExtType == ISD::EXTLOAD)
371 return LD->getAlignment() >= 2 && !LD->isVolatile();
375 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),
377 LoadSDNode *LD = cast<LoadSDNode>(N);
378 if (const Value *Src = LD->getSrcValue())
379 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
380 if (PT->getAddressSpace() > 255)
382 ISD::LoadExtType ExtType = LD->getExtensionType();
383 if (ExtType == ISD::EXTLOAD)
384 return LD->getAlignment() >= 2 && !LD->isVolatile();
388 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
389 LoadSDNode *LD = cast<LoadSDNode>(N);
390 if (const Value *Src = LD->getSrcValue())
391 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
392 if (PT->getAddressSpace() > 255)
394 ISD::LoadExtType ExtType = LD->getExtensionType();
395 if (ExtType == ISD::NON_EXTLOAD)
397 if (ExtType == ISD::EXTLOAD)
398 return LD->getAlignment() >= 4 && !LD->isVolatile();
402 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
403 LoadSDNode *LD = cast<LoadSDNode>(N);
404 if (const Value *Src = LD->getSrcValue())
405 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
406 if (PT->getAddressSpace() > 255)
408 if (LD->isVolatile())
410 ISD::LoadExtType ExtType = LD->getExtensionType();
411 if (ExtType == ISD::NON_EXTLOAD)
413 if (ExtType == ISD::EXTLOAD)
414 return LD->getAlignment() >= 4;
418 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
419 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
420 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
421 return PT->getAddressSpace() == 256;
425 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
426 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
427 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
428 return PT->getAddressSpace() == 257;
432 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{
433 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
434 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
435 if (PT->getAddressSpace() > 255)
439 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{
440 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
441 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
442 if (PT->getAddressSpace() > 255)
447 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{
448 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
449 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
450 if (PT->getAddressSpace() > 255)
454 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{
455 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
456 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
457 if (PT->getAddressSpace() > 255)
461 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{
462 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
463 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
464 if (PT->getAddressSpace() > 255)
469 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
470 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
471 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
473 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
474 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
475 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
476 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
477 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
478 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
480 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
481 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
482 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
483 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
484 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
485 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
488 // An 'and' node with a single use.
489 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
490 return N->hasOneUse();
492 // An 'srl' node with a single use.
493 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
494 return N->hasOneUse();
496 // An 'trunc' node with a single use.
497 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
498 return N->hasOneUse();
501 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
502 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
503 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
504 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
506 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
507 APInt Mask = APInt::getAllOnesValue(BitWidth);
508 APInt KnownZero0, KnownOne0;
509 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
510 APInt KnownZero1, KnownOne1;
511 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
512 return (~KnownZero0 & ~KnownZero1) == 0;
516 // 'shld' and 'shrd' instruction patterns. Note that even though these have
517 // the srl and shl in their patterns, the C++ code must still check for them,
518 // because predicates are tested before children nodes are explored.
520 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
521 (or (srl node:$src1, node:$amt1),
522 (shl node:$src2, node:$amt2)), [{
523 assert(N->getOpcode() == ISD::OR);
524 return N->getOperand(0).getOpcode() == ISD::SRL &&
525 N->getOperand(1).getOpcode() == ISD::SHL &&
526 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
527 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
528 N->getOperand(0).getConstantOperandVal(1) ==
529 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
532 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
533 (or (shl node:$src1, node:$amt1),
534 (srl node:$src2, node:$amt2)), [{
535 assert(N->getOpcode() == ISD::OR);
536 return N->getOperand(0).getOpcode() == ISD::SHL &&
537 N->getOperand(1).getOpcode() == ISD::SRL &&
538 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
539 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
540 N->getOperand(0).getConstantOperandVal(1) ==
541 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
544 //===----------------------------------------------------------------------===//
545 // Instruction list...
548 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
549 // a stack adjustment and the codegen must know that they may modify the stack
550 // pointer before prolog-epilog rewriting occurs.
551 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
552 // sub / add which can clobber EFLAGS.
553 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
554 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
556 [(X86callseq_start timm:$amt)]>,
557 Requires<[In32BitMode]>;
558 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
560 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
561 Requires<[In32BitMode]>;
564 // x86-64 va_start lowering magic.
565 let usesCustomInserter = 1 in
566 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
569 i64imm:$regsavefi, i64imm:$offset,
571 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
572 [(X86vastart_save_xmm_regs GR8:$al,
577 let neverHasSideEffects = 1 in {
578 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
579 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
580 "nop{w}\t$zero", []>, TB, OpSize;
581 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
582 "nop{l}\t$zero", []>, TB;
586 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int\t3", []>;
587 def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
588 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize;
589 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>;
591 // PIC base construction. This expands to code that looks like this:
594 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
595 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
598 //===----------------------------------------------------------------------===//
599 // Control Flow Instructions.
602 // Return instructions.
603 let isTerminator = 1, isReturn = 1, isBarrier = 1,
604 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
605 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
608 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
610 [(X86retflag timm:$amt)]>;
611 def LRET : I <0xCB, RawFrm, (outs), (ins),
613 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
617 // Unconditional branches.
618 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
619 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
620 "jmp\t$dst", [(br bb:$dst)]>;
621 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
625 // Conditional Branches.
626 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
627 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
628 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
629 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
630 [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
634 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
635 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
636 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
637 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
638 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
639 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
640 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
641 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
642 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
643 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
644 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
645 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
646 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
647 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
648 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
649 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
651 // FIXME: What about the CX/RCX versions of this instruction?
652 let Uses = [ECX], isBranch = 1, isTerminator = 1 in
653 def JCXZ8 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
658 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
659 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
660 [(brind GR32:$dst)]>;
661 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
662 [(brind (loadi32 addr:$dst))]>;
664 def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
665 (ins i16imm:$seg, i16imm:$off),
666 "ljmp{w}\t$seg, $off", []>, OpSize;
667 def FARJMP32i : Iseg32<0xEA, RawFrm, (outs),
668 (ins i16imm:$seg, i32imm:$off),
669 "ljmp{l}\t$seg, $off", []>;
671 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
672 "ljmp{w}\t{*}$dst", []>, OpSize;
673 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
674 "ljmp{l}\t{*}$dst", []>;
680 def LOOP : I<0xE2, RawFrm, (ins brtarget8:$dst), (outs), "loop\t$dst", []>;
681 def LOOPE : I<0xE1, RawFrm, (ins brtarget8:$dst), (outs), "loope\t$dst", []>;
682 def LOOPNE : I<0xE0, RawFrm, (ins brtarget8:$dst), (outs), "loopne\t$dst", []>;
684 //===----------------------------------------------------------------------===//
685 // Call Instructions...
688 // All calls clobber the non-callee saved registers. ESP is marked as
689 // a use to prevent stack-pointer assignments that appear immediately
690 // before calls from potentially appearing dead. Uses for argument
691 // registers are added manually.
692 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
693 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
694 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
695 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
697 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
698 (outs), (ins i32imm_pcrel:$dst,variable_ops),
700 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
701 "call\t{*}$dst", [(X86call GR32:$dst)]>;
702 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
703 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
705 def FARCALL16i : Iseg16<0x9A, RawFrm, (outs),
706 (ins i16imm:$seg, i16imm:$off),
707 "lcall{w}\t$seg, $off", []>, OpSize;
708 def FARCALL32i : Iseg32<0x9A, RawFrm, (outs),
709 (ins i16imm:$seg, i32imm:$off),
710 "lcall{l}\t$seg, $off", []>;
712 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
713 "lcall{w}\t{*}$dst", []>, OpSize;
714 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
715 "lcall{l}\t{*}$dst", []>;
718 // Constructing a stack frame.
720 def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl),
721 "enter\t$len, $lvl", []>;
725 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
726 def TCRETURNdi : I<0, Pseudo, (outs),
727 (ins i32imm:$dst, i32imm:$offset, variable_ops),
728 "#TC_RETURN $dst $offset",
731 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
732 def TCRETURNri : I<0, Pseudo, (outs),
733 (ins GR32:$dst, i32imm:$offset, variable_ops),
734 "#TC_RETURN $dst $offset",
737 // FIXME: The should be pseudo instructions that are lowered when going to
739 let isCall = 1, isBranch = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
740 def TAILJMPd : Ii32<0xE9, RawFrm, (outs),(ins i32imm_pcrel:$dst,variable_ops),
741 "jmp\t$dst # TAILCALL",
743 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
744 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst, variable_ops),
745 "jmp{l}\t{*}$dst # TAILCALL",
747 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
748 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst, variable_ops),
749 "jmp\t{*}$dst # TAILCALL", []>;
751 //===----------------------------------------------------------------------===//
752 // Miscellaneous Instructions...
754 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
755 def LEAVE : I<0xC9, RawFrm,
756 (outs), (ins), "leave", []>;
758 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
759 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
760 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
761 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
762 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
763 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
764 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
765 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
767 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
769 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
771 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
772 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
774 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
776 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
777 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
780 let mayStore = 1 in {
781 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
783 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
784 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
786 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
788 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
789 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
793 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
794 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
795 "push{l}\t$imm", []>;
796 def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
797 "push{l}\t$imm", []>;
798 def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
799 "push{l}\t$imm", []>;
802 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
803 def POPF : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
804 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf{l}", []>;
806 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
807 def PUSHF : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
808 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf{l}", []>;
811 let isTwoAddress = 1 in // GR32 = bswap GR32
812 def BSWAP32r : I<0xC8, AddRegFrm,
813 (outs GR32:$dst), (ins GR32:$src),
815 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
818 // Bit scan instructions.
819 let Defs = [EFLAGS] in {
820 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
821 "bsf{w}\t{$src, $dst|$dst, $src}",
822 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
823 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
824 "bsf{w}\t{$src, $dst|$dst, $src}",
825 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
826 (implicit EFLAGS)]>, TB;
827 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
828 "bsf{l}\t{$src, $dst|$dst, $src}",
829 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
830 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
831 "bsf{l}\t{$src, $dst|$dst, $src}",
832 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
833 (implicit EFLAGS)]>, TB;
835 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
836 "bsr{w}\t{$src, $dst|$dst, $src}",
837 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
838 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
839 "bsr{w}\t{$src, $dst|$dst, $src}",
840 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
841 (implicit EFLAGS)]>, TB;
842 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
843 "bsr{l}\t{$src, $dst|$dst, $src}",
844 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
845 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
846 "bsr{l}\t{$src, $dst|$dst, $src}",
847 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
848 (implicit EFLAGS)]>, TB;
851 let neverHasSideEffects = 1 in
852 def LEA16r : I<0x8D, MRMSrcMem,
853 (outs GR16:$dst), (ins lea32mem:$src),
854 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
855 let isReMaterializable = 1 in
856 def LEA32r : I<0x8D, MRMSrcMem,
857 (outs GR32:$dst), (ins lea32mem:$src),
858 "lea{l}\t{$src|$dst}, {$dst|$src}",
859 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
861 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
862 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
863 [(X86rep_movs i8)]>, REP;
864 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
865 [(X86rep_movs i16)]>, REP, OpSize;
866 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
867 [(X86rep_movs i32)]>, REP;
870 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
871 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
872 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
873 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
874 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
877 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
878 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
879 [(X86rep_stos i8)]>, REP;
880 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
881 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
882 [(X86rep_stos i16)]>, REP, OpSize;
883 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
884 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
885 [(X86rep_stos i32)]>, REP;
887 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
888 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
889 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
890 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
891 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
892 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
893 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
895 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
896 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
897 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
899 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
900 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
901 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
903 let Defs = [RAX, RDX] in
904 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
907 let isBarrier = 1, hasCtrlDep = 1 in {
908 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
911 def SYSCALL : I<0x05, RawFrm,
912 (outs), (ins), "syscall", []>, TB;
913 def SYSRET : I<0x07, RawFrm,
914 (outs), (ins), "sysret", []>, TB;
915 def SYSENTER : I<0x34, RawFrm,
916 (outs), (ins), "sysenter", []>, TB;
917 def SYSEXIT : I<0x35, RawFrm,
918 (outs), (ins), "sysexit", []>, TB;
920 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
923 //===----------------------------------------------------------------------===//
924 // Input/Output Instructions...
926 let Defs = [AL], Uses = [DX] in
927 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
928 "in{b}\t{%dx, %al|%AL, %DX}", []>;
929 let Defs = [AX], Uses = [DX] in
930 def IN16rr : I<0xED, RawFrm, (outs), (ins),
931 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
932 let Defs = [EAX], Uses = [DX] in
933 def IN32rr : I<0xED, RawFrm, (outs), (ins),
934 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
937 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
938 "in{b}\t{$port, %al|%AL, $port}", []>;
940 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
941 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
943 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
944 "in{l}\t{$port, %eax|%EAX, $port}", []>;
946 let Uses = [DX, AL] in
947 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
948 "out{b}\t{%al, %dx|%DX, %AL}", []>;
949 let Uses = [DX, AX] in
950 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
951 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
952 let Uses = [DX, EAX] in
953 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
954 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
957 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
958 "out{b}\t{%al, $port|$port, %AL}", []>;
960 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
961 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
963 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
964 "out{l}\t{%eax, $port|$port, %EAX}", []>;
966 def IN8 : I<0x6C, RawFrm, (outs), (ins),
968 def IN16 : I<0x6D, RawFrm, (outs), (ins),
969 "ins{w}", []>, OpSize;
970 def IN32 : I<0x6D, RawFrm, (outs), (ins),
973 //===----------------------------------------------------------------------===//
974 // Move Instructions...
976 let neverHasSideEffects = 1 in {
977 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
978 "mov{b}\t{$src, $dst|$dst, $src}", []>;
979 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
980 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
981 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
982 "mov{l}\t{$src, $dst|$dst, $src}", []>;
984 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
985 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
986 "mov{b}\t{$src, $dst|$dst, $src}",
987 [(set GR8:$dst, imm:$src)]>;
988 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
989 "mov{w}\t{$src, $dst|$dst, $src}",
990 [(set GR16:$dst, imm:$src)]>, OpSize;
991 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
992 "mov{l}\t{$src, $dst|$dst, $src}",
993 [(set GR32:$dst, imm:$src)]>;
996 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
997 "mov{b}\t{$src, $dst|$dst, $src}",
998 [(store (i8 imm:$src), addr:$dst)]>;
999 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1000 "mov{w}\t{$src, $dst|$dst, $src}",
1001 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
1002 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1003 "mov{l}\t{$src, $dst|$dst, $src}",
1004 [(store (i32 imm:$src), addr:$dst)]>;
1006 def MOV8o8a : Ii8 <0xA0, RawFrm, (outs), (ins offset8:$src),
1007 "mov{b}\t{$src, %al|%al, $src}", []>;
1008 def MOV16o16a : Ii16 <0xA1, RawFrm, (outs), (ins offset16:$src),
1009 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1010 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1011 "mov{l}\t{$src, %eax|%eax, $src}", []>;
1013 def MOV8ao8 : Ii8 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1014 "mov{b}\t{%al, $dst|$dst, %al}", []>;
1015 def MOV16ao16 : Ii16 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1016 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize;
1017 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1018 "mov{l}\t{%eax, $dst|$dst, %eax}", []>;
1020 // Moves to and from segment registers
1021 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
1022 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1023 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
1024 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1025 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
1026 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1027 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
1028 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1030 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1031 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1032 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1033 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1034 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1035 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1037 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
1038 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1039 "mov{b}\t{$src, $dst|$dst, $src}",
1040 [(set GR8:$dst, (loadi8 addr:$src))]>;
1041 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1042 "mov{w}\t{$src, $dst|$dst, $src}",
1043 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
1044 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1045 "mov{l}\t{$src, $dst|$dst, $src}",
1046 [(set GR32:$dst, (loadi32 addr:$src))]>;
1049 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1050 "mov{b}\t{$src, $dst|$dst, $src}",
1051 [(store GR8:$src, addr:$dst)]>;
1052 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1053 "mov{w}\t{$src, $dst|$dst, $src}",
1054 [(store GR16:$src, addr:$dst)]>, OpSize;
1055 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1056 "mov{l}\t{$src, $dst|$dst, $src}",
1057 [(store GR32:$src, addr:$dst)]>;
1059 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1060 // that they can be used for copying and storing h registers, which can't be
1061 // encoded when a REX prefix is present.
1062 let neverHasSideEffects = 1 in
1063 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1064 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1065 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1067 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1068 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1069 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1071 canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1072 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1073 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1074 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1076 // Moves to and from debug registers
1077 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
1078 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1079 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
1080 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1082 // Moves to and from control registers
1083 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG_32:$src),
1084 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1085 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_32:$dst), (ins GR32:$src),
1086 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1088 //===----------------------------------------------------------------------===//
1089 // Fixed-Register Multiplication and Division Instructions...
1092 // Extra precision multiplication
1093 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1094 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
1095 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1096 // This probably ought to be moved to a def : Pat<> if the
1097 // syntax can be accepted.
1098 [(set AL, (mul AL, GR8:$src)),
1099 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1101 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1102 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1104 []>, OpSize; // AX,DX = AX*GR16
1106 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1107 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1109 []>; // EAX,EDX = EAX*GR32
1111 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1112 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1114 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1115 // This probably ought to be moved to a def : Pat<> if the
1116 // syntax can be accepted.
1117 [(set AL, (mul AL, (loadi8 addr:$src))),
1118 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1120 let mayLoad = 1, neverHasSideEffects = 1 in {
1121 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1122 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1124 []>, OpSize; // AX,DX = AX*[mem16]
1126 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1127 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1129 []>; // EAX,EDX = EAX*[mem32]
1132 let neverHasSideEffects = 1 in {
1133 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1134 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1136 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1137 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1138 OpSize; // AX,DX = AX*GR16
1139 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1140 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1141 // EAX,EDX = EAX*GR32
1142 let mayLoad = 1 in {
1143 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1144 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1145 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1146 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1147 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1148 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1149 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1150 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1151 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1153 } // neverHasSideEffects
1155 // unsigned division/remainder
1156 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1157 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1158 "div{b}\t$src", []>;
1159 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1160 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1161 "div{w}\t$src", []>, OpSize;
1162 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1163 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1164 "div{l}\t$src", []>;
1165 let mayLoad = 1 in {
1166 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1167 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1168 "div{b}\t$src", []>;
1169 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1170 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1171 "div{w}\t$src", []>, OpSize;
1172 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1173 // EDX:EAX/[mem32] = EAX,EDX
1174 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
1175 "div{l}\t$src", []>;
1178 // Signed division/remainder.
1179 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1180 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1181 "idiv{b}\t$src", []>;
1182 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1183 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1184 "idiv{w}\t$src", []>, OpSize;
1185 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1186 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1187 "idiv{l}\t$src", []>;
1188 let mayLoad = 1, mayLoad = 1 in {
1189 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1190 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1191 "idiv{b}\t$src", []>;
1192 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1193 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1194 "idiv{w}\t$src", []>, OpSize;
1195 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1196 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1197 // EDX:EAX/[mem32] = EAX,EDX
1198 "idiv{l}\t$src", []>;
1201 //===----------------------------------------------------------------------===//
1202 // Two address Instructions.
1204 let isTwoAddress = 1 in {
1206 // Conditional moves
1207 let Uses = [EFLAGS] in {
1209 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1210 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1211 // however that requires promoting the operands, and can induce additional
1212 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1213 // clobber EFLAGS, because if one of the operands is zero, the expansion
1214 // could involve an xor.
1215 let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in
1216 def CMOV_GR8 : I<0, Pseudo,
1217 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1218 "#CMOV_GR8 PSEUDO!",
1219 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1220 imm:$cond, EFLAGS))]>;
1222 let isCommutable = 1 in {
1223 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1224 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1225 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1226 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1227 X86_COND_B, EFLAGS))]>,
1229 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1230 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1231 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1232 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1233 X86_COND_B, EFLAGS))]>,
1235 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1236 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1237 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1238 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1239 X86_COND_AE, EFLAGS))]>,
1241 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1242 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1243 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1244 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1245 X86_COND_AE, EFLAGS))]>,
1247 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1248 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1249 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1250 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1251 X86_COND_E, EFLAGS))]>,
1253 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1254 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1255 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1256 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1257 X86_COND_E, EFLAGS))]>,
1259 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1260 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1261 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1262 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1263 X86_COND_NE, EFLAGS))]>,
1265 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1266 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1267 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1268 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1269 X86_COND_NE, EFLAGS))]>,
1271 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1272 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1273 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1274 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1275 X86_COND_BE, EFLAGS))]>,
1277 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1278 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1279 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1280 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1281 X86_COND_BE, EFLAGS))]>,
1283 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1284 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1285 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1286 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1287 X86_COND_A, EFLAGS))]>,
1289 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1290 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1291 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1292 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1293 X86_COND_A, EFLAGS))]>,
1295 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1296 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1297 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1298 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1299 X86_COND_L, EFLAGS))]>,
1301 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1302 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1303 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1304 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1305 X86_COND_L, EFLAGS))]>,
1307 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1308 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1309 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1310 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1311 X86_COND_GE, EFLAGS))]>,
1313 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1314 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1315 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1316 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1317 X86_COND_GE, EFLAGS))]>,
1319 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1320 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1321 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1322 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1323 X86_COND_LE, EFLAGS))]>,
1325 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1326 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1327 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1328 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1329 X86_COND_LE, EFLAGS))]>,
1331 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1332 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1333 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1334 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1335 X86_COND_G, EFLAGS))]>,
1337 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1338 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1339 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1340 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1341 X86_COND_G, EFLAGS))]>,
1343 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1344 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1345 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1346 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1347 X86_COND_S, EFLAGS))]>,
1349 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1350 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1351 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1352 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1353 X86_COND_S, EFLAGS))]>,
1355 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1356 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1357 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1358 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1359 X86_COND_NS, EFLAGS))]>,
1361 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1362 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1363 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1364 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1365 X86_COND_NS, EFLAGS))]>,
1367 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1368 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1369 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1370 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1371 X86_COND_P, EFLAGS))]>,
1373 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1374 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1375 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1376 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1377 X86_COND_P, EFLAGS))]>,
1379 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1380 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1381 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1382 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1383 X86_COND_NP, EFLAGS))]>,
1385 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1386 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1387 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1388 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1389 X86_COND_NP, EFLAGS))]>,
1391 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1392 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1393 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1394 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1395 X86_COND_O, EFLAGS))]>,
1397 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1398 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1399 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1400 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1401 X86_COND_O, EFLAGS))]>,
1403 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1404 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1405 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1406 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1407 X86_COND_NO, EFLAGS))]>,
1409 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1410 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1411 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1412 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1413 X86_COND_NO, EFLAGS))]>,
1415 } // isCommutable = 1
1417 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1418 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1419 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1420 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1421 X86_COND_B, EFLAGS))]>,
1423 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1424 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1425 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1426 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1427 X86_COND_B, EFLAGS))]>,
1429 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1430 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1431 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1432 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1433 X86_COND_AE, EFLAGS))]>,
1435 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1436 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1437 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1438 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1439 X86_COND_AE, EFLAGS))]>,
1441 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1442 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1443 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1444 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1445 X86_COND_E, EFLAGS))]>,
1447 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1448 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1449 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1450 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1451 X86_COND_E, EFLAGS))]>,
1453 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1454 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1455 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1456 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1457 X86_COND_NE, EFLAGS))]>,
1459 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1460 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1461 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1462 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1463 X86_COND_NE, EFLAGS))]>,
1465 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1466 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1467 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1468 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1469 X86_COND_BE, EFLAGS))]>,
1471 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1472 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1473 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1474 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1475 X86_COND_BE, EFLAGS))]>,
1477 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1478 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1479 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1480 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1481 X86_COND_A, EFLAGS))]>,
1483 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1484 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1485 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1486 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1487 X86_COND_A, EFLAGS))]>,
1489 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1490 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1491 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1492 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1493 X86_COND_L, EFLAGS))]>,
1495 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1496 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1497 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1498 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1499 X86_COND_L, EFLAGS))]>,
1501 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1502 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1503 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1504 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1505 X86_COND_GE, EFLAGS))]>,
1507 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1508 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1509 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1510 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1511 X86_COND_GE, EFLAGS))]>,
1513 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1514 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1515 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1516 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1517 X86_COND_LE, EFLAGS))]>,
1519 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1520 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1521 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1522 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1523 X86_COND_LE, EFLAGS))]>,
1525 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1526 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1527 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1528 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1529 X86_COND_G, EFLAGS))]>,
1531 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1532 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1533 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1534 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1535 X86_COND_G, EFLAGS))]>,
1537 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1538 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1539 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1540 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1541 X86_COND_S, EFLAGS))]>,
1543 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1544 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1545 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1546 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1547 X86_COND_S, EFLAGS))]>,
1549 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1550 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1551 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1552 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1553 X86_COND_NS, EFLAGS))]>,
1555 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1556 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1557 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1558 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1559 X86_COND_NS, EFLAGS))]>,
1561 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1562 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1563 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1564 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1565 X86_COND_P, EFLAGS))]>,
1567 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1568 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1569 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1570 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1571 X86_COND_P, EFLAGS))]>,
1573 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1574 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1575 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1576 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1577 X86_COND_NP, EFLAGS))]>,
1579 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1580 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1581 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1582 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1583 X86_COND_NP, EFLAGS))]>,
1585 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1586 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1587 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1588 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1589 X86_COND_O, EFLAGS))]>,
1591 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1592 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1593 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1594 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1595 X86_COND_O, EFLAGS))]>,
1597 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1598 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1599 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1600 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1601 X86_COND_NO, EFLAGS))]>,
1603 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1604 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1605 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1606 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1607 X86_COND_NO, EFLAGS))]>,
1609 } // Uses = [EFLAGS]
1612 // unary instructions
1613 let CodeSize = 2 in {
1614 let Defs = [EFLAGS] in {
1615 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1616 [(set GR8:$dst, (ineg GR8:$src)),
1617 (implicit EFLAGS)]>;
1618 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1619 [(set GR16:$dst, (ineg GR16:$src)),
1620 (implicit EFLAGS)]>, OpSize;
1621 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1622 [(set GR32:$dst, (ineg GR32:$src)),
1623 (implicit EFLAGS)]>;
1624 let isTwoAddress = 0 in {
1625 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1626 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1627 (implicit EFLAGS)]>;
1628 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1629 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1630 (implicit EFLAGS)]>, OpSize;
1631 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1632 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1633 (implicit EFLAGS)]>;
1635 } // Defs = [EFLAGS]
1637 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1638 let AddedComplexity = 15 in {
1639 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1640 [(set GR8:$dst, (not GR8:$src))]>;
1641 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1642 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1643 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1644 [(set GR32:$dst, (not GR32:$src))]>;
1646 let isTwoAddress = 0 in {
1647 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1648 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1649 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1650 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1651 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1652 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1656 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1657 let Defs = [EFLAGS] in {
1659 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1660 [(set GR8:$dst, (add GR8:$src, 1)),
1661 (implicit EFLAGS)]>;
1662 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1663 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1665 [(set GR16:$dst, (add GR16:$src, 1)),
1666 (implicit EFLAGS)]>,
1667 OpSize, Requires<[In32BitMode]>;
1668 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1670 [(set GR32:$dst, (add GR32:$src, 1)),
1671 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1673 let isTwoAddress = 0, CodeSize = 2 in {
1674 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1675 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1676 (implicit EFLAGS)]>;
1677 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1678 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1679 (implicit EFLAGS)]>,
1680 OpSize, Requires<[In32BitMode]>;
1681 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1682 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1683 (implicit EFLAGS)]>,
1684 Requires<[In32BitMode]>;
1688 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1689 [(set GR8:$dst, (add GR8:$src, -1)),
1690 (implicit EFLAGS)]>;
1691 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1692 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1694 [(set GR16:$dst, (add GR16:$src, -1)),
1695 (implicit EFLAGS)]>,
1696 OpSize, Requires<[In32BitMode]>;
1697 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1699 [(set GR32:$dst, (add GR32:$src, -1)),
1700 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1703 let isTwoAddress = 0, CodeSize = 2 in {
1704 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1705 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1706 (implicit EFLAGS)]>;
1707 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1708 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1709 (implicit EFLAGS)]>,
1710 OpSize, Requires<[In32BitMode]>;
1711 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1712 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1713 (implicit EFLAGS)]>,
1714 Requires<[In32BitMode]>;
1716 } // Defs = [EFLAGS]
1718 // Logical operators...
1719 let Defs = [EFLAGS] in {
1720 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1721 def AND8rr : I<0x20, MRMDestReg,
1722 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1723 "and{b}\t{$src2, $dst|$dst, $src2}",
1724 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
1725 (implicit EFLAGS)]>;
1726 def AND16rr : I<0x21, MRMDestReg,
1727 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1728 "and{w}\t{$src2, $dst|$dst, $src2}",
1729 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
1730 (implicit EFLAGS)]>, OpSize;
1731 def AND32rr : I<0x21, MRMDestReg,
1732 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1733 "and{l}\t{$src2, $dst|$dst, $src2}",
1734 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
1735 (implicit EFLAGS)]>;
1738 // AND instructions with the destination register in REG and the source register
1739 // in R/M. Included for the disassembler.
1740 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1741 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1742 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1743 (ins GR16:$src1, GR16:$src2),
1744 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1745 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1746 (ins GR32:$src1, GR32:$src2),
1747 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1749 def AND8rm : I<0x22, MRMSrcMem,
1750 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1751 "and{b}\t{$src2, $dst|$dst, $src2}",
1752 [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
1753 (implicit EFLAGS)]>;
1754 def AND16rm : I<0x23, MRMSrcMem,
1755 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1756 "and{w}\t{$src2, $dst|$dst, $src2}",
1757 [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
1758 (implicit EFLAGS)]>, OpSize;
1759 def AND32rm : I<0x23, MRMSrcMem,
1760 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1761 "and{l}\t{$src2, $dst|$dst, $src2}",
1762 [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
1763 (implicit EFLAGS)]>;
1765 def AND8ri : Ii8<0x80, MRM4r,
1766 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1767 "and{b}\t{$src2, $dst|$dst, $src2}",
1768 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
1769 (implicit EFLAGS)]>;
1770 def AND16ri : Ii16<0x81, MRM4r,
1771 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1772 "and{w}\t{$src2, $dst|$dst, $src2}",
1773 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
1774 (implicit EFLAGS)]>, OpSize;
1775 def AND32ri : Ii32<0x81, MRM4r,
1776 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1777 "and{l}\t{$src2, $dst|$dst, $src2}",
1778 [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
1779 (implicit EFLAGS)]>;
1780 def AND16ri8 : Ii8<0x83, MRM4r,
1781 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1782 "and{w}\t{$src2, $dst|$dst, $src2}",
1783 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
1784 (implicit EFLAGS)]>,
1786 def AND32ri8 : Ii8<0x83, MRM4r,
1787 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1788 "and{l}\t{$src2, $dst|$dst, $src2}",
1789 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
1790 (implicit EFLAGS)]>;
1792 let isTwoAddress = 0 in {
1793 def AND8mr : I<0x20, MRMDestMem,
1794 (outs), (ins i8mem :$dst, GR8 :$src),
1795 "and{b}\t{$src, $dst|$dst, $src}",
1796 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1797 (implicit EFLAGS)]>;
1798 def AND16mr : I<0x21, MRMDestMem,
1799 (outs), (ins i16mem:$dst, GR16:$src),
1800 "and{w}\t{$src, $dst|$dst, $src}",
1801 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1802 (implicit EFLAGS)]>,
1804 def AND32mr : I<0x21, MRMDestMem,
1805 (outs), (ins i32mem:$dst, GR32:$src),
1806 "and{l}\t{$src, $dst|$dst, $src}",
1807 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1808 (implicit EFLAGS)]>;
1809 def AND8mi : Ii8<0x80, MRM4m,
1810 (outs), (ins i8mem :$dst, i8imm :$src),
1811 "and{b}\t{$src, $dst|$dst, $src}",
1812 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1813 (implicit EFLAGS)]>;
1814 def AND16mi : Ii16<0x81, MRM4m,
1815 (outs), (ins i16mem:$dst, i16imm:$src),
1816 "and{w}\t{$src, $dst|$dst, $src}",
1817 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1818 (implicit EFLAGS)]>,
1820 def AND32mi : Ii32<0x81, MRM4m,
1821 (outs), (ins i32mem:$dst, i32imm:$src),
1822 "and{l}\t{$src, $dst|$dst, $src}",
1823 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1824 (implicit EFLAGS)]>;
1825 def AND16mi8 : Ii8<0x83, MRM4m,
1826 (outs), (ins i16mem:$dst, i16i8imm :$src),
1827 "and{w}\t{$src, $dst|$dst, $src}",
1828 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1829 (implicit EFLAGS)]>,
1831 def AND32mi8 : Ii8<0x83, MRM4m,
1832 (outs), (ins i32mem:$dst, i32i8imm :$src),
1833 "and{l}\t{$src, $dst|$dst, $src}",
1834 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1835 (implicit EFLAGS)]>;
1837 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1838 "and{b}\t{$src, %al|%al, $src}", []>;
1839 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1840 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1841 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1842 "and{l}\t{$src, %eax|%eax, $src}", []>;
1847 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1848 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1849 (ins GR8 :$src1, GR8 :$src2),
1850 "or{b}\t{$src2, $dst|$dst, $src2}",
1851 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
1852 (implicit EFLAGS)]>;
1853 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1854 (ins GR16:$src1, GR16:$src2),
1855 "or{w}\t{$src2, $dst|$dst, $src2}",
1856 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
1857 (implicit EFLAGS)]>, OpSize;
1858 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1859 (ins GR32:$src1, GR32:$src2),
1860 "or{l}\t{$src2, $dst|$dst, $src2}",
1861 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
1862 (implicit EFLAGS)]>;
1865 // OR instructions with the destination register in REG and the source register
1866 // in R/M. Included for the disassembler.
1867 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1868 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1869 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1870 (ins GR16:$src1, GR16:$src2),
1871 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1872 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1873 (ins GR32:$src1, GR32:$src2),
1874 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
1876 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst),
1877 (ins GR8 :$src1, i8mem :$src2),
1878 "or{b}\t{$src2, $dst|$dst, $src2}",
1879 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
1880 (implicit EFLAGS)]>;
1881 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst),
1882 (ins GR16:$src1, i16mem:$src2),
1883 "or{w}\t{$src2, $dst|$dst, $src2}",
1884 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
1885 (implicit EFLAGS)]>, OpSize;
1886 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst),
1887 (ins GR32:$src1, i32mem:$src2),
1888 "or{l}\t{$src2, $dst|$dst, $src2}",
1889 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
1890 (implicit EFLAGS)]>;
1892 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
1893 (ins GR8 :$src1, i8imm:$src2),
1894 "or{b}\t{$src2, $dst|$dst, $src2}",
1895 [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
1896 (implicit EFLAGS)]>;
1897 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
1898 (ins GR16:$src1, i16imm:$src2),
1899 "or{w}\t{$src2, $dst|$dst, $src2}",
1900 [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
1901 (implicit EFLAGS)]>, OpSize;
1902 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
1903 (ins GR32:$src1, i32imm:$src2),
1904 "or{l}\t{$src2, $dst|$dst, $src2}",
1905 [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
1906 (implicit EFLAGS)]>;
1908 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
1909 (ins GR16:$src1, i16i8imm:$src2),
1910 "or{w}\t{$src2, $dst|$dst, $src2}",
1911 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
1912 (implicit EFLAGS)]>, OpSize;
1913 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
1914 (ins GR32:$src1, i32i8imm:$src2),
1915 "or{l}\t{$src2, $dst|$dst, $src2}",
1916 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
1917 (implicit EFLAGS)]>;
1918 let isTwoAddress = 0 in {
1919 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1920 "or{b}\t{$src, $dst|$dst, $src}",
1921 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1922 (implicit EFLAGS)]>;
1923 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1924 "or{w}\t{$src, $dst|$dst, $src}",
1925 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1926 (implicit EFLAGS)]>, OpSize;
1927 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1928 "or{l}\t{$src, $dst|$dst, $src}",
1929 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1930 (implicit EFLAGS)]>;
1931 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1932 "or{b}\t{$src, $dst|$dst, $src}",
1933 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1934 (implicit EFLAGS)]>;
1935 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1936 "or{w}\t{$src, $dst|$dst, $src}",
1937 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1938 (implicit EFLAGS)]>,
1940 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1941 "or{l}\t{$src, $dst|$dst, $src}",
1942 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1943 (implicit EFLAGS)]>;
1944 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1945 "or{w}\t{$src, $dst|$dst, $src}",
1946 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1947 (implicit EFLAGS)]>,
1949 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1950 "or{l}\t{$src, $dst|$dst, $src}",
1951 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1952 (implicit EFLAGS)]>;
1954 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
1955 "or{b}\t{$src, %al|%al, $src}", []>;
1956 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
1957 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1958 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
1959 "or{l}\t{$src, %eax|%eax, $src}", []>;
1960 } // isTwoAddress = 0
1963 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1964 def XOR8rr : I<0x30, MRMDestReg,
1965 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1966 "xor{b}\t{$src2, $dst|$dst, $src2}",
1967 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
1968 (implicit EFLAGS)]>;
1969 def XOR16rr : I<0x31, MRMDestReg,
1970 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1971 "xor{w}\t{$src2, $dst|$dst, $src2}",
1972 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
1973 (implicit EFLAGS)]>, OpSize;
1974 def XOR32rr : I<0x31, MRMDestReg,
1975 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1976 "xor{l}\t{$src2, $dst|$dst, $src2}",
1977 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
1978 (implicit EFLAGS)]>;
1979 } // isCommutable = 1
1981 // XOR instructions with the destination register in REG and the source register
1982 // in R/M. Included for the disassembler.
1983 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1984 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
1985 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
1986 (ins GR16:$src1, GR16:$src2),
1987 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1988 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
1989 (ins GR32:$src1, GR32:$src2),
1990 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
1992 def XOR8rm : I<0x32, MRMSrcMem ,
1993 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1994 "xor{b}\t{$src2, $dst|$dst, $src2}",
1995 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
1996 (implicit EFLAGS)]>;
1997 def XOR16rm : I<0x33, MRMSrcMem ,
1998 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1999 "xor{w}\t{$src2, $dst|$dst, $src2}",
2000 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
2001 (implicit EFLAGS)]>,
2003 def XOR32rm : I<0x33, MRMSrcMem ,
2004 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2005 "xor{l}\t{$src2, $dst|$dst, $src2}",
2006 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
2007 (implicit EFLAGS)]>;
2009 def XOR8ri : Ii8<0x80, MRM6r,
2010 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2011 "xor{b}\t{$src2, $dst|$dst, $src2}",
2012 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
2013 (implicit EFLAGS)]>;
2014 def XOR16ri : Ii16<0x81, MRM6r,
2015 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2016 "xor{w}\t{$src2, $dst|$dst, $src2}",
2017 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
2018 (implicit EFLAGS)]>, OpSize;
2019 def XOR32ri : Ii32<0x81, MRM6r,
2020 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2021 "xor{l}\t{$src2, $dst|$dst, $src2}",
2022 [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
2023 (implicit EFLAGS)]>;
2024 def XOR16ri8 : Ii8<0x83, MRM6r,
2025 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2026 "xor{w}\t{$src2, $dst|$dst, $src2}",
2027 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
2028 (implicit EFLAGS)]>,
2030 def XOR32ri8 : Ii8<0x83, MRM6r,
2031 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2032 "xor{l}\t{$src2, $dst|$dst, $src2}",
2033 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
2034 (implicit EFLAGS)]>;
2036 let isTwoAddress = 0 in {
2037 def XOR8mr : I<0x30, MRMDestMem,
2038 (outs), (ins i8mem :$dst, GR8 :$src),
2039 "xor{b}\t{$src, $dst|$dst, $src}",
2040 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
2041 (implicit EFLAGS)]>;
2042 def XOR16mr : I<0x31, MRMDestMem,
2043 (outs), (ins i16mem:$dst, GR16:$src),
2044 "xor{w}\t{$src, $dst|$dst, $src}",
2045 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
2046 (implicit EFLAGS)]>,
2048 def XOR32mr : I<0x31, MRMDestMem,
2049 (outs), (ins i32mem:$dst, GR32:$src),
2050 "xor{l}\t{$src, $dst|$dst, $src}",
2051 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
2052 (implicit EFLAGS)]>;
2053 def XOR8mi : Ii8<0x80, MRM6m,
2054 (outs), (ins i8mem :$dst, i8imm :$src),
2055 "xor{b}\t{$src, $dst|$dst, $src}",
2056 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
2057 (implicit EFLAGS)]>;
2058 def XOR16mi : Ii16<0x81, MRM6m,
2059 (outs), (ins i16mem:$dst, i16imm:$src),
2060 "xor{w}\t{$src, $dst|$dst, $src}",
2061 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
2062 (implicit EFLAGS)]>,
2064 def XOR32mi : Ii32<0x81, MRM6m,
2065 (outs), (ins i32mem:$dst, i32imm:$src),
2066 "xor{l}\t{$src, $dst|$dst, $src}",
2067 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
2068 (implicit EFLAGS)]>;
2069 def XOR16mi8 : Ii8<0x83, MRM6m,
2070 (outs), (ins i16mem:$dst, i16i8imm :$src),
2071 "xor{w}\t{$src, $dst|$dst, $src}",
2072 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
2073 (implicit EFLAGS)]>,
2075 def XOR32mi8 : Ii8<0x83, MRM6m,
2076 (outs), (ins i32mem:$dst, i32i8imm :$src),
2077 "xor{l}\t{$src, $dst|$dst, $src}",
2078 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
2079 (implicit EFLAGS)]>;
2081 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
2082 "xor{b}\t{$src, %al|%al, $src}", []>;
2083 def XOR16i16 : Ii16 <0x35, RawFrm, (outs), (ins i16imm:$src),
2084 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2085 def XOR32i32 : Ii32 <0x35, RawFrm, (outs), (ins i32imm:$src),
2086 "xor{l}\t{$src, %eax|%eax, $src}", []>;
2087 } // isTwoAddress = 0
2088 } // Defs = [EFLAGS]
2090 // Shift instructions
2091 let Defs = [EFLAGS] in {
2092 let Uses = [CL] in {
2093 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
2094 "shl{b}\t{%cl, $dst|$dst, CL}",
2095 [(set GR8:$dst, (shl GR8:$src, CL))]>;
2096 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
2097 "shl{w}\t{%cl, $dst|$dst, CL}",
2098 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
2099 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
2100 "shl{l}\t{%cl, $dst|$dst, CL}",
2101 [(set GR32:$dst, (shl GR32:$src, CL))]>;
2104 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2105 "shl{b}\t{$src2, $dst|$dst, $src2}",
2106 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
2107 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2108 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2109 "shl{w}\t{$src2, $dst|$dst, $src2}",
2110 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2111 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2112 "shl{l}\t{$src2, $dst|$dst, $src2}",
2113 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
2115 // NOTE: We don't include patterns for shifts of a register by one, because
2116 // 'add reg,reg' is cheaper.
2118 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
2119 "shl{b}\t$dst", []>;
2120 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2121 "shl{w}\t$dst", []>, OpSize;
2122 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2123 "shl{l}\t$dst", []>;
2125 } // isConvertibleToThreeAddress = 1
2127 let isTwoAddress = 0 in {
2128 let Uses = [CL] in {
2129 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
2130 "shl{b}\t{%cl, $dst|$dst, CL}",
2131 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
2132 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
2133 "shl{w}\t{%cl, $dst|$dst, CL}",
2134 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2135 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
2136 "shl{l}\t{%cl, $dst|$dst, CL}",
2137 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
2139 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
2140 "shl{b}\t{$src, $dst|$dst, $src}",
2141 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2142 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
2143 "shl{w}\t{$src, $dst|$dst, $src}",
2144 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2146 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
2147 "shl{l}\t{$src, $dst|$dst, $src}",
2148 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2151 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
2153 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2154 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
2156 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2158 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2160 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2163 let Uses = [CL] in {
2164 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
2165 "shr{b}\t{%cl, $dst|$dst, CL}",
2166 [(set GR8:$dst, (srl GR8:$src, CL))]>;
2167 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
2168 "shr{w}\t{%cl, $dst|$dst, CL}",
2169 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
2170 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
2171 "shr{l}\t{%cl, $dst|$dst, CL}",
2172 [(set GR32:$dst, (srl GR32:$src, CL))]>;
2175 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2176 "shr{b}\t{$src2, $dst|$dst, $src2}",
2177 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2178 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2179 "shr{w}\t{$src2, $dst|$dst, $src2}",
2180 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2181 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2182 "shr{l}\t{$src2, $dst|$dst, $src2}",
2183 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2186 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2188 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2189 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2191 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2192 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2194 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2196 let isTwoAddress = 0 in {
2197 let Uses = [CL] in {
2198 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2199 "shr{b}\t{%cl, $dst|$dst, CL}",
2200 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2201 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2202 "shr{w}\t{%cl, $dst|$dst, CL}",
2203 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2205 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2206 "shr{l}\t{%cl, $dst|$dst, CL}",
2207 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2209 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2210 "shr{b}\t{$src, $dst|$dst, $src}",
2211 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2212 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2213 "shr{w}\t{$src, $dst|$dst, $src}",
2214 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2216 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2217 "shr{l}\t{$src, $dst|$dst, $src}",
2218 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2221 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2223 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2224 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2226 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2227 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2229 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2232 let Uses = [CL] in {
2233 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
2234 "sar{b}\t{%cl, $dst|$dst, CL}",
2235 [(set GR8:$dst, (sra GR8:$src, CL))]>;
2236 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
2237 "sar{w}\t{%cl, $dst|$dst, CL}",
2238 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
2239 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
2240 "sar{l}\t{%cl, $dst|$dst, CL}",
2241 [(set GR32:$dst, (sra GR32:$src, CL))]>;
2244 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2245 "sar{b}\t{$src2, $dst|$dst, $src2}",
2246 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2247 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2248 "sar{w}\t{$src2, $dst|$dst, $src2}",
2249 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2251 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2252 "sar{l}\t{$src2, $dst|$dst, $src2}",
2253 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2256 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2258 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2259 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2261 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2262 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2264 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2266 let isTwoAddress = 0 in {
2267 let Uses = [CL] in {
2268 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2269 "sar{b}\t{%cl, $dst|$dst, CL}",
2270 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2271 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2272 "sar{w}\t{%cl, $dst|$dst, CL}",
2273 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2274 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2275 "sar{l}\t{%cl, $dst|$dst, CL}",
2276 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2278 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2279 "sar{b}\t{$src, $dst|$dst, $src}",
2280 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2281 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2282 "sar{w}\t{$src, $dst|$dst, $src}",
2283 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2285 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2286 "sar{l}\t{$src, $dst|$dst, $src}",
2287 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2290 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2292 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2293 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2295 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2297 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2299 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2302 // Rotate instructions
2304 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2305 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2306 let Uses = [CL] in {
2307 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2308 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2310 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2311 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2313 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2314 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2315 let Uses = [CL] in {
2316 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2317 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2319 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2320 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2322 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2323 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2324 let Uses = [CL] in {
2325 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2326 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2328 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2329 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2331 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2332 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2333 let Uses = [CL] in {
2334 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2335 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2337 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2338 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2340 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2341 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2342 let Uses = [CL] in {
2343 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2344 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2346 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2347 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2349 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2350 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2351 let Uses = [CL] in {
2352 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2353 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2355 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2356 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2358 let isTwoAddress = 0 in {
2359 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
2360 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2361 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2362 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2363 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
2364 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2365 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2366 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2367 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
2368 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2369 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2370 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2371 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
2372 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2373 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2374 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2375 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
2376 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2377 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2378 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2379 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
2380 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2381 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2382 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2384 let Uses = [CL] in {
2385 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
2386 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2387 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
2388 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2389 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
2390 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2391 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
2392 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2393 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
2394 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2395 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
2396 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2400 // FIXME: provide shorter instructions when imm8 == 1
2401 let Uses = [CL] in {
2402 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
2403 "rol{b}\t{%cl, $dst|$dst, CL}",
2404 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
2405 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
2406 "rol{w}\t{%cl, $dst|$dst, CL}",
2407 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
2408 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
2409 "rol{l}\t{%cl, $dst|$dst, CL}",
2410 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2413 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2414 "rol{b}\t{$src2, $dst|$dst, $src2}",
2415 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2416 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2417 "rol{w}\t{$src2, $dst|$dst, $src2}",
2418 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2420 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2421 "rol{l}\t{$src2, $dst|$dst, $src2}",
2422 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2425 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2427 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2428 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2430 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2431 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2433 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2435 let isTwoAddress = 0 in {
2436 let Uses = [CL] in {
2437 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2438 "rol{b}\t{%cl, $dst|$dst, CL}",
2439 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2440 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2441 "rol{w}\t{%cl, $dst|$dst, CL}",
2442 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2443 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2444 "rol{l}\t{%cl, $dst|$dst, CL}",
2445 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2447 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2448 "rol{b}\t{$src, $dst|$dst, $src}",
2449 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2450 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2451 "rol{w}\t{$src, $dst|$dst, $src}",
2452 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2454 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2455 "rol{l}\t{$src, $dst|$dst, $src}",
2456 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2459 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2461 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2462 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2464 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2466 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2468 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2471 let Uses = [CL] in {
2472 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2473 "ror{b}\t{%cl, $dst|$dst, CL}",
2474 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2475 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2476 "ror{w}\t{%cl, $dst|$dst, CL}",
2477 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2478 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2479 "ror{l}\t{%cl, $dst|$dst, CL}",
2480 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2483 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2484 "ror{b}\t{$src2, $dst|$dst, $src2}",
2485 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2486 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2487 "ror{w}\t{$src2, $dst|$dst, $src2}",
2488 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2490 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2491 "ror{l}\t{$src2, $dst|$dst, $src2}",
2492 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2495 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2497 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2498 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2500 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2501 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2503 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2505 let isTwoAddress = 0 in {
2506 let Uses = [CL] in {
2507 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2508 "ror{b}\t{%cl, $dst|$dst, CL}",
2509 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2510 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2511 "ror{w}\t{%cl, $dst|$dst, CL}",
2512 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2513 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2514 "ror{l}\t{%cl, $dst|$dst, CL}",
2515 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2517 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2518 "ror{b}\t{$src, $dst|$dst, $src}",
2519 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2520 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2521 "ror{w}\t{$src, $dst|$dst, $src}",
2522 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2524 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2525 "ror{l}\t{$src, $dst|$dst, $src}",
2526 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2529 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2531 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2532 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2534 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2536 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2538 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2543 // Double shift instructions (generalizations of rotate)
2544 let Uses = [CL] in {
2545 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2546 (ins GR32:$src1, GR32:$src2),
2547 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2548 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2549 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2550 (ins GR32:$src1, GR32:$src2),
2551 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2552 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2553 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2554 (ins GR16:$src1, GR16:$src2),
2555 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2556 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2558 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2559 (ins GR16:$src1, GR16:$src2),
2560 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2561 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2565 let isCommutable = 1 in { // These instructions commute to each other.
2566 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2568 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2569 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2570 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2573 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2575 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2576 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2577 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2580 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2582 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2583 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2584 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2587 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2589 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2590 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2591 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2596 let isTwoAddress = 0 in {
2597 let Uses = [CL] in {
2598 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2599 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2600 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2602 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2603 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2604 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2607 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2608 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2609 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2610 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2611 (i8 imm:$src3)), addr:$dst)]>,
2613 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2614 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2615 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2616 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2617 (i8 imm:$src3)), addr:$dst)]>,
2620 let Uses = [CL] in {
2621 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2622 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2623 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2624 addr:$dst)]>, TB, OpSize;
2625 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2626 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2627 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2628 addr:$dst)]>, TB, OpSize;
2630 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2631 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2632 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2633 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2634 (i8 imm:$src3)), addr:$dst)]>,
2636 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2637 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2638 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2639 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2640 (i8 imm:$src3)), addr:$dst)]>,
2643 } // Defs = [EFLAGS]
2647 let Defs = [EFLAGS] in {
2648 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2649 // Register-Register Addition
2650 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2651 (ins GR8 :$src1, GR8 :$src2),
2652 "add{b}\t{$src2, $dst|$dst, $src2}",
2653 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
2654 (implicit EFLAGS)]>;
2656 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2657 // Register-Register Addition
2658 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2659 (ins GR16:$src1, GR16:$src2),
2660 "add{w}\t{$src2, $dst|$dst, $src2}",
2661 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2662 (implicit EFLAGS)]>, OpSize;
2663 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2664 (ins GR32:$src1, GR32:$src2),
2665 "add{l}\t{$src2, $dst|$dst, $src2}",
2666 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2667 (implicit EFLAGS)]>;
2668 } // end isConvertibleToThreeAddress
2669 } // end isCommutable
2671 // Register-Memory Addition
2672 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2673 (ins GR8 :$src1, i8mem :$src2),
2674 "add{b}\t{$src2, $dst|$dst, $src2}",
2675 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2676 (implicit EFLAGS)]>;
2677 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2678 (ins GR16:$src1, i16mem:$src2),
2679 "add{w}\t{$src2, $dst|$dst, $src2}",
2680 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2681 (implicit EFLAGS)]>, OpSize;
2682 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2683 (ins GR32:$src1, i32mem:$src2),
2684 "add{l}\t{$src2, $dst|$dst, $src2}",
2685 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2686 (implicit EFLAGS)]>;
2688 // Register-Register Addition - Equivalent to the normal rr forms (ADD8rr,
2689 // ADD16rr, and ADD32rr), but differently encoded.
2690 def ADD8mrmrr: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2691 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2692 def ADD16mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2693 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2694 def ADD32mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2695 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2697 // Register-Integer Addition
2698 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2699 "add{b}\t{$src2, $dst|$dst, $src2}",
2700 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2701 (implicit EFLAGS)]>;
2703 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2704 // Register-Integer Addition
2705 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2706 (ins GR16:$src1, i16imm:$src2),
2707 "add{w}\t{$src2, $dst|$dst, $src2}",
2708 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2709 (implicit EFLAGS)]>, OpSize;
2710 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2711 (ins GR32:$src1, i32imm:$src2),
2712 "add{l}\t{$src2, $dst|$dst, $src2}",
2713 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2714 (implicit EFLAGS)]>;
2715 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2716 (ins GR16:$src1, i16i8imm:$src2),
2717 "add{w}\t{$src2, $dst|$dst, $src2}",
2718 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2719 (implicit EFLAGS)]>, OpSize;
2720 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2721 (ins GR32:$src1, i32i8imm:$src2),
2722 "add{l}\t{$src2, $dst|$dst, $src2}",
2723 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2724 (implicit EFLAGS)]>;
2727 let isTwoAddress = 0 in {
2728 // Memory-Register Addition
2729 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2730 "add{b}\t{$src2, $dst|$dst, $src2}",
2731 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2732 (implicit EFLAGS)]>;
2733 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2734 "add{w}\t{$src2, $dst|$dst, $src2}",
2735 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2736 (implicit EFLAGS)]>, OpSize;
2737 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2738 "add{l}\t{$src2, $dst|$dst, $src2}",
2739 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2740 (implicit EFLAGS)]>;
2741 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2742 "add{b}\t{$src2, $dst|$dst, $src2}",
2743 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2744 (implicit EFLAGS)]>;
2745 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2746 "add{w}\t{$src2, $dst|$dst, $src2}",
2747 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2748 (implicit EFLAGS)]>, OpSize;
2749 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2750 "add{l}\t{$src2, $dst|$dst, $src2}",
2751 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2752 (implicit EFLAGS)]>;
2753 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2754 "add{w}\t{$src2, $dst|$dst, $src2}",
2755 [(store (add (load addr:$dst), i16immSExt8:$src2),
2757 (implicit EFLAGS)]>, OpSize;
2758 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2759 "add{l}\t{$src2, $dst|$dst, $src2}",
2760 [(store (add (load addr:$dst), i32immSExt8:$src2),
2762 (implicit EFLAGS)]>;
2765 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2766 "add{b}\t{$src, %al|%al, $src}", []>;
2767 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2768 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2769 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2770 "add{l}\t{$src, %eax|%eax, $src}", []>;
2773 let Uses = [EFLAGS] in {
2774 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2775 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2776 "adc{b}\t{$src2, $dst|$dst, $src2}",
2777 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2778 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2779 (ins GR16:$src1, GR16:$src2),
2780 "adc{w}\t{$src2, $dst|$dst, $src2}",
2781 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2782 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2783 (ins GR32:$src1, GR32:$src2),
2784 "adc{l}\t{$src2, $dst|$dst, $src2}",
2785 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2788 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2789 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2790 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2791 (ins GR16:$src1, GR16:$src2),
2792 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2793 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2794 (ins GR32:$src1, GR32:$src2),
2795 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2797 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2798 (ins GR8:$src1, i8mem:$src2),
2799 "adc{b}\t{$src2, $dst|$dst, $src2}",
2800 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2801 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2802 (ins GR16:$src1, i16mem:$src2),
2803 "adc{w}\t{$src2, $dst|$dst, $src2}",
2804 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2806 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2807 (ins GR32:$src1, i32mem:$src2),
2808 "adc{l}\t{$src2, $dst|$dst, $src2}",
2809 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2810 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2811 "adc{b}\t{$src2, $dst|$dst, $src2}",
2812 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2813 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2814 (ins GR16:$src1, i16imm:$src2),
2815 "adc{w}\t{$src2, $dst|$dst, $src2}",
2816 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2817 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2818 (ins GR16:$src1, i16i8imm:$src2),
2819 "adc{w}\t{$src2, $dst|$dst, $src2}",
2820 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2822 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2823 (ins GR32:$src1, i32imm:$src2),
2824 "adc{l}\t{$src2, $dst|$dst, $src2}",
2825 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2826 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2827 (ins GR32:$src1, i32i8imm:$src2),
2828 "adc{l}\t{$src2, $dst|$dst, $src2}",
2829 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2831 let isTwoAddress = 0 in {
2832 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2833 "adc{b}\t{$src2, $dst|$dst, $src2}",
2834 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2835 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2836 "adc{w}\t{$src2, $dst|$dst, $src2}",
2837 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2839 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2840 "adc{l}\t{$src2, $dst|$dst, $src2}",
2841 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2842 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2843 "adc{b}\t{$src2, $dst|$dst, $src2}",
2844 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2845 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2846 "adc{w}\t{$src2, $dst|$dst, $src2}",
2847 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2849 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2850 "adc{w}\t{$src2, $dst|$dst, $src2}",
2851 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2853 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2854 "adc{l}\t{$src2, $dst|$dst, $src2}",
2855 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2856 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2857 "adc{l}\t{$src2, $dst|$dst, $src2}",
2858 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2860 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2861 "adc{b}\t{$src, %al|%al, $src}", []>;
2862 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2863 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2864 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2865 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2867 } // Uses = [EFLAGS]
2869 // Register-Register Subtraction
2870 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2871 "sub{b}\t{$src2, $dst|$dst, $src2}",
2872 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2873 (implicit EFLAGS)]>;
2874 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2875 "sub{w}\t{$src2, $dst|$dst, $src2}",
2876 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2877 (implicit EFLAGS)]>, OpSize;
2878 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2879 "sub{l}\t{$src2, $dst|$dst, $src2}",
2880 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2881 (implicit EFLAGS)]>;
2883 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2884 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
2885 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
2886 (ins GR16:$src1, GR16:$src2),
2887 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2888 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
2889 (ins GR32:$src1, GR32:$src2),
2890 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
2892 // Register-Memory Subtraction
2893 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2894 (ins GR8 :$src1, i8mem :$src2),
2895 "sub{b}\t{$src2, $dst|$dst, $src2}",
2896 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2897 (implicit EFLAGS)]>;
2898 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2899 (ins GR16:$src1, i16mem:$src2),
2900 "sub{w}\t{$src2, $dst|$dst, $src2}",
2901 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2902 (implicit EFLAGS)]>, OpSize;
2903 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2904 (ins GR32:$src1, i32mem:$src2),
2905 "sub{l}\t{$src2, $dst|$dst, $src2}",
2906 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2907 (implicit EFLAGS)]>;
2909 // Register-Integer Subtraction
2910 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2911 (ins GR8:$src1, i8imm:$src2),
2912 "sub{b}\t{$src2, $dst|$dst, $src2}",
2913 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2914 (implicit EFLAGS)]>;
2915 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2916 (ins GR16:$src1, i16imm:$src2),
2917 "sub{w}\t{$src2, $dst|$dst, $src2}",
2918 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2919 (implicit EFLAGS)]>, OpSize;
2920 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2921 (ins GR32:$src1, i32imm:$src2),
2922 "sub{l}\t{$src2, $dst|$dst, $src2}",
2923 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2924 (implicit EFLAGS)]>;
2925 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2926 (ins GR16:$src1, i16i8imm:$src2),
2927 "sub{w}\t{$src2, $dst|$dst, $src2}",
2928 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2929 (implicit EFLAGS)]>, OpSize;
2930 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2931 (ins GR32:$src1, i32i8imm:$src2),
2932 "sub{l}\t{$src2, $dst|$dst, $src2}",
2933 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2934 (implicit EFLAGS)]>;
2936 let isTwoAddress = 0 in {
2937 // Memory-Register Subtraction
2938 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2939 "sub{b}\t{$src2, $dst|$dst, $src2}",
2940 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2941 (implicit EFLAGS)]>;
2942 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2943 "sub{w}\t{$src2, $dst|$dst, $src2}",
2944 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2945 (implicit EFLAGS)]>, OpSize;
2946 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2947 "sub{l}\t{$src2, $dst|$dst, $src2}",
2948 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2949 (implicit EFLAGS)]>;
2951 // Memory-Integer Subtraction
2952 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2953 "sub{b}\t{$src2, $dst|$dst, $src2}",
2954 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2955 (implicit EFLAGS)]>;
2956 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2957 "sub{w}\t{$src2, $dst|$dst, $src2}",
2958 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2959 (implicit EFLAGS)]>, OpSize;
2960 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2961 "sub{l}\t{$src2, $dst|$dst, $src2}",
2962 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2963 (implicit EFLAGS)]>;
2964 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2965 "sub{w}\t{$src2, $dst|$dst, $src2}",
2966 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2968 (implicit EFLAGS)]>, OpSize;
2969 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2970 "sub{l}\t{$src2, $dst|$dst, $src2}",
2971 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2973 (implicit EFLAGS)]>;
2975 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
2976 "sub{b}\t{$src, %al|%al, $src}", []>;
2977 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
2978 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2979 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
2980 "sub{l}\t{$src, %eax|%eax, $src}", []>;
2983 let Uses = [EFLAGS] in {
2984 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
2985 (ins GR8:$src1, GR8:$src2),
2986 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2987 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
2988 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
2989 (ins GR16:$src1, GR16:$src2),
2990 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2991 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
2992 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
2993 (ins GR32:$src1, GR32:$src2),
2994 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2995 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2997 let isTwoAddress = 0 in {
2998 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2999 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3000 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
3001 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3002 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3003 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
3005 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3006 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3007 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
3008 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
3009 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3010 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
3011 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
3012 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3013 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
3015 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3016 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3017 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
3019 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
3020 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3021 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
3022 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3023 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3024 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
3026 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
3027 "sbb{b}\t{$src, %al|%al, $src}", []>;
3028 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
3029 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3030 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
3031 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
3034 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3035 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
3036 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
3037 (ins GR16:$src1, GR16:$src2),
3038 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3039 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
3040 (ins GR32:$src1, GR32:$src2),
3041 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
3043 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
3044 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3045 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
3046 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
3047 (ins GR16:$src1, i16mem:$src2),
3048 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3049 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
3051 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
3052 (ins GR32:$src1, i32mem:$src2),
3053 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3054 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
3055 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
3056 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3057 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
3058 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
3059 (ins GR16:$src1, i16imm:$src2),
3060 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3061 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
3062 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
3063 (ins GR16:$src1, i16i8imm:$src2),
3064 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3065 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
3067 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
3068 (ins GR32:$src1, i32imm:$src2),
3069 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3070 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
3071 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
3072 (ins GR32:$src1, i32i8imm:$src2),
3073 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3074 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
3075 } // Uses = [EFLAGS]
3076 } // Defs = [EFLAGS]
3078 let Defs = [EFLAGS] in {
3079 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
3080 // Register-Register Signed Integer Multiply
3081 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3082 "imul{w}\t{$src2, $dst|$dst, $src2}",
3083 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
3084 (implicit EFLAGS)]>, TB, OpSize;
3085 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3086 "imul{l}\t{$src2, $dst|$dst, $src2}",
3087 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
3088 (implicit EFLAGS)]>, TB;
3091 // Register-Memory Signed Integer Multiply
3092 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
3093 (ins GR16:$src1, i16mem:$src2),
3094 "imul{w}\t{$src2, $dst|$dst, $src2}",
3095 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
3096 (implicit EFLAGS)]>, TB, OpSize;
3097 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
3098 (ins GR32:$src1, i32mem:$src2),
3099 "imul{l}\t{$src2, $dst|$dst, $src2}",
3100 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
3101 (implicit EFLAGS)]>, TB;
3102 } // Defs = [EFLAGS]
3103 } // end Two Address instructions
3105 // Suprisingly enough, these are not two address instructions!
3106 let Defs = [EFLAGS] in {
3107 // Register-Integer Signed Integer Multiply
3108 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
3109 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
3110 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3111 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
3112 (implicit EFLAGS)]>, OpSize;
3113 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
3114 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
3115 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3116 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
3117 (implicit EFLAGS)]>;
3118 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
3119 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
3120 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3121 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
3122 (implicit EFLAGS)]>, OpSize;
3123 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
3124 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
3125 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3126 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
3127 (implicit EFLAGS)]>;
3129 // Memory-Integer Signed Integer Multiply
3130 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
3131 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
3132 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3133 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
3134 (implicit EFLAGS)]>, OpSize;
3135 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
3136 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
3137 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3138 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
3139 (implicit EFLAGS)]>;
3140 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
3141 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
3142 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3143 [(set GR16:$dst, (mul (load addr:$src1),
3144 i16immSExt8:$src2)),
3145 (implicit EFLAGS)]>, OpSize;
3146 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
3147 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
3148 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3149 [(set GR32:$dst, (mul (load addr:$src1),
3150 i32immSExt8:$src2)),
3151 (implicit EFLAGS)]>;
3152 } // Defs = [EFLAGS]
3154 //===----------------------------------------------------------------------===//
3155 // Test instructions are just like AND, except they don't generate a result.
3157 let Defs = [EFLAGS] in {
3158 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
3159 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
3160 "test{b}\t{$src2, $src1|$src1, $src2}",
3161 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
3162 (implicit EFLAGS)]>;
3163 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3164 "test{w}\t{$src2, $src1|$src1, $src2}",
3165 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
3166 (implicit EFLAGS)]>,
3168 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3169 "test{l}\t{$src2, $src1|$src1, $src2}",
3170 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
3171 (implicit EFLAGS)]>;
3174 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
3175 "test{b}\t{$src, %al|%al, $src}", []>;
3176 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
3177 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3178 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
3179 "test{l}\t{$src, %eax|%eax, $src}", []>;
3181 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
3182 "test{b}\t{$src2, $src1|$src1, $src2}",
3183 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
3184 (implicit EFLAGS)]>;
3185 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
3186 "test{w}\t{$src2, $src1|$src1, $src2}",
3187 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
3188 (implicit EFLAGS)]>, OpSize;
3189 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
3190 "test{l}\t{$src2, $src1|$src1, $src2}",
3191 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
3192 (implicit EFLAGS)]>;
3194 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
3195 (outs), (ins GR8:$src1, i8imm:$src2),
3196 "test{b}\t{$src2, $src1|$src1, $src2}",
3197 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
3198 (implicit EFLAGS)]>;
3199 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
3200 (outs), (ins GR16:$src1, i16imm:$src2),
3201 "test{w}\t{$src2, $src1|$src1, $src2}",
3202 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
3203 (implicit EFLAGS)]>, OpSize;
3204 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
3205 (outs), (ins GR32:$src1, i32imm:$src2),
3206 "test{l}\t{$src2, $src1|$src1, $src2}",
3207 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
3208 (implicit EFLAGS)]>;
3210 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
3211 (outs), (ins i8mem:$src1, i8imm:$src2),
3212 "test{b}\t{$src2, $src1|$src1, $src2}",
3213 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
3214 (implicit EFLAGS)]>;
3215 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3216 (outs), (ins i16mem:$src1, i16imm:$src2),
3217 "test{w}\t{$src2, $src1|$src1, $src2}",
3218 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
3219 (implicit EFLAGS)]>, OpSize;
3220 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3221 (outs), (ins i32mem:$src1, i32imm:$src2),
3222 "test{l}\t{$src2, $src1|$src1, $src2}",
3223 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
3224 (implicit EFLAGS)]>;
3225 } // Defs = [EFLAGS]
3228 // Condition code ops, incl. set if equal/not equal/...
3229 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3230 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3231 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3232 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3234 let Uses = [EFLAGS] in {
3235 // Use sbb to materialize carry bit.
3236 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
3237 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
3238 // However, Pat<> can't replicate the destination reg into the inputs of the
3240 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
3242 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
3243 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3244 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
3245 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
3247 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
3248 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3251 def SETEr : I<0x94, MRM0r,
3252 (outs GR8 :$dst), (ins),
3254 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3256 def SETEm : I<0x94, MRM0m,
3257 (outs), (ins i8mem:$dst),
3259 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3262 def SETNEr : I<0x95, MRM0r,
3263 (outs GR8 :$dst), (ins),
3265 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3267 def SETNEm : I<0x95, MRM0m,
3268 (outs), (ins i8mem:$dst),
3270 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3273 def SETLr : I<0x9C, MRM0r,
3274 (outs GR8 :$dst), (ins),
3276 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3277 TB; // GR8 = < signed
3278 def SETLm : I<0x9C, MRM0m,
3279 (outs), (ins i8mem:$dst),
3281 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3282 TB; // [mem8] = < signed
3284 def SETGEr : I<0x9D, MRM0r,
3285 (outs GR8 :$dst), (ins),
3287 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3288 TB; // GR8 = >= signed
3289 def SETGEm : I<0x9D, MRM0m,
3290 (outs), (ins i8mem:$dst),
3292 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3293 TB; // [mem8] = >= signed
3295 def SETLEr : I<0x9E, MRM0r,
3296 (outs GR8 :$dst), (ins),
3298 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3299 TB; // GR8 = <= signed
3300 def SETLEm : I<0x9E, MRM0m,
3301 (outs), (ins i8mem:$dst),
3303 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3304 TB; // [mem8] = <= signed
3306 def SETGr : I<0x9F, MRM0r,
3307 (outs GR8 :$dst), (ins),
3309 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3310 TB; // GR8 = > signed
3311 def SETGm : I<0x9F, MRM0m,
3312 (outs), (ins i8mem:$dst),
3314 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3315 TB; // [mem8] = > signed
3317 def SETBr : I<0x92, MRM0r,
3318 (outs GR8 :$dst), (ins),
3320 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3321 TB; // GR8 = < unsign
3322 def SETBm : I<0x92, MRM0m,
3323 (outs), (ins i8mem:$dst),
3325 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3326 TB; // [mem8] = < unsign
3328 def SETAEr : I<0x93, MRM0r,
3329 (outs GR8 :$dst), (ins),
3331 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3332 TB; // GR8 = >= unsign
3333 def SETAEm : I<0x93, MRM0m,
3334 (outs), (ins i8mem:$dst),
3336 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3337 TB; // [mem8] = >= unsign
3339 def SETBEr : I<0x96, MRM0r,
3340 (outs GR8 :$dst), (ins),
3342 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3343 TB; // GR8 = <= unsign
3344 def SETBEm : I<0x96, MRM0m,
3345 (outs), (ins i8mem:$dst),
3347 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3348 TB; // [mem8] = <= unsign
3350 def SETAr : I<0x97, MRM0r,
3351 (outs GR8 :$dst), (ins),
3353 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3354 TB; // GR8 = > signed
3355 def SETAm : I<0x97, MRM0m,
3356 (outs), (ins i8mem:$dst),
3358 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3359 TB; // [mem8] = > signed
3361 def SETSr : I<0x98, MRM0r,
3362 (outs GR8 :$dst), (ins),
3364 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3365 TB; // GR8 = <sign bit>
3366 def SETSm : I<0x98, MRM0m,
3367 (outs), (ins i8mem:$dst),
3369 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3370 TB; // [mem8] = <sign bit>
3371 def SETNSr : I<0x99, MRM0r,
3372 (outs GR8 :$dst), (ins),
3374 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3375 TB; // GR8 = !<sign bit>
3376 def SETNSm : I<0x99, MRM0m,
3377 (outs), (ins i8mem:$dst),
3379 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3380 TB; // [mem8] = !<sign bit>
3382 def SETPr : I<0x9A, MRM0r,
3383 (outs GR8 :$dst), (ins),
3385 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3387 def SETPm : I<0x9A, MRM0m,
3388 (outs), (ins i8mem:$dst),
3390 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3391 TB; // [mem8] = parity
3392 def SETNPr : I<0x9B, MRM0r,
3393 (outs GR8 :$dst), (ins),
3395 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3396 TB; // GR8 = not parity
3397 def SETNPm : I<0x9B, MRM0m,
3398 (outs), (ins i8mem:$dst),
3400 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3401 TB; // [mem8] = not parity
3403 def SETOr : I<0x90, MRM0r,
3404 (outs GR8 :$dst), (ins),
3406 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3407 TB; // GR8 = overflow
3408 def SETOm : I<0x90, MRM0m,
3409 (outs), (ins i8mem:$dst),
3411 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3412 TB; // [mem8] = overflow
3413 def SETNOr : I<0x91, MRM0r,
3414 (outs GR8 :$dst), (ins),
3416 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3417 TB; // GR8 = not overflow
3418 def SETNOm : I<0x91, MRM0m,
3419 (outs), (ins i8mem:$dst),
3421 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3422 TB; // [mem8] = not overflow
3423 } // Uses = [EFLAGS]
3426 // Integer comparisons
3427 let Defs = [EFLAGS] in {
3428 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3429 "cmp{b}\t{$src, %al|%al, $src}", []>;
3430 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3431 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3432 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3433 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3435 def CMP8rr : I<0x38, MRMDestReg,
3436 (outs), (ins GR8 :$src1, GR8 :$src2),
3437 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3438 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
3439 def CMP16rr : I<0x39, MRMDestReg,
3440 (outs), (ins GR16:$src1, GR16:$src2),
3441 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3442 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
3443 def CMP32rr : I<0x39, MRMDestReg,
3444 (outs), (ins GR32:$src1, GR32:$src2),
3445 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3446 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
3447 def CMP8mr : I<0x38, MRMDestMem,
3448 (outs), (ins i8mem :$src1, GR8 :$src2),
3449 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3450 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
3451 (implicit EFLAGS)]>;
3452 def CMP16mr : I<0x39, MRMDestMem,
3453 (outs), (ins i16mem:$src1, GR16:$src2),
3454 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3455 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
3456 (implicit EFLAGS)]>, OpSize;
3457 def CMP32mr : I<0x39, MRMDestMem,
3458 (outs), (ins i32mem:$src1, GR32:$src2),
3459 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3460 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
3461 (implicit EFLAGS)]>;
3462 def CMP8rm : I<0x3A, MRMSrcMem,
3463 (outs), (ins GR8 :$src1, i8mem :$src2),
3464 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3465 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
3466 (implicit EFLAGS)]>;
3467 def CMP16rm : I<0x3B, MRMSrcMem,
3468 (outs), (ins GR16:$src1, i16mem:$src2),
3469 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3470 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
3471 (implicit EFLAGS)]>, OpSize;
3472 def CMP32rm : I<0x3B, MRMSrcMem,
3473 (outs), (ins GR32:$src1, i32mem:$src2),
3474 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3475 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
3476 (implicit EFLAGS)]>;
3477 def CMP8mrmrr : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3478 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3479 def CMP16mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3480 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3481 def CMP32mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3482 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3483 def CMP8ri : Ii8<0x80, MRM7r,
3484 (outs), (ins GR8:$src1, i8imm:$src2),
3485 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3486 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
3487 def CMP16ri : Ii16<0x81, MRM7r,
3488 (outs), (ins GR16:$src1, i16imm:$src2),
3489 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3490 [(X86cmp GR16:$src1, imm:$src2),
3491 (implicit EFLAGS)]>, OpSize;
3492 def CMP32ri : Ii32<0x81, MRM7r,
3493 (outs), (ins GR32:$src1, i32imm:$src2),
3494 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3495 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
3496 def CMP8mi : Ii8 <0x80, MRM7m,
3497 (outs), (ins i8mem :$src1, i8imm :$src2),
3498 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3499 [(X86cmp (loadi8 addr:$src1), imm:$src2),
3500 (implicit EFLAGS)]>;
3501 def CMP16mi : Ii16<0x81, MRM7m,
3502 (outs), (ins i16mem:$src1, i16imm:$src2),
3503 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3504 [(X86cmp (loadi16 addr:$src1), imm:$src2),
3505 (implicit EFLAGS)]>, OpSize;
3506 def CMP32mi : Ii32<0x81, MRM7m,
3507 (outs), (ins i32mem:$src1, i32imm:$src2),
3508 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3509 [(X86cmp (loadi32 addr:$src1), imm:$src2),
3510 (implicit EFLAGS)]>;
3511 def CMP16ri8 : Ii8<0x83, MRM7r,
3512 (outs), (ins GR16:$src1, i16i8imm:$src2),
3513 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3514 [(X86cmp GR16:$src1, i16immSExt8:$src2),
3515 (implicit EFLAGS)]>, OpSize;
3516 def CMP16mi8 : Ii8<0x83, MRM7m,
3517 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3518 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3519 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
3520 (implicit EFLAGS)]>, OpSize;
3521 def CMP32mi8 : Ii8<0x83, MRM7m,
3522 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3523 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3524 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
3525 (implicit EFLAGS)]>;
3526 def CMP32ri8 : Ii8<0x83, MRM7r,
3527 (outs), (ins GR32:$src1, i32i8imm:$src2),
3528 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3529 [(X86cmp GR32:$src1, i32immSExt8:$src2),
3530 (implicit EFLAGS)]>;
3531 } // Defs = [EFLAGS]
3534 // TODO: BTC, BTR, and BTS
3535 let Defs = [EFLAGS] in {
3536 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3537 "bt{w}\t{$src2, $src1|$src1, $src2}",
3538 [(X86bt GR16:$src1, GR16:$src2),
3539 (implicit EFLAGS)]>, OpSize, TB;
3540 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3541 "bt{l}\t{$src2, $src1|$src1, $src2}",
3542 [(X86bt GR32:$src1, GR32:$src2),
3543 (implicit EFLAGS)]>, TB;
3545 // Unlike with the register+register form, the memory+register form of the
3546 // bt instruction does not ignore the high bits of the index. From ISel's
3547 // perspective, this is pretty bizarre. Make these instructions disassembly
3550 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3551 "bt{w}\t{$src2, $src1|$src1, $src2}",
3552 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3553 // (implicit EFLAGS)]
3555 >, OpSize, TB, Requires<[FastBTMem]>;
3556 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3557 "bt{l}\t{$src2, $src1|$src1, $src2}",
3558 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3559 // (implicit EFLAGS)]
3561 >, TB, Requires<[FastBTMem]>;
3563 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3564 "bt{w}\t{$src2, $src1|$src1, $src2}",
3565 [(X86bt GR16:$src1, i16immSExt8:$src2),
3566 (implicit EFLAGS)]>, OpSize, TB;
3567 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3568 "bt{l}\t{$src2, $src1|$src1, $src2}",
3569 [(X86bt GR32:$src1, i32immSExt8:$src2),
3570 (implicit EFLAGS)]>, TB;
3571 // Note that these instructions don't need FastBTMem because that
3572 // only applies when the other operand is in a register. When it's
3573 // an immediate, bt is still fast.
3574 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3575 "bt{w}\t{$src2, $src1|$src1, $src2}",
3576 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
3577 (implicit EFLAGS)]>, OpSize, TB;
3578 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3579 "bt{l}\t{$src2, $src1|$src1, $src2}",
3580 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
3581 (implicit EFLAGS)]>, TB;
3583 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3584 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3585 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3586 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3587 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3588 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3589 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3590 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3591 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3592 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3593 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3594 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3595 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3596 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3597 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3598 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3600 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3601 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3602 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3603 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3604 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3605 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3606 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3607 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3608 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3609 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3610 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3611 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3612 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3613 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3614 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3615 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3617 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3618 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3619 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3620 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3621 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3622 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3623 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3624 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3625 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3626 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3627 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3628 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3629 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3630 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3631 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3632 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3633 } // Defs = [EFLAGS]
3635 // Sign/Zero extenders
3636 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3637 // of the register here. This has a smaller encoding and avoids a
3638 // partial-register update. Actual movsbw included for the disassembler.
3639 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3640 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3641 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3642 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3643 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3644 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3645 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3646 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3647 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3648 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3649 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3650 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3651 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3652 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3653 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3654 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3655 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3656 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3657 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3658 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3660 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3661 // of the register here. This has a smaller encoding and avoids a
3662 // partial-register update. Actual movzbw included for the disassembler.
3663 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3664 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3665 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3666 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3667 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3668 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3669 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3670 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3671 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3672 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3673 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3674 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3675 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3676 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3677 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3678 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3679 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3680 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3681 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3682 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3684 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
3685 // except that they use GR32_NOREX for the output operand register class
3686 // instead of GR32. This allows them to operate on h registers on x86-64.
3687 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3688 (outs GR32_NOREX:$dst), (ins GR8:$src),
3689 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3692 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3693 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3694 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3697 let neverHasSideEffects = 1 in {
3698 let Defs = [AX], Uses = [AL] in
3699 def CBW : I<0x98, RawFrm, (outs), (ins),
3700 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3701 let Defs = [EAX], Uses = [AX] in
3702 def CWDE : I<0x98, RawFrm, (outs), (ins),
3703 "{cwtl|cwde}", []>; // EAX = signext(AX)
3705 let Defs = [AX,DX], Uses = [AX] in
3706 def CWD : I<0x99, RawFrm, (outs), (ins),
3707 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3708 let Defs = [EAX,EDX], Uses = [EAX] in
3709 def CDQ : I<0x99, RawFrm, (outs), (ins),
3710 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3713 //===----------------------------------------------------------------------===//
3714 // Alias Instructions
3715 //===----------------------------------------------------------------------===//
3717 // Alias instructions that map movr0 to xor.
3718 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3719 // FIXME: Set encoding to pseudo.
3720 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3721 isCodeGenOnly = 1 in {
3722 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
3723 [(set GR8:$dst, 0)]>;
3725 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
3726 // encoding and avoids a partial-register update sometimes, but doing so
3727 // at isel time interferes with rematerialization in the current register
3728 // allocator. For now, this is rewritten when the instruction is lowered
3730 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3732 [(set GR16:$dst, 0)]>, OpSize;
3734 // FIXME: Set encoding to pseudo.
3735 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
3736 [(set GR32:$dst, 0)]>;
3739 //===----------------------------------------------------------------------===//
3740 // Thread Local Storage Instructions
3743 // All calls clobber the non-callee saved registers. ESP is marked as
3744 // a use to prevent stack-pointer assignments that appear immediately
3745 // before calls from potentially appearing dead.
3746 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3747 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3748 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3749 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3751 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3752 "leal\t$sym, %eax; "
3753 "call\t___tls_get_addr@PLT",
3754 [(X86tlsaddr tls32addr:$sym)]>,
3755 Requires<[In32BitMode]>;
3757 let AddedComplexity = 5, isCodeGenOnly = 1 in
3758 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3759 "movl\t%gs:$src, $dst",
3760 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3762 let AddedComplexity = 5, isCodeGenOnly = 1 in
3763 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3764 "movl\t%fs:$src, $dst",
3765 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3767 //===----------------------------------------------------------------------===//
3768 // EH Pseudo Instructions
3770 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3771 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3772 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3773 "ret\t#eh_return, addr: $addr",
3774 [(X86ehret GR32:$addr)]>;
3778 //===----------------------------------------------------------------------===//
3782 // Atomic swap. These are just normal xchg instructions. But since a memory
3783 // operand is referenced, the atomicity is ensured.
3784 let Constraints = "$val = $dst" in {
3785 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3786 (ins GR32:$val, i32mem:$ptr),
3787 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3788 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3789 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3790 (ins GR16:$val, i16mem:$ptr),
3791 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3792 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3794 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3795 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3796 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3798 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3799 "xchg{l}\t{$val, $src|$src, $val}", []>;
3800 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3801 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3802 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3803 "xchg{b}\t{$val, $src|$src, $val}", []>;
3806 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3807 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3808 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3809 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
3811 // Atomic compare and swap.
3812 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3813 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3815 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3816 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3818 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3819 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
3822 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3825 let Defs = [AX, EFLAGS], Uses = [AX] in {
3826 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3828 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3829 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3831 let Defs = [AL, EFLAGS], Uses = [AL] in {
3832 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3834 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3835 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3838 // Atomic exchange and add
3839 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3840 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
3842 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3843 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3845 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
3847 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3848 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3850 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3852 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3853 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3857 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3858 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3859 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3860 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3861 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3862 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3864 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3865 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3866 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3867 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3868 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3869 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3871 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3872 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3873 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3874 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3875 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3876 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3878 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3879 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3880 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3881 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3882 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3883 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3885 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
3886 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
3887 "cmpxchg8b\t$dst", []>, TB;
3889 // Optimized codegen when the non-memory output is not used.
3890 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3891 let Defs = [EFLAGS] in {
3892 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3894 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3895 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3897 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3898 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3900 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3901 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3903 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3904 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3906 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3907 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3909 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3910 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3912 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3913 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3915 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3917 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3919 "inc{b}\t$dst", []>, LOCK;
3920 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3922 "inc{w}\t$dst", []>, OpSize, LOCK;
3923 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3925 "inc{l}\t$dst", []>, LOCK;
3927 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3929 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3930 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3932 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3933 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3935 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3936 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3938 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3939 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3941 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3942 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3944 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3945 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3947 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3948 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3950 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3952 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3954 "dec{b}\t$dst", []>, LOCK;
3955 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3957 "dec{w}\t$dst", []>, OpSize, LOCK;
3958 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3960 "dec{l}\t$dst", []>, LOCK;
3963 // Atomic exchange, and, or, xor
3964 let Constraints = "$val = $dst", Defs = [EFLAGS],
3965 usesCustomInserter = 1 in {
3966 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3967 "#ATOMAND32 PSEUDO!",
3968 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3969 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3970 "#ATOMOR32 PSEUDO!",
3971 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
3972 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3973 "#ATOMXOR32 PSEUDO!",
3974 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
3975 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3976 "#ATOMNAND32 PSEUDO!",
3977 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
3978 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3979 "#ATOMMIN32 PSEUDO!",
3980 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
3981 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3982 "#ATOMMAX32 PSEUDO!",
3983 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
3984 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3985 "#ATOMUMIN32 PSEUDO!",
3986 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
3987 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3988 "#ATOMUMAX32 PSEUDO!",
3989 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
3991 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3992 "#ATOMAND16 PSEUDO!",
3993 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
3994 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3995 "#ATOMOR16 PSEUDO!",
3996 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
3997 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3998 "#ATOMXOR16 PSEUDO!",
3999 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
4000 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4001 "#ATOMNAND16 PSEUDO!",
4002 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
4003 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
4004 "#ATOMMIN16 PSEUDO!",
4005 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
4006 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4007 "#ATOMMAX16 PSEUDO!",
4008 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
4009 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4010 "#ATOMUMIN16 PSEUDO!",
4011 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
4012 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4013 "#ATOMUMAX16 PSEUDO!",
4014 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
4016 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4017 "#ATOMAND8 PSEUDO!",
4018 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
4019 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4021 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
4022 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4023 "#ATOMXOR8 PSEUDO!",
4024 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
4025 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4026 "#ATOMNAND8 PSEUDO!",
4027 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
4030 let Constraints = "$val1 = $dst1, $val2 = $dst2",
4031 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
4032 Uses = [EAX, EBX, ECX, EDX],
4033 mayLoad = 1, mayStore = 1,
4034 usesCustomInserter = 1 in {
4035 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4036 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4037 "#ATOMAND6432 PSEUDO!", []>;
4038 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4039 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4040 "#ATOMOR6432 PSEUDO!", []>;
4041 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4042 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4043 "#ATOMXOR6432 PSEUDO!", []>;
4044 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4045 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4046 "#ATOMNAND6432 PSEUDO!", []>;
4047 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4048 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4049 "#ATOMADD6432 PSEUDO!", []>;
4050 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4051 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4052 "#ATOMSUB6432 PSEUDO!", []>;
4053 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4054 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4055 "#ATOMSWAP6432 PSEUDO!", []>;
4058 // Segmentation support instructions.
4060 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4061 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4062 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4063 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4065 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
4066 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
4067 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4068 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4069 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4071 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4072 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4073 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4074 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4075 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4076 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4077 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4078 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4080 def INVLPG : I<0x01, RawFrm, (outs), (ins), "invlpg", []>, TB;
4082 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
4083 "str{w}\t{$dst}", []>, TB;
4084 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
4085 "str{w}\t{$dst}", []>, TB;
4086 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
4087 "ltr{w}\t{$src}", []>, TB;
4088 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
4089 "ltr{w}\t{$src}", []>, TB;
4091 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
4092 "push{w}\t%fs", []>, OpSize, TB;
4093 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
4094 "push{l}\t%fs", []>, TB;
4095 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
4096 "push{w}\t%gs", []>, OpSize, TB;
4097 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
4098 "push{l}\t%gs", []>, TB;
4100 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
4101 "pop{w}\t%fs", []>, OpSize, TB;
4102 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
4103 "pop{l}\t%fs", []>, TB;
4104 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
4105 "pop{w}\t%gs", []>, OpSize, TB;
4106 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
4107 "pop{l}\t%gs", []>, TB;
4109 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4110 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4111 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4112 "lds{l}\t{$src, $dst|$dst, $src}", []>;
4113 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4114 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4115 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4116 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
4117 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4118 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4119 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4120 "les{l}\t{$src, $dst|$dst, $src}", []>;
4121 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4122 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4123 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4124 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4125 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4126 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4127 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4128 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4130 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
4131 "verr\t$seg", []>, TB;
4132 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
4133 "verr\t$seg", []>, TB;
4134 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
4135 "verw\t$seg", []>, TB;
4136 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
4137 "verw\t$seg", []>, TB;
4139 // Descriptor-table support instructions
4141 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
4142 "sgdt\t$dst", []>, TB;
4143 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
4144 "sidt\t$dst", []>, TB;
4145 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
4146 "sldt{w}\t$dst", []>, TB;
4147 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
4148 "sldt{w}\t$dst", []>, TB;
4149 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
4150 "lgdt\t$src", []>, TB;
4151 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
4152 "lidt\t$src", []>, TB;
4153 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
4154 "lldt{w}\t$src", []>, TB;
4155 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
4156 "lldt{w}\t$src", []>, TB;
4158 // Lock instruction prefix
4159 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
4161 // Repeat string operation instruction prefixes
4162 // These uses the DF flag in the EFLAGS register to inc or dec ECX
4163 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
4164 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
4165 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
4166 // Repeat while not equal (used with CMPS and SCAS)
4167 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
4170 // Segment override instruction prefixes
4171 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
4172 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
4173 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
4174 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
4175 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
4176 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
4178 // String manipulation instructions
4180 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
4181 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
4182 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
4184 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
4185 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
4186 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
4188 // CPU flow control instructions
4190 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
4191 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
4193 // FPU control instructions
4195 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
4197 // Flag instructions
4199 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
4200 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
4201 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
4202 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
4203 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
4204 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
4205 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
4207 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
4209 // Table lookup instructions
4211 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
4213 // Specialized register support
4215 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
4216 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
4217 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
4219 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
4220 "smsw{w}\t$dst", []>, OpSize, TB;
4221 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
4222 "smsw{l}\t$dst", []>, TB;
4223 // For memory operands, there is only a 16-bit form
4224 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
4225 "smsw{w}\t$dst", []>, TB;
4227 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
4228 "lmsw{w}\t$src", []>, TB;
4229 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
4230 "lmsw{w}\t$src", []>, TB;
4232 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
4234 // Cache instructions
4236 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
4237 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
4242 def INVEPT : I<0x38, RawFrm, (outs), (ins), "invept", []>, OpSize, TB;
4244 def INVVPID : I<0x38, RawFrm, (outs), (ins), "invvpid", []>, OpSize, TB;
4246 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
4247 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4248 "vmclear\t$vmcs", []>, OpSize, TB;
4250 def VMLAUNCH : I<0x01, RawFrm, (outs), (ins), "vmlaunch", []>, TB;
4252 def VMRESUME : I<0x01, RawFrm, (outs), (ins), "vmresume", []>, TB;
4253 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4254 "vmptrld\t$vmcs", []>, TB;
4255 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4256 "vmptrst\t$vmcs", []>, TB;
4257 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
4258 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4259 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
4260 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4261 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
4262 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4263 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4264 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4265 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4266 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4267 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4268 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4269 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4270 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4271 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4272 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4274 def VMXOFF : I<0x01, RawFrm, (outs), (ins), "vmxoff", []>, OpSize;
4275 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
4276 "vmxon\t{$vmxon}", []>, XD;
4278 //===----------------------------------------------------------------------===//
4279 // Non-Instruction Patterns
4280 //===----------------------------------------------------------------------===//
4282 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
4283 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
4284 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
4285 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
4286 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
4287 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
4288 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
4290 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
4291 (ADD32ri GR32:$src1, tconstpool:$src2)>;
4292 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
4293 (ADD32ri GR32:$src1, tjumptable:$src2)>;
4294 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
4295 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
4296 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
4297 (ADD32ri GR32:$src1, texternalsym:$src2)>;
4298 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
4299 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
4301 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
4302 (MOV32mi addr:$dst, tglobaladdr:$src)>;
4303 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
4304 (MOV32mi addr:$dst, texternalsym:$src)>;
4305 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
4306 (MOV32mi addr:$dst, tblockaddress:$src)>;
4310 def : Pat<(X86tcret GR32:$dst, imm:$off),
4311 (TCRETURNri GR32:$dst, imm:$off)>;
4313 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
4314 (TCRETURNdi texternalsym:$dst, imm:$off)>;
4316 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
4317 (TCRETURNdi texternalsym:$dst, imm:$off)>;
4319 // Normal calls, with various flavors of addresses.
4320 def : Pat<(X86call (i32 tglobaladdr:$dst)),
4321 (CALLpcrel32 tglobaladdr:$dst)>;
4322 def : Pat<(X86call (i32 texternalsym:$dst)),
4323 (CALLpcrel32 texternalsym:$dst)>;
4324 def : Pat<(X86call (i32 imm:$dst)),
4325 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
4327 // X86 specific add which produces a flag.
4328 def : Pat<(addc GR32:$src1, GR32:$src2),
4329 (ADD32rr GR32:$src1, GR32:$src2)>;
4330 def : Pat<(addc GR32:$src1, (load addr:$src2)),
4331 (ADD32rm GR32:$src1, addr:$src2)>;
4332 def : Pat<(addc GR32:$src1, imm:$src2),
4333 (ADD32ri GR32:$src1, imm:$src2)>;
4334 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
4335 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4337 def : Pat<(subc GR32:$src1, GR32:$src2),
4338 (SUB32rr GR32:$src1, GR32:$src2)>;
4339 def : Pat<(subc GR32:$src1, (load addr:$src2)),
4340 (SUB32rm GR32:$src1, addr:$src2)>;
4341 def : Pat<(subc GR32:$src1, imm:$src2),
4342 (SUB32ri GR32:$src1, imm:$src2)>;
4343 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
4344 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4348 // TEST R,R is smaller than CMP R,0
4349 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
4350 (TEST8rr GR8:$src1, GR8:$src1)>;
4351 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
4352 (TEST16rr GR16:$src1, GR16:$src1)>;
4353 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
4354 (TEST32rr GR32:$src1, GR32:$src1)>;
4356 // Conditional moves with folded loads with operands swapped and conditions
4358 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
4359 (CMOVAE16rm GR16:$src2, addr:$src1)>;
4360 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
4361 (CMOVAE32rm GR32:$src2, addr:$src1)>;
4362 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
4363 (CMOVB16rm GR16:$src2, addr:$src1)>;
4364 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
4365 (CMOVB32rm GR32:$src2, addr:$src1)>;
4366 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
4367 (CMOVNE16rm GR16:$src2, addr:$src1)>;
4368 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
4369 (CMOVNE32rm GR32:$src2, addr:$src1)>;
4370 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
4371 (CMOVE16rm GR16:$src2, addr:$src1)>;
4372 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
4373 (CMOVE32rm GR32:$src2, addr:$src1)>;
4374 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
4375 (CMOVA16rm GR16:$src2, addr:$src1)>;
4376 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
4377 (CMOVA32rm GR32:$src2, addr:$src1)>;
4378 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
4379 (CMOVBE16rm GR16:$src2, addr:$src1)>;
4380 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
4381 (CMOVBE32rm GR32:$src2, addr:$src1)>;
4382 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
4383 (CMOVGE16rm GR16:$src2, addr:$src1)>;
4384 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
4385 (CMOVGE32rm GR32:$src2, addr:$src1)>;
4386 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
4387 (CMOVL16rm GR16:$src2, addr:$src1)>;
4388 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
4389 (CMOVL32rm GR32:$src2, addr:$src1)>;
4390 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
4391 (CMOVG16rm GR16:$src2, addr:$src1)>;
4392 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
4393 (CMOVG32rm GR32:$src2, addr:$src1)>;
4394 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
4395 (CMOVLE16rm GR16:$src2, addr:$src1)>;
4396 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
4397 (CMOVLE32rm GR32:$src2, addr:$src1)>;
4398 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
4399 (CMOVNP16rm GR16:$src2, addr:$src1)>;
4400 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
4401 (CMOVNP32rm GR32:$src2, addr:$src1)>;
4402 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
4403 (CMOVP16rm GR16:$src2, addr:$src1)>;
4404 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
4405 (CMOVP32rm GR32:$src2, addr:$src1)>;
4406 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
4407 (CMOVNS16rm GR16:$src2, addr:$src1)>;
4408 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
4409 (CMOVNS32rm GR32:$src2, addr:$src1)>;
4410 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
4411 (CMOVS16rm GR16:$src2, addr:$src1)>;
4412 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
4413 (CMOVS32rm GR32:$src2, addr:$src1)>;
4414 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
4415 (CMOVNO16rm GR16:$src2, addr:$src1)>;
4416 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
4417 (CMOVNO32rm GR32:$src2, addr:$src1)>;
4418 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
4419 (CMOVO16rm GR16:$src2, addr:$src1)>;
4420 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
4421 (CMOVO32rm GR32:$src2, addr:$src1)>;
4423 // zextload bool -> zextload byte
4424 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4425 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4426 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4428 // extload bool -> extload byte
4429 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4430 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4431 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4432 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
4433 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
4434 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
4436 // anyext. Define these to do an explicit zero-extend to
4437 // avoid partial-register updates.
4438 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
4439 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
4440 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
4442 // (and (i32 load), 255) -> (zextload i8)
4443 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
4444 (MOVZX32rm8 addr:$src)>;
4445 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
4446 (MOVZX32rm16 addr:$src)>;
4448 //===----------------------------------------------------------------------===//
4450 //===----------------------------------------------------------------------===//
4452 // Odd encoding trick: -128 fits into an 8-bit immediate field while
4453 // +128 doesn't, so in this special case use a sub instead of an add.
4454 def : Pat<(add GR16:$src1, 128),
4455 (SUB16ri8 GR16:$src1, -128)>;
4456 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
4457 (SUB16mi8 addr:$dst, -128)>;
4458 def : Pat<(add GR32:$src1, 128),
4459 (SUB32ri8 GR32:$src1, -128)>;
4460 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
4461 (SUB32mi8 addr:$dst, -128)>;
4463 // r & (2^16-1) ==> movz
4464 def : Pat<(and GR32:$src1, 0xffff),
4465 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
4466 // r & (2^8-1) ==> movz
4467 def : Pat<(and GR32:$src1, 0xff),
4468 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
4471 Requires<[In32BitMode]>;
4472 // r & (2^8-1) ==> movz
4473 def : Pat<(and GR16:$src1, 0xff),
4474 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
4477 Requires<[In32BitMode]>;
4479 // sext_inreg patterns
4480 def : Pat<(sext_inreg GR32:$src, i16),
4481 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
4482 def : Pat<(sext_inreg GR32:$src, i8),
4483 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4486 Requires<[In32BitMode]>;
4487 def : Pat<(sext_inreg GR16:$src, i8),
4488 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4491 Requires<[In32BitMode]>;
4494 def : Pat<(i16 (trunc GR32:$src)),
4495 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
4496 def : Pat<(i8 (trunc GR32:$src)),
4497 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4499 Requires<[In32BitMode]>;
4500 def : Pat<(i8 (trunc GR16:$src)),
4501 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4503 Requires<[In32BitMode]>;
4505 // h-register tricks
4506 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
4507 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4508 x86_subreg_8bit_hi)>,
4509 Requires<[In32BitMode]>;
4510 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
4511 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4512 x86_subreg_8bit_hi)>,
4513 Requires<[In32BitMode]>;
4514 def : Pat<(srl GR16:$src, (i8 8)),
4517 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4518 x86_subreg_8bit_hi)),
4520 Requires<[In32BitMode]>;
4521 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4522 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4524 x86_subreg_8bit_hi))>,
4525 Requires<[In32BitMode]>;
4526 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4527 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4529 x86_subreg_8bit_hi))>,
4530 Requires<[In32BitMode]>;
4531 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4532 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4534 x86_subreg_8bit_hi))>,
4535 Requires<[In32BitMode]>;
4537 // (shl x, 1) ==> (add x, x)
4538 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
4539 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
4540 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
4542 // (shl x (and y, 31)) ==> (shl x, y)
4543 def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
4544 (SHL8rCL GR8:$src1)>;
4545 def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
4546 (SHL16rCL GR16:$src1)>;
4547 def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
4548 (SHL32rCL GR32:$src1)>;
4549 def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4550 (SHL8mCL addr:$dst)>;
4551 def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4552 (SHL16mCL addr:$dst)>;
4553 def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4554 (SHL32mCL addr:$dst)>;
4556 def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
4557 (SHR8rCL GR8:$src1)>;
4558 def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
4559 (SHR16rCL GR16:$src1)>;
4560 def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
4561 (SHR32rCL GR32:$src1)>;
4562 def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4563 (SHR8mCL addr:$dst)>;
4564 def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4565 (SHR16mCL addr:$dst)>;
4566 def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4567 (SHR32mCL addr:$dst)>;
4569 def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
4570 (SAR8rCL GR8:$src1)>;
4571 def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
4572 (SAR16rCL GR16:$src1)>;
4573 def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
4574 (SAR32rCL GR32:$src1)>;
4575 def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4576 (SAR8mCL addr:$dst)>;
4577 def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4578 (SAR16mCL addr:$dst)>;
4579 def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4580 (SAR32mCL addr:$dst)>;
4582 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
4583 def : Pat<(or (srl GR32:$src1, CL:$amt),
4584 (shl GR32:$src2, (sub 32, CL:$amt))),
4585 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4587 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
4588 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4589 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4591 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
4592 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4593 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4595 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4596 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4598 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4600 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
4601 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4603 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
4604 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
4605 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4607 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
4608 def : Pat<(or (shl GR32:$src1, CL:$amt),
4609 (srl GR32:$src2, (sub 32, CL:$amt))),
4610 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4612 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
4613 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4614 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4616 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
4617 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4618 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4620 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4621 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4623 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4625 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
4626 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4628 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
4629 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
4630 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4632 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
4633 def : Pat<(or (srl GR16:$src1, CL:$amt),
4634 (shl GR16:$src2, (sub 16, CL:$amt))),
4635 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4637 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
4638 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4639 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4641 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
4642 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4643 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4645 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4646 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4648 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4650 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
4651 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4653 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
4654 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
4655 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4657 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
4658 def : Pat<(or (shl GR16:$src1, CL:$amt),
4659 (srl GR16:$src2, (sub 16, CL:$amt))),
4660 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4662 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
4663 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4664 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4666 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
4667 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4668 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4670 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4671 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4673 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4675 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
4676 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4678 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
4679 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
4680 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4682 // (anyext (setcc_carry)) -> (setcc_carry)
4683 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4685 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4688 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
4689 let AddedComplexity = 5 in { // Try this before the selecting to OR
4690 def : Pat<(parallel (or_is_add GR16:$src1, imm:$src2),
4692 (ADD16ri GR16:$src1, imm:$src2)>;
4693 def : Pat<(parallel (or_is_add GR32:$src1, imm:$src2),
4695 (ADD32ri GR32:$src1, imm:$src2)>;
4696 def : Pat<(parallel (or_is_add GR16:$src1, i16immSExt8:$src2),
4698 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4699 def : Pat<(parallel (or_is_add GR32:$src1, i32immSExt8:$src2),
4701 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4702 def : Pat<(parallel (or_is_add GR16:$src1, GR16:$src2),
4704 (ADD16rr GR16:$src1, GR16:$src2)>;
4705 def : Pat<(parallel (or_is_add GR32:$src1, GR32:$src2),
4707 (ADD32rr GR32:$src1, GR32:$src2)>;
4708 } // AddedComplexity
4710 //===----------------------------------------------------------------------===//
4711 // EFLAGS-defining Patterns
4712 //===----------------------------------------------------------------------===//
4714 // Register-Register Addition with EFLAGS result
4715 def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
4717 (ADD8rr GR8:$src1, GR8:$src2)>;
4718 def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
4720 (ADD16rr GR16:$src1, GR16:$src2)>;
4721 def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
4723 (ADD32rr GR32:$src1, GR32:$src2)>;
4725 // Register-Memory Addition with EFLAGS result
4726 def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
4728 (ADD8rm GR8:$src1, addr:$src2)>;
4729 def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
4731 (ADD16rm GR16:$src1, addr:$src2)>;
4732 def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
4734 (ADD32rm GR32:$src1, addr:$src2)>;
4736 // Register-Integer Addition with EFLAGS result
4737 def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
4739 (ADD8ri GR8:$src1, imm:$src2)>;
4740 def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
4742 (ADD16ri GR16:$src1, imm:$src2)>;
4743 def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
4745 (ADD32ri GR32:$src1, imm:$src2)>;
4746 def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
4748 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4749 def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
4751 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4753 // Memory-Register Addition with EFLAGS result
4754 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
4757 (ADD8mr addr:$dst, GR8:$src2)>;
4758 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
4761 (ADD16mr addr:$dst, GR16:$src2)>;
4762 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
4765 (ADD32mr addr:$dst, GR32:$src2)>;
4767 // Memory-Integer Addition with EFLAGS result
4768 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
4771 (ADD8mi addr:$dst, imm:$src2)>;
4772 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
4775 (ADD16mi addr:$dst, imm:$src2)>;
4776 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
4779 (ADD32mi addr:$dst, imm:$src2)>;
4780 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4783 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
4784 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4787 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
4789 // Register-Register Subtraction with EFLAGS result
4790 def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
4792 (SUB8rr GR8:$src1, GR8:$src2)>;
4793 def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
4795 (SUB16rr GR16:$src1, GR16:$src2)>;
4796 def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
4798 (SUB32rr GR32:$src1, GR32:$src2)>;
4800 // Register-Memory Subtraction with EFLAGS result
4801 def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
4803 (SUB8rm GR8:$src1, addr:$src2)>;
4804 def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
4806 (SUB16rm GR16:$src1, addr:$src2)>;
4807 def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
4809 (SUB32rm GR32:$src1, addr:$src2)>;
4811 // Register-Integer Subtraction with EFLAGS result
4812 def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
4814 (SUB8ri GR8:$src1, imm:$src2)>;
4815 def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
4817 (SUB16ri GR16:$src1, imm:$src2)>;
4818 def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
4820 (SUB32ri GR32:$src1, imm:$src2)>;
4821 def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
4823 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4824 def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
4826 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4828 // Memory-Register Subtraction with EFLAGS result
4829 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
4832 (SUB8mr addr:$dst, GR8:$src2)>;
4833 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
4836 (SUB16mr addr:$dst, GR16:$src2)>;
4837 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
4840 (SUB32mr addr:$dst, GR32:$src2)>;
4842 // Memory-Integer Subtraction with EFLAGS result
4843 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
4846 (SUB8mi addr:$dst, imm:$src2)>;
4847 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
4850 (SUB16mi addr:$dst, imm:$src2)>;
4851 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
4854 (SUB32mi addr:$dst, imm:$src2)>;
4855 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4858 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
4859 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4862 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
4865 // Register-Register Signed Integer Multiply with EFLAGS result
4866 def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
4868 (IMUL16rr GR16:$src1, GR16:$src2)>;
4869 def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
4871 (IMUL32rr GR32:$src1, GR32:$src2)>;
4873 // Register-Memory Signed Integer Multiply with EFLAGS result
4874 def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
4876 (IMUL16rm GR16:$src1, addr:$src2)>;
4877 def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
4879 (IMUL32rm GR32:$src1, addr:$src2)>;
4881 // Register-Integer Signed Integer Multiply with EFLAGS result
4882 def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
4884 (IMUL16rri GR16:$src1, imm:$src2)>;
4885 def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
4887 (IMUL32rri GR32:$src1, imm:$src2)>;
4888 def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
4890 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4891 def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
4893 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4895 // Memory-Integer Signed Integer Multiply with EFLAGS result
4896 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
4898 (IMUL16rmi addr:$src1, imm:$src2)>;
4899 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
4901 (IMUL32rmi addr:$src1, imm:$src2)>;
4902 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
4904 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4905 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
4907 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4909 // Optimize multiply by 2 with EFLAGS result.
4910 let AddedComplexity = 2 in {
4911 def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
4913 (ADD16rr GR16:$src1, GR16:$src1)>;
4915 def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
4917 (ADD32rr GR32:$src1, GR32:$src1)>;
4920 // INC and DEC with EFLAGS result. Note that these do not set CF.
4921 def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
4923 def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
4926 def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
4928 def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
4932 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
4933 (INC16r GR16:$src)>, Requires<[In32BitMode]>;
4934 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
4936 (INC16m addr:$dst)>, Requires<[In32BitMode]>;
4937 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
4938 (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
4939 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
4941 (DEC16m addr:$dst)>, Requires<[In32BitMode]>;
4943 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
4944 (INC32r GR32:$src)>, Requires<[In32BitMode]>;
4945 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
4947 (INC32m addr:$dst)>, Requires<[In32BitMode]>;
4948 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
4949 (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
4950 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
4952 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
4954 // Register-Register Or with EFLAGS result
4955 def : Pat<(parallel (X86or_flag GR8:$src1, GR8:$src2),
4957 (OR8rr GR8:$src1, GR8:$src2)>;
4958 def : Pat<(parallel (X86or_flag GR16:$src1, GR16:$src2),
4960 (OR16rr GR16:$src1, GR16:$src2)>;
4961 def : Pat<(parallel (X86or_flag GR32:$src1, GR32:$src2),
4963 (OR32rr GR32:$src1, GR32:$src2)>;
4965 // Register-Memory Or with EFLAGS result
4966 def : Pat<(parallel (X86or_flag GR8:$src1, (loadi8 addr:$src2)),
4968 (OR8rm GR8:$src1, addr:$src2)>;
4969 def : Pat<(parallel (X86or_flag GR16:$src1, (loadi16 addr:$src2)),
4971 (OR16rm GR16:$src1, addr:$src2)>;
4972 def : Pat<(parallel (X86or_flag GR32:$src1, (loadi32 addr:$src2)),
4974 (OR32rm GR32:$src1, addr:$src2)>;
4976 // Register-Integer Or with EFLAGS result
4977 def : Pat<(parallel (X86or_flag GR8:$src1, imm:$src2),
4979 (OR8ri GR8:$src1, imm:$src2)>;
4980 def : Pat<(parallel (X86or_flag GR16:$src1, imm:$src2),
4982 (OR16ri GR16:$src1, imm:$src2)>;
4983 def : Pat<(parallel (X86or_flag GR32:$src1, imm:$src2),
4985 (OR32ri GR32:$src1, imm:$src2)>;
4986 def : Pat<(parallel (X86or_flag GR16:$src1, i16immSExt8:$src2),
4988 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4989 def : Pat<(parallel (X86or_flag GR32:$src1, i32immSExt8:$src2),
4991 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4993 // Memory-Register Or with EFLAGS result
4994 def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), GR8:$src2),
4997 (OR8mr addr:$dst, GR8:$src2)>;
4998 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), GR16:$src2),
5001 (OR16mr addr:$dst, GR16:$src2)>;
5002 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), GR32:$src2),
5005 (OR32mr addr:$dst, GR32:$src2)>;
5007 // Memory-Integer Or with EFLAGS result
5008 def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), imm:$src2),
5011 (OR8mi addr:$dst, imm:$src2)>;
5012 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), imm:$src2),
5015 (OR16mi addr:$dst, imm:$src2)>;
5016 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), imm:$src2),
5019 (OR32mi addr:$dst, imm:$src2)>;
5020 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), i16immSExt8:$src2),
5023 (OR16mi8 addr:$dst, i16immSExt8:$src2)>;
5024 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), i32immSExt8:$src2),
5027 (OR32mi8 addr:$dst, i32immSExt8:$src2)>;
5029 // Register-Register XOr with EFLAGS result
5030 def : Pat<(parallel (X86xor_flag GR8:$src1, GR8:$src2),
5032 (XOR8rr GR8:$src1, GR8:$src2)>;
5033 def : Pat<(parallel (X86xor_flag GR16:$src1, GR16:$src2),
5035 (XOR16rr GR16:$src1, GR16:$src2)>;
5036 def : Pat<(parallel (X86xor_flag GR32:$src1, GR32:$src2),
5038 (XOR32rr GR32:$src1, GR32:$src2)>;
5040 // Register-Memory XOr with EFLAGS result
5041 def : Pat<(parallel (X86xor_flag GR8:$src1, (loadi8 addr:$src2)),
5043 (XOR8rm GR8:$src1, addr:$src2)>;
5044 def : Pat<(parallel (X86xor_flag GR16:$src1, (loadi16 addr:$src2)),
5046 (XOR16rm GR16:$src1, addr:$src2)>;
5047 def : Pat<(parallel (X86xor_flag GR32:$src1, (loadi32 addr:$src2)),
5049 (XOR32rm GR32:$src1, addr:$src2)>;
5051 // Register-Integer XOr with EFLAGS result
5052 def : Pat<(parallel (X86xor_flag GR8:$src1, imm:$src2),
5054 (XOR8ri GR8:$src1, imm:$src2)>;
5055 def : Pat<(parallel (X86xor_flag GR16:$src1, imm:$src2),
5057 (XOR16ri GR16:$src1, imm:$src2)>;
5058 def : Pat<(parallel (X86xor_flag GR32:$src1, imm:$src2),
5060 (XOR32ri GR32:$src1, imm:$src2)>;
5061 def : Pat<(parallel (X86xor_flag GR16:$src1, i16immSExt8:$src2),
5063 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
5064 def : Pat<(parallel (X86xor_flag GR32:$src1, i32immSExt8:$src2),
5066 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
5068 // Memory-Register XOr with EFLAGS result
5069 def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), GR8:$src2),
5072 (XOR8mr addr:$dst, GR8:$src2)>;
5073 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), GR16:$src2),
5076 (XOR16mr addr:$dst, GR16:$src2)>;
5077 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), GR32:$src2),
5080 (XOR32mr addr:$dst, GR32:$src2)>;
5082 // Memory-Integer XOr with EFLAGS result
5083 def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), imm:$src2),
5086 (XOR8mi addr:$dst, imm:$src2)>;
5087 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), imm:$src2),
5090 (XOR16mi addr:$dst, imm:$src2)>;
5091 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), imm:$src2),
5094 (XOR32mi addr:$dst, imm:$src2)>;
5095 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), i16immSExt8:$src2),
5098 (XOR16mi8 addr:$dst, i16immSExt8:$src2)>;
5099 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), i32immSExt8:$src2),
5102 (XOR32mi8 addr:$dst, i32immSExt8:$src2)>;
5104 // Register-Register And with EFLAGS result
5105 def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2),
5107 (AND8rr GR8:$src1, GR8:$src2)>;
5108 def : Pat<(parallel (X86and_flag GR16:$src1, GR16:$src2),
5110 (AND16rr GR16:$src1, GR16:$src2)>;
5111 def : Pat<(parallel (X86and_flag GR32:$src1, GR32:$src2),
5113 (AND32rr GR32:$src1, GR32:$src2)>;
5115 // Register-Memory And with EFLAGS result
5116 def : Pat<(parallel (X86and_flag GR8:$src1, (loadi8 addr:$src2)),
5118 (AND8rm GR8:$src1, addr:$src2)>;
5119 def : Pat<(parallel (X86and_flag GR16:$src1, (loadi16 addr:$src2)),
5121 (AND16rm GR16:$src1, addr:$src2)>;
5122 def : Pat<(parallel (X86and_flag GR32:$src1, (loadi32 addr:$src2)),
5124 (AND32rm GR32:$src1, addr:$src2)>;
5126 // Register-Integer And with EFLAGS result
5127 def : Pat<(parallel (X86and_flag GR8:$src1, imm:$src2),
5129 (AND8ri GR8:$src1, imm:$src2)>;
5130 def : Pat<(parallel (X86and_flag GR16:$src1, imm:$src2),
5132 (AND16ri GR16:$src1, imm:$src2)>;
5133 def : Pat<(parallel (X86and_flag GR32:$src1, imm:$src2),
5135 (AND32ri GR32:$src1, imm:$src2)>;
5136 def : Pat<(parallel (X86and_flag GR16:$src1, i16immSExt8:$src2),
5138 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
5139 def : Pat<(parallel (X86and_flag GR32:$src1, i32immSExt8:$src2),
5141 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
5143 // Memory-Register And with EFLAGS result
5144 def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), GR8:$src2),
5147 (AND8mr addr:$dst, GR8:$src2)>;
5148 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), GR16:$src2),
5151 (AND16mr addr:$dst, GR16:$src2)>;
5152 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), GR32:$src2),
5155 (AND32mr addr:$dst, GR32:$src2)>;
5157 // Memory-Integer And with EFLAGS result
5158 def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), imm:$src2),
5161 (AND8mi addr:$dst, imm:$src2)>;
5162 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), imm:$src2),
5165 (AND16mi addr:$dst, imm:$src2)>;
5166 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), imm:$src2),
5169 (AND32mi addr:$dst, imm:$src2)>;
5170 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), i16immSExt8:$src2),
5173 (AND16mi8 addr:$dst, i16immSExt8:$src2)>;
5174 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), i32immSExt8:$src2),
5177 (AND32mi8 addr:$dst, i32immSExt8:$src2)>;
5179 // -disable-16bit support.
5180 def : Pat<(truncstorei16 (i32 imm:$src), addr:$dst),
5181 (MOV16mi addr:$dst, imm:$src)>;
5182 def : Pat<(truncstorei16 GR32:$src, addr:$dst),
5183 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
5184 def : Pat<(i32 (sextloadi16 addr:$dst)),
5185 (MOVSX32rm16 addr:$dst)>;
5186 def : Pat<(i32 (zextloadi16 addr:$dst)),
5187 (MOVZX32rm16 addr:$dst)>;
5188 def : Pat<(i32 (extloadi16 addr:$dst)),
5189 (MOVZX32rm16 addr:$dst)>;
5191 //===----------------------------------------------------------------------===//
5192 // Floating Point Stack Support
5193 //===----------------------------------------------------------------------===//
5195 include "X86InstrFPStack.td"
5197 //===----------------------------------------------------------------------===//
5199 //===----------------------------------------------------------------------===//
5201 include "X86Instr64bit.td"
5203 //===----------------------------------------------------------------------===//
5204 // SIMD support (SSE, MMX and AVX)
5205 //===----------------------------------------------------------------------===//
5207 include "X86InstrFragmentsSIMD.td"
5209 //===----------------------------------------------------------------------===//
5210 // XMM Floating point support (requires SSE / SSE2)
5211 //===----------------------------------------------------------------------===//
5213 include "X86InstrSSE.td"
5215 //===----------------------------------------------------------------------===//
5216 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
5217 //===----------------------------------------------------------------------===//
5219 include "X86InstrMMX.td"