1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 //def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
35 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
49 // RES1, RES2, FLAGS = op LHS, RHS
50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
54 SDTCisInt<0>, SDTCisVT<1, i32>]>;
55 def SDTX86BrCond : SDTypeProfile<0, 3,
56 [SDTCisVT<0, OtherVT>,
57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 def SDTX86SetCC : SDTypeProfile<1, 2,
61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
62 def SDTX86SetCC_C : SDTypeProfile<1, 2,
64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
66 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
68 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
70 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
72 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
74 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
75 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
76 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
78 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
79 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
82 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
84 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
88 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
94 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
96 def SDTX86Void : SDTypeProfile<0, 0, []>;
98 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
100 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
102 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
104 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
106 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
108 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
110 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
112 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
114 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
116 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
117 [SDNPHasChain,SDNPSideEffect]>;
118 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
120 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
122 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
126 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
127 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
128 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
129 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
131 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
132 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
134 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
135 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
137 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
138 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
140 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
142 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
143 [SDNPHasChain, SDNPSideEffect]>;
145 def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand,
146 [SDNPHasChain, SDNPSideEffect]>;
148 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
149 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
150 SDNPMayLoad, SDNPMemOperand]>;
151 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
152 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
153 SDNPMayLoad, SDNPMemOperand]>;
154 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
155 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
156 SDNPMayLoad, SDNPMemOperand]>;
158 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
159 [SDNPHasChain, SDNPMayStore,
160 SDNPMayLoad, SDNPMemOperand]>;
161 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
162 [SDNPHasChain, SDNPMayStore,
163 SDNPMayLoad, SDNPMemOperand]>;
164 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
165 [SDNPHasChain, SDNPMayStore,
166 SDNPMayLoad, SDNPMemOperand]>;
167 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
168 [SDNPHasChain, SDNPMayStore,
169 SDNPMayLoad, SDNPMemOperand]>;
170 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
171 [SDNPHasChain, SDNPMayStore,
172 SDNPMayLoad, SDNPMemOperand]>;
173 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
174 [SDNPHasChain, SDNPMayStore,
175 SDNPMayLoad, SDNPMemOperand]>;
176 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
177 [SDNPHasChain, SDNPMayStore,
178 SDNPMayLoad, SDNPMemOperand]>;
179 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
180 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
182 def X86vastart_save_xmm_regs :
183 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
184 SDT_X86VASTART_SAVE_XMM_REGS,
185 [SDNPHasChain, SDNPVariadic]>;
187 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
188 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
190 def X86callseq_start :
191 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
192 [SDNPHasChain, SDNPOutGlue]>;
194 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
195 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
197 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
198 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
201 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
202 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
203 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
204 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
207 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
208 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
210 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
211 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
213 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
214 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
216 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
217 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
219 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
222 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
223 SDTypeProfile<1, 1, [SDTCisInt<0>,
225 [SDNPHasChain, SDNPSideEffect]>;
226 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
227 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
228 [SDNPHasChain, SDNPSideEffect]>;
230 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
231 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
233 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
235 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
236 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
238 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
240 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
241 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
243 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
244 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
245 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
247 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
249 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
252 def X86bzhi : SDNode<"X86ISD::BZHI", SDTIntShiftOp>;
253 def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>;
255 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
257 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
258 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
260 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
263 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
264 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
266 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL,
267 [SDNPHasChain, SDNPOutGlue]>;
269 //===----------------------------------------------------------------------===//
270 // X86 Operand Definitions.
273 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
274 // the index operand of an address, to conform to x86 encoding restrictions.
275 def ptr_rc_nosp : PointerLikeRegClass<1>;
277 // *mem - Operand definitions for the funky X86 addressing mode operands.
279 def X86MemAsmOperand : AsmOperandClass {
282 def X86Mem8AsmOperand : AsmOperandClass {
283 let Name = "Mem8"; let RenderMethod = "addMemOperands";
285 def X86Mem16AsmOperand : AsmOperandClass {
286 let Name = "Mem16"; let RenderMethod = "addMemOperands";
288 def X86Mem32AsmOperand : AsmOperandClass {
289 let Name = "Mem32"; let RenderMethod = "addMemOperands";
291 def X86Mem64AsmOperand : AsmOperandClass {
292 let Name = "Mem64"; let RenderMethod = "addMemOperands";
294 def X86Mem80AsmOperand : AsmOperandClass {
295 let Name = "Mem80"; let RenderMethod = "addMemOperands";
297 def X86Mem128AsmOperand : AsmOperandClass {
298 let Name = "Mem128"; let RenderMethod = "addMemOperands";
300 def X86Mem256AsmOperand : AsmOperandClass {
301 let Name = "Mem256"; let RenderMethod = "addMemOperands";
303 def X86Mem512AsmOperand : AsmOperandClass {
304 let Name = "Mem512"; let RenderMethod = "addMemOperands";
307 // Gather mem operands
308 def X86MemVX32Operand : AsmOperandClass {
309 let Name = "MemVX32"; let RenderMethod = "addMemOperands";
311 def X86MemVY32Operand : AsmOperandClass {
312 let Name = "MemVY32"; let RenderMethod = "addMemOperands";
314 def X86MemVZ32Operand : AsmOperandClass {
315 let Name = "MemVZ32"; let RenderMethod = "addMemOperands";
317 def X86MemVX64Operand : AsmOperandClass {
318 let Name = "MemVX64"; let RenderMethod = "addMemOperands";
320 def X86MemVY64Operand : AsmOperandClass {
321 let Name = "MemVY64"; let RenderMethod = "addMemOperands";
323 def X86MemVZ64Operand : AsmOperandClass {
324 let Name = "MemVZ64"; let RenderMethod = "addMemOperands";
327 def X86AbsMemAsmOperand : AsmOperandClass {
329 let SuperClasses = [X86MemAsmOperand];
331 class X86MemOperand<string printMethod> : Operand<iPTR> {
332 let PrintMethod = printMethod;
333 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
334 let ParserMatchClass = X86MemAsmOperand;
337 let OperandType = "OPERAND_MEMORY" in {
338 def opaque32mem : X86MemOperand<"printopaquemem">;
339 def opaque48mem : X86MemOperand<"printopaquemem">;
340 def opaque80mem : X86MemOperand<"printopaquemem">;
341 def opaque512mem : X86MemOperand<"printopaquemem">;
343 def i8mem : X86MemOperand<"printi8mem"> {
344 let ParserMatchClass = X86Mem8AsmOperand; }
345 def i16mem : X86MemOperand<"printi16mem"> {
346 let ParserMatchClass = X86Mem16AsmOperand; }
347 def i32mem : X86MemOperand<"printi32mem"> {
348 let ParserMatchClass = X86Mem32AsmOperand; }
349 def i64mem : X86MemOperand<"printi64mem"> {
350 let ParserMatchClass = X86Mem64AsmOperand; }
351 def i128mem : X86MemOperand<"printi128mem"> {
352 let ParserMatchClass = X86Mem128AsmOperand; }
353 def i256mem : X86MemOperand<"printi256mem"> {
354 let ParserMatchClass = X86Mem256AsmOperand; }
355 def i512mem : X86MemOperand<"printi512mem"> {
356 let ParserMatchClass = X86Mem512AsmOperand; }
357 def f32mem : X86MemOperand<"printf32mem"> {
358 let ParserMatchClass = X86Mem32AsmOperand; }
359 def f64mem : X86MemOperand<"printf64mem"> {
360 let ParserMatchClass = X86Mem64AsmOperand; }
361 def f80mem : X86MemOperand<"printf80mem"> {
362 let ParserMatchClass = X86Mem80AsmOperand; }
363 def f128mem : X86MemOperand<"printf128mem"> {
364 let ParserMatchClass = X86Mem128AsmOperand; }
365 def f256mem : X86MemOperand<"printf256mem">{
366 let ParserMatchClass = X86Mem256AsmOperand; }
367 def f512mem : X86MemOperand<"printf512mem">{
368 let ParserMatchClass = X86Mem512AsmOperand; }
369 def v512mem : Operand<iPTR> {
370 let PrintMethod = "printf512mem";
371 let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm);
372 let ParserMatchClass = X86Mem512AsmOperand; }
374 // Gather mem operands
375 def vx32mem : X86MemOperand<"printi32mem">{
376 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
377 let ParserMatchClass = X86MemVX32Operand; }
378 def vy32mem : X86MemOperand<"printi32mem">{
379 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
380 let ParserMatchClass = X86MemVY32Operand; }
381 def vx64mem : X86MemOperand<"printi64mem">{
382 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
383 let ParserMatchClass = X86MemVX64Operand; }
384 def vy64mem : X86MemOperand<"printi64mem">{
385 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
386 let ParserMatchClass = X86MemVY64Operand; }
387 def vy64xmem : X86MemOperand<"printi64mem">{
388 let MIOperandInfo = (ops ptr_rc, i8imm, VR256X, i32imm, i8imm);
389 let ParserMatchClass = X86MemVY64Operand; }
390 def vz32mem : X86MemOperand<"printi32mem">{
391 let MIOperandInfo = (ops ptr_rc, i16imm, VR512, i32imm, i8imm);
392 let ParserMatchClass = X86MemVZ32Operand; }
393 def vz64mem : X86MemOperand<"printi64mem">{
394 let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm);
395 let ParserMatchClass = X86MemVZ64Operand; }
398 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
399 // plain GR64, so that it doesn't potentially require a REX prefix.
400 def i8mem_NOREX : Operand<i64> {
401 let PrintMethod = "printi8mem";
402 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
403 let ParserMatchClass = X86Mem8AsmOperand;
404 let OperandType = "OPERAND_MEMORY";
407 // GPRs available for tailcall.
408 // It represents GR32_TC, GR64_TC or GR64_TCW64.
409 def ptr_rc_tailcall : PointerLikeRegClass<2>;
411 // Special i32mem for addresses of load folding tail calls. These are not
412 // allowed to use callee-saved registers since they must be scheduled
413 // after callee-saved register are popped.
414 def i32mem_TC : Operand<i32> {
415 let PrintMethod = "printi32mem";
416 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
418 let ParserMatchClass = X86Mem32AsmOperand;
419 let OperandType = "OPERAND_MEMORY";
422 // Special i64mem for addresses of load folding tail calls. These are not
423 // allowed to use callee-saved registers since they must be scheduled
424 // after callee-saved register are popped.
425 def i64mem_TC : Operand<i64> {
426 let PrintMethod = "printi64mem";
427 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
428 ptr_rc_tailcall, i32imm, i8imm);
429 let ParserMatchClass = X86Mem64AsmOperand;
430 let OperandType = "OPERAND_MEMORY";
433 let OperandType = "OPERAND_PCREL",
434 ParserMatchClass = X86AbsMemAsmOperand,
435 PrintMethod = "printPCRelImm" in {
436 def i32imm_pcrel : Operand<i32>;
437 def i16imm_pcrel : Operand<i16>;
439 // Branch targets have OtherVT type and print as pc-relative values.
440 def brtarget : Operand<OtherVT>;
441 def brtarget8 : Operand<OtherVT>;
445 def X86SrcIdx8Operand : AsmOperandClass {
446 let Name = "SrcIdx8";
447 let RenderMethod = "addSrcIdxOperands";
448 let SuperClasses = [X86Mem8AsmOperand];
450 def X86SrcIdx16Operand : AsmOperandClass {
451 let Name = "SrcIdx16";
452 let RenderMethod = "addSrcIdxOperands";
453 let SuperClasses = [X86Mem16AsmOperand];
455 def X86SrcIdx32Operand : AsmOperandClass {
456 let Name = "SrcIdx32";
457 let RenderMethod = "addSrcIdxOperands";
458 let SuperClasses = [X86Mem32AsmOperand];
460 def X86SrcIdx64Operand : AsmOperandClass {
461 let Name = "SrcIdx64";
462 let RenderMethod = "addSrcIdxOperands";
463 let SuperClasses = [X86Mem64AsmOperand];
465 def X86DstIdx8Operand : AsmOperandClass {
466 let Name = "DstIdx8";
467 let RenderMethod = "addDstIdxOperands";
468 let SuperClasses = [X86Mem8AsmOperand];
470 def X86DstIdx16Operand : AsmOperandClass {
471 let Name = "DstIdx16";
472 let RenderMethod = "addDstIdxOperands";
473 let SuperClasses = [X86Mem16AsmOperand];
475 def X86DstIdx32Operand : AsmOperandClass {
476 let Name = "DstIdx32";
477 let RenderMethod = "addDstIdxOperands";
478 let SuperClasses = [X86Mem32AsmOperand];
480 def X86DstIdx64Operand : AsmOperandClass {
481 let Name = "DstIdx64";
482 let RenderMethod = "addDstIdxOperands";
483 let SuperClasses = [X86Mem64AsmOperand];
485 def X86MemOffs8AsmOperand : AsmOperandClass {
486 let Name = "MemOffs8";
487 let RenderMethod = "addMemOffsOperands";
488 let SuperClasses = [X86Mem8AsmOperand];
490 def X86MemOffs16AsmOperand : AsmOperandClass {
491 let Name = "MemOffs16";
492 let RenderMethod = "addMemOffsOperands";
493 let SuperClasses = [X86Mem16AsmOperand];
495 def X86MemOffs32AsmOperand : AsmOperandClass {
496 let Name = "MemOffs32";
497 let RenderMethod = "addMemOffsOperands";
498 let SuperClasses = [X86Mem32AsmOperand];
500 def X86MemOffs64AsmOperand : AsmOperandClass {
501 let Name = "MemOffs64";
502 let RenderMethod = "addMemOffsOperands";
503 let SuperClasses = [X86Mem64AsmOperand];
505 let OperandType = "OPERAND_MEMORY" in {
506 def srcidx8 : Operand<iPTR> {
507 let ParserMatchClass = X86SrcIdx8Operand;
508 let MIOperandInfo = (ops ptr_rc, i8imm);
509 let PrintMethod = "printSrcIdx8"; }
510 def srcidx16 : Operand<iPTR> {
511 let ParserMatchClass = X86SrcIdx16Operand;
512 let MIOperandInfo = (ops ptr_rc, i8imm);
513 let PrintMethod = "printSrcIdx16"; }
514 def srcidx32 : Operand<iPTR> {
515 let ParserMatchClass = X86SrcIdx32Operand;
516 let MIOperandInfo = (ops ptr_rc, i8imm);
517 let PrintMethod = "printSrcIdx32"; }
518 def srcidx64 : Operand<iPTR> {
519 let ParserMatchClass = X86SrcIdx64Operand;
520 let MIOperandInfo = (ops ptr_rc, i8imm);
521 let PrintMethod = "printSrcIdx64"; }
522 def dstidx8 : Operand<iPTR> {
523 let ParserMatchClass = X86DstIdx8Operand;
524 let MIOperandInfo = (ops ptr_rc);
525 let PrintMethod = "printDstIdx8"; }
526 def dstidx16 : Operand<iPTR> {
527 let ParserMatchClass = X86DstIdx16Operand;
528 let MIOperandInfo = (ops ptr_rc);
529 let PrintMethod = "printDstIdx16"; }
530 def dstidx32 : Operand<iPTR> {
531 let ParserMatchClass = X86DstIdx32Operand;
532 let MIOperandInfo = (ops ptr_rc);
533 let PrintMethod = "printDstIdx32"; }
534 def dstidx64 : Operand<iPTR> {
535 let ParserMatchClass = X86DstIdx64Operand;
536 let MIOperandInfo = (ops ptr_rc);
537 let PrintMethod = "printDstIdx64"; }
538 def offset8 : Operand<iPTR> {
539 let ParserMatchClass = X86MemOffs8AsmOperand;
540 let MIOperandInfo = (ops i64imm, i8imm);
541 let PrintMethod = "printMemOffs8"; }
542 def offset16 : Operand<iPTR> {
543 let ParserMatchClass = X86MemOffs16AsmOperand;
544 let MIOperandInfo = (ops i64imm, i8imm);
545 let PrintMethod = "printMemOffs16"; }
546 def offset32 : Operand<iPTR> {
547 let ParserMatchClass = X86MemOffs32AsmOperand;
548 let MIOperandInfo = (ops i64imm, i8imm);
549 let PrintMethod = "printMemOffs32"; }
550 def offset64 : Operand<iPTR> {
551 let ParserMatchClass = X86MemOffs64AsmOperand;
552 let MIOperandInfo = (ops i64imm, i8imm);
553 let PrintMethod = "printMemOffs64"; }
557 def SSECC : Operand<i8> {
558 let PrintMethod = "printSSECC";
559 let OperandType = "OPERAND_IMMEDIATE";
562 def AVXCC : Operand<i8> {
563 let PrintMethod = "printAVXCC";
564 let OperandType = "OPERAND_IMMEDIATE";
567 class ImmSExtAsmOperandClass : AsmOperandClass {
568 let SuperClasses = [ImmAsmOperand];
569 let RenderMethod = "addImmOperands";
572 class ImmZExtAsmOperandClass : AsmOperandClass {
573 let SuperClasses = [ImmAsmOperand];
574 let RenderMethod = "addImmOperands";
577 def X86GR32orGR64AsmOperand : AsmOperandClass {
578 let Name = "GR32orGR64";
581 def GR32orGR64 : RegisterOperand<GR32> {
582 let ParserMatchClass = X86GR32orGR64AsmOperand;
585 def AVX512RC : Operand<i32> {
586 let PrintMethod = "printRoundingControl";
587 let OperandType = "OPERAND_IMMEDIATE";
589 // Sign-extended immediate classes. We don't need to define the full lattice
590 // here because there is no instruction with an ambiguity between ImmSExti64i32
593 // The strange ranges come from the fact that the assembler always works with
594 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
595 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
598 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
599 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
600 let Name = "ImmSExti64i32";
603 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
604 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
605 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
606 let Name = "ImmSExti16i8";
607 let SuperClasses = [ImmSExti64i32AsmOperand];
610 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
611 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
612 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
613 let Name = "ImmSExti32i8";
617 def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass {
618 let Name = "ImmZExtu32u8";
623 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
624 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
625 let Name = "ImmSExti64i8";
626 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
627 ImmSExti64i32AsmOperand];
630 // A couple of more descriptive operand definitions.
631 // 16-bits but only 8 bits are significant.
632 def i16i8imm : Operand<i16> {
633 let ParserMatchClass = ImmSExti16i8AsmOperand;
634 let OperandType = "OPERAND_IMMEDIATE";
636 // 32-bits but only 8 bits are significant.
637 def i32i8imm : Operand<i32> {
638 let ParserMatchClass = ImmSExti32i8AsmOperand;
639 let OperandType = "OPERAND_IMMEDIATE";
641 // 32-bits but only 8 bits are significant, and those 8 bits are unsigned.
642 def u32u8imm : Operand<i32> {
643 let ParserMatchClass = ImmZExtu32u8AsmOperand;
644 let OperandType = "OPERAND_IMMEDIATE";
647 // 64-bits but only 32 bits are significant.
648 def i64i32imm : Operand<i64> {
649 let ParserMatchClass = ImmSExti64i32AsmOperand;
650 let OperandType = "OPERAND_IMMEDIATE";
653 // 64-bits but only 32 bits are significant, and those bits are treated as being
655 def i64i32imm_pcrel : Operand<i64> {
656 let PrintMethod = "printPCRelImm";
657 let ParserMatchClass = X86AbsMemAsmOperand;
658 let OperandType = "OPERAND_PCREL";
661 // 64-bits but only 8 bits are significant.
662 def i64i8imm : Operand<i64> {
663 let ParserMatchClass = ImmSExti64i8AsmOperand;
664 let OperandType = "OPERAND_IMMEDIATE";
667 def lea64_32mem : Operand<i32> {
668 let PrintMethod = "printi32mem";
669 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
670 let ParserMatchClass = X86MemAsmOperand;
673 // Memory operands that use 64-bit pointers in both ILP32 and LP64.
674 def lea64mem : Operand<i64> {
675 let PrintMethod = "printi64mem";
676 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
677 let ParserMatchClass = X86MemAsmOperand;
681 //===----------------------------------------------------------------------===//
682 // X86 Complex Pattern Definitions.
685 // Define X86 specific addressing mode.
686 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
687 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
688 [add, sub, mul, X86mul_imm, shl, or, frameindex],
690 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
691 def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr",
692 [add, sub, mul, X86mul_imm, shl, or,
693 frameindex, X86WrapperRIP],
696 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
697 [tglobaltlsaddr], []>;
699 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
700 [tglobaltlsaddr], []>;
702 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
703 [add, sub, mul, X86mul_imm, shl, or, frameindex,
706 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
707 [tglobaltlsaddr], []>;
709 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
710 [tglobaltlsaddr], []>;
712 //===----------------------------------------------------------------------===//
713 // X86 Instruction Predicate Definitions.
714 def HasCMov : Predicate<"Subtarget->hasCMov()">;
715 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
717 def HasMMX : Predicate<"Subtarget->hasMMX()">;
718 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
719 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
720 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
721 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
722 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
723 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
724 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
725 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
726 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
727 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
728 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
729 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
730 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
731 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
732 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
733 def HasAVX : Predicate<"Subtarget->hasAVX()">;
734 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
735 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
736 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">,
737 AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">;
738 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
739 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
740 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
741 def HasCDI : Predicate<"Subtarget->hasCDI()">;
742 def HasPFI : Predicate<"Subtarget->hasPFI()">;
743 def HasERI : Predicate<"Subtarget->hasERI()">;
745 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
746 def HasAES : Predicate<"Subtarget->hasAES()">;
747 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
748 def HasFMA : Predicate<"Subtarget->hasFMA()">;
749 def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">;
750 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
751 def HasXOP : Predicate<"Subtarget->hasXOP()">;
752 def HasTBM : Predicate<"Subtarget->hasTBM()">;
753 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
754 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
755 def HasF16C : Predicate<"Subtarget->hasF16C()">;
756 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
757 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
758 def HasBMI : Predicate<"Subtarget->hasBMI()">;
759 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
760 def HasRTM : Predicate<"Subtarget->hasRTM()">;
761 def HasHLE : Predicate<"Subtarget->hasHLE()">;
762 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
763 def HasADX : Predicate<"Subtarget->hasADX()">;
764 def HasSHA : Predicate<"Subtarget->hasSHA()">;
765 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
766 def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
767 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
768 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
769 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
770 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
771 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
772 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
773 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
774 AssemblerPredicate<"Mode64Bit", "64-bit mode">;
775 def In16BitMode : Predicate<"Subtarget->is16Bit()">,
776 AssemblerPredicate<"Mode16Bit", "16-bit mode">;
777 def Not16BitMode : Predicate<"!Subtarget->is16Bit()">,
778 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">;
779 def In32BitMode : Predicate<"Subtarget->is32Bit()">,
780 AssemblerPredicate<"Mode32Bit", "32-bit mode">;
781 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
782 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
783 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
784 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
785 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
786 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
787 "TM.getCodeModel() != CodeModel::Kernel">;
788 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
789 "TM.getCodeModel() == CodeModel::Kernel">;
790 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
791 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
792 def OptForSize : Predicate<"OptForSize">;
793 def OptForSpeed : Predicate<"!OptForSize">;
794 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
795 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
796 def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">;
798 //===----------------------------------------------------------------------===//
799 // X86 Instruction Format Definitions.
802 include "X86InstrFormats.td"
804 //===----------------------------------------------------------------------===//
805 // Pattern fragments.
808 // X86 specific condition code. These correspond to CondCode in
809 // X86InstrInfo.h. They must be kept in synch.
810 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
811 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
812 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
813 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
814 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
815 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
816 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
817 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
818 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
819 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
820 def X86_COND_NO : PatLeaf<(i8 10)>;
821 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
822 def X86_COND_NS : PatLeaf<(i8 12)>;
823 def X86_COND_O : PatLeaf<(i8 13)>;
824 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
825 def X86_COND_S : PatLeaf<(i8 15)>;
827 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
828 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
829 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
830 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
833 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
836 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
838 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
840 def i64immZExt32SExt8 : ImmLeaf<i64, [{
841 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
844 // Helper fragments for loads.
845 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
846 // known to be 32-bit aligned or better. Ditto for i8 to i16.
847 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
848 LoadSDNode *LD = cast<LoadSDNode>(N);
849 ISD::LoadExtType ExtType = LD->getExtensionType();
850 if (ExtType == ISD::NON_EXTLOAD)
852 if (ExtType == ISD::EXTLOAD)
853 return LD->getAlignment() >= 2 && !LD->isVolatile();
857 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
858 LoadSDNode *LD = cast<LoadSDNode>(N);
859 ISD::LoadExtType ExtType = LD->getExtensionType();
860 if (ExtType == ISD::EXTLOAD)
861 return LD->getAlignment() >= 2 && !LD->isVolatile();
865 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
866 LoadSDNode *LD = cast<LoadSDNode>(N);
867 ISD::LoadExtType ExtType = LD->getExtensionType();
868 if (ExtType == ISD::NON_EXTLOAD)
870 if (ExtType == ISD::EXTLOAD)
871 return LD->getAlignment() >= 4 && !LD->isVolatile();
875 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
876 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
877 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
878 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
879 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
881 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
882 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
883 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
884 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
885 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
886 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
888 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
889 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
890 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
891 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
892 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
893 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
894 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
895 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
896 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
897 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
899 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
900 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
901 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
902 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
903 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
904 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
905 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
906 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
907 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
908 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
911 // An 'and' node with a single use.
912 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
913 return N->hasOneUse();
915 // An 'srl' node with a single use.
916 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
917 return N->hasOneUse();
919 // An 'trunc' node with a single use.
920 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
921 return N->hasOneUse();
924 //===----------------------------------------------------------------------===//
929 let neverHasSideEffects = 1, SchedRW = [WriteZero] in {
930 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
931 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero),
932 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
933 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero),
934 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
938 // Constructing a stack frame.
939 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
940 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
942 let SchedRW = [WriteALU] in {
943 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
944 def LEAVE : I<0xC9, RawFrm,
945 (outs), (ins), "leave", [], IIC_LEAVE>,
946 Requires<[Not64BitMode]>;
948 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
949 def LEAVE64 : I<0xC9, RawFrm,
950 (outs), (ins), "leave", [], IIC_LEAVE>,
951 Requires<[In64BitMode]>;
954 //===----------------------------------------------------------------------===//
955 // Miscellaneous Instructions.
958 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
959 let mayLoad = 1, SchedRW = [WriteLoad] in {
960 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
961 IIC_POP_REG16>, OpSize16;
962 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
963 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
964 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
965 IIC_POP_REG>, OpSize16;
966 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
967 IIC_POP_MEM>, OpSize16;
968 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
969 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
970 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
971 IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>;
973 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>,
975 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
976 OpSize32, Requires<[Not64BitMode]>;
977 } // mayLoad, SchedRW
979 let mayStore = 1, SchedRW = [WriteStore] in {
980 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
981 IIC_PUSH_REG>, OpSize16;
982 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
983 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
984 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
985 IIC_PUSH_REG>, OpSize16;
986 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
987 IIC_PUSH_MEM>, OpSize16;
988 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
989 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
990 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
991 IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>;
993 def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
994 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
995 Requires<[Not64BitMode]>;
996 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
997 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
998 Requires<[Not64BitMode]>;
999 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1000 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1001 Requires<[Not64BitMode]>;
1002 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
1003 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1004 Requires<[Not64BitMode]>;
1006 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
1008 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
1009 OpSize32, Requires<[Not64BitMode]>;
1011 } // mayStore, SchedRW
1014 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
1015 let mayLoad = 1, SchedRW = [WriteLoad] in {
1016 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1017 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
1018 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1019 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
1020 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [],
1021 IIC_POP_MEM>, OpSize32, Requires<[In64BitMode]>;
1022 } // mayLoad, SchedRW
1023 let mayStore = 1, SchedRW = [WriteStore] in {
1024 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1025 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1026 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1027 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1028 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
1029 IIC_PUSH_MEM>, OpSize32, Requires<[In64BitMode]>;
1030 } // mayStore, SchedRW
1033 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1,
1034 SchedRW = [WriteStore] in {
1035 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
1036 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
1037 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1038 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1039 Requires<[In64BitMode]>;
1040 def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
1041 "push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1042 Requires<[In64BitMode]>;
1045 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
1046 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
1047 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>;
1048 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
1049 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
1050 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>;
1052 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
1053 mayLoad = 1, neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
1054 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>,
1055 OpSize32, Requires<[Not64BitMode]>;
1056 def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>,
1057 OpSize16, Requires<[Not64BitMode]>;
1059 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
1060 mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
1061 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>,
1062 OpSize32, Requires<[Not64BitMode]>;
1063 def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>,
1064 OpSize16, Requires<[Not64BitMode]>;
1067 let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
1068 // GR32 = bswap GR32
1069 def BSWAP32r : I<0xC8, AddRegFrm,
1070 (outs GR32:$dst), (ins GR32:$src),
1072 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB;
1074 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
1076 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
1077 } // Constraints = "$src = $dst", SchedRW
1079 // Bit scan instructions.
1080 let Defs = [EFLAGS] in {
1081 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1082 "bsf{w}\t{$src, $dst|$dst, $src}",
1083 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
1084 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1085 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1086 "bsf{w}\t{$src, $dst|$dst, $src}",
1087 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
1088 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1089 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1090 "bsf{l}\t{$src, $dst|$dst, $src}",
1091 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
1092 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1093 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1094 "bsf{l}\t{$src, $dst|$dst, $src}",
1095 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
1096 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1097 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1098 "bsf{q}\t{$src, $dst|$dst, $src}",
1099 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
1100 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1101 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1102 "bsf{q}\t{$src, $dst|$dst, $src}",
1103 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
1104 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1106 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1107 "bsr{w}\t{$src, $dst|$dst, $src}",
1108 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))],
1109 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1110 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1111 "bsr{w}\t{$src, $dst|$dst, $src}",
1112 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
1113 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1114 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1115 "bsr{l}\t{$src, $dst|$dst, $src}",
1116 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
1117 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1118 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1119 "bsr{l}\t{$src, $dst|$dst, $src}",
1120 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
1121 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1122 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1123 "bsr{q}\t{$src, $dst|$dst, $src}",
1124 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))],
1125 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1126 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1127 "bsr{q}\t{$src, $dst|$dst, $src}",
1128 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
1129 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1130 } // Defs = [EFLAGS]
1132 let SchedRW = [WriteMicrocoded] in {
1133 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1134 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
1135 def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src),
1136 "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1137 def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src),
1138 "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16;
1139 def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src),
1140 "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize32;
1141 def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src),
1142 "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1145 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1146 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
1147 def STOSB : I<0xAA, RawFrmDst, (outs dstidx8:$dst), (ins),
1148 "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>;
1149 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
1150 def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins),
1151 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16;
1152 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
1153 def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins),
1154 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32;
1155 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
1156 def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins),
1157 "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>;
1159 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1160 let Defs = [EDI,EFLAGS], Uses = [AL,EDI,EFLAGS] in
1161 def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst),
1162 "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>;
1163 let Defs = [EDI,EFLAGS], Uses = [AX,EDI,EFLAGS] in
1164 def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst),
1165 "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16;
1166 let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,EFLAGS] in
1167 def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst),
1168 "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32;
1169 let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,EFLAGS] in
1170 def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst),
1171 "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>;
1173 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1174 let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,EFLAGS] in {
1175 def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src),
1176 "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1177 def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src),
1178 "cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16;
1179 def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src),
1180 "cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize32;
1181 def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src),
1182 "cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1186 //===----------------------------------------------------------------------===//
1187 // Move Instructions.
1189 let SchedRW = [WriteMove] in {
1190 let neverHasSideEffects = 1 in {
1191 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1192 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1193 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1194 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1195 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1196 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1197 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1198 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1201 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1202 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1203 "mov{b}\t{$src, $dst|$dst, $src}",
1204 [(set GR8:$dst, imm:$src)], IIC_MOV>;
1205 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1206 "mov{w}\t{$src, $dst|$dst, $src}",
1207 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize16;
1208 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1209 "mov{l}\t{$src, $dst|$dst, $src}",
1210 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize32;
1211 def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1212 "mov{q}\t{$src, $dst|$dst, $src}",
1213 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
1215 let isReMaterializable = 1 in {
1216 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
1217 "movabs{q}\t{$src, $dst|$dst, $src}",
1218 [(set GR64:$dst, imm:$src)], IIC_MOV>;
1221 // Longer forms that use a ModR/M byte. Needed for disassembler
1222 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1223 def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src),
1224 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1225 def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src),
1226 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1227 def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src),
1228 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1232 let SchedRW = [WriteStore] in {
1233 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1234 "mov{b}\t{$src, $dst|$dst, $src}",
1235 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
1236 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1237 "mov{w}\t{$src, $dst|$dst, $src}",
1238 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
1239 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1240 "mov{l}\t{$src, $dst|$dst, $src}",
1241 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32;
1242 def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1243 "mov{q}\t{$src, $dst|$dst, $src}",
1244 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
1247 let hasSideEffects = 0 in {
1249 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
1250 /// 32-bit offset from the segment base. These are only valid in x86-32 mode.
1251 let SchedRW = [WriteALU] in {
1252 let mayLoad = 1 in {
1254 def MOV8o8a : Ii32 <0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
1255 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
1256 Requires<[In32BitMode]>;
1258 def MOV16o16a : Ii32 <0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
1259 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1260 OpSize16, Requires<[In32BitMode]>;
1262 def MOV32o32a : Ii32 <0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
1263 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1264 OpSize32, Requires<[In32BitMode]>;
1267 def MOV8o8a_16 : Ii16 <0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
1268 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
1269 AdSize, Requires<[In16BitMode]>;
1271 def MOV16o16a_16 : Ii16 <0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
1272 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1273 OpSize16, AdSize, Requires<[In16BitMode]>;
1275 def MOV32o32a_16 : Ii16 <0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
1276 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1277 AdSize, OpSize32, Requires<[In16BitMode]>;
1279 let mayStore = 1 in {
1281 def MOV8ao8 : Ii32 <0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
1282 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
1283 Requires<[In32BitMode]>;
1285 def MOV16ao16 : Ii32 <0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
1286 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1287 OpSize16, Requires<[In32BitMode]>;
1289 def MOV32ao32 : Ii32 <0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
1290 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1291 OpSize32, Requires<[In32BitMode]>;
1294 def MOV8ao8_16 : Ii16 <0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
1295 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
1296 AdSize, Requires<[In16BitMode]>;
1298 def MOV16ao16_16 : Ii16 <0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
1299 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1300 OpSize16, AdSize, Requires<[In16BitMode]>;
1302 def MOV32ao32_16 : Ii16 <0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
1303 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1304 OpSize32, AdSize, Requires<[In16BitMode]>;
1308 // These forms all have full 64-bit absolute addresses in their instructions
1309 // and use the movabs mnemonic to indicate this specific form.
1310 let mayLoad = 1 in {
1312 def MOV64o8a : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
1313 "movabs{b}\t{$src, %al|al, $src}", []>,
1314 Requires<[In64BitMode]>;
1316 def MOV64o16a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
1317 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16,
1318 Requires<[In64BitMode]>;
1320 def MOV64o32a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
1321 "movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32,
1322 Requires<[In64BitMode]>;
1324 def MOV64o64a : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64:$src),
1325 "movabs{q}\t{$src, %rax|rax, $src}", []>,
1326 Requires<[In64BitMode]>;
1329 let mayStore = 1 in {
1331 def MOV64ao8 : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
1332 "movabs{b}\t{%al, $dst|$dst, al}", []>,
1333 Requires<[In64BitMode]>;
1335 def MOV64ao16 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
1336 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16,
1337 Requires<[In64BitMode]>;
1339 def MOV64ao32 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
1340 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32,
1341 Requires<[In64BitMode]>;
1343 def MOV64ao64 : RIi64<0xA3, RawFrmMemOffs, (outs offset64:$dst), (ins),
1344 "movabs{q}\t{%rax, $dst|$dst, rax}", []>,
1345 Requires<[In64BitMode]>;
1347 } // hasSideEffects = 0
1349 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
1350 SchedRW = [WriteMove] in {
1351 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1352 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1353 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1354 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1355 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1356 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1357 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1358 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1361 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1362 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1363 "mov{b}\t{$src, $dst|$dst, $src}",
1364 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1365 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1366 "mov{w}\t{$src, $dst|$dst, $src}",
1367 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize16;
1368 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1369 "mov{l}\t{$src, $dst|$dst, $src}",
1370 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32;
1371 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1372 "mov{q}\t{$src, $dst|$dst, $src}",
1373 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1376 let SchedRW = [WriteStore] in {
1377 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1378 "mov{b}\t{$src, $dst|$dst, $src}",
1379 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1380 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1381 "mov{w}\t{$src, $dst|$dst, $src}",
1382 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
1383 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1384 "mov{l}\t{$src, $dst|$dst, $src}",
1385 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32;
1386 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1387 "mov{q}\t{$src, $dst|$dst, $src}",
1388 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1391 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1392 // that they can be used for copying and storing h registers, which can't be
1393 // encoded when a REX prefix is present.
1394 let isCodeGenOnly = 1 in {
1395 let neverHasSideEffects = 1 in
1396 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1397 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1398 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
1400 let mayStore = 1, neverHasSideEffects = 1 in
1401 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1402 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1403 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1404 IIC_MOV_MEM>, Sched<[WriteStore]>;
1405 let mayLoad = 1, neverHasSideEffects = 1,
1406 canFoldAsLoad = 1, isReMaterializable = 1 in
1407 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1408 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1409 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1410 IIC_MOV_MEM>, Sched<[WriteLoad]>;
1414 // Condition code ops, incl. set if equal/not equal/...
1415 let SchedRW = [WriteALU] in {
1416 let Defs = [EFLAGS], Uses = [AH] in
1417 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1418 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
1419 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
1420 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1421 IIC_AHF>; // AH = flags
1424 //===----------------------------------------------------------------------===//
1425 // Bit tests instructions: BT, BTS, BTR, BTC.
1427 let Defs = [EFLAGS] in {
1428 let SchedRW = [WriteALU] in {
1429 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1430 "bt{w}\t{$src2, $src1|$src1, $src2}",
1431 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1433 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1434 "bt{l}\t{$src2, $src1|$src1, $src2}",
1435 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,
1437 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1438 "bt{q}\t{$src2, $src1|$src1, $src2}",
1439 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1442 // Unlike with the register+register form, the memory+register form of the
1443 // bt instruction does not ignore the high bits of the index. From ISel's
1444 // perspective, this is pretty bizarre. Make these instructions disassembly
1447 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
1448 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1449 "bt{w}\t{$src2, $src1|$src1, $src2}",
1450 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1451 // (implicit EFLAGS)]
1453 >, OpSize16, TB, Requires<[FastBTMem]>;
1454 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1455 "bt{l}\t{$src2, $src1|$src1, $src2}",
1456 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1457 // (implicit EFLAGS)]
1459 >, OpSize32, TB, Requires<[FastBTMem]>;
1460 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1461 "bt{q}\t{$src2, $src1|$src1, $src2}",
1462 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1463 // (implicit EFLAGS)]
1468 let SchedRW = [WriteALU] in {
1469 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1470 "bt{w}\t{$src2, $src1|$src1, $src2}",
1471 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1472 IIC_BT_RI>, OpSize16, TB;
1473 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1474 "bt{l}\t{$src2, $src1|$src1, $src2}",
1475 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1476 IIC_BT_RI>, OpSize32, TB;
1477 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1478 "bt{q}\t{$src2, $src1|$src1, $src2}",
1479 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1483 // Note that these instructions don't need FastBTMem because that
1484 // only applies when the other operand is in a register. When it's
1485 // an immediate, bt is still fast.
1486 let SchedRW = [WriteALU] in {
1487 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1488 "bt{w}\t{$src2, $src1|$src1, $src2}",
1489 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1490 ], IIC_BT_MI>, OpSize16, TB;
1491 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1492 "bt{l}\t{$src2, $src1|$src1, $src2}",
1493 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1494 ], IIC_BT_MI>, OpSize32, TB;
1495 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1496 "bt{q}\t{$src2, $src1|$src1, $src2}",
1497 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1498 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1501 let hasSideEffects = 0 in {
1502 let SchedRW = [WriteALU] in {
1503 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1504 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1506 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1507 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1509 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1510 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1513 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1514 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1515 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1517 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1518 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1520 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1521 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1524 let SchedRW = [WriteALU] in {
1525 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1526 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1528 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1529 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1531 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1532 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1535 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1536 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1537 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1539 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1540 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1542 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1543 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1546 let SchedRW = [WriteALU] in {
1547 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1548 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1550 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1551 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1553 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1554 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1557 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1558 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1559 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1561 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1562 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1564 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1565 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1568 let SchedRW = [WriteALU] in {
1569 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1570 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1572 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1573 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1575 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1576 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1579 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1580 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1581 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1583 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1584 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1586 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1587 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1590 let SchedRW = [WriteALU] in {
1591 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1592 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1594 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1595 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1597 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1598 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1601 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1602 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1603 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1605 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1606 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1608 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1609 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1612 let SchedRW = [WriteALU] in {
1613 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1614 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1616 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1617 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1619 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1620 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1623 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1624 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1625 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1627 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1628 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1630 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1631 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1633 } // hasSideEffects = 0
1634 } // Defs = [EFLAGS]
1637 //===----------------------------------------------------------------------===//
1641 // Atomic swap. These are just normal xchg instructions. But since a memory
1642 // operand is referenced, the atomicity is ensured.
1643 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
1644 InstrItinClass itin> {
1645 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
1646 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
1647 (ins GR8:$val, i8mem:$ptr),
1648 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
1651 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
1653 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
1654 (ins GR16:$val, i16mem:$ptr),
1655 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
1658 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
1660 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
1661 (ins GR32:$val, i32mem:$ptr),
1662 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
1665 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
1667 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
1668 (ins GR64:$val, i64mem:$ptr),
1669 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
1672 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
1677 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
1679 // Swap between registers.
1680 let SchedRW = [WriteALU] in {
1681 let Constraints = "$val = $dst" in {
1682 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1683 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1684 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1685 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1687 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1688 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1690 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1691 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1694 // Swap between EAX and other registers.
1695 let Uses = [AX], Defs = [AX] in
1696 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1697 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16;
1698 let Uses = [EAX], Defs = [EAX] in
1699 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1700 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1701 OpSize32, Requires<[Not64BitMode]>;
1702 let Uses = [EAX], Defs = [EAX] in
1703 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1704 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1705 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1706 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1707 OpSize32, Requires<[In64BitMode]>;
1708 let Uses = [RAX], Defs = [RAX] in
1709 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1710 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>;
1713 let SchedRW = [WriteALU] in {
1714 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1715 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1716 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1717 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1719 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1720 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1722 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1723 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1726 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1727 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1728 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1729 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1730 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1732 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1733 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1735 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1736 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1740 let SchedRW = [WriteALU] in {
1741 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1742 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1743 IIC_CMPXCHG_REG8>, TB;
1744 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1745 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1746 IIC_CMPXCHG_REG>, TB, OpSize16;
1747 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1748 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1749 IIC_CMPXCHG_REG>, TB, OpSize32;
1750 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1751 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1752 IIC_CMPXCHG_REG>, TB;
1755 let SchedRW = [WriteALULd, WriteRMW] in {
1756 let mayLoad = 1, mayStore = 1 in {
1757 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1758 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1759 IIC_CMPXCHG_MEM8>, TB;
1760 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1761 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1762 IIC_CMPXCHG_MEM>, TB, OpSize16;
1763 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1764 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1765 IIC_CMPXCHG_MEM>, TB, OpSize32;
1766 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1767 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1768 IIC_CMPXCHG_MEM>, TB;
1771 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1772 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1773 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1775 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1776 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1777 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1778 TB, Requires<[HasCmpxchg16b]>;
1782 // Lock instruction prefix
1783 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1785 // Rex64 instruction prefix
1786 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>,
1787 Requires<[In64BitMode]>;
1789 // Data16 instruction prefix
1790 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1792 // Repeat string operation instruction prefixes
1793 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1794 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1795 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1796 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1797 // Repeat while not equal (used with CMPS and SCAS)
1798 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1802 // String manipulation instructions
1803 let SchedRW = [WriteMicrocoded] in {
1804 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1805 let Defs = [AL,ESI], Uses = [ESI,EFLAGS] in
1806 def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src),
1807 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>;
1808 let Defs = [AX,ESI], Uses = [ESI,EFLAGS] in
1809 def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src),
1810 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16;
1811 let Defs = [EAX,ESI], Uses = [ESI,EFLAGS] in
1812 def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src),
1813 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32;
1814 let Defs = [RAX,ESI], Uses = [ESI,EFLAGS] in
1815 def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),
1816 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>;
1819 let SchedRW = [WriteSystem] in {
1820 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1821 let Defs = [ESI], Uses = [DX,ESI,EFLAGS] in {
1822 def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src),
1823 "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>;
1824 def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src),
1825 "outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16;
1826 def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src),
1827 "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32;
1830 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1831 let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in {
1832 def INSB : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins),
1833 "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
1834 def INSW : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins),
1835 "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
1836 def INSL : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins),
1837 "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32;
1841 // Flag instructions
1842 let SchedRW = [WriteALU] in {
1843 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1844 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1845 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1846 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1847 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1848 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1849 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1851 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1854 // Table lookup instructions
1855 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,
1858 let SchedRW = [WriteMicrocoded] in {
1859 // ASCII Adjust After Addition
1860 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1861 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1862 Requires<[Not64BitMode]>;
1864 // ASCII Adjust AX Before Division
1865 // sets AL, AH and EFLAGS and uses AL and AH
1866 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1867 "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>;
1869 // ASCII Adjust AX After Multiply
1870 // sets AL, AH and EFLAGS and uses AL
1871 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1872 "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>;
1874 // ASCII Adjust AL After Subtraction - sets
1875 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1876 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1877 Requires<[Not64BitMode]>;
1879 // Decimal Adjust AL after Addition
1880 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1881 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1882 Requires<[Not64BitMode]>;
1884 // Decimal Adjust AL after Subtraction
1885 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1886 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1887 Requires<[Not64BitMode]>;
1890 let SchedRW = [WriteSystem] in {
1891 // Check Array Index Against Bounds
1892 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1893 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,
1894 Requires<[Not64BitMode]>;
1895 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1896 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize32,
1897 Requires<[Not64BitMode]>;
1899 // Adjust RPL Field of Segment Selector
1900 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1901 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1902 Requires<[Not64BitMode]>;
1903 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1904 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1905 Requires<[Not64BitMode]>;
1908 //===----------------------------------------------------------------------===//
1909 // MOVBE Instructions
1911 let Predicates = [HasMOVBE] in {
1912 let SchedRW = [WriteALULd] in {
1913 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1914 "movbe{w}\t{$src, $dst|$dst, $src}",
1915 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1917 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1918 "movbe{l}\t{$src, $dst|$dst, $src}",
1919 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1921 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1922 "movbe{q}\t{$src, $dst|$dst, $src}",
1923 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
1926 let SchedRW = [WriteStore] in {
1927 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1928 "movbe{w}\t{$src, $dst|$dst, $src}",
1929 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1931 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1932 "movbe{l}\t{$src, $dst|$dst, $src}",
1933 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1935 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1936 "movbe{q}\t{$src, $dst|$dst, $src}",
1937 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
1942 //===----------------------------------------------------------------------===//
1943 // RDRAND Instruction
1945 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1946 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1948 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
1949 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1951 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, TB;
1952 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1954 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
1957 //===----------------------------------------------------------------------===//
1958 // RDSEED Instruction
1960 let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
1961 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
1963 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
1964 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
1966 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB;
1967 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
1969 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
1972 //===----------------------------------------------------------------------===//
1973 // LZCNT Instruction
1975 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
1976 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1977 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1978 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
1980 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1981 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1982 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
1983 (implicit EFLAGS)]>, XS, OpSize16;
1985 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1986 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1987 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS,
1989 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1990 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1991 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
1992 (implicit EFLAGS)]>, XS, OpSize32;
1994 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1995 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1996 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
1998 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1999 "lzcnt{q}\t{$src, $dst|$dst, $src}",
2000 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
2001 (implicit EFLAGS)]>, XS;
2004 //===----------------------------------------------------------------------===//
2007 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2008 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2009 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2010 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
2012 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2013 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2014 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
2015 (implicit EFLAGS)]>, XS, OpSize16;
2017 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2018 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2019 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS,
2021 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2022 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2023 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
2024 (implicit EFLAGS)]>, XS, OpSize32;
2026 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2027 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2028 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
2030 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2031 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2032 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
2033 (implicit EFLAGS)]>, XS;
2036 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
2037 RegisterClass RC, X86MemOperand x86memop> {
2038 let hasSideEffects = 0 in {
2039 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
2040 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2043 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
2044 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2049 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2050 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>;
2051 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
2052 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>;
2053 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W;
2054 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>;
2055 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W;
2058 //===----------------------------------------------------------------------===//
2059 // Pattern fragments to auto generate BMI instructions.
2060 //===----------------------------------------------------------------------===//
2062 let Predicates = [HasBMI] in {
2063 // FIXME: patterns for the load versions are not implemented
2064 def : Pat<(and GR32:$src, (add GR32:$src, -1)),
2065 (BLSR32rr GR32:$src)>;
2066 def : Pat<(and GR64:$src, (add GR64:$src, -1)),
2067 (BLSR64rr GR64:$src)>;
2069 def : Pat<(xor GR32:$src, (add GR32:$src, -1)),
2070 (BLSMSK32rr GR32:$src)>;
2071 def : Pat<(xor GR64:$src, (add GR64:$src, -1)),
2072 (BLSMSK64rr GR64:$src)>;
2074 def : Pat<(and GR32:$src, (ineg GR32:$src)),
2075 (BLSI32rr GR32:$src)>;
2076 def : Pat<(and GR64:$src, (ineg GR64:$src)),
2077 (BLSI64rr GR64:$src)>;
2080 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
2081 X86MemOperand x86memop, Intrinsic Int,
2083 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2084 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2085 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
2087 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
2088 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2089 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
2090 (implicit EFLAGS)]>, T8PS, VEX_4VOp3;
2093 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2094 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
2095 int_x86_bmi_bextr_32, loadi32>;
2096 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
2097 int_x86_bmi_bextr_64, loadi64>, VEX_W;
2100 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
2101 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
2102 int_x86_bmi_bzhi_32, loadi32>;
2103 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
2104 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
2107 def : Pat<(X86bzhi GR32:$src1, GR8:$src2),
2108 (BZHI32rr GR32:$src1,
2109 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
2110 def : Pat<(X86bzhi (loadi32 addr:$src1), GR8:$src2),
2111 (BZHI32rm addr:$src1,
2112 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
2113 def : Pat<(X86bzhi GR64:$src1, GR8:$src2),
2114 (BZHI64rr GR64:$src1,
2115 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
2116 def : Pat<(X86bzhi (loadi64 addr:$src1), GR8:$src2),
2117 (BZHI64rm addr:$src1,
2118 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
2120 let Predicates = [HasBMI] in {
2121 def : Pat<(X86bextr GR32:$src1, GR32:$src2),
2122 (BEXTR32rr GR32:$src1, GR32:$src2)>;
2123 def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2),
2124 (BEXTR32rm addr:$src1, GR32:$src2)>;
2125 def : Pat<(X86bextr GR64:$src1, GR64:$src2),
2126 (BEXTR64rr GR64:$src1, GR64:$src2)>;
2127 def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2),
2128 (BEXTR64rm addr:$src1, GR64:$src2)>;
2131 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
2132 X86MemOperand x86memop, Intrinsic Int,
2134 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2135 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2136 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
2138 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2139 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2140 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
2143 let Predicates = [HasBMI2] in {
2144 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
2145 int_x86_bmi_pdep_32, loadi32>, T8XD;
2146 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
2147 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
2148 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
2149 int_x86_bmi_pext_32, loadi32>, T8XS;
2150 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
2151 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
2154 //===----------------------------------------------------------------------===//
2157 let Predicates = [HasTBM], Defs = [EFLAGS] in {
2159 multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr,
2160 X86MemOperand x86memop, PatFrag ld_frag,
2161 Intrinsic Int, Operand immtype,
2162 SDPatternOperator immoperator> {
2163 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
2164 !strconcat(OpcodeStr,
2165 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2166 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>,
2168 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst),
2169 (ins x86memop:$src1, immtype:$cntl),
2170 !strconcat(OpcodeStr,
2171 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2172 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>,
2176 defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32,
2177 int_x86_tbm_bextri_u32, i32imm, imm>;
2178 let ImmT = Imm32S in
2179 defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64,
2180 int_x86_tbm_bextri_u64, i64i32imm,
2181 i64immSExt32>, VEX_W;
2183 multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem,
2184 RegisterClass RC, string OpcodeStr,
2185 X86MemOperand x86memop, PatFrag ld_frag> {
2186 let hasSideEffects = 0 in {
2187 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src),
2188 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2191 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src),
2192 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2197 multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr,
2198 Format FormReg, Format FormMem> {
2199 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem,
2201 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem,
2205 defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
2206 defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>;
2207 defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>;
2208 defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>;
2209 defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>;
2210 defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>;
2211 defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>;
2212 defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>;
2213 defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>;
2216 //===----------------------------------------------------------------------===//
2217 // Pattern fragments to auto generate TBM instructions.
2218 //===----------------------------------------------------------------------===//
2220 let Predicates = [HasTBM] in {
2221 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)),
2222 (BEXTRI32ri GR32:$src1, imm:$src2)>;
2223 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)),
2224 (BEXTRI32mi addr:$src1, imm:$src2)>;
2225 def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2),
2226 (BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>;
2227 def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2),
2228 (BEXTRI64mi addr:$src1, i64immSExt32:$src2)>;
2230 // FIXME: patterns for the load versions are not implemented
2231 def : Pat<(and GR32:$src, (add GR32:$src, 1)),
2232 (BLCFILL32rr GR32:$src)>;
2233 def : Pat<(and GR64:$src, (add GR64:$src, 1)),
2234 (BLCFILL64rr GR64:$src)>;
2236 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
2237 (BLCI32rr GR32:$src)>;
2238 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
2239 (BLCI64rr GR64:$src)>;
2241 // Extra patterns because opt can optimize the above patterns to this.
2242 def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
2243 (BLCI32rr GR32:$src)>;
2244 def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
2245 (BLCI64rr GR64:$src)>;
2247 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
2248 (BLCIC32rr GR32:$src)>;
2249 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),
2250 (BLCIC64rr GR64:$src)>;
2252 def : Pat<(xor GR32:$src, (add GR32:$src, 1)),
2253 (BLCMSK32rr GR32:$src)>;
2254 def : Pat<(xor GR64:$src, (add GR64:$src, 1)),
2255 (BLCMSK64rr GR64:$src)>;
2257 def : Pat<(or GR32:$src, (add GR32:$src, 1)),
2258 (BLCS32rr GR32:$src)>;
2259 def : Pat<(or GR64:$src, (add GR64:$src, 1)),
2260 (BLCS64rr GR64:$src)>;
2262 def : Pat<(or GR32:$src, (add GR32:$src, -1)),
2263 (BLSFILL32rr GR32:$src)>;
2264 def : Pat<(or GR64:$src, (add GR64:$src, -1)),
2265 (BLSFILL64rr GR64:$src)>;
2267 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
2268 (BLSIC32rr GR32:$src)>;
2269 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)),
2270 (BLSIC64rr GR64:$src)>;
2272 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)),
2273 (T1MSKC32rr GR32:$src)>;
2274 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)),
2275 (T1MSKC64rr GR64:$src)>;
2277 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)),
2278 (TZMSK32rr GR32:$src)>;
2279 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)),
2280 (TZMSK64rr GR64:$src)>;
2283 //===----------------------------------------------------------------------===//
2285 //===----------------------------------------------------------------------===//
2287 include "X86InstrArithmetic.td"
2288 include "X86InstrCMovSetCC.td"
2289 include "X86InstrExtension.td"
2290 include "X86InstrControl.td"
2291 include "X86InstrShiftRotate.td"
2293 // X87 Floating Point Stack.
2294 include "X86InstrFPStack.td"
2296 // SIMD support (SSE, MMX and AVX)
2297 include "X86InstrFragmentsSIMD.td"
2299 // FMA - Fused Multiply-Add support (requires FMA)
2300 include "X86InstrFMA.td"
2303 include "X86InstrXOP.td"
2305 // SSE, MMX and 3DNow! vector support.
2306 include "X86InstrSSE.td"
2307 include "X86InstrAVX512.td"
2308 include "X86InstrMMX.td"
2309 include "X86Instr3DNow.td"
2311 include "X86InstrVMX.td"
2312 include "X86InstrSVM.td"
2314 include "X86InstrTSX.td"
2316 // System instructions.
2317 include "X86InstrSystem.td"
2319 // Compiler Pseudo Instructions and Pat Patterns
2320 include "X86InstrCompiler.td"
2322 //===----------------------------------------------------------------------===//
2323 // Assembler Mnemonic Aliases
2324 //===----------------------------------------------------------------------===//
2326 def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>;
2327 def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>;
2328 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;
2330 def : MnemonicAlias<"cbw", "cbtw", "att">;
2331 def : MnemonicAlias<"cwde", "cwtl", "att">;
2332 def : MnemonicAlias<"cwd", "cwtd", "att">;
2333 def : MnemonicAlias<"cdq", "cltd", "att">;
2334 def : MnemonicAlias<"cdqe", "cltq", "att">;
2335 def : MnemonicAlias<"cqo", "cqto", "att">;
2337 // In 64-bit mode lret maps to lretl; it is not ambiguous with lretq.
2338 def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>;
2339 def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>;
2341 def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>;
2342 def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>;
2344 def : MnemonicAlias<"loopz", "loope", "att">;
2345 def : MnemonicAlias<"loopnz", "loopne", "att">;
2347 def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>;
2348 def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>;
2349 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>;
2350 def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>;
2351 def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>;
2352 def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>;
2353 def : MnemonicAlias<"popfd", "popfl", "att">;
2355 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
2356 // all modes. However: "push (addr)" and "push $42" should default to
2357 // pushl/pushq depending on the current mode. Similar for "pop %bx"
2358 def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>;
2359 def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>;
2360 def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>;
2361 def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>;
2362 def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>;
2363 def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
2364 def : MnemonicAlias<"pushfd", "pushfl", "att">;
2366 def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>;
2367 def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>;
2368 def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>;
2369 def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>;
2370 def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>;
2371 def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>;
2373 def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>;
2374 def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>;
2375 def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>;
2376 def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>;
2378 def : MnemonicAlias<"repe", "rep", "att">;
2379 def : MnemonicAlias<"repz", "rep", "att">;
2380 def : MnemonicAlias<"repnz", "repne", "att">;
2382 def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>;
2383 def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>;
2384 def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>;
2386 def : MnemonicAlias<"salb", "shlb", "att">;
2387 def : MnemonicAlias<"salw", "shlw", "att">;
2388 def : MnemonicAlias<"sall", "shll", "att">;
2389 def : MnemonicAlias<"salq", "shlq", "att">;
2391 def : MnemonicAlias<"smovb", "movsb", "att">;
2392 def : MnemonicAlias<"smovw", "movsw", "att">;
2393 def : MnemonicAlias<"smovl", "movsl", "att">;
2394 def : MnemonicAlias<"smovq", "movsq", "att">;
2396 def : MnemonicAlias<"ud2a", "ud2", "att">;
2397 def : MnemonicAlias<"verrw", "verr", "att">;
2399 // System instruction aliases.
2400 def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>;
2401 def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>;
2402 def : MnemonicAlias<"sysret", "sysretl", "att">;
2403 def : MnemonicAlias<"sysexit", "sysexitl", "att">;
2405 def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>;
2406 def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>;
2407 def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>;
2408 def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>;
2409 def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>;
2410 def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>;
2411 def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>;
2412 def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>;
2413 def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>;
2414 def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>;
2415 def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>;
2416 def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>;
2419 // Floating point stack aliases.
2420 def : MnemonicAlias<"fcmovz", "fcmove", "att">;
2421 def : MnemonicAlias<"fcmova", "fcmovnbe", "att">;
2422 def : MnemonicAlias<"fcmovnae", "fcmovb", "att">;
2423 def : MnemonicAlias<"fcmovna", "fcmovbe", "att">;
2424 def : MnemonicAlias<"fcmovae", "fcmovnb", "att">;
2425 def : MnemonicAlias<"fcomip", "fcompi", "att">;
2426 def : MnemonicAlias<"fildq", "fildll", "att">;
2427 def : MnemonicAlias<"fistpq", "fistpll", "att">;
2428 def : MnemonicAlias<"fisttpq", "fisttpll", "att">;
2429 def : MnemonicAlias<"fldcww", "fldcw", "att">;
2430 def : MnemonicAlias<"fnstcww", "fnstcw", "att">;
2431 def : MnemonicAlias<"fnstsww", "fnstsw", "att">;
2432 def : MnemonicAlias<"fucomip", "fucompi", "att">;
2433 def : MnemonicAlias<"fwait", "wait", "att">;
2436 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond,
2438 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
2439 !strconcat(Prefix, NewCond, Suffix), VariantName>;
2441 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
2442 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
2443 /// example "setz" -> "sete".
2444 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix,
2446 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb
2447 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete
2448 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe
2449 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae
2450 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae
2451 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle
2452 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge
2453 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne
2454 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp
2455 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp
2457 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb
2458 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta
2459 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl
2460 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg
2463 // Aliases for set<CC>
2464 defm : IntegerCondCodeMnemonicAlias<"set", "">;
2465 // Aliases for j<CC>
2466 defm : IntegerCondCodeMnemonicAlias<"j", "">;
2467 // Aliases for cmov<CC>{w,l,q}
2468 defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">;
2469 defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">;
2470 defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">;
2471 // No size suffix for intel-style asm.
2472 defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">;
2475 //===----------------------------------------------------------------------===//
2476 // Assembler Instruction Aliases
2477 //===----------------------------------------------------------------------===//
2479 // aad/aam default to base 10 if no operand is specified.
2480 def : InstAlias<"aad", (AAD8i8 10)>;
2481 def : InstAlias<"aam", (AAM8i8 10)>;
2483 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
2484 // Likewise for btc/btr/bts.
2485 def : InstAlias<"bt {$imm, $mem|$mem, $imm}",
2486 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2487 def : InstAlias<"btc {$imm, $mem|$mem, $imm}",
2488 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2489 def : InstAlias<"btr {$imm, $mem|$mem, $imm}",
2490 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2491 def : InstAlias<"bts {$imm, $mem|$mem, $imm}",
2492 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2495 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>;
2496 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>;
2497 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>;
2498 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;
2500 // lods aliases. Accept the destination being omitted because it's implicit
2501 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2502 // in the destination.
2503 def : InstAlias<"lodsb $src", (LODSB srcidx8:$src), 0>;
2504 def : InstAlias<"lodsw $src", (LODSW srcidx16:$src), 0>;
2505 def : InstAlias<"lods{l|d} $src", (LODSL srcidx32:$src), 0>;
2506 def : InstAlias<"lodsq $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2507 def : InstAlias<"lods {$src, %al|al, $src}", (LODSB srcidx8:$src), 0>;
2508 def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>;
2509 def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>;
2510 def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2512 // stos aliases. Accept the source being omitted because it's implicit in
2513 // the mnemonic, or the mnemonic suffix being omitted because it's implicit
2515 def : InstAlias<"stosb $dst", (STOSB dstidx8:$dst), 0>;
2516 def : InstAlias<"stosw $dst", (STOSW dstidx16:$dst), 0>;
2517 def : InstAlias<"stos{l|d} $dst", (STOSL dstidx32:$dst), 0>;
2518 def : InstAlias<"stosq $dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2519 def : InstAlias<"stos {%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>;
2520 def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>;
2521 def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>;
2522 def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2524 // scas aliases. Accept the destination being omitted because it's implicit
2525 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2526 // in the destination.
2527 def : InstAlias<"scasb $dst", (SCASB dstidx8:$dst), 0>;
2528 def : InstAlias<"scasw $dst", (SCASW dstidx16:$dst), 0>;
2529 def : InstAlias<"scas{l|d} $dst", (SCASL dstidx32:$dst), 0>;
2530 def : InstAlias<"scasq $dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2531 def : InstAlias<"scas {$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>;
2532 def : InstAlias<"scas {$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>;
2533 def : InstAlias<"scas {$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>;
2534 def : InstAlias<"scas {$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2536 // div and idiv aliases for explicit A register.
2537 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
2538 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
2539 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>;
2540 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>;
2541 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>;
2542 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>;
2543 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>;
2544 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>;
2545 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>;
2546 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>;
2547 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>;
2548 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>;
2549 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>;
2550 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>;
2551 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;
2552 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;
2556 // Various unary fpstack operations default to operating on on ST1.
2557 // For example, "fxch" -> "fxch %st(1)"
2558 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
2559 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
2560 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
2561 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
2562 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
2563 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
2564 def : InstAlias<"fxch", (XCH_F ST1), 0>;
2565 def : InstAlias<"fcom", (COM_FST0r ST1), 0>;
2566 def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>;
2567 def : InstAlias<"fcomi", (COM_FIr ST1), 0>;
2568 def : InstAlias<"fcompi", (COM_FIPr ST1), 0>;
2569 def : InstAlias<"fucom", (UCOM_Fr ST1), 0>;
2570 def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>;
2571 def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>;
2572 def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>;
2574 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
2575 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
2576 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
2578 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
2579 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"),
2580 (Inst RST:$op), EmitAlias>;
2581 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"),
2582 (Inst ST0), EmitAlias>;
2585 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
2586 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
2587 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
2588 defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>;
2589 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
2590 defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>;
2591 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
2592 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
2593 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
2594 defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>;
2595 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
2596 defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>;
2597 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
2598 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
2599 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
2600 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
2603 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
2604 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
2605 // solely because gas supports it.
2606 def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>;
2607 def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>;
2608 def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>;
2609 def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>;
2610 def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>;
2611 def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>;
2613 // We accept "fnstsw %eax" even though it only writes %ax.
2614 def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>;
2615 def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>;
2616 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
2618 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
2619 // this is compatible with what GAS does.
2620 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2621 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2622 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>, Requires<[Not16BitMode]>;
2623 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>, Requires<[Not16BitMode]>;
2624 def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2625 def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2626 def : InstAlias<"lcall *$dst", (FARCALL16m opaque32mem:$dst)>, Requires<[In16BitMode]>;
2627 def : InstAlias<"ljmp *$dst", (FARJMP16m opaque32mem:$dst)>, Requires<[In16BitMode]>;
2629 def : InstAlias<"call *$dst", (CALL64m i16mem:$dst)>, Requires<[In64BitMode]>;
2630 def : InstAlias<"jmp *$dst", (JMP64m i16mem:$dst)>, Requires<[In64BitMode]>;
2631 def : InstAlias<"call *$dst", (CALL32m i16mem:$dst)>, Requires<[In32BitMode]>;
2632 def : InstAlias<"jmp *$dst", (JMP32m i16mem:$dst)>, Requires<[In32BitMode]>;
2633 def : InstAlias<"call *$dst", (CALL16m i16mem:$dst)>, Requires<[In16BitMode]>;
2634 def : InstAlias<"jmp *$dst", (JMP16m i16mem:$dst)>, Requires<[In16BitMode]>;
2637 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
2638 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
2639 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
2640 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
2641 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
2642 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
2643 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
2645 // inb %dx -> inb %al, %dx
2646 def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;
2647 def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;
2648 def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>;
2649 def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>;
2650 def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>;
2651 def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>;
2654 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
2655 def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2656 def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2657 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2658 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2659 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
2660 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
2661 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2662 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2664 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
2665 // the move. All segment/mem forms are equivalent, this has the shortest
2667 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
2668 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
2670 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
2671 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
2673 // Match 'movq GR64, MMX' as an alias for movd.
2674 def : InstAlias<"movq $src, $dst",
2675 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
2676 def : InstAlias<"movq $src, $dst",
2677 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
2680 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
2681 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
2682 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
2683 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
2684 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
2685 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
2686 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
2689 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
2690 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
2691 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
2692 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
2693 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
2694 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
2695 // Note: No GR32->GR64 movzx form.
2697 // outb %dx -> outb %al, %dx
2698 def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>;
2699 def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>;
2700 def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>;
2701 def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>;
2702 def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>;
2703 def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>;
2705 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
2706 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
2707 // errors, since its encoding is the most compact.
2708 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
2710 // shld/shrd op,op -> shld op, op, CL
2711 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;
2712 def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>;
2713 def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>;
2714 def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>;
2715 def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>;
2716 def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>;
2718 def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>;
2719 def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>;
2720 def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>;
2721 def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>;
2722 def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>;
2723 def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>;
2725 /* FIXME: This is disabled because the asm matcher is currently incapable of
2726 * matching a fixed immediate like $1.
2727 // "shl X, $1" is an alias for "shl X".
2728 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
2729 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2730 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
2731 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2732 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
2733 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2734 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
2735 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2736 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
2737 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2738 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
2739 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2740 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
2741 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2742 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
2743 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2744 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2747 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2748 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
2749 defm : ShiftRotateByOneAlias<"rol", "ROL">;
2750 defm : ShiftRotateByOneAlias<"ror", "ROR">;
2753 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
2754 def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}", (TEST8rm GR8 :$val, i8mem :$mem)>;
2755 def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}", (TEST16rm GR16:$val, i16mem:$mem)>;
2756 def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}", (TEST32rm GR32:$val, i32mem:$mem)>;
2757 def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}", (TEST64rm GR64:$val, i64mem:$mem)>;
2759 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
2760 def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", (XCHG8rm GR8 :$val, i8mem :$mem)>;
2761 def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}", (XCHG16rm GR16:$val, i16mem:$mem)>;
2762 def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}", (XCHG32rm GR32:$val, i32mem:$mem)>;
2763 def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", (XCHG64rm GR64:$val, i64mem:$mem)>;
2765 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
2766 def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src)>;
2767 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar GR32:$src)>, Requires<[Not64BitMode]>;
2768 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
2769 def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src)>;