1 //===----------------------------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
32 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
34 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTX86BrCond : SDTypeProfile<0, 3,
39 [SDTCisVT<0, OtherVT>,
40 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
42 def SDTX86SetCC : SDTypeProfile<1, 2,
44 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86SetCC_C : SDTypeProfile<1, 2,
47 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
49 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
51 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
53 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
54 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
55 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
57 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
58 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
61 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
63 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
67 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
69 def SDTX86Void : SDTypeProfile<0, 0, []>;
71 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
73 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
75 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
77 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
79 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
81 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
82 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
83 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
84 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
86 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
87 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
89 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
90 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
92 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
93 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
95 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
96 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
98 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
99 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
101 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
102 [SDNPHasChain, SDNPMayStore,
103 SDNPMayLoad, SDNPMemOperand]>;
104 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
105 [SDNPHasChain, SDNPMayStore,
106 SDNPMayLoad, SDNPMemOperand]>;
107 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
108 [SDNPHasChain, SDNPMayStore,
109 SDNPMayLoad, SDNPMemOperand]>;
110 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
111 [SDNPHasChain, SDNPMayStore,
112 SDNPMayLoad, SDNPMemOperand]>;
113 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
114 [SDNPHasChain, SDNPMayStore,
115 SDNPMayLoad, SDNPMemOperand]>;
116 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
117 [SDNPHasChain, SDNPMayStore,
118 SDNPMayLoad, SDNPMemOperand]>;
119 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
120 [SDNPHasChain, SDNPMayStore,
121 SDNPMayLoad, SDNPMemOperand]>;
122 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
123 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
125 def X86vastart_save_xmm_regs :
126 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
127 SDT_X86VASTART_SAVE_XMM_REGS,
128 [SDNPHasChain, SDNPVariadic]>;
130 def X86callseq_start :
131 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
132 [SDNPHasChain, SDNPOutFlag]>;
134 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
135 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
137 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
138 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
141 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
142 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
143 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
144 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
147 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
148 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
150 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
151 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
153 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
154 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
155 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
156 SDT_X86SegmentBaseAddress, []>;
158 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
161 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
162 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
164 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
166 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
167 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
169 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
172 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
173 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
174 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
176 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
178 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
181 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
183 def X86MingwAlloca : SDNode<"X86ISD::MINGW_ALLOCA", SDTX86Void,
184 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
186 //===----------------------------------------------------------------------===//
187 // X86 Operand Definitions.
190 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
191 // the index operand of an address, to conform to x86 encoding restrictions.
192 def ptr_rc_nosp : PointerLikeRegClass<1>;
194 // *mem - Operand definitions for the funky X86 addressing mode operands.
196 def X86MemAsmOperand : AsmOperandClass {
200 def X86AbsMemAsmOperand : AsmOperandClass {
202 let SuperClass = X86MemAsmOperand;
204 def X86NoSegMemAsmOperand : AsmOperandClass {
205 let Name = "NoSegMem";
206 let SuperClass = X86MemAsmOperand;
208 class X86MemOperand<string printMethod> : Operand<iPTR> {
209 let PrintMethod = printMethod;
210 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
211 let ParserMatchClass = X86MemAsmOperand;
214 def opaque32mem : X86MemOperand<"printopaquemem">;
215 def opaque48mem : X86MemOperand<"printopaquemem">;
216 def opaque80mem : X86MemOperand<"printopaquemem">;
217 def opaque512mem : X86MemOperand<"printopaquemem">;
219 def i8mem : X86MemOperand<"printi8mem">;
220 def i16mem : X86MemOperand<"printi16mem">;
221 def i32mem : X86MemOperand<"printi32mem">;
222 def i64mem : X86MemOperand<"printi64mem">;
223 def i128mem : X86MemOperand<"printi128mem">;
224 //def i256mem : X86MemOperand<"printi256mem">;
225 def f32mem : X86MemOperand<"printf32mem">;
226 def f64mem : X86MemOperand<"printf64mem">;
227 def f80mem : X86MemOperand<"printf80mem">;
228 def f128mem : X86MemOperand<"printf128mem">;
229 //def f256mem : X86MemOperand<"printf256mem">;
231 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
232 // plain GR64, so that it doesn't potentially require a REX prefix.
233 def i8mem_NOREX : Operand<i64> {
234 let PrintMethod = "printi8mem";
235 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
236 let ParserMatchClass = X86MemAsmOperand;
239 // Special i32mem for addresses of load folding tail calls. These are not
240 // allowed to use callee-saved registers since they must be scheduled
241 // after callee-saved register are popped.
242 def i32mem_TC : Operand<i32> {
243 let PrintMethod = "printi32mem";
244 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
245 let ParserMatchClass = X86MemAsmOperand;
248 def lea32mem : Operand<i32> {
249 let PrintMethod = "printlea32mem";
250 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
251 let ParserMatchClass = X86NoSegMemAsmOperand;
254 let ParserMatchClass = X86AbsMemAsmOperand,
255 PrintMethod = "print_pcrel_imm" in {
256 def i32imm_pcrel : Operand<i32>;
258 def offset8 : Operand<i64>;
259 def offset16 : Operand<i64>;
260 def offset32 : Operand<i64>;
261 def offset64 : Operand<i64>;
263 // Branch targets have OtherVT type and print as pc-relative values.
264 def brtarget : Operand<OtherVT>;
265 def brtarget8 : Operand<OtherVT>;
269 def SSECC : Operand<i8> {
270 let PrintMethod = "printSSECC";
273 def ImmSExt8AsmOperand : AsmOperandClass {
274 let Name = "ImmSExt8";
275 let SuperClass = ImmAsmOperand;
278 // A couple of more descriptive operand definitions.
279 // 16-bits but only 8 bits are significant.
280 def i16i8imm : Operand<i16> {
281 let ParserMatchClass = ImmSExt8AsmOperand;
283 // 32-bits but only 8 bits are significant.
284 def i32i8imm : Operand<i32> {
285 let ParserMatchClass = ImmSExt8AsmOperand;
288 //===----------------------------------------------------------------------===//
289 // X86 Complex Pattern Definitions.
292 // Define X86 specific addressing mode.
293 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
294 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
295 [add, sub, mul, X86mul_imm, shl, or, frameindex],
297 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
298 [tglobaltlsaddr], []>;
300 //===----------------------------------------------------------------------===//
301 // X86 Instruction Predicate Definitions.
302 def HasCMov : Predicate<"Subtarget->hasCMov()">;
303 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
304 def HasMMX : Predicate<"Subtarget->hasMMX()">;
305 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
306 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
307 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
308 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
309 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
310 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
311 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
312 def HasAVX : Predicate<"Subtarget->hasAVX()">;
313 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
314 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
315 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
316 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
317 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
318 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
319 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
320 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
321 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
322 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
323 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
324 "TM.getCodeModel() != CodeModel::Kernel">;
325 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
326 "TM.getCodeModel() == CodeModel::Kernel">;
327 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
328 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
329 def OptForSize : Predicate<"OptForSize">;
330 def OptForSpeed : Predicate<"!OptForSize">;
331 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
332 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
334 //===----------------------------------------------------------------------===//
335 // X86 Instruction Format Definitions.
338 include "X86InstrFormats.td"
340 //===----------------------------------------------------------------------===//
341 // Pattern fragments...
344 // X86 specific condition code. These correspond to CondCode in
345 // X86InstrInfo.h. They must be kept in synch.
346 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
347 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
348 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
349 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
350 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
351 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
352 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
353 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
354 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
355 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
356 def X86_COND_NO : PatLeaf<(i8 10)>;
357 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
358 def X86_COND_NS : PatLeaf<(i8 12)>;
359 def X86_COND_O : PatLeaf<(i8 13)>;
360 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
361 def X86_COND_S : PatLeaf<(i8 15)>;
363 def immSext8 : PatLeaf<(imm), [{
364 return N->getSExtValue() == (int8_t)N->getSExtValue();
367 def i16immSExt8 : PatLeaf<(i16 immSext8)>;
368 def i32immSExt8 : PatLeaf<(i32 immSext8)>;
370 /// Load patterns: these constraint the match to the right address space.
371 def dsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
372 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
373 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
374 if (PT->getAddressSpace() > 255)
379 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
380 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
381 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
382 return PT->getAddressSpace() == 256;
386 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
387 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
388 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
389 return PT->getAddressSpace() == 257;
394 // Helper fragments for loads.
395 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
396 // known to be 32-bit aligned or better. Ditto for i8 to i16.
397 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
398 LoadSDNode *LD = cast<LoadSDNode>(N);
399 if (const Value *Src = LD->getSrcValue())
400 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
401 if (PT->getAddressSpace() > 255)
403 ISD::LoadExtType ExtType = LD->getExtensionType();
404 if (ExtType == ISD::NON_EXTLOAD)
406 if (ExtType == ISD::EXTLOAD)
407 return LD->getAlignment() >= 2 && !LD->isVolatile();
411 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
412 LoadSDNode *LD = cast<LoadSDNode>(N);
413 if (const Value *Src = LD->getSrcValue())
414 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
415 if (PT->getAddressSpace() > 255)
417 ISD::LoadExtType ExtType = LD->getExtensionType();
418 if (ExtType == ISD::EXTLOAD)
419 return LD->getAlignment() >= 2 && !LD->isVolatile();
423 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
424 LoadSDNode *LD = cast<LoadSDNode>(N);
425 if (const Value *Src = LD->getSrcValue())
426 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
427 if (PT->getAddressSpace() > 255)
429 ISD::LoadExtType ExtType = LD->getExtensionType();
430 if (ExtType == ISD::NON_EXTLOAD)
432 if (ExtType == ISD::EXTLOAD)
433 return LD->getAlignment() >= 4 && !LD->isVolatile();
437 def loadi8 : PatFrag<(ops node:$ptr), (i8 (dsload node:$ptr))>;
438 def loadi64 : PatFrag<(ops node:$ptr), (i64 (dsload node:$ptr))>;
439 def loadf32 : PatFrag<(ops node:$ptr), (f32 (dsload node:$ptr))>;
440 def loadf64 : PatFrag<(ops node:$ptr), (f64 (dsload node:$ptr))>;
441 def loadf80 : PatFrag<(ops node:$ptr), (f80 (dsload node:$ptr))>;
443 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
444 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
445 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
447 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
448 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
449 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
450 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
451 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
452 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
454 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
455 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
456 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
457 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
458 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
459 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
462 // An 'and' node with a single use.
463 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
464 return N->hasOneUse();
466 // An 'srl' node with a single use.
467 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
468 return N->hasOneUse();
470 // An 'trunc' node with a single use.
471 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
472 return N->hasOneUse();
475 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
476 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
477 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
478 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
480 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
481 APInt Mask = APInt::getAllOnesValue(BitWidth);
482 APInt KnownZero0, KnownOne0;
483 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
484 APInt KnownZero1, KnownOne1;
485 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
486 return (~KnownZero0 & ~KnownZero1) == 0;
489 // 'shld' and 'shrd' instruction patterns. Note that even though these have
490 // the srl and shl in their patterns, the C++ code must still check for them,
491 // because predicates are tested before children nodes are explored.
493 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
494 (or (srl node:$src1, node:$amt1),
495 (shl node:$src2, node:$amt2)), [{
496 assert(N->getOpcode() == ISD::OR);
497 return N->getOperand(0).getOpcode() == ISD::SRL &&
498 N->getOperand(1).getOpcode() == ISD::SHL &&
499 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
500 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
501 N->getOperand(0).getConstantOperandVal(1) ==
502 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
505 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
506 (or (shl node:$src1, node:$amt1),
507 (srl node:$src2, node:$amt2)), [{
508 assert(N->getOpcode() == ISD::OR);
509 return N->getOperand(0).getOpcode() == ISD::SHL &&
510 N->getOperand(1).getOpcode() == ISD::SRL &&
511 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
512 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
513 N->getOperand(0).getConstantOperandVal(1) ==
514 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
517 //===----------------------------------------------------------------------===//
518 // Instruction list...
521 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
522 // a stack adjustment and the codegen must know that they may modify the stack
523 // pointer before prolog-epilog rewriting occurs.
524 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
525 // sub / add which can clobber EFLAGS.
526 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
527 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
529 [(X86callseq_start timm:$amt)]>,
530 Requires<[In32BitMode]>;
531 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
533 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
534 Requires<[In32BitMode]>;
537 // x86-64 va_start lowering magic.
538 let usesCustomInserter = 1 in {
539 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
542 i64imm:$regsavefi, i64imm:$offset,
544 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
545 [(X86vastart_save_xmm_regs GR8:$al,
549 // Dynamic stack allocation yields _alloca call for Cygwin/Mingw targets. Calls
550 // to _alloca is needed to probe the stack when allocating more than 4k bytes in
551 // one go. Touching the stack at 4K increments is necessary to ensure that the
552 // guard pages used by the OS virtual memory manager are allocated in correct
554 // The main point of having separate instruction are extra unmodelled effects
555 // (compared to ordinary calls) like stack pointer change.
557 def MINGW_ALLOCA : I<0, Pseudo, (outs), (ins),
558 "# dynamic stack allocation",
563 let neverHasSideEffects = 1 in {
564 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
565 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
566 "nop{w}\t$zero", []>, TB, OpSize;
567 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
568 "nop{l}\t$zero", []>, TB;
572 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int\t3", []>;
573 def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
574 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize;
575 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>;
577 // PIC base construction. This expands to code that looks like this:
580 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
581 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
584 //===----------------------------------------------------------------------===//
585 // Control Flow Instructions.
588 // Return instructions.
589 let isTerminator = 1, isReturn = 1, isBarrier = 1,
590 hasCtrlDep = 1, FPForm = SpecialFP in {
591 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
594 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
596 [(X86retflag timm:$amt)]>;
597 def LRET : I <0xCB, RawFrm, (outs), (ins),
599 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
603 // Unconditional branches.
604 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
605 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
606 "jmp\t$dst", [(br bb:$dst)]>;
607 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
611 // Conditional Branches.
612 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
613 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
614 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
615 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
616 [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
620 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
621 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
622 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
623 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
624 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
625 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
626 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
627 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
628 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
629 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
630 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
631 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
632 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
633 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
634 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
635 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
637 // FIXME: What about the CX/RCX versions of this instruction?
638 let Uses = [ECX], isBranch = 1, isTerminator = 1 in
639 def JCXZ8 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
644 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
645 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
646 [(brind GR32:$dst)]>;
647 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
648 [(brind (loadi32 addr:$dst))]>;
650 def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
651 (ins i16imm:$seg, i16imm:$off),
652 "ljmp{w}\t$seg, $off", []>, OpSize;
653 def FARJMP32i : Iseg32<0xEA, RawFrm, (outs),
654 (ins i16imm:$seg, i32imm:$off),
655 "ljmp{l}\t$seg, $off", []>;
657 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
658 "ljmp{w}\t{*}$dst", []>, OpSize;
659 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
660 "ljmp{l}\t{*}$dst", []>;
666 def LOOP : I<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>;
667 def LOOPE : I<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>;
668 def LOOPNE : I<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>;
670 //===----------------------------------------------------------------------===//
671 // Call Instructions...
674 // All calls clobber the non-callee saved registers. ESP is marked as
675 // a use to prevent stack-pointer assignments that appear immediately
676 // before calls from potentially appearing dead. Uses for argument
677 // registers are added manually.
678 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
679 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
680 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
681 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
683 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
684 (outs), (ins i32imm_pcrel:$dst,variable_ops),
686 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
687 "call\t{*}$dst", [(X86call GR32:$dst)]>;
688 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
689 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
691 def FARCALL16i : Iseg16<0x9A, RawFrm, (outs),
692 (ins i16imm:$seg, i16imm:$off),
693 "lcall{w}\t$seg, $off", []>, OpSize;
694 def FARCALL32i : Iseg32<0x9A, RawFrm, (outs),
695 (ins i16imm:$seg, i32imm:$off),
696 "lcall{l}\t$seg, $off", []>;
698 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
699 "lcall{w}\t{*}$dst", []>, OpSize;
700 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
701 "lcall{l}\t{*}$dst", []>;
704 // Constructing a stack frame.
706 def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl),
707 "enter\t$len, $lvl", []>;
711 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
712 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
713 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
714 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
715 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
717 def TCRETURNdi : I<0, Pseudo, (outs),
718 (ins i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
719 "#TC_RETURN $dst $offset", []>;
720 def TCRETURNri : I<0, Pseudo, (outs),
721 (ins GR32_TC:$dst, i32imm:$offset, variable_ops),
722 "#TC_RETURN $dst $offset", []>;
723 def TCRETURNmi : I<0, Pseudo, (outs),
724 (ins i32mem_TC:$dst, i32imm:$offset, variable_ops),
725 "#TC_RETURN $dst $offset", []>;
727 // FIXME: The should be pseudo instructions that are lowered when going to
729 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
730 (ins i32imm_pcrel:$dst, variable_ops),
731 "jmp\t$dst # TAILCALL",
733 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops),
734 "jmp{l}\t{*}$dst # TAILCALL",
736 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops),
737 "jmp{l}\t{*}$dst # TAILCALL", []>;
740 //===----------------------------------------------------------------------===//
741 // Miscellaneous Instructions...
743 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
744 def LEAVE : I<0xC9, RawFrm,
745 (outs), (ins), "leave", []>;
747 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
748 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
749 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
750 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
751 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
752 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
753 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
754 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
756 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
758 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
760 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
761 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
763 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
765 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
766 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
769 let mayStore = 1 in {
770 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
772 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
773 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
775 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
777 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
778 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
782 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
783 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
784 "push{l}\t$imm", []>;
785 def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
786 "push{l}\t$imm", []>;
787 def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
788 "push{l}\t$imm", []>;
791 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
792 def POPF : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
793 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf{l}", []>;
795 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
796 def PUSHF : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
797 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf{l}", []>;
800 let isTwoAddress = 1 in // GR32 = bswap GR32
801 def BSWAP32r : I<0xC8, AddRegFrm,
802 (outs GR32:$dst), (ins GR32:$src),
804 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
807 // Bit scan instructions.
808 let Defs = [EFLAGS] in {
809 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
810 "bsf{w}\t{$src, $dst|$dst, $src}",
811 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB;
812 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
813 "bsf{w}\t{$src, $dst|$dst, $src}",
814 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB;
815 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
816 "bsf{l}\t{$src, $dst|$dst, $src}",
817 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
818 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
819 "bsf{l}\t{$src, $dst|$dst, $src}",
820 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
822 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
823 "bsr{w}\t{$src, $dst|$dst, $src}",
824 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB;
825 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
826 "bsr{w}\t{$src, $dst|$dst, $src}",
827 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB;
828 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
829 "bsr{l}\t{$src, $dst|$dst, $src}",
830 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
831 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
832 "bsr{l}\t{$src, $dst|$dst, $src}",
833 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
836 let neverHasSideEffects = 1 in
837 def LEA16r : I<0x8D, MRMSrcMem,
838 (outs GR16:$dst), (ins lea32mem:$src),
839 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
840 let isReMaterializable = 1 in
841 def LEA32r : I<0x8D, MRMSrcMem,
842 (outs GR32:$dst), (ins lea32mem:$src),
843 "lea{l}\t{$src|$dst}, {$dst|$src}",
844 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
846 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
847 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
848 [(X86rep_movs i8)]>, REP;
849 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
850 [(X86rep_movs i16)]>, REP, OpSize;
851 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
852 [(X86rep_movs i32)]>, REP;
855 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
856 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
857 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
858 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
859 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
862 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
863 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
864 [(X86rep_stos i8)]>, REP;
865 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
866 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
867 [(X86rep_stos i16)]>, REP, OpSize;
868 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
869 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
870 [(X86rep_stos i32)]>, REP;
872 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
873 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
874 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
875 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
876 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
877 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
878 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
880 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
881 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
882 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
884 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
885 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
886 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
888 let Defs = [RAX, RDX] in
889 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
892 let Defs = [RAX, RCX, RDX] in
893 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
895 let isBarrier = 1, hasCtrlDep = 1 in {
896 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
899 def SYSCALL : I<0x05, RawFrm,
900 (outs), (ins), "syscall", []>, TB;
901 def SYSRET : I<0x07, RawFrm,
902 (outs), (ins), "sysret", []>, TB;
903 def SYSENTER : I<0x34, RawFrm,
904 (outs), (ins), "sysenter", []>, TB;
905 def SYSEXIT : I<0x35, RawFrm,
906 (outs), (ins), "sysexit", []>, TB;
908 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
911 //===----------------------------------------------------------------------===//
912 // Input/Output Instructions...
914 let Defs = [AL], Uses = [DX] in
915 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
916 "in{b}\t{%dx, %al|%AL, %DX}", []>;
917 let Defs = [AX], Uses = [DX] in
918 def IN16rr : I<0xED, RawFrm, (outs), (ins),
919 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
920 let Defs = [EAX], Uses = [DX] in
921 def IN32rr : I<0xED, RawFrm, (outs), (ins),
922 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
925 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
926 "in{b}\t{$port, %al|%AL, $port}", []>;
928 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
929 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
931 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
932 "in{l}\t{$port, %eax|%EAX, $port}", []>;
934 let Uses = [DX, AL] in
935 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
936 "out{b}\t{%al, %dx|%DX, %AL}", []>;
937 let Uses = [DX, AX] in
938 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
939 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
940 let Uses = [DX, EAX] in
941 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
942 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
945 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
946 "out{b}\t{%al, $port|$port, %AL}", []>;
948 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
949 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
951 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
952 "out{l}\t{%eax, $port|$port, %EAX}", []>;
954 def IN8 : I<0x6C, RawFrm, (outs), (ins),
956 def IN16 : I<0x6D, RawFrm, (outs), (ins),
957 "ins{w}", []>, OpSize;
958 def IN32 : I<0x6D, RawFrm, (outs), (ins),
961 //===----------------------------------------------------------------------===//
962 // Move Instructions...
964 let neverHasSideEffects = 1 in {
965 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
966 "mov{b}\t{$src, $dst|$dst, $src}", []>;
967 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
968 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
969 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
970 "mov{l}\t{$src, $dst|$dst, $src}", []>;
972 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
973 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
974 "mov{b}\t{$src, $dst|$dst, $src}",
975 [(set GR8:$dst, imm:$src)]>;
976 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
977 "mov{w}\t{$src, $dst|$dst, $src}",
978 [(set GR16:$dst, imm:$src)]>, OpSize;
979 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
980 "mov{l}\t{$src, $dst|$dst, $src}",
981 [(set GR32:$dst, imm:$src)]>;
984 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
985 "mov{b}\t{$src, $dst|$dst, $src}",
986 [(store (i8 imm:$src), addr:$dst)]>;
987 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
988 "mov{w}\t{$src, $dst|$dst, $src}",
989 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
990 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
991 "mov{l}\t{$src, $dst|$dst, $src}",
992 [(store (i32 imm:$src), addr:$dst)]>;
994 def MOV8o8a : Ii8 <0xA0, RawFrm, (outs), (ins offset8:$src),
995 "mov{b}\t{$src, %al|%al, $src}", []>;
996 def MOV16o16a : Ii16 <0xA1, RawFrm, (outs), (ins offset16:$src),
997 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
998 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
999 "mov{l}\t{$src, %eax|%eax, $src}", []>;
1001 def MOV8ao8 : Ii8 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1002 "mov{b}\t{%al, $dst|$dst, %al}", []>;
1003 def MOV16ao16 : Ii16 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1004 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize;
1005 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1006 "mov{l}\t{%eax, $dst|$dst, %eax}", []>;
1008 // Moves to and from segment registers
1009 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
1010 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1011 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
1012 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1013 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
1014 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1015 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
1016 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1018 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1019 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1020 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1021 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1022 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1023 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1025 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1026 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1027 "mov{b}\t{$src, $dst|$dst, $src}",
1028 [(set GR8:$dst, (loadi8 addr:$src))]>;
1029 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1030 "mov{w}\t{$src, $dst|$dst, $src}",
1031 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
1032 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1033 "mov{l}\t{$src, $dst|$dst, $src}",
1034 [(set GR32:$dst, (loadi32 addr:$src))]>;
1037 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1038 "mov{b}\t{$src, $dst|$dst, $src}",
1039 [(store GR8:$src, addr:$dst)]>;
1040 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1041 "mov{w}\t{$src, $dst|$dst, $src}",
1042 [(store GR16:$src, addr:$dst)]>, OpSize;
1043 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1044 "mov{l}\t{$src, $dst|$dst, $src}",
1045 [(store GR32:$src, addr:$dst)]>;
1047 /// Versions of MOV32rr, MOV32rm, and MOV32mr for i32mem_TC and GR32_TC.
1048 let neverHasSideEffects = 1 in
1049 def MOV32rr_TC : I<0x89, MRMDestReg, (outs GR32_TC:$dst), (ins GR32_TC:$src),
1050 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1053 canFoldAsLoad = 1, isReMaterializable = 1 in
1054 def MOV32rm_TC : I<0x8B, MRMSrcMem, (outs GR32_TC:$dst), (ins i32mem_TC:$src),
1055 "mov{l}\t{$src, $dst|$dst, $src}",
1059 def MOV32mr_TC : I<0x89, MRMDestMem, (outs), (ins i32mem_TC:$dst, GR32_TC:$src),
1060 "mov{l}\t{$src, $dst|$dst, $src}",
1063 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1064 // that they can be used for copying and storing h registers, which can't be
1065 // encoded when a REX prefix is present.
1066 let neverHasSideEffects = 1 in
1067 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1068 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1069 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1071 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1072 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1073 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1075 canFoldAsLoad = 1, isReMaterializable = 1 in
1076 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1077 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1078 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1080 // Moves to and from debug registers
1081 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
1082 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1083 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
1084 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1086 // Moves to and from control registers
1087 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG_32:$src),
1088 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1089 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_32:$dst), (ins GR32:$src),
1090 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1092 //===----------------------------------------------------------------------===//
1093 // Fixed-Register Multiplication and Division Instructions...
1096 // Extra precision multiplication
1098 // AL is really implied by AX, by the registers in Defs must match the
1099 // SDNode results (i8, i32).
1100 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1101 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
1102 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1103 // This probably ought to be moved to a def : Pat<> if the
1104 // syntax can be accepted.
1105 [(set AL, (mul AL, GR8:$src)),
1106 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1108 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1109 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1111 []>, OpSize; // AX,DX = AX*GR16
1113 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1114 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1116 []>; // EAX,EDX = EAX*GR32
1118 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1119 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1121 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1122 // This probably ought to be moved to a def : Pat<> if the
1123 // syntax can be accepted.
1124 [(set AL, (mul AL, (loadi8 addr:$src))),
1125 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1127 let mayLoad = 1, neverHasSideEffects = 1 in {
1128 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1129 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1131 []>, OpSize; // AX,DX = AX*[mem16]
1133 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1134 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1136 []>; // EAX,EDX = EAX*[mem32]
1139 let neverHasSideEffects = 1 in {
1140 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1141 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1143 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1144 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1145 OpSize; // AX,DX = AX*GR16
1146 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1147 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1148 // EAX,EDX = EAX*GR32
1149 let mayLoad = 1 in {
1150 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1151 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1152 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1153 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1154 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1155 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1156 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1157 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1158 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1160 } // neverHasSideEffects
1162 // unsigned division/remainder
1163 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1164 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1165 "div{b}\t$src", []>;
1166 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1167 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1168 "div{w}\t$src", []>, OpSize;
1169 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1170 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1171 "div{l}\t$src", []>;
1172 let mayLoad = 1 in {
1173 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1174 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1175 "div{b}\t$src", []>;
1176 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1177 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1178 "div{w}\t$src", []>, OpSize;
1179 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1180 // EDX:EAX/[mem32] = EAX,EDX
1181 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
1182 "div{l}\t$src", []>;
1185 // Signed division/remainder.
1186 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1187 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1188 "idiv{b}\t$src", []>;
1189 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1190 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1191 "idiv{w}\t$src", []>, OpSize;
1192 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1193 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1194 "idiv{l}\t$src", []>;
1195 let mayLoad = 1, mayLoad = 1 in {
1196 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1197 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1198 "idiv{b}\t$src", []>;
1199 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1200 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1201 "idiv{w}\t$src", []>, OpSize;
1202 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1203 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1204 // EDX:EAX/[mem32] = EAX,EDX
1205 "idiv{l}\t$src", []>;
1208 //===----------------------------------------------------------------------===//
1209 // Two address Instructions.
1211 let isTwoAddress = 1 in {
1213 // Conditional moves
1214 let Uses = [EFLAGS] in {
1216 let Predicates = [HasCMov] in {
1217 let isCommutable = 1 in {
1218 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1219 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1220 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1221 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1222 X86_COND_B, EFLAGS))]>,
1224 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1225 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1226 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1227 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1228 X86_COND_B, EFLAGS))]>,
1230 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1231 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1232 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1233 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1234 X86_COND_AE, EFLAGS))]>,
1236 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1237 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1238 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1239 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1240 X86_COND_AE, EFLAGS))]>,
1242 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1243 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1244 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1245 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1246 X86_COND_E, EFLAGS))]>,
1248 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1249 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1250 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1251 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1252 X86_COND_E, EFLAGS))]>,
1254 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1255 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1256 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1257 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1258 X86_COND_NE, EFLAGS))]>,
1260 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1261 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1262 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1263 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1264 X86_COND_NE, EFLAGS))]>,
1266 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1267 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1268 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1269 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1270 X86_COND_BE, EFLAGS))]>,
1272 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1273 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1274 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1275 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1276 X86_COND_BE, EFLAGS))]>,
1278 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1279 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1280 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1281 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1282 X86_COND_A, EFLAGS))]>,
1284 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1285 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1286 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1287 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1288 X86_COND_A, EFLAGS))]>,
1290 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1291 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1292 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1293 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1294 X86_COND_L, EFLAGS))]>,
1296 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1297 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1298 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1299 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1300 X86_COND_L, EFLAGS))]>,
1302 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1303 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1304 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1305 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1306 X86_COND_GE, EFLAGS))]>,
1308 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1309 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1310 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1311 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1312 X86_COND_GE, EFLAGS))]>,
1314 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1315 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1316 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1317 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1318 X86_COND_LE, EFLAGS))]>,
1320 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1321 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1322 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1323 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1324 X86_COND_LE, EFLAGS))]>,
1326 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1327 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1328 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1329 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1330 X86_COND_G, EFLAGS))]>,
1332 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1333 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1334 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1335 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1336 X86_COND_G, EFLAGS))]>,
1338 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1339 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1340 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1341 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1342 X86_COND_S, EFLAGS))]>,
1344 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1345 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1346 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1347 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1348 X86_COND_S, EFLAGS))]>,
1350 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1351 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1352 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1353 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1354 X86_COND_NS, EFLAGS))]>,
1356 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1357 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1358 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1359 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1360 X86_COND_NS, EFLAGS))]>,
1362 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1363 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1364 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1365 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1366 X86_COND_P, EFLAGS))]>,
1368 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1369 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1370 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1371 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1372 X86_COND_P, EFLAGS))]>,
1374 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1375 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1376 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1377 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1378 X86_COND_NP, EFLAGS))]>,
1380 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1381 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1382 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1383 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1384 X86_COND_NP, EFLAGS))]>,
1386 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1387 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1388 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1389 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1390 X86_COND_O, EFLAGS))]>,
1392 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1393 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1394 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1395 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1396 X86_COND_O, EFLAGS))]>,
1398 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1399 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1400 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1401 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1402 X86_COND_NO, EFLAGS))]>,
1404 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1405 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1406 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1407 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1408 X86_COND_NO, EFLAGS))]>,
1410 } // isCommutable = 1
1412 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1413 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1414 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1415 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1416 X86_COND_B, EFLAGS))]>,
1418 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1419 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1420 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1421 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1422 X86_COND_B, EFLAGS))]>,
1424 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1425 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1426 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1427 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1428 X86_COND_AE, EFLAGS))]>,
1430 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1431 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1432 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1433 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1434 X86_COND_AE, EFLAGS))]>,
1436 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1437 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1438 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1439 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1440 X86_COND_E, EFLAGS))]>,
1442 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1443 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1444 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1445 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1446 X86_COND_E, EFLAGS))]>,
1448 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1449 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1450 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1451 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1452 X86_COND_NE, EFLAGS))]>,
1454 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1455 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1456 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1457 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1458 X86_COND_NE, EFLAGS))]>,
1460 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1461 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1462 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1463 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1464 X86_COND_BE, EFLAGS))]>,
1466 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1467 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1468 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1469 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1470 X86_COND_BE, EFLAGS))]>,
1472 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1473 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1474 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1475 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1476 X86_COND_A, EFLAGS))]>,
1478 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1479 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1480 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1481 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1482 X86_COND_A, EFLAGS))]>,
1484 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1485 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1486 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1487 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1488 X86_COND_L, EFLAGS))]>,
1490 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1491 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1492 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1493 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1494 X86_COND_L, EFLAGS))]>,
1496 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1497 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1498 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1499 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1500 X86_COND_GE, EFLAGS))]>,
1502 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1503 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1504 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1505 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1506 X86_COND_GE, EFLAGS))]>,
1508 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1509 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1510 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1511 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1512 X86_COND_LE, EFLAGS))]>,
1514 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1515 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1516 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1517 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1518 X86_COND_LE, EFLAGS))]>,
1520 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1521 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1522 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1523 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1524 X86_COND_G, EFLAGS))]>,
1526 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1527 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1528 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1529 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1530 X86_COND_G, EFLAGS))]>,
1532 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1533 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1534 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1535 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1536 X86_COND_S, EFLAGS))]>,
1538 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1539 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1540 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1541 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1542 X86_COND_S, EFLAGS))]>,
1544 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1545 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1546 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1547 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1548 X86_COND_NS, EFLAGS))]>,
1550 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1551 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1552 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1553 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1554 X86_COND_NS, EFLAGS))]>,
1556 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1557 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1558 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1559 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1560 X86_COND_P, EFLAGS))]>,
1562 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1563 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1564 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1565 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1566 X86_COND_P, EFLAGS))]>,
1568 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1569 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1570 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1571 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1572 X86_COND_NP, EFLAGS))]>,
1574 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1575 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1576 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1577 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1578 X86_COND_NP, EFLAGS))]>,
1580 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1581 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1582 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1583 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1584 X86_COND_O, EFLAGS))]>,
1586 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1587 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1588 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1589 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1590 X86_COND_O, EFLAGS))]>,
1592 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1593 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1594 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1595 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1596 X86_COND_NO, EFLAGS))]>,
1598 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1599 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1600 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1601 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1602 X86_COND_NO, EFLAGS))]>,
1604 } // Predicates = [HasCMov]
1606 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1607 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1608 // however that requires promoting the operands, and can induce additional
1609 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1610 // clobber EFLAGS, because if one of the operands is zero, the expansion
1611 // could involve an xor.
1612 let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in {
1613 def CMOV_GR8 : I<0, Pseudo,
1614 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1615 "#CMOV_GR8 PSEUDO!",
1616 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1617 imm:$cond, EFLAGS))]>;
1619 let Predicates = [NoCMov] in {
1620 def CMOV_GR32 : I<0, Pseudo,
1621 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
1622 "#CMOV_GR32* PSEUDO!",
1624 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
1625 def CMOV_GR16 : I<0, Pseudo,
1626 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
1627 "#CMOV_GR16* PSEUDO!",
1629 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
1630 def CMOV_RFP32 : I<0, Pseudo,
1631 (outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
1632 "#CMOV_RFP32 PSEUDO!",
1633 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
1635 def CMOV_RFP64 : I<0, Pseudo,
1636 (outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
1637 "#CMOV_RFP64 PSEUDO!",
1638 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
1640 def CMOV_RFP80 : I<0, Pseudo,
1641 (outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
1642 "#CMOV_RFP80 PSEUDO!",
1643 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
1645 } // Predicates = [NoCMov]
1646 } // UsesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS]
1647 } // Uses = [EFLAGS]
1650 // unary instructions
1651 let CodeSize = 2 in {
1652 let Defs = [EFLAGS] in {
1653 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1654 [(set GR8:$dst, (ineg GR8:$src)),
1655 (implicit EFLAGS)]>;
1656 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1657 [(set GR16:$dst, (ineg GR16:$src)),
1658 (implicit EFLAGS)]>, OpSize;
1659 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1660 [(set GR32:$dst, (ineg GR32:$src)),
1661 (implicit EFLAGS)]>;
1662 let isTwoAddress = 0 in {
1663 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1664 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1665 (implicit EFLAGS)]>;
1666 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1667 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1668 (implicit EFLAGS)]>, OpSize;
1669 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1670 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1671 (implicit EFLAGS)]>;
1673 } // Defs = [EFLAGS]
1675 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1676 let AddedComplexity = 15 in {
1677 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1678 [(set GR8:$dst, (not GR8:$src))]>;
1679 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1680 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1681 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1682 [(set GR32:$dst, (not GR32:$src))]>;
1684 let isTwoAddress = 0 in {
1685 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1686 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1687 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1688 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1689 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1690 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1694 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1695 let Defs = [EFLAGS] in {
1697 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1698 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src))]>;
1700 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1701 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1703 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src))]>,
1704 OpSize, Requires<[In32BitMode]>;
1705 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1707 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src))]>,
1708 Requires<[In32BitMode]>;
1710 let isTwoAddress = 0, CodeSize = 2 in {
1711 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1712 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1713 (implicit EFLAGS)]>;
1714 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1715 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1716 (implicit EFLAGS)]>,
1717 OpSize, Requires<[In32BitMode]>;
1718 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1719 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1720 (implicit EFLAGS)]>,
1721 Requires<[In32BitMode]>;
1725 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1726 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src))]>;
1727 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1728 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1730 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src))]>,
1731 OpSize, Requires<[In32BitMode]>;
1732 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1734 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src))]>,
1735 Requires<[In32BitMode]>;
1738 let isTwoAddress = 0, CodeSize = 2 in {
1739 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1740 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1741 (implicit EFLAGS)]>;
1742 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1743 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1744 (implicit EFLAGS)]>,
1745 OpSize, Requires<[In32BitMode]>;
1746 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1747 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1748 (implicit EFLAGS)]>,
1749 Requires<[In32BitMode]>;
1751 } // Defs = [EFLAGS]
1753 // Logical operators...
1754 let Defs = [EFLAGS] in {
1755 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1756 def AND8rr : I<0x20, MRMDestReg,
1757 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1758 "and{b}\t{$src2, $dst|$dst, $src2}",
1759 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, GR8:$src2))]>;
1760 def AND16rr : I<0x21, MRMDestReg,
1761 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1762 "and{w}\t{$src2, $dst|$dst, $src2}",
1763 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1764 GR16:$src2))]>, OpSize;
1765 def AND32rr : I<0x21, MRMDestReg,
1766 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1767 "and{l}\t{$src2, $dst|$dst, $src2}",
1768 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1772 // AND instructions with the destination register in REG and the source register
1773 // in R/M. Included for the disassembler.
1774 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1775 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1776 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1777 (ins GR16:$src1, GR16:$src2),
1778 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1779 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1780 (ins GR32:$src1, GR32:$src2),
1781 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1783 def AND8rm : I<0x22, MRMSrcMem,
1784 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1785 "and{b}\t{$src2, $dst|$dst, $src2}",
1786 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1787 (loadi8 addr:$src2)))]>;
1788 def AND16rm : I<0x23, MRMSrcMem,
1789 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1790 "and{w}\t{$src2, $dst|$dst, $src2}",
1791 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1792 (loadi16 addr:$src2)))]>,
1794 def AND32rm : I<0x23, MRMSrcMem,
1795 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1796 "and{l}\t{$src2, $dst|$dst, $src2}",
1797 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1798 (loadi32 addr:$src2)))]>;
1800 def AND8ri : Ii8<0x80, MRM4r,
1801 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1802 "and{b}\t{$src2, $dst|$dst, $src2}",
1803 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1805 def AND16ri : Ii16<0x81, MRM4r,
1806 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1807 "and{w}\t{$src2, $dst|$dst, $src2}",
1808 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1809 imm:$src2))]>, OpSize;
1810 def AND32ri : Ii32<0x81, MRM4r,
1811 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1812 "and{l}\t{$src2, $dst|$dst, $src2}",
1813 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1815 def AND16ri8 : Ii8<0x83, MRM4r,
1816 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1817 "and{w}\t{$src2, $dst|$dst, $src2}",
1818 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1819 i16immSExt8:$src2))]>,
1821 def AND32ri8 : Ii8<0x83, MRM4r,
1822 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1823 "and{l}\t{$src2, $dst|$dst, $src2}",
1824 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1825 i32immSExt8:$src2))]>;
1827 let isTwoAddress = 0 in {
1828 def AND8mr : I<0x20, MRMDestMem,
1829 (outs), (ins i8mem :$dst, GR8 :$src),
1830 "and{b}\t{$src, $dst|$dst, $src}",
1831 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1832 (implicit EFLAGS)]>;
1833 def AND16mr : I<0x21, MRMDestMem,
1834 (outs), (ins i16mem:$dst, GR16:$src),
1835 "and{w}\t{$src, $dst|$dst, $src}",
1836 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1837 (implicit EFLAGS)]>,
1839 def AND32mr : I<0x21, MRMDestMem,
1840 (outs), (ins i32mem:$dst, GR32:$src),
1841 "and{l}\t{$src, $dst|$dst, $src}",
1842 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1843 (implicit EFLAGS)]>;
1844 def AND8mi : Ii8<0x80, MRM4m,
1845 (outs), (ins i8mem :$dst, i8imm :$src),
1846 "and{b}\t{$src, $dst|$dst, $src}",
1847 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1848 (implicit EFLAGS)]>;
1849 def AND16mi : Ii16<0x81, MRM4m,
1850 (outs), (ins i16mem:$dst, i16imm:$src),
1851 "and{w}\t{$src, $dst|$dst, $src}",
1852 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1853 (implicit EFLAGS)]>,
1855 def AND32mi : Ii32<0x81, MRM4m,
1856 (outs), (ins i32mem:$dst, i32imm:$src),
1857 "and{l}\t{$src, $dst|$dst, $src}",
1858 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1859 (implicit EFLAGS)]>;
1860 def AND16mi8 : Ii8<0x83, MRM4m,
1861 (outs), (ins i16mem:$dst, i16i8imm :$src),
1862 "and{w}\t{$src, $dst|$dst, $src}",
1863 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1864 (implicit EFLAGS)]>,
1866 def AND32mi8 : Ii8<0x83, MRM4m,
1867 (outs), (ins i32mem:$dst, i32i8imm :$src),
1868 "and{l}\t{$src, $dst|$dst, $src}",
1869 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1870 (implicit EFLAGS)]>;
1872 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1873 "and{b}\t{$src, %al|%al, $src}", []>;
1874 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1875 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1876 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1877 "and{l}\t{$src, %eax|%eax, $src}", []>;
1882 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1883 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1884 (ins GR8 :$src1, GR8 :$src2),
1885 "or{b}\t{$src2, $dst|$dst, $src2}",
1886 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
1887 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1888 (ins GR16:$src1, GR16:$src2),
1889 "or{w}\t{$src2, $dst|$dst, $src2}",
1890 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
1892 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1893 (ins GR32:$src1, GR32:$src2),
1894 "or{l}\t{$src2, $dst|$dst, $src2}",
1895 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
1898 // OR instructions with the destination register in REG and the source register
1899 // in R/M. Included for the disassembler.
1900 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1901 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1902 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1903 (ins GR16:$src1, GR16:$src2),
1904 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1905 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1906 (ins GR32:$src1, GR32:$src2),
1907 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
1909 def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst),
1910 (ins GR8 :$src1, i8mem :$src2),
1911 "or{b}\t{$src2, $dst|$dst, $src2}",
1912 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
1913 (load addr:$src2)))]>;
1914 def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst),
1915 (ins GR16:$src1, i16mem:$src2),
1916 "or{w}\t{$src2, $dst|$dst, $src2}",
1917 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1918 (load addr:$src2)))]>,
1920 def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst),
1921 (ins GR32:$src1, i32mem:$src2),
1922 "or{l}\t{$src2, $dst|$dst, $src2}",
1923 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1924 (load addr:$src2)))]>;
1926 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
1927 (ins GR8 :$src1, i8imm:$src2),
1928 "or{b}\t{$src2, $dst|$dst, $src2}",
1929 [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
1930 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
1931 (ins GR16:$src1, i16imm:$src2),
1932 "or{w}\t{$src2, $dst|$dst, $src2}",
1933 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1934 imm:$src2))]>, OpSize;
1935 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
1936 (ins GR32:$src1, i32imm:$src2),
1937 "or{l}\t{$src2, $dst|$dst, $src2}",
1938 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1941 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
1942 (ins GR16:$src1, i16i8imm:$src2),
1943 "or{w}\t{$src2, $dst|$dst, $src2}",
1944 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1945 i16immSExt8:$src2))]>, OpSize;
1946 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
1947 (ins GR32:$src1, i32i8imm:$src2),
1948 "or{l}\t{$src2, $dst|$dst, $src2}",
1949 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1950 i32immSExt8:$src2))]>;
1951 let isTwoAddress = 0 in {
1952 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1953 "or{b}\t{$src, $dst|$dst, $src}",
1954 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1955 (implicit EFLAGS)]>;
1956 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1957 "or{w}\t{$src, $dst|$dst, $src}",
1958 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1959 (implicit EFLAGS)]>, OpSize;
1960 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1961 "or{l}\t{$src, $dst|$dst, $src}",
1962 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1963 (implicit EFLAGS)]>;
1964 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1965 "or{b}\t{$src, $dst|$dst, $src}",
1966 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1967 (implicit EFLAGS)]>;
1968 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1969 "or{w}\t{$src, $dst|$dst, $src}",
1970 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1971 (implicit EFLAGS)]>,
1973 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1974 "or{l}\t{$src, $dst|$dst, $src}",
1975 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1976 (implicit EFLAGS)]>;
1977 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1978 "or{w}\t{$src, $dst|$dst, $src}",
1979 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1980 (implicit EFLAGS)]>,
1982 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1983 "or{l}\t{$src, $dst|$dst, $src}",
1984 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1985 (implicit EFLAGS)]>;
1987 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
1988 "or{b}\t{$src, %al|%al, $src}", []>;
1989 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
1990 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1991 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
1992 "or{l}\t{$src, %eax|%eax, $src}", []>;
1993 } // isTwoAddress = 0
1996 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1997 def XOR8rr : I<0x30, MRMDestReg,
1998 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1999 "xor{b}\t{$src2, $dst|$dst, $src2}",
2000 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2002 def XOR16rr : I<0x31, MRMDestReg,
2003 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2004 "xor{w}\t{$src2, $dst|$dst, $src2}",
2005 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2006 GR16:$src2))]>, OpSize;
2007 def XOR32rr : I<0x31, MRMDestReg,
2008 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2009 "xor{l}\t{$src2, $dst|$dst, $src2}",
2010 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2012 } // isCommutable = 1
2014 // XOR instructions with the destination register in REG and the source register
2015 // in R/M. Included for the disassembler.
2016 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2017 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
2018 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
2019 (ins GR16:$src1, GR16:$src2),
2020 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2021 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
2022 (ins GR32:$src1, GR32:$src2),
2023 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
2025 def XOR8rm : I<0x32, MRMSrcMem,
2026 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
2027 "xor{b}\t{$src2, $dst|$dst, $src2}",
2028 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2029 (load addr:$src2)))]>;
2030 def XOR16rm : I<0x33, MRMSrcMem,
2031 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2032 "xor{w}\t{$src2, $dst|$dst, $src2}",
2033 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2034 (load addr:$src2)))]>,
2036 def XOR32rm : I<0x33, MRMSrcMem,
2037 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2038 "xor{l}\t{$src2, $dst|$dst, $src2}",
2039 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2040 (load addr:$src2)))]>;
2042 def XOR8ri : Ii8<0x80, MRM6r,
2043 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2044 "xor{b}\t{$src2, $dst|$dst, $src2}",
2045 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
2046 def XOR16ri : Ii16<0x81, MRM6r,
2047 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2048 "xor{w}\t{$src2, $dst|$dst, $src2}",
2049 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2050 imm:$src2))]>, OpSize;
2051 def XOR32ri : Ii32<0x81, MRM6r,
2052 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2053 "xor{l}\t{$src2, $dst|$dst, $src2}",
2054 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2056 def XOR16ri8 : Ii8<0x83, MRM6r,
2057 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2058 "xor{w}\t{$src2, $dst|$dst, $src2}",
2059 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2060 i16immSExt8:$src2))]>,
2062 def XOR32ri8 : Ii8<0x83, MRM6r,
2063 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2064 "xor{l}\t{$src2, $dst|$dst, $src2}",
2065 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2066 i32immSExt8:$src2))]>;
2068 let isTwoAddress = 0 in {
2069 def XOR8mr : I<0x30, MRMDestMem,
2070 (outs), (ins i8mem :$dst, GR8 :$src),
2071 "xor{b}\t{$src, $dst|$dst, $src}",
2072 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
2073 (implicit EFLAGS)]>;
2074 def XOR16mr : I<0x31, MRMDestMem,
2075 (outs), (ins i16mem:$dst, GR16:$src),
2076 "xor{w}\t{$src, $dst|$dst, $src}",
2077 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
2078 (implicit EFLAGS)]>,
2080 def XOR32mr : I<0x31, MRMDestMem,
2081 (outs), (ins i32mem:$dst, GR32:$src),
2082 "xor{l}\t{$src, $dst|$dst, $src}",
2083 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
2084 (implicit EFLAGS)]>;
2085 def XOR8mi : Ii8<0x80, MRM6m,
2086 (outs), (ins i8mem :$dst, i8imm :$src),
2087 "xor{b}\t{$src, $dst|$dst, $src}",
2088 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
2089 (implicit EFLAGS)]>;
2090 def XOR16mi : Ii16<0x81, MRM6m,
2091 (outs), (ins i16mem:$dst, i16imm:$src),
2092 "xor{w}\t{$src, $dst|$dst, $src}",
2093 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
2094 (implicit EFLAGS)]>,
2096 def XOR32mi : Ii32<0x81, MRM6m,
2097 (outs), (ins i32mem:$dst, i32imm:$src),
2098 "xor{l}\t{$src, $dst|$dst, $src}",
2099 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
2100 (implicit EFLAGS)]>;
2101 def XOR16mi8 : Ii8<0x83, MRM6m,
2102 (outs), (ins i16mem:$dst, i16i8imm :$src),
2103 "xor{w}\t{$src, $dst|$dst, $src}",
2104 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
2105 (implicit EFLAGS)]>,
2107 def XOR32mi8 : Ii8<0x83, MRM6m,
2108 (outs), (ins i32mem:$dst, i32i8imm :$src),
2109 "xor{l}\t{$src, $dst|$dst, $src}",
2110 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
2111 (implicit EFLAGS)]>;
2113 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
2114 "xor{b}\t{$src, %al|%al, $src}", []>;
2115 def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
2116 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2117 def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
2118 "xor{l}\t{$src, %eax|%eax, $src}", []>;
2119 } // isTwoAddress = 0
2120 } // Defs = [EFLAGS]
2122 // Shift instructions
2123 let Defs = [EFLAGS] in {
2124 let Uses = [CL] in {
2125 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
2126 "shl{b}\t{%cl, $dst|$dst, CL}",
2127 [(set GR8:$dst, (shl GR8:$src, CL))]>;
2128 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
2129 "shl{w}\t{%cl, $dst|$dst, CL}",
2130 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
2131 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
2132 "shl{l}\t{%cl, $dst|$dst, CL}",
2133 [(set GR32:$dst, (shl GR32:$src, CL))]>;
2136 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2137 "shl{b}\t{$src2, $dst|$dst, $src2}",
2138 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
2139 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2140 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2141 "shl{w}\t{$src2, $dst|$dst, $src2}",
2142 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2143 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2144 "shl{l}\t{$src2, $dst|$dst, $src2}",
2145 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
2147 // NOTE: We don't include patterns for shifts of a register by one, because
2148 // 'add reg,reg' is cheaper.
2150 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
2151 "shl{b}\t$dst", []>;
2152 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2153 "shl{w}\t$dst", []>, OpSize;
2154 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2155 "shl{l}\t$dst", []>;
2157 } // isConvertibleToThreeAddress = 1
2159 let isTwoAddress = 0 in {
2160 let Uses = [CL] in {
2161 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
2162 "shl{b}\t{%cl, $dst|$dst, CL}",
2163 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
2164 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
2165 "shl{w}\t{%cl, $dst|$dst, CL}",
2166 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2167 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
2168 "shl{l}\t{%cl, $dst|$dst, CL}",
2169 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
2171 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
2172 "shl{b}\t{$src, $dst|$dst, $src}",
2173 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2174 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
2175 "shl{w}\t{$src, $dst|$dst, $src}",
2176 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2178 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
2179 "shl{l}\t{$src, $dst|$dst, $src}",
2180 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2183 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
2185 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2186 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
2188 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2190 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2192 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2195 let Uses = [CL] in {
2196 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
2197 "shr{b}\t{%cl, $dst|$dst, CL}",
2198 [(set GR8:$dst, (srl GR8:$src, CL))]>;
2199 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
2200 "shr{w}\t{%cl, $dst|$dst, CL}",
2201 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
2202 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
2203 "shr{l}\t{%cl, $dst|$dst, CL}",
2204 [(set GR32:$dst, (srl GR32:$src, CL))]>;
2207 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2208 "shr{b}\t{$src2, $dst|$dst, $src2}",
2209 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2210 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2211 "shr{w}\t{$src2, $dst|$dst, $src2}",
2212 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2213 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2214 "shr{l}\t{$src2, $dst|$dst, $src2}",
2215 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2218 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2220 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2221 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2223 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2224 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2226 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2228 let isTwoAddress = 0 in {
2229 let Uses = [CL] in {
2230 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2231 "shr{b}\t{%cl, $dst|$dst, CL}",
2232 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2233 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2234 "shr{w}\t{%cl, $dst|$dst, CL}",
2235 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2237 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2238 "shr{l}\t{%cl, $dst|$dst, CL}",
2239 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2241 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2242 "shr{b}\t{$src, $dst|$dst, $src}",
2243 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2244 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2245 "shr{w}\t{$src, $dst|$dst, $src}",
2246 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2248 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2249 "shr{l}\t{$src, $dst|$dst, $src}",
2250 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2253 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2255 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2256 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2258 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2259 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2261 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2264 let Uses = [CL] in {
2265 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
2266 "sar{b}\t{%cl, $dst|$dst, CL}",
2267 [(set GR8:$dst, (sra GR8:$src, CL))]>;
2268 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
2269 "sar{w}\t{%cl, $dst|$dst, CL}",
2270 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
2271 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
2272 "sar{l}\t{%cl, $dst|$dst, CL}",
2273 [(set GR32:$dst, (sra GR32:$src, CL))]>;
2276 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2277 "sar{b}\t{$src2, $dst|$dst, $src2}",
2278 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2279 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2280 "sar{w}\t{$src2, $dst|$dst, $src2}",
2281 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2283 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2284 "sar{l}\t{$src2, $dst|$dst, $src2}",
2285 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2288 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2290 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2291 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2293 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2294 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2296 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2298 let isTwoAddress = 0 in {
2299 let Uses = [CL] in {
2300 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2301 "sar{b}\t{%cl, $dst|$dst, CL}",
2302 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2303 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2304 "sar{w}\t{%cl, $dst|$dst, CL}",
2305 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2306 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2307 "sar{l}\t{%cl, $dst|$dst, CL}",
2308 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2310 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2311 "sar{b}\t{$src, $dst|$dst, $src}",
2312 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2313 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2314 "sar{w}\t{$src, $dst|$dst, $src}",
2315 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2317 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2318 "sar{l}\t{$src, $dst|$dst, $src}",
2319 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2322 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2324 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2325 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2327 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2329 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2331 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2334 // Rotate instructions
2336 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2337 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2338 let Uses = [CL] in {
2339 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2340 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2342 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2343 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2345 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2346 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2347 let Uses = [CL] in {
2348 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2349 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2351 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2352 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2354 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2355 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2356 let Uses = [CL] in {
2357 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2358 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2360 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2361 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2363 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2364 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2365 let Uses = [CL] in {
2366 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2367 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2369 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2370 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2372 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2373 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2374 let Uses = [CL] in {
2375 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2376 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2378 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2379 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2381 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2382 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2383 let Uses = [CL] in {
2384 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2385 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2387 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2388 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2390 let isTwoAddress = 0 in {
2391 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
2392 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2393 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2394 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2395 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
2396 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2397 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2398 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2399 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
2400 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2401 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2402 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2403 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
2404 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2405 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2406 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2407 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
2408 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2409 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2410 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2411 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
2412 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2413 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2414 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2416 let Uses = [CL] in {
2417 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
2418 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2419 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
2420 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2421 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
2422 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2423 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
2424 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2425 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
2426 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2427 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
2428 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2432 // FIXME: provide shorter instructions when imm8 == 1
2433 let Uses = [CL] in {
2434 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
2435 "rol{b}\t{%cl, $dst|$dst, CL}",
2436 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
2437 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
2438 "rol{w}\t{%cl, $dst|$dst, CL}",
2439 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
2440 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
2441 "rol{l}\t{%cl, $dst|$dst, CL}",
2442 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2445 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2446 "rol{b}\t{$src2, $dst|$dst, $src2}",
2447 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2448 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2449 "rol{w}\t{$src2, $dst|$dst, $src2}",
2450 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2452 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2453 "rol{l}\t{$src2, $dst|$dst, $src2}",
2454 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2457 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2459 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2460 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2462 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2463 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2465 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2467 let isTwoAddress = 0 in {
2468 let Uses = [CL] in {
2469 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2470 "rol{b}\t{%cl, $dst|$dst, CL}",
2471 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2472 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2473 "rol{w}\t{%cl, $dst|$dst, CL}",
2474 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2475 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2476 "rol{l}\t{%cl, $dst|$dst, CL}",
2477 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2479 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2480 "rol{b}\t{$src, $dst|$dst, $src}",
2481 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2482 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2483 "rol{w}\t{$src, $dst|$dst, $src}",
2484 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2486 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2487 "rol{l}\t{$src, $dst|$dst, $src}",
2488 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2491 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2493 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2494 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2496 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2498 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2500 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2503 let Uses = [CL] in {
2504 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2505 "ror{b}\t{%cl, $dst|$dst, CL}",
2506 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2507 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2508 "ror{w}\t{%cl, $dst|$dst, CL}",
2509 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2510 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2511 "ror{l}\t{%cl, $dst|$dst, CL}",
2512 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2515 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2516 "ror{b}\t{$src2, $dst|$dst, $src2}",
2517 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2518 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2519 "ror{w}\t{$src2, $dst|$dst, $src2}",
2520 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2522 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2523 "ror{l}\t{$src2, $dst|$dst, $src2}",
2524 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2527 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2529 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2530 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2532 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2533 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2535 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2537 let isTwoAddress = 0 in {
2538 let Uses = [CL] in {
2539 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2540 "ror{b}\t{%cl, $dst|$dst, CL}",
2541 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2542 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2543 "ror{w}\t{%cl, $dst|$dst, CL}",
2544 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2545 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2546 "ror{l}\t{%cl, $dst|$dst, CL}",
2547 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2549 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2550 "ror{b}\t{$src, $dst|$dst, $src}",
2551 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2552 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2553 "ror{w}\t{$src, $dst|$dst, $src}",
2554 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2556 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2557 "ror{l}\t{$src, $dst|$dst, $src}",
2558 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2561 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2563 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2564 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2566 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2568 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2570 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2575 // Double shift instructions (generalizations of rotate)
2576 let Uses = [CL] in {
2577 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2578 (ins GR32:$src1, GR32:$src2),
2579 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2580 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2581 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2582 (ins GR32:$src1, GR32:$src2),
2583 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2584 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2585 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2586 (ins GR16:$src1, GR16:$src2),
2587 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2588 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2590 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2591 (ins GR16:$src1, GR16:$src2),
2592 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2593 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2597 let isCommutable = 1 in { // These instructions commute to each other.
2598 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2600 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2601 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2602 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2605 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2607 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2608 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2609 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2612 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2614 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2615 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2616 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2619 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2621 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2622 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2623 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2628 let isTwoAddress = 0 in {
2629 let Uses = [CL] in {
2630 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2631 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2632 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2634 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2635 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2636 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2639 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2640 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2641 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2642 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2643 (i8 imm:$src3)), addr:$dst)]>,
2645 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2646 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2647 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2648 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2649 (i8 imm:$src3)), addr:$dst)]>,
2652 let Uses = [CL] in {
2653 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2654 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2655 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2656 addr:$dst)]>, TB, OpSize;
2657 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2658 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2659 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2660 addr:$dst)]>, TB, OpSize;
2662 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2663 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2664 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2665 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2666 (i8 imm:$src3)), addr:$dst)]>,
2668 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2669 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2670 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2671 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2672 (i8 imm:$src3)), addr:$dst)]>,
2675 } // Defs = [EFLAGS]
2679 let Defs = [EFLAGS] in {
2680 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2681 // Register-Register Addition
2682 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2683 (ins GR8 :$src1, GR8 :$src2),
2684 "add{b}\t{$src2, $dst|$dst, $src2}",
2685 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
2687 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2688 // Register-Register Addition
2689 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2690 (ins GR16:$src1, GR16:$src2),
2691 "add{w}\t{$src2, $dst|$dst, $src2}",
2692 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2693 GR16:$src2))]>, OpSize;
2694 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2695 (ins GR32:$src1, GR32:$src2),
2696 "add{l}\t{$src2, $dst|$dst, $src2}",
2697 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2699 } // end isConvertibleToThreeAddress
2700 } // end isCommutable
2702 // These are alternate spellings for use by the disassembler, we mark them as
2703 // code gen only to ensure they aren't matched by the assembler.
2704 let isCodeGenOnly = 1 in {
2705 def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2706 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2707 def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2708 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2709 def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2710 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2713 // Register-Memory Addition
2714 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2715 (ins GR8 :$src1, i8mem :$src2),
2716 "add{b}\t{$src2, $dst|$dst, $src2}",
2717 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
2718 (load addr:$src2)))]>;
2719 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2720 (ins GR16:$src1, i16mem:$src2),
2721 "add{w}\t{$src2, $dst|$dst, $src2}",
2722 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2723 (load addr:$src2)))]>, OpSize;
2724 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2725 (ins GR32:$src1, i32mem:$src2),
2726 "add{l}\t{$src2, $dst|$dst, $src2}",
2727 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2728 (load addr:$src2)))]>;
2730 // Register-Integer Addition
2731 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2732 "add{b}\t{$src2, $dst|$dst, $src2}",
2733 [(set GR8:$dst, EFLAGS,
2734 (X86add_flag GR8:$src1, imm:$src2))]>;
2736 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2737 // Register-Integer Addition
2738 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2739 (ins GR16:$src1, i16imm:$src2),
2740 "add{w}\t{$src2, $dst|$dst, $src2}",
2741 [(set GR16:$dst, EFLAGS,
2742 (X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
2743 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2744 (ins GR32:$src1, i32imm:$src2),
2745 "add{l}\t{$src2, $dst|$dst, $src2}",
2746 [(set GR32:$dst, EFLAGS,
2747 (X86add_flag GR32:$src1, imm:$src2))]>;
2748 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2749 (ins GR16:$src1, i16i8imm:$src2),
2750 "add{w}\t{$src2, $dst|$dst, $src2}",
2751 [(set GR16:$dst, EFLAGS,
2752 (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2753 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2754 (ins GR32:$src1, i32i8imm:$src2),
2755 "add{l}\t{$src2, $dst|$dst, $src2}",
2756 [(set GR32:$dst, EFLAGS,
2757 (X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
2760 let isTwoAddress = 0 in {
2761 // Memory-Register Addition
2762 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2763 "add{b}\t{$src2, $dst|$dst, $src2}",
2764 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2765 (implicit EFLAGS)]>;
2766 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2767 "add{w}\t{$src2, $dst|$dst, $src2}",
2768 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2769 (implicit EFLAGS)]>, OpSize;
2770 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2771 "add{l}\t{$src2, $dst|$dst, $src2}",
2772 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2773 (implicit EFLAGS)]>;
2774 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2775 "add{b}\t{$src2, $dst|$dst, $src2}",
2776 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2777 (implicit EFLAGS)]>;
2778 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2779 "add{w}\t{$src2, $dst|$dst, $src2}",
2780 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2781 (implicit EFLAGS)]>, OpSize;
2782 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2783 "add{l}\t{$src2, $dst|$dst, $src2}",
2784 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2785 (implicit EFLAGS)]>;
2786 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2787 "add{w}\t{$src2, $dst|$dst, $src2}",
2788 [(store (add (load addr:$dst), i16immSExt8:$src2),
2790 (implicit EFLAGS)]>, OpSize;
2791 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2792 "add{l}\t{$src2, $dst|$dst, $src2}",
2793 [(store (add (load addr:$dst), i32immSExt8:$src2),
2795 (implicit EFLAGS)]>;
2798 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2799 "add{b}\t{$src, %al|%al, $src}", []>;
2800 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2801 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2802 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2803 "add{l}\t{$src, %eax|%eax, $src}", []>;
2806 let Uses = [EFLAGS] in {
2807 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2808 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2809 "adc{b}\t{$src2, $dst|$dst, $src2}",
2810 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2811 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2812 (ins GR16:$src1, GR16:$src2),
2813 "adc{w}\t{$src2, $dst|$dst, $src2}",
2814 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2815 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2816 (ins GR32:$src1, GR32:$src2),
2817 "adc{l}\t{$src2, $dst|$dst, $src2}",
2818 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2821 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2822 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2823 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2824 (ins GR16:$src1, GR16:$src2),
2825 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2826 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2827 (ins GR32:$src1, GR32:$src2),
2828 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2830 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2831 (ins GR8:$src1, i8mem:$src2),
2832 "adc{b}\t{$src2, $dst|$dst, $src2}",
2833 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2834 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2835 (ins GR16:$src1, i16mem:$src2),
2836 "adc{w}\t{$src2, $dst|$dst, $src2}",
2837 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2839 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2840 (ins GR32:$src1, i32mem:$src2),
2841 "adc{l}\t{$src2, $dst|$dst, $src2}",
2842 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2843 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2844 "adc{b}\t{$src2, $dst|$dst, $src2}",
2845 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2846 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2847 (ins GR16:$src1, i16imm:$src2),
2848 "adc{w}\t{$src2, $dst|$dst, $src2}",
2849 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2850 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2851 (ins GR16:$src1, i16i8imm:$src2),
2852 "adc{w}\t{$src2, $dst|$dst, $src2}",
2853 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2855 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2856 (ins GR32:$src1, i32imm:$src2),
2857 "adc{l}\t{$src2, $dst|$dst, $src2}",
2858 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2859 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2860 (ins GR32:$src1, i32i8imm:$src2),
2861 "adc{l}\t{$src2, $dst|$dst, $src2}",
2862 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2864 let isTwoAddress = 0 in {
2865 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2866 "adc{b}\t{$src2, $dst|$dst, $src2}",
2867 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2868 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2869 "adc{w}\t{$src2, $dst|$dst, $src2}",
2870 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2872 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2873 "adc{l}\t{$src2, $dst|$dst, $src2}",
2874 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2875 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2876 "adc{b}\t{$src2, $dst|$dst, $src2}",
2877 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2878 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2879 "adc{w}\t{$src2, $dst|$dst, $src2}",
2880 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2882 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2883 "adc{w}\t{$src2, $dst|$dst, $src2}",
2884 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2886 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2887 "adc{l}\t{$src2, $dst|$dst, $src2}",
2888 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2889 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2890 "adc{l}\t{$src2, $dst|$dst, $src2}",
2891 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2893 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2894 "adc{b}\t{$src, %al|%al, $src}", []>;
2895 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2896 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2897 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2898 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2900 } // Uses = [EFLAGS]
2902 // Register-Register Subtraction
2903 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2904 "sub{b}\t{$src2, $dst|$dst, $src2}",
2905 [(set GR8:$dst, EFLAGS,
2906 (X86sub_flag GR8:$src1, GR8:$src2))]>;
2907 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2908 "sub{w}\t{$src2, $dst|$dst, $src2}",
2909 [(set GR16:$dst, EFLAGS,
2910 (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
2911 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2912 "sub{l}\t{$src2, $dst|$dst, $src2}",
2913 [(set GR32:$dst, EFLAGS,
2914 (X86sub_flag GR32:$src1, GR32:$src2))]>;
2916 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2917 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
2918 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
2919 (ins GR16:$src1, GR16:$src2),
2920 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2921 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
2922 (ins GR32:$src1, GR32:$src2),
2923 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
2925 // Register-Memory Subtraction
2926 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2927 (ins GR8 :$src1, i8mem :$src2),
2928 "sub{b}\t{$src2, $dst|$dst, $src2}",
2929 [(set GR8:$dst, EFLAGS,
2930 (X86sub_flag GR8:$src1, (load addr:$src2)))]>;
2931 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2932 (ins GR16:$src1, i16mem:$src2),
2933 "sub{w}\t{$src2, $dst|$dst, $src2}",
2934 [(set GR16:$dst, EFLAGS,
2935 (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
2936 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2937 (ins GR32:$src1, i32mem:$src2),
2938 "sub{l}\t{$src2, $dst|$dst, $src2}",
2939 [(set GR32:$dst, EFLAGS,
2940 (X86sub_flag GR32:$src1, (load addr:$src2)))]>;
2942 // Register-Integer Subtraction
2943 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2944 (ins GR8:$src1, i8imm:$src2),
2945 "sub{b}\t{$src2, $dst|$dst, $src2}",
2946 [(set GR8:$dst, EFLAGS,
2947 (X86sub_flag GR8:$src1, imm:$src2))]>;
2948 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2949 (ins GR16:$src1, i16imm:$src2),
2950 "sub{w}\t{$src2, $dst|$dst, $src2}",
2951 [(set GR16:$dst, EFLAGS,
2952 (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
2953 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2954 (ins GR32:$src1, i32imm:$src2),
2955 "sub{l}\t{$src2, $dst|$dst, $src2}",
2956 [(set GR32:$dst, EFLAGS,
2957 (X86sub_flag GR32:$src1, imm:$src2))]>;
2958 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2959 (ins GR16:$src1, i16i8imm:$src2),
2960 "sub{w}\t{$src2, $dst|$dst, $src2}",
2961 [(set GR16:$dst, EFLAGS,
2962 (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2963 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2964 (ins GR32:$src1, i32i8imm:$src2),
2965 "sub{l}\t{$src2, $dst|$dst, $src2}",
2966 [(set GR32:$dst, EFLAGS,
2967 (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
2969 let isTwoAddress = 0 in {
2970 // Memory-Register Subtraction
2971 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2972 "sub{b}\t{$src2, $dst|$dst, $src2}",
2973 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2974 (implicit EFLAGS)]>;
2975 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2976 "sub{w}\t{$src2, $dst|$dst, $src2}",
2977 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2978 (implicit EFLAGS)]>, OpSize;
2979 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2980 "sub{l}\t{$src2, $dst|$dst, $src2}",
2981 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2982 (implicit EFLAGS)]>;
2984 // Memory-Integer Subtraction
2985 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2986 "sub{b}\t{$src2, $dst|$dst, $src2}",
2987 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2988 (implicit EFLAGS)]>;
2989 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2990 "sub{w}\t{$src2, $dst|$dst, $src2}",
2991 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2992 (implicit EFLAGS)]>, OpSize;
2993 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2994 "sub{l}\t{$src2, $dst|$dst, $src2}",
2995 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2996 (implicit EFLAGS)]>;
2997 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2998 "sub{w}\t{$src2, $dst|$dst, $src2}",
2999 [(store (sub (load addr:$dst), i16immSExt8:$src2),
3001 (implicit EFLAGS)]>, OpSize;
3002 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3003 "sub{l}\t{$src2, $dst|$dst, $src2}",
3004 [(store (sub (load addr:$dst), i32immSExt8:$src2),
3006 (implicit EFLAGS)]>;
3008 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
3009 "sub{b}\t{$src, %al|%al, $src}", []>;
3010 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
3011 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3012 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
3013 "sub{l}\t{$src, %eax|%eax, $src}", []>;
3016 let Uses = [EFLAGS] in {
3017 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
3018 (ins GR8:$src1, GR8:$src2),
3019 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3020 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
3021 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
3022 (ins GR16:$src1, GR16:$src2),
3023 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3024 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
3025 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
3026 (ins GR32:$src1, GR32:$src2),
3027 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3028 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
3030 let isTwoAddress = 0 in {
3031 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3032 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3033 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
3034 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3035 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3036 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
3038 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3039 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3040 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
3041 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
3042 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3043 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
3044 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
3045 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3046 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
3048 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3049 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3050 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
3052 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
3053 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3054 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
3055 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3056 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3057 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
3059 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
3060 "sbb{b}\t{$src, %al|%al, $src}", []>;
3061 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
3062 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3063 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
3064 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
3067 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3068 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
3069 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
3070 (ins GR16:$src1, GR16:$src2),
3071 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3072 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
3073 (ins GR32:$src1, GR32:$src2),
3074 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
3076 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
3077 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3078 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
3079 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
3080 (ins GR16:$src1, i16mem:$src2),
3081 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3082 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
3084 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
3085 (ins GR32:$src1, i32mem:$src2),
3086 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3087 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
3088 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
3089 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3090 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
3091 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
3092 (ins GR16:$src1, i16imm:$src2),
3093 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3094 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
3095 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
3096 (ins GR16:$src1, i16i8imm:$src2),
3097 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3098 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
3100 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
3101 (ins GR32:$src1, i32imm:$src2),
3102 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3103 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
3104 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
3105 (ins GR32:$src1, i32i8imm:$src2),
3106 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3107 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
3108 } // Uses = [EFLAGS]
3109 } // Defs = [EFLAGS]
3111 let Defs = [EFLAGS] in {
3112 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
3113 // Register-Register Signed Integer Multiply
3114 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3115 "imul{w}\t{$src2, $dst|$dst, $src2}",
3116 [(set GR16:$dst, EFLAGS,
3117 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
3118 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3119 "imul{l}\t{$src2, $dst|$dst, $src2}",
3120 [(set GR32:$dst, EFLAGS,
3121 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
3124 // Register-Memory Signed Integer Multiply
3125 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
3126 (ins GR16:$src1, i16mem:$src2),
3127 "imul{w}\t{$src2, $dst|$dst, $src2}",
3128 [(set GR16:$dst, EFLAGS,
3129 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
3131 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
3132 (ins GR32:$src1, i32mem:$src2),
3133 "imul{l}\t{$src2, $dst|$dst, $src2}",
3134 [(set GR32:$dst, EFLAGS,
3135 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
3136 } // Defs = [EFLAGS]
3137 } // end Two Address instructions
3139 // Suprisingly enough, these are not two address instructions!
3140 let Defs = [EFLAGS] in {
3141 // Register-Integer Signed Integer Multiply
3142 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
3143 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
3144 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3145 [(set GR16:$dst, EFLAGS,
3146 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
3147 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
3148 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
3149 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3150 [(set GR32:$dst, EFLAGS,
3151 (X86smul_flag GR32:$src1, imm:$src2))]>;
3152 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
3153 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
3154 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3155 [(set GR16:$dst, EFLAGS,
3156 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
3158 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
3159 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
3160 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3161 [(set GR32:$dst, EFLAGS,
3162 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
3164 // Memory-Integer Signed Integer Multiply
3165 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
3166 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
3167 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3168 [(set GR16:$dst, EFLAGS,
3169 (X86smul_flag (load addr:$src1), imm:$src2))]>,
3171 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
3172 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
3173 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3174 [(set GR32:$dst, EFLAGS,
3175 (X86smul_flag (load addr:$src1), imm:$src2))]>;
3176 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
3177 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
3178 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3179 [(set GR16:$dst, EFLAGS,
3180 (X86smul_flag (load addr:$src1),
3181 i16immSExt8:$src2))]>, OpSize;
3182 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
3183 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
3184 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3185 [(set GR32:$dst, EFLAGS,
3186 (X86smul_flag (load addr:$src1),
3187 i32immSExt8:$src2))]>;
3188 } // Defs = [EFLAGS]
3190 //===----------------------------------------------------------------------===//
3191 // Test instructions are just like AND, except they don't generate a result.
3193 let Defs = [EFLAGS] in {
3194 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
3195 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3196 "test{b}\t{$src2, $src1|$src1, $src2}",
3197 [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
3198 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3199 "test{w}\t{$src2, $src1|$src1, $src2}",
3200 [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
3203 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3204 "test{l}\t{$src2, $src1|$src1, $src2}",
3205 [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
3209 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
3210 "test{b}\t{$src, %al|%al, $src}", []>;
3211 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
3212 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3213 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
3214 "test{l}\t{$src, %eax|%eax, $src}", []>;
3216 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
3217 "test{b}\t{$src2, $src1|$src1, $src2}",
3218 [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
3220 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
3221 "test{w}\t{$src2, $src1|$src1, $src2}",
3222 [(set EFLAGS, (X86cmp (and GR16:$src1,
3223 (loadi16 addr:$src2)), 0))]>, OpSize;
3224 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
3225 "test{l}\t{$src2, $src1|$src1, $src2}",
3226 [(set EFLAGS, (X86cmp (and GR32:$src1,
3227 (loadi32 addr:$src2)), 0))]>;
3229 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
3230 (outs), (ins GR8:$src1, i8imm:$src2),
3231 "test{b}\t{$src2, $src1|$src1, $src2}",
3232 [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
3233 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
3234 (outs), (ins GR16:$src1, i16imm:$src2),
3235 "test{w}\t{$src2, $src1|$src1, $src2}",
3236 [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
3238 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
3239 (outs), (ins GR32:$src1, i32imm:$src2),
3240 "test{l}\t{$src2, $src1|$src1, $src2}",
3241 [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
3243 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
3244 (outs), (ins i8mem:$src1, i8imm:$src2),
3245 "test{b}\t{$src2, $src1|$src1, $src2}",
3246 [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
3248 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3249 (outs), (ins i16mem:$src1, i16imm:$src2),
3250 "test{w}\t{$src2, $src1|$src1, $src2}",
3251 [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
3253 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3254 (outs), (ins i32mem:$src1, i32imm:$src2),
3255 "test{l}\t{$src2, $src1|$src1, $src2}",
3256 [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
3258 } // Defs = [EFLAGS]
3261 // Condition code ops, incl. set if equal/not equal/...
3262 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3263 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3264 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3265 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3267 let Uses = [EFLAGS] in {
3268 // Use sbb to materialize carry bit.
3269 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
3270 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
3271 // However, Pat<> can't replicate the destination reg into the inputs of the
3273 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
3275 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
3276 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3277 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
3278 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
3280 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
3281 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3284 def SETEr : I<0x94, MRM0r,
3285 (outs GR8 :$dst), (ins),
3287 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3289 def SETEm : I<0x94, MRM0m,
3290 (outs), (ins i8mem:$dst),
3292 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3295 def SETNEr : I<0x95, MRM0r,
3296 (outs GR8 :$dst), (ins),
3298 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3300 def SETNEm : I<0x95, MRM0m,
3301 (outs), (ins i8mem:$dst),
3303 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3306 def SETLr : I<0x9C, MRM0r,
3307 (outs GR8 :$dst), (ins),
3309 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3310 TB; // GR8 = < signed
3311 def SETLm : I<0x9C, MRM0m,
3312 (outs), (ins i8mem:$dst),
3314 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3315 TB; // [mem8] = < signed
3317 def SETGEr : I<0x9D, MRM0r,
3318 (outs GR8 :$dst), (ins),
3320 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3321 TB; // GR8 = >= signed
3322 def SETGEm : I<0x9D, MRM0m,
3323 (outs), (ins i8mem:$dst),
3325 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3326 TB; // [mem8] = >= signed
3328 def SETLEr : I<0x9E, MRM0r,
3329 (outs GR8 :$dst), (ins),
3331 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3332 TB; // GR8 = <= signed
3333 def SETLEm : I<0x9E, MRM0m,
3334 (outs), (ins i8mem:$dst),
3336 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3337 TB; // [mem8] = <= signed
3339 def SETGr : I<0x9F, MRM0r,
3340 (outs GR8 :$dst), (ins),
3342 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3343 TB; // GR8 = > signed
3344 def SETGm : I<0x9F, MRM0m,
3345 (outs), (ins i8mem:$dst),
3347 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3348 TB; // [mem8] = > signed
3350 def SETBr : I<0x92, MRM0r,
3351 (outs GR8 :$dst), (ins),
3353 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3354 TB; // GR8 = < unsign
3355 def SETBm : I<0x92, MRM0m,
3356 (outs), (ins i8mem:$dst),
3358 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3359 TB; // [mem8] = < unsign
3361 def SETAEr : I<0x93, MRM0r,
3362 (outs GR8 :$dst), (ins),
3364 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3365 TB; // GR8 = >= unsign
3366 def SETAEm : I<0x93, MRM0m,
3367 (outs), (ins i8mem:$dst),
3369 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3370 TB; // [mem8] = >= unsign
3372 def SETBEr : I<0x96, MRM0r,
3373 (outs GR8 :$dst), (ins),
3375 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3376 TB; // GR8 = <= unsign
3377 def SETBEm : I<0x96, MRM0m,
3378 (outs), (ins i8mem:$dst),
3380 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3381 TB; // [mem8] = <= unsign
3383 def SETAr : I<0x97, MRM0r,
3384 (outs GR8 :$dst), (ins),
3386 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3387 TB; // GR8 = > signed
3388 def SETAm : I<0x97, MRM0m,
3389 (outs), (ins i8mem:$dst),
3391 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3392 TB; // [mem8] = > signed
3394 def SETSr : I<0x98, MRM0r,
3395 (outs GR8 :$dst), (ins),
3397 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3398 TB; // GR8 = <sign bit>
3399 def SETSm : I<0x98, MRM0m,
3400 (outs), (ins i8mem:$dst),
3402 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3403 TB; // [mem8] = <sign bit>
3404 def SETNSr : I<0x99, MRM0r,
3405 (outs GR8 :$dst), (ins),
3407 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3408 TB; // GR8 = !<sign bit>
3409 def SETNSm : I<0x99, MRM0m,
3410 (outs), (ins i8mem:$dst),
3412 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3413 TB; // [mem8] = !<sign bit>
3415 def SETPr : I<0x9A, MRM0r,
3416 (outs GR8 :$dst), (ins),
3418 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3420 def SETPm : I<0x9A, MRM0m,
3421 (outs), (ins i8mem:$dst),
3423 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3424 TB; // [mem8] = parity
3425 def SETNPr : I<0x9B, MRM0r,
3426 (outs GR8 :$dst), (ins),
3428 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3429 TB; // GR8 = not parity
3430 def SETNPm : I<0x9B, MRM0m,
3431 (outs), (ins i8mem:$dst),
3433 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3434 TB; // [mem8] = not parity
3436 def SETOr : I<0x90, MRM0r,
3437 (outs GR8 :$dst), (ins),
3439 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3440 TB; // GR8 = overflow
3441 def SETOm : I<0x90, MRM0m,
3442 (outs), (ins i8mem:$dst),
3444 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3445 TB; // [mem8] = overflow
3446 def SETNOr : I<0x91, MRM0r,
3447 (outs GR8 :$dst), (ins),
3449 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3450 TB; // GR8 = not overflow
3451 def SETNOm : I<0x91, MRM0m,
3452 (outs), (ins i8mem:$dst),
3454 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3455 TB; // [mem8] = not overflow
3456 } // Uses = [EFLAGS]
3459 // Integer comparisons
3460 let Defs = [EFLAGS] in {
3461 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3462 "cmp{b}\t{$src, %al|%al, $src}", []>;
3463 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3464 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3465 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3466 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3468 def CMP8rr : I<0x38, MRMDestReg,
3469 (outs), (ins GR8 :$src1, GR8 :$src2),
3470 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3471 [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
3472 def CMP16rr : I<0x39, MRMDestReg,
3473 (outs), (ins GR16:$src1, GR16:$src2),
3474 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3475 [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
3476 def CMP32rr : I<0x39, MRMDestReg,
3477 (outs), (ins GR32:$src1, GR32:$src2),
3478 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3479 [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
3480 def CMP8mr : I<0x38, MRMDestMem,
3481 (outs), (ins i8mem :$src1, GR8 :$src2),
3482 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3483 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
3484 def CMP16mr : I<0x39, MRMDestMem,
3485 (outs), (ins i16mem:$src1, GR16:$src2),
3486 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3487 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
3489 def CMP32mr : I<0x39, MRMDestMem,
3490 (outs), (ins i32mem:$src1, GR32:$src2),
3491 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3492 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
3493 def CMP8rm : I<0x3A, MRMSrcMem,
3494 (outs), (ins GR8 :$src1, i8mem :$src2),
3495 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3496 [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
3497 def CMP16rm : I<0x3B, MRMSrcMem,
3498 (outs), (ins GR16:$src1, i16mem:$src2),
3499 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3500 [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
3502 def CMP32rm : I<0x3B, MRMSrcMem,
3503 (outs), (ins GR32:$src1, i32mem:$src2),
3504 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3505 [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
3507 // These are alternate spellings for use by the disassembler, we mark them as
3508 // code gen only to ensure they aren't matched by the assembler.
3509 let isCodeGenOnly = 1 in {
3510 def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3511 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3512 def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3513 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3514 def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3515 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3518 def CMP8ri : Ii8<0x80, MRM7r,
3519 (outs), (ins GR8:$src1, i8imm:$src2),
3520 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3521 [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
3522 def CMP16ri : Ii16<0x81, MRM7r,
3523 (outs), (ins GR16:$src1, i16imm:$src2),
3524 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3525 [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
3526 def CMP32ri : Ii32<0x81, MRM7r,
3527 (outs), (ins GR32:$src1, i32imm:$src2),
3528 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3529 [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
3530 def CMP8mi : Ii8 <0x80, MRM7m,
3531 (outs), (ins i8mem :$src1, i8imm :$src2),
3532 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3533 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
3534 def CMP16mi : Ii16<0x81, MRM7m,
3535 (outs), (ins i16mem:$src1, i16imm:$src2),
3536 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3537 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
3539 def CMP32mi : Ii32<0x81, MRM7m,
3540 (outs), (ins i32mem:$src1, i32imm:$src2),
3541 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3542 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
3543 def CMP16ri8 : Ii8<0x83, MRM7r,
3544 (outs), (ins GR16:$src1, i16i8imm:$src2),
3545 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3546 [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
3548 def CMP16mi8 : Ii8<0x83, MRM7m,
3549 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3550 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3551 [(set EFLAGS, (X86cmp (loadi16 addr:$src1),
3552 i16immSExt8:$src2))]>, OpSize;
3553 def CMP32mi8 : Ii8<0x83, MRM7m,
3554 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3555 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3556 [(set EFLAGS, (X86cmp (loadi32 addr:$src1),
3557 i32immSExt8:$src2))]>;
3558 def CMP32ri8 : Ii8<0x83, MRM7r,
3559 (outs), (ins GR32:$src1, i32i8imm:$src2),
3560 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3561 [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
3562 } // Defs = [EFLAGS]
3565 // TODO: BTC, BTR, and BTS
3566 let Defs = [EFLAGS] in {
3567 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3568 "bt{w}\t{$src2, $src1|$src1, $src2}",
3569 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
3570 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3571 "bt{l}\t{$src2, $src1|$src1, $src2}",
3572 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
3574 // Unlike with the register+register form, the memory+register form of the
3575 // bt instruction does not ignore the high bits of the index. From ISel's
3576 // perspective, this is pretty bizarre. Make these instructions disassembly
3579 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3580 "bt{w}\t{$src2, $src1|$src1, $src2}",
3581 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3582 // (implicit EFLAGS)]
3584 >, OpSize, TB, Requires<[FastBTMem]>;
3585 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3586 "bt{l}\t{$src2, $src1|$src1, $src2}",
3587 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3588 // (implicit EFLAGS)]
3590 >, TB, Requires<[FastBTMem]>;
3592 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3593 "bt{w}\t{$src2, $src1|$src1, $src2}",
3594 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
3596 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3597 "bt{l}\t{$src2, $src1|$src1, $src2}",
3598 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
3599 // Note that these instructions don't need FastBTMem because that
3600 // only applies when the other operand is in a register. When it's
3601 // an immediate, bt is still fast.
3602 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3603 "bt{w}\t{$src2, $src1|$src1, $src2}",
3604 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
3606 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3607 "bt{l}\t{$src2, $src1|$src1, $src2}",
3608 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
3611 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3612 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3613 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3614 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3615 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3616 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3617 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3618 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3619 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3620 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3621 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3622 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3623 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3624 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3625 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3626 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3628 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3629 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3630 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3631 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3632 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3633 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3634 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3635 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3636 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3637 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3638 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3639 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3640 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3641 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3642 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3643 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3645 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3646 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3647 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3648 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3649 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3650 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3651 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3652 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3653 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3654 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3655 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3656 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3657 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3658 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3659 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3660 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3661 } // Defs = [EFLAGS]
3663 // Sign/Zero extenders
3664 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3665 // of the register here. This has a smaller encoding and avoids a
3666 // partial-register update. Actual movsbw included for the disassembler.
3667 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3668 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3669 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3670 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3671 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3672 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3673 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3674 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3675 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3676 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3677 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3678 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3679 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3680 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3681 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3682 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3683 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3684 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3685 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3686 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3688 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3689 // of the register here. This has a smaller encoding and avoids a
3690 // partial-register update. Actual movzbw included for the disassembler.
3691 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3692 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3693 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3694 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3695 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3696 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3697 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3698 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3699 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3700 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3701 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3702 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3703 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3704 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3705 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3706 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3707 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3708 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3709 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3710 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3712 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
3713 // except that they use GR32_NOREX for the output operand register class
3714 // instead of GR32. This allows them to operate on h registers on x86-64.
3715 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3716 (outs GR32_NOREX:$dst), (ins GR8:$src),
3717 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3720 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3721 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3722 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3725 let neverHasSideEffects = 1 in {
3726 let Defs = [AX], Uses = [AL] in
3727 def CBW : I<0x98, RawFrm, (outs), (ins),
3728 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3729 let Defs = [EAX], Uses = [AX] in
3730 def CWDE : I<0x98, RawFrm, (outs), (ins),
3731 "{cwtl|cwde}", []>; // EAX = signext(AX)
3733 let Defs = [AX,DX], Uses = [AX] in
3734 def CWD : I<0x99, RawFrm, (outs), (ins),
3735 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3736 let Defs = [EAX,EDX], Uses = [EAX] in
3737 def CDQ : I<0x99, RawFrm, (outs), (ins),
3738 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3741 //===----------------------------------------------------------------------===//
3742 // Alias Instructions
3743 //===----------------------------------------------------------------------===//
3745 // Alias instructions that map movr0 to xor.
3746 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3747 // FIXME: Set encoding to pseudo.
3748 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3749 isCodeGenOnly = 1 in {
3750 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
3751 [(set GR8:$dst, 0)]>;
3753 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
3754 // encoding and avoids a partial-register update sometimes, but doing so
3755 // at isel time interferes with rematerialization in the current register
3756 // allocator. For now, this is rewritten when the instruction is lowered
3758 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3760 [(set GR16:$dst, 0)]>, OpSize;
3762 // FIXME: Set encoding to pseudo.
3763 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
3764 [(set GR32:$dst, 0)]>;
3767 //===----------------------------------------------------------------------===//
3768 // Thread Local Storage Instructions
3771 // All calls clobber the non-callee saved registers. ESP is marked as
3772 // a use to prevent stack-pointer assignments that appear immediately
3773 // before calls from potentially appearing dead.
3774 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3775 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3776 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3777 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3779 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3780 "leal\t$sym, %eax; "
3781 "call\t___tls_get_addr@PLT",
3782 [(X86tlsaddr tls32addr:$sym)]>,
3783 Requires<[In32BitMode]>;
3785 let AddedComplexity = 5, isCodeGenOnly = 1 in
3786 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3787 "movl\t%gs:$src, $dst",
3788 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3790 let AddedComplexity = 5, isCodeGenOnly = 1 in
3791 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3792 "movl\t%fs:$src, $dst",
3793 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3795 //===----------------------------------------------------------------------===//
3796 // EH Pseudo Instructions
3798 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3799 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3800 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3801 "ret\t#eh_return, addr: $addr",
3802 [(X86ehret GR32:$addr)]>;
3806 //===----------------------------------------------------------------------===//
3810 // Atomic swap. These are just normal xchg instructions. But since a memory
3811 // operand is referenced, the atomicity is ensured.
3812 let Constraints = "$val = $dst" in {
3813 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3814 (ins GR32:$val, i32mem:$ptr),
3815 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3816 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3817 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3818 (ins GR16:$val, i16mem:$ptr),
3819 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3820 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3822 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3823 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3824 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3826 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3827 "xchg{l}\t{$val, $src|$src, $val}", []>;
3828 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3829 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3830 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3831 "xchg{b}\t{$val, $src|$src, $val}", []>;
3834 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3835 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3836 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3837 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
3839 // Atomic compare and swap.
3840 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3841 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3843 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3844 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3846 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3847 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
3850 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3853 let Defs = [AX, EFLAGS], Uses = [AX] in {
3854 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3856 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3857 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3859 let Defs = [AL, EFLAGS], Uses = [AL] in {
3860 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3862 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3863 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3866 // Atomic exchange and add
3867 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3868 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
3870 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3871 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3873 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
3875 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3876 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3878 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3880 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3881 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3885 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3886 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3887 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3888 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3889 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3890 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3892 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3893 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3894 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3895 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3896 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3897 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3899 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3900 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3901 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3902 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3903 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3904 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3906 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3907 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3908 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3909 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3910 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3911 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3913 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
3914 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
3915 "cmpxchg8b\t$dst", []>, TB;
3917 // Optimized codegen when the non-memory output is not used.
3918 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3919 let Defs = [EFLAGS] in {
3920 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3922 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3923 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3925 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3926 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3928 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3929 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3931 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3932 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3934 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3935 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3937 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3938 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3940 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3941 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3943 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3945 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3947 "inc{b}\t$dst", []>, LOCK;
3948 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3950 "inc{w}\t$dst", []>, OpSize, LOCK;
3951 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3953 "inc{l}\t$dst", []>, LOCK;
3955 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3957 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3958 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3960 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3961 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3963 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3964 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3966 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3967 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3969 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3970 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3972 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3973 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3975 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3976 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3978 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3980 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3982 "dec{b}\t$dst", []>, LOCK;
3983 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3985 "dec{w}\t$dst", []>, OpSize, LOCK;
3986 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3988 "dec{l}\t$dst", []>, LOCK;
3991 // Atomic exchange, and, or, xor
3992 let Constraints = "$val = $dst", Defs = [EFLAGS],
3993 usesCustomInserter = 1 in {
3994 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3995 "#ATOMAND32 PSEUDO!",
3996 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3997 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3998 "#ATOMOR32 PSEUDO!",
3999 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
4000 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4001 "#ATOMXOR32 PSEUDO!",
4002 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
4003 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4004 "#ATOMNAND32 PSEUDO!",
4005 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
4006 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
4007 "#ATOMMIN32 PSEUDO!",
4008 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
4009 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4010 "#ATOMMAX32 PSEUDO!",
4011 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
4012 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4013 "#ATOMUMIN32 PSEUDO!",
4014 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
4015 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4016 "#ATOMUMAX32 PSEUDO!",
4017 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
4019 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4020 "#ATOMAND16 PSEUDO!",
4021 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
4022 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4023 "#ATOMOR16 PSEUDO!",
4024 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
4025 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4026 "#ATOMXOR16 PSEUDO!",
4027 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
4028 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4029 "#ATOMNAND16 PSEUDO!",
4030 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
4031 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
4032 "#ATOMMIN16 PSEUDO!",
4033 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
4034 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4035 "#ATOMMAX16 PSEUDO!",
4036 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
4037 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4038 "#ATOMUMIN16 PSEUDO!",
4039 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
4040 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4041 "#ATOMUMAX16 PSEUDO!",
4042 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
4044 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4045 "#ATOMAND8 PSEUDO!",
4046 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
4047 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4049 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
4050 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4051 "#ATOMXOR8 PSEUDO!",
4052 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
4053 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4054 "#ATOMNAND8 PSEUDO!",
4055 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
4058 let Constraints = "$val1 = $dst1, $val2 = $dst2",
4059 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
4060 Uses = [EAX, EBX, ECX, EDX],
4061 mayLoad = 1, mayStore = 1,
4062 usesCustomInserter = 1 in {
4063 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4064 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4065 "#ATOMAND6432 PSEUDO!", []>;
4066 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4067 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4068 "#ATOMOR6432 PSEUDO!", []>;
4069 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4070 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4071 "#ATOMXOR6432 PSEUDO!", []>;
4072 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4073 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4074 "#ATOMNAND6432 PSEUDO!", []>;
4075 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4076 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4077 "#ATOMADD6432 PSEUDO!", []>;
4078 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4079 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4080 "#ATOMSUB6432 PSEUDO!", []>;
4081 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4082 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4083 "#ATOMSWAP6432 PSEUDO!", []>;
4086 // Segmentation support instructions.
4088 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4089 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4090 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4091 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4093 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
4094 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
4095 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4096 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4097 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4099 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4100 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4101 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4102 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4103 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4104 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4105 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4106 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4108 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
4110 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
4111 "str{w}\t{$dst}", []>, TB;
4112 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
4113 "str{w}\t{$dst}", []>, TB;
4114 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
4115 "ltr{w}\t{$src}", []>, TB;
4116 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
4117 "ltr{w}\t{$src}", []>, TB;
4119 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
4120 "push{w}\t%fs", []>, OpSize, TB;
4121 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
4122 "push{l}\t%fs", []>, TB;
4123 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
4124 "push{w}\t%gs", []>, OpSize, TB;
4125 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
4126 "push{l}\t%gs", []>, TB;
4128 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
4129 "pop{w}\t%fs", []>, OpSize, TB;
4130 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
4131 "pop{l}\t%fs", []>, TB;
4132 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
4133 "pop{w}\t%gs", []>, OpSize, TB;
4134 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
4135 "pop{l}\t%gs", []>, TB;
4137 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4138 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4139 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4140 "lds{l}\t{$src, $dst|$dst, $src}", []>;
4141 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4142 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4143 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4144 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
4145 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4146 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4147 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4148 "les{l}\t{$src, $dst|$dst, $src}", []>;
4149 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4150 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4151 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4152 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4153 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4154 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4155 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4156 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4158 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
4159 "verr\t$seg", []>, TB;
4160 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
4161 "verr\t$seg", []>, TB;
4162 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
4163 "verw\t$seg", []>, TB;
4164 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
4165 "verw\t$seg", []>, TB;
4167 // Descriptor-table support instructions
4169 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
4170 "sgdt\t$dst", []>, TB;
4171 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
4172 "sidt\t$dst", []>, TB;
4173 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
4174 "sldt{w}\t$dst", []>, TB;
4175 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
4176 "sldt{w}\t$dst", []>, TB;
4177 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
4178 "lgdt\t$src", []>, TB;
4179 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
4180 "lidt\t$src", []>, TB;
4181 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
4182 "lldt{w}\t$src", []>, TB;
4183 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
4184 "lldt{w}\t$src", []>, TB;
4186 // Lock instruction prefix
4187 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
4189 // Repeat string operation instruction prefixes
4190 // These uses the DF flag in the EFLAGS register to inc or dec ECX
4191 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
4192 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
4193 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
4194 // Repeat while not equal (used with CMPS and SCAS)
4195 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
4198 // Segment override instruction prefixes
4199 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
4200 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
4201 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
4202 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
4203 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
4204 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
4206 // String manipulation instructions
4208 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
4209 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
4210 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
4212 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
4213 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
4214 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
4216 // CPU flow control instructions
4218 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
4219 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
4221 // FPU control instructions
4223 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
4225 // Flag instructions
4227 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
4228 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
4229 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
4230 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
4231 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
4232 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
4233 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
4235 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
4237 // Table lookup instructions
4239 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
4241 // Specialized register support
4243 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
4244 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
4245 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
4247 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
4248 "smsw{w}\t$dst", []>, OpSize, TB;
4249 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
4250 "smsw{l}\t$dst", []>, TB;
4251 // For memory operands, there is only a 16-bit form
4252 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
4253 "smsw{w}\t$dst", []>, TB;
4255 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
4256 "lmsw{w}\t$src", []>, TB;
4257 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
4258 "lmsw{w}\t$src", []>, TB;
4260 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
4262 // Cache instructions
4264 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
4265 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
4270 def INVEPT : I<0x80, RawFrm, (outs), (ins), "invept", []>, OpSize, T8;
4272 def INVVPID : I<0x81, RawFrm, (outs), (ins), "invvpid", []>, OpSize, T8;
4274 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
4275 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4276 "vmclear\t$vmcs", []>, OpSize, TB;
4278 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
4280 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
4281 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4282 "vmptrld\t$vmcs", []>, TB;
4283 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4284 "vmptrst\t$vmcs", []>, TB;
4285 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
4286 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4287 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
4288 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4289 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
4290 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4291 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4292 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4293 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4294 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4295 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4296 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4297 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4298 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4299 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4300 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4302 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
4303 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
4304 "vmxon\t{$vmxon}", []>, XS;
4306 //===----------------------------------------------------------------------===//
4307 // Non-Instruction Patterns
4308 //===----------------------------------------------------------------------===//
4310 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
4311 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
4312 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
4313 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
4314 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
4315 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
4316 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
4318 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
4319 (ADD32ri GR32:$src1, tconstpool:$src2)>;
4320 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
4321 (ADD32ri GR32:$src1, tjumptable:$src2)>;
4322 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
4323 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
4324 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
4325 (ADD32ri GR32:$src1, texternalsym:$src2)>;
4326 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
4327 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
4329 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
4330 (MOV32mi addr:$dst, tglobaladdr:$src)>;
4331 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
4332 (MOV32mi addr:$dst, texternalsym:$src)>;
4333 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
4334 (MOV32mi addr:$dst, tblockaddress:$src)>;
4338 def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
4339 (TCRETURNri GR32_TC:$dst, imm:$off)>,
4340 Requires<[In32BitMode]>;
4342 // FIXME: This is disabled for 32-bit PIC mode because the global base
4343 // register which is part of the address mode may be assigned a
4344 // callee-saved register.
4345 def : Pat<(X86tcret (load addr:$dst), imm:$off),
4346 (TCRETURNmi addr:$dst, imm:$off)>,
4347 Requires<[In32BitMode, IsNotPIC]>;
4349 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
4350 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4351 Requires<[In32BitMode]>;
4353 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
4354 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4355 Requires<[In32BitMode]>;
4357 // Normal calls, with various flavors of addresses.
4358 def : Pat<(X86call (i32 tglobaladdr:$dst)),
4359 (CALLpcrel32 tglobaladdr:$dst)>;
4360 def : Pat<(X86call (i32 texternalsym:$dst)),
4361 (CALLpcrel32 texternalsym:$dst)>;
4362 def : Pat<(X86call (i32 imm:$dst)),
4363 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
4365 // X86 specific add which produces a flag.
4366 def : Pat<(addc GR32:$src1, GR32:$src2),
4367 (ADD32rr GR32:$src1, GR32:$src2)>;
4368 def : Pat<(addc GR32:$src1, (load addr:$src2)),
4369 (ADD32rm GR32:$src1, addr:$src2)>;
4370 def : Pat<(addc GR32:$src1, imm:$src2),
4371 (ADD32ri GR32:$src1, imm:$src2)>;
4372 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
4373 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4375 def : Pat<(subc GR32:$src1, GR32:$src2),
4376 (SUB32rr GR32:$src1, GR32:$src2)>;
4377 def : Pat<(subc GR32:$src1, (load addr:$src2)),
4378 (SUB32rm GR32:$src1, addr:$src2)>;
4379 def : Pat<(subc GR32:$src1, imm:$src2),
4380 (SUB32ri GR32:$src1, imm:$src2)>;
4381 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
4382 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4386 // TEST R,R is smaller than CMP R,0
4387 def : Pat<(X86cmp GR8:$src1, 0),
4388 (TEST8rr GR8:$src1, GR8:$src1)>;
4389 def : Pat<(X86cmp GR16:$src1, 0),
4390 (TEST16rr GR16:$src1, GR16:$src1)>;
4391 def : Pat<(X86cmp GR32:$src1, 0),
4392 (TEST32rr GR32:$src1, GR32:$src1)>;
4394 // Conditional moves with folded loads with operands swapped and conditions
4396 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
4397 (CMOVAE16rm GR16:$src2, addr:$src1)>;
4398 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
4399 (CMOVAE32rm GR32:$src2, addr:$src1)>;
4400 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
4401 (CMOVB16rm GR16:$src2, addr:$src1)>;
4402 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
4403 (CMOVB32rm GR32:$src2, addr:$src1)>;
4404 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
4405 (CMOVNE16rm GR16:$src2, addr:$src1)>;
4406 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
4407 (CMOVNE32rm GR32:$src2, addr:$src1)>;
4408 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
4409 (CMOVE16rm GR16:$src2, addr:$src1)>;
4410 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
4411 (CMOVE32rm GR32:$src2, addr:$src1)>;
4412 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
4413 (CMOVA16rm GR16:$src2, addr:$src1)>;
4414 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
4415 (CMOVA32rm GR32:$src2, addr:$src1)>;
4416 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
4417 (CMOVBE16rm GR16:$src2, addr:$src1)>;
4418 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
4419 (CMOVBE32rm GR32:$src2, addr:$src1)>;
4420 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
4421 (CMOVGE16rm GR16:$src2, addr:$src1)>;
4422 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
4423 (CMOVGE32rm GR32:$src2, addr:$src1)>;
4424 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
4425 (CMOVL16rm GR16:$src2, addr:$src1)>;
4426 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
4427 (CMOVL32rm GR32:$src2, addr:$src1)>;
4428 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
4429 (CMOVG16rm GR16:$src2, addr:$src1)>;
4430 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
4431 (CMOVG32rm GR32:$src2, addr:$src1)>;
4432 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
4433 (CMOVLE16rm GR16:$src2, addr:$src1)>;
4434 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
4435 (CMOVLE32rm GR32:$src2, addr:$src1)>;
4436 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
4437 (CMOVNP16rm GR16:$src2, addr:$src1)>;
4438 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
4439 (CMOVNP32rm GR32:$src2, addr:$src1)>;
4440 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
4441 (CMOVP16rm GR16:$src2, addr:$src1)>;
4442 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
4443 (CMOVP32rm GR32:$src2, addr:$src1)>;
4444 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
4445 (CMOVNS16rm GR16:$src2, addr:$src1)>;
4446 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
4447 (CMOVNS32rm GR32:$src2, addr:$src1)>;
4448 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
4449 (CMOVS16rm GR16:$src2, addr:$src1)>;
4450 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
4451 (CMOVS32rm GR32:$src2, addr:$src1)>;
4452 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
4453 (CMOVNO16rm GR16:$src2, addr:$src1)>;
4454 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
4455 (CMOVNO32rm GR32:$src2, addr:$src1)>;
4456 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
4457 (CMOVO16rm GR16:$src2, addr:$src1)>;
4458 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
4459 (CMOVO32rm GR32:$src2, addr:$src1)>;
4461 // zextload bool -> zextload byte
4462 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4463 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4464 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4466 // extload bool -> extload byte
4467 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4468 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4469 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4470 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
4471 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
4472 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
4474 // anyext. Define these to do an explicit zero-extend to
4475 // avoid partial-register updates.
4476 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
4477 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
4478 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
4480 //===----------------------------------------------------------------------===//
4482 //===----------------------------------------------------------------------===//
4484 // Odd encoding trick: -128 fits into an 8-bit immediate field while
4485 // +128 doesn't, so in this special case use a sub instead of an add.
4486 def : Pat<(add GR16:$src1, 128),
4487 (SUB16ri8 GR16:$src1, -128)>;
4488 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
4489 (SUB16mi8 addr:$dst, -128)>;
4490 def : Pat<(add GR32:$src1, 128),
4491 (SUB32ri8 GR32:$src1, -128)>;
4492 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
4493 (SUB32mi8 addr:$dst, -128)>;
4495 // r & (2^16-1) ==> movz
4496 def : Pat<(and GR32:$src1, 0xffff),
4497 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
4498 // r & (2^8-1) ==> movz
4499 def : Pat<(and GR32:$src1, 0xff),
4500 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
4503 Requires<[In32BitMode]>;
4504 // r & (2^8-1) ==> movz
4505 def : Pat<(and GR16:$src1, 0xff),
4506 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
4509 Requires<[In32BitMode]>;
4511 // sext_inreg patterns
4512 def : Pat<(sext_inreg GR32:$src, i16),
4513 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
4514 def : Pat<(sext_inreg GR32:$src, i8),
4515 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4518 Requires<[In32BitMode]>;
4519 def : Pat<(sext_inreg GR16:$src, i8),
4520 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4523 Requires<[In32BitMode]>;
4526 def : Pat<(i16 (trunc GR32:$src)),
4527 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
4528 def : Pat<(i8 (trunc GR32:$src)),
4529 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4531 Requires<[In32BitMode]>;
4532 def : Pat<(i8 (trunc GR16:$src)),
4533 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4535 Requires<[In32BitMode]>;
4537 // h-register tricks
4538 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
4539 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4540 x86_subreg_8bit_hi)>,
4541 Requires<[In32BitMode]>;
4542 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
4543 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4544 x86_subreg_8bit_hi)>,
4545 Requires<[In32BitMode]>;
4546 def : Pat<(srl GR16:$src, (i8 8)),
4549 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4550 x86_subreg_8bit_hi)),
4552 Requires<[In32BitMode]>;
4553 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4554 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4556 x86_subreg_8bit_hi))>,
4557 Requires<[In32BitMode]>;
4558 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4559 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4561 x86_subreg_8bit_hi))>,
4562 Requires<[In32BitMode]>;
4563 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4564 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4566 x86_subreg_8bit_hi))>,
4567 Requires<[In32BitMode]>;
4569 // (shl x, 1) ==> (add x, x)
4570 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
4571 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
4572 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
4574 // (shl x (and y, 31)) ==> (shl x, y)
4575 def : Pat<(shl GR8:$src1, (and CL, 31)),
4576 (SHL8rCL GR8:$src1)>;
4577 def : Pat<(shl GR16:$src1, (and CL, 31)),
4578 (SHL16rCL GR16:$src1)>;
4579 def : Pat<(shl GR32:$src1, (and CL, 31)),
4580 (SHL32rCL GR32:$src1)>;
4581 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4582 (SHL8mCL addr:$dst)>;
4583 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4584 (SHL16mCL addr:$dst)>;
4585 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4586 (SHL32mCL addr:$dst)>;
4588 def : Pat<(srl GR8:$src1, (and CL, 31)),
4589 (SHR8rCL GR8:$src1)>;
4590 def : Pat<(srl GR16:$src1, (and CL, 31)),
4591 (SHR16rCL GR16:$src1)>;
4592 def : Pat<(srl GR32:$src1, (and CL, 31)),
4593 (SHR32rCL GR32:$src1)>;
4594 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4595 (SHR8mCL addr:$dst)>;
4596 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4597 (SHR16mCL addr:$dst)>;
4598 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4599 (SHR32mCL addr:$dst)>;
4601 def : Pat<(sra GR8:$src1, (and CL, 31)),
4602 (SAR8rCL GR8:$src1)>;
4603 def : Pat<(sra GR16:$src1, (and CL, 31)),
4604 (SAR16rCL GR16:$src1)>;
4605 def : Pat<(sra GR32:$src1, (and CL, 31)),
4606 (SAR32rCL GR32:$src1)>;
4607 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4608 (SAR8mCL addr:$dst)>;
4609 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4610 (SAR16mCL addr:$dst)>;
4611 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4612 (SAR32mCL addr:$dst)>;
4614 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
4615 def : Pat<(or (srl GR32:$src1, CL:$amt),
4616 (shl GR32:$src2, (sub 32, CL:$amt))),
4617 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4619 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
4620 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4621 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4623 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
4624 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4625 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4627 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4628 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4630 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4632 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm/*:$amt2*/)),
4633 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4635 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
4636 GR32:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4637 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4639 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
4640 def : Pat<(or (shl GR32:$src1, CL:$amt),
4641 (srl GR32:$src2, (sub 32, CL:$amt))),
4642 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4644 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
4645 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4646 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4648 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
4649 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4650 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4652 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4653 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4655 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4657 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm/*:$amt2*/)),
4658 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4660 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
4661 GR32:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4662 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4664 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
4665 def : Pat<(or (srl GR16:$src1, CL:$amt),
4666 (shl GR16:$src2, (sub 16, CL:$amt))),
4667 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4669 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
4670 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4671 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4673 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
4674 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4675 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4677 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4678 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4680 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4682 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm/*:$amt2*/)),
4683 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4685 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
4686 GR16:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4687 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4689 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
4690 def : Pat<(or (shl GR16:$src1, CL:$amt),
4691 (srl GR16:$src2, (sub 16, CL:$amt))),
4692 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4694 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
4695 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4696 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4698 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
4699 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4700 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4702 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4703 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4705 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4707 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm/*:$amt2*/)),
4708 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4710 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
4711 GR16:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4712 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4714 // (anyext (setcc_carry)) -> (setcc_carry)
4715 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4717 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4720 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
4721 let AddedComplexity = 5 in { // Try this before the selecting to OR
4722 def : Pat<(or_is_add GR16:$src1, imm:$src2),
4723 (ADD16ri GR16:$src1, imm:$src2)>;
4724 def : Pat<(or_is_add GR32:$src1, imm:$src2),
4725 (ADD32ri GR32:$src1, imm:$src2)>;
4726 def : Pat<(or_is_add GR16:$src1, i16immSExt8:$src2),
4727 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4728 def : Pat<(or_is_add GR32:$src1, i32immSExt8:$src2),
4729 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4730 def : Pat<(or_is_add GR16:$src1, GR16:$src2),
4731 (ADD16rr GR16:$src1, GR16:$src2)>;
4732 def : Pat<(or_is_add GR32:$src1, GR32:$src2),
4733 (ADD32rr GR32:$src1, GR32:$src2)>;
4734 } // AddedComplexity
4736 //===----------------------------------------------------------------------===//
4737 // EFLAGS-defining Patterns
4738 //===----------------------------------------------------------------------===//
4741 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
4742 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
4743 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
4746 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
4747 (ADD8rm GR8:$src1, addr:$src2)>;
4748 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
4749 (ADD16rm GR16:$src1, addr:$src2)>;
4750 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
4751 (ADD32rm GR32:$src1, addr:$src2)>;
4754 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
4755 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
4756 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
4757 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
4758 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4759 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
4760 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4763 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
4764 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
4765 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
4768 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
4769 (SUB8rm GR8:$src1, addr:$src2)>;
4770 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
4771 (SUB16rm GR16:$src1, addr:$src2)>;
4772 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
4773 (SUB32rm GR32:$src1, addr:$src2)>;
4776 def : Pat<(sub GR8:$src1, imm:$src2),
4777 (SUB8ri GR8:$src1, imm:$src2)>;
4778 def : Pat<(sub GR16:$src1, imm:$src2),
4779 (SUB16ri GR16:$src1, imm:$src2)>;
4780 def : Pat<(sub GR32:$src1, imm:$src2),
4781 (SUB32ri GR32:$src1, imm:$src2)>;
4782 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
4783 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4784 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
4785 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4788 def : Pat<(mul GR16:$src1, GR16:$src2),
4789 (IMUL16rr GR16:$src1, GR16:$src2)>;
4790 def : Pat<(mul GR32:$src1, GR32:$src2),
4791 (IMUL32rr GR32:$src1, GR32:$src2)>;
4794 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
4795 (IMUL16rm GR16:$src1, addr:$src2)>;
4796 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
4797 (IMUL32rm GR32:$src1, addr:$src2)>;
4800 def : Pat<(mul GR16:$src1, imm:$src2),
4801 (IMUL16rri GR16:$src1, imm:$src2)>;
4802 def : Pat<(mul GR32:$src1, imm:$src2),
4803 (IMUL32rri GR32:$src1, imm:$src2)>;
4804 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
4805 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4806 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
4807 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4809 // reg = mul mem, imm
4810 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
4811 (IMUL16rmi addr:$src1, imm:$src2)>;
4812 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
4813 (IMUL32rmi addr:$src1, imm:$src2)>;
4814 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
4815 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4816 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
4817 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4819 // Optimize multiply by 2 with EFLAGS result.
4820 let AddedComplexity = 2 in {
4821 def : Pat<(X86smul_flag GR16:$src1, 2), (ADD16rr GR16:$src1, GR16:$src1)>;
4822 def : Pat<(X86smul_flag GR32:$src1, 2), (ADD32rr GR32:$src1, GR32:$src1)>;
4825 // Patterns for nodes that do not produce flags, for instructions that do.
4828 def : Pat<(add GR8:$src , 1), (INC8r GR8:$src)>;
4829 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>;
4830 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>;
4833 def : Pat<(add GR8:$src , -1), (DEC8r GR8:$src)>;
4834 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
4835 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
4838 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
4839 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
4840 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
4843 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
4844 (OR8rm GR8:$src1, addr:$src2)>;
4845 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
4846 (OR16rm GR16:$src1, addr:$src2)>;
4847 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
4848 (OR32rm GR32:$src1, addr:$src2)>;
4851 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
4852 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
4853 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
4854 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
4855 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4856 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
4857 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4860 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
4861 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
4862 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
4865 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
4866 (XOR8rm GR8:$src1, addr:$src2)>;
4867 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
4868 (XOR16rm GR16:$src1, addr:$src2)>;
4869 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
4870 (XOR32rm GR32:$src1, addr:$src2)>;
4873 def : Pat<(xor GR8:$src1, imm:$src2),
4874 (XOR8ri GR8:$src1, imm:$src2)>;
4875 def : Pat<(xor GR16:$src1, imm:$src2),
4876 (XOR16ri GR16:$src1, imm:$src2)>;
4877 def : Pat<(xor GR32:$src1, imm:$src2),
4878 (XOR32ri GR32:$src1, imm:$src2)>;
4879 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
4880 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4881 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
4882 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4885 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
4886 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
4887 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
4890 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
4891 (AND8rm GR8:$src1, addr:$src2)>;
4892 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
4893 (AND16rm GR16:$src1, addr:$src2)>;
4894 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
4895 (AND32rm GR32:$src1, addr:$src2)>;
4898 def : Pat<(and GR8:$src1, imm:$src2),
4899 (AND8ri GR8:$src1, imm:$src2)>;
4900 def : Pat<(and GR16:$src1, imm:$src2),
4901 (AND16ri GR16:$src1, imm:$src2)>;
4902 def : Pat<(and GR32:$src1, imm:$src2),
4903 (AND32ri GR32:$src1, imm:$src2)>;
4904 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
4905 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
4906 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
4907 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
4909 // -disable-16bit support.
4910 def : Pat<(truncstorei16 (i16 imm:$src), addr:$dst),
4911 (MOV16mi addr:$dst, imm:$src)>;
4912 def : Pat<(truncstorei16 GR32:$src, addr:$dst),
4913 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
4914 def : Pat<(i32 (sextloadi16 addr:$dst)),
4915 (MOVSX32rm16 addr:$dst)>;
4916 def : Pat<(i32 (zextloadi16 addr:$dst)),
4917 (MOVZX32rm16 addr:$dst)>;
4918 def : Pat<(i32 (extloadi16 addr:$dst)),
4919 (MOVZX32rm16 addr:$dst)>;
4921 //===----------------------------------------------------------------------===//
4922 // Floating Point Stack Support
4923 //===----------------------------------------------------------------------===//
4925 include "X86InstrFPStack.td"
4927 //===----------------------------------------------------------------------===//
4929 //===----------------------------------------------------------------------===//
4931 include "X86Instr64bit.td"
4933 //===----------------------------------------------------------------------===//
4934 // SIMD support (SSE, MMX and AVX)
4935 //===----------------------------------------------------------------------===//
4937 include "X86InstrFragmentsSIMD.td"
4939 //===----------------------------------------------------------------------===//
4940 // XMM Floating point support (requires SSE / SSE2)
4941 //===----------------------------------------------------------------------===//
4943 include "X86InstrSSE.td"
4945 //===----------------------------------------------------------------------===//
4946 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
4947 //===----------------------------------------------------------------------===//
4949 include "X86InstrMMX.td"