1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 def SDTX86BrCond : SDTypeProfile<0, 3,
31 [SDTCisVT<0, OtherVT>,
32 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
34 def SDTX86SetCC : SDTypeProfile<1, 2,
36 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
38 def SDTX86Ret : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>;
40 def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
41 def SDT_X86CallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
44 def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
46 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
48 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
50 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
52 def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
54 def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
56 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
58 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
60 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
61 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
62 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
63 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
65 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
67 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
68 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
70 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
72 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
73 [SDNPHasChain, SDNPOptInFlag]>;
75 def X86callseq_start :
76 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
77 [SDNPHasChain, SDNPOutFlag]>;
79 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
82 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
83 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
85 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
86 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
88 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
89 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
90 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
91 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
94 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
95 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
97 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
98 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
100 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
101 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
102 def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
104 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
107 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
108 [SDNPHasChain, SDNPOptInFlag]>;
110 //===----------------------------------------------------------------------===//
111 // X86 Operand Definitions.
114 // *mem - Operand definitions for the funky X86 addressing mode operands.
116 class X86MemOperand<string printMethod> : Operand<iPTR> {
117 let PrintMethod = printMethod;
118 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
121 def i8mem : X86MemOperand<"printi8mem">;
122 def i16mem : X86MemOperand<"printi16mem">;
123 def i32mem : X86MemOperand<"printi32mem">;
124 def i64mem : X86MemOperand<"printi64mem">;
125 def i128mem : X86MemOperand<"printi128mem">;
126 def f32mem : X86MemOperand<"printf32mem">;
127 def f64mem : X86MemOperand<"printf64mem">;
128 def f80mem : X86MemOperand<"printf80mem">;
129 def f128mem : X86MemOperand<"printf128mem">;
131 def lea32mem : Operand<i32> {
132 let PrintMethod = "printi32mem";
133 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
136 def SSECC : Operand<i8> {
137 let PrintMethod = "printSSECC";
140 def piclabel: Operand<i32> {
141 let PrintMethod = "printPICLabel";
144 // A couple of more descriptive operand definitions.
145 // 16-bits but only 8 bits are significant.
146 def i16i8imm : Operand<i16>;
147 // 32-bits but only 8 bits are significant.
148 def i32i8imm : Operand<i32>;
150 // Branch targets have OtherVT type.
151 def brtarget : Operand<OtherVT>;
153 //===----------------------------------------------------------------------===//
154 // X86 Complex Pattern Definitions.
157 // Define X86 specific addressing mode.
158 def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
159 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
160 [add, mul, shl, or, frameindex], []>;
162 //===----------------------------------------------------------------------===//
163 // X86 Instruction Predicate Definitions.
164 def HasMMX : Predicate<"Subtarget->hasMMX()">;
165 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
166 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
167 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
168 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
169 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
170 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
171 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
172 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
173 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
174 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
175 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
176 def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
177 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
179 //===----------------------------------------------------------------------===//
180 // X86 Instruction Format Definitions.
183 include "X86InstrFormats.td"
185 //===----------------------------------------------------------------------===//
186 // Pattern fragments...
189 // X86 specific condition code. These correspond to CondCode in
190 // X86InstrInfo.h. They must be kept in synch.
191 def X86_COND_A : PatLeaf<(i8 0)>;
192 def X86_COND_AE : PatLeaf<(i8 1)>;
193 def X86_COND_B : PatLeaf<(i8 2)>;
194 def X86_COND_BE : PatLeaf<(i8 3)>;
195 def X86_COND_E : PatLeaf<(i8 4)>;
196 def X86_COND_G : PatLeaf<(i8 5)>;
197 def X86_COND_GE : PatLeaf<(i8 6)>;
198 def X86_COND_L : PatLeaf<(i8 7)>;
199 def X86_COND_LE : PatLeaf<(i8 8)>;
200 def X86_COND_NE : PatLeaf<(i8 9)>;
201 def X86_COND_NO : PatLeaf<(i8 10)>;
202 def X86_COND_NP : PatLeaf<(i8 11)>;
203 def X86_COND_NS : PatLeaf<(i8 12)>;
204 def X86_COND_O : PatLeaf<(i8 13)>;
205 def X86_COND_P : PatLeaf<(i8 14)>;
206 def X86_COND_S : PatLeaf<(i8 15)>;
208 def i16immSExt8 : PatLeaf<(i16 imm), [{
209 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
210 // sign extended field.
211 return (int16_t)N->getValue() == (int8_t)N->getValue();
214 def i32immSExt8 : PatLeaf<(i32 imm), [{
215 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
216 // sign extended field.
217 return (int32_t)N->getValue() == (int8_t)N->getValue();
220 // Helper fragments for loads.
221 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
222 def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>;
223 def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>;
224 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
226 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
227 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
228 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
230 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
231 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
232 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
234 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
235 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
236 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
237 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
238 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
239 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
241 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
242 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
243 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
244 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
245 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
246 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
249 // An 'and' node with a single use.
250 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
251 return AlwaysFoldAndInTest || N->hasOneUse();
254 //===----------------------------------------------------------------------===//
255 // Instruction list...
258 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
259 // a stack adjustment and the codegen must know that they may modify the stack
260 // pointer before prolog-epilog rewriting occurs.
261 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become sub / add
262 // which can clobber EFLAGS.
263 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
264 def ADJCALLSTACKDOWN : I<0, Pseudo, (outs), (ins i32imm:$amt),
266 [(X86callseq_start imm:$amt)]>;
267 def ADJCALLSTACKUP : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
269 [(X86callseq_end imm:$amt1, imm:$amt2)]>;
271 let isImplicitDef = 1 in {
272 def IMPLICIT_DEF_GR8 : I<0, Pseudo, (outs GR8:$dst), (ins),
273 "#IMPLICIT_DEF $dst",
274 [(set GR8:$dst, (undef))]>;
275 def IMPLICIT_DEF_GR16 : I<0, Pseudo, (outs GR16:$dst), (ins),
276 "#IMPLICIT_DEF $dst",
277 [(set GR16:$dst, (undef))]>;
278 def IMPLICIT_DEF_GR32 : I<0, Pseudo, (outs GR32:$dst), (ins),
279 "#IMPLICIT_DEF $dst",
280 [(set GR32:$dst, (undef))]>;
284 let neverHasSideEffects = 1 in
285 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
288 let neverHasSideEffects = 1, isNotDuplicable = 1 in
289 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
290 "call\t$label\n\tpop{l}\t$reg", []>;
292 //===----------------------------------------------------------------------===//
293 // Control Flow Instructions...
296 // Return instructions.
297 let isTerminator = 1, isReturn = 1, isBarrier = 1,
299 def RET : I<0xC3, RawFrm, (outs), (ins), "ret", [(X86retflag 0)]>;
300 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), "ret\t$amt",
301 [(X86retflag imm:$amt)]>;
304 // All branches are RawFrm, Void, Branch, and Terminators
305 let isBranch = 1, isTerminator = 1 in
306 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
307 I<opcode, RawFrm, (outs), ins, asm, pattern>;
309 let isBranch = 1, isBarrier = 1 in
310 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
313 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
314 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
315 [(brind GR32:$dst)]>;
316 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
317 [(brind (loadi32 addr:$dst))]>;
320 // Conditional branches
321 let Uses = [EFLAGS] in {
322 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
323 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
324 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
325 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
326 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
327 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
328 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
329 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
330 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
331 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
332 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
333 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
335 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
336 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
337 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
338 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
339 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
340 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
341 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
342 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
344 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
345 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
346 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
347 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
348 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
349 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
350 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
351 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
352 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
353 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
354 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
355 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
358 //===----------------------------------------------------------------------===//
359 // Call Instructions...
362 // All calls clobber the non-callee saved registers...
363 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
364 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
365 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, EFLAGS] in {
366 def CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:$dst,variable_ops),
367 "call\t${dst:call}", []>;
368 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
369 "call\t{*}$dst", [(X86call GR32:$dst)]>;
370 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
371 "call\t{*}$dst", []>;
376 def TAILCALL : I<0, Pseudo, (outs), (ins ),
380 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
381 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset),
382 "#TC_RETURN $dst $offset",
385 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
386 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset),
387 "#TC_RETURN $dst $offset",
390 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
391 def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAILCALL",
393 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
394 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
396 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
397 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
398 "jmp\t{*}$dst # TAILCALL", []>;
400 //===----------------------------------------------------------------------===//
401 // Miscellaneous Instructions...
403 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
404 def LEAVE : I<0xC9, RawFrm,
405 (outs), (ins), "leave", []>;
407 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
409 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
412 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
415 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
416 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
417 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
418 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
420 let isTwoAddress = 1 in // GR32 = bswap GR32
421 def BSWAP32r : I<0xC8, AddRegFrm,
422 (outs GR32:$dst), (ins GR32:$src),
424 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
427 // Bit scan instructions.
428 let Defs = [EFLAGS] in {
429 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
430 "bsf{w}\t{$src, $dst|$dst, $src}",
431 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
432 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
433 "bsf{w}\t{$src, $dst|$dst, $src}",
434 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
435 (implicit EFLAGS)]>, TB;
436 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
437 "bsf{l}\t{$src, $dst|$dst, $src}",
438 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
439 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
440 "bsf{l}\t{$src, $dst|$dst, $src}",
441 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
442 (implicit EFLAGS)]>, TB;
444 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
445 "bsr{w}\t{$src, $dst|$dst, $src}",
446 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
447 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
448 "bsr{w}\t{$src, $dst|$dst, $src}",
449 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
450 (implicit EFLAGS)]>, TB;
451 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
452 "bsr{l}\t{$src, $dst|$dst, $src}",
453 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
454 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
455 "bsr{l}\t{$src, $dst|$dst, $src}",
456 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
457 (implicit EFLAGS)]>, TB;
460 let neverHasSideEffects = 1 in
461 def LEA16r : I<0x8D, MRMSrcMem,
462 (outs GR16:$dst), (ins i32mem:$src),
463 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
464 def LEA32r : I<0x8D, MRMSrcMem,
465 (outs GR32:$dst), (ins lea32mem:$src),
466 "lea{l}\t{$src|$dst}, {$dst|$src}",
467 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
469 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
470 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
471 [(X86rep_movs i8)]>, REP;
472 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
473 [(X86rep_movs i16)]>, REP, OpSize;
474 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
475 [(X86rep_movs i32)]>, REP;
478 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
479 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
480 [(X86rep_stos i8)]>, REP;
481 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
482 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
483 [(X86rep_stos i16)]>, REP, OpSize;
484 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
485 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
486 [(X86rep_stos i32)]>, REP;
488 let Defs = [RAX, RDX] in
489 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
492 let isBarrier = 1, hasCtrlDep = 1 in {
493 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
496 //===----------------------------------------------------------------------===//
497 // Input/Output Instructions...
499 let Defs = [AL], Uses = [DX] in
500 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
501 "in{b}\t{%dx, %al|%AL, %DX}", []>;
502 let Defs = [AX], Uses = [DX] in
503 def IN16rr : I<0xED, RawFrm, (outs), (ins),
504 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
505 let Defs = [EAX], Uses = [DX] in
506 def IN32rr : I<0xED, RawFrm, (outs), (ins),
507 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
510 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
511 "in{b}\t{$port, %al|%AL, $port}", []>;
513 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
514 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
516 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
517 "in{l}\t{$port, %eax|%EAX, $port}", []>;
519 let Uses = [DX, AL] in
520 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
521 "out{b}\t{%al, %dx|%DX, %AL}", []>;
522 let Uses = [DX, AX] in
523 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
524 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
525 let Uses = [DX, EAX] in
526 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
527 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
530 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
531 "out{b}\t{%al, $port|$port, %AL}", []>;
533 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
534 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
536 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
537 "out{l}\t{%eax, $port|$port, %EAX}", []>;
539 //===----------------------------------------------------------------------===//
540 // Move Instructions...
542 let neverHasSideEffects = 1 in {
543 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
544 "mov{b}\t{$src, $dst|$dst, $src}", []>;
545 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
546 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
547 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
548 "mov{l}\t{$src, $dst|$dst, $src}", []>;
550 let isReMaterializable = 1 in {
551 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
552 "mov{b}\t{$src, $dst|$dst, $src}",
553 [(set GR8:$dst, imm:$src)]>;
554 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
555 "mov{w}\t{$src, $dst|$dst, $src}",
556 [(set GR16:$dst, imm:$src)]>, OpSize;
557 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
558 "mov{l}\t{$src, $dst|$dst, $src}",
559 [(set GR32:$dst, imm:$src)]>;
561 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
562 "mov{b}\t{$src, $dst|$dst, $src}",
563 [(store (i8 imm:$src), addr:$dst)]>;
564 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
565 "mov{w}\t{$src, $dst|$dst, $src}",
566 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
567 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
568 "mov{l}\t{$src, $dst|$dst, $src}",
569 [(store (i32 imm:$src), addr:$dst)]>;
571 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
572 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
573 "mov{b}\t{$src, $dst|$dst, $src}",
574 [(set GR8:$dst, (load addr:$src))]>;
575 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
576 "mov{w}\t{$src, $dst|$dst, $src}",
577 [(set GR16:$dst, (load addr:$src))]>, OpSize;
578 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
579 "mov{l}\t{$src, $dst|$dst, $src}",
580 [(set GR32:$dst, (load addr:$src))]>;
583 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
584 "mov{b}\t{$src, $dst|$dst, $src}",
585 [(store GR8:$src, addr:$dst)]>;
586 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
587 "mov{w}\t{$src, $dst|$dst, $src}",
588 [(store GR16:$src, addr:$dst)]>, OpSize;
589 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
590 "mov{l}\t{$src, $dst|$dst, $src}",
591 [(store GR32:$src, addr:$dst)]>;
593 //===----------------------------------------------------------------------===//
594 // Fixed-Register Multiplication and Division Instructions...
597 // Extra precision multiplication
598 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
599 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
600 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
601 // This probably ought to be moved to a def : Pat<> if the
602 // syntax can be accepted.
603 [(set AL, (mul AL, GR8:$src))]>; // AL,AH = AL*GR8
604 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
605 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>,
606 OpSize; // AX,DX = AX*GR16
607 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
608 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l}\t$src", []>;
609 // EAX,EDX = EAX*GR32
610 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
611 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
613 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
614 // This probably ought to be moved to a def : Pat<> if the
615 // syntax can be accepted.
616 [(set AL, (mul AL, (loadi8 addr:$src)))]>; // AL,AH = AL*[mem8]
617 let mayLoad = 1, neverHasSideEffects = 1 in {
618 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
619 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
620 "mul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
621 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
622 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
623 "mul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
626 let neverHasSideEffects = 1 in {
627 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
628 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
630 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
631 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
632 OpSize; // AX,DX = AX*GR16
633 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
634 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
635 // EAX,EDX = EAX*GR32
637 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
638 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
639 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
640 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
641 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
642 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
643 let Defs = [EAX,EDX], Uses = [EAX] in
644 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
645 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
648 // unsigned division/remainder
649 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
650 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
652 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
653 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
654 "div{w}\t$src", []>, OpSize;
655 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
656 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
659 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
660 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
662 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
663 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
664 "div{w}\t$src", []>, OpSize;
665 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
666 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
670 // Signed division/remainder.
671 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
672 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
673 "idiv{b}\t$src", []>;
674 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
675 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
676 "idiv{w}\t$src", []>, OpSize;
677 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
678 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
679 "idiv{l}\t$src", []>;
680 let mayLoad = 1, mayLoad = 1 in {
681 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
682 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
683 "idiv{b}\t$src", []>;
684 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
685 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
686 "idiv{w}\t$src", []>, OpSize;
687 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
688 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
689 "idiv{l}\t$src", []>;
691 } // neverHasSideEffects
693 //===----------------------------------------------------------------------===//
694 // Two address Instructions.
696 let isTwoAddress = 1 in {
699 let Uses = [EFLAGS] in {
700 let isCommutable = 1 in {
701 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
702 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
703 "cmovb\t{$src2, $dst|$dst, $src2}",
704 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
705 X86_COND_B, EFLAGS))]>,
707 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
708 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
709 "cmovb\t{$src2, $dst|$dst, $src2}",
710 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
711 X86_COND_B, EFLAGS))]>,
714 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
715 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
716 "cmovae\t{$src2, $dst|$dst, $src2}",
717 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
718 X86_COND_AE, EFLAGS))]>,
720 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
721 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
722 "cmovae\t{$src2, $dst|$dst, $src2}",
723 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
724 X86_COND_AE, EFLAGS))]>,
726 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
727 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
728 "cmove\t{$src2, $dst|$dst, $src2}",
729 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
730 X86_COND_E, EFLAGS))]>,
732 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
733 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
734 "cmove\t{$src2, $dst|$dst, $src2}",
735 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
736 X86_COND_E, EFLAGS))]>,
738 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
739 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
740 "cmovne\t{$src2, $dst|$dst, $src2}",
741 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
742 X86_COND_NE, EFLAGS))]>,
744 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
745 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
746 "cmovne\t{$src2, $dst|$dst, $src2}",
747 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
748 X86_COND_NE, EFLAGS))]>,
750 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
751 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
752 "cmovbe\t{$src2, $dst|$dst, $src2}",
753 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
754 X86_COND_BE, EFLAGS))]>,
756 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
757 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
758 "cmovbe\t{$src2, $dst|$dst, $src2}",
759 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
760 X86_COND_BE, EFLAGS))]>,
762 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
763 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
764 "cmova\t{$src2, $dst|$dst, $src2}",
765 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
766 X86_COND_A, EFLAGS))]>,
768 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
769 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
770 "cmova\t{$src2, $dst|$dst, $src2}",
771 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
772 X86_COND_A, EFLAGS))]>,
774 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
775 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
776 "cmovl\t{$src2, $dst|$dst, $src2}",
777 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
778 X86_COND_L, EFLAGS))]>,
780 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
781 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
782 "cmovl\t{$src2, $dst|$dst, $src2}",
783 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
784 X86_COND_L, EFLAGS))]>,
786 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
787 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
788 "cmovge\t{$src2, $dst|$dst, $src2}",
789 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
790 X86_COND_GE, EFLAGS))]>,
792 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
793 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
794 "cmovge\t{$src2, $dst|$dst, $src2}",
795 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
796 X86_COND_GE, EFLAGS))]>,
798 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
799 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
800 "cmovle\t{$src2, $dst|$dst, $src2}",
801 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
802 X86_COND_LE, EFLAGS))]>,
804 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
805 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
806 "cmovle\t{$src2, $dst|$dst, $src2}",
807 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
808 X86_COND_LE, EFLAGS))]>,
810 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
811 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
812 "cmovg\t{$src2, $dst|$dst, $src2}",
813 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
814 X86_COND_G, EFLAGS))]>,
816 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
817 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
818 "cmovg\t{$src2, $dst|$dst, $src2}",
819 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
820 X86_COND_G, EFLAGS))]>,
822 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
823 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
824 "cmovs\t{$src2, $dst|$dst, $src2}",
825 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
826 X86_COND_S, EFLAGS))]>,
828 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
829 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
830 "cmovs\t{$src2, $dst|$dst, $src2}",
831 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
832 X86_COND_S, EFLAGS))]>,
834 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
835 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
836 "cmovns\t{$src2, $dst|$dst, $src2}",
837 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
838 X86_COND_NS, EFLAGS))]>,
840 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
841 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
842 "cmovns\t{$src2, $dst|$dst, $src2}",
843 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
844 X86_COND_NS, EFLAGS))]>,
846 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
847 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
848 "cmovp\t{$src2, $dst|$dst, $src2}",
849 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
850 X86_COND_P, EFLAGS))]>,
852 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
853 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
854 "cmovp\t{$src2, $dst|$dst, $src2}",
855 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
856 X86_COND_P, EFLAGS))]>,
858 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
859 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
860 "cmovnp\t{$src2, $dst|$dst, $src2}",
861 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
862 X86_COND_NP, EFLAGS))]>,
864 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
865 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
866 "cmovnp\t{$src2, $dst|$dst, $src2}",
867 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
868 X86_COND_NP, EFLAGS))]>,
870 } // isCommutable = 1
872 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
873 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
874 "cmovnp\t{$src2, $dst|$dst, $src2}",
875 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
876 X86_COND_NP, EFLAGS))]>,
879 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
880 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
881 "cmovb\t{$src2, $dst|$dst, $src2}",
882 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
883 X86_COND_B, EFLAGS))]>,
885 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
886 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
887 "cmovb\t{$src2, $dst|$dst, $src2}",
888 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
889 X86_COND_B, EFLAGS))]>,
891 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
892 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
893 "cmovae\t{$src2, $dst|$dst, $src2}",
894 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
895 X86_COND_AE, EFLAGS))]>,
897 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
898 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
899 "cmovae\t{$src2, $dst|$dst, $src2}",
900 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
901 X86_COND_AE, EFLAGS))]>,
903 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
904 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
905 "cmove\t{$src2, $dst|$dst, $src2}",
906 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
907 X86_COND_E, EFLAGS))]>,
909 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
910 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
911 "cmove\t{$src2, $dst|$dst, $src2}",
912 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
913 X86_COND_E, EFLAGS))]>,
915 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
916 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
917 "cmovne\t{$src2, $dst|$dst, $src2}",
918 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
919 X86_COND_NE, EFLAGS))]>,
921 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
922 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
923 "cmovne\t{$src2, $dst|$dst, $src2}",
924 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
925 X86_COND_NE, EFLAGS))]>,
927 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
928 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
929 "cmovbe\t{$src2, $dst|$dst, $src2}",
930 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
931 X86_COND_BE, EFLAGS))]>,
933 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
934 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
935 "cmovbe\t{$src2, $dst|$dst, $src2}",
936 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
937 X86_COND_BE, EFLAGS))]>,
939 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
940 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
941 "cmova\t{$src2, $dst|$dst, $src2}",
942 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
943 X86_COND_A, EFLAGS))]>,
945 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
946 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
947 "cmova\t{$src2, $dst|$dst, $src2}",
948 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
949 X86_COND_A, EFLAGS))]>,
951 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
952 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
953 "cmovl\t{$src2, $dst|$dst, $src2}",
954 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
955 X86_COND_L, EFLAGS))]>,
957 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
958 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
959 "cmovl\t{$src2, $dst|$dst, $src2}",
960 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
961 X86_COND_L, EFLAGS))]>,
963 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
964 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
965 "cmovge\t{$src2, $dst|$dst, $src2}",
966 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
967 X86_COND_GE, EFLAGS))]>,
969 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
970 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
971 "cmovge\t{$src2, $dst|$dst, $src2}",
972 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
973 X86_COND_GE, EFLAGS))]>,
975 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
976 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
977 "cmovle\t{$src2, $dst|$dst, $src2}",
978 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
979 X86_COND_LE, EFLAGS))]>,
981 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
982 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
983 "cmovle\t{$src2, $dst|$dst, $src2}",
984 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
985 X86_COND_LE, EFLAGS))]>,
987 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
988 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
989 "cmovg\t{$src2, $dst|$dst, $src2}",
990 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
991 X86_COND_G, EFLAGS))]>,
993 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
994 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
995 "cmovg\t{$src2, $dst|$dst, $src2}",
996 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
997 X86_COND_G, EFLAGS))]>,
999 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1000 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1001 "cmovs\t{$src2, $dst|$dst, $src2}",
1002 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1003 X86_COND_S, EFLAGS))]>,
1005 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1006 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1007 "cmovs\t{$src2, $dst|$dst, $src2}",
1008 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1009 X86_COND_S, EFLAGS))]>,
1011 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1012 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1013 "cmovns\t{$src2, $dst|$dst, $src2}",
1014 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1015 X86_COND_NS, EFLAGS))]>,
1017 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1018 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1019 "cmovns\t{$src2, $dst|$dst, $src2}",
1020 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1021 X86_COND_NS, EFLAGS))]>,
1023 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1024 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1025 "cmovp\t{$src2, $dst|$dst, $src2}",
1026 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1027 X86_COND_P, EFLAGS))]>,
1029 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1030 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1031 "cmovp\t{$src2, $dst|$dst, $src2}",
1032 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1033 X86_COND_P, EFLAGS))]>,
1035 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1036 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1037 "cmovnp\t{$src2, $dst|$dst, $src2}",
1038 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1039 X86_COND_NP, EFLAGS))]>,
1041 } // Uses = [EFLAGS]
1044 // unary instructions
1045 let CodeSize = 2 in {
1046 let Defs = [EFLAGS] in {
1047 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1048 [(set GR8:$dst, (ineg GR8:$src))]>;
1049 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1050 [(set GR16:$dst, (ineg GR16:$src))]>, OpSize;
1051 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1052 [(set GR32:$dst, (ineg GR32:$src))]>;
1053 let isTwoAddress = 0 in {
1054 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1055 [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
1056 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1057 [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1058 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1059 [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
1062 } // Defs = [EFLAGS]
1064 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1065 [(set GR8:$dst, (not GR8:$src))]>;
1066 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1067 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1068 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1069 [(set GR32:$dst, (not GR32:$src))]>;
1070 let isTwoAddress = 0 in {
1071 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1072 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1073 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1074 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1075 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1076 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1080 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1081 let Defs = [EFLAGS] in {
1083 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1084 [(set GR8:$dst, (add GR8:$src, 1))]>;
1085 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1086 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1087 [(set GR16:$dst, (add GR16:$src, 1))]>,
1088 OpSize, Requires<[In32BitMode]>;
1089 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1090 [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>;
1092 let isTwoAddress = 0, CodeSize = 2 in {
1093 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1094 [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
1095 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1096 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>,
1097 OpSize, Requires<[In32BitMode]>;
1098 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1099 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>,
1100 Requires<[In32BitMode]>;
1104 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1105 [(set GR8:$dst, (add GR8:$src, -1))]>;
1106 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1107 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1108 [(set GR16:$dst, (add GR16:$src, -1))]>,
1109 OpSize, Requires<[In32BitMode]>;
1110 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1111 [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>;
1114 let isTwoAddress = 0, CodeSize = 2 in {
1115 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1116 [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
1117 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1118 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>,
1119 OpSize, Requires<[In32BitMode]>;
1120 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1121 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>,
1122 Requires<[In32BitMode]>;
1124 } // Defs = [EFLAGS]
1126 // Logical operators...
1127 let Defs = [EFLAGS] in {
1128 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1129 def AND8rr : I<0x20, MRMDestReg,
1130 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1131 "and{b}\t{$src2, $dst|$dst, $src2}",
1132 [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>;
1133 def AND16rr : I<0x21, MRMDestReg,
1134 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1135 "and{w}\t{$src2, $dst|$dst, $src2}",
1136 [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize;
1137 def AND32rr : I<0x21, MRMDestReg,
1138 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1139 "and{l}\t{$src2, $dst|$dst, $src2}",
1140 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
1143 def AND8rm : I<0x22, MRMSrcMem,
1144 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1145 "and{b}\t{$src2, $dst|$dst, $src2}",
1146 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>;
1147 def AND16rm : I<0x23, MRMSrcMem,
1148 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1149 "and{w}\t{$src2, $dst|$dst, $src2}",
1150 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize;
1151 def AND32rm : I<0x23, MRMSrcMem,
1152 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1153 "and{l}\t{$src2, $dst|$dst, $src2}",
1154 [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>;
1156 def AND8ri : Ii8<0x80, MRM4r,
1157 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1158 "and{b}\t{$src2, $dst|$dst, $src2}",
1159 [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>;
1160 def AND16ri : Ii16<0x81, MRM4r,
1161 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1162 "and{w}\t{$src2, $dst|$dst, $src2}",
1163 [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize;
1164 def AND32ri : Ii32<0x81, MRM4r,
1165 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1166 "and{l}\t{$src2, $dst|$dst, $src2}",
1167 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
1168 def AND16ri8 : Ii8<0x83, MRM4r,
1169 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1170 "and{w}\t{$src2, $dst|$dst, $src2}",
1171 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>,
1173 def AND32ri8 : Ii8<0x83, MRM4r,
1174 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1175 "and{l}\t{$src2, $dst|$dst, $src2}",
1176 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>;
1178 let isTwoAddress = 0 in {
1179 def AND8mr : I<0x20, MRMDestMem,
1180 (outs), (ins i8mem :$dst, GR8 :$src),
1181 "and{b}\t{$src, $dst|$dst, $src}",
1182 [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>;
1183 def AND16mr : I<0x21, MRMDestMem,
1184 (outs), (ins i16mem:$dst, GR16:$src),
1185 "and{w}\t{$src, $dst|$dst, $src}",
1186 [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>,
1188 def AND32mr : I<0x21, MRMDestMem,
1189 (outs), (ins i32mem:$dst, GR32:$src),
1190 "and{l}\t{$src, $dst|$dst, $src}",
1191 [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>;
1192 def AND8mi : Ii8<0x80, MRM4m,
1193 (outs), (ins i8mem :$dst, i8imm :$src),
1194 "and{b}\t{$src, $dst|$dst, $src}",
1195 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1196 def AND16mi : Ii16<0x81, MRM4m,
1197 (outs), (ins i16mem:$dst, i16imm:$src),
1198 "and{w}\t{$src, $dst|$dst, $src}",
1199 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1201 def AND32mi : Ii32<0x81, MRM4m,
1202 (outs), (ins i32mem:$dst, i32imm:$src),
1203 "and{l}\t{$src, $dst|$dst, $src}",
1204 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1205 def AND16mi8 : Ii8<0x83, MRM4m,
1206 (outs), (ins i16mem:$dst, i16i8imm :$src),
1207 "and{w}\t{$src, $dst|$dst, $src}",
1208 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1210 def AND32mi8 : Ii8<0x83, MRM4m,
1211 (outs), (ins i32mem:$dst, i32i8imm :$src),
1212 "and{l}\t{$src, $dst|$dst, $src}",
1213 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1217 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1218 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1219 "or{b}\t{$src2, $dst|$dst, $src2}",
1220 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
1221 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1222 "or{w}\t{$src2, $dst|$dst, $src2}",
1223 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize;
1224 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1225 "or{l}\t{$src2, $dst|$dst, $src2}",
1226 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
1228 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1229 "or{b}\t{$src2, $dst|$dst, $src2}",
1230 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
1231 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1232 "or{w}\t{$src2, $dst|$dst, $src2}",
1233 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize;
1234 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1235 "or{l}\t{$src2, $dst|$dst, $src2}",
1236 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>;
1238 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1239 "or{b}\t{$src2, $dst|$dst, $src2}",
1240 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
1241 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1242 "or{w}\t{$src2, $dst|$dst, $src2}",
1243 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize;
1244 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1245 "or{l}\t{$src2, $dst|$dst, $src2}",
1246 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
1248 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1249 "or{w}\t{$src2, $dst|$dst, $src2}",
1250 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1251 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1252 "or{l}\t{$src2, $dst|$dst, $src2}",
1253 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>;
1254 let isTwoAddress = 0 in {
1255 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1256 "or{b}\t{$src, $dst|$dst, $src}",
1257 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
1258 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1259 "or{w}\t{$src, $dst|$dst, $src}",
1260 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize;
1261 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1262 "or{l}\t{$src, $dst|$dst, $src}",
1263 [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>;
1264 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1265 "or{b}\t{$src, $dst|$dst, $src}",
1266 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1267 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1268 "or{w}\t{$src, $dst|$dst, $src}",
1269 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1271 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1272 "or{l}\t{$src, $dst|$dst, $src}",
1273 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1274 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1275 "or{w}\t{$src, $dst|$dst, $src}",
1276 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1278 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1279 "or{l}\t{$src, $dst|$dst, $src}",
1280 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1284 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1285 def XOR8rr : I<0x30, MRMDestReg,
1286 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1287 "xor{b}\t{$src2, $dst|$dst, $src2}",
1288 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>;
1289 def XOR16rr : I<0x31, MRMDestReg,
1290 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1291 "xor{w}\t{$src2, $dst|$dst, $src2}",
1292 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize;
1293 def XOR32rr : I<0x31, MRMDestReg,
1294 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1295 "xor{l}\t{$src2, $dst|$dst, $src2}",
1296 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
1299 def XOR8rm : I<0x32, MRMSrcMem ,
1300 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1301 "xor{b}\t{$src2, $dst|$dst, $src2}",
1302 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>;
1303 def XOR16rm : I<0x33, MRMSrcMem ,
1304 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1305 "xor{w}\t{$src2, $dst|$dst, $src2}",
1306 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>, OpSize;
1307 def XOR32rm : I<0x33, MRMSrcMem ,
1308 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1309 "xor{l}\t{$src2, $dst|$dst, $src2}",
1310 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>;
1312 def XOR8ri : Ii8<0x80, MRM6r,
1313 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1314 "xor{b}\t{$src2, $dst|$dst, $src2}",
1315 [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>;
1316 def XOR16ri : Ii16<0x81, MRM6r,
1317 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1318 "xor{w}\t{$src2, $dst|$dst, $src2}",
1319 [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize;
1320 def XOR32ri : Ii32<0x81, MRM6r,
1321 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1322 "xor{l}\t{$src2, $dst|$dst, $src2}",
1323 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
1324 def XOR16ri8 : Ii8<0x83, MRM6r,
1325 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1326 "xor{w}\t{$src2, $dst|$dst, $src2}",
1327 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>,
1329 def XOR32ri8 : Ii8<0x83, MRM6r,
1330 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1331 "xor{l}\t{$src2, $dst|$dst, $src2}",
1332 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>;
1333 let isTwoAddress = 0 in {
1334 def XOR8mr : I<0x30, MRMDestMem,
1335 (outs), (ins i8mem :$dst, GR8 :$src),
1336 "xor{b}\t{$src, $dst|$dst, $src}",
1337 [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>;
1338 def XOR16mr : I<0x31, MRMDestMem,
1339 (outs), (ins i16mem:$dst, GR16:$src),
1340 "xor{w}\t{$src, $dst|$dst, $src}",
1341 [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>,
1343 def XOR32mr : I<0x31, MRMDestMem,
1344 (outs), (ins i32mem:$dst, GR32:$src),
1345 "xor{l}\t{$src, $dst|$dst, $src}",
1346 [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>;
1347 def XOR8mi : Ii8<0x80, MRM6m,
1348 (outs), (ins i8mem :$dst, i8imm :$src),
1349 "xor{b}\t{$src, $dst|$dst, $src}",
1350 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1351 def XOR16mi : Ii16<0x81, MRM6m,
1352 (outs), (ins i16mem:$dst, i16imm:$src),
1353 "xor{w}\t{$src, $dst|$dst, $src}",
1354 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1356 def XOR32mi : Ii32<0x81, MRM6m,
1357 (outs), (ins i32mem:$dst, i32imm:$src),
1358 "xor{l}\t{$src, $dst|$dst, $src}",
1359 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1360 def XOR16mi8 : Ii8<0x83, MRM6m,
1361 (outs), (ins i16mem:$dst, i16i8imm :$src),
1362 "xor{w}\t{$src, $dst|$dst, $src}",
1363 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1365 def XOR32mi8 : Ii8<0x83, MRM6m,
1366 (outs), (ins i32mem:$dst, i32i8imm :$src),
1367 "xor{l}\t{$src, $dst|$dst, $src}",
1368 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1370 } // Defs = [EFLAGS]
1372 // Shift instructions
1373 let Defs = [EFLAGS] in {
1374 let Uses = [CL] in {
1375 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1376 "shl{b}\t{%cl, $dst|$dst, %CL}",
1377 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1378 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1379 "shl{w}\t{%cl, $dst|$dst, %CL}",
1380 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1381 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1382 "shl{l}\t{%cl, $dst|$dst, %CL}",
1383 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1386 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1387 "shl{b}\t{$src2, $dst|$dst, $src2}",
1388 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1389 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1390 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1391 "shl{w}\t{$src2, $dst|$dst, $src2}",
1392 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1393 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1394 "shl{l}\t{$src2, $dst|$dst, $src2}",
1395 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1396 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1400 let isTwoAddress = 0 in {
1401 let Uses = [CL] in {
1402 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1403 "shl{b}\t{%cl, $dst|$dst, %CL}",
1404 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1405 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1406 "shl{w}\t{%cl, $dst|$dst, %CL}",
1407 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1408 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1409 "shl{l}\t{%cl, $dst|$dst, %CL}",
1410 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1412 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1413 "shl{b}\t{$src, $dst|$dst, $src}",
1414 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1415 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1416 "shl{w}\t{$src, $dst|$dst, $src}",
1417 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1419 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1420 "shl{l}\t{$src, $dst|$dst, $src}",
1421 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1424 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1426 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1427 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1429 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1431 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1433 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1436 let Uses = [CL] in {
1437 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1438 "shr{b}\t{%cl, $dst|$dst, %CL}",
1439 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1440 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1441 "shr{w}\t{%cl, $dst|$dst, %CL}",
1442 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1443 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1444 "shr{l}\t{%cl, $dst|$dst, %CL}",
1445 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1448 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1449 "shr{b}\t{$src2, $dst|$dst, $src2}",
1450 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1451 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1452 "shr{w}\t{$src2, $dst|$dst, $src2}",
1453 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1454 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1455 "shr{l}\t{$src2, $dst|$dst, $src2}",
1456 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1459 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1461 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1462 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1464 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1465 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1467 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1469 let isTwoAddress = 0 in {
1470 let Uses = [CL] in {
1471 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1472 "shr{b}\t{%cl, $dst|$dst, %CL}",
1473 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1474 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1475 "shr{w}\t{%cl, $dst|$dst, %CL}",
1476 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1478 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1479 "shr{l}\t{%cl, $dst|$dst, %CL}",
1480 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1482 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1483 "shr{b}\t{$src, $dst|$dst, $src}",
1484 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1485 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1486 "shr{w}\t{$src, $dst|$dst, $src}",
1487 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1489 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1490 "shr{l}\t{$src, $dst|$dst, $src}",
1491 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1494 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1496 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1497 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1499 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1500 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1502 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1505 let Uses = [CL] in {
1506 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1507 "sar{b}\t{%cl, $dst|$dst, %CL}",
1508 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1509 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1510 "sar{w}\t{%cl, $dst|$dst, %CL}",
1511 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1512 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1513 "sar{l}\t{%cl, $dst|$dst, %CL}",
1514 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1517 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1518 "sar{b}\t{$src2, $dst|$dst, $src2}",
1519 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1520 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1521 "sar{w}\t{$src2, $dst|$dst, $src2}",
1522 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1524 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1525 "sar{l}\t{$src2, $dst|$dst, $src2}",
1526 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1529 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1531 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1532 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1534 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1535 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1537 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1539 let isTwoAddress = 0 in {
1540 let Uses = [CL] in {
1541 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1542 "sar{b}\t{%cl, $dst|$dst, %CL}",
1543 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
1544 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1545 "sar{w}\t{%cl, $dst|$dst, %CL}",
1546 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1547 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1548 "sar{l}\t{%cl, $dst|$dst, %CL}",
1549 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1551 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1552 "sar{b}\t{$src, $dst|$dst, $src}",
1553 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1554 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1555 "sar{w}\t{$src, $dst|$dst, $src}",
1556 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1558 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1559 "sar{l}\t{$src, $dst|$dst, $src}",
1560 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1563 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1565 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1566 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1568 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1570 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
1572 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1575 // Rotate instructions
1576 // FIXME: provide shorter instructions when imm8 == 1
1577 let Uses = [CL] in {
1578 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
1579 "rol{b}\t{%cl, $dst|$dst, %CL}",
1580 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
1581 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
1582 "rol{w}\t{%cl, $dst|$dst, %CL}",
1583 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
1584 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
1585 "rol{l}\t{%cl, $dst|$dst, %CL}",
1586 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
1589 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1590 "rol{b}\t{$src2, $dst|$dst, $src2}",
1591 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1592 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1593 "rol{w}\t{$src2, $dst|$dst, $src2}",
1594 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1595 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1596 "rol{l}\t{$src2, $dst|$dst, $src2}",
1597 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1600 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1602 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1603 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
1605 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1606 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1608 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1610 let isTwoAddress = 0 in {
1611 let Uses = [CL] in {
1612 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
1613 "rol{b}\t{%cl, $dst|$dst, %CL}",
1614 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
1615 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
1616 "rol{w}\t{%cl, $dst|$dst, %CL}",
1617 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1618 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
1619 "rol{l}\t{%cl, $dst|$dst, %CL}",
1620 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
1622 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
1623 "rol{b}\t{$src, $dst|$dst, $src}",
1624 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1625 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
1626 "rol{w}\t{$src, $dst|$dst, $src}",
1627 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1629 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
1630 "rol{l}\t{$src, $dst|$dst, $src}",
1631 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1634 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
1636 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1637 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
1639 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1641 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
1643 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1646 let Uses = [CL] in {
1647 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
1648 "ror{b}\t{%cl, $dst|$dst, %CL}",
1649 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
1650 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
1651 "ror{w}\t{%cl, $dst|$dst, %CL}",
1652 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
1653 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
1654 "ror{l}\t{%cl, $dst|$dst, %CL}",
1655 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
1658 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1659 "ror{b}\t{$src2, $dst|$dst, $src2}",
1660 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
1661 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1662 "ror{w}\t{$src2, $dst|$dst, $src2}",
1663 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1664 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1665 "ror{l}\t{$src2, $dst|$dst, $src2}",
1666 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
1669 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1671 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
1672 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
1674 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
1675 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
1677 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
1679 let isTwoAddress = 0 in {
1680 let Uses = [CL] in {
1681 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
1682 "ror{b}\t{%cl, $dst|$dst, %CL}",
1683 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
1684 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
1685 "ror{w}\t{%cl, $dst|$dst, %CL}",
1686 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1687 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
1688 "ror{l}\t{%cl, $dst|$dst, %CL}",
1689 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
1691 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1692 "ror{b}\t{$src, $dst|$dst, $src}",
1693 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1694 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
1695 "ror{w}\t{$src, $dst|$dst, $src}",
1696 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1698 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
1699 "ror{l}\t{$src, $dst|$dst, $src}",
1700 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1703 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
1705 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1706 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
1708 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1710 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
1712 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1717 // Double shift instructions (generalizations of rotate)
1718 let Uses = [CL] in {
1719 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1720 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1721 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
1722 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1723 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1724 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
1725 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1726 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1727 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
1729 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1730 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1731 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
1735 let isCommutable = 1 in { // These instructions commute to each other.
1736 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
1737 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1738 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1739 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
1742 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
1743 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1744 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1745 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
1748 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
1749 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1750 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1751 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
1754 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
1755 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1756 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1757 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
1762 let isTwoAddress = 0 in {
1763 let Uses = [CL] in {
1764 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1765 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1766 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
1768 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1769 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1770 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
1773 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
1774 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1775 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1776 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
1777 (i8 imm:$src3)), addr:$dst)]>,
1779 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
1780 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1781 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1782 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
1783 (i8 imm:$src3)), addr:$dst)]>,
1786 let Uses = [CL] in {
1787 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1788 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1789 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
1790 addr:$dst)]>, TB, OpSize;
1791 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1792 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1793 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
1794 addr:$dst)]>, TB, OpSize;
1796 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
1797 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1798 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1799 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
1800 (i8 imm:$src3)), addr:$dst)]>,
1802 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
1803 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1804 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1805 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
1806 (i8 imm:$src3)), addr:$dst)]>,
1809 } // Defs = [EFLAGS]
1813 let Defs = [EFLAGS] in {
1814 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1815 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
1816 (ins GR8 :$src1, GR8 :$src2),
1817 "add{b}\t{$src2, $dst|$dst, $src2}",
1818 [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>;
1819 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1820 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
1821 (ins GR16:$src1, GR16:$src2),
1822 "add{w}\t{$src2, $dst|$dst, $src2}",
1823 [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize;
1824 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
1825 (ins GR32:$src1, GR32:$src2),
1826 "add{l}\t{$src2, $dst|$dst, $src2}",
1827 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
1828 } // end isConvertibleToThreeAddress
1829 } // end isCommutable
1830 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
1831 (ins GR8 :$src1, i8mem :$src2),
1832 "add{b}\t{$src2, $dst|$dst, $src2}",
1833 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>;
1834 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
1835 (ins GR16:$src1, i16mem:$src2),
1836 "add{w}\t{$src2, $dst|$dst, $src2}",
1837 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>,OpSize;
1838 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
1839 (ins GR32:$src1, i32mem:$src2),
1840 "add{l}\t{$src2, $dst|$dst, $src2}",
1841 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>;
1843 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1844 "add{b}\t{$src2, $dst|$dst, $src2}",
1845 [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>;
1847 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1848 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
1849 (ins GR16:$src1, i16imm:$src2),
1850 "add{w}\t{$src2, $dst|$dst, $src2}",
1851 [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize;
1852 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
1853 (ins GR32:$src1, i32imm:$src2),
1854 "add{l}\t{$src2, $dst|$dst, $src2}",
1855 [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>;
1856 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
1857 (ins GR16:$src1, i16i8imm:$src2),
1858 "add{w}\t{$src2, $dst|$dst, $src2}",
1859 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1860 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
1861 (ins GR32:$src1, i32i8imm:$src2),
1862 "add{l}\t{$src2, $dst|$dst, $src2}",
1863 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>;
1866 let isTwoAddress = 0 in {
1867 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1868 "add{b}\t{$src2, $dst|$dst, $src2}",
1869 [(store (add (load addr:$dst), GR8:$src2), addr:$dst)]>;
1870 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1871 "add{w}\t{$src2, $dst|$dst, $src2}",
1872 [(store (add (load addr:$dst), GR16:$src2), addr:$dst)]>,
1874 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1875 "add{l}\t{$src2, $dst|$dst, $src2}",
1876 [(store (add (load addr:$dst), GR32:$src2), addr:$dst)]>;
1877 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
1878 "add{b}\t{$src2, $dst|$dst, $src2}",
1879 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1880 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
1881 "add{w}\t{$src2, $dst|$dst, $src2}",
1882 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1884 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
1885 "add{l}\t{$src2, $dst|$dst, $src2}",
1886 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1887 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1888 "add{w}\t{$src2, $dst|$dst, $src2}",
1889 [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1891 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1892 "add{l}\t{$src2, $dst|$dst, $src2}",
1893 [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1896 let Uses = [EFLAGS] in {
1897 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1898 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1899 "adc{l}\t{$src2, $dst|$dst, $src2}",
1900 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
1902 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1903 "adc{l}\t{$src2, $dst|$dst, $src2}",
1904 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
1905 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1906 "adc{l}\t{$src2, $dst|$dst, $src2}",
1907 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
1908 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1909 "adc{l}\t{$src2, $dst|$dst, $src2}",
1910 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
1912 let isTwoAddress = 0 in {
1913 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1914 "adc{l}\t{$src2, $dst|$dst, $src2}",
1915 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
1916 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
1917 "adc{l}\t{$src2, $dst|$dst, $src2}",
1918 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1919 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1920 "adc{l}\t{$src2, $dst|$dst, $src2}",
1921 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1923 } // Uses = [EFLAGS]
1925 def SUB8rr : I<0x28, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1926 "sub{b}\t{$src2, $dst|$dst, $src2}",
1927 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2))]>;
1928 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1929 "sub{w}\t{$src2, $dst|$dst, $src2}",
1930 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2))]>, OpSize;
1931 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1932 "sub{l}\t{$src2, $dst|$dst, $src2}",
1933 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
1934 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1935 "sub{b}\t{$src2, $dst|$dst, $src2}",
1936 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2)))]>;
1937 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1938 "sub{w}\t{$src2, $dst|$dst, $src2}",
1939 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2)))]>, OpSize;
1940 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1941 "sub{l}\t{$src2, $dst|$dst, $src2}",
1942 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2)))]>;
1944 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1945 "sub{b}\t{$src2, $dst|$dst, $src2}",
1946 [(set GR8:$dst, (sub GR8:$src1, imm:$src2))]>;
1947 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1948 "sub{w}\t{$src2, $dst|$dst, $src2}",
1949 [(set GR16:$dst, (sub GR16:$src1, imm:$src2))]>, OpSize;
1950 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1951 "sub{l}\t{$src2, $dst|$dst, $src2}",
1952 [(set GR32:$dst, (sub GR32:$src1, imm:$src2))]>;
1953 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1954 "sub{w}\t{$src2, $dst|$dst, $src2}",
1955 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2))]>,
1957 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1958 "sub{l}\t{$src2, $dst|$dst, $src2}",
1959 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2))]>;
1960 let isTwoAddress = 0 in {
1961 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1962 "sub{b}\t{$src2, $dst|$dst, $src2}",
1963 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst)]>;
1964 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1965 "sub{w}\t{$src2, $dst|$dst, $src2}",
1966 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst)]>,
1968 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1969 "sub{l}\t{$src2, $dst|$dst, $src2}",
1970 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst)]>;
1971 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
1972 "sub{b}\t{$src2, $dst|$dst, $src2}",
1973 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1974 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
1975 "sub{w}\t{$src2, $dst|$dst, $src2}",
1976 [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1978 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
1979 "sub{l}\t{$src2, $dst|$dst, $src2}",
1980 [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1981 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1982 "sub{w}\t{$src2, $dst|$dst, $src2}",
1983 [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1985 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1986 "sub{l}\t{$src2, $dst|$dst, $src2}",
1987 [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1990 let Uses = [EFLAGS] in {
1991 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1992 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1993 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
1995 let isTwoAddress = 0 in {
1996 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1997 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1998 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
1999 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2000 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2001 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2002 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2003 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2004 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2005 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2006 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2007 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2009 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2010 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2011 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2012 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2013 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2014 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2015 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2016 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2017 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2018 } // Uses = [EFLAGS]
2019 } // Defs = [EFLAGS]
2021 let Defs = [EFLAGS] in {
2022 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2023 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2024 "imul{w}\t{$src2, $dst|$dst, $src2}",
2025 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2))]>, TB, OpSize;
2026 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2027 "imul{l}\t{$src2, $dst|$dst, $src2}",
2028 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>, TB;
2030 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2031 "imul{w}\t{$src2, $dst|$dst, $src2}",
2032 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2)))]>,
2034 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2035 "imul{l}\t{$src2, $dst|$dst, $src2}",
2036 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2)))]>, TB;
2037 } // Defs = [EFLAGS]
2038 } // end Two Address instructions
2040 // Suprisingly enough, these are not two address instructions!
2041 let Defs = [EFLAGS] in {
2042 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2043 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2044 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2045 [(set GR16:$dst, (mul GR16:$src1, imm:$src2))]>, OpSize;
2046 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2047 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2048 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2049 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
2050 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2051 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2052 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2053 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2))]>,
2055 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2056 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2057 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2058 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2))]>;
2060 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2061 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2062 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2063 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2))]>,
2065 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2066 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2067 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2068 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2))]>;
2069 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2070 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2071 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2072 [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>,
2074 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2075 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2076 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2077 [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>;
2078 } // Defs = [EFLAGS]
2080 //===----------------------------------------------------------------------===//
2081 // Test instructions are just like AND, except they don't generate a result.
2083 let Defs = [EFLAGS] in {
2084 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2085 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2086 "test{b}\t{$src2, $src1|$src1, $src2}",
2087 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
2088 (implicit EFLAGS)]>;
2089 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2090 "test{w}\t{$src2, $src1|$src1, $src2}",
2091 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
2092 (implicit EFLAGS)]>,
2094 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2095 "test{l}\t{$src2, $src1|$src1, $src2}",
2096 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
2097 (implicit EFLAGS)]>;
2100 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2101 "test{b}\t{$src2, $src1|$src1, $src2}",
2102 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2103 (implicit EFLAGS)]>;
2104 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2105 "test{w}\t{$src2, $src1|$src1, $src2}",
2106 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2107 (implicit EFLAGS)]>, OpSize;
2108 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2109 "test{l}\t{$src2, $src1|$src1, $src2}",
2110 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2111 (implicit EFLAGS)]>;
2113 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2114 (outs), (ins GR8:$src1, i8imm:$src2),
2115 "test{b}\t{$src2, $src1|$src1, $src2}",
2116 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
2117 (implicit EFLAGS)]>;
2118 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2119 (outs), (ins GR16:$src1, i16imm:$src2),
2120 "test{w}\t{$src2, $src1|$src1, $src2}",
2121 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
2122 (implicit EFLAGS)]>, OpSize;
2123 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2124 (outs), (ins GR32:$src1, i32imm:$src2),
2125 "test{l}\t{$src2, $src1|$src1, $src2}",
2126 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
2127 (implicit EFLAGS)]>;
2129 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2130 (outs), (ins i8mem:$src1, i8imm:$src2),
2131 "test{b}\t{$src2, $src1|$src1, $src2}",
2132 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2133 (implicit EFLAGS)]>;
2134 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2135 (outs), (ins i16mem:$src1, i16imm:$src2),
2136 "test{w}\t{$src2, $src1|$src1, $src2}",
2137 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2138 (implicit EFLAGS)]>, OpSize;
2139 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2140 (outs), (ins i32mem:$src1, i32imm:$src2),
2141 "test{l}\t{$src2, $src1|$src1, $src2}",
2142 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2143 (implicit EFLAGS)]>;
2144 } // Defs = [EFLAGS]
2147 // Condition code ops, incl. set if equal/not equal/...
2148 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2149 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2150 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2151 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2153 let Uses = [EFLAGS] in {
2154 def SETEr : I<0x94, MRM0r,
2155 (outs GR8 :$dst), (ins),
2157 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2159 def SETEm : I<0x94, MRM0m,
2160 (outs), (ins i8mem:$dst),
2162 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2164 def SETNEr : I<0x95, MRM0r,
2165 (outs GR8 :$dst), (ins),
2167 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2169 def SETNEm : I<0x95, MRM0m,
2170 (outs), (ins i8mem:$dst),
2172 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2174 def SETLr : I<0x9C, MRM0r,
2175 (outs GR8 :$dst), (ins),
2177 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2178 TB; // GR8 = < signed
2179 def SETLm : I<0x9C, MRM0m,
2180 (outs), (ins i8mem:$dst),
2182 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2183 TB; // [mem8] = < signed
2184 def SETGEr : I<0x9D, MRM0r,
2185 (outs GR8 :$dst), (ins),
2187 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2188 TB; // GR8 = >= signed
2189 def SETGEm : I<0x9D, MRM0m,
2190 (outs), (ins i8mem:$dst),
2192 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2193 TB; // [mem8] = >= signed
2194 def SETLEr : I<0x9E, MRM0r,
2195 (outs GR8 :$dst), (ins),
2197 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2198 TB; // GR8 = <= signed
2199 def SETLEm : I<0x9E, MRM0m,
2200 (outs), (ins i8mem:$dst),
2202 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2203 TB; // [mem8] = <= signed
2204 def SETGr : I<0x9F, MRM0r,
2205 (outs GR8 :$dst), (ins),
2207 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2208 TB; // GR8 = > signed
2209 def SETGm : I<0x9F, MRM0m,
2210 (outs), (ins i8mem:$dst),
2212 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2213 TB; // [mem8] = > signed
2215 def SETBr : I<0x92, MRM0r,
2216 (outs GR8 :$dst), (ins),
2218 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2219 TB; // GR8 = < unsign
2220 def SETBm : I<0x92, MRM0m,
2221 (outs), (ins i8mem:$dst),
2223 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
2224 TB; // [mem8] = < unsign
2225 def SETAEr : I<0x93, MRM0r,
2226 (outs GR8 :$dst), (ins),
2228 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
2229 TB; // GR8 = >= unsign
2230 def SETAEm : I<0x93, MRM0m,
2231 (outs), (ins i8mem:$dst),
2233 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
2234 TB; // [mem8] = >= unsign
2235 def SETBEr : I<0x96, MRM0r,
2236 (outs GR8 :$dst), (ins),
2238 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
2239 TB; // GR8 = <= unsign
2240 def SETBEm : I<0x96, MRM0m,
2241 (outs), (ins i8mem:$dst),
2243 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
2244 TB; // [mem8] = <= unsign
2245 def SETAr : I<0x97, MRM0r,
2246 (outs GR8 :$dst), (ins),
2248 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
2249 TB; // GR8 = > signed
2250 def SETAm : I<0x97, MRM0m,
2251 (outs), (ins i8mem:$dst),
2253 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
2254 TB; // [mem8] = > signed
2256 def SETSr : I<0x98, MRM0r,
2257 (outs GR8 :$dst), (ins),
2259 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
2260 TB; // GR8 = <sign bit>
2261 def SETSm : I<0x98, MRM0m,
2262 (outs), (ins i8mem:$dst),
2264 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
2265 TB; // [mem8] = <sign bit>
2266 def SETNSr : I<0x99, MRM0r,
2267 (outs GR8 :$dst), (ins),
2269 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
2270 TB; // GR8 = !<sign bit>
2271 def SETNSm : I<0x99, MRM0m,
2272 (outs), (ins i8mem:$dst),
2274 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
2275 TB; // [mem8] = !<sign bit>
2276 def SETPr : I<0x9A, MRM0r,
2277 (outs GR8 :$dst), (ins),
2279 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
2281 def SETPm : I<0x9A, MRM0m,
2282 (outs), (ins i8mem:$dst),
2284 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
2285 TB; // [mem8] = parity
2286 def SETNPr : I<0x9B, MRM0r,
2287 (outs GR8 :$dst), (ins),
2289 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
2290 TB; // GR8 = not parity
2291 def SETNPm : I<0x9B, MRM0m,
2292 (outs), (ins i8mem:$dst),
2294 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
2295 TB; // [mem8] = not parity
2296 } // Uses = [EFLAGS]
2299 // Integer comparisons
2300 let Defs = [EFLAGS] in {
2301 def CMP8rr : I<0x38, MRMDestReg,
2302 (outs), (ins GR8 :$src1, GR8 :$src2),
2303 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2304 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2305 def CMP16rr : I<0x39, MRMDestReg,
2306 (outs), (ins GR16:$src1, GR16:$src2),
2307 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2308 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
2309 def CMP32rr : I<0x39, MRMDestReg,
2310 (outs), (ins GR32:$src1, GR32:$src2),
2311 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2312 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
2313 def CMP8mr : I<0x38, MRMDestMem,
2314 (outs), (ins i8mem :$src1, GR8 :$src2),
2315 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2316 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
2317 (implicit EFLAGS)]>;
2318 def CMP16mr : I<0x39, MRMDestMem,
2319 (outs), (ins i16mem:$src1, GR16:$src2),
2320 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2321 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
2322 (implicit EFLAGS)]>, OpSize;
2323 def CMP32mr : I<0x39, MRMDestMem,
2324 (outs), (ins i32mem:$src1, GR32:$src2),
2325 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2326 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
2327 (implicit EFLAGS)]>;
2328 def CMP8rm : I<0x3A, MRMSrcMem,
2329 (outs), (ins GR8 :$src1, i8mem :$src2),
2330 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2331 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
2332 (implicit EFLAGS)]>;
2333 def CMP16rm : I<0x3B, MRMSrcMem,
2334 (outs), (ins GR16:$src1, i16mem:$src2),
2335 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2336 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
2337 (implicit EFLAGS)]>, OpSize;
2338 def CMP32rm : I<0x3B, MRMSrcMem,
2339 (outs), (ins GR32:$src1, i32mem:$src2),
2340 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2341 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
2342 (implicit EFLAGS)]>;
2343 def CMP8ri : Ii8<0x80, MRM7r,
2344 (outs), (ins GR8:$src1, i8imm:$src2),
2345 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2346 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
2347 def CMP16ri : Ii16<0x81, MRM7r,
2348 (outs), (ins GR16:$src1, i16imm:$src2),
2349 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2350 [(X86cmp GR16:$src1, imm:$src2),
2351 (implicit EFLAGS)]>, OpSize;
2352 def CMP32ri : Ii32<0x81, MRM7r,
2353 (outs), (ins GR32:$src1, i32imm:$src2),
2354 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2355 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
2356 def CMP8mi : Ii8 <0x80, MRM7m,
2357 (outs), (ins i8mem :$src1, i8imm :$src2),
2358 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2359 [(X86cmp (loadi8 addr:$src1), imm:$src2),
2360 (implicit EFLAGS)]>;
2361 def CMP16mi : Ii16<0x81, MRM7m,
2362 (outs), (ins i16mem:$src1, i16imm:$src2),
2363 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2364 [(X86cmp (loadi16 addr:$src1), imm:$src2),
2365 (implicit EFLAGS)]>, OpSize;
2366 def CMP32mi : Ii32<0x81, MRM7m,
2367 (outs), (ins i32mem:$src1, i32imm:$src2),
2368 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2369 [(X86cmp (loadi32 addr:$src1), imm:$src2),
2370 (implicit EFLAGS)]>;
2371 def CMP16ri8 : Ii8<0x83, MRM7r,
2372 (outs), (ins GR16:$src1, i16i8imm:$src2),
2373 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2374 [(X86cmp GR16:$src1, i16immSExt8:$src2),
2375 (implicit EFLAGS)]>, OpSize;
2376 def CMP16mi8 : Ii8<0x83, MRM7m,
2377 (outs), (ins i16mem:$src1, i16i8imm:$src2),
2378 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2379 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
2380 (implicit EFLAGS)]>, OpSize;
2381 def CMP32mi8 : Ii8<0x83, MRM7m,
2382 (outs), (ins i32mem:$src1, i32i8imm:$src2),
2383 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2384 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
2385 (implicit EFLAGS)]>;
2386 def CMP32ri8 : Ii8<0x83, MRM7r,
2387 (outs), (ins GR32:$src1, i32i8imm:$src2),
2388 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2389 [(X86cmp GR32:$src1, i32immSExt8:$src2),
2390 (implicit EFLAGS)]>;
2391 } // Defs = [EFLAGS]
2393 // Sign/Zero extenders
2394 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2395 "movs{bw|x}\t{$src, $dst|$dst, $src}",
2396 [(set GR16:$dst, (sext GR8:$src))]>, TB, OpSize;
2397 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2398 "movs{bw|x}\t{$src, $dst|$dst, $src}",
2399 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize;
2400 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2401 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2402 [(set GR32:$dst, (sext GR8:$src))]>, TB;
2403 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2404 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2405 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
2406 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2407 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2408 [(set GR32:$dst, (sext GR16:$src))]>, TB;
2409 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2410 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2411 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
2413 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2414 "movz{bw|x}\t{$src, $dst|$dst, $src}",
2415 [(set GR16:$dst, (zext GR8:$src))]>, TB, OpSize;
2416 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2417 "movz{bw|x}\t{$src, $dst|$dst, $src}",
2418 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize;
2419 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2420 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2421 [(set GR32:$dst, (zext GR8:$src))]>, TB;
2422 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2423 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2424 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
2425 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2426 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2427 [(set GR32:$dst, (zext GR16:$src))]>, TB;
2428 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2429 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2430 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
2432 let neverHasSideEffects = 1 in {
2433 let Defs = [AX], Uses = [AL] in
2434 def CBW : I<0x98, RawFrm, (outs), (ins),
2435 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
2436 let Defs = [EAX], Uses = [AX] in
2437 def CWDE : I<0x98, RawFrm, (outs), (ins),
2438 "{cwtl|cwde}", []>; // EAX = signext(AX)
2440 let Defs = [AX,DX], Uses = [AX] in
2441 def CWD : I<0x99, RawFrm, (outs), (ins),
2442 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
2443 let Defs = [EAX,EDX], Uses = [EAX] in
2444 def CDQ : I<0x99, RawFrm, (outs), (ins),
2445 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
2448 //===----------------------------------------------------------------------===//
2449 // Alias Instructions
2450 //===----------------------------------------------------------------------===//
2452 // Alias instructions that map movr0 to xor.
2453 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2454 let Defs = [EFLAGS], isReMaterializable = 1 in {
2455 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
2456 "xor{b}\t$dst, $dst",
2457 [(set GR8:$dst, 0)]>;
2458 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
2459 "xor{w}\t$dst, $dst",
2460 [(set GR16:$dst, 0)]>, OpSize;
2461 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
2462 "xor{l}\t$dst, $dst",
2463 [(set GR32:$dst, 0)]>;
2466 // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
2467 // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
2468 let neverHasSideEffects = 1 in {
2469 def MOV16to16_ : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16:$src),
2470 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2471 def MOV32to32_ : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32:$src),
2472 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2474 def MOV16_rr : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16_:$src),
2475 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2476 def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src),
2477 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2478 } // neverHasSideEffects
2480 let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
2481 def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src),
2482 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2483 def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src),
2484 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2486 let mayStore = 1, neverHasSideEffects = 1 in {
2487 def MOV16_mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16_:$src),
2488 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2489 def MOV32_mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32_:$src),
2490 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2493 //===----------------------------------------------------------------------===//
2494 // Thread Local Storage Instructions
2498 def TLS_addr : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
2499 "leal\t${sym:mem}(,%ebx,1), $dst",
2500 [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
2502 let AddedComplexity = 10 in
2503 def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
2504 "movl\t%gs:($src), $dst",
2505 [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
2507 let AddedComplexity = 15 in
2508 def TLS_gs_ri : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
2509 "movl\t%gs:${src:mem}, $dst",
2511 (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>;
2513 def TLS_tp : I<0, Pseudo, (outs GR32:$dst), (ins),
2514 "movl\t%gs:0, $dst",
2515 [(set GR32:$dst, X86TLStp)]>;
2517 //===----------------------------------------------------------------------===//
2518 // DWARF Pseudo Instructions
2521 def DWARF_LOC : I<0, Pseudo, (outs),
2522 (ins i32imm:$line, i32imm:$col, i32imm:$file),
2523 ".loc\t${file:debug} ${line:debug} ${col:debug}",
2524 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
2527 //===----------------------------------------------------------------------===//
2528 // EH Pseudo Instructions
2530 let isTerminator = 1, isReturn = 1, isBarrier = 1,
2532 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
2533 "ret\t#eh_return, addr: $addr",
2534 [(X86ehret GR32:$addr)]>;
2538 //===----------------------------------------------------------------------===//
2542 def LCMPXCHGL : I<0, Pseudo, (outs GR32:$dst),
2543 (ins GR32:$ptr, GR32:$cmp, GR32:$swap),
2544 "movl $cmp, %eax ; lock cmpxchgl $swap,($ptr) ; movl %eax, $dst",
2545 [(set GR32:$dst, (atomic_lcs_32 GR32:$ptr, GR32:$cmp, GR32:$swap))]>;
2547 //===----------------------------------------------------------------------===//
2548 // Non-Instruction Patterns
2549 //===----------------------------------------------------------------------===//
2551 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
2552 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
2553 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
2554 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)), (MOV32ri tglobaltlsaddr:$dst)>;
2555 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
2556 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
2558 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
2559 (ADD32ri GR32:$src1, tconstpool:$src2)>;
2560 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
2561 (ADD32ri GR32:$src1, tjumptable:$src2)>;
2562 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
2563 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
2564 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
2565 (ADD32ri GR32:$src1, texternalsym:$src2)>;
2567 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
2568 (MOV32mi addr:$dst, tglobaladdr:$src)>;
2569 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
2570 (MOV32mi addr:$dst, texternalsym:$src)>;
2574 def : Pat<(X86tailcall GR32:$dst),
2577 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
2579 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
2582 def : Pat<(X86tcret GR32:$dst, imm:$off),
2583 (TCRETURNri GR32:$dst, imm:$off)>;
2585 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
2586 (TCRETURNdi texternalsym:$dst, imm:$off)>;
2588 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
2589 (TCRETURNdi texternalsym:$dst, imm:$off)>;
2591 def : Pat<(X86call (i32 tglobaladdr:$dst)),
2592 (CALLpcrel32 tglobaladdr:$dst)>;
2593 def : Pat<(X86call (i32 texternalsym:$dst)),
2594 (CALLpcrel32 texternalsym:$dst)>;
2596 // X86 specific add which produces a flag.
2597 def : Pat<(addc GR32:$src1, GR32:$src2),
2598 (ADD32rr GR32:$src1, GR32:$src2)>;
2599 def : Pat<(addc GR32:$src1, (load addr:$src2)),
2600 (ADD32rm GR32:$src1, addr:$src2)>;
2601 def : Pat<(addc GR32:$src1, imm:$src2),
2602 (ADD32ri GR32:$src1, imm:$src2)>;
2603 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
2604 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
2606 def : Pat<(subc GR32:$src1, GR32:$src2),
2607 (SUB32rr GR32:$src1, GR32:$src2)>;
2608 def : Pat<(subc GR32:$src1, (load addr:$src2)),
2609 (SUB32rm GR32:$src1, addr:$src2)>;
2610 def : Pat<(subc GR32:$src1, imm:$src2),
2611 (SUB32ri GR32:$src1, imm:$src2)>;
2612 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
2613 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
2617 // TEST R,R is smaller than CMP R,0
2618 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
2619 (TEST8rr GR8:$src1, GR8:$src1)>;
2620 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
2621 (TEST16rr GR16:$src1, GR16:$src1)>;
2622 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
2623 (TEST32rr GR32:$src1, GR32:$src1)>;
2625 // zextload bool -> zextload byte
2626 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2627 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2628 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2630 // extload bool -> extload byte
2631 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2632 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2633 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2634 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
2635 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
2636 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
2639 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
2640 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
2641 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
2642 def : Pat<(i16 (anyext (loadi8 addr:$src))), (MOVZX16rm8 addr:$src)>;
2643 def : Pat<(i32 (anyext (loadi8 addr:$src))), (MOVZX32rm8 addr:$src)>;
2644 def : Pat<(i32 (anyext (loadi16 addr:$src))), (MOVZX32rm16 addr:$src)>;
2646 // (and (i32 load), 255) -> (zextload i8)
2647 def : Pat<(i32 (and (loadi32 addr:$src), (i32 255))), (MOVZX32rm8 addr:$src)>;
2648 def : Pat<(i32 (and (loadi32 addr:$src), (i32 65535))),(MOVZX32rm16 addr:$src)>;
2650 //===----------------------------------------------------------------------===//
2652 //===----------------------------------------------------------------------===//
2654 // (shl x, 1) ==> (add x, x)
2655 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
2656 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
2657 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
2659 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
2660 def : Pat<(or (srl GR32:$src1, CL:$amt),
2661 (shl GR32:$src2, (sub 32, CL:$amt))),
2662 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
2664 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
2665 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2666 (SHRD32mrCL addr:$dst, GR32:$src2)>;
2668 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
2669 def : Pat<(or (shl GR32:$src1, CL:$amt),
2670 (srl GR32:$src2, (sub 32, CL:$amt))),
2671 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
2673 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
2674 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2675 (SHLD32mrCL addr:$dst, GR32:$src2)>;
2677 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
2678 def : Pat<(or (srl GR16:$src1, CL:$amt),
2679 (shl GR16:$src2, (sub 16, CL:$amt))),
2680 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
2682 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
2683 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2684 (SHRD16mrCL addr:$dst, GR16:$src2)>;
2686 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
2687 def : Pat<(or (shl GR16:$src1, CL:$amt),
2688 (srl GR16:$src2, (sub 16, CL:$amt))),
2689 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
2691 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
2692 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2693 (SHLD16mrCL addr:$dst, GR16:$src2)>;
2695 //===----------------------------------------------------------------------===//
2696 // Floating Point Stack Support
2697 //===----------------------------------------------------------------------===//
2699 include "X86InstrFPStack.td"
2701 //===----------------------------------------------------------------------===//
2703 //===----------------------------------------------------------------------===//
2705 include "X86Instr64bit.td"
2707 //===----------------------------------------------------------------------===//
2708 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
2709 //===----------------------------------------------------------------------===//
2711 include "X86InstrMMX.td"
2713 //===----------------------------------------------------------------------===//
2714 // XMM Floating point support (requires SSE / SSE2)
2715 //===----------------------------------------------------------------------===//
2717 include "X86InstrSSE.td"