1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
35 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
49 // RES1, RES2, FLAGS = op LHS, RHS
50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
54 SDTCisInt<0>, SDTCisVT<1, i32>]>;
55 def SDTX86BrCond : SDTypeProfile<0, 3,
56 [SDTCisVT<0, OtherVT>,
57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 def SDTX86SetCC : SDTypeProfile<1, 2,
61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
62 def SDTX86SetCC_C : SDTypeProfile<1, 2,
64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
66 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
68 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
70 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
72 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
74 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
75 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
76 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
78 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
79 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
82 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
84 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
88 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
94 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
96 def SDTX86Void : SDTypeProfile<0, 0, []>;
98 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
100 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
102 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
104 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
106 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
108 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
110 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
112 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
114 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
116 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
117 [SDNPHasChain,SDNPSideEffect]>;
118 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
120 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
122 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
126 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
127 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
128 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
129 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
131 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
132 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
134 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
135 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
137 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
138 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
140 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
142 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
143 [SDNPHasChain, SDNPSideEffect]>;
145 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
146 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
147 SDNPMayLoad, SDNPMemOperand]>;
148 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
149 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
150 SDNPMayLoad, SDNPMemOperand]>;
151 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
152 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
153 SDNPMayLoad, SDNPMemOperand]>;
155 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
156 [SDNPHasChain, SDNPMayStore,
157 SDNPMayLoad, SDNPMemOperand]>;
158 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
159 [SDNPHasChain, SDNPMayStore,
160 SDNPMayLoad, SDNPMemOperand]>;
161 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
162 [SDNPHasChain, SDNPMayStore,
163 SDNPMayLoad, SDNPMemOperand]>;
164 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
165 [SDNPHasChain, SDNPMayStore,
166 SDNPMayLoad, SDNPMemOperand]>;
167 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
168 [SDNPHasChain, SDNPMayStore,
169 SDNPMayLoad, SDNPMemOperand]>;
170 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
171 [SDNPHasChain, SDNPMayStore,
172 SDNPMayLoad, SDNPMemOperand]>;
173 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
174 [SDNPHasChain, SDNPMayStore,
175 SDNPMayLoad, SDNPMemOperand]>;
176 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
177 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
179 def X86vastart_save_xmm_regs :
180 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
181 SDT_X86VASTART_SAVE_XMM_REGS,
182 [SDNPHasChain, SDNPVariadic]>;
184 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
185 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
187 def X86callseq_start :
188 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
189 [SDNPHasChain, SDNPOutGlue]>;
191 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
192 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
194 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
195 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
198 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
199 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
200 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
201 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
204 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
205 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
207 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
208 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
210 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
211 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
213 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
214 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
216 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
219 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
220 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
222 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
224 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
225 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
227 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
229 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
230 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
232 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
233 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
234 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
236 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
238 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
240 def X86andn_flag : SDNode<"X86ISD::ANDN", SDTBinaryArithWithFlags>;
242 def X86blsi_flag : SDNode<"X86ISD::BLSI", SDTUnaryArithWithFlags>;
243 def X86blsmsk_flag : SDNode<"X86ISD::BLSMSK", SDTUnaryArithWithFlags>;
244 def X86blsr_flag : SDNode<"X86ISD::BLSR", SDTUnaryArithWithFlags>;
246 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
248 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
249 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
251 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
254 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
255 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
257 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL,
258 [SDNPHasChain, SDNPOutGlue]>;
260 //===----------------------------------------------------------------------===//
261 // X86 Operand Definitions.
264 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
265 // the index operand of an address, to conform to x86 encoding restrictions.
266 def ptr_rc_nosp : PointerLikeRegClass<1>;
268 // *mem - Operand definitions for the funky X86 addressing mode operands.
270 def X86MemAsmOperand : AsmOperandClass {
271 let Name = "Mem"; let PredicateMethod = "isMem";
273 def X86Mem8AsmOperand : AsmOperandClass {
274 let Name = "Mem8"; let PredicateMethod = "isMem8";
276 def X86Mem16AsmOperand : AsmOperandClass {
277 let Name = "Mem16"; let PredicateMethod = "isMem16";
279 def X86Mem32AsmOperand : AsmOperandClass {
280 let Name = "Mem32"; let PredicateMethod = "isMem32";
282 def X86Mem64AsmOperand : AsmOperandClass {
283 let Name = "Mem64"; let PredicateMethod = "isMem64";
285 def X86Mem80AsmOperand : AsmOperandClass {
286 let Name = "Mem80"; let PredicateMethod = "isMem80";
288 def X86Mem128AsmOperand : AsmOperandClass {
289 let Name = "Mem128"; let PredicateMethod = "isMem128";
291 def X86Mem256AsmOperand : AsmOperandClass {
292 let Name = "Mem256"; let PredicateMethod = "isMem256";
295 // Gather mem operands
296 def X86MemVX32Operand : AsmOperandClass {
297 let Name = "MemVX32"; let PredicateMethod = "isMemVX32";
299 def X86MemVY32Operand : AsmOperandClass {
300 let Name = "MemVY32"; let PredicateMethod = "isMemVY32";
302 def X86MemVX64Operand : AsmOperandClass {
303 let Name = "MemVX64"; let PredicateMethod = "isMemVX64";
305 def X86MemVY64Operand : AsmOperandClass {
306 let Name = "MemVY64"; let PredicateMethod = "isMemVY64";
309 def X86AbsMemAsmOperand : AsmOperandClass {
311 let SuperClasses = [X86MemAsmOperand];
313 class X86MemOperand<string printMethod> : Operand<iPTR> {
314 let PrintMethod = printMethod;
315 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
316 let ParserMatchClass = X86MemAsmOperand;
319 let OperandType = "OPERAND_MEMORY" in {
320 def opaque32mem : X86MemOperand<"printopaquemem">;
321 def opaque48mem : X86MemOperand<"printopaquemem">;
322 def opaque80mem : X86MemOperand<"printopaquemem">;
323 def opaque512mem : X86MemOperand<"printopaquemem">;
325 def i8mem : X86MemOperand<"printi8mem"> {
326 let ParserMatchClass = X86Mem8AsmOperand; }
327 def i16mem : X86MemOperand<"printi16mem"> {
328 let ParserMatchClass = X86Mem16AsmOperand; }
329 def i32mem : X86MemOperand<"printi32mem"> {
330 let ParserMatchClass = X86Mem32AsmOperand; }
331 def i64mem : X86MemOperand<"printi64mem"> {
332 let ParserMatchClass = X86Mem64AsmOperand; }
333 def i128mem : X86MemOperand<"printi128mem"> {
334 let ParserMatchClass = X86Mem128AsmOperand; }
335 def i256mem : X86MemOperand<"printi256mem"> {
336 let ParserMatchClass = X86Mem256AsmOperand; }
337 def f32mem : X86MemOperand<"printf32mem"> {
338 let ParserMatchClass = X86Mem32AsmOperand; }
339 def f64mem : X86MemOperand<"printf64mem"> {
340 let ParserMatchClass = X86Mem64AsmOperand; }
341 def f80mem : X86MemOperand<"printf80mem"> {
342 let ParserMatchClass = X86Mem80AsmOperand; }
343 def f128mem : X86MemOperand<"printf128mem"> {
344 let ParserMatchClass = X86Mem128AsmOperand; }
345 def f256mem : X86MemOperand<"printf256mem">{
346 let ParserMatchClass = X86Mem256AsmOperand; }
348 // Gather mem operands
349 def vx32mem : X86MemOperand<"printi32mem">{
350 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
351 let ParserMatchClass = X86MemVX32Operand; }
352 def vy32mem : X86MemOperand<"printi32mem">{
353 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
354 let ParserMatchClass = X86MemVY32Operand; }
355 def vx64mem : X86MemOperand<"printi64mem">{
356 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
357 let ParserMatchClass = X86MemVX64Operand; }
358 def vy64mem : X86MemOperand<"printi64mem">{
359 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
360 let ParserMatchClass = X86MemVY64Operand; }
363 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
364 // plain GR64, so that it doesn't potentially require a REX prefix.
365 def i8mem_NOREX : Operand<i64> {
366 let PrintMethod = "printi8mem";
367 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
368 let ParserMatchClass = X86Mem8AsmOperand;
369 let OperandType = "OPERAND_MEMORY";
372 // GPRs available for tailcall.
373 // It represents GR32_TC, GR64_TC or GR64_TCW64.
374 def ptr_rc_tailcall : PointerLikeRegClass<2>;
376 // Special i32mem for addresses of load folding tail calls. These are not
377 // allowed to use callee-saved registers since they must be scheduled
378 // after callee-saved register are popped.
379 def i32mem_TC : Operand<i32> {
380 let PrintMethod = "printi32mem";
381 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
383 let ParserMatchClass = X86Mem32AsmOperand;
384 let OperandType = "OPERAND_MEMORY";
387 // Special i64mem for addresses of load folding tail calls. These are not
388 // allowed to use callee-saved registers since they must be scheduled
389 // after callee-saved register are popped.
390 def i64mem_TC : Operand<i64> {
391 let PrintMethod = "printi64mem";
392 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
393 ptr_rc_tailcall, i32imm, i8imm);
394 let ParserMatchClass = X86Mem64AsmOperand;
395 let OperandType = "OPERAND_MEMORY";
398 let OperandType = "OPERAND_PCREL",
399 ParserMatchClass = X86AbsMemAsmOperand,
400 PrintMethod = "printPCRelImm" in {
401 def i32imm_pcrel : Operand<i32>;
402 def i16imm_pcrel : Operand<i16>;
404 def offset8 : Operand<i64>;
405 def offset16 : Operand<i64>;
406 def offset32 : Operand<i64>;
407 def offset64 : Operand<i64>;
409 // Branch targets have OtherVT type and print as pc-relative values.
410 def brtarget : Operand<OtherVT>;
411 def brtarget8 : Operand<OtherVT>;
415 def SSECC : Operand<i8> {
416 let PrintMethod = "printSSECC";
417 let OperandType = "OPERAND_IMMEDIATE";
420 def AVXCC : Operand<i8> {
421 let PrintMethod = "printSSECC";
422 let OperandType = "OPERAND_IMMEDIATE";
425 class ImmSExtAsmOperandClass : AsmOperandClass {
426 let SuperClasses = [ImmAsmOperand];
427 let RenderMethod = "addImmOperands";
430 class ImmZExtAsmOperandClass : AsmOperandClass {
431 let SuperClasses = [ImmAsmOperand];
432 let RenderMethod = "addImmOperands";
435 // Sign-extended immediate classes. We don't need to define the full lattice
436 // here because there is no instruction with an ambiguity between ImmSExti64i32
439 // The strange ranges come from the fact that the assembler always works with
440 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
441 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
444 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
445 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
446 let Name = "ImmSExti64i32";
449 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
450 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
451 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
452 let Name = "ImmSExti16i8";
453 let SuperClasses = [ImmSExti64i32AsmOperand];
456 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
457 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
458 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
459 let Name = "ImmSExti32i8";
463 def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass {
464 let Name = "ImmZExtu32u8";
469 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
470 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
471 let Name = "ImmSExti64i8";
472 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
473 ImmSExti64i32AsmOperand];
476 // A couple of more descriptive operand definitions.
477 // 16-bits but only 8 bits are significant.
478 def i16i8imm : Operand<i16> {
479 let ParserMatchClass = ImmSExti16i8AsmOperand;
480 let OperandType = "OPERAND_IMMEDIATE";
482 // 32-bits but only 8 bits are significant.
483 def i32i8imm : Operand<i32> {
484 let ParserMatchClass = ImmSExti32i8AsmOperand;
485 let OperandType = "OPERAND_IMMEDIATE";
487 // 32-bits but only 8 bits are significant, and those 8 bits are unsigned.
488 def u32u8imm : Operand<i32> {
489 let ParserMatchClass = ImmZExtu32u8AsmOperand;
490 let OperandType = "OPERAND_IMMEDIATE";
493 // 64-bits but only 32 bits are significant.
494 def i64i32imm : Operand<i64> {
495 let ParserMatchClass = ImmSExti64i32AsmOperand;
496 let OperandType = "OPERAND_IMMEDIATE";
499 // 64-bits but only 32 bits are significant, and those bits are treated as being
501 def i64i32imm_pcrel : Operand<i64> {
502 let PrintMethod = "printPCRelImm";
503 let ParserMatchClass = X86AbsMemAsmOperand;
504 let OperandType = "OPERAND_PCREL";
507 // 64-bits but only 8 bits are significant.
508 def i64i8imm : Operand<i64> {
509 let ParserMatchClass = ImmSExti64i8AsmOperand;
510 let OperandType = "OPERAND_IMMEDIATE";
513 def lea64_32mem : Operand<i32> {
514 let PrintMethod = "printi32mem";
515 let AsmOperandLowerMethod = "lower_lea64_32mem";
516 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm);
517 let ParserMatchClass = X86MemAsmOperand;
521 //===----------------------------------------------------------------------===//
522 // X86 Complex Pattern Definitions.
525 // Define X86 specific addressing mode.
526 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
527 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
528 [add, sub, mul, X86mul_imm, shl, or, frameindex],
530 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
531 [tglobaltlsaddr], []>;
533 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
534 [tglobaltlsaddr], []>;
536 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
537 [add, sub, mul, X86mul_imm, shl, or, frameindex,
540 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
541 [tglobaltlsaddr], []>;
543 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
544 [tglobaltlsaddr], []>;
546 //===----------------------------------------------------------------------===//
547 // X86 Instruction Predicate Definitions.
548 def HasCMov : Predicate<"Subtarget->hasCMov()">;
549 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
551 def HasMMX : Predicate<"Subtarget->hasMMX()">;
552 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
553 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
554 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
555 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
556 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
557 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
558 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
559 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
560 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
561 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
562 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
563 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
564 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
565 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
566 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
567 def HasAVX : Predicate<"Subtarget->hasAVX()">;
568 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
569 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
571 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
572 def HasAES : Predicate<"Subtarget->hasAES()">;
573 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
574 def HasFMA : Predicate<"Subtarget->hasFMA()">;
575 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
576 def HasXOP : Predicate<"Subtarget->hasXOP()">;
577 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
578 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
579 def HasF16C : Predicate<"Subtarget->hasF16C()">;
580 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
581 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
582 def HasBMI : Predicate<"Subtarget->hasBMI()">;
583 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
584 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
585 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
586 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
587 def In32BitMode : Predicate<"!Subtarget->is64Bit()">,
588 AssemblerPredicate<"!Mode64Bit">;
589 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
590 AssemblerPredicate<"Mode64Bit">;
591 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
592 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
593 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
594 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
595 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
596 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
597 "TM.getCodeModel() != CodeModel::Kernel">;
598 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
599 "TM.getCodeModel() == CodeModel::Kernel">;
600 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
601 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
602 def OptForSize : Predicate<"OptForSize">;
603 def OptForSpeed : Predicate<"!OptForSize">;
604 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
605 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
607 //===----------------------------------------------------------------------===//
608 // X86 Instruction Format Definitions.
611 include "X86InstrFormats.td"
613 //===----------------------------------------------------------------------===//
614 // Pattern fragments.
617 // X86 specific condition code. These correspond to CondCode in
618 // X86InstrInfo.h. They must be kept in synch.
619 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
620 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
621 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
622 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
623 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
624 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
625 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
626 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
627 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
628 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
629 def X86_COND_NO : PatLeaf<(i8 10)>;
630 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
631 def X86_COND_NS : PatLeaf<(i8 12)>;
632 def X86_COND_O : PatLeaf<(i8 13)>;
633 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
634 def X86_COND_S : PatLeaf<(i8 15)>;
636 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
637 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
638 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
639 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
642 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
645 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
647 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
649 def i64immZExt32SExt8 : ImmLeaf<i64, [{
650 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
653 // Helper fragments for loads.
654 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
655 // known to be 32-bit aligned or better. Ditto for i8 to i16.
656 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
657 LoadSDNode *LD = cast<LoadSDNode>(N);
658 ISD::LoadExtType ExtType = LD->getExtensionType();
659 if (ExtType == ISD::NON_EXTLOAD)
661 if (ExtType == ISD::EXTLOAD)
662 return LD->getAlignment() >= 2 && !LD->isVolatile();
666 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
667 LoadSDNode *LD = cast<LoadSDNode>(N);
668 ISD::LoadExtType ExtType = LD->getExtensionType();
669 if (ExtType == ISD::EXTLOAD)
670 return LD->getAlignment() >= 2 && !LD->isVolatile();
674 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
675 LoadSDNode *LD = cast<LoadSDNode>(N);
676 ISD::LoadExtType ExtType = LD->getExtensionType();
677 if (ExtType == ISD::NON_EXTLOAD)
679 if (ExtType == ISD::EXTLOAD)
680 return LD->getAlignment() >= 4 && !LD->isVolatile();
684 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
685 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
686 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
687 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
688 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
690 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
691 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
692 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
693 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
694 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
695 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
697 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
698 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
699 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
700 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
701 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
702 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
703 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
704 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
705 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
706 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
708 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
709 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
710 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
711 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
712 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
713 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
714 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
715 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
716 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
717 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
720 // An 'and' node with a single use.
721 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
722 return N->hasOneUse();
724 // An 'srl' node with a single use.
725 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
726 return N->hasOneUse();
728 // An 'trunc' node with a single use.
729 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
730 return N->hasOneUse();
733 //===----------------------------------------------------------------------===//
738 let neverHasSideEffects = 1 in {
739 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
740 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
741 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize;
742 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
743 "nop{l}\t$zero", [], IIC_NOP>, TB;
747 // Constructing a stack frame.
748 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
749 "enter\t$len, $lvl", [], IIC_ENTER>;
751 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
752 def LEAVE : I<0xC9, RawFrm,
753 (outs), (ins), "leave", [], IIC_LEAVE>,
754 Requires<[In32BitMode]>;
756 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
757 def LEAVE64 : I<0xC9, RawFrm,
758 (outs), (ins), "leave", [], IIC_LEAVE>,
759 Requires<[In64BitMode]>;
761 //===----------------------------------------------------------------------===//
762 // Miscellaneous Instructions.
765 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
767 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
768 IIC_POP_REG16>, OpSize;
769 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
771 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
772 IIC_POP_REG>, OpSize;
773 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", [],
774 IIC_POP_MEM>, OpSize;
775 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
777 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", [],
780 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, OpSize;
781 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
782 Requires<[In32BitMode]>;
785 let mayStore = 1 in {
786 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
787 IIC_PUSH_REG>, OpSize;
788 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
790 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
791 IIC_PUSH_REG>, OpSize;
792 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
795 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
797 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
800 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
801 "push{l}\t$imm", [], IIC_PUSH_IMM>;
802 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
803 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize;
804 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
805 "push{l}\t$imm", [], IIC_PUSH_IMM>;
807 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
809 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
810 Requires<[In32BitMode]>;
815 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
817 def POP64r : I<0x58, AddRegFrm,
818 (outs GR64:$reg), (ins), "pop{q}\t$reg", [], IIC_POP_REG>;
819 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
821 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", [],
824 let mayStore = 1 in {
825 def PUSH64r : I<0x50, AddRegFrm,
826 (outs), (ins GR64:$reg), "push{q}\t$reg", [], IIC_PUSH_REG>;
827 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
829 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
834 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
835 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
836 "push{q}\t$imm", [], IIC_PUSH_IMM>;
837 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
838 "push{q}\t$imm", [], IIC_PUSH_IMM>;
839 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
840 "push{q}\t$imm", [], IIC_PUSH_IMM>;
843 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
844 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
845 Requires<[In64BitMode]>;
846 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
847 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
848 Requires<[In64BitMode]>;
852 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
853 mayLoad=1, neverHasSideEffects=1 in {
854 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", [], IIC_POP_A>,
855 Requires<[In32BitMode]>;
857 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
858 mayStore=1, neverHasSideEffects=1 in {
859 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", [], IIC_PUSH_A>,
860 Requires<[In32BitMode]>;
863 let Constraints = "$src = $dst" in { // GR32 = bswap GR32
864 def BSWAP32r : I<0xC8, AddRegFrm,
865 (outs GR32:$dst), (ins GR32:$src),
867 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, TB;
869 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
871 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
872 } // Constraints = "$src = $dst"
874 // Bit scan instructions.
875 let Defs = [EFLAGS] in {
876 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
877 "bsf{w}\t{$src, $dst|$dst, $src}",
878 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
879 IIC_BSF>, TB, OpSize;
880 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
881 "bsf{w}\t{$src, $dst|$dst, $src}",
882 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
883 IIC_BSF>, TB, OpSize;
884 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
885 "bsf{l}\t{$src, $dst|$dst, $src}",
886 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))], IIC_BSF>, TB;
887 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
888 "bsf{l}\t{$src, $dst|$dst, $src}",
889 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
891 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
892 "bsf{q}\t{$src, $dst|$dst, $src}",
893 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
895 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
896 "bsf{q}\t{$src, $dst|$dst, $src}",
897 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
900 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
901 "bsr{w}\t{$src, $dst|$dst, $src}",
902 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))], IIC_BSR>,
904 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
905 "bsr{w}\t{$src, $dst|$dst, $src}",
906 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
909 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
910 "bsr{l}\t{$src, $dst|$dst, $src}",
911 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))], IIC_BSR>, TB;
912 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
913 "bsr{l}\t{$src, $dst|$dst, $src}",
914 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
916 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
917 "bsr{q}\t{$src, $dst|$dst, $src}",
918 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], IIC_BSR>, TB;
919 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
920 "bsr{q}\t{$src, $dst|$dst, $src}",
921 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
926 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
927 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
928 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", [], IIC_MOVS>;
929 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", [], IIC_MOVS>, OpSize;
930 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", [], IIC_MOVS>;
931 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", [], IIC_MOVS>;
934 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
935 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
936 def STOSB : I<0xAA, RawFrm, (outs), (ins), "stosb", [], IIC_STOS>;
937 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
938 def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", [], IIC_STOS>, OpSize;
939 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
940 def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", [], IIC_STOS>;
941 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
942 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", [], IIC_STOS>;
944 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", [], IIC_SCAS>;
945 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", [], IIC_SCAS>, OpSize;
946 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", [], IIC_SCAS>;
947 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", [], IIC_SCAS>;
949 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", [], IIC_CMPS>;
950 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", [], IIC_CMPS>, OpSize;
951 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", [], IIC_CMPS>;
952 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", [], IIC_CMPS>;
955 //===----------------------------------------------------------------------===//
956 // Move Instructions.
959 let neverHasSideEffects = 1 in {
960 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
961 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
962 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
963 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
964 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
965 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
966 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
967 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
969 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
970 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
971 "mov{b}\t{$src, $dst|$dst, $src}",
972 [(set GR8:$dst, imm:$src)], IIC_MOV>;
973 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
974 "mov{w}\t{$src, $dst|$dst, $src}",
975 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize;
976 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
977 "mov{l}\t{$src, $dst|$dst, $src}",
978 [(set GR32:$dst, imm:$src)], IIC_MOV>;
979 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
980 "movabs{q}\t{$src, $dst|$dst, $src}",
981 [(set GR64:$dst, imm:$src)], IIC_MOV>;
982 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
983 "mov{q}\t{$src, $dst|$dst, $src}",
984 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
987 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
988 "mov{b}\t{$src, $dst|$dst, $src}",
989 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
990 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
991 "mov{w}\t{$src, $dst|$dst, $src}",
992 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize;
993 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
994 "mov{l}\t{$src, $dst|$dst, $src}",
995 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>;
996 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
997 "mov{q}\t{$src, $dst|$dst, $src}",
998 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
1000 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
1001 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
1002 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
1003 "mov{b}\t{$src, %al|AL, $src}", [], IIC_MOV_MEM>,
1004 Requires<[In32BitMode]>;
1005 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
1006 "mov{w}\t{$src, %ax|AL, $src}", [], IIC_MOV_MEM>, OpSize,
1007 Requires<[In32BitMode]>;
1008 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1009 "mov{l}\t{$src, %eax|EAX, $src}", [], IIC_MOV_MEM>,
1010 Requires<[In32BitMode]>;
1011 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1012 "mov{b}\t{%al, $dst|$dst, AL}", [], IIC_MOV_MEM>,
1013 Requires<[In32BitMode]>;
1014 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1015 "mov{w}\t{%ax, $dst|$dst, AL}", [], IIC_MOV_MEM>, OpSize,
1016 Requires<[In32BitMode]>;
1017 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1018 "mov{l}\t{%eax, $dst|$dst, EAX}", [], IIC_MOV_MEM>,
1019 Requires<[In32BitMode]>;
1021 // FIXME: These definitions are utterly broken
1022 // Just leave them commented out for now because they're useless outside
1023 // of the large code model, and most compilers won't generate the instructions
1026 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
1027 "mov{q}\t{$src, %rax|RAX, $src}", []>;
1028 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
1029 "mov{q}\t{$src, %rax|RAX, $src}", []>;
1030 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
1031 "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
1032 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
1033 "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
1037 let isCodeGenOnly = 1 in {
1038 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1039 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1040 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1041 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
1042 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1043 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1044 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1045 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1048 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1049 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1050 "mov{b}\t{$src, $dst|$dst, $src}",
1051 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1052 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1053 "mov{w}\t{$src, $dst|$dst, $src}",
1054 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize;
1055 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1056 "mov{l}\t{$src, $dst|$dst, $src}",
1057 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>;
1058 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1059 "mov{q}\t{$src, $dst|$dst, $src}",
1060 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1063 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1064 "mov{b}\t{$src, $dst|$dst, $src}",
1065 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1066 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1067 "mov{w}\t{$src, $dst|$dst, $src}",
1068 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize;
1069 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1070 "mov{l}\t{$src, $dst|$dst, $src}",
1071 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>;
1072 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1073 "mov{q}\t{$src, $dst|$dst, $src}",
1074 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1076 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1077 // that they can be used for copying and storing h registers, which can't be
1078 // encoded when a REX prefix is present.
1079 let isCodeGenOnly = 1 in {
1080 let neverHasSideEffects = 1 in
1081 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1082 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1083 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>;
1085 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1086 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1087 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1089 let mayLoad = 1, neverHasSideEffects = 1,
1090 canFoldAsLoad = 1, isReMaterializable = 1 in
1091 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1092 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1093 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1098 // Condition code ops, incl. set if equal/not equal/...
1099 let Defs = [EFLAGS], Uses = [AH] in
1100 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1101 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
1102 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
1103 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1104 IIC_AHF>; // AH = flags
1107 //===----------------------------------------------------------------------===//
1108 // Bit tests instructions: BT, BTS, BTR, BTC.
1110 let Defs = [EFLAGS] in {
1111 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1112 "bt{w}\t{$src2, $src1|$src1, $src2}",
1113 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1115 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1116 "bt{l}\t{$src2, $src1|$src1, $src2}",
1117 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>, TB;
1118 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1119 "bt{q}\t{$src2, $src1|$src1, $src2}",
1120 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1122 // Unlike with the register+register form, the memory+register form of the
1123 // bt instruction does not ignore the high bits of the index. From ISel's
1124 // perspective, this is pretty bizarre. Make these instructions disassembly
1127 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1128 "bt{w}\t{$src2, $src1|$src1, $src2}",
1129 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1130 // (implicit EFLAGS)]
1132 >, OpSize, TB, Requires<[FastBTMem]>;
1133 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1134 "bt{l}\t{$src2, $src1|$src1, $src2}",
1135 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1136 // (implicit EFLAGS)]
1138 >, TB, Requires<[FastBTMem]>;
1139 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1140 "bt{q}\t{$src2, $src1|$src1, $src2}",
1141 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1142 // (implicit EFLAGS)]
1146 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1147 "bt{w}\t{$src2, $src1|$src1, $src2}",
1148 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1149 IIC_BT_RI>, OpSize, TB;
1150 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1151 "bt{l}\t{$src2, $src1|$src1, $src2}",
1152 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1154 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1155 "bt{q}\t{$src2, $src1|$src1, $src2}",
1156 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1159 // Note that these instructions don't need FastBTMem because that
1160 // only applies when the other operand is in a register. When it's
1161 // an immediate, bt is still fast.
1162 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1163 "bt{w}\t{$src2, $src1|$src1, $src2}",
1164 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1165 ], IIC_BT_MI>, OpSize, TB;
1166 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1167 "bt{l}\t{$src2, $src1|$src1, $src2}",
1168 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1170 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1171 "bt{q}\t{$src2, $src1|$src1, $src2}",
1172 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1173 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1176 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1177 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1179 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1180 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1181 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1182 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1183 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1184 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1186 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1187 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1188 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1189 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1190 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1191 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1193 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1194 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1195 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1196 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1197 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1198 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1200 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1201 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1202 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1203 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1205 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1206 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1208 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1209 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1210 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1211 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1212 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1213 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1215 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1216 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1217 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1218 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1219 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1220 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1222 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1223 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1224 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1225 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1226 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1227 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1229 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1230 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1231 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1232 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1234 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1235 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1237 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1238 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1239 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1240 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1241 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1242 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1244 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1245 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1246 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1247 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1248 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1249 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1251 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1252 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1253 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1254 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1255 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1256 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1258 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1259 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1260 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1261 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1262 } // Defs = [EFLAGS]
1265 //===----------------------------------------------------------------------===//
1269 // Atomic swap. These are just normal xchg instructions. But since a memory
1270 // operand is referenced, the atomicity is ensured.
1271 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
1272 InstrItinClass itin> {
1273 let Constraints = "$val = $dst" in {
1274 def #NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
1275 (ins GR8:$val, i8mem:$ptr),
1276 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
1279 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
1281 def #NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
1282 (ins GR16:$val, i16mem:$ptr),
1283 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
1286 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
1288 def #NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
1289 (ins GR32:$val, i32mem:$ptr),
1290 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
1293 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
1295 def #NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
1296 (ins GR64:$val, i64mem:$ptr),
1297 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
1300 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
1305 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
1307 // Swap between registers.
1308 let Constraints = "$val = $dst" in {
1309 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1310 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1311 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1312 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, OpSize;
1313 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1314 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1315 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1316 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1319 // Swap between EAX and other registers.
1320 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1321 "xchg{w}\t{$src, %ax|AX, $src}", [], IIC_XCHG_REG>, OpSize;
1322 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1323 "xchg{l}\t{$src, %eax|EAX, $src}", [], IIC_XCHG_REG>,
1324 Requires<[In32BitMode]>;
1325 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1326 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1327 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1328 "xchg{l}\t{$src, %eax|EAX, $src}", [], IIC_XCHG_REG>,
1329 Requires<[In64BitMode]>;
1330 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1331 "xchg{q}\t{$src, %rax|RAX, $src}", [], IIC_XCHG_REG>;
1335 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1336 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1337 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1338 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1340 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1341 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1342 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1343 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1345 let mayLoad = 1, mayStore = 1 in {
1346 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1347 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1348 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1349 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1351 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1352 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1353 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1354 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1358 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1359 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1360 IIC_CMPXCHG_REG8>, TB;
1361 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1362 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1363 IIC_CMPXCHG_REG>, TB, OpSize;
1364 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1365 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1366 IIC_CMPXCHG_REG>, TB;
1367 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1368 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1369 IIC_CMPXCHG_REG>, TB;
1371 let mayLoad = 1, mayStore = 1 in {
1372 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1373 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1374 IIC_CMPXCHG_MEM8>, TB;
1375 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1376 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1377 IIC_CMPXCHG_MEM>, TB, OpSize;
1378 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1379 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1380 IIC_CMPXCHG_MEM>, TB;
1381 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1382 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1383 IIC_CMPXCHG_MEM>, TB;
1386 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1387 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1388 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1390 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1391 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1392 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1393 TB, Requires<[HasCmpxchg16b]>;
1397 // Lock instruction prefix
1398 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1400 // Rex64 instruction prefix
1401 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>;
1403 // Data16 instruction prefix
1404 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1406 // Repeat string operation instruction prefixes
1407 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1408 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1409 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1410 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1411 // Repeat while not equal (used with CMPS and SCAS)
1412 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1416 // String manipulation instructions
1417 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", [], IIC_LODS>;
1418 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", [], IIC_LODS>, OpSize;
1419 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", [], IIC_LODS>;
1420 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", [], IIC_LODS>;
1422 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", [], IIC_OUTS>;
1423 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", [], IIC_OUTS>, OpSize;
1424 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", [], IIC_OUTS>;
1427 // Flag instructions
1428 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1429 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1430 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1431 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1432 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1433 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1434 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1436 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1438 // Table lookup instructions
1439 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>;
1441 // ASCII Adjust After Addition
1442 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1443 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1444 Requires<[In32BitMode]>;
1446 // ASCII Adjust AX Before Division
1447 // sets AL, AH and EFLAGS and uses AL and AH
1448 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1449 "aad\t$src", [], IIC_AAD>, Requires<[In32BitMode]>;
1451 // ASCII Adjust AX After Multiply
1452 // sets AL, AH and EFLAGS and uses AL
1453 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1454 "aam\t$src", [], IIC_AAM>, Requires<[In32BitMode]>;
1456 // ASCII Adjust AL After Subtraction - sets
1457 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1458 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1459 Requires<[In32BitMode]>;
1461 // Decimal Adjust AL after Addition
1462 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1463 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1464 Requires<[In32BitMode]>;
1466 // Decimal Adjust AL after Subtraction
1467 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1468 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1469 Requires<[In32BitMode]>;
1471 // Check Array Index Against Bounds
1472 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1473 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize,
1474 Requires<[In32BitMode]>;
1475 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1476 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>,
1477 Requires<[In32BitMode]>;
1479 // Adjust RPL Field of Segment Selector
1480 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$src), (ins GR16:$dst),
1481 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1482 Requires<[In32BitMode]>;
1483 def ARPL16mr : I<0x63, MRMSrcMem, (outs GR16:$src), (ins i16mem:$dst),
1484 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1485 Requires<[In32BitMode]>;
1487 //===----------------------------------------------------------------------===//
1488 // MOVBE Instructions
1490 let Predicates = [HasMOVBE] in {
1491 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1492 "movbe{w}\t{$src, $dst|$dst, $src}",
1493 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1495 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1496 "movbe{l}\t{$src, $dst|$dst, $src}",
1497 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1499 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1500 "movbe{q}\t{$src, $dst|$dst, $src}",
1501 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
1503 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1504 "movbe{w}\t{$src, $dst|$dst, $src}",
1505 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1507 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1508 "movbe{l}\t{$src, $dst|$dst, $src}",
1509 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1511 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1512 "movbe{q}\t{$src, $dst|$dst, $src}",
1513 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
1517 //===----------------------------------------------------------------------===//
1518 // RDRAND Instruction
1520 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1521 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1523 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize, TB;
1524 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1526 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, TB;
1527 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1529 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
1532 //===----------------------------------------------------------------------===//
1533 // LZCNT Instruction
1535 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
1536 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1537 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1538 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
1540 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1541 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1542 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
1543 (implicit EFLAGS)]>, XS, OpSize;
1545 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1546 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1547 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS;
1548 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1549 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1550 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
1551 (implicit EFLAGS)]>, XS;
1553 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1554 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1555 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
1557 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1558 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1559 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
1560 (implicit EFLAGS)]>, XS;
1563 //===----------------------------------------------------------------------===//
1566 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1567 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1568 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1569 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
1571 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1572 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1573 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
1574 (implicit EFLAGS)]>, XS, OpSize;
1576 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1577 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1578 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS;
1579 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1580 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1581 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
1582 (implicit EFLAGS)]>, XS;
1584 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1585 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1586 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
1588 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1589 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1590 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
1591 (implicit EFLAGS)]>, XS;
1594 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
1595 RegisterClass RC, X86MemOperand x86memop, SDNode OpNode,
1597 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
1598 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1599 [(set RC:$dst, EFLAGS, (OpNode RC:$src))]>, T8, VEX_4V;
1600 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
1601 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1602 [(set RC:$dst, EFLAGS, (OpNode (ld_frag addr:$src)))]>,
1606 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1607 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem,
1608 X86blsr_flag, loadi32>;
1609 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem,
1610 X86blsr_flag, loadi64>, VEX_W;
1611 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem,
1612 X86blsmsk_flag, loadi32>;
1613 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem,
1614 X86blsmsk_flag, loadi64>, VEX_W;
1615 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem,
1616 X86blsi_flag, loadi32>;
1617 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem,
1618 X86blsi_flag, loadi64>, VEX_W;
1621 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
1622 X86MemOperand x86memop, Intrinsic Int,
1624 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1625 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1626 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
1628 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
1629 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1630 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
1631 (implicit EFLAGS)]>, T8, VEX_4VOp3;
1634 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1635 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
1636 int_x86_bmi_bextr_32, loadi32>;
1637 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
1638 int_x86_bmi_bextr_64, loadi64>, VEX_W;
1641 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
1642 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
1643 int_x86_bmi_bzhi_32, loadi32>;
1644 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
1645 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
1648 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
1649 X86MemOperand x86memop, Intrinsic Int,
1651 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1652 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1653 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
1655 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1656 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1657 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
1660 let Predicates = [HasBMI2] in {
1661 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
1662 int_x86_bmi_pdep_32, loadi32>, T8XD;
1663 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
1664 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
1665 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
1666 int_x86_bmi_pext_32, loadi32>, T8XS;
1667 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
1668 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
1671 //===----------------------------------------------------------------------===//
1673 //===----------------------------------------------------------------------===//
1675 include "X86InstrArithmetic.td"
1676 include "X86InstrCMovSetCC.td"
1677 include "X86InstrExtension.td"
1678 include "X86InstrControl.td"
1679 include "X86InstrShiftRotate.td"
1681 // X87 Floating Point Stack.
1682 include "X86InstrFPStack.td"
1684 // SIMD support (SSE, MMX and AVX)
1685 include "X86InstrFragmentsSIMD.td"
1687 // FMA - Fused Multiply-Add support (requires FMA)
1688 include "X86InstrFMA.td"
1691 include "X86InstrXOP.td"
1693 // SSE, MMX and 3DNow! vector support.
1694 include "X86InstrSSE.td"
1695 include "X86InstrMMX.td"
1696 include "X86Instr3DNow.td"
1698 include "X86InstrVMX.td"
1699 include "X86InstrSVM.td"
1701 // System instructions.
1702 include "X86InstrSystem.td"
1704 // Compiler Pseudo Instructions and Pat Patterns
1705 include "X86InstrCompiler.td"
1707 //===----------------------------------------------------------------------===//
1708 // Assembler Mnemonic Aliases
1709 //===----------------------------------------------------------------------===//
1711 def : MnemonicAlias<"call", "calll">, Requires<[In32BitMode]>;
1712 def : MnemonicAlias<"call", "callq">, Requires<[In64BitMode]>;
1714 def : MnemonicAlias<"cbw", "cbtw">;
1715 def : MnemonicAlias<"cwde", "cwtl">;
1716 def : MnemonicAlias<"cwd", "cwtd">;
1717 def : MnemonicAlias<"cdq", "cltd">;
1718 def : MnemonicAlias<"cdqe", "cltq">;
1719 def : MnemonicAlias<"cqo", "cqto">;
1721 // lret maps to lretl, it is not ambiguous with lretq.
1722 def : MnemonicAlias<"lret", "lretl">;
1724 def : MnemonicAlias<"leavel", "leave">, Requires<[In32BitMode]>;
1725 def : MnemonicAlias<"leaveq", "leave">, Requires<[In64BitMode]>;
1727 def : MnemonicAlias<"loopz", "loope">;
1728 def : MnemonicAlias<"loopnz", "loopne">;
1730 def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
1731 def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
1732 def : MnemonicAlias<"popf", "popfl">, Requires<[In32BitMode]>;
1733 def : MnemonicAlias<"popf", "popfq">, Requires<[In64BitMode]>;
1734 def : MnemonicAlias<"popfd", "popfl">;
1736 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
1737 // all modes. However: "push (addr)" and "push $42" should default to
1738 // pushl/pushq depending on the current mode. Similar for "pop %bx"
1739 def : MnemonicAlias<"push", "pushl">, Requires<[In32BitMode]>;
1740 def : MnemonicAlias<"push", "pushq">, Requires<[In64BitMode]>;
1741 def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
1742 def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1743 def : MnemonicAlias<"pushfd", "pushfl">;
1745 def : MnemonicAlias<"repe", "rep">;
1746 def : MnemonicAlias<"repz", "rep">;
1747 def : MnemonicAlias<"repnz", "repne">;
1749 def : MnemonicAlias<"retl", "ret">, Requires<[In32BitMode]>;
1750 def : MnemonicAlias<"retq", "ret">, Requires<[In64BitMode]>;
1752 def : MnemonicAlias<"salb", "shlb">;
1753 def : MnemonicAlias<"salw", "shlw">;
1754 def : MnemonicAlias<"sall", "shll">;
1755 def : MnemonicAlias<"salq", "shlq">;
1757 def : MnemonicAlias<"smovb", "movsb">;
1758 def : MnemonicAlias<"smovw", "movsw">;
1759 def : MnemonicAlias<"smovl", "movsl">;
1760 def : MnemonicAlias<"smovq", "movsq">;
1762 def : MnemonicAlias<"ud2a", "ud2">;
1763 def : MnemonicAlias<"verrw", "verr">;
1765 // System instruction aliases.
1766 def : MnemonicAlias<"iret", "iretl">;
1767 def : MnemonicAlias<"sysret", "sysretl">;
1768 def : MnemonicAlias<"sysexit", "sysexitl">;
1770 def : MnemonicAlias<"lgdtl", "lgdt">, Requires<[In32BitMode]>;
1771 def : MnemonicAlias<"lgdtq", "lgdt">, Requires<[In64BitMode]>;
1772 def : MnemonicAlias<"lidtl", "lidt">, Requires<[In32BitMode]>;
1773 def : MnemonicAlias<"lidtq", "lidt">, Requires<[In64BitMode]>;
1774 def : MnemonicAlias<"sgdtl", "sgdt">, Requires<[In32BitMode]>;
1775 def : MnemonicAlias<"sgdtq", "sgdt">, Requires<[In64BitMode]>;
1776 def : MnemonicAlias<"sidtl", "sidt">, Requires<[In32BitMode]>;
1777 def : MnemonicAlias<"sidtq", "sidt">, Requires<[In64BitMode]>;
1780 // Floating point stack aliases.
1781 def : MnemonicAlias<"fcmovz", "fcmove">;
1782 def : MnemonicAlias<"fcmova", "fcmovnbe">;
1783 def : MnemonicAlias<"fcmovnae", "fcmovb">;
1784 def : MnemonicAlias<"fcmovna", "fcmovbe">;
1785 def : MnemonicAlias<"fcmovae", "fcmovnb">;
1786 def : MnemonicAlias<"fcomip", "fcompi">;
1787 def : MnemonicAlias<"fildq", "fildll">;
1788 def : MnemonicAlias<"fistpq", "fistpll">;
1789 def : MnemonicAlias<"fisttpq", "fisttpll">;
1790 def : MnemonicAlias<"fldcww", "fldcw">;
1791 def : MnemonicAlias<"fnstcww", "fnstcw">;
1792 def : MnemonicAlias<"fnstsww", "fnstsw">;
1793 def : MnemonicAlias<"fucomip", "fucompi">;
1794 def : MnemonicAlias<"fwait", "wait">;
1797 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond>
1798 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
1799 !strconcat(Prefix, NewCond, Suffix)>;
1801 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
1802 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
1803 /// example "setz" -> "sete".
1804 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix> {
1805 def C : CondCodeAlias<Prefix, Suffix, "c", "b">; // setc -> setb
1806 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e">; // setz -> sete
1807 def NA : CondCodeAlias<Prefix, Suffix, "na", "be">; // setna -> setbe
1808 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae">; // setnb -> setae
1809 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae">; // setnc -> setae
1810 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le">; // setng -> setle
1811 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge">; // setnl -> setge
1812 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne">; // setnz -> setne
1813 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p">; // setpe -> setp
1814 def PO : CondCodeAlias<Prefix, Suffix, "po", "np">; // setpo -> setnp
1816 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b">; // setnae -> setb
1817 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a">; // setnbe -> seta
1818 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l">; // setnge -> setl
1819 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g">; // setnle -> setg
1822 // Aliases for set<CC>
1823 defm : IntegerCondCodeMnemonicAlias<"set", "">;
1824 // Aliases for j<CC>
1825 defm : IntegerCondCodeMnemonicAlias<"j", "">;
1826 // Aliases for cmov<CC>{w,l,q}
1827 defm : IntegerCondCodeMnemonicAlias<"cmov", "w">;
1828 defm : IntegerCondCodeMnemonicAlias<"cmov", "l">;
1829 defm : IntegerCondCodeMnemonicAlias<"cmov", "q">;
1832 //===----------------------------------------------------------------------===//
1833 // Assembler Instruction Aliases
1834 //===----------------------------------------------------------------------===//
1836 // aad/aam default to base 10 if no operand is specified.
1837 def : InstAlias<"aad", (AAD8i8 10)>;
1838 def : InstAlias<"aam", (AAM8i8 10)>;
1840 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
1841 def : InstAlias<"bt $imm, $mem", (BT32mi8 i32mem:$mem, i32i8imm:$imm)>;
1844 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>;
1845 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>;
1846 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
1847 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
1849 // div and idiv aliases for explicit A register.
1850 def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>;
1851 def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>;
1852 def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>;
1853 def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>;
1854 def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>;
1855 def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>;
1856 def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>;
1857 def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>;
1858 def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>;
1859 def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>;
1860 def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>;
1861 def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>;
1862 def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>;
1863 def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>;
1864 def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>;
1865 def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>;
1869 // Various unary fpstack operations default to operating on on ST1.
1870 // For example, "fxch" -> "fxch %st(1)"
1871 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
1872 def : InstAlias<"fsubp", (SUBR_FPrST0 ST1)>;
1873 def : InstAlias<"fsubrp", (SUB_FPrST0 ST1)>;
1874 def : InstAlias<"fmulp", (MUL_FPrST0 ST1)>;
1875 def : InstAlias<"fdivp", (DIVR_FPrST0 ST1)>;
1876 def : InstAlias<"fdivrp", (DIV_FPrST0 ST1)>;
1877 def : InstAlias<"fxch", (XCH_F ST1)>;
1878 def : InstAlias<"fcomi", (COM_FIr ST1)>;
1879 def : InstAlias<"fcompi", (COM_FIPr ST1)>;
1880 def : InstAlias<"fucom", (UCOM_Fr ST1)>;
1881 def : InstAlias<"fucomp", (UCOM_FPr ST1)>;
1882 def : InstAlias<"fucomi", (UCOM_FIr ST1)>;
1883 def : InstAlias<"fucompi", (UCOM_FIPr ST1)>;
1885 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
1886 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
1887 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
1889 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
1890 def : InstAlias<!strconcat(Mnemonic, " $op, %st(0)"),
1891 (Inst RST:$op), EmitAlias>;
1892 def : InstAlias<!strconcat(Mnemonic, " %st(0), %st(0)"),
1893 (Inst ST0), EmitAlias>;
1896 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
1897 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
1898 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
1899 defm : FpUnaryAlias<"fsubp", SUBR_FPrST0>;
1900 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
1901 defm : FpUnaryAlias<"fsubrp", SUB_FPrST0>;
1902 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
1903 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
1904 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
1905 defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>;
1906 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
1907 defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>;
1908 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
1909 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
1910 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
1911 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
1914 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
1915 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
1916 // solely because gas supports it.
1917 def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op), 0>;
1918 def : InstAlias<"fmulp %st(0), $op", (MUL_FPrST0 RST:$op)>;
1919 def : InstAlias<"fsubp %st(0), $op", (SUBR_FPrST0 RST:$op)>;
1920 def : InstAlias<"fsubrp %st(0), $op", (SUB_FPrST0 RST:$op)>;
1921 def : InstAlias<"fdivp %st(0), $op", (DIVR_FPrST0 RST:$op)>;
1922 def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>;
1924 // We accept "fnstsw %eax" even though it only writes %ax.
1925 def : InstAlias<"fnstsw %eax", (FNSTSW16r)>;
1926 def : InstAlias<"fnstsw %al" , (FNSTSW16r)>;
1927 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
1929 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
1930 // this is compatible with what GAS does.
1931 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1932 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1933 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>;
1934 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>;
1936 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
1937 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
1938 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
1939 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
1940 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
1941 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
1942 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
1944 // inb %dx -> inb %al, %dx
1945 def : InstAlias<"inb %dx", (IN8rr)>;
1946 def : InstAlias<"inw %dx", (IN16rr)>;
1947 def : InstAlias<"inl %dx", (IN32rr)>;
1948 def : InstAlias<"inb $port", (IN8ri i8imm:$port)>;
1949 def : InstAlias<"inw $port", (IN16ri i8imm:$port)>;
1950 def : InstAlias<"inl $port", (IN32ri i8imm:$port)>;
1953 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
1954 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1955 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1956 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
1957 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
1958 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1959 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1961 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
1962 // the move. All segment/mem forms are equivalent, this has the shortest
1964 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
1965 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
1967 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
1968 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
1970 // Match 'movq GR64, MMX' as an alias for movd.
1971 def : InstAlias<"movq $src, $dst",
1972 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
1973 def : InstAlias<"movq $src, $dst",
1974 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
1976 // movsd with no operands (as opposed to the SSE scalar move of a double) is an
1977 // alias for movsl. (as in rep; movsd)
1978 def : InstAlias<"movsd", (MOVSD)>;
1981 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
1982 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
1983 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
1984 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
1985 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
1986 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
1987 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
1990 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
1991 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
1992 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
1993 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
1994 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
1995 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
1996 // Note: No GR32->GR64 movzx form.
1998 // outb %dx -> outb %al, %dx
1999 def : InstAlias<"outb %dx", (OUT8rr)>;
2000 def : InstAlias<"outw %dx", (OUT16rr)>;
2001 def : InstAlias<"outl %dx", (OUT32rr)>;
2002 def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>;
2003 def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>;
2004 def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>;
2006 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
2007 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
2008 // errors, since its encoding is the most compact.
2009 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
2011 // shld/shrd op,op -> shld op, op, CL
2012 def : InstAlias<"shldw $r2, $r1", (SHLD16rrCL GR16:$r1, GR16:$r2)>;
2013 def : InstAlias<"shldl $r2, $r1", (SHLD32rrCL GR32:$r1, GR32:$r2)>;
2014 def : InstAlias<"shldq $r2, $r1", (SHLD64rrCL GR64:$r1, GR64:$r2)>;
2015 def : InstAlias<"shrdw $r2, $r1", (SHRD16rrCL GR16:$r1, GR16:$r2)>;
2016 def : InstAlias<"shrdl $r2, $r1", (SHRD32rrCL GR32:$r1, GR32:$r2)>;
2017 def : InstAlias<"shrdq $r2, $r1", (SHRD64rrCL GR64:$r1, GR64:$r2)>;
2019 def : InstAlias<"shldw $reg, $mem", (SHLD16mrCL i16mem:$mem, GR16:$reg)>;
2020 def : InstAlias<"shldl $reg, $mem", (SHLD32mrCL i32mem:$mem, GR32:$reg)>;
2021 def : InstAlias<"shldq $reg, $mem", (SHLD64mrCL i64mem:$mem, GR64:$reg)>;
2022 def : InstAlias<"shrdw $reg, $mem", (SHRD16mrCL i16mem:$mem, GR16:$reg)>;
2023 def : InstAlias<"shrdl $reg, $mem", (SHRD32mrCL i32mem:$mem, GR32:$reg)>;
2024 def : InstAlias<"shrdq $reg, $mem", (SHRD64mrCL i64mem:$mem, GR64:$reg)>;
2026 /* FIXME: This is disabled because the asm matcher is currently incapable of
2027 * matching a fixed immediate like $1.
2028 // "shl X, $1" is an alias for "shl X".
2029 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
2030 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2031 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
2032 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2033 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
2034 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2035 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
2036 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2037 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
2038 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2039 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
2040 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2041 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
2042 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2043 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
2044 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2045 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2048 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2049 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
2050 defm : ShiftRotateByOneAlias<"rol", "ROL">;
2051 defm : ShiftRotateByOneAlias<"ror", "ROR">;
2054 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
2055 def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>;
2056 def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>;
2057 def : InstAlias<"testl $val, $mem", (TEST32rm GR32:$val, i32mem:$mem)>;
2058 def : InstAlias<"testq $val, $mem", (TEST64rm GR64:$val, i64mem:$mem)>;
2060 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
2061 def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>;
2062 def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>;
2063 def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>;
2064 def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>;
2066 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
2067 def : InstAlias<"xchgw %ax, $src", (XCHG16ar GR16:$src)>;
2068 def : InstAlias<"xchgl %eax, $src", (XCHG32ar GR32:$src)>, Requires<[In32BitMode]>;
2069 def : InstAlias<"xchgl %eax, $src", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
2070 def : InstAlias<"xchgq %rax, $src", (XCHG64ar GR64:$src)>;