1 //===----------------------------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
32 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
34 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTX86BrCond : SDTypeProfile<0, 3,
39 [SDTCisVT<0, OtherVT>,
40 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
42 def SDTX86SetCC : SDTypeProfile<1, 2,
44 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86SetCC_C : SDTypeProfile<1, 2,
47 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
49 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
51 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
53 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
54 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
55 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
57 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
58 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
61 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
63 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
67 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
69 def SDTX86Void : SDTypeProfile<0, 0, []>;
71 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
73 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
75 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
77 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
79 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
81 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
82 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
83 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
84 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
86 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
87 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
89 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
90 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
92 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
93 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
95 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
96 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
98 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
99 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
101 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
102 [SDNPHasChain, SDNPMayStore,
103 SDNPMayLoad, SDNPMemOperand]>;
104 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
105 [SDNPHasChain, SDNPMayStore,
106 SDNPMayLoad, SDNPMemOperand]>;
107 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
108 [SDNPHasChain, SDNPMayStore,
109 SDNPMayLoad, SDNPMemOperand]>;
110 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
111 [SDNPHasChain, SDNPMayStore,
112 SDNPMayLoad, SDNPMemOperand]>;
113 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
114 [SDNPHasChain, SDNPMayStore,
115 SDNPMayLoad, SDNPMemOperand]>;
116 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
117 [SDNPHasChain, SDNPMayStore,
118 SDNPMayLoad, SDNPMemOperand]>;
119 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
120 [SDNPHasChain, SDNPMayStore,
121 SDNPMayLoad, SDNPMemOperand]>;
122 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
123 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
125 def X86vastart_save_xmm_regs :
126 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
127 SDT_X86VASTART_SAVE_XMM_REGS,
128 [SDNPHasChain, SDNPVariadic]>;
130 def X86callseq_start :
131 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
132 [SDNPHasChain, SDNPOutFlag]>;
134 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
135 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
137 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
138 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
141 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
142 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
143 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
144 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
147 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
148 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
150 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
151 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
153 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
154 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
155 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
156 SDT_X86SegmentBaseAddress, []>;
158 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
161 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
162 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
164 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
166 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
167 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
169 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
172 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
173 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
174 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
176 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
178 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
181 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
183 def X86MingwAlloca : SDNode<"X86ISD::MINGW_ALLOCA", SDTX86Void,
184 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
186 //===----------------------------------------------------------------------===//
187 // X86 Operand Definitions.
190 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
191 // the index operand of an address, to conform to x86 encoding restrictions.
192 def ptr_rc_nosp : PointerLikeRegClass<1>;
194 // *mem - Operand definitions for the funky X86 addressing mode operands.
196 def X86MemAsmOperand : AsmOperandClass {
200 def X86AbsMemAsmOperand : AsmOperandClass {
202 let SuperClass = X86MemAsmOperand;
204 def X86NoSegMemAsmOperand : AsmOperandClass {
205 let Name = "NoSegMem";
206 let SuperClass = X86MemAsmOperand;
208 class X86MemOperand<string printMethod> : Operand<iPTR> {
209 let PrintMethod = printMethod;
210 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
211 let ParserMatchClass = X86MemAsmOperand;
214 def opaque32mem : X86MemOperand<"printopaquemem">;
215 def opaque48mem : X86MemOperand<"printopaquemem">;
216 def opaque80mem : X86MemOperand<"printopaquemem">;
217 def opaque512mem : X86MemOperand<"printopaquemem">;
219 def i8mem : X86MemOperand<"printi8mem">;
220 def i16mem : X86MemOperand<"printi16mem">;
221 def i32mem : X86MemOperand<"printi32mem">;
222 def i64mem : X86MemOperand<"printi64mem">;
223 def i128mem : X86MemOperand<"printi128mem">;
224 //def i256mem : X86MemOperand<"printi256mem">;
225 def f32mem : X86MemOperand<"printf32mem">;
226 def f64mem : X86MemOperand<"printf64mem">;
227 def f80mem : X86MemOperand<"printf80mem">;
228 def f128mem : X86MemOperand<"printf128mem">;
229 //def f256mem : X86MemOperand<"printf256mem">;
231 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
232 // plain GR64, so that it doesn't potentially require a REX prefix.
233 def i8mem_NOREX : Operand<i64> {
234 let PrintMethod = "printi8mem";
235 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
236 let ParserMatchClass = X86MemAsmOperand;
239 // Special i32mem for addresses of load folding tail calls. These are not
240 // allowed to use callee-saved registers since they must be scheduled
241 // after callee-saved register are popped.
242 def i32mem_TC : Operand<i32> {
243 let PrintMethod = "printi32mem";
244 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
245 let ParserMatchClass = X86MemAsmOperand;
248 def lea32mem : Operand<i32> {
249 let PrintMethod = "printlea32mem";
250 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
251 let ParserMatchClass = X86NoSegMemAsmOperand;
254 let ParserMatchClass = X86AbsMemAsmOperand,
255 PrintMethod = "print_pcrel_imm" in {
256 def i32imm_pcrel : Operand<i32>;
258 def offset8 : Operand<i64>;
259 def offset16 : Operand<i64>;
260 def offset32 : Operand<i64>;
261 def offset64 : Operand<i64>;
263 // Branch targets have OtherVT type and print as pc-relative values.
264 def brtarget : Operand<OtherVT>;
265 def brtarget8 : Operand<OtherVT>;
269 def SSECC : Operand<i8> {
270 let PrintMethod = "printSSECC";
273 def ImmSExt8AsmOperand : AsmOperandClass {
274 let Name = "ImmSExt8";
275 let SuperClass = ImmAsmOperand;
278 // A couple of more descriptive operand definitions.
279 // 16-bits but only 8 bits are significant.
280 def i16i8imm : Operand<i16> {
281 let ParserMatchClass = ImmSExt8AsmOperand;
283 // 32-bits but only 8 bits are significant.
284 def i32i8imm : Operand<i32> {
285 let ParserMatchClass = ImmSExt8AsmOperand;
288 //===----------------------------------------------------------------------===//
289 // X86 Complex Pattern Definitions.
292 // Define X86 specific addressing mode.
293 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
294 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
295 [add, sub, mul, X86mul_imm, shl, or, frameindex],
297 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
298 [tglobaltlsaddr], []>;
300 //===----------------------------------------------------------------------===//
301 // X86 Instruction Predicate Definitions.
302 def HasCMov : Predicate<"Subtarget->hasCMov()">;
303 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
304 def HasMMX : Predicate<"Subtarget->hasMMX()">;
305 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
306 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
307 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
308 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
309 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
310 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
311 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
312 def HasAVX : Predicate<"Subtarget->hasAVX()">;
313 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
314 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
315 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
316 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
317 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
318 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
319 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
320 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
321 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
322 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
323 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
324 "TM.getCodeModel() != CodeModel::Kernel">;
325 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
326 "TM.getCodeModel() == CodeModel::Kernel">;
327 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
328 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
329 def OptForSize : Predicate<"OptForSize">;
330 def OptForSpeed : Predicate<"!OptForSize">;
331 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
332 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
333 def HasAES : Predicate<"Subtarget->hasAES()">;
335 //===----------------------------------------------------------------------===//
336 // X86 Instruction Format Definitions.
339 include "X86InstrFormats.td"
341 //===----------------------------------------------------------------------===//
342 // Pattern fragments...
345 // X86 specific condition code. These correspond to CondCode in
346 // X86InstrInfo.h. They must be kept in synch.
347 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
348 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
349 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
350 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
351 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
352 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
353 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
354 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
355 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
356 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
357 def X86_COND_NO : PatLeaf<(i8 10)>;
358 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
359 def X86_COND_NS : PatLeaf<(i8 12)>;
360 def X86_COND_O : PatLeaf<(i8 13)>;
361 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
362 def X86_COND_S : PatLeaf<(i8 15)>;
364 def immSext8 : PatLeaf<(imm), [{
365 return N->getSExtValue() == (int8_t)N->getSExtValue();
368 def i16immSExt8 : PatLeaf<(i16 immSext8)>;
369 def i32immSExt8 : PatLeaf<(i32 immSext8)>;
371 /// Load patterns: these constraint the match to the right address space.
372 def dsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
373 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
374 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
375 if (PT->getAddressSpace() > 255)
380 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
381 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
382 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
383 return PT->getAddressSpace() == 256;
387 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
388 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
389 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
390 return PT->getAddressSpace() == 257;
395 // Helper fragments for loads.
396 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
397 // known to be 32-bit aligned or better. Ditto for i8 to i16.
398 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
399 LoadSDNode *LD = cast<LoadSDNode>(N);
400 if (const Value *Src = LD->getSrcValue())
401 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
402 if (PT->getAddressSpace() > 255)
404 ISD::LoadExtType ExtType = LD->getExtensionType();
405 if (ExtType == ISD::NON_EXTLOAD)
407 if (ExtType == ISD::EXTLOAD)
408 return LD->getAlignment() >= 2 && !LD->isVolatile();
412 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
413 LoadSDNode *LD = cast<LoadSDNode>(N);
414 if (const Value *Src = LD->getSrcValue())
415 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
416 if (PT->getAddressSpace() > 255)
418 ISD::LoadExtType ExtType = LD->getExtensionType();
419 if (ExtType == ISD::EXTLOAD)
420 return LD->getAlignment() >= 2 && !LD->isVolatile();
424 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
425 LoadSDNode *LD = cast<LoadSDNode>(N);
426 if (const Value *Src = LD->getSrcValue())
427 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
428 if (PT->getAddressSpace() > 255)
430 ISD::LoadExtType ExtType = LD->getExtensionType();
431 if (ExtType == ISD::NON_EXTLOAD)
433 if (ExtType == ISD::EXTLOAD)
434 return LD->getAlignment() >= 4 && !LD->isVolatile();
438 def loadi8 : PatFrag<(ops node:$ptr), (i8 (dsload node:$ptr))>;
439 def loadi64 : PatFrag<(ops node:$ptr), (i64 (dsload node:$ptr))>;
440 def loadf32 : PatFrag<(ops node:$ptr), (f32 (dsload node:$ptr))>;
441 def loadf64 : PatFrag<(ops node:$ptr), (f64 (dsload node:$ptr))>;
442 def loadf80 : PatFrag<(ops node:$ptr), (f80 (dsload node:$ptr))>;
444 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
445 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
446 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
448 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
449 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
450 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
451 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
452 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
453 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
455 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
456 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
457 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
458 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
459 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
460 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
463 // An 'and' node with a single use.
464 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
465 return N->hasOneUse();
467 // An 'srl' node with a single use.
468 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
469 return N->hasOneUse();
471 // An 'trunc' node with a single use.
472 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
473 return N->hasOneUse();
476 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
477 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
478 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
479 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
481 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
482 APInt Mask = APInt::getAllOnesValue(BitWidth);
483 APInt KnownZero0, KnownOne0;
484 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
485 APInt KnownZero1, KnownOne1;
486 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
487 return (~KnownZero0 & ~KnownZero1) == 0;
490 //===----------------------------------------------------------------------===//
491 // Instruction list...
494 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
495 // a stack adjustment and the codegen must know that they may modify the stack
496 // pointer before prolog-epilog rewriting occurs.
497 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
498 // sub / add which can clobber EFLAGS.
499 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
500 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
502 [(X86callseq_start timm:$amt)]>,
503 Requires<[In32BitMode]>;
504 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
506 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
507 Requires<[In32BitMode]>;
510 // x86-64 va_start lowering magic.
511 let usesCustomInserter = 1 in {
512 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
515 i64imm:$regsavefi, i64imm:$offset,
517 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
518 [(X86vastart_save_xmm_regs GR8:$al,
522 // Dynamic stack allocation yields _alloca call for Cygwin/Mingw targets. Calls
523 // to _alloca is needed to probe the stack when allocating more than 4k bytes in
524 // one go. Touching the stack at 4K increments is necessary to ensure that the
525 // guard pages used by the OS virtual memory manager are allocated in correct
527 // The main point of having separate instruction are extra unmodelled effects
528 // (compared to ordinary calls) like stack pointer change.
530 def MINGW_ALLOCA : I<0, Pseudo, (outs), (ins),
531 "# dynamic stack allocation",
536 let neverHasSideEffects = 1 in {
537 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
538 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
539 "nop{w}\t$zero", []>, TB, OpSize;
540 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
541 "nop{l}\t$zero", []>, TB;
545 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int\t3", []>;
546 def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
547 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize;
548 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>;
550 // PIC base construction. This expands to code that looks like this:
553 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
554 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
557 //===----------------------------------------------------------------------===//
558 // Control Flow Instructions.
561 // Return instructions.
562 let isTerminator = 1, isReturn = 1, isBarrier = 1,
563 hasCtrlDep = 1, FPForm = SpecialFP in {
564 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
567 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
569 [(X86retflag timm:$amt)]>;
570 def LRET : I <0xCB, RawFrm, (outs), (ins),
572 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
576 // Unconditional branches.
577 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
578 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
579 "jmp\t$dst", [(br bb:$dst)]>;
580 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
584 // Conditional Branches.
585 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
586 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
587 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
588 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
589 [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
593 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
594 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
595 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
596 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
597 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
598 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
599 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
600 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
601 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
602 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
603 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
604 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
605 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
606 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
607 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
608 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
610 // FIXME: What about the CX/RCX versions of this instruction?
611 let Uses = [ECX], isBranch = 1, isTerminator = 1 in
612 def JCXZ8 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
617 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
618 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
619 [(brind GR32:$dst)]>;
620 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
621 [(brind (loadi32 addr:$dst))]>;
623 def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
624 (ins i16imm:$seg, i16imm:$off),
625 "ljmp{w}\t$seg, $off", []>, OpSize;
626 def FARJMP32i : Iseg32<0xEA, RawFrm, (outs),
627 (ins i16imm:$seg, i32imm:$off),
628 "ljmp{l}\t$seg, $off", []>;
630 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
631 "ljmp{w}\t{*}$dst", []>, OpSize;
632 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
633 "ljmp{l}\t{*}$dst", []>;
639 def LOOP : I<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>;
640 def LOOPE : I<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>;
641 def LOOPNE : I<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>;
643 //===----------------------------------------------------------------------===//
644 // Call Instructions...
647 // All calls clobber the non-callee saved registers. ESP is marked as
648 // a use to prevent stack-pointer assignments that appear immediately
649 // before calls from potentially appearing dead. Uses for argument
650 // registers are added manually.
651 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
652 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
653 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
654 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
656 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
657 (outs), (ins i32imm_pcrel:$dst,variable_ops),
659 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
660 "call\t{*}$dst", [(X86call GR32:$dst)]>;
661 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
662 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
664 def FARCALL16i : Iseg16<0x9A, RawFrm, (outs),
665 (ins i16imm:$seg, i16imm:$off),
666 "lcall{w}\t$seg, $off", []>, OpSize;
667 def FARCALL32i : Iseg32<0x9A, RawFrm, (outs),
668 (ins i16imm:$seg, i32imm:$off),
669 "lcall{l}\t$seg, $off", []>;
671 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
672 "lcall{w}\t{*}$dst", []>, OpSize;
673 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
674 "lcall{l}\t{*}$dst", []>;
677 // Constructing a stack frame.
679 def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl),
680 "enter\t$len, $lvl", []>;
684 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
685 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
686 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
687 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
688 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
690 def TCRETURNdi : I<0, Pseudo, (outs),
691 (ins i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
692 "#TC_RETURN $dst $offset", []>;
693 def TCRETURNri : I<0, Pseudo, (outs),
694 (ins GR32_TC:$dst, i32imm:$offset, variable_ops),
695 "#TC_RETURN $dst $offset", []>;
696 def TCRETURNmi : I<0, Pseudo, (outs),
697 (ins i32mem_TC:$dst, i32imm:$offset, variable_ops),
698 "#TC_RETURN $dst $offset", []>;
700 // FIXME: The should be pseudo instructions that are lowered when going to
702 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
703 (ins i32imm_pcrel:$dst, variable_ops),
704 "jmp\t$dst # TAILCALL",
706 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops),
707 "jmp{l}\t{*}$dst # TAILCALL",
709 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops),
710 "jmp{l}\t{*}$dst # TAILCALL", []>;
713 //===----------------------------------------------------------------------===//
714 // Miscellaneous Instructions...
716 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
717 def LEAVE : I<0xC9, RawFrm,
718 (outs), (ins), "leave", []>;
720 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
721 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
722 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
723 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
724 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
725 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
726 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
727 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
729 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
731 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
733 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
734 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
736 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
738 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
739 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
742 let mayStore = 1 in {
743 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
745 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
746 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
748 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
750 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
751 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
755 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
756 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
757 "push{l}\t$imm", []>;
758 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
759 "push{w}\t$imm", []>, OpSize;
760 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
761 "push{l}\t$imm", []>;
764 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
765 def POPF : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
766 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf{l}", []>;
768 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
769 def PUSHF : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
770 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf{l}", []>;
773 let isTwoAddress = 1 in // GR32 = bswap GR32
774 def BSWAP32r : I<0xC8, AddRegFrm,
775 (outs GR32:$dst), (ins GR32:$src),
777 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
780 // Bit scan instructions.
781 let Defs = [EFLAGS] in {
782 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
783 "bsf{w}\t{$src, $dst|$dst, $src}",
784 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
785 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
786 "bsf{w}\t{$src, $dst|$dst, $src}",
787 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
789 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
790 "bsf{l}\t{$src, $dst|$dst, $src}",
791 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
792 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
793 "bsf{l}\t{$src, $dst|$dst, $src}",
794 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
796 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
797 "bsr{w}\t{$src, $dst|$dst, $src}",
798 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
799 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
800 "bsr{w}\t{$src, $dst|$dst, $src}",
801 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
803 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
804 "bsr{l}\t{$src, $dst|$dst, $src}",
805 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
806 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
807 "bsr{l}\t{$src, $dst|$dst, $src}",
808 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
811 let neverHasSideEffects = 1 in
812 def LEA16r : I<0x8D, MRMSrcMem,
813 (outs GR16:$dst), (ins lea32mem:$src),
814 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
815 let isReMaterializable = 1 in
816 def LEA32r : I<0x8D, MRMSrcMem,
817 (outs GR32:$dst), (ins lea32mem:$src),
818 "lea{l}\t{$src|$dst}, {$dst|$src}",
819 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
821 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
822 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
823 [(X86rep_movs i8)]>, REP;
824 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
825 [(X86rep_movs i16)]>, REP, OpSize;
826 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
827 [(X86rep_movs i32)]>, REP;
830 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
831 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
832 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
833 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
834 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
837 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
838 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
839 [(X86rep_stos i8)]>, REP;
840 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
841 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
842 [(X86rep_stos i16)]>, REP, OpSize;
843 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
844 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
845 [(X86rep_stos i32)]>, REP;
847 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
848 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
849 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
850 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
851 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
852 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
853 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
855 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
856 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
857 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
859 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
860 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
861 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
863 let Defs = [RAX, RDX] in
864 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
867 let Defs = [RAX, RCX, RDX] in
868 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
870 let isBarrier = 1, hasCtrlDep = 1 in {
871 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
874 def SYSCALL : I<0x05, RawFrm,
875 (outs), (ins), "syscall", []>, TB;
876 def SYSRET : I<0x07, RawFrm,
877 (outs), (ins), "sysret", []>, TB;
878 def SYSENTER : I<0x34, RawFrm,
879 (outs), (ins), "sysenter", []>, TB;
880 def SYSEXIT : I<0x35, RawFrm,
881 (outs), (ins), "sysexit", []>, TB;
883 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
886 //===----------------------------------------------------------------------===//
887 // Input/Output Instructions...
889 let Defs = [AL], Uses = [DX] in
890 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
891 "in{b}\t{%dx, %al|%AL, %DX}", []>;
892 let Defs = [AX], Uses = [DX] in
893 def IN16rr : I<0xED, RawFrm, (outs), (ins),
894 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
895 let Defs = [EAX], Uses = [DX] in
896 def IN32rr : I<0xED, RawFrm, (outs), (ins),
897 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
900 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
901 "in{b}\t{$port, %al|%AL, $port}", []>;
903 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
904 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
906 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
907 "in{l}\t{$port, %eax|%EAX, $port}", []>;
909 let Uses = [DX, AL] in
910 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
911 "out{b}\t{%al, %dx|%DX, %AL}", []>;
912 let Uses = [DX, AX] in
913 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
914 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
915 let Uses = [DX, EAX] in
916 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
917 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
920 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
921 "out{b}\t{%al, $port|$port, %AL}", []>;
923 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
924 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
926 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
927 "out{l}\t{%eax, $port|$port, %EAX}", []>;
929 def IN8 : I<0x6C, RawFrm, (outs), (ins),
931 def IN16 : I<0x6D, RawFrm, (outs), (ins),
932 "ins{w}", []>, OpSize;
933 def IN32 : I<0x6D, RawFrm, (outs), (ins),
936 //===----------------------------------------------------------------------===//
937 // Move Instructions...
939 let neverHasSideEffects = 1 in {
940 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
941 "mov{b}\t{$src, $dst|$dst, $src}", []>;
942 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
943 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
944 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
945 "mov{l}\t{$src, $dst|$dst, $src}", []>;
947 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
948 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
949 "mov{b}\t{$src, $dst|$dst, $src}",
950 [(set GR8:$dst, imm:$src)]>;
951 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
952 "mov{w}\t{$src, $dst|$dst, $src}",
953 [(set GR16:$dst, imm:$src)]>, OpSize;
954 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
955 "mov{l}\t{$src, $dst|$dst, $src}",
956 [(set GR32:$dst, imm:$src)]>;
959 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
960 "mov{b}\t{$src, $dst|$dst, $src}",
961 [(store (i8 imm:$src), addr:$dst)]>;
962 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
963 "mov{w}\t{$src, $dst|$dst, $src}",
964 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
965 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
966 "mov{l}\t{$src, $dst|$dst, $src}",
967 [(store (i32 imm:$src), addr:$dst)]>;
969 def MOV8o8a : Ii8 <0xA0, RawFrm, (outs), (ins offset8:$src),
970 "mov{b}\t{$src, %al|%al, $src}", []>;
971 def MOV16o16a : Ii16 <0xA1, RawFrm, (outs), (ins offset16:$src),
972 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
973 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
974 "mov{l}\t{$src, %eax|%eax, $src}", []>;
976 def MOV8ao8 : Ii8 <0xA2, RawFrm, (outs offset8:$dst), (ins),
977 "mov{b}\t{%al, $dst|$dst, %al}", []>;
978 def MOV16ao16 : Ii16 <0xA3, RawFrm, (outs offset16:$dst), (ins),
979 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize;
980 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
981 "mov{l}\t{%eax, $dst|$dst, %eax}", []>;
983 // Moves to and from segment registers
984 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
985 "mov{w}\t{$src, $dst|$dst, $src}", []>;
986 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
987 "mov{w}\t{$src, $dst|$dst, $src}", []>;
988 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
989 "mov{w}\t{$src, $dst|$dst, $src}", []>;
990 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
991 "mov{w}\t{$src, $dst|$dst, $src}", []>;
993 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
994 "mov{b}\t{$src, $dst|$dst, $src}", []>;
995 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
996 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
997 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
998 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1000 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1001 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1002 "mov{b}\t{$src, $dst|$dst, $src}",
1003 [(set GR8:$dst, (loadi8 addr:$src))]>;
1004 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1005 "mov{w}\t{$src, $dst|$dst, $src}",
1006 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
1007 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1008 "mov{l}\t{$src, $dst|$dst, $src}",
1009 [(set GR32:$dst, (loadi32 addr:$src))]>;
1012 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1013 "mov{b}\t{$src, $dst|$dst, $src}",
1014 [(store GR8:$src, addr:$dst)]>;
1015 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1016 "mov{w}\t{$src, $dst|$dst, $src}",
1017 [(store GR16:$src, addr:$dst)]>, OpSize;
1018 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1019 "mov{l}\t{$src, $dst|$dst, $src}",
1020 [(store GR32:$src, addr:$dst)]>;
1022 /// Versions of MOV32rr, MOV32rm, and MOV32mr for i32mem_TC and GR32_TC.
1023 let neverHasSideEffects = 1 in
1024 def MOV32rr_TC : I<0x89, MRMDestReg, (outs GR32_TC:$dst), (ins GR32_TC:$src),
1025 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1028 canFoldAsLoad = 1, isReMaterializable = 1 in
1029 def MOV32rm_TC : I<0x8B, MRMSrcMem, (outs GR32_TC:$dst), (ins i32mem_TC:$src),
1030 "mov{l}\t{$src, $dst|$dst, $src}",
1034 def MOV32mr_TC : I<0x89, MRMDestMem, (outs), (ins i32mem_TC:$dst, GR32_TC:$src),
1035 "mov{l}\t{$src, $dst|$dst, $src}",
1038 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1039 // that they can be used for copying and storing h registers, which can't be
1040 // encoded when a REX prefix is present.
1041 let neverHasSideEffects = 1 in
1042 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1043 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1044 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1046 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1047 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1048 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1050 canFoldAsLoad = 1, isReMaterializable = 1 in
1051 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1052 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1053 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1055 // Moves to and from debug registers
1056 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
1057 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1058 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
1059 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1061 // Moves to and from control registers
1062 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG_32:$src),
1063 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1064 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_32:$dst), (ins GR32:$src),
1065 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1067 //===----------------------------------------------------------------------===//
1068 // Fixed-Register Multiplication and Division Instructions...
1071 // Extra precision multiplication
1073 // AL is really implied by AX, by the registers in Defs must match the
1074 // SDNode results (i8, i32).
1075 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1076 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
1077 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1078 // This probably ought to be moved to a def : Pat<> if the
1079 // syntax can be accepted.
1080 [(set AL, (mul AL, GR8:$src)),
1081 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1083 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1084 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1086 []>, OpSize; // AX,DX = AX*GR16
1088 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1089 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1091 []>; // EAX,EDX = EAX*GR32
1093 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1094 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1096 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1097 // This probably ought to be moved to a def : Pat<> if the
1098 // syntax can be accepted.
1099 [(set AL, (mul AL, (loadi8 addr:$src))),
1100 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1102 let mayLoad = 1, neverHasSideEffects = 1 in {
1103 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1104 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1106 []>, OpSize; // AX,DX = AX*[mem16]
1108 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1109 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1111 []>; // EAX,EDX = EAX*[mem32]
1114 let neverHasSideEffects = 1 in {
1115 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1116 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1118 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1119 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1120 OpSize; // AX,DX = AX*GR16
1121 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1122 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1123 // EAX,EDX = EAX*GR32
1124 let mayLoad = 1 in {
1125 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1126 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1127 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1128 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1129 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1130 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1131 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1132 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1133 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1135 } // neverHasSideEffects
1137 // unsigned division/remainder
1138 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1139 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1140 "div{b}\t$src", []>;
1141 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1142 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1143 "div{w}\t$src", []>, OpSize;
1144 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1145 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1146 "div{l}\t$src", []>;
1147 let mayLoad = 1 in {
1148 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1149 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1150 "div{b}\t$src", []>;
1151 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1152 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1153 "div{w}\t$src", []>, OpSize;
1154 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1155 // EDX:EAX/[mem32] = EAX,EDX
1156 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
1157 "div{l}\t$src", []>;
1160 // Signed division/remainder.
1161 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1162 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1163 "idiv{b}\t$src", []>;
1164 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1165 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1166 "idiv{w}\t$src", []>, OpSize;
1167 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1168 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1169 "idiv{l}\t$src", []>;
1170 let mayLoad = 1, mayLoad = 1 in {
1171 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1172 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1173 "idiv{b}\t$src", []>;
1174 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1175 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1176 "idiv{w}\t$src", []>, OpSize;
1177 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1178 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1179 // EDX:EAX/[mem32] = EAX,EDX
1180 "idiv{l}\t$src", []>;
1183 //===----------------------------------------------------------------------===//
1184 // Two address Instructions.
1186 let isTwoAddress = 1 in {
1188 // Conditional moves
1189 let Uses = [EFLAGS] in {
1191 let Predicates = [HasCMov] in {
1192 let isCommutable = 1 in {
1193 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1194 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1195 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1196 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1197 X86_COND_B, EFLAGS))]>,
1199 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1200 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1201 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1202 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1203 X86_COND_B, EFLAGS))]>,
1205 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1206 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1207 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1208 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1209 X86_COND_AE, EFLAGS))]>,
1211 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1212 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1213 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1214 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1215 X86_COND_AE, EFLAGS))]>,
1217 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1218 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1219 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1220 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1221 X86_COND_E, EFLAGS))]>,
1223 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1224 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1225 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1226 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1227 X86_COND_E, EFLAGS))]>,
1229 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1230 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1231 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1232 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1233 X86_COND_NE, EFLAGS))]>,
1235 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1236 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1237 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1238 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1239 X86_COND_NE, EFLAGS))]>,
1241 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1242 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1243 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1244 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1245 X86_COND_BE, EFLAGS))]>,
1247 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1248 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1249 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1250 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1251 X86_COND_BE, EFLAGS))]>,
1253 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1254 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1255 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1256 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1257 X86_COND_A, EFLAGS))]>,
1259 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1260 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1261 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1262 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1263 X86_COND_A, EFLAGS))]>,
1265 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1266 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1267 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1268 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1269 X86_COND_L, EFLAGS))]>,
1271 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1272 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1273 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1274 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1275 X86_COND_L, EFLAGS))]>,
1277 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1278 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1279 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1280 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1281 X86_COND_GE, EFLAGS))]>,
1283 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1284 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1285 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1286 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1287 X86_COND_GE, EFLAGS))]>,
1289 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1290 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1291 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1292 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1293 X86_COND_LE, EFLAGS))]>,
1295 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1296 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1297 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1298 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1299 X86_COND_LE, EFLAGS))]>,
1301 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1302 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1303 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1304 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1305 X86_COND_G, EFLAGS))]>,
1307 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1308 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1309 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1310 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1311 X86_COND_G, EFLAGS))]>,
1313 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1314 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1315 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1316 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1317 X86_COND_S, EFLAGS))]>,
1319 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1320 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1321 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1322 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1323 X86_COND_S, EFLAGS))]>,
1325 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1326 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1327 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1328 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1329 X86_COND_NS, EFLAGS))]>,
1331 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1332 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1333 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1334 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1335 X86_COND_NS, EFLAGS))]>,
1337 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1338 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1339 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1340 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1341 X86_COND_P, EFLAGS))]>,
1343 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1344 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1345 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1346 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1347 X86_COND_P, EFLAGS))]>,
1349 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1350 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1351 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1352 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1353 X86_COND_NP, EFLAGS))]>,
1355 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1356 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1357 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1358 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1359 X86_COND_NP, EFLAGS))]>,
1361 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1362 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1363 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1364 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1365 X86_COND_O, EFLAGS))]>,
1367 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1368 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1369 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1370 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1371 X86_COND_O, EFLAGS))]>,
1373 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1374 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1375 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1376 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1377 X86_COND_NO, EFLAGS))]>,
1379 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1380 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1381 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1382 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1383 X86_COND_NO, EFLAGS))]>,
1385 } // isCommutable = 1
1387 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1388 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1389 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1390 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1391 X86_COND_B, EFLAGS))]>,
1393 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1394 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1395 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1396 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1397 X86_COND_B, EFLAGS))]>,
1399 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1400 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1401 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1402 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1403 X86_COND_AE, EFLAGS))]>,
1405 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1406 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1407 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1408 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1409 X86_COND_AE, EFLAGS))]>,
1411 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1412 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1413 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1414 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1415 X86_COND_E, EFLAGS))]>,
1417 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1418 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1419 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1420 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1421 X86_COND_E, EFLAGS))]>,
1423 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1424 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1425 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1426 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1427 X86_COND_NE, EFLAGS))]>,
1429 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1430 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1431 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1432 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1433 X86_COND_NE, EFLAGS))]>,
1435 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1436 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1437 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1438 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1439 X86_COND_BE, EFLAGS))]>,
1441 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1442 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1443 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1444 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1445 X86_COND_BE, EFLAGS))]>,
1447 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1448 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1449 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1450 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1451 X86_COND_A, EFLAGS))]>,
1453 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1454 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1455 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1456 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1457 X86_COND_A, EFLAGS))]>,
1459 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1460 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1461 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1462 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1463 X86_COND_L, EFLAGS))]>,
1465 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1466 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1467 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1468 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1469 X86_COND_L, EFLAGS))]>,
1471 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1472 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1473 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1474 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1475 X86_COND_GE, EFLAGS))]>,
1477 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1478 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1479 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1480 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1481 X86_COND_GE, EFLAGS))]>,
1483 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1484 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1485 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1486 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1487 X86_COND_LE, EFLAGS))]>,
1489 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1490 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1491 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1492 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1493 X86_COND_LE, EFLAGS))]>,
1495 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1496 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1497 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1498 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1499 X86_COND_G, EFLAGS))]>,
1501 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1502 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1503 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1504 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1505 X86_COND_G, EFLAGS))]>,
1507 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1508 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1509 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1510 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1511 X86_COND_S, EFLAGS))]>,
1513 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1514 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1515 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1516 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1517 X86_COND_S, EFLAGS))]>,
1519 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1520 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1521 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1522 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1523 X86_COND_NS, EFLAGS))]>,
1525 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1526 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1527 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1528 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1529 X86_COND_NS, EFLAGS))]>,
1531 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1532 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1533 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1534 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1535 X86_COND_P, EFLAGS))]>,
1537 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1538 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1539 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1540 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1541 X86_COND_P, EFLAGS))]>,
1543 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1544 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1545 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1546 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1547 X86_COND_NP, EFLAGS))]>,
1549 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1550 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1551 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1552 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1553 X86_COND_NP, EFLAGS))]>,
1555 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1556 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1557 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1558 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1559 X86_COND_O, EFLAGS))]>,
1561 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1562 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1563 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1564 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1565 X86_COND_O, EFLAGS))]>,
1567 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1568 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1569 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1570 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1571 X86_COND_NO, EFLAGS))]>,
1573 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1574 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1575 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1576 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1577 X86_COND_NO, EFLAGS))]>,
1579 } // Predicates = [HasCMov]
1581 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1582 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1583 // however that requires promoting the operands, and can induce additional
1584 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1585 // clobber EFLAGS, because if one of the operands is zero, the expansion
1586 // could involve an xor.
1587 let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in {
1588 def CMOV_GR8 : I<0, Pseudo,
1589 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1590 "#CMOV_GR8 PSEUDO!",
1591 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1592 imm:$cond, EFLAGS))]>;
1594 let Predicates = [NoCMov] in {
1595 def CMOV_GR32 : I<0, Pseudo,
1596 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
1597 "#CMOV_GR32* PSEUDO!",
1599 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
1600 def CMOV_GR16 : I<0, Pseudo,
1601 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
1602 "#CMOV_GR16* PSEUDO!",
1604 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
1605 def CMOV_RFP32 : I<0, Pseudo,
1606 (outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
1607 "#CMOV_RFP32 PSEUDO!",
1608 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
1610 def CMOV_RFP64 : I<0, Pseudo,
1611 (outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
1612 "#CMOV_RFP64 PSEUDO!",
1613 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
1615 def CMOV_RFP80 : I<0, Pseudo,
1616 (outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
1617 "#CMOV_RFP80 PSEUDO!",
1618 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
1620 } // Predicates = [NoCMov]
1621 } // UsesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS]
1622 } // Uses = [EFLAGS]
1625 // unary instructions
1626 let CodeSize = 2 in {
1627 let Defs = [EFLAGS] in {
1628 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1629 [(set GR8:$dst, (ineg GR8:$src)),
1630 (implicit EFLAGS)]>;
1631 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1632 [(set GR16:$dst, (ineg GR16:$src)),
1633 (implicit EFLAGS)]>, OpSize;
1634 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1635 [(set GR32:$dst, (ineg GR32:$src)),
1636 (implicit EFLAGS)]>;
1637 let isTwoAddress = 0 in {
1638 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1639 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1640 (implicit EFLAGS)]>;
1641 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1642 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1643 (implicit EFLAGS)]>, OpSize;
1644 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1645 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1646 (implicit EFLAGS)]>;
1648 } // Defs = [EFLAGS]
1650 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1651 let AddedComplexity = 15 in {
1652 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1653 [(set GR8:$dst, (not GR8:$src))]>;
1654 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1655 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1656 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1657 [(set GR32:$dst, (not GR32:$src))]>;
1659 let isTwoAddress = 0 in {
1660 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1661 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1662 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1663 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1664 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1665 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1669 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1670 let Defs = [EFLAGS] in {
1672 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1673 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src))]>;
1675 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1676 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1678 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src))]>,
1679 OpSize, Requires<[In32BitMode]>;
1680 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1682 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src))]>,
1683 Requires<[In32BitMode]>;
1685 let isTwoAddress = 0, CodeSize = 2 in {
1686 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1687 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1688 (implicit EFLAGS)]>;
1689 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1690 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1691 (implicit EFLAGS)]>,
1692 OpSize, Requires<[In32BitMode]>;
1693 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1694 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1695 (implicit EFLAGS)]>,
1696 Requires<[In32BitMode]>;
1700 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1701 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src))]>;
1702 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1703 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1705 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src))]>,
1706 OpSize, Requires<[In32BitMode]>;
1707 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1709 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src))]>,
1710 Requires<[In32BitMode]>;
1713 let isTwoAddress = 0, CodeSize = 2 in {
1714 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1715 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1716 (implicit EFLAGS)]>;
1717 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1718 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1719 (implicit EFLAGS)]>,
1720 OpSize, Requires<[In32BitMode]>;
1721 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1722 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1723 (implicit EFLAGS)]>,
1724 Requires<[In32BitMode]>;
1726 } // Defs = [EFLAGS]
1728 // Logical operators...
1729 let Defs = [EFLAGS] in {
1730 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1731 def AND8rr : I<0x20, MRMDestReg,
1732 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1733 "and{b}\t{$src2, $dst|$dst, $src2}",
1734 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, GR8:$src2))]>;
1735 def AND16rr : I<0x21, MRMDestReg,
1736 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1737 "and{w}\t{$src2, $dst|$dst, $src2}",
1738 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1739 GR16:$src2))]>, OpSize;
1740 def AND32rr : I<0x21, MRMDestReg,
1741 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1742 "and{l}\t{$src2, $dst|$dst, $src2}",
1743 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1747 // AND instructions with the destination register in REG and the source register
1748 // in R/M. Included for the disassembler.
1749 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1750 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1751 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1752 (ins GR16:$src1, GR16:$src2),
1753 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1754 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1755 (ins GR32:$src1, GR32:$src2),
1756 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1758 def AND8rm : I<0x22, MRMSrcMem,
1759 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1760 "and{b}\t{$src2, $dst|$dst, $src2}",
1761 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1762 (loadi8 addr:$src2)))]>;
1763 def AND16rm : I<0x23, MRMSrcMem,
1764 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1765 "and{w}\t{$src2, $dst|$dst, $src2}",
1766 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1767 (loadi16 addr:$src2)))]>,
1769 def AND32rm : I<0x23, MRMSrcMem,
1770 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1771 "and{l}\t{$src2, $dst|$dst, $src2}",
1772 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1773 (loadi32 addr:$src2)))]>;
1775 def AND8ri : Ii8<0x80, MRM4r,
1776 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1777 "and{b}\t{$src2, $dst|$dst, $src2}",
1778 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1780 def AND16ri : Ii16<0x81, MRM4r,
1781 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1782 "and{w}\t{$src2, $dst|$dst, $src2}",
1783 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1784 imm:$src2))]>, OpSize;
1785 def AND32ri : Ii32<0x81, MRM4r,
1786 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1787 "and{l}\t{$src2, $dst|$dst, $src2}",
1788 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1790 def AND16ri8 : Ii8<0x83, MRM4r,
1791 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1792 "and{w}\t{$src2, $dst|$dst, $src2}",
1793 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1794 i16immSExt8:$src2))]>,
1796 def AND32ri8 : Ii8<0x83, MRM4r,
1797 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1798 "and{l}\t{$src2, $dst|$dst, $src2}",
1799 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1800 i32immSExt8:$src2))]>;
1802 let isTwoAddress = 0 in {
1803 def AND8mr : I<0x20, MRMDestMem,
1804 (outs), (ins i8mem :$dst, GR8 :$src),
1805 "and{b}\t{$src, $dst|$dst, $src}",
1806 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1807 (implicit EFLAGS)]>;
1808 def AND16mr : I<0x21, MRMDestMem,
1809 (outs), (ins i16mem:$dst, GR16:$src),
1810 "and{w}\t{$src, $dst|$dst, $src}",
1811 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1812 (implicit EFLAGS)]>,
1814 def AND32mr : I<0x21, MRMDestMem,
1815 (outs), (ins i32mem:$dst, GR32:$src),
1816 "and{l}\t{$src, $dst|$dst, $src}",
1817 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1818 (implicit EFLAGS)]>;
1819 def AND8mi : Ii8<0x80, MRM4m,
1820 (outs), (ins i8mem :$dst, i8imm :$src),
1821 "and{b}\t{$src, $dst|$dst, $src}",
1822 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1823 (implicit EFLAGS)]>;
1824 def AND16mi : Ii16<0x81, MRM4m,
1825 (outs), (ins i16mem:$dst, i16imm:$src),
1826 "and{w}\t{$src, $dst|$dst, $src}",
1827 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1828 (implicit EFLAGS)]>,
1830 def AND32mi : Ii32<0x81, MRM4m,
1831 (outs), (ins i32mem:$dst, i32imm:$src),
1832 "and{l}\t{$src, $dst|$dst, $src}",
1833 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1834 (implicit EFLAGS)]>;
1835 def AND16mi8 : Ii8<0x83, MRM4m,
1836 (outs), (ins i16mem:$dst, i16i8imm :$src),
1837 "and{w}\t{$src, $dst|$dst, $src}",
1838 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1839 (implicit EFLAGS)]>,
1841 def AND32mi8 : Ii8<0x83, MRM4m,
1842 (outs), (ins i32mem:$dst, i32i8imm :$src),
1843 "and{l}\t{$src, $dst|$dst, $src}",
1844 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1845 (implicit EFLAGS)]>;
1847 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1848 "and{b}\t{$src, %al|%al, $src}", []>;
1849 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1850 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1851 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1852 "and{l}\t{$src, %eax|%eax, $src}", []>;
1857 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1858 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1859 (ins GR8 :$src1, GR8 :$src2),
1860 "or{b}\t{$src2, $dst|$dst, $src2}",
1861 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
1862 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1863 (ins GR16:$src1, GR16:$src2),
1864 "or{w}\t{$src2, $dst|$dst, $src2}",
1865 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
1867 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1868 (ins GR32:$src1, GR32:$src2),
1869 "or{l}\t{$src2, $dst|$dst, $src2}",
1870 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
1873 // OR instructions with the destination register in REG and the source register
1874 // in R/M. Included for the disassembler.
1875 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1876 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1877 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1878 (ins GR16:$src1, GR16:$src2),
1879 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1880 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1881 (ins GR32:$src1, GR32:$src2),
1882 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
1884 def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst),
1885 (ins GR8 :$src1, i8mem :$src2),
1886 "or{b}\t{$src2, $dst|$dst, $src2}",
1887 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
1888 (load addr:$src2)))]>;
1889 def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst),
1890 (ins GR16:$src1, i16mem:$src2),
1891 "or{w}\t{$src2, $dst|$dst, $src2}",
1892 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1893 (load addr:$src2)))]>,
1895 def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst),
1896 (ins GR32:$src1, i32mem:$src2),
1897 "or{l}\t{$src2, $dst|$dst, $src2}",
1898 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1899 (load addr:$src2)))]>;
1901 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
1902 (ins GR8 :$src1, i8imm:$src2),
1903 "or{b}\t{$src2, $dst|$dst, $src2}",
1904 [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
1905 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
1906 (ins GR16:$src1, i16imm:$src2),
1907 "or{w}\t{$src2, $dst|$dst, $src2}",
1908 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1909 imm:$src2))]>, OpSize;
1910 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
1911 (ins GR32:$src1, i32imm:$src2),
1912 "or{l}\t{$src2, $dst|$dst, $src2}",
1913 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1916 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
1917 (ins GR16:$src1, i16i8imm:$src2),
1918 "or{w}\t{$src2, $dst|$dst, $src2}",
1919 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1920 i16immSExt8:$src2))]>, OpSize;
1921 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
1922 (ins GR32:$src1, i32i8imm:$src2),
1923 "or{l}\t{$src2, $dst|$dst, $src2}",
1924 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1925 i32immSExt8:$src2))]>;
1926 let isTwoAddress = 0 in {
1927 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1928 "or{b}\t{$src, $dst|$dst, $src}",
1929 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1930 (implicit EFLAGS)]>;
1931 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1932 "or{w}\t{$src, $dst|$dst, $src}",
1933 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1934 (implicit EFLAGS)]>, OpSize;
1935 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1936 "or{l}\t{$src, $dst|$dst, $src}",
1937 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1938 (implicit EFLAGS)]>;
1939 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1940 "or{b}\t{$src, $dst|$dst, $src}",
1941 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1942 (implicit EFLAGS)]>;
1943 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1944 "or{w}\t{$src, $dst|$dst, $src}",
1945 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1946 (implicit EFLAGS)]>,
1948 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1949 "or{l}\t{$src, $dst|$dst, $src}",
1950 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1951 (implicit EFLAGS)]>;
1952 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1953 "or{w}\t{$src, $dst|$dst, $src}",
1954 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1955 (implicit EFLAGS)]>,
1957 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1958 "or{l}\t{$src, $dst|$dst, $src}",
1959 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1960 (implicit EFLAGS)]>;
1962 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
1963 "or{b}\t{$src, %al|%al, $src}", []>;
1964 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
1965 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1966 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
1967 "or{l}\t{$src, %eax|%eax, $src}", []>;
1968 } // isTwoAddress = 0
1971 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1972 def XOR8rr : I<0x30, MRMDestReg,
1973 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1974 "xor{b}\t{$src2, $dst|$dst, $src2}",
1975 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
1977 def XOR16rr : I<0x31, MRMDestReg,
1978 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1979 "xor{w}\t{$src2, $dst|$dst, $src2}",
1980 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
1981 GR16:$src2))]>, OpSize;
1982 def XOR32rr : I<0x31, MRMDestReg,
1983 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1984 "xor{l}\t{$src2, $dst|$dst, $src2}",
1985 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
1987 } // isCommutable = 1
1989 // XOR instructions with the destination register in REG and the source register
1990 // in R/M. Included for the disassembler.
1991 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1992 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
1993 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
1994 (ins GR16:$src1, GR16:$src2),
1995 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1996 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
1997 (ins GR32:$src1, GR32:$src2),
1998 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
2000 def XOR8rm : I<0x32, MRMSrcMem,
2001 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
2002 "xor{b}\t{$src2, $dst|$dst, $src2}",
2003 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2004 (load addr:$src2)))]>;
2005 def XOR16rm : I<0x33, MRMSrcMem,
2006 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2007 "xor{w}\t{$src2, $dst|$dst, $src2}",
2008 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2009 (load addr:$src2)))]>,
2011 def XOR32rm : I<0x33, MRMSrcMem,
2012 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2013 "xor{l}\t{$src2, $dst|$dst, $src2}",
2014 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2015 (load addr:$src2)))]>;
2017 def XOR8ri : Ii8<0x80, MRM6r,
2018 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2019 "xor{b}\t{$src2, $dst|$dst, $src2}",
2020 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
2021 def XOR16ri : Ii16<0x81, MRM6r,
2022 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2023 "xor{w}\t{$src2, $dst|$dst, $src2}",
2024 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2025 imm:$src2))]>, OpSize;
2026 def XOR32ri : Ii32<0x81, MRM6r,
2027 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2028 "xor{l}\t{$src2, $dst|$dst, $src2}",
2029 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2031 def XOR16ri8 : Ii8<0x83, MRM6r,
2032 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2033 "xor{w}\t{$src2, $dst|$dst, $src2}",
2034 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2035 i16immSExt8:$src2))]>,
2037 def XOR32ri8 : Ii8<0x83, MRM6r,
2038 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2039 "xor{l}\t{$src2, $dst|$dst, $src2}",
2040 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2041 i32immSExt8:$src2))]>;
2043 let isTwoAddress = 0 in {
2044 def XOR8mr : I<0x30, MRMDestMem,
2045 (outs), (ins i8mem :$dst, GR8 :$src),
2046 "xor{b}\t{$src, $dst|$dst, $src}",
2047 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
2048 (implicit EFLAGS)]>;
2049 def XOR16mr : I<0x31, MRMDestMem,
2050 (outs), (ins i16mem:$dst, GR16:$src),
2051 "xor{w}\t{$src, $dst|$dst, $src}",
2052 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
2053 (implicit EFLAGS)]>,
2055 def XOR32mr : I<0x31, MRMDestMem,
2056 (outs), (ins i32mem:$dst, GR32:$src),
2057 "xor{l}\t{$src, $dst|$dst, $src}",
2058 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
2059 (implicit EFLAGS)]>;
2060 def XOR8mi : Ii8<0x80, MRM6m,
2061 (outs), (ins i8mem :$dst, i8imm :$src),
2062 "xor{b}\t{$src, $dst|$dst, $src}",
2063 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
2064 (implicit EFLAGS)]>;
2065 def XOR16mi : Ii16<0x81, MRM6m,
2066 (outs), (ins i16mem:$dst, i16imm:$src),
2067 "xor{w}\t{$src, $dst|$dst, $src}",
2068 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
2069 (implicit EFLAGS)]>,
2071 def XOR32mi : Ii32<0x81, MRM6m,
2072 (outs), (ins i32mem:$dst, i32imm:$src),
2073 "xor{l}\t{$src, $dst|$dst, $src}",
2074 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
2075 (implicit EFLAGS)]>;
2076 def XOR16mi8 : Ii8<0x83, MRM6m,
2077 (outs), (ins i16mem:$dst, i16i8imm :$src),
2078 "xor{w}\t{$src, $dst|$dst, $src}",
2079 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
2080 (implicit EFLAGS)]>,
2082 def XOR32mi8 : Ii8<0x83, MRM6m,
2083 (outs), (ins i32mem:$dst, i32i8imm :$src),
2084 "xor{l}\t{$src, $dst|$dst, $src}",
2085 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
2086 (implicit EFLAGS)]>;
2088 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
2089 "xor{b}\t{$src, %al|%al, $src}", []>;
2090 def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
2091 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2092 def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
2093 "xor{l}\t{$src, %eax|%eax, $src}", []>;
2094 } // isTwoAddress = 0
2095 } // Defs = [EFLAGS]
2097 // Shift instructions
2098 let Defs = [EFLAGS] in {
2099 let Uses = [CL] in {
2100 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
2101 "shl{b}\t{%cl, $dst|$dst, CL}",
2102 [(set GR8:$dst, (shl GR8:$src, CL))]>;
2103 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
2104 "shl{w}\t{%cl, $dst|$dst, CL}",
2105 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
2106 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
2107 "shl{l}\t{%cl, $dst|$dst, CL}",
2108 [(set GR32:$dst, (shl GR32:$src, CL))]>;
2111 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2112 "shl{b}\t{$src2, $dst|$dst, $src2}",
2113 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
2114 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2115 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2116 "shl{w}\t{$src2, $dst|$dst, $src2}",
2117 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2118 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2119 "shl{l}\t{$src2, $dst|$dst, $src2}",
2120 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
2122 // NOTE: We don't include patterns for shifts of a register by one, because
2123 // 'add reg,reg' is cheaper.
2125 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
2126 "shl{b}\t$dst", []>;
2127 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2128 "shl{w}\t$dst", []>, OpSize;
2129 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2130 "shl{l}\t$dst", []>;
2132 } // isConvertibleToThreeAddress = 1
2134 let isTwoAddress = 0 in {
2135 let Uses = [CL] in {
2136 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
2137 "shl{b}\t{%cl, $dst|$dst, CL}",
2138 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
2139 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
2140 "shl{w}\t{%cl, $dst|$dst, CL}",
2141 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2142 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
2143 "shl{l}\t{%cl, $dst|$dst, CL}",
2144 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
2146 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
2147 "shl{b}\t{$src, $dst|$dst, $src}",
2148 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2149 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
2150 "shl{w}\t{$src, $dst|$dst, $src}",
2151 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2153 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
2154 "shl{l}\t{$src, $dst|$dst, $src}",
2155 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2158 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
2160 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2161 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
2163 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2165 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2167 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2170 let Uses = [CL] in {
2171 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
2172 "shr{b}\t{%cl, $dst|$dst, CL}",
2173 [(set GR8:$dst, (srl GR8:$src, CL))]>;
2174 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
2175 "shr{w}\t{%cl, $dst|$dst, CL}",
2176 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
2177 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
2178 "shr{l}\t{%cl, $dst|$dst, CL}",
2179 [(set GR32:$dst, (srl GR32:$src, CL))]>;
2182 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2183 "shr{b}\t{$src2, $dst|$dst, $src2}",
2184 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2185 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2186 "shr{w}\t{$src2, $dst|$dst, $src2}",
2187 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2188 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2189 "shr{l}\t{$src2, $dst|$dst, $src2}",
2190 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2193 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2195 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2196 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2198 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2199 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2201 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2203 let isTwoAddress = 0 in {
2204 let Uses = [CL] in {
2205 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2206 "shr{b}\t{%cl, $dst|$dst, CL}",
2207 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2208 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2209 "shr{w}\t{%cl, $dst|$dst, CL}",
2210 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2212 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2213 "shr{l}\t{%cl, $dst|$dst, CL}",
2214 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2216 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2217 "shr{b}\t{$src, $dst|$dst, $src}",
2218 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2219 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2220 "shr{w}\t{$src, $dst|$dst, $src}",
2221 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2223 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2224 "shr{l}\t{$src, $dst|$dst, $src}",
2225 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2228 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2230 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2231 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2233 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2234 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2236 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2239 let Uses = [CL] in {
2240 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
2241 "sar{b}\t{%cl, $dst|$dst, CL}",
2242 [(set GR8:$dst, (sra GR8:$src, CL))]>;
2243 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
2244 "sar{w}\t{%cl, $dst|$dst, CL}",
2245 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
2246 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
2247 "sar{l}\t{%cl, $dst|$dst, CL}",
2248 [(set GR32:$dst, (sra GR32:$src, CL))]>;
2251 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2252 "sar{b}\t{$src2, $dst|$dst, $src2}",
2253 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2254 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2255 "sar{w}\t{$src2, $dst|$dst, $src2}",
2256 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2258 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2259 "sar{l}\t{$src2, $dst|$dst, $src2}",
2260 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2263 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2265 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2266 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2268 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2269 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2271 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2273 let isTwoAddress = 0 in {
2274 let Uses = [CL] in {
2275 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2276 "sar{b}\t{%cl, $dst|$dst, CL}",
2277 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2278 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2279 "sar{w}\t{%cl, $dst|$dst, CL}",
2280 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2281 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2282 "sar{l}\t{%cl, $dst|$dst, CL}",
2283 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2285 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2286 "sar{b}\t{$src, $dst|$dst, $src}",
2287 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2288 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2289 "sar{w}\t{$src, $dst|$dst, $src}",
2290 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2292 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2293 "sar{l}\t{$src, $dst|$dst, $src}",
2294 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2297 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2299 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2300 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2302 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2304 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2306 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2309 // Rotate instructions
2311 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2312 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2313 let Uses = [CL] in {
2314 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2315 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2317 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2318 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2320 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2321 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2322 let Uses = [CL] in {
2323 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2324 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2326 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2327 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2329 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2330 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2331 let Uses = [CL] in {
2332 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2333 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2335 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2336 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2338 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2339 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2340 let Uses = [CL] in {
2341 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2342 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2344 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2345 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2347 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2348 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2349 let Uses = [CL] in {
2350 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2351 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2353 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2354 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2356 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2357 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2358 let Uses = [CL] in {
2359 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2360 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2362 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2363 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2365 let isTwoAddress = 0 in {
2366 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
2367 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2368 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2369 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2370 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
2371 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2372 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2373 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2374 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
2375 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2376 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2377 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2378 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
2379 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2380 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2381 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2382 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
2383 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2384 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2385 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2386 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
2387 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2388 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2389 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2391 let Uses = [CL] in {
2392 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
2393 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2394 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
2395 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2396 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
2397 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2398 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
2399 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2400 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
2401 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2402 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
2403 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2407 // FIXME: provide shorter instructions when imm8 == 1
2408 let Uses = [CL] in {
2409 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
2410 "rol{b}\t{%cl, $dst|$dst, CL}",
2411 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
2412 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
2413 "rol{w}\t{%cl, $dst|$dst, CL}",
2414 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
2415 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
2416 "rol{l}\t{%cl, $dst|$dst, CL}",
2417 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2420 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2421 "rol{b}\t{$src2, $dst|$dst, $src2}",
2422 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2423 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2424 "rol{w}\t{$src2, $dst|$dst, $src2}",
2425 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2427 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2428 "rol{l}\t{$src2, $dst|$dst, $src2}",
2429 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2432 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2434 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2435 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2437 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2438 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2440 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2442 let isTwoAddress = 0 in {
2443 let Uses = [CL] in {
2444 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2445 "rol{b}\t{%cl, $dst|$dst, CL}",
2446 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2447 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2448 "rol{w}\t{%cl, $dst|$dst, CL}",
2449 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2450 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2451 "rol{l}\t{%cl, $dst|$dst, CL}",
2452 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2454 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2455 "rol{b}\t{$src, $dst|$dst, $src}",
2456 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2457 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2458 "rol{w}\t{$src, $dst|$dst, $src}",
2459 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2461 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2462 "rol{l}\t{$src, $dst|$dst, $src}",
2463 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2466 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2468 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2469 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2471 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2473 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2475 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2478 let Uses = [CL] in {
2479 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2480 "ror{b}\t{%cl, $dst|$dst, CL}",
2481 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2482 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2483 "ror{w}\t{%cl, $dst|$dst, CL}",
2484 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2485 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2486 "ror{l}\t{%cl, $dst|$dst, CL}",
2487 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2490 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2491 "ror{b}\t{$src2, $dst|$dst, $src2}",
2492 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2493 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2494 "ror{w}\t{$src2, $dst|$dst, $src2}",
2495 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2497 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2498 "ror{l}\t{$src2, $dst|$dst, $src2}",
2499 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2502 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2504 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2505 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2507 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2508 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2510 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2512 let isTwoAddress = 0 in {
2513 let Uses = [CL] in {
2514 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2515 "ror{b}\t{%cl, $dst|$dst, CL}",
2516 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2517 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2518 "ror{w}\t{%cl, $dst|$dst, CL}",
2519 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2520 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2521 "ror{l}\t{%cl, $dst|$dst, CL}",
2522 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2524 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2525 "ror{b}\t{$src, $dst|$dst, $src}",
2526 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2527 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2528 "ror{w}\t{$src, $dst|$dst, $src}",
2529 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2531 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2532 "ror{l}\t{$src, $dst|$dst, $src}",
2533 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2536 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2538 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2539 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2541 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2543 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2545 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2550 // Double shift instructions (generalizations of rotate)
2551 let Uses = [CL] in {
2552 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2553 (ins GR32:$src1, GR32:$src2),
2554 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2555 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2556 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2557 (ins GR32:$src1, GR32:$src2),
2558 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2559 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2560 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2561 (ins GR16:$src1, GR16:$src2),
2562 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2563 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2565 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2566 (ins GR16:$src1, GR16:$src2),
2567 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2568 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2572 let isCommutable = 1 in { // These instructions commute to each other.
2573 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2575 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2576 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2577 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2580 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2582 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2583 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2584 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2587 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2589 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2590 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2591 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2594 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2596 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2597 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2598 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2603 let isTwoAddress = 0 in {
2604 let Uses = [CL] in {
2605 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2606 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2607 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2609 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2610 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2611 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2614 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2615 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2616 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2617 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2618 (i8 imm:$src3)), addr:$dst)]>,
2620 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2621 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2622 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2623 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2624 (i8 imm:$src3)), addr:$dst)]>,
2627 let Uses = [CL] in {
2628 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2629 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2630 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2631 addr:$dst)]>, TB, OpSize;
2632 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2633 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2634 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2635 addr:$dst)]>, TB, OpSize;
2637 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2638 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2639 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2640 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2641 (i8 imm:$src3)), addr:$dst)]>,
2643 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2644 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2645 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2646 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2647 (i8 imm:$src3)), addr:$dst)]>,
2650 } // Defs = [EFLAGS]
2654 let Defs = [EFLAGS] in {
2655 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2656 // Register-Register Addition
2657 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2658 (ins GR8 :$src1, GR8 :$src2),
2659 "add{b}\t{$src2, $dst|$dst, $src2}",
2660 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
2662 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2663 // Register-Register Addition
2664 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2665 (ins GR16:$src1, GR16:$src2),
2666 "add{w}\t{$src2, $dst|$dst, $src2}",
2667 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2668 GR16:$src2))]>, OpSize;
2669 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2670 (ins GR32:$src1, GR32:$src2),
2671 "add{l}\t{$src2, $dst|$dst, $src2}",
2672 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2674 } // end isConvertibleToThreeAddress
2675 } // end isCommutable
2677 // These are alternate spellings for use by the disassembler, we mark them as
2678 // code gen only to ensure they aren't matched by the assembler.
2679 let isCodeGenOnly = 1 in {
2680 def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2681 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2682 def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2683 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2684 def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR32:$dst),(ins GR32:$src1, GR32:$src2),
2685 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2688 // Register-Memory Addition
2689 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2690 (ins GR8 :$src1, i8mem :$src2),
2691 "add{b}\t{$src2, $dst|$dst, $src2}",
2692 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
2693 (load addr:$src2)))]>;
2694 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2695 (ins GR16:$src1, i16mem:$src2),
2696 "add{w}\t{$src2, $dst|$dst, $src2}",
2697 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2698 (load addr:$src2)))]>, OpSize;
2699 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2700 (ins GR32:$src1, i32mem:$src2),
2701 "add{l}\t{$src2, $dst|$dst, $src2}",
2702 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2703 (load addr:$src2)))]>;
2705 // Register-Integer Addition
2706 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2707 "add{b}\t{$src2, $dst|$dst, $src2}",
2708 [(set GR8:$dst, EFLAGS,
2709 (X86add_flag GR8:$src1, imm:$src2))]>;
2711 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2712 // Register-Integer Addition
2713 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2714 (ins GR16:$src1, i16imm:$src2),
2715 "add{w}\t{$src2, $dst|$dst, $src2}",
2716 [(set GR16:$dst, EFLAGS,
2717 (X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
2718 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2719 (ins GR32:$src1, i32imm:$src2),
2720 "add{l}\t{$src2, $dst|$dst, $src2}",
2721 [(set GR32:$dst, EFLAGS,
2722 (X86add_flag GR32:$src1, imm:$src2))]>;
2723 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2724 (ins GR16:$src1, i16i8imm:$src2),
2725 "add{w}\t{$src2, $dst|$dst, $src2}",
2726 [(set GR16:$dst, EFLAGS,
2727 (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2728 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2729 (ins GR32:$src1, i32i8imm:$src2),
2730 "add{l}\t{$src2, $dst|$dst, $src2}",
2731 [(set GR32:$dst, EFLAGS,
2732 (X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
2735 let isTwoAddress = 0 in {
2736 // Memory-Register Addition
2737 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2738 "add{b}\t{$src2, $dst|$dst, $src2}",
2739 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2740 (implicit EFLAGS)]>;
2741 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2742 "add{w}\t{$src2, $dst|$dst, $src2}",
2743 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2744 (implicit EFLAGS)]>, OpSize;
2745 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2746 "add{l}\t{$src2, $dst|$dst, $src2}",
2747 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2748 (implicit EFLAGS)]>;
2749 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2750 "add{b}\t{$src2, $dst|$dst, $src2}",
2751 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2752 (implicit EFLAGS)]>;
2753 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2754 "add{w}\t{$src2, $dst|$dst, $src2}",
2755 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2756 (implicit EFLAGS)]>, OpSize;
2757 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2758 "add{l}\t{$src2, $dst|$dst, $src2}",
2759 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2760 (implicit EFLAGS)]>;
2761 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2762 "add{w}\t{$src2, $dst|$dst, $src2}",
2763 [(store (add (load addr:$dst), i16immSExt8:$src2),
2765 (implicit EFLAGS)]>, OpSize;
2766 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2767 "add{l}\t{$src2, $dst|$dst, $src2}",
2768 [(store (add (load addr:$dst), i32immSExt8:$src2),
2770 (implicit EFLAGS)]>;
2773 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2774 "add{b}\t{$src, %al|%al, $src}", []>;
2775 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2776 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2777 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2778 "add{l}\t{$src, %eax|%eax, $src}", []>;
2781 let Uses = [EFLAGS] in {
2782 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2783 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2784 "adc{b}\t{$src2, $dst|$dst, $src2}",
2785 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2786 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2787 (ins GR16:$src1, GR16:$src2),
2788 "adc{w}\t{$src2, $dst|$dst, $src2}",
2789 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2790 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2791 (ins GR32:$src1, GR32:$src2),
2792 "adc{l}\t{$src2, $dst|$dst, $src2}",
2793 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2796 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2797 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2798 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2799 (ins GR16:$src1, GR16:$src2),
2800 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2801 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2802 (ins GR32:$src1, GR32:$src2),
2803 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2805 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2806 (ins GR8:$src1, i8mem:$src2),
2807 "adc{b}\t{$src2, $dst|$dst, $src2}",
2808 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2809 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2810 (ins GR16:$src1, i16mem:$src2),
2811 "adc{w}\t{$src2, $dst|$dst, $src2}",
2812 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2814 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2815 (ins GR32:$src1, i32mem:$src2),
2816 "adc{l}\t{$src2, $dst|$dst, $src2}",
2817 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2818 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2819 "adc{b}\t{$src2, $dst|$dst, $src2}",
2820 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2821 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2822 (ins GR16:$src1, i16imm:$src2),
2823 "adc{w}\t{$src2, $dst|$dst, $src2}",
2824 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2825 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2826 (ins GR16:$src1, i16i8imm:$src2),
2827 "adc{w}\t{$src2, $dst|$dst, $src2}",
2828 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2830 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2831 (ins GR32:$src1, i32imm:$src2),
2832 "adc{l}\t{$src2, $dst|$dst, $src2}",
2833 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2834 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2835 (ins GR32:$src1, i32i8imm:$src2),
2836 "adc{l}\t{$src2, $dst|$dst, $src2}",
2837 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2839 let isTwoAddress = 0 in {
2840 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2841 "adc{b}\t{$src2, $dst|$dst, $src2}",
2842 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2843 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2844 "adc{w}\t{$src2, $dst|$dst, $src2}",
2845 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2847 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2848 "adc{l}\t{$src2, $dst|$dst, $src2}",
2849 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2850 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2851 "adc{b}\t{$src2, $dst|$dst, $src2}",
2852 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2853 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2854 "adc{w}\t{$src2, $dst|$dst, $src2}",
2855 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2857 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2858 "adc{w}\t{$src2, $dst|$dst, $src2}",
2859 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2861 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2862 "adc{l}\t{$src2, $dst|$dst, $src2}",
2863 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2864 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2865 "adc{l}\t{$src2, $dst|$dst, $src2}",
2866 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2868 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2869 "adc{b}\t{$src, %al|%al, $src}", []>;
2870 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2871 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2872 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2873 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2875 } // Uses = [EFLAGS]
2877 // Register-Register Subtraction
2878 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2879 "sub{b}\t{$src2, $dst|$dst, $src2}",
2880 [(set GR8:$dst, EFLAGS,
2881 (X86sub_flag GR8:$src1, GR8:$src2))]>;
2882 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2883 "sub{w}\t{$src2, $dst|$dst, $src2}",
2884 [(set GR16:$dst, EFLAGS,
2885 (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
2886 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2887 "sub{l}\t{$src2, $dst|$dst, $src2}",
2888 [(set GR32:$dst, EFLAGS,
2889 (X86sub_flag GR32:$src1, GR32:$src2))]>;
2891 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2892 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
2893 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
2894 (ins GR16:$src1, GR16:$src2),
2895 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2896 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
2897 (ins GR32:$src1, GR32:$src2),
2898 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
2900 // Register-Memory Subtraction
2901 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2902 (ins GR8 :$src1, i8mem :$src2),
2903 "sub{b}\t{$src2, $dst|$dst, $src2}",
2904 [(set GR8:$dst, EFLAGS,
2905 (X86sub_flag GR8:$src1, (load addr:$src2)))]>;
2906 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2907 (ins GR16:$src1, i16mem:$src2),
2908 "sub{w}\t{$src2, $dst|$dst, $src2}",
2909 [(set GR16:$dst, EFLAGS,
2910 (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
2911 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2912 (ins GR32:$src1, i32mem:$src2),
2913 "sub{l}\t{$src2, $dst|$dst, $src2}",
2914 [(set GR32:$dst, EFLAGS,
2915 (X86sub_flag GR32:$src1, (load addr:$src2)))]>;
2917 // Register-Integer Subtraction
2918 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2919 (ins GR8:$src1, i8imm:$src2),
2920 "sub{b}\t{$src2, $dst|$dst, $src2}",
2921 [(set GR8:$dst, EFLAGS,
2922 (X86sub_flag GR8:$src1, imm:$src2))]>;
2923 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2924 (ins GR16:$src1, i16imm:$src2),
2925 "sub{w}\t{$src2, $dst|$dst, $src2}",
2926 [(set GR16:$dst, EFLAGS,
2927 (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
2928 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2929 (ins GR32:$src1, i32imm:$src2),
2930 "sub{l}\t{$src2, $dst|$dst, $src2}",
2931 [(set GR32:$dst, EFLAGS,
2932 (X86sub_flag GR32:$src1, imm:$src2))]>;
2933 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2934 (ins GR16:$src1, i16i8imm:$src2),
2935 "sub{w}\t{$src2, $dst|$dst, $src2}",
2936 [(set GR16:$dst, EFLAGS,
2937 (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2938 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2939 (ins GR32:$src1, i32i8imm:$src2),
2940 "sub{l}\t{$src2, $dst|$dst, $src2}",
2941 [(set GR32:$dst, EFLAGS,
2942 (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
2944 let isTwoAddress = 0 in {
2945 // Memory-Register Subtraction
2946 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2947 "sub{b}\t{$src2, $dst|$dst, $src2}",
2948 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2949 (implicit EFLAGS)]>;
2950 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2951 "sub{w}\t{$src2, $dst|$dst, $src2}",
2952 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2953 (implicit EFLAGS)]>, OpSize;
2954 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2955 "sub{l}\t{$src2, $dst|$dst, $src2}",
2956 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2957 (implicit EFLAGS)]>;
2959 // Memory-Integer Subtraction
2960 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2961 "sub{b}\t{$src2, $dst|$dst, $src2}",
2962 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2963 (implicit EFLAGS)]>;
2964 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2965 "sub{w}\t{$src2, $dst|$dst, $src2}",
2966 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2967 (implicit EFLAGS)]>, OpSize;
2968 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2969 "sub{l}\t{$src2, $dst|$dst, $src2}",
2970 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2971 (implicit EFLAGS)]>;
2972 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2973 "sub{w}\t{$src2, $dst|$dst, $src2}",
2974 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2976 (implicit EFLAGS)]>, OpSize;
2977 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2978 "sub{l}\t{$src2, $dst|$dst, $src2}",
2979 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2981 (implicit EFLAGS)]>;
2983 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
2984 "sub{b}\t{$src, %al|%al, $src}", []>;
2985 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
2986 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2987 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
2988 "sub{l}\t{$src, %eax|%eax, $src}", []>;
2991 let Uses = [EFLAGS] in {
2992 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
2993 (ins GR8:$src1, GR8:$src2),
2994 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2995 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
2996 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
2997 (ins GR16:$src1, GR16:$src2),
2998 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2999 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
3000 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
3001 (ins GR32:$src1, GR32:$src2),
3002 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3003 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
3005 let isTwoAddress = 0 in {
3006 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3007 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3008 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
3009 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3010 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3011 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
3013 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3014 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3015 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
3016 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
3017 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3018 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
3019 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
3020 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3021 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
3023 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3024 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3025 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
3027 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
3028 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3029 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
3030 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3031 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3032 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
3034 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
3035 "sbb{b}\t{$src, %al|%al, $src}", []>;
3036 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
3037 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3038 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
3039 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
3042 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3043 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
3044 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
3045 (ins GR16:$src1, GR16:$src2),
3046 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3047 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
3048 (ins GR32:$src1, GR32:$src2),
3049 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
3051 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
3052 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3053 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
3054 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
3055 (ins GR16:$src1, i16mem:$src2),
3056 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3057 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
3059 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
3060 (ins GR32:$src1, i32mem:$src2),
3061 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3062 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
3063 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
3064 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3065 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
3066 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
3067 (ins GR16:$src1, i16imm:$src2),
3068 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3069 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
3070 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
3071 (ins GR16:$src1, i16i8imm:$src2),
3072 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3073 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
3075 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
3076 (ins GR32:$src1, i32imm:$src2),
3077 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3078 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
3079 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
3080 (ins GR32:$src1, i32i8imm:$src2),
3081 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3082 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
3083 } // Uses = [EFLAGS]
3084 } // Defs = [EFLAGS]
3086 let Defs = [EFLAGS] in {
3087 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
3088 // Register-Register Signed Integer Multiply
3089 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3090 "imul{w}\t{$src2, $dst|$dst, $src2}",
3091 [(set GR16:$dst, EFLAGS,
3092 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
3093 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3094 "imul{l}\t{$src2, $dst|$dst, $src2}",
3095 [(set GR32:$dst, EFLAGS,
3096 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
3099 // Register-Memory Signed Integer Multiply
3100 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
3101 (ins GR16:$src1, i16mem:$src2),
3102 "imul{w}\t{$src2, $dst|$dst, $src2}",
3103 [(set GR16:$dst, EFLAGS,
3104 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
3106 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
3107 (ins GR32:$src1, i32mem:$src2),
3108 "imul{l}\t{$src2, $dst|$dst, $src2}",
3109 [(set GR32:$dst, EFLAGS,
3110 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
3111 } // Defs = [EFLAGS]
3112 } // end Two Address instructions
3114 // Suprisingly enough, these are not two address instructions!
3115 let Defs = [EFLAGS] in {
3116 // Register-Integer Signed Integer Multiply
3117 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
3118 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
3119 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3120 [(set GR16:$dst, EFLAGS,
3121 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
3122 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
3123 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
3124 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3125 [(set GR32:$dst, EFLAGS,
3126 (X86smul_flag GR32:$src1, imm:$src2))]>;
3127 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
3128 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
3129 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3130 [(set GR16:$dst, EFLAGS,
3131 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
3133 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
3134 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
3135 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3136 [(set GR32:$dst, EFLAGS,
3137 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
3139 // Memory-Integer Signed Integer Multiply
3140 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
3141 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
3142 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3143 [(set GR16:$dst, EFLAGS,
3144 (X86smul_flag (load addr:$src1), imm:$src2))]>,
3146 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
3147 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
3148 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3149 [(set GR32:$dst, EFLAGS,
3150 (X86smul_flag (load addr:$src1), imm:$src2))]>;
3151 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
3152 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
3153 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3154 [(set GR16:$dst, EFLAGS,
3155 (X86smul_flag (load addr:$src1),
3156 i16immSExt8:$src2))]>, OpSize;
3157 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
3158 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
3159 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3160 [(set GR32:$dst, EFLAGS,
3161 (X86smul_flag (load addr:$src1),
3162 i32immSExt8:$src2))]>;
3163 } // Defs = [EFLAGS]
3165 //===----------------------------------------------------------------------===//
3166 // Test instructions are just like AND, except they don't generate a result.
3168 let Defs = [EFLAGS] in {
3169 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
3170 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3171 "test{b}\t{$src2, $src1|$src1, $src2}",
3172 [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
3173 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3174 "test{w}\t{$src2, $src1|$src1, $src2}",
3175 [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
3178 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3179 "test{l}\t{$src2, $src1|$src1, $src2}",
3180 [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
3184 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
3185 "test{b}\t{$src, %al|%al, $src}", []>;
3186 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
3187 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3188 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
3189 "test{l}\t{$src, %eax|%eax, $src}", []>;
3191 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
3192 "test{b}\t{$src2, $src1|$src1, $src2}",
3193 [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
3195 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
3196 "test{w}\t{$src2, $src1|$src1, $src2}",
3197 [(set EFLAGS, (X86cmp (and GR16:$src1,
3198 (loadi16 addr:$src2)), 0))]>, OpSize;
3199 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
3200 "test{l}\t{$src2, $src1|$src1, $src2}",
3201 [(set EFLAGS, (X86cmp (and GR32:$src1,
3202 (loadi32 addr:$src2)), 0))]>;
3204 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
3205 (outs), (ins GR8:$src1, i8imm:$src2),
3206 "test{b}\t{$src2, $src1|$src1, $src2}",
3207 [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
3208 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
3209 (outs), (ins GR16:$src1, i16imm:$src2),
3210 "test{w}\t{$src2, $src1|$src1, $src2}",
3211 [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
3213 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
3214 (outs), (ins GR32:$src1, i32imm:$src2),
3215 "test{l}\t{$src2, $src1|$src1, $src2}",
3216 [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
3218 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
3219 (outs), (ins i8mem:$src1, i8imm:$src2),
3220 "test{b}\t{$src2, $src1|$src1, $src2}",
3221 [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
3223 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3224 (outs), (ins i16mem:$src1, i16imm:$src2),
3225 "test{w}\t{$src2, $src1|$src1, $src2}",
3226 [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
3228 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3229 (outs), (ins i32mem:$src1, i32imm:$src2),
3230 "test{l}\t{$src2, $src1|$src1, $src2}",
3231 [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
3233 } // Defs = [EFLAGS]
3236 // Condition code ops, incl. set if equal/not equal/...
3237 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3238 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3239 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3240 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3242 let Uses = [EFLAGS] in {
3243 // Use sbb to materialize carry bit.
3244 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
3245 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
3246 // However, Pat<> can't replicate the destination reg into the inputs of the
3248 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
3250 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
3251 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3252 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
3253 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
3255 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
3256 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3259 def SETEr : I<0x94, MRM0r,
3260 (outs GR8 :$dst), (ins),
3262 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3264 def SETEm : I<0x94, MRM0m,
3265 (outs), (ins i8mem:$dst),
3267 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3270 def SETNEr : I<0x95, MRM0r,
3271 (outs GR8 :$dst), (ins),
3273 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3275 def SETNEm : I<0x95, MRM0m,
3276 (outs), (ins i8mem:$dst),
3278 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3281 def SETLr : I<0x9C, MRM0r,
3282 (outs GR8 :$dst), (ins),
3284 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3285 TB; // GR8 = < signed
3286 def SETLm : I<0x9C, MRM0m,
3287 (outs), (ins i8mem:$dst),
3289 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3290 TB; // [mem8] = < signed
3292 def SETGEr : I<0x9D, MRM0r,
3293 (outs GR8 :$dst), (ins),
3295 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3296 TB; // GR8 = >= signed
3297 def SETGEm : I<0x9D, MRM0m,
3298 (outs), (ins i8mem:$dst),
3300 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3301 TB; // [mem8] = >= signed
3303 def SETLEr : I<0x9E, MRM0r,
3304 (outs GR8 :$dst), (ins),
3306 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3307 TB; // GR8 = <= signed
3308 def SETLEm : I<0x9E, MRM0m,
3309 (outs), (ins i8mem:$dst),
3311 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3312 TB; // [mem8] = <= signed
3314 def SETGr : I<0x9F, MRM0r,
3315 (outs GR8 :$dst), (ins),
3317 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3318 TB; // GR8 = > signed
3319 def SETGm : I<0x9F, MRM0m,
3320 (outs), (ins i8mem:$dst),
3322 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3323 TB; // [mem8] = > signed
3325 def SETBr : I<0x92, MRM0r,
3326 (outs GR8 :$dst), (ins),
3328 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3329 TB; // GR8 = < unsign
3330 def SETBm : I<0x92, MRM0m,
3331 (outs), (ins i8mem:$dst),
3333 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3334 TB; // [mem8] = < unsign
3336 def SETAEr : I<0x93, MRM0r,
3337 (outs GR8 :$dst), (ins),
3339 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3340 TB; // GR8 = >= unsign
3341 def SETAEm : I<0x93, MRM0m,
3342 (outs), (ins i8mem:$dst),
3344 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3345 TB; // [mem8] = >= unsign
3347 def SETBEr : I<0x96, MRM0r,
3348 (outs GR8 :$dst), (ins),
3350 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3351 TB; // GR8 = <= unsign
3352 def SETBEm : I<0x96, MRM0m,
3353 (outs), (ins i8mem:$dst),
3355 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3356 TB; // [mem8] = <= unsign
3358 def SETAr : I<0x97, MRM0r,
3359 (outs GR8 :$dst), (ins),
3361 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3362 TB; // GR8 = > signed
3363 def SETAm : I<0x97, MRM0m,
3364 (outs), (ins i8mem:$dst),
3366 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3367 TB; // [mem8] = > signed
3369 def SETSr : I<0x98, MRM0r,
3370 (outs GR8 :$dst), (ins),
3372 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3373 TB; // GR8 = <sign bit>
3374 def SETSm : I<0x98, MRM0m,
3375 (outs), (ins i8mem:$dst),
3377 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3378 TB; // [mem8] = <sign bit>
3379 def SETNSr : I<0x99, MRM0r,
3380 (outs GR8 :$dst), (ins),
3382 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3383 TB; // GR8 = !<sign bit>
3384 def SETNSm : I<0x99, MRM0m,
3385 (outs), (ins i8mem:$dst),
3387 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3388 TB; // [mem8] = !<sign bit>
3390 def SETPr : I<0x9A, MRM0r,
3391 (outs GR8 :$dst), (ins),
3393 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3395 def SETPm : I<0x9A, MRM0m,
3396 (outs), (ins i8mem:$dst),
3398 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3399 TB; // [mem8] = parity
3400 def SETNPr : I<0x9B, MRM0r,
3401 (outs GR8 :$dst), (ins),
3403 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3404 TB; // GR8 = not parity
3405 def SETNPm : I<0x9B, MRM0m,
3406 (outs), (ins i8mem:$dst),
3408 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3409 TB; // [mem8] = not parity
3411 def SETOr : I<0x90, MRM0r,
3412 (outs GR8 :$dst), (ins),
3414 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3415 TB; // GR8 = overflow
3416 def SETOm : I<0x90, MRM0m,
3417 (outs), (ins i8mem:$dst),
3419 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3420 TB; // [mem8] = overflow
3421 def SETNOr : I<0x91, MRM0r,
3422 (outs GR8 :$dst), (ins),
3424 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3425 TB; // GR8 = not overflow
3426 def SETNOm : I<0x91, MRM0m,
3427 (outs), (ins i8mem:$dst),
3429 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3430 TB; // [mem8] = not overflow
3431 } // Uses = [EFLAGS]
3434 // Integer comparisons
3435 let Defs = [EFLAGS] in {
3436 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3437 "cmp{b}\t{$src, %al|%al, $src}", []>;
3438 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3439 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3440 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3441 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3443 def CMP8rr : I<0x38, MRMDestReg,
3444 (outs), (ins GR8 :$src1, GR8 :$src2),
3445 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3446 [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
3447 def CMP16rr : I<0x39, MRMDestReg,
3448 (outs), (ins GR16:$src1, GR16:$src2),
3449 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3450 [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
3451 def CMP32rr : I<0x39, MRMDestReg,
3452 (outs), (ins GR32:$src1, GR32:$src2),
3453 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3454 [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
3455 def CMP8mr : I<0x38, MRMDestMem,
3456 (outs), (ins i8mem :$src1, GR8 :$src2),
3457 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3458 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
3459 def CMP16mr : I<0x39, MRMDestMem,
3460 (outs), (ins i16mem:$src1, GR16:$src2),
3461 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3462 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
3464 def CMP32mr : I<0x39, MRMDestMem,
3465 (outs), (ins i32mem:$src1, GR32:$src2),
3466 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3467 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
3468 def CMP8rm : I<0x3A, MRMSrcMem,
3469 (outs), (ins GR8 :$src1, i8mem :$src2),
3470 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3471 [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
3472 def CMP16rm : I<0x3B, MRMSrcMem,
3473 (outs), (ins GR16:$src1, i16mem:$src2),
3474 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3475 [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
3477 def CMP32rm : I<0x3B, MRMSrcMem,
3478 (outs), (ins GR32:$src1, i32mem:$src2),
3479 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3480 [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
3482 // These are alternate spellings for use by the disassembler, we mark them as
3483 // code gen only to ensure they aren't matched by the assembler.
3484 let isCodeGenOnly = 1 in {
3485 def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3486 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3487 def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3488 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3489 def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3490 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3493 def CMP8ri : Ii8<0x80, MRM7r,
3494 (outs), (ins GR8:$src1, i8imm:$src2),
3495 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3496 [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
3497 def CMP16ri : Ii16<0x81, MRM7r,
3498 (outs), (ins GR16:$src1, i16imm:$src2),
3499 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3500 [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
3501 def CMP32ri : Ii32<0x81, MRM7r,
3502 (outs), (ins GR32:$src1, i32imm:$src2),
3503 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3504 [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
3505 def CMP8mi : Ii8 <0x80, MRM7m,
3506 (outs), (ins i8mem :$src1, i8imm :$src2),
3507 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3508 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
3509 def CMP16mi : Ii16<0x81, MRM7m,
3510 (outs), (ins i16mem:$src1, i16imm:$src2),
3511 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3512 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
3514 def CMP32mi : Ii32<0x81, MRM7m,
3515 (outs), (ins i32mem:$src1, i32imm:$src2),
3516 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3517 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
3518 def CMP16ri8 : Ii8<0x83, MRM7r,
3519 (outs), (ins GR16:$src1, i16i8imm:$src2),
3520 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3521 [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
3523 def CMP16mi8 : Ii8<0x83, MRM7m,
3524 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3525 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3526 [(set EFLAGS, (X86cmp (loadi16 addr:$src1),
3527 i16immSExt8:$src2))]>, OpSize;
3528 def CMP32mi8 : Ii8<0x83, MRM7m,
3529 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3530 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3531 [(set EFLAGS, (X86cmp (loadi32 addr:$src1),
3532 i32immSExt8:$src2))]>;
3533 def CMP32ri8 : Ii8<0x83, MRM7r,
3534 (outs), (ins GR32:$src1, i32i8imm:$src2),
3535 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3536 [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
3537 } // Defs = [EFLAGS]
3540 // TODO: BTC, BTR, and BTS
3541 let Defs = [EFLAGS] in {
3542 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3543 "bt{w}\t{$src2, $src1|$src1, $src2}",
3544 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
3545 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3546 "bt{l}\t{$src2, $src1|$src1, $src2}",
3547 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
3549 // Unlike with the register+register form, the memory+register form of the
3550 // bt instruction does not ignore the high bits of the index. From ISel's
3551 // perspective, this is pretty bizarre. Make these instructions disassembly
3554 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3555 "bt{w}\t{$src2, $src1|$src1, $src2}",
3556 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3557 // (implicit EFLAGS)]
3559 >, OpSize, TB, Requires<[FastBTMem]>;
3560 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3561 "bt{l}\t{$src2, $src1|$src1, $src2}",
3562 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3563 // (implicit EFLAGS)]
3565 >, TB, Requires<[FastBTMem]>;
3567 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3568 "bt{w}\t{$src2, $src1|$src1, $src2}",
3569 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
3571 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3572 "bt{l}\t{$src2, $src1|$src1, $src2}",
3573 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
3574 // Note that these instructions don't need FastBTMem because that
3575 // only applies when the other operand is in a register. When it's
3576 // an immediate, bt is still fast.
3577 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3578 "bt{w}\t{$src2, $src1|$src1, $src2}",
3579 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
3581 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3582 "bt{l}\t{$src2, $src1|$src1, $src2}",
3583 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
3586 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3587 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3588 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3589 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3590 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3591 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3592 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3593 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3594 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3595 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3596 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3597 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3598 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3599 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3600 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3601 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3603 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3604 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3605 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3606 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3607 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3608 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3609 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3610 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3611 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3612 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3613 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3614 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3615 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3616 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3617 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3618 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3620 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3621 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3622 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3623 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3624 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3625 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3626 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3627 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3628 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3629 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3630 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3631 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3632 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3633 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3634 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3635 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3636 } // Defs = [EFLAGS]
3638 // Sign/Zero extenders
3639 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3640 // of the register here. This has a smaller encoding and avoids a
3641 // partial-register update. Actual movsbw included for the disassembler.
3642 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3643 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3644 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3645 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3646 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3647 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3648 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3649 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3650 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3651 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3652 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3653 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3654 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3655 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3656 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3657 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3658 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3659 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3660 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3661 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3663 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3664 // of the register here. This has a smaller encoding and avoids a
3665 // partial-register update. Actual movzbw included for the disassembler.
3666 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3667 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3668 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3669 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3670 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3671 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3672 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3673 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3674 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3675 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3676 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3677 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3678 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3679 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3680 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3681 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3682 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3683 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3684 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3685 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3687 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
3688 // except that they use GR32_NOREX for the output operand register class
3689 // instead of GR32. This allows them to operate on h registers on x86-64.
3690 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3691 (outs GR32_NOREX:$dst), (ins GR8:$src),
3692 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3695 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3696 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3697 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3700 let neverHasSideEffects = 1 in {
3701 let Defs = [AX], Uses = [AL] in
3702 def CBW : I<0x98, RawFrm, (outs), (ins),
3703 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3704 let Defs = [EAX], Uses = [AX] in
3705 def CWDE : I<0x98, RawFrm, (outs), (ins),
3706 "{cwtl|cwde}", []>; // EAX = signext(AX)
3708 let Defs = [AX,DX], Uses = [AX] in
3709 def CWD : I<0x99, RawFrm, (outs), (ins),
3710 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3711 let Defs = [EAX,EDX], Uses = [EAX] in
3712 def CDQ : I<0x99, RawFrm, (outs), (ins),
3713 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3716 //===----------------------------------------------------------------------===//
3717 // Alias Instructions
3718 //===----------------------------------------------------------------------===//
3720 // Alias instructions that map movr0 to xor.
3721 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3722 // FIXME: Set encoding to pseudo.
3723 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3724 isCodeGenOnly = 1 in {
3725 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
3726 [(set GR8:$dst, 0)]>;
3728 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
3729 // encoding and avoids a partial-register update sometimes, but doing so
3730 // at isel time interferes with rematerialization in the current register
3731 // allocator. For now, this is rewritten when the instruction is lowered
3733 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3735 [(set GR16:$dst, 0)]>, OpSize;
3737 // FIXME: Set encoding to pseudo.
3738 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
3739 [(set GR32:$dst, 0)]>;
3742 //===----------------------------------------------------------------------===//
3743 // Thread Local Storage Instructions
3746 // All calls clobber the non-callee saved registers. ESP is marked as
3747 // a use to prevent stack-pointer assignments that appear immediately
3748 // before calls from potentially appearing dead.
3749 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3750 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3751 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3752 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3754 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3755 "leal\t$sym, %eax; "
3756 "call\t___tls_get_addr@PLT",
3757 [(X86tlsaddr tls32addr:$sym)]>,
3758 Requires<[In32BitMode]>;
3760 let AddedComplexity = 5, isCodeGenOnly = 1 in
3761 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3762 "movl\t%gs:$src, $dst",
3763 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3765 let AddedComplexity = 5, isCodeGenOnly = 1 in
3766 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3767 "movl\t%fs:$src, $dst",
3768 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3770 //===----------------------------------------------------------------------===//
3771 // EH Pseudo Instructions
3773 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3774 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3775 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3776 "ret\t#eh_return, addr: $addr",
3777 [(X86ehret GR32:$addr)]>;
3781 //===----------------------------------------------------------------------===//
3785 // Atomic swap. These are just normal xchg instructions. But since a memory
3786 // operand is referenced, the atomicity is ensured.
3787 let Constraints = "$val = $dst" in {
3788 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3789 (ins GR32:$val, i32mem:$ptr),
3790 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3791 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3792 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3793 (ins GR16:$val, i16mem:$ptr),
3794 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3795 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3797 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3798 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3799 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3801 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3802 "xchg{l}\t{$val, $src|$src, $val}", []>;
3803 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3804 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3805 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3806 "xchg{b}\t{$val, $src|$src, $val}", []>;
3809 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3810 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3811 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3812 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
3814 // Atomic compare and swap.
3815 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3816 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3818 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3819 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3821 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3822 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
3825 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3828 let Defs = [AX, EFLAGS], Uses = [AX] in {
3829 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3831 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3832 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3834 let Defs = [AL, EFLAGS], Uses = [AL] in {
3835 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3837 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3838 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3841 // Atomic exchange and add
3842 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3843 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
3845 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3846 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3848 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
3850 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3851 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3853 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3855 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3856 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3860 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3861 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3862 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3863 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3864 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3865 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3867 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3868 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3869 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3870 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3871 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3872 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3874 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3875 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3876 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3877 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3878 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3879 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3881 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3882 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3883 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3884 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3885 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3886 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3888 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
3889 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
3890 "cmpxchg8b\t$dst", []>, TB;
3892 // Optimized codegen when the non-memory output is not used.
3893 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3894 let Defs = [EFLAGS] in {
3895 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3897 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3898 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3900 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3901 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3903 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3904 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3906 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3907 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3909 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3910 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3912 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3913 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3915 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3916 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3918 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3920 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3922 "inc{b}\t$dst", []>, LOCK;
3923 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3925 "inc{w}\t$dst", []>, OpSize, LOCK;
3926 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3928 "inc{l}\t$dst", []>, LOCK;
3930 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3932 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3933 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3935 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3936 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3938 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3939 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3941 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3942 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3944 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3945 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3947 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3948 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3950 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3951 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3953 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3955 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3957 "dec{b}\t$dst", []>, LOCK;
3958 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3960 "dec{w}\t$dst", []>, OpSize, LOCK;
3961 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3963 "dec{l}\t$dst", []>, LOCK;
3966 // Atomic exchange, and, or, xor
3967 let Constraints = "$val = $dst", Defs = [EFLAGS],
3968 usesCustomInserter = 1 in {
3969 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3970 "#ATOMAND32 PSEUDO!",
3971 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3972 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3973 "#ATOMOR32 PSEUDO!",
3974 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
3975 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3976 "#ATOMXOR32 PSEUDO!",
3977 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
3978 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3979 "#ATOMNAND32 PSEUDO!",
3980 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
3981 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3982 "#ATOMMIN32 PSEUDO!",
3983 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
3984 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3985 "#ATOMMAX32 PSEUDO!",
3986 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
3987 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3988 "#ATOMUMIN32 PSEUDO!",
3989 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
3990 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3991 "#ATOMUMAX32 PSEUDO!",
3992 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
3994 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3995 "#ATOMAND16 PSEUDO!",
3996 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
3997 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3998 "#ATOMOR16 PSEUDO!",
3999 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
4000 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4001 "#ATOMXOR16 PSEUDO!",
4002 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
4003 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4004 "#ATOMNAND16 PSEUDO!",
4005 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
4006 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
4007 "#ATOMMIN16 PSEUDO!",
4008 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
4009 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4010 "#ATOMMAX16 PSEUDO!",
4011 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
4012 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4013 "#ATOMUMIN16 PSEUDO!",
4014 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
4015 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4016 "#ATOMUMAX16 PSEUDO!",
4017 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
4019 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4020 "#ATOMAND8 PSEUDO!",
4021 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
4022 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4024 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
4025 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4026 "#ATOMXOR8 PSEUDO!",
4027 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
4028 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4029 "#ATOMNAND8 PSEUDO!",
4030 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
4033 let Constraints = "$val1 = $dst1, $val2 = $dst2",
4034 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
4035 Uses = [EAX, EBX, ECX, EDX],
4036 mayLoad = 1, mayStore = 1,
4037 usesCustomInserter = 1 in {
4038 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4039 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4040 "#ATOMAND6432 PSEUDO!", []>;
4041 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4042 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4043 "#ATOMOR6432 PSEUDO!", []>;
4044 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4045 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4046 "#ATOMXOR6432 PSEUDO!", []>;
4047 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4048 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4049 "#ATOMNAND6432 PSEUDO!", []>;
4050 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4051 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4052 "#ATOMADD6432 PSEUDO!", []>;
4053 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4054 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4055 "#ATOMSUB6432 PSEUDO!", []>;
4056 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4057 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4058 "#ATOMSWAP6432 PSEUDO!", []>;
4061 // Segmentation support instructions.
4063 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4064 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4065 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4066 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4068 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
4069 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
4070 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4071 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4072 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4074 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4075 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4076 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4077 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4078 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4079 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4080 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4081 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4083 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
4085 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
4086 "str{w}\t{$dst}", []>, TB;
4087 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
4088 "str{w}\t{$dst}", []>, TB;
4089 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
4090 "ltr{w}\t{$src}", []>, TB;
4091 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
4092 "ltr{w}\t{$src}", []>, TB;
4094 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
4095 "push{w}\t%fs", []>, OpSize, TB;
4096 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
4097 "push{l}\t%fs", []>, TB;
4098 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
4099 "push{w}\t%gs", []>, OpSize, TB;
4100 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
4101 "push{l}\t%gs", []>, TB;
4103 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
4104 "pop{w}\t%fs", []>, OpSize, TB;
4105 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
4106 "pop{l}\t%fs", []>, TB;
4107 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
4108 "pop{w}\t%gs", []>, OpSize, TB;
4109 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
4110 "pop{l}\t%gs", []>, TB;
4112 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4113 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4114 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4115 "lds{l}\t{$src, $dst|$dst, $src}", []>;
4116 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4117 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4118 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4119 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
4120 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4121 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4122 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4123 "les{l}\t{$src, $dst|$dst, $src}", []>;
4124 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4125 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4126 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4127 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4128 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4129 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4130 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4131 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4133 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
4134 "verr\t$seg", []>, TB;
4135 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
4136 "verr\t$seg", []>, TB;
4137 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
4138 "verw\t$seg", []>, TB;
4139 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
4140 "verw\t$seg", []>, TB;
4142 // Descriptor-table support instructions
4144 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
4145 "sgdt\t$dst", []>, TB;
4146 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
4147 "sidt\t$dst", []>, TB;
4148 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
4149 "sldt{w}\t$dst", []>, TB;
4150 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
4151 "sldt{w}\t$dst", []>, TB;
4152 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
4153 "lgdt\t$src", []>, TB;
4154 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
4155 "lidt\t$src", []>, TB;
4156 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
4157 "lldt{w}\t$src", []>, TB;
4158 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
4159 "lldt{w}\t$src", []>, TB;
4161 // Lock instruction prefix
4162 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
4164 // Repeat string operation instruction prefixes
4165 // These uses the DF flag in the EFLAGS register to inc or dec ECX
4166 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
4167 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
4168 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
4169 // Repeat while not equal (used with CMPS and SCAS)
4170 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
4173 // Segment override instruction prefixes
4174 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
4175 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
4176 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
4177 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
4178 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
4179 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
4181 // String manipulation instructions
4183 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
4184 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
4185 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
4187 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
4188 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
4189 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
4191 // CPU flow control instructions
4193 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
4194 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
4196 // FPU control instructions
4198 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
4200 // Flag instructions
4202 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
4203 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
4204 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
4205 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
4206 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
4207 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
4208 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
4210 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
4212 // Table lookup instructions
4214 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
4216 // Specialized register support
4218 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
4219 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
4220 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
4222 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
4223 "smsw{w}\t$dst", []>, OpSize, TB;
4224 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
4225 "smsw{l}\t$dst", []>, TB;
4226 // For memory operands, there is only a 16-bit form
4227 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
4228 "smsw{w}\t$dst", []>, TB;
4230 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
4231 "lmsw{w}\t$src", []>, TB;
4232 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
4233 "lmsw{w}\t$src", []>, TB;
4235 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
4237 // Cache instructions
4239 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
4240 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
4245 def INVEPT : I<0x80, RawFrm, (outs), (ins), "invept", []>, OpSize, T8;
4247 def INVVPID : I<0x81, RawFrm, (outs), (ins), "invvpid", []>, OpSize, T8;
4249 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
4250 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4251 "vmclear\t$vmcs", []>, OpSize, TB;
4253 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
4255 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
4256 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4257 "vmptrld\t$vmcs", []>, TB;
4258 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4259 "vmptrst\t$vmcs", []>, TB;
4260 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
4261 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4262 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
4263 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4264 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
4265 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4266 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4267 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4268 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4269 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4270 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4271 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4272 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4273 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4274 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4275 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4277 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
4278 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
4279 "vmxon\t{$vmxon}", []>, XS;
4281 //===----------------------------------------------------------------------===//
4282 // Non-Instruction Patterns
4283 //===----------------------------------------------------------------------===//
4285 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
4286 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
4287 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
4288 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
4289 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
4290 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
4291 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
4293 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
4294 (ADD32ri GR32:$src1, tconstpool:$src2)>;
4295 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
4296 (ADD32ri GR32:$src1, tjumptable:$src2)>;
4297 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
4298 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
4299 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
4300 (ADD32ri GR32:$src1, texternalsym:$src2)>;
4301 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
4302 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
4304 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
4305 (MOV32mi addr:$dst, tglobaladdr:$src)>;
4306 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
4307 (MOV32mi addr:$dst, texternalsym:$src)>;
4308 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
4309 (MOV32mi addr:$dst, tblockaddress:$src)>;
4313 def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
4314 (TCRETURNri GR32_TC:$dst, imm:$off)>,
4315 Requires<[In32BitMode]>;
4317 // FIXME: This is disabled for 32-bit PIC mode because the global base
4318 // register which is part of the address mode may be assigned a
4319 // callee-saved register.
4320 def : Pat<(X86tcret (load addr:$dst), imm:$off),
4321 (TCRETURNmi addr:$dst, imm:$off)>,
4322 Requires<[In32BitMode, IsNotPIC]>;
4324 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
4325 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4326 Requires<[In32BitMode]>;
4328 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
4329 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4330 Requires<[In32BitMode]>;
4332 // Normal calls, with various flavors of addresses.
4333 def : Pat<(X86call (i32 tglobaladdr:$dst)),
4334 (CALLpcrel32 tglobaladdr:$dst)>;
4335 def : Pat<(X86call (i32 texternalsym:$dst)),
4336 (CALLpcrel32 texternalsym:$dst)>;
4337 def : Pat<(X86call (i32 imm:$dst)),
4338 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
4340 // X86 specific add which produces a flag.
4341 def : Pat<(addc GR32:$src1, GR32:$src2),
4342 (ADD32rr GR32:$src1, GR32:$src2)>;
4343 def : Pat<(addc GR32:$src1, (load addr:$src2)),
4344 (ADD32rm GR32:$src1, addr:$src2)>;
4345 def : Pat<(addc GR32:$src1, imm:$src2),
4346 (ADD32ri GR32:$src1, imm:$src2)>;
4347 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
4348 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4350 def : Pat<(subc GR32:$src1, GR32:$src2),
4351 (SUB32rr GR32:$src1, GR32:$src2)>;
4352 def : Pat<(subc GR32:$src1, (load addr:$src2)),
4353 (SUB32rm GR32:$src1, addr:$src2)>;
4354 def : Pat<(subc GR32:$src1, imm:$src2),
4355 (SUB32ri GR32:$src1, imm:$src2)>;
4356 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
4357 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4361 // TEST R,R is smaller than CMP R,0
4362 def : Pat<(X86cmp GR8:$src1, 0),
4363 (TEST8rr GR8:$src1, GR8:$src1)>;
4364 def : Pat<(X86cmp GR16:$src1, 0),
4365 (TEST16rr GR16:$src1, GR16:$src1)>;
4366 def : Pat<(X86cmp GR32:$src1, 0),
4367 (TEST32rr GR32:$src1, GR32:$src1)>;
4369 // Conditional moves with folded loads with operands swapped and conditions
4371 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
4372 (CMOVAE16rm GR16:$src2, addr:$src1)>;
4373 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
4374 (CMOVAE32rm GR32:$src2, addr:$src1)>;
4375 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
4376 (CMOVB16rm GR16:$src2, addr:$src1)>;
4377 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
4378 (CMOVB32rm GR32:$src2, addr:$src1)>;
4379 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
4380 (CMOVNE16rm GR16:$src2, addr:$src1)>;
4381 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
4382 (CMOVNE32rm GR32:$src2, addr:$src1)>;
4383 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
4384 (CMOVE16rm GR16:$src2, addr:$src1)>;
4385 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
4386 (CMOVE32rm GR32:$src2, addr:$src1)>;
4387 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
4388 (CMOVA16rm GR16:$src2, addr:$src1)>;
4389 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
4390 (CMOVA32rm GR32:$src2, addr:$src1)>;
4391 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
4392 (CMOVBE16rm GR16:$src2, addr:$src1)>;
4393 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
4394 (CMOVBE32rm GR32:$src2, addr:$src1)>;
4395 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
4396 (CMOVGE16rm GR16:$src2, addr:$src1)>;
4397 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
4398 (CMOVGE32rm GR32:$src2, addr:$src1)>;
4399 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
4400 (CMOVL16rm GR16:$src2, addr:$src1)>;
4401 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
4402 (CMOVL32rm GR32:$src2, addr:$src1)>;
4403 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
4404 (CMOVG16rm GR16:$src2, addr:$src1)>;
4405 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
4406 (CMOVG32rm GR32:$src2, addr:$src1)>;
4407 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
4408 (CMOVLE16rm GR16:$src2, addr:$src1)>;
4409 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
4410 (CMOVLE32rm GR32:$src2, addr:$src1)>;
4411 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
4412 (CMOVNP16rm GR16:$src2, addr:$src1)>;
4413 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
4414 (CMOVNP32rm GR32:$src2, addr:$src1)>;
4415 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
4416 (CMOVP16rm GR16:$src2, addr:$src1)>;
4417 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
4418 (CMOVP32rm GR32:$src2, addr:$src1)>;
4419 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
4420 (CMOVNS16rm GR16:$src2, addr:$src1)>;
4421 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
4422 (CMOVNS32rm GR32:$src2, addr:$src1)>;
4423 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
4424 (CMOVS16rm GR16:$src2, addr:$src1)>;
4425 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
4426 (CMOVS32rm GR32:$src2, addr:$src1)>;
4427 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
4428 (CMOVNO16rm GR16:$src2, addr:$src1)>;
4429 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
4430 (CMOVNO32rm GR32:$src2, addr:$src1)>;
4431 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
4432 (CMOVO16rm GR16:$src2, addr:$src1)>;
4433 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
4434 (CMOVO32rm GR32:$src2, addr:$src1)>;
4436 // zextload bool -> zextload byte
4437 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4438 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4439 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4441 // extload bool -> extload byte
4442 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4443 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4444 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4445 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
4446 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
4447 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
4449 // anyext. Define these to do an explicit zero-extend to
4450 // avoid partial-register updates.
4451 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
4452 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
4454 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
4455 def : Pat<(i32 (anyext GR16:$src)),
4456 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
4459 //===----------------------------------------------------------------------===//
4461 //===----------------------------------------------------------------------===//
4463 // Odd encoding trick: -128 fits into an 8-bit immediate field while
4464 // +128 doesn't, so in this special case use a sub instead of an add.
4465 def : Pat<(add GR16:$src1, 128),
4466 (SUB16ri8 GR16:$src1, -128)>;
4467 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
4468 (SUB16mi8 addr:$dst, -128)>;
4469 def : Pat<(add GR32:$src1, 128),
4470 (SUB32ri8 GR32:$src1, -128)>;
4471 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
4472 (SUB32mi8 addr:$dst, -128)>;
4474 // r & (2^16-1) ==> movz
4475 def : Pat<(and GR32:$src1, 0xffff),
4476 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
4477 // r & (2^8-1) ==> movz
4478 def : Pat<(and GR32:$src1, 0xff),
4479 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
4482 Requires<[In32BitMode]>;
4483 // r & (2^8-1) ==> movz
4484 def : Pat<(and GR16:$src1, 0xff),
4485 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
4488 Requires<[In32BitMode]>;
4490 // sext_inreg patterns
4491 def : Pat<(sext_inreg GR32:$src, i16),
4492 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
4493 def : Pat<(sext_inreg GR32:$src, i8),
4494 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4497 Requires<[In32BitMode]>;
4498 def : Pat<(sext_inreg GR16:$src, i8),
4499 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4502 Requires<[In32BitMode]>;
4505 def : Pat<(i16 (trunc GR32:$src)),
4506 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
4507 def : Pat<(i8 (trunc GR32:$src)),
4508 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4510 Requires<[In32BitMode]>;
4511 def : Pat<(i8 (trunc GR16:$src)),
4512 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4514 Requires<[In32BitMode]>;
4516 // h-register tricks
4517 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
4518 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4519 x86_subreg_8bit_hi)>,
4520 Requires<[In32BitMode]>;
4521 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
4522 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4523 x86_subreg_8bit_hi)>,
4524 Requires<[In32BitMode]>;
4525 def : Pat<(srl GR16:$src, (i8 8)),
4528 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4529 x86_subreg_8bit_hi)),
4531 Requires<[In32BitMode]>;
4532 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4533 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4535 x86_subreg_8bit_hi))>,
4536 Requires<[In32BitMode]>;
4537 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4538 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4540 x86_subreg_8bit_hi))>,
4541 Requires<[In32BitMode]>;
4542 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4543 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4545 x86_subreg_8bit_hi))>,
4546 Requires<[In32BitMode]>;
4547 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
4548 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4550 x86_subreg_8bit_hi))>,
4551 Requires<[In32BitMode]>;
4553 // (shl x, 1) ==> (add x, x)
4554 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
4555 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
4556 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
4558 // (shl x (and y, 31)) ==> (shl x, y)
4559 def : Pat<(shl GR8:$src1, (and CL, 31)),
4560 (SHL8rCL GR8:$src1)>;
4561 def : Pat<(shl GR16:$src1, (and CL, 31)),
4562 (SHL16rCL GR16:$src1)>;
4563 def : Pat<(shl GR32:$src1, (and CL, 31)),
4564 (SHL32rCL GR32:$src1)>;
4565 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4566 (SHL8mCL addr:$dst)>;
4567 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4568 (SHL16mCL addr:$dst)>;
4569 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4570 (SHL32mCL addr:$dst)>;
4572 def : Pat<(srl GR8:$src1, (and CL, 31)),
4573 (SHR8rCL GR8:$src1)>;
4574 def : Pat<(srl GR16:$src1, (and CL, 31)),
4575 (SHR16rCL GR16:$src1)>;
4576 def : Pat<(srl GR32:$src1, (and CL, 31)),
4577 (SHR32rCL GR32:$src1)>;
4578 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4579 (SHR8mCL addr:$dst)>;
4580 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4581 (SHR16mCL addr:$dst)>;
4582 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4583 (SHR32mCL addr:$dst)>;
4585 def : Pat<(sra GR8:$src1, (and CL, 31)),
4586 (SAR8rCL GR8:$src1)>;
4587 def : Pat<(sra GR16:$src1, (and CL, 31)),
4588 (SAR16rCL GR16:$src1)>;
4589 def : Pat<(sra GR32:$src1, (and CL, 31)),
4590 (SAR32rCL GR32:$src1)>;
4591 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4592 (SAR8mCL addr:$dst)>;
4593 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4594 (SAR16mCL addr:$dst)>;
4595 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4596 (SAR32mCL addr:$dst)>;
4598 // (anyext (setcc_carry)) -> (setcc_carry)
4599 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4601 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4603 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
4606 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
4607 let AddedComplexity = 5 in { // Try this before the selecting to OR
4608 def : Pat<(or_is_add GR16:$src1, imm:$src2),
4609 (ADD16ri GR16:$src1, imm:$src2)>;
4610 def : Pat<(or_is_add GR32:$src1, imm:$src2),
4611 (ADD32ri GR32:$src1, imm:$src2)>;
4612 def : Pat<(or_is_add GR16:$src1, i16immSExt8:$src2),
4613 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4614 def : Pat<(or_is_add GR32:$src1, i32immSExt8:$src2),
4615 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4616 def : Pat<(or_is_add GR16:$src1, GR16:$src2),
4617 (ADD16rr GR16:$src1, GR16:$src2)>;
4618 def : Pat<(or_is_add GR32:$src1, GR32:$src2),
4619 (ADD32rr GR32:$src1, GR32:$src2)>;
4620 } // AddedComplexity
4622 //===----------------------------------------------------------------------===//
4623 // EFLAGS-defining Patterns
4624 //===----------------------------------------------------------------------===//
4627 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
4628 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
4629 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
4632 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
4633 (ADD8rm GR8:$src1, addr:$src2)>;
4634 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
4635 (ADD16rm GR16:$src1, addr:$src2)>;
4636 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
4637 (ADD32rm GR32:$src1, addr:$src2)>;
4640 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
4641 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
4642 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
4643 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
4644 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4645 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
4646 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4649 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
4650 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
4651 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
4654 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
4655 (SUB8rm GR8:$src1, addr:$src2)>;
4656 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
4657 (SUB16rm GR16:$src1, addr:$src2)>;
4658 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
4659 (SUB32rm GR32:$src1, addr:$src2)>;
4662 def : Pat<(sub GR8:$src1, imm:$src2),
4663 (SUB8ri GR8:$src1, imm:$src2)>;
4664 def : Pat<(sub GR16:$src1, imm:$src2),
4665 (SUB16ri GR16:$src1, imm:$src2)>;
4666 def : Pat<(sub GR32:$src1, imm:$src2),
4667 (SUB32ri GR32:$src1, imm:$src2)>;
4668 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
4669 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4670 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
4671 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4674 def : Pat<(mul GR16:$src1, GR16:$src2),
4675 (IMUL16rr GR16:$src1, GR16:$src2)>;
4676 def : Pat<(mul GR32:$src1, GR32:$src2),
4677 (IMUL32rr GR32:$src1, GR32:$src2)>;
4680 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
4681 (IMUL16rm GR16:$src1, addr:$src2)>;
4682 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
4683 (IMUL32rm GR32:$src1, addr:$src2)>;
4686 def : Pat<(mul GR16:$src1, imm:$src2),
4687 (IMUL16rri GR16:$src1, imm:$src2)>;
4688 def : Pat<(mul GR32:$src1, imm:$src2),
4689 (IMUL32rri GR32:$src1, imm:$src2)>;
4690 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
4691 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4692 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
4693 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4695 // reg = mul mem, imm
4696 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
4697 (IMUL16rmi addr:$src1, imm:$src2)>;
4698 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
4699 (IMUL32rmi addr:$src1, imm:$src2)>;
4700 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
4701 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4702 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
4703 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4705 // Optimize multiply by 2 with EFLAGS result.
4706 let AddedComplexity = 2 in {
4707 def : Pat<(X86smul_flag GR16:$src1, 2), (ADD16rr GR16:$src1, GR16:$src1)>;
4708 def : Pat<(X86smul_flag GR32:$src1, 2), (ADD32rr GR32:$src1, GR32:$src1)>;
4711 // Patterns for nodes that do not produce flags, for instructions that do.
4714 def : Pat<(add GR8:$src , 1), (INC8r GR8:$src)>;
4715 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>;
4716 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>;
4719 def : Pat<(add GR8:$src , -1), (DEC8r GR8:$src)>;
4720 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
4721 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
4724 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
4725 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
4726 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
4729 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
4730 (OR8rm GR8:$src1, addr:$src2)>;
4731 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
4732 (OR16rm GR16:$src1, addr:$src2)>;
4733 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
4734 (OR32rm GR32:$src1, addr:$src2)>;
4737 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
4738 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
4739 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
4740 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
4741 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4742 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
4743 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4746 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
4747 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
4748 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
4751 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
4752 (XOR8rm GR8:$src1, addr:$src2)>;
4753 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
4754 (XOR16rm GR16:$src1, addr:$src2)>;
4755 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
4756 (XOR32rm GR32:$src1, addr:$src2)>;
4759 def : Pat<(xor GR8:$src1, imm:$src2),
4760 (XOR8ri GR8:$src1, imm:$src2)>;
4761 def : Pat<(xor GR16:$src1, imm:$src2),
4762 (XOR16ri GR16:$src1, imm:$src2)>;
4763 def : Pat<(xor GR32:$src1, imm:$src2),
4764 (XOR32ri GR32:$src1, imm:$src2)>;
4765 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
4766 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4767 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
4768 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4771 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
4772 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
4773 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
4776 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
4777 (AND8rm GR8:$src1, addr:$src2)>;
4778 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
4779 (AND16rm GR16:$src1, addr:$src2)>;
4780 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
4781 (AND32rm GR32:$src1, addr:$src2)>;
4784 def : Pat<(and GR8:$src1, imm:$src2),
4785 (AND8ri GR8:$src1, imm:$src2)>;
4786 def : Pat<(and GR16:$src1, imm:$src2),
4787 (AND16ri GR16:$src1, imm:$src2)>;
4788 def : Pat<(and GR32:$src1, imm:$src2),
4789 (AND32ri GR32:$src1, imm:$src2)>;
4790 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
4791 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
4792 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
4793 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
4795 //===----------------------------------------------------------------------===//
4796 // Floating Point Stack Support
4797 //===----------------------------------------------------------------------===//
4799 include "X86InstrFPStack.td"
4801 //===----------------------------------------------------------------------===//
4803 //===----------------------------------------------------------------------===//
4805 include "X86Instr64bit.td"
4807 //===----------------------------------------------------------------------===//
4808 // SIMD support (SSE, MMX and AVX)
4809 //===----------------------------------------------------------------------===//
4811 include "X86InstrFragmentsSIMD.td"
4813 //===----------------------------------------------------------------------===//
4814 // XMM Floating point support (requires SSE / SSE2)
4815 //===----------------------------------------------------------------------===//
4817 include "X86InstrSSE.td"
4819 //===----------------------------------------------------------------------===//
4820 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
4821 //===----------------------------------------------------------------------===//
4823 include "X86InstrMMX.td"