1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
33 def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
37 def SDTX86BrCond : SDTypeProfile<0, 3,
38 [SDTCisVT<0, OtherVT>,
39 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
41 def SDTX86SetCC : SDTypeProfile<1, 2,
43 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
47 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
49 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
50 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
51 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
53 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
54 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
57 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
59 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
61 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
63 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
65 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
67 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
69 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
71 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
73 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
74 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
75 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
76 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
78 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
80 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
82 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
83 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
85 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
87 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
88 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
90 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
91 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
93 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
94 [SDNPHasChain, SDNPMayStore,
95 SDNPMayLoad, SDNPMemOperand]>;
96 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
97 [SDNPHasChain, SDNPMayStore,
98 SDNPMayLoad, SDNPMemOperand]>;
99 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
100 [SDNPHasChain, SDNPMayStore,
101 SDNPMayLoad, SDNPMemOperand]>;
102 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
103 [SDNPHasChain, SDNPMayStore,
104 SDNPMayLoad, SDNPMemOperand]>;
105 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
106 [SDNPHasChain, SDNPMayStore,
107 SDNPMayLoad, SDNPMemOperand]>;
108 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
109 [SDNPHasChain, SDNPMayStore,
110 SDNPMayLoad, SDNPMemOperand]>;
111 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
112 [SDNPHasChain, SDNPMayStore,
113 SDNPMayLoad, SDNPMemOperand]>;
114 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
115 [SDNPHasChain, SDNPOptInFlag]>;
117 def X86callseq_start :
118 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
119 [SDNPHasChain, SDNPOutFlag]>;
121 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
122 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
124 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
125 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
127 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
128 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
130 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
131 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
132 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
133 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
136 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
137 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
139 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
140 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
142 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
143 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
144 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
145 SDT_X86SegmentBaseAddress, []>;
147 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
150 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
151 [SDNPHasChain, SDNPOptInFlag]>;
153 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags>;
154 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
155 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags>;
156 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>;
157 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
158 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
160 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
162 //===----------------------------------------------------------------------===//
163 // X86 Operand Definitions.
166 def i32imm_pcrel : Operand<i32> {
167 let PrintMethod = "print_pcrel_imm";
171 // *mem - Operand definitions for the funky X86 addressing mode operands.
173 class X86MemOperand<string printMethod> : Operand<iPTR> {
174 let PrintMethod = printMethod;
175 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm);
178 def i8mem : X86MemOperand<"printi8mem">;
179 def i16mem : X86MemOperand<"printi16mem">;
180 def i32mem : X86MemOperand<"printi32mem">;
181 def i64mem : X86MemOperand<"printi64mem">;
182 def i128mem : X86MemOperand<"printi128mem">;
183 def f32mem : X86MemOperand<"printf32mem">;
184 def f64mem : X86MemOperand<"printf64mem">;
185 def f80mem : X86MemOperand<"printf80mem">;
186 def f128mem : X86MemOperand<"printf128mem">;
188 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
189 // plain GR64, so that it doesn't potentially require a REX prefix.
190 def i8mem_NOREX : Operand<i64> {
191 let PrintMethod = "printi8mem";
192 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX, i32imm, i8imm);
195 def lea32mem : Operand<i32> {
196 let PrintMethod = "printlea32mem";
197 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
200 def SSECC : Operand<i8> {
201 let PrintMethod = "printSSECC";
204 def piclabel: Operand<i32> {
205 let PrintMethod = "printPICLabel";
208 // A couple of more descriptive operand definitions.
209 // 16-bits but only 8 bits are significant.
210 def i16i8imm : Operand<i16>;
211 // 32-bits but only 8 bits are significant.
212 def i32i8imm : Operand<i32>;
214 // Branch targets have OtherVT type and print as pc-relative values.
215 def brtarget : Operand<OtherVT> {
216 let PrintMethod = "print_pcrel_imm";
219 //===----------------------------------------------------------------------===//
220 // X86 Complex Pattern Definitions.
223 // Define X86 specific addressing mode.
224 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
225 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
226 [add, sub, mul, shl, or, frameindex], []>;
227 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
228 [tglobaltlsaddr], []>;
230 //===----------------------------------------------------------------------===//
231 // X86 Instruction Predicate Definitions.
232 def HasMMX : Predicate<"Subtarget->hasMMX()">;
233 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
234 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
235 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
236 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
237 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
238 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
239 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
240 def HasAVX : Predicate<"Subtarget->hasAVX()">;
241 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
242 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
243 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
244 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
245 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
246 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
247 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
248 def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
249 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
250 def OptForSpeed : Predicate<"!OptForSize">;
251 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
252 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
254 //===----------------------------------------------------------------------===//
255 // X86 Instruction Format Definitions.
258 include "X86InstrFormats.td"
260 //===----------------------------------------------------------------------===//
261 // Pattern fragments...
264 // X86 specific condition code. These correspond to CondCode in
265 // X86InstrInfo.h. They must be kept in synch.
266 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
267 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
268 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
269 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
270 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
271 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
272 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
273 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
274 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
275 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
276 def X86_COND_NO : PatLeaf<(i8 10)>;
277 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
278 def X86_COND_NS : PatLeaf<(i8 12)>;
279 def X86_COND_O : PatLeaf<(i8 13)>;
280 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
281 def X86_COND_S : PatLeaf<(i8 15)>;
283 def i16immSExt8 : PatLeaf<(i16 imm), [{
284 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
285 // sign extended field.
286 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
289 def i32immSExt8 : PatLeaf<(i32 imm), [{
290 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
291 // sign extended field.
292 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
295 // Helper fragments for loads.
296 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
297 // known to be 32-bit aligned or better. Ditto for i8 to i16.
298 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
299 LoadSDNode *LD = cast<LoadSDNode>(N);
300 if (const Value *Src = LD->getSrcValue())
301 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
302 if (PT->getAddressSpace() > 255)
304 ISD::LoadExtType ExtType = LD->getExtensionType();
305 if (ExtType == ISD::NON_EXTLOAD)
307 if (ExtType == ISD::EXTLOAD)
308 return LD->getAlignment() >= 2 && !LD->isVolatile();
312 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
313 LoadSDNode *LD = cast<LoadSDNode>(N);
314 if (const Value *Src = LD->getSrcValue())
315 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
316 if (PT->getAddressSpace() > 255)
318 ISD::LoadExtType ExtType = LD->getExtensionType();
319 if (ExtType == ISD::EXTLOAD)
320 return LD->getAlignment() >= 2 && !LD->isVolatile();
324 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
325 LoadSDNode *LD = cast<LoadSDNode>(N);
326 if (const Value *Src = LD->getSrcValue())
327 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
328 if (PT->getAddressSpace() > 255)
330 ISD::LoadExtType ExtType = LD->getExtensionType();
331 if (ExtType == ISD::NON_EXTLOAD)
333 if (ExtType == ISD::EXTLOAD)
334 return LD->getAlignment() >= 4 && !LD->isVolatile();
338 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
339 LoadSDNode *LD = cast<LoadSDNode>(N);
340 if (const Value *Src = LD->getSrcValue())
341 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
342 if (PT->getAddressSpace() > 255)
344 if (LD->isVolatile())
346 ISD::LoadExtType ExtType = LD->getExtensionType();
347 if (ExtType == ISD::NON_EXTLOAD)
349 if (ExtType == ISD::EXTLOAD)
350 return LD->getAlignment() >= 4;
354 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
355 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
356 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
357 return PT->getAddressSpace() == 256;
361 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
362 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
363 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
364 return PT->getAddressSpace() == 257;
368 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{
369 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
370 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
371 if (PT->getAddressSpace() > 255)
375 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{
376 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
377 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
378 if (PT->getAddressSpace() > 255)
383 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{
384 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
385 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
386 if (PT->getAddressSpace() > 255)
390 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{
391 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
392 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
393 if (PT->getAddressSpace() > 255)
397 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{
398 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
399 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
400 if (PT->getAddressSpace() > 255)
405 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
406 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
407 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
409 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
410 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
411 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
412 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
413 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
414 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
416 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
417 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
418 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
419 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
420 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
421 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
424 // An 'and' node with a single use.
425 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
426 return N->hasOneUse();
428 // An 'srl' node with a single use.
429 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
430 return N->hasOneUse();
432 // An 'trunc' node with a single use.
433 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
434 return N->hasOneUse();
437 // 'shld' and 'shrd' instruction patterns. Note that even though these have
438 // the srl and shl in their patterns, the C++ code must still check for them,
439 // because predicates are tested before children nodes are explored.
441 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
442 (or (srl node:$src1, node:$amt1),
443 (shl node:$src2, node:$amt2)), [{
444 assert(N->getOpcode() == ISD::OR);
445 return N->getOperand(0).getOpcode() == ISD::SRL &&
446 N->getOperand(1).getOpcode() == ISD::SHL &&
447 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
448 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
449 N->getOperand(0).getConstantOperandVal(1) ==
450 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
453 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
454 (or (shl node:$src1, node:$amt1),
455 (srl node:$src2, node:$amt2)), [{
456 assert(N->getOpcode() == ISD::OR);
457 return N->getOperand(0).getOpcode() == ISD::SHL &&
458 N->getOperand(1).getOpcode() == ISD::SRL &&
459 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
460 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
461 N->getOperand(0).getConstantOperandVal(1) ==
462 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
465 //===----------------------------------------------------------------------===//
466 // Instruction list...
469 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
470 // a stack adjustment and the codegen must know that they may modify the stack
471 // pointer before prolog-epilog rewriting occurs.
472 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
473 // sub / add which can clobber EFLAGS.
474 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
475 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
477 [(X86callseq_start timm:$amt)]>,
478 Requires<[In32BitMode]>;
479 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
481 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
482 Requires<[In32BitMode]>;
486 let neverHasSideEffects = 1 in
487 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
490 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
491 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
495 //===----------------------------------------------------------------------===//
496 // Control Flow Instructions...
499 // Return instructions.
500 let isTerminator = 1, isReturn = 1, isBarrier = 1,
501 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
502 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
505 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
507 [(X86retflag imm:$amt)]>;
510 // All branches are RawFrm, Void, Branch, and Terminators
511 let isBranch = 1, isTerminator = 1 in
512 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
513 I<opcode, RawFrm, (outs), ins, asm, pattern>;
515 let isBranch = 1, isBarrier = 1 in
516 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
519 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
520 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
521 [(brind GR32:$dst)]>;
522 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
523 [(brind (loadi32 addr:$dst))]>;
526 // Conditional branches
527 let Uses = [EFLAGS] in {
528 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
529 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
530 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
531 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
532 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
533 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
534 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
535 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
536 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
537 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
538 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
539 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
541 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
542 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
543 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
544 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
545 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
546 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
547 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
548 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
550 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
551 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
552 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
553 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
554 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
555 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
556 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
557 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
558 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
559 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
560 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
561 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
564 //===----------------------------------------------------------------------===//
565 // Call Instructions...
568 // All calls clobber the non-callee saved registers. ESP is marked as
569 // a use to prevent stack-pointer assignments that appear immediately
570 // before calls from potentially appearing dead. Uses for argument
571 // registers are added manually.
572 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
573 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
574 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
575 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
577 def CALLpcrel32 : Ii32<0xE8, RawFrm,
578 (outs), (ins i32imm_pcrel:$dst,variable_ops),
580 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
581 "call\t{*}$dst", [(X86call GR32:$dst)]>;
582 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
583 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
588 def TAILCALL : I<0, Pseudo, (outs), (ins),
592 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
593 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops),
594 "#TC_RETURN $dst $offset",
597 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
598 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops),
599 "#TC_RETURN $dst $offset",
602 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
604 def TAILJMPd : IBr<0xE9, (ins i32imm_pcrel:$dst), "jmp\t$dst # TAILCALL",
606 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
607 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
609 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
610 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
611 "jmp\t{*}$dst # TAILCALL", []>;
613 //===----------------------------------------------------------------------===//
614 // Miscellaneous Instructions...
616 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
617 def LEAVE : I<0xC9, RawFrm,
618 (outs), (ins), "leave", []>;
620 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
622 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
625 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
628 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
629 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
630 "push{l}\t$imm", []>;
631 def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
632 "push{l}\t$imm", []>;
633 def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
634 "push{l}\t$imm", []>;
637 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
638 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
639 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
640 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
642 let isTwoAddress = 1 in // GR32 = bswap GR32
643 def BSWAP32r : I<0xC8, AddRegFrm,
644 (outs GR32:$dst), (ins GR32:$src),
646 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
649 // Bit scan instructions.
650 let Defs = [EFLAGS] in {
651 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
652 "bsf{w}\t{$src, $dst|$dst, $src}",
653 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
654 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
655 "bsf{w}\t{$src, $dst|$dst, $src}",
656 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
657 (implicit EFLAGS)]>, TB;
658 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
659 "bsf{l}\t{$src, $dst|$dst, $src}",
660 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
661 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
662 "bsf{l}\t{$src, $dst|$dst, $src}",
663 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
664 (implicit EFLAGS)]>, TB;
666 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
667 "bsr{w}\t{$src, $dst|$dst, $src}",
668 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
669 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
670 "bsr{w}\t{$src, $dst|$dst, $src}",
671 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
672 (implicit EFLAGS)]>, TB;
673 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
674 "bsr{l}\t{$src, $dst|$dst, $src}",
675 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
676 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
677 "bsr{l}\t{$src, $dst|$dst, $src}",
678 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
679 (implicit EFLAGS)]>, TB;
682 let neverHasSideEffects = 1 in
683 def LEA16r : I<0x8D, MRMSrcMem,
684 (outs GR16:$dst), (ins i32mem:$src),
685 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
686 let isReMaterializable = 1 in
687 def LEA32r : I<0x8D, MRMSrcMem,
688 (outs GR32:$dst), (ins lea32mem:$src),
689 "lea{l}\t{$src|$dst}, {$dst|$src}",
690 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
692 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
693 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
694 [(X86rep_movs i8)]>, REP;
695 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
696 [(X86rep_movs i16)]>, REP, OpSize;
697 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
698 [(X86rep_movs i32)]>, REP;
701 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
702 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
703 [(X86rep_stos i8)]>, REP;
704 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
705 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
706 [(X86rep_stos i16)]>, REP, OpSize;
707 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
708 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
709 [(X86rep_stos i32)]>, REP;
711 let Defs = [RAX, RDX] in
712 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
715 let isBarrier = 1, hasCtrlDep = 1 in {
716 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
719 //===----------------------------------------------------------------------===//
720 // Input/Output Instructions...
722 let Defs = [AL], Uses = [DX] in
723 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
724 "in{b}\t{%dx, %al|%AL, %DX}", []>;
725 let Defs = [AX], Uses = [DX] in
726 def IN16rr : I<0xED, RawFrm, (outs), (ins),
727 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
728 let Defs = [EAX], Uses = [DX] in
729 def IN32rr : I<0xED, RawFrm, (outs), (ins),
730 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
733 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
734 "in{b}\t{$port, %al|%AL, $port}", []>;
736 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
737 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
739 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
740 "in{l}\t{$port, %eax|%EAX, $port}", []>;
742 let Uses = [DX, AL] in
743 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
744 "out{b}\t{%al, %dx|%DX, %AL}", []>;
745 let Uses = [DX, AX] in
746 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
747 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
748 let Uses = [DX, EAX] in
749 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
750 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
753 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
754 "out{b}\t{%al, $port|$port, %AL}", []>;
756 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
757 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
759 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
760 "out{l}\t{%eax, $port|$port, %EAX}", []>;
762 //===----------------------------------------------------------------------===//
763 // Move Instructions...
765 let neverHasSideEffects = 1 in {
766 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
767 "mov{b}\t{$src, $dst|$dst, $src}", []>;
768 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
769 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
770 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
771 "mov{l}\t{$src, $dst|$dst, $src}", []>;
773 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
774 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
775 "mov{b}\t{$src, $dst|$dst, $src}",
776 [(set GR8:$dst, imm:$src)]>;
777 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
778 "mov{w}\t{$src, $dst|$dst, $src}",
779 [(set GR16:$dst, imm:$src)]>, OpSize;
780 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
781 "mov{l}\t{$src, $dst|$dst, $src}",
782 [(set GR32:$dst, imm:$src)]>;
784 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
785 "mov{b}\t{$src, $dst|$dst, $src}",
786 [(store (i8 imm:$src), addr:$dst)]>;
787 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
788 "mov{w}\t{$src, $dst|$dst, $src}",
789 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
790 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
791 "mov{l}\t{$src, $dst|$dst, $src}",
792 [(store (i32 imm:$src), addr:$dst)]>;
794 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
795 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
796 "mov{b}\t{$src, $dst|$dst, $src}",
797 [(set GR8:$dst, (loadi8 addr:$src))]>;
798 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
799 "mov{w}\t{$src, $dst|$dst, $src}",
800 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
801 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
802 "mov{l}\t{$src, $dst|$dst, $src}",
803 [(set GR32:$dst, (loadi32 addr:$src))]>;
806 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
807 "mov{b}\t{$src, $dst|$dst, $src}",
808 [(store GR8:$src, addr:$dst)]>;
809 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
810 "mov{w}\t{$src, $dst|$dst, $src}",
811 [(store GR16:$src, addr:$dst)]>, OpSize;
812 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
813 "mov{l}\t{$src, $dst|$dst, $src}",
814 [(store GR32:$src, addr:$dst)]>;
816 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
817 // that they can be used for copying and storing h registers, which can't be
818 // encoded when a REX prefix is present.
819 let neverHasSideEffects = 1 in
820 def MOV8rr_NOREX : I<0x88, MRMDestReg,
821 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
822 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
824 def MOV8mr_NOREX : I<0x88, MRMDestMem,
825 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
826 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
828 canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
829 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
830 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
831 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
833 //===----------------------------------------------------------------------===//
834 // Fixed-Register Multiplication and Division Instructions...
837 // Extra precision multiplication
838 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
839 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
840 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
841 // This probably ought to be moved to a def : Pat<> if the
842 // syntax can be accepted.
843 [(set AL, (mul AL, GR8:$src)),
844 (implicit EFLAGS)]>; // AL,AH = AL*GR8
846 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
847 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
849 []>, OpSize; // AX,DX = AX*GR16
851 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
852 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
854 []>; // EAX,EDX = EAX*GR32
856 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
857 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
859 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
860 // This probably ought to be moved to a def : Pat<> if the
861 // syntax can be accepted.
862 [(set AL, (mul AL, (loadi8 addr:$src))),
863 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
865 let mayLoad = 1, neverHasSideEffects = 1 in {
866 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
867 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
869 []>, OpSize; // AX,DX = AX*[mem16]
871 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
872 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
874 []>; // EAX,EDX = EAX*[mem32]
877 let neverHasSideEffects = 1 in {
878 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
879 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
881 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
882 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
883 OpSize; // AX,DX = AX*GR16
884 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
885 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
886 // EAX,EDX = EAX*GR32
888 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
889 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
890 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
891 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
892 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
893 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
894 let Defs = [EAX,EDX], Uses = [EAX] in
895 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
896 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
898 } // neverHasSideEffects
900 // unsigned division/remainder
901 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
902 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
904 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
905 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
906 "div{w}\t$src", []>, OpSize;
907 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
908 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
911 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
912 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
914 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
915 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
916 "div{w}\t$src", []>, OpSize;
917 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
918 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
922 // Signed division/remainder.
923 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
924 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
925 "idiv{b}\t$src", []>;
926 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
927 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
928 "idiv{w}\t$src", []>, OpSize;
929 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
930 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
931 "idiv{l}\t$src", []>;
932 let mayLoad = 1, mayLoad = 1 in {
933 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
934 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
935 "idiv{b}\t$src", []>;
936 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
937 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
938 "idiv{w}\t$src", []>, OpSize;
939 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
940 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
941 "idiv{l}\t$src", []>;
944 //===----------------------------------------------------------------------===//
945 // Two address Instructions.
947 let isTwoAddress = 1 in {
950 let Uses = [EFLAGS] in {
951 let isCommutable = 1 in {
952 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
953 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
954 "cmovb\t{$src2, $dst|$dst, $src2}",
955 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
956 X86_COND_B, EFLAGS))]>,
958 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
959 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
960 "cmovb\t{$src2, $dst|$dst, $src2}",
961 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
962 X86_COND_B, EFLAGS))]>,
964 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
965 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
966 "cmovae\t{$src2, $dst|$dst, $src2}",
967 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
968 X86_COND_AE, EFLAGS))]>,
970 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
971 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
972 "cmovae\t{$src2, $dst|$dst, $src2}",
973 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
974 X86_COND_AE, EFLAGS))]>,
976 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
977 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
978 "cmove\t{$src2, $dst|$dst, $src2}",
979 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
980 X86_COND_E, EFLAGS))]>,
982 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
983 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
984 "cmove\t{$src2, $dst|$dst, $src2}",
985 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
986 X86_COND_E, EFLAGS))]>,
988 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
989 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
990 "cmovne\t{$src2, $dst|$dst, $src2}",
991 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
992 X86_COND_NE, EFLAGS))]>,
994 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
995 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
996 "cmovne\t{$src2, $dst|$dst, $src2}",
997 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
998 X86_COND_NE, EFLAGS))]>,
1000 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1001 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1002 "cmovbe\t{$src2, $dst|$dst, $src2}",
1003 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1004 X86_COND_BE, EFLAGS))]>,
1006 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1007 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1008 "cmovbe\t{$src2, $dst|$dst, $src2}",
1009 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1010 X86_COND_BE, EFLAGS))]>,
1012 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1013 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1014 "cmova\t{$src2, $dst|$dst, $src2}",
1015 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1016 X86_COND_A, EFLAGS))]>,
1018 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1019 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1020 "cmova\t{$src2, $dst|$dst, $src2}",
1021 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1022 X86_COND_A, EFLAGS))]>,
1024 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1025 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1026 "cmovl\t{$src2, $dst|$dst, $src2}",
1027 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1028 X86_COND_L, EFLAGS))]>,
1030 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1031 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1032 "cmovl\t{$src2, $dst|$dst, $src2}",
1033 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1034 X86_COND_L, EFLAGS))]>,
1036 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1037 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1038 "cmovge\t{$src2, $dst|$dst, $src2}",
1039 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1040 X86_COND_GE, EFLAGS))]>,
1042 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1043 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1044 "cmovge\t{$src2, $dst|$dst, $src2}",
1045 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1046 X86_COND_GE, EFLAGS))]>,
1048 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1049 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1050 "cmovle\t{$src2, $dst|$dst, $src2}",
1051 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1052 X86_COND_LE, EFLAGS))]>,
1054 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1055 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1056 "cmovle\t{$src2, $dst|$dst, $src2}",
1057 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1058 X86_COND_LE, EFLAGS))]>,
1060 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1061 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1062 "cmovg\t{$src2, $dst|$dst, $src2}",
1063 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1064 X86_COND_G, EFLAGS))]>,
1066 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1067 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1068 "cmovg\t{$src2, $dst|$dst, $src2}",
1069 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1070 X86_COND_G, EFLAGS))]>,
1072 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1073 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1074 "cmovs\t{$src2, $dst|$dst, $src2}",
1075 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1076 X86_COND_S, EFLAGS))]>,
1078 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1079 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1080 "cmovs\t{$src2, $dst|$dst, $src2}",
1081 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1082 X86_COND_S, EFLAGS))]>,
1084 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1085 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1086 "cmovns\t{$src2, $dst|$dst, $src2}",
1087 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1088 X86_COND_NS, EFLAGS))]>,
1090 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1091 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1092 "cmovns\t{$src2, $dst|$dst, $src2}",
1093 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1094 X86_COND_NS, EFLAGS))]>,
1096 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1097 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1098 "cmovp\t{$src2, $dst|$dst, $src2}",
1099 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1100 X86_COND_P, EFLAGS))]>,
1102 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1103 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1104 "cmovp\t{$src2, $dst|$dst, $src2}",
1105 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1106 X86_COND_P, EFLAGS))]>,
1108 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1109 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1110 "cmovnp\t{$src2, $dst|$dst, $src2}",
1111 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1112 X86_COND_NP, EFLAGS))]>,
1114 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1115 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1116 "cmovnp\t{$src2, $dst|$dst, $src2}",
1117 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1118 X86_COND_NP, EFLAGS))]>,
1120 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1121 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1122 "cmovo\t{$src2, $dst|$dst, $src2}",
1123 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1124 X86_COND_O, EFLAGS))]>,
1126 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1127 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1128 "cmovo\t{$src2, $dst|$dst, $src2}",
1129 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1130 X86_COND_O, EFLAGS))]>,
1132 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1133 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1134 "cmovno\t{$src2, $dst|$dst, $src2}",
1135 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1136 X86_COND_NO, EFLAGS))]>,
1138 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1139 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1140 "cmovno\t{$src2, $dst|$dst, $src2}",
1141 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1142 X86_COND_NO, EFLAGS))]>,
1144 } // isCommutable = 1
1146 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1147 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1148 "cmovb\t{$src2, $dst|$dst, $src2}",
1149 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1150 X86_COND_B, EFLAGS))]>,
1152 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1153 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1154 "cmovb\t{$src2, $dst|$dst, $src2}",
1155 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1156 X86_COND_B, EFLAGS))]>,
1158 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1159 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1160 "cmovae\t{$src2, $dst|$dst, $src2}",
1161 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1162 X86_COND_AE, EFLAGS))]>,
1164 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1165 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1166 "cmovae\t{$src2, $dst|$dst, $src2}",
1167 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1168 X86_COND_AE, EFLAGS))]>,
1170 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1171 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1172 "cmove\t{$src2, $dst|$dst, $src2}",
1173 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1174 X86_COND_E, EFLAGS))]>,
1176 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1177 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1178 "cmove\t{$src2, $dst|$dst, $src2}",
1179 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1180 X86_COND_E, EFLAGS))]>,
1182 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1183 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1184 "cmovne\t{$src2, $dst|$dst, $src2}",
1185 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1186 X86_COND_NE, EFLAGS))]>,
1188 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1189 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1190 "cmovne\t{$src2, $dst|$dst, $src2}",
1191 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1192 X86_COND_NE, EFLAGS))]>,
1194 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1195 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1196 "cmovbe\t{$src2, $dst|$dst, $src2}",
1197 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1198 X86_COND_BE, EFLAGS))]>,
1200 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1201 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1202 "cmovbe\t{$src2, $dst|$dst, $src2}",
1203 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1204 X86_COND_BE, EFLAGS))]>,
1206 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1207 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1208 "cmova\t{$src2, $dst|$dst, $src2}",
1209 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1210 X86_COND_A, EFLAGS))]>,
1212 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1213 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1214 "cmova\t{$src2, $dst|$dst, $src2}",
1215 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1216 X86_COND_A, EFLAGS))]>,
1218 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1219 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1220 "cmovl\t{$src2, $dst|$dst, $src2}",
1221 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1222 X86_COND_L, EFLAGS))]>,
1224 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1225 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1226 "cmovl\t{$src2, $dst|$dst, $src2}",
1227 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1228 X86_COND_L, EFLAGS))]>,
1230 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1231 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1232 "cmovge\t{$src2, $dst|$dst, $src2}",
1233 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1234 X86_COND_GE, EFLAGS))]>,
1236 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1237 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1238 "cmovge\t{$src2, $dst|$dst, $src2}",
1239 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1240 X86_COND_GE, EFLAGS))]>,
1242 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1243 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1244 "cmovle\t{$src2, $dst|$dst, $src2}",
1245 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1246 X86_COND_LE, EFLAGS))]>,
1248 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1249 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1250 "cmovle\t{$src2, $dst|$dst, $src2}",
1251 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1252 X86_COND_LE, EFLAGS))]>,
1254 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1255 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1256 "cmovg\t{$src2, $dst|$dst, $src2}",
1257 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1258 X86_COND_G, EFLAGS))]>,
1260 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1261 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1262 "cmovg\t{$src2, $dst|$dst, $src2}",
1263 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1264 X86_COND_G, EFLAGS))]>,
1266 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1267 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1268 "cmovs\t{$src2, $dst|$dst, $src2}",
1269 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1270 X86_COND_S, EFLAGS))]>,
1272 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1273 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1274 "cmovs\t{$src2, $dst|$dst, $src2}",
1275 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1276 X86_COND_S, EFLAGS))]>,
1278 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1279 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1280 "cmovns\t{$src2, $dst|$dst, $src2}",
1281 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1282 X86_COND_NS, EFLAGS))]>,
1284 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1285 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1286 "cmovns\t{$src2, $dst|$dst, $src2}",
1287 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1288 X86_COND_NS, EFLAGS))]>,
1290 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1291 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1292 "cmovp\t{$src2, $dst|$dst, $src2}",
1293 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1294 X86_COND_P, EFLAGS))]>,
1296 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1297 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1298 "cmovp\t{$src2, $dst|$dst, $src2}",
1299 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1300 X86_COND_P, EFLAGS))]>,
1302 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1303 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1304 "cmovnp\t{$src2, $dst|$dst, $src2}",
1305 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1306 X86_COND_NP, EFLAGS))]>,
1308 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1309 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1310 "cmovnp\t{$src2, $dst|$dst, $src2}",
1311 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1312 X86_COND_NP, EFLAGS))]>,
1314 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1315 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1316 "cmovo\t{$src2, $dst|$dst, $src2}",
1317 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1318 X86_COND_O, EFLAGS))]>,
1320 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1321 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1322 "cmovo\t{$src2, $dst|$dst, $src2}",
1323 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1324 X86_COND_O, EFLAGS))]>,
1326 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1327 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1328 "cmovno\t{$src2, $dst|$dst, $src2}",
1329 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1330 X86_COND_NO, EFLAGS))]>,
1332 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1333 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1334 "cmovno\t{$src2, $dst|$dst, $src2}",
1335 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1336 X86_COND_NO, EFLAGS))]>,
1338 } // Uses = [EFLAGS]
1341 // unary instructions
1342 let CodeSize = 2 in {
1343 let Defs = [EFLAGS] in {
1344 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1345 [(set GR8:$dst, (ineg GR8:$src)),
1346 (implicit EFLAGS)]>;
1347 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1348 [(set GR16:$dst, (ineg GR16:$src)),
1349 (implicit EFLAGS)]>, OpSize;
1350 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1351 [(set GR32:$dst, (ineg GR32:$src)),
1352 (implicit EFLAGS)]>;
1353 let isTwoAddress = 0 in {
1354 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1355 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1356 (implicit EFLAGS)]>;
1357 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1358 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1359 (implicit EFLAGS)]>, OpSize;
1360 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1361 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1362 (implicit EFLAGS)]>;
1364 } // Defs = [EFLAGS]
1366 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1367 let AddedComplexity = 15 in {
1368 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1369 [(set GR8:$dst, (not GR8:$src))]>;
1370 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1371 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1372 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1373 [(set GR32:$dst, (not GR32:$src))]>;
1375 let isTwoAddress = 0 in {
1376 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1377 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1378 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1379 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1380 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1381 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1385 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1386 let Defs = [EFLAGS] in {
1388 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1389 [(set GR8:$dst, (add GR8:$src, 1)),
1390 (implicit EFLAGS)]>;
1391 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1392 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1393 [(set GR16:$dst, (add GR16:$src, 1)),
1394 (implicit EFLAGS)]>,
1395 OpSize, Requires<[In32BitMode]>;
1396 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1397 [(set GR32:$dst, (add GR32:$src, 1)),
1398 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1400 let isTwoAddress = 0, CodeSize = 2 in {
1401 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1402 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1403 (implicit EFLAGS)]>;
1404 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1405 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1406 (implicit EFLAGS)]>,
1407 OpSize, Requires<[In32BitMode]>;
1408 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1409 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1410 (implicit EFLAGS)]>,
1411 Requires<[In32BitMode]>;
1415 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1416 [(set GR8:$dst, (add GR8:$src, -1)),
1417 (implicit EFLAGS)]>;
1418 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1419 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1420 [(set GR16:$dst, (add GR16:$src, -1)),
1421 (implicit EFLAGS)]>,
1422 OpSize, Requires<[In32BitMode]>;
1423 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1424 [(set GR32:$dst, (add GR32:$src, -1)),
1425 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1428 let isTwoAddress = 0, CodeSize = 2 in {
1429 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1430 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1431 (implicit EFLAGS)]>;
1432 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1433 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1434 (implicit EFLAGS)]>,
1435 OpSize, Requires<[In32BitMode]>;
1436 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1437 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1438 (implicit EFLAGS)]>,
1439 Requires<[In32BitMode]>;
1441 } // Defs = [EFLAGS]
1443 // Logical operators...
1444 let Defs = [EFLAGS] in {
1445 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1446 def AND8rr : I<0x20, MRMDestReg,
1447 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1448 "and{b}\t{$src2, $dst|$dst, $src2}",
1449 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
1450 (implicit EFLAGS)]>;
1451 def AND16rr : I<0x21, MRMDestReg,
1452 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1453 "and{w}\t{$src2, $dst|$dst, $src2}",
1454 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
1455 (implicit EFLAGS)]>, OpSize;
1456 def AND32rr : I<0x21, MRMDestReg,
1457 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1458 "and{l}\t{$src2, $dst|$dst, $src2}",
1459 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
1460 (implicit EFLAGS)]>;
1463 def AND8rm : I<0x22, MRMSrcMem,
1464 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1465 "and{b}\t{$src2, $dst|$dst, $src2}",
1466 [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
1467 (implicit EFLAGS)]>;
1468 def AND16rm : I<0x23, MRMSrcMem,
1469 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1470 "and{w}\t{$src2, $dst|$dst, $src2}",
1471 [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
1472 (implicit EFLAGS)]>, OpSize;
1473 def AND32rm : I<0x23, MRMSrcMem,
1474 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1475 "and{l}\t{$src2, $dst|$dst, $src2}",
1476 [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
1477 (implicit EFLAGS)]>;
1479 def AND8ri : Ii8<0x80, MRM4r,
1480 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1481 "and{b}\t{$src2, $dst|$dst, $src2}",
1482 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
1483 (implicit EFLAGS)]>;
1484 def AND16ri : Ii16<0x81, MRM4r,
1485 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1486 "and{w}\t{$src2, $dst|$dst, $src2}",
1487 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
1488 (implicit EFLAGS)]>, OpSize;
1489 def AND32ri : Ii32<0x81, MRM4r,
1490 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1491 "and{l}\t{$src2, $dst|$dst, $src2}",
1492 [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
1493 (implicit EFLAGS)]>;
1494 def AND16ri8 : Ii8<0x83, MRM4r,
1495 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1496 "and{w}\t{$src2, $dst|$dst, $src2}",
1497 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
1498 (implicit EFLAGS)]>,
1500 def AND32ri8 : Ii8<0x83, MRM4r,
1501 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1502 "and{l}\t{$src2, $dst|$dst, $src2}",
1503 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
1504 (implicit EFLAGS)]>;
1506 let isTwoAddress = 0 in {
1507 def AND8mr : I<0x20, MRMDestMem,
1508 (outs), (ins i8mem :$dst, GR8 :$src),
1509 "and{b}\t{$src, $dst|$dst, $src}",
1510 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1511 (implicit EFLAGS)]>;
1512 def AND16mr : I<0x21, MRMDestMem,
1513 (outs), (ins i16mem:$dst, GR16:$src),
1514 "and{w}\t{$src, $dst|$dst, $src}",
1515 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1516 (implicit EFLAGS)]>,
1518 def AND32mr : I<0x21, MRMDestMem,
1519 (outs), (ins i32mem:$dst, GR32:$src),
1520 "and{l}\t{$src, $dst|$dst, $src}",
1521 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1522 (implicit EFLAGS)]>;
1523 def AND8mi : Ii8<0x80, MRM4m,
1524 (outs), (ins i8mem :$dst, i8imm :$src),
1525 "and{b}\t{$src, $dst|$dst, $src}",
1526 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1527 (implicit EFLAGS)]>;
1528 def AND16mi : Ii16<0x81, MRM4m,
1529 (outs), (ins i16mem:$dst, i16imm:$src),
1530 "and{w}\t{$src, $dst|$dst, $src}",
1531 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1532 (implicit EFLAGS)]>,
1534 def AND32mi : Ii32<0x81, MRM4m,
1535 (outs), (ins i32mem:$dst, i32imm:$src),
1536 "and{l}\t{$src, $dst|$dst, $src}",
1537 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1538 (implicit EFLAGS)]>;
1539 def AND16mi8 : Ii8<0x83, MRM4m,
1540 (outs), (ins i16mem:$dst, i16i8imm :$src),
1541 "and{w}\t{$src, $dst|$dst, $src}",
1542 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1543 (implicit EFLAGS)]>,
1545 def AND32mi8 : Ii8<0x83, MRM4m,
1546 (outs), (ins i32mem:$dst, i32i8imm :$src),
1547 "and{l}\t{$src, $dst|$dst, $src}",
1548 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1549 (implicit EFLAGS)]>;
1553 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1554 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1555 "or{b}\t{$src2, $dst|$dst, $src2}",
1556 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
1557 (implicit EFLAGS)]>;
1558 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1559 "or{w}\t{$src2, $dst|$dst, $src2}",
1560 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
1561 (implicit EFLAGS)]>, OpSize;
1562 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1563 "or{l}\t{$src2, $dst|$dst, $src2}",
1564 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
1565 (implicit EFLAGS)]>;
1567 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1568 "or{b}\t{$src2, $dst|$dst, $src2}",
1569 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
1570 (implicit EFLAGS)]>;
1571 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1572 "or{w}\t{$src2, $dst|$dst, $src2}",
1573 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
1574 (implicit EFLAGS)]>, OpSize;
1575 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1576 "or{l}\t{$src2, $dst|$dst, $src2}",
1577 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
1578 (implicit EFLAGS)]>;
1580 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1581 "or{b}\t{$src2, $dst|$dst, $src2}",
1582 [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
1583 (implicit EFLAGS)]>;
1584 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1585 "or{w}\t{$src2, $dst|$dst, $src2}",
1586 [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
1587 (implicit EFLAGS)]>, OpSize;
1588 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1589 "or{l}\t{$src2, $dst|$dst, $src2}",
1590 [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
1591 (implicit EFLAGS)]>;
1593 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1594 "or{w}\t{$src2, $dst|$dst, $src2}",
1595 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
1596 (implicit EFLAGS)]>, OpSize;
1597 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1598 "or{l}\t{$src2, $dst|$dst, $src2}",
1599 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
1600 (implicit EFLAGS)]>;
1601 let isTwoAddress = 0 in {
1602 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1603 "or{b}\t{$src, $dst|$dst, $src}",
1604 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1605 (implicit EFLAGS)]>;
1606 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1607 "or{w}\t{$src, $dst|$dst, $src}",
1608 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1609 (implicit EFLAGS)]>, OpSize;
1610 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1611 "or{l}\t{$src, $dst|$dst, $src}",
1612 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1613 (implicit EFLAGS)]>;
1614 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1615 "or{b}\t{$src, $dst|$dst, $src}",
1616 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1617 (implicit EFLAGS)]>;
1618 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1619 "or{w}\t{$src, $dst|$dst, $src}",
1620 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1621 (implicit EFLAGS)]>,
1623 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1624 "or{l}\t{$src, $dst|$dst, $src}",
1625 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1626 (implicit EFLAGS)]>;
1627 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1628 "or{w}\t{$src, $dst|$dst, $src}",
1629 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1630 (implicit EFLAGS)]>,
1632 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1633 "or{l}\t{$src, $dst|$dst, $src}",
1634 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1635 (implicit EFLAGS)]>;
1636 } // isTwoAddress = 0
1639 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1640 def XOR8rr : I<0x30, MRMDestReg,
1641 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1642 "xor{b}\t{$src2, $dst|$dst, $src2}",
1643 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
1644 (implicit EFLAGS)]>;
1645 def XOR16rr : I<0x31, MRMDestReg,
1646 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1647 "xor{w}\t{$src2, $dst|$dst, $src2}",
1648 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
1649 (implicit EFLAGS)]>, OpSize;
1650 def XOR32rr : I<0x31, MRMDestReg,
1651 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1652 "xor{l}\t{$src2, $dst|$dst, $src2}",
1653 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
1654 (implicit EFLAGS)]>;
1655 } // isCommutable = 1
1657 def XOR8rm : I<0x32, MRMSrcMem ,
1658 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1659 "xor{b}\t{$src2, $dst|$dst, $src2}",
1660 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
1661 (implicit EFLAGS)]>;
1662 def XOR16rm : I<0x33, MRMSrcMem ,
1663 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1664 "xor{w}\t{$src2, $dst|$dst, $src2}",
1665 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
1666 (implicit EFLAGS)]>,
1668 def XOR32rm : I<0x33, MRMSrcMem ,
1669 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1670 "xor{l}\t{$src2, $dst|$dst, $src2}",
1671 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
1672 (implicit EFLAGS)]>;
1674 def XOR8ri : Ii8<0x80, MRM6r,
1675 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1676 "xor{b}\t{$src2, $dst|$dst, $src2}",
1677 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
1678 (implicit EFLAGS)]>;
1679 def XOR16ri : Ii16<0x81, MRM6r,
1680 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1681 "xor{w}\t{$src2, $dst|$dst, $src2}",
1682 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
1683 (implicit EFLAGS)]>, OpSize;
1684 def XOR32ri : Ii32<0x81, MRM6r,
1685 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1686 "xor{l}\t{$src2, $dst|$dst, $src2}",
1687 [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
1688 (implicit EFLAGS)]>;
1689 def XOR16ri8 : Ii8<0x83, MRM6r,
1690 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1691 "xor{w}\t{$src2, $dst|$dst, $src2}",
1692 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
1693 (implicit EFLAGS)]>,
1695 def XOR32ri8 : Ii8<0x83, MRM6r,
1696 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1697 "xor{l}\t{$src2, $dst|$dst, $src2}",
1698 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
1699 (implicit EFLAGS)]>;
1701 let isTwoAddress = 0 in {
1702 def XOR8mr : I<0x30, MRMDestMem,
1703 (outs), (ins i8mem :$dst, GR8 :$src),
1704 "xor{b}\t{$src, $dst|$dst, $src}",
1705 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
1706 (implicit EFLAGS)]>;
1707 def XOR16mr : I<0x31, MRMDestMem,
1708 (outs), (ins i16mem:$dst, GR16:$src),
1709 "xor{w}\t{$src, $dst|$dst, $src}",
1710 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
1711 (implicit EFLAGS)]>,
1713 def XOR32mr : I<0x31, MRMDestMem,
1714 (outs), (ins i32mem:$dst, GR32:$src),
1715 "xor{l}\t{$src, $dst|$dst, $src}",
1716 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
1717 (implicit EFLAGS)]>;
1718 def XOR8mi : Ii8<0x80, MRM6m,
1719 (outs), (ins i8mem :$dst, i8imm :$src),
1720 "xor{b}\t{$src, $dst|$dst, $src}",
1721 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
1722 (implicit EFLAGS)]>;
1723 def XOR16mi : Ii16<0x81, MRM6m,
1724 (outs), (ins i16mem:$dst, i16imm:$src),
1725 "xor{w}\t{$src, $dst|$dst, $src}",
1726 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
1727 (implicit EFLAGS)]>,
1729 def XOR32mi : Ii32<0x81, MRM6m,
1730 (outs), (ins i32mem:$dst, i32imm:$src),
1731 "xor{l}\t{$src, $dst|$dst, $src}",
1732 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
1733 (implicit EFLAGS)]>;
1734 def XOR16mi8 : Ii8<0x83, MRM6m,
1735 (outs), (ins i16mem:$dst, i16i8imm :$src),
1736 "xor{w}\t{$src, $dst|$dst, $src}",
1737 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
1738 (implicit EFLAGS)]>,
1740 def XOR32mi8 : Ii8<0x83, MRM6m,
1741 (outs), (ins i32mem:$dst, i32i8imm :$src),
1742 "xor{l}\t{$src, $dst|$dst, $src}",
1743 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
1744 (implicit EFLAGS)]>;
1745 } // isTwoAddress = 0
1746 } // Defs = [EFLAGS]
1748 // Shift instructions
1749 let Defs = [EFLAGS] in {
1750 let Uses = [CL] in {
1751 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1752 "shl{b}\t{%cl, $dst|$dst, CL}",
1753 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1754 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1755 "shl{w}\t{%cl, $dst|$dst, CL}",
1756 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1757 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1758 "shl{l}\t{%cl, $dst|$dst, CL}",
1759 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1762 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1763 "shl{b}\t{$src2, $dst|$dst, $src2}",
1764 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1765 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1766 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1767 "shl{w}\t{$src2, $dst|$dst, $src2}",
1768 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1769 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1770 "shl{l}\t{$src2, $dst|$dst, $src2}",
1771 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1772 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1774 } // isConvertibleToThreeAddress = 1
1776 let isTwoAddress = 0 in {
1777 let Uses = [CL] in {
1778 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1779 "shl{b}\t{%cl, $dst|$dst, CL}",
1780 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1781 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1782 "shl{w}\t{%cl, $dst|$dst, CL}",
1783 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1784 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1785 "shl{l}\t{%cl, $dst|$dst, CL}",
1786 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1788 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1789 "shl{b}\t{$src, $dst|$dst, $src}",
1790 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1791 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1792 "shl{w}\t{$src, $dst|$dst, $src}",
1793 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1795 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1796 "shl{l}\t{$src, $dst|$dst, $src}",
1797 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1800 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1802 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1803 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1805 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1807 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1809 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1812 let Uses = [CL] in {
1813 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1814 "shr{b}\t{%cl, $dst|$dst, CL}",
1815 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1816 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1817 "shr{w}\t{%cl, $dst|$dst, CL}",
1818 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1819 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1820 "shr{l}\t{%cl, $dst|$dst, CL}",
1821 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1824 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1825 "shr{b}\t{$src2, $dst|$dst, $src2}",
1826 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1827 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1828 "shr{w}\t{$src2, $dst|$dst, $src2}",
1829 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1830 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1831 "shr{l}\t{$src2, $dst|$dst, $src2}",
1832 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1835 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1837 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1838 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1840 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1841 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1843 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1845 let isTwoAddress = 0 in {
1846 let Uses = [CL] in {
1847 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1848 "shr{b}\t{%cl, $dst|$dst, CL}",
1849 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1850 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1851 "shr{w}\t{%cl, $dst|$dst, CL}",
1852 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1854 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1855 "shr{l}\t{%cl, $dst|$dst, CL}",
1856 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1858 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1859 "shr{b}\t{$src, $dst|$dst, $src}",
1860 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1861 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1862 "shr{w}\t{$src, $dst|$dst, $src}",
1863 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1865 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1866 "shr{l}\t{$src, $dst|$dst, $src}",
1867 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1870 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1872 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1873 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1875 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1876 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1878 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1881 let Uses = [CL] in {
1882 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1883 "sar{b}\t{%cl, $dst|$dst, CL}",
1884 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1885 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1886 "sar{w}\t{%cl, $dst|$dst, CL}",
1887 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1888 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1889 "sar{l}\t{%cl, $dst|$dst, CL}",
1890 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1893 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1894 "sar{b}\t{$src2, $dst|$dst, $src2}",
1895 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1896 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1897 "sar{w}\t{$src2, $dst|$dst, $src2}",
1898 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1900 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1901 "sar{l}\t{$src2, $dst|$dst, $src2}",
1902 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1905 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1907 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1908 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1910 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1911 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1913 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1915 let isTwoAddress = 0 in {
1916 let Uses = [CL] in {
1917 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1918 "sar{b}\t{%cl, $dst|$dst, CL}",
1919 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
1920 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1921 "sar{w}\t{%cl, $dst|$dst, CL}",
1922 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1923 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1924 "sar{l}\t{%cl, $dst|$dst, CL}",
1925 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1927 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1928 "sar{b}\t{$src, $dst|$dst, $src}",
1929 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1930 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1931 "sar{w}\t{$src, $dst|$dst, $src}",
1932 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1934 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1935 "sar{l}\t{$src, $dst|$dst, $src}",
1936 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1939 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1941 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1942 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1944 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1946 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
1948 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1951 // Rotate instructions
1952 // FIXME: provide shorter instructions when imm8 == 1
1953 let Uses = [CL] in {
1954 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
1955 "rol{b}\t{%cl, $dst|$dst, CL}",
1956 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
1957 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
1958 "rol{w}\t{%cl, $dst|$dst, CL}",
1959 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
1960 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
1961 "rol{l}\t{%cl, $dst|$dst, CL}",
1962 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
1965 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1966 "rol{b}\t{$src2, $dst|$dst, $src2}",
1967 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1968 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1969 "rol{w}\t{$src2, $dst|$dst, $src2}",
1970 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1971 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1972 "rol{l}\t{$src2, $dst|$dst, $src2}",
1973 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1976 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1978 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1979 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
1981 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1982 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1984 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1986 let isTwoAddress = 0 in {
1987 let Uses = [CL] in {
1988 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
1989 "rol{b}\t{%cl, $dst|$dst, CL}",
1990 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
1991 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
1992 "rol{w}\t{%cl, $dst|$dst, CL}",
1993 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1994 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
1995 "rol{l}\t{%cl, $dst|$dst, CL}",
1996 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
1998 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
1999 "rol{b}\t{$src, $dst|$dst, $src}",
2000 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2001 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2002 "rol{w}\t{$src, $dst|$dst, $src}",
2003 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2005 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2006 "rol{l}\t{$src, $dst|$dst, $src}",
2007 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2010 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2012 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2013 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2015 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2017 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2019 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2022 let Uses = [CL] in {
2023 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2024 "ror{b}\t{%cl, $dst|$dst, CL}",
2025 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2026 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2027 "ror{w}\t{%cl, $dst|$dst, CL}",
2028 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2029 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2030 "ror{l}\t{%cl, $dst|$dst, CL}",
2031 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2034 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2035 "ror{b}\t{$src2, $dst|$dst, $src2}",
2036 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2037 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2038 "ror{w}\t{$src2, $dst|$dst, $src2}",
2039 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2040 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2041 "ror{l}\t{$src2, $dst|$dst, $src2}",
2042 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2045 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2047 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2048 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2050 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2051 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2053 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2055 let isTwoAddress = 0 in {
2056 let Uses = [CL] in {
2057 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2058 "ror{b}\t{%cl, $dst|$dst, CL}",
2059 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2060 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2061 "ror{w}\t{%cl, $dst|$dst, CL}",
2062 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2063 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2064 "ror{l}\t{%cl, $dst|$dst, CL}",
2065 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2067 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2068 "ror{b}\t{$src, $dst|$dst, $src}",
2069 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2070 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2071 "ror{w}\t{$src, $dst|$dst, $src}",
2072 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2074 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2075 "ror{l}\t{$src, $dst|$dst, $src}",
2076 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2079 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2081 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2082 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2084 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2086 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2088 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2093 // Double shift instructions (generalizations of rotate)
2094 let Uses = [CL] in {
2095 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2096 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2097 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2098 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2099 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2100 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2101 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2102 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2103 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2105 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2106 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2107 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2111 let isCommutable = 1 in { // These instructions commute to each other.
2112 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2113 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2114 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2115 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2118 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2119 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2120 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2121 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2124 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2125 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2126 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2127 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2130 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2131 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2132 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2133 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2138 let isTwoAddress = 0 in {
2139 let Uses = [CL] in {
2140 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2141 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2142 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2144 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2145 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2146 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2149 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2150 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2151 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2152 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2153 (i8 imm:$src3)), addr:$dst)]>,
2155 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2156 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2157 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2158 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2159 (i8 imm:$src3)), addr:$dst)]>,
2162 let Uses = [CL] in {
2163 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2164 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2165 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2166 addr:$dst)]>, TB, OpSize;
2167 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2168 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2169 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2170 addr:$dst)]>, TB, OpSize;
2172 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2173 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2174 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2175 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2176 (i8 imm:$src3)), addr:$dst)]>,
2178 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2179 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2180 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2181 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2182 (i8 imm:$src3)), addr:$dst)]>,
2185 } // Defs = [EFLAGS]
2189 let Defs = [EFLAGS] in {
2190 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2191 // Register-Register Addition
2192 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2193 (ins GR8 :$src1, GR8 :$src2),
2194 "add{b}\t{$src2, $dst|$dst, $src2}",
2195 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
2196 (implicit EFLAGS)]>;
2198 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2199 // Register-Register Addition
2200 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2201 (ins GR16:$src1, GR16:$src2),
2202 "add{w}\t{$src2, $dst|$dst, $src2}",
2203 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2204 (implicit EFLAGS)]>, OpSize;
2205 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2206 (ins GR32:$src1, GR32:$src2),
2207 "add{l}\t{$src2, $dst|$dst, $src2}",
2208 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2209 (implicit EFLAGS)]>;
2210 } // end isConvertibleToThreeAddress
2211 } // end isCommutable
2213 // Register-Memory Addition
2214 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2215 (ins GR8 :$src1, i8mem :$src2),
2216 "add{b}\t{$src2, $dst|$dst, $src2}",
2217 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2218 (implicit EFLAGS)]>;
2219 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2220 (ins GR16:$src1, i16mem:$src2),
2221 "add{w}\t{$src2, $dst|$dst, $src2}",
2222 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2223 (implicit EFLAGS)]>, OpSize;
2224 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2225 (ins GR32:$src1, i32mem:$src2),
2226 "add{l}\t{$src2, $dst|$dst, $src2}",
2227 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2228 (implicit EFLAGS)]>;
2230 // Register-Integer Addition
2231 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2232 "add{b}\t{$src2, $dst|$dst, $src2}",
2233 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2234 (implicit EFLAGS)]>;
2236 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2237 // Register-Integer Addition
2238 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2239 (ins GR16:$src1, i16imm:$src2),
2240 "add{w}\t{$src2, $dst|$dst, $src2}",
2241 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2242 (implicit EFLAGS)]>, OpSize;
2243 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2244 (ins GR32:$src1, i32imm:$src2),
2245 "add{l}\t{$src2, $dst|$dst, $src2}",
2246 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2247 (implicit EFLAGS)]>;
2248 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2249 (ins GR16:$src1, i16i8imm:$src2),
2250 "add{w}\t{$src2, $dst|$dst, $src2}",
2251 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2252 (implicit EFLAGS)]>, OpSize;
2253 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2254 (ins GR32:$src1, i32i8imm:$src2),
2255 "add{l}\t{$src2, $dst|$dst, $src2}",
2256 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2257 (implicit EFLAGS)]>;
2260 let isTwoAddress = 0 in {
2261 // Memory-Register Addition
2262 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2263 "add{b}\t{$src2, $dst|$dst, $src2}",
2264 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2265 (implicit EFLAGS)]>;
2266 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2267 "add{w}\t{$src2, $dst|$dst, $src2}",
2268 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2269 (implicit EFLAGS)]>, OpSize;
2270 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2271 "add{l}\t{$src2, $dst|$dst, $src2}",
2272 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2273 (implicit EFLAGS)]>;
2274 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2275 "add{b}\t{$src2, $dst|$dst, $src2}",
2276 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2277 (implicit EFLAGS)]>;
2278 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2279 "add{w}\t{$src2, $dst|$dst, $src2}",
2280 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2281 (implicit EFLAGS)]>, OpSize;
2282 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2283 "add{l}\t{$src2, $dst|$dst, $src2}",
2284 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2285 (implicit EFLAGS)]>;
2286 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2287 "add{w}\t{$src2, $dst|$dst, $src2}",
2288 [(store (add (load addr:$dst), i16immSExt8:$src2),
2290 (implicit EFLAGS)]>, OpSize;
2291 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2292 "add{l}\t{$src2, $dst|$dst, $src2}",
2293 [(store (add (load addr:$dst), i32immSExt8:$src2),
2295 (implicit EFLAGS)]>;
2298 let Uses = [EFLAGS] in {
2299 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2300 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2301 "adc{b}\t{$src2, $dst|$dst, $src2}",
2302 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2303 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2304 (ins GR16:$src1, GR16:$src2),
2305 "adc{w}\t{$src2, $dst|$dst, $src2}",
2306 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2307 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2308 (ins GR32:$src1, GR32:$src2),
2309 "adc{l}\t{$src2, $dst|$dst, $src2}",
2310 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2312 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2313 (ins GR8:$src1, i8mem:$src2),
2314 "adc{b}\t{$src2, $dst|$dst, $src2}",
2315 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2316 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2317 (ins GR16:$src1, i16mem:$src2),
2318 "adc{w}\t{$src2, $dst|$dst, $src2}",
2319 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2321 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2322 (ins GR32:$src1, i32mem:$src2),
2323 "adc{l}\t{$src2, $dst|$dst, $src2}",
2324 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2325 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2326 "adc{b}\t{$src2, $dst|$dst, $src2}",
2327 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2328 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2329 (ins GR16:$src1, i16imm:$src2),
2330 "adc{w}\t{$src2, $dst|$dst, $src2}",
2331 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2332 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2333 (ins GR16:$src1, i16i8imm:$src2),
2334 "adc{w}\t{$src2, $dst|$dst, $src2}",
2335 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2337 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2338 (ins GR32:$src1, i32imm:$src2),
2339 "adc{l}\t{$src2, $dst|$dst, $src2}",
2340 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2341 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2342 (ins GR32:$src1, i32i8imm:$src2),
2343 "adc{l}\t{$src2, $dst|$dst, $src2}",
2344 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2346 let isTwoAddress = 0 in {
2347 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2348 "adc{b}\t{$src2, $dst|$dst, $src2}",
2349 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2350 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2351 "adc{w}\t{$src2, $dst|$dst, $src2}",
2352 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2354 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2355 "adc{l}\t{$src2, $dst|$dst, $src2}",
2356 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2357 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2358 "adc{b}\t{$src2, $dst|$dst, $src2}",
2359 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2360 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2361 "adc{w}\t{$src2, $dst|$dst, $src2}",
2362 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2364 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2365 "adc{w}\t{$src2, $dst|$dst, $src2}",
2366 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2368 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2369 "adc{l}\t{$src2, $dst|$dst, $src2}",
2370 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2371 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2372 "adc{l}\t{$src2, $dst|$dst, $src2}",
2373 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2375 } // Uses = [EFLAGS]
2377 // Register-Register Subtraction
2378 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2379 "sub{b}\t{$src2, $dst|$dst, $src2}",
2380 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2381 (implicit EFLAGS)]>;
2382 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2383 "sub{w}\t{$src2, $dst|$dst, $src2}",
2384 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2385 (implicit EFLAGS)]>, OpSize;
2386 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2387 "sub{l}\t{$src2, $dst|$dst, $src2}",
2388 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2389 (implicit EFLAGS)]>;
2391 // Register-Memory Subtraction
2392 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2393 (ins GR8 :$src1, i8mem :$src2),
2394 "sub{b}\t{$src2, $dst|$dst, $src2}",
2395 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2396 (implicit EFLAGS)]>;
2397 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2398 (ins GR16:$src1, i16mem:$src2),
2399 "sub{w}\t{$src2, $dst|$dst, $src2}",
2400 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2401 (implicit EFLAGS)]>, OpSize;
2402 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2403 (ins GR32:$src1, i32mem:$src2),
2404 "sub{l}\t{$src2, $dst|$dst, $src2}",
2405 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2406 (implicit EFLAGS)]>;
2408 // Register-Integer Subtraction
2409 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2410 (ins GR8:$src1, i8imm:$src2),
2411 "sub{b}\t{$src2, $dst|$dst, $src2}",
2412 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2413 (implicit EFLAGS)]>;
2414 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2415 (ins GR16:$src1, i16imm:$src2),
2416 "sub{w}\t{$src2, $dst|$dst, $src2}",
2417 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2418 (implicit EFLAGS)]>, OpSize;
2419 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2420 (ins GR32:$src1, i32imm:$src2),
2421 "sub{l}\t{$src2, $dst|$dst, $src2}",
2422 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2423 (implicit EFLAGS)]>;
2424 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2425 (ins GR16:$src1, i16i8imm:$src2),
2426 "sub{w}\t{$src2, $dst|$dst, $src2}",
2427 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2428 (implicit EFLAGS)]>, OpSize;
2429 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2430 (ins GR32:$src1, i32i8imm:$src2),
2431 "sub{l}\t{$src2, $dst|$dst, $src2}",
2432 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2433 (implicit EFLAGS)]>;
2435 let isTwoAddress = 0 in {
2436 // Memory-Register Subtraction
2437 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2438 "sub{b}\t{$src2, $dst|$dst, $src2}",
2439 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2440 (implicit EFLAGS)]>;
2441 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2442 "sub{w}\t{$src2, $dst|$dst, $src2}",
2443 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2444 (implicit EFLAGS)]>, OpSize;
2445 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2446 "sub{l}\t{$src2, $dst|$dst, $src2}",
2447 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2448 (implicit EFLAGS)]>;
2450 // Memory-Integer Subtraction
2451 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2452 "sub{b}\t{$src2, $dst|$dst, $src2}",
2453 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2454 (implicit EFLAGS)]>;
2455 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2456 "sub{w}\t{$src2, $dst|$dst, $src2}",
2457 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2458 (implicit EFLAGS)]>, OpSize;
2459 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2460 "sub{l}\t{$src2, $dst|$dst, $src2}",
2461 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2462 (implicit EFLAGS)]>;
2463 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2464 "sub{w}\t{$src2, $dst|$dst, $src2}",
2465 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2467 (implicit EFLAGS)]>, OpSize;
2468 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2469 "sub{l}\t{$src2, $dst|$dst, $src2}",
2470 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2472 (implicit EFLAGS)]>;
2475 let Uses = [EFLAGS] in {
2476 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
2477 (ins GR8:$src1, GR8:$src2),
2478 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2479 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
2480 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
2481 (ins GR16:$src1, GR16:$src2),
2482 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2483 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
2484 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
2485 (ins GR32:$src1, GR32:$src2),
2486 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2487 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2489 let isTwoAddress = 0 in {
2490 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2491 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2492 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
2493 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2494 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2495 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
2497 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2498 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2499 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2500 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2501 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2502 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2503 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
2504 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2505 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2507 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2508 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2509 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2511 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2512 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2513 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2514 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2515 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2516 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2518 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
2519 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2520 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
2521 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
2522 (ins GR16:$src1, i16mem:$src2),
2523 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2524 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
2526 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
2527 (ins GR32:$src1, i32mem:$src2),
2528 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2529 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2530 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2531 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2532 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
2533 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
2534 (ins GR16:$src1, i16imm:$src2),
2535 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2536 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
2537 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
2538 (ins GR16:$src1, i16i8imm:$src2),
2539 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2540 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
2542 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
2543 (ins GR32:$src1, i32imm:$src2),
2544 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2545 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2546 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
2547 (ins GR32:$src1, i32i8imm:$src2),
2548 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2549 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2550 } // Uses = [EFLAGS]
2551 } // Defs = [EFLAGS]
2553 let Defs = [EFLAGS] in {
2554 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2555 // Register-Register Signed Integer Multiply
2556 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2557 "imul{w}\t{$src2, $dst|$dst, $src2}",
2558 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
2559 (implicit EFLAGS)]>, TB, OpSize;
2560 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2561 "imul{l}\t{$src2, $dst|$dst, $src2}",
2562 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
2563 (implicit EFLAGS)]>, TB;
2566 // Register-Memory Signed Integer Multiply
2567 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
2568 (ins GR16:$src1, i16mem:$src2),
2569 "imul{w}\t{$src2, $dst|$dst, $src2}",
2570 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
2571 (implicit EFLAGS)]>, TB, OpSize;
2572 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2573 "imul{l}\t{$src2, $dst|$dst, $src2}",
2574 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
2575 (implicit EFLAGS)]>, TB;
2576 } // Defs = [EFLAGS]
2577 } // end Two Address instructions
2579 // Suprisingly enough, these are not two address instructions!
2580 let Defs = [EFLAGS] in {
2581 // Register-Integer Signed Integer Multiply
2582 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2583 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2584 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2585 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
2586 (implicit EFLAGS)]>, OpSize;
2587 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2588 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2589 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2590 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
2591 (implicit EFLAGS)]>;
2592 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2593 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2594 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2595 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
2596 (implicit EFLAGS)]>, OpSize;
2597 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2598 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2599 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2600 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
2601 (implicit EFLAGS)]>;
2603 // Memory-Integer Signed Integer Multiply
2604 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2605 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2606 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2607 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
2608 (implicit EFLAGS)]>, OpSize;
2609 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2610 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2611 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2612 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
2613 (implicit EFLAGS)]>;
2614 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2615 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2616 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2617 [(set GR16:$dst, (mul (load addr:$src1),
2618 i16immSExt8:$src2)),
2619 (implicit EFLAGS)]>, OpSize;
2620 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2621 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2622 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2623 [(set GR32:$dst, (mul (load addr:$src1),
2624 i32immSExt8:$src2)),
2625 (implicit EFLAGS)]>;
2626 } // Defs = [EFLAGS]
2628 //===----------------------------------------------------------------------===//
2629 // Test instructions are just like AND, except they don't generate a result.
2631 let Defs = [EFLAGS] in {
2632 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2633 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2634 "test{b}\t{$src2, $src1|$src1, $src2}",
2635 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
2636 (implicit EFLAGS)]>;
2637 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2638 "test{w}\t{$src2, $src1|$src1, $src2}",
2639 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
2640 (implicit EFLAGS)]>,
2642 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2643 "test{l}\t{$src2, $src1|$src1, $src2}",
2644 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
2645 (implicit EFLAGS)]>;
2648 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2649 "test{b}\t{$src2, $src1|$src1, $src2}",
2650 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2651 (implicit EFLAGS)]>;
2652 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2653 "test{w}\t{$src2, $src1|$src1, $src2}",
2654 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2655 (implicit EFLAGS)]>, OpSize;
2656 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2657 "test{l}\t{$src2, $src1|$src1, $src2}",
2658 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2659 (implicit EFLAGS)]>;
2661 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2662 (outs), (ins GR8:$src1, i8imm:$src2),
2663 "test{b}\t{$src2, $src1|$src1, $src2}",
2664 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
2665 (implicit EFLAGS)]>;
2666 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2667 (outs), (ins GR16:$src1, i16imm:$src2),
2668 "test{w}\t{$src2, $src1|$src1, $src2}",
2669 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
2670 (implicit EFLAGS)]>, OpSize;
2671 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2672 (outs), (ins GR32:$src1, i32imm:$src2),
2673 "test{l}\t{$src2, $src1|$src1, $src2}",
2674 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
2675 (implicit EFLAGS)]>;
2677 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2678 (outs), (ins i8mem:$src1, i8imm:$src2),
2679 "test{b}\t{$src2, $src1|$src1, $src2}",
2680 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2681 (implicit EFLAGS)]>;
2682 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2683 (outs), (ins i16mem:$src1, i16imm:$src2),
2684 "test{w}\t{$src2, $src1|$src1, $src2}",
2685 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2686 (implicit EFLAGS)]>, OpSize;
2687 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2688 (outs), (ins i32mem:$src1, i32imm:$src2),
2689 "test{l}\t{$src2, $src1|$src1, $src2}",
2690 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2691 (implicit EFLAGS)]>;
2692 } // Defs = [EFLAGS]
2695 // Condition code ops, incl. set if equal/not equal/...
2696 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2697 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2698 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2699 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2701 let Uses = [EFLAGS] in {
2702 def SETEr : I<0x94, MRM0r,
2703 (outs GR8 :$dst), (ins),
2705 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2707 def SETEm : I<0x94, MRM0m,
2708 (outs), (ins i8mem:$dst),
2710 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2713 def SETNEr : I<0x95, MRM0r,
2714 (outs GR8 :$dst), (ins),
2716 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2718 def SETNEm : I<0x95, MRM0m,
2719 (outs), (ins i8mem:$dst),
2721 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2724 def SETLr : I<0x9C, MRM0r,
2725 (outs GR8 :$dst), (ins),
2727 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2728 TB; // GR8 = < signed
2729 def SETLm : I<0x9C, MRM0m,
2730 (outs), (ins i8mem:$dst),
2732 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2733 TB; // [mem8] = < signed
2735 def SETGEr : I<0x9D, MRM0r,
2736 (outs GR8 :$dst), (ins),
2738 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2739 TB; // GR8 = >= signed
2740 def SETGEm : I<0x9D, MRM0m,
2741 (outs), (ins i8mem:$dst),
2743 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2744 TB; // [mem8] = >= signed
2746 def SETLEr : I<0x9E, MRM0r,
2747 (outs GR8 :$dst), (ins),
2749 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2750 TB; // GR8 = <= signed
2751 def SETLEm : I<0x9E, MRM0m,
2752 (outs), (ins i8mem:$dst),
2754 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2755 TB; // [mem8] = <= signed
2757 def SETGr : I<0x9F, MRM0r,
2758 (outs GR8 :$dst), (ins),
2760 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2761 TB; // GR8 = > signed
2762 def SETGm : I<0x9F, MRM0m,
2763 (outs), (ins i8mem:$dst),
2765 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2766 TB; // [mem8] = > signed
2768 def SETBr : I<0x92, MRM0r,
2769 (outs GR8 :$dst), (ins),
2771 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2772 TB; // GR8 = < unsign
2773 def SETBm : I<0x92, MRM0m,
2774 (outs), (ins i8mem:$dst),
2776 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
2777 TB; // [mem8] = < unsign
2779 def SETAEr : I<0x93, MRM0r,
2780 (outs GR8 :$dst), (ins),
2782 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
2783 TB; // GR8 = >= unsign
2784 def SETAEm : I<0x93, MRM0m,
2785 (outs), (ins i8mem:$dst),
2787 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
2788 TB; // [mem8] = >= unsign
2790 def SETBEr : I<0x96, MRM0r,
2791 (outs GR8 :$dst), (ins),
2793 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
2794 TB; // GR8 = <= unsign
2795 def SETBEm : I<0x96, MRM0m,
2796 (outs), (ins i8mem:$dst),
2798 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
2799 TB; // [mem8] = <= unsign
2801 def SETAr : I<0x97, MRM0r,
2802 (outs GR8 :$dst), (ins),
2804 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
2805 TB; // GR8 = > signed
2806 def SETAm : I<0x97, MRM0m,
2807 (outs), (ins i8mem:$dst),
2809 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
2810 TB; // [mem8] = > signed
2812 def SETSr : I<0x98, MRM0r,
2813 (outs GR8 :$dst), (ins),
2815 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
2816 TB; // GR8 = <sign bit>
2817 def SETSm : I<0x98, MRM0m,
2818 (outs), (ins i8mem:$dst),
2820 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
2821 TB; // [mem8] = <sign bit>
2822 def SETNSr : I<0x99, MRM0r,
2823 (outs GR8 :$dst), (ins),
2825 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
2826 TB; // GR8 = !<sign bit>
2827 def SETNSm : I<0x99, MRM0m,
2828 (outs), (ins i8mem:$dst),
2830 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
2831 TB; // [mem8] = !<sign bit>
2833 def SETPr : I<0x9A, MRM0r,
2834 (outs GR8 :$dst), (ins),
2836 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
2838 def SETPm : I<0x9A, MRM0m,
2839 (outs), (ins i8mem:$dst),
2841 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
2842 TB; // [mem8] = parity
2843 def SETNPr : I<0x9B, MRM0r,
2844 (outs GR8 :$dst), (ins),
2846 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
2847 TB; // GR8 = not parity
2848 def SETNPm : I<0x9B, MRM0m,
2849 (outs), (ins i8mem:$dst),
2851 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
2852 TB; // [mem8] = not parity
2854 def SETOr : I<0x90, MRM0r,
2855 (outs GR8 :$dst), (ins),
2857 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
2858 TB; // GR8 = overflow
2859 def SETOm : I<0x90, MRM0m,
2860 (outs), (ins i8mem:$dst),
2862 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
2863 TB; // [mem8] = overflow
2864 def SETNOr : I<0x91, MRM0r,
2865 (outs GR8 :$dst), (ins),
2867 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
2868 TB; // GR8 = not overflow
2869 def SETNOm : I<0x91, MRM0m,
2870 (outs), (ins i8mem:$dst),
2872 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
2873 TB; // [mem8] = not overflow
2874 } // Uses = [EFLAGS]
2877 // Integer comparisons
2878 let Defs = [EFLAGS] in {
2879 def CMP8rr : I<0x38, MRMDestReg,
2880 (outs), (ins GR8 :$src1, GR8 :$src2),
2881 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2882 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2883 def CMP16rr : I<0x39, MRMDestReg,
2884 (outs), (ins GR16:$src1, GR16:$src2),
2885 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2886 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
2887 def CMP32rr : I<0x39, MRMDestReg,
2888 (outs), (ins GR32:$src1, GR32:$src2),
2889 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2890 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
2891 def CMP8mr : I<0x38, MRMDestMem,
2892 (outs), (ins i8mem :$src1, GR8 :$src2),
2893 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2894 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
2895 (implicit EFLAGS)]>;
2896 def CMP16mr : I<0x39, MRMDestMem,
2897 (outs), (ins i16mem:$src1, GR16:$src2),
2898 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2899 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
2900 (implicit EFLAGS)]>, OpSize;
2901 def CMP32mr : I<0x39, MRMDestMem,
2902 (outs), (ins i32mem:$src1, GR32:$src2),
2903 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2904 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
2905 (implicit EFLAGS)]>;
2906 def CMP8rm : I<0x3A, MRMSrcMem,
2907 (outs), (ins GR8 :$src1, i8mem :$src2),
2908 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2909 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
2910 (implicit EFLAGS)]>;
2911 def CMP16rm : I<0x3B, MRMSrcMem,
2912 (outs), (ins GR16:$src1, i16mem:$src2),
2913 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2914 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
2915 (implicit EFLAGS)]>, OpSize;
2916 def CMP32rm : I<0x3B, MRMSrcMem,
2917 (outs), (ins GR32:$src1, i32mem:$src2),
2918 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2919 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
2920 (implicit EFLAGS)]>;
2921 def CMP8ri : Ii8<0x80, MRM7r,
2922 (outs), (ins GR8:$src1, i8imm:$src2),
2923 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2924 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
2925 def CMP16ri : Ii16<0x81, MRM7r,
2926 (outs), (ins GR16:$src1, i16imm:$src2),
2927 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2928 [(X86cmp GR16:$src1, imm:$src2),
2929 (implicit EFLAGS)]>, OpSize;
2930 def CMP32ri : Ii32<0x81, MRM7r,
2931 (outs), (ins GR32:$src1, i32imm:$src2),
2932 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2933 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
2934 def CMP8mi : Ii8 <0x80, MRM7m,
2935 (outs), (ins i8mem :$src1, i8imm :$src2),
2936 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2937 [(X86cmp (loadi8 addr:$src1), imm:$src2),
2938 (implicit EFLAGS)]>;
2939 def CMP16mi : Ii16<0x81, MRM7m,
2940 (outs), (ins i16mem:$src1, i16imm:$src2),
2941 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2942 [(X86cmp (loadi16 addr:$src1), imm:$src2),
2943 (implicit EFLAGS)]>, OpSize;
2944 def CMP32mi : Ii32<0x81, MRM7m,
2945 (outs), (ins i32mem:$src1, i32imm:$src2),
2946 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2947 [(X86cmp (loadi32 addr:$src1), imm:$src2),
2948 (implicit EFLAGS)]>;
2949 def CMP16ri8 : Ii8<0x83, MRM7r,
2950 (outs), (ins GR16:$src1, i16i8imm:$src2),
2951 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2952 [(X86cmp GR16:$src1, i16immSExt8:$src2),
2953 (implicit EFLAGS)]>, OpSize;
2954 def CMP16mi8 : Ii8<0x83, MRM7m,
2955 (outs), (ins i16mem:$src1, i16i8imm:$src2),
2956 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2957 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
2958 (implicit EFLAGS)]>, OpSize;
2959 def CMP32mi8 : Ii8<0x83, MRM7m,
2960 (outs), (ins i32mem:$src1, i32i8imm:$src2),
2961 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2962 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
2963 (implicit EFLAGS)]>;
2964 def CMP32ri8 : Ii8<0x83, MRM7r,
2965 (outs), (ins GR32:$src1, i32i8imm:$src2),
2966 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2967 [(X86cmp GR32:$src1, i32immSExt8:$src2),
2968 (implicit EFLAGS)]>;
2969 } // Defs = [EFLAGS]
2972 // TODO: BTC, BTR, and BTS
2973 let Defs = [EFLAGS] in {
2974 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2975 "bt{w}\t{$src2, $src1|$src1, $src2}",
2976 [(X86bt GR16:$src1, GR16:$src2),
2977 (implicit EFLAGS)]>, OpSize, TB;
2978 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2979 "bt{l}\t{$src2, $src1|$src1, $src2}",
2980 [(X86bt GR32:$src1, GR32:$src2),
2981 (implicit EFLAGS)]>, TB;
2983 // Unlike with the register+register form, the memory+register form of the
2984 // bt instruction does not ignore the high bits of the index. From ISel's
2985 // perspective, this is pretty bizarre. Disable these instructions for now.
2986 //def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
2987 // "bt{w}\t{$src2, $src1|$src1, $src2}",
2988 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
2989 // (implicit EFLAGS)]>, OpSize, TB, Requires<[FastBTMem]>;
2990 //def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
2991 // "bt{l}\t{$src2, $src1|$src1, $src2}",
2992 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
2993 // (implicit EFLAGS)]>, TB, Requires<[FastBTMem]>;
2995 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
2996 "bt{w}\t{$src2, $src1|$src1, $src2}",
2997 [(X86bt GR16:$src1, i16immSExt8:$src2),
2998 (implicit EFLAGS)]>, OpSize, TB;
2999 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3000 "bt{l}\t{$src2, $src1|$src1, $src2}",
3001 [(X86bt GR32:$src1, i32immSExt8:$src2),
3002 (implicit EFLAGS)]>, TB;
3003 // Note that these instructions don't need FastBTMem because that
3004 // only applies when the other operand is in a register. When it's
3005 // an immediate, bt is still fast.
3006 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3007 "bt{w}\t{$src2, $src1|$src1, $src2}",
3008 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
3009 (implicit EFLAGS)]>, OpSize, TB;
3010 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3011 "bt{l}\t{$src2, $src1|$src1, $src2}",
3012 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
3013 (implicit EFLAGS)]>, TB;
3014 } // Defs = [EFLAGS]
3016 // Sign/Zero extenders
3017 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3018 // of the register here. This has a smaller encoding and avoids a
3019 // partial-register update.
3020 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3021 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3022 [(set GR16:$dst, (sext GR8:$src))]>, TB;
3023 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3024 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3025 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3026 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3027 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3028 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3029 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3030 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3031 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3032 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3033 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3034 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3035 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3036 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3037 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3039 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3040 // of the register here. This has a smaller encoding and avoids a
3041 // partial-register update.
3042 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3043 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3044 [(set GR16:$dst, (zext GR8:$src))]>, TB;
3045 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3046 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3047 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3048 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3049 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3050 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3051 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3052 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3053 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3054 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3055 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3056 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3057 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3058 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3059 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3061 // These are the same as the regular regular MOVZX32rr8 and MOVZX32rm8
3062 // except that they use GR32_NOREX for the output operand register class
3063 // instead of GR32. This allows them to operate on h registers on x86-64.
3064 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3065 (outs GR32_NOREX:$dst), (ins GR8:$src),
3066 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3069 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3070 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3071 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3074 let neverHasSideEffects = 1 in {
3075 let Defs = [AX], Uses = [AL] in
3076 def CBW : I<0x98, RawFrm, (outs), (ins),
3077 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3078 let Defs = [EAX], Uses = [AX] in
3079 def CWDE : I<0x98, RawFrm, (outs), (ins),
3080 "{cwtl|cwde}", []>; // EAX = signext(AX)
3082 let Defs = [AX,DX], Uses = [AX] in
3083 def CWD : I<0x99, RawFrm, (outs), (ins),
3084 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3085 let Defs = [EAX,EDX], Uses = [EAX] in
3086 def CDQ : I<0x99, RawFrm, (outs), (ins),
3087 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3090 //===----------------------------------------------------------------------===//
3091 // Alias Instructions
3092 //===----------------------------------------------------------------------===//
3094 // Alias instructions that map movr0 to xor.
3095 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3096 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1 in {
3097 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
3098 "xor{b}\t$dst, $dst",
3099 [(set GR8:$dst, 0)]>;
3100 // Use xorl instead of xorw since we don't care about the high 16 bits,
3101 // it's smaller, and it avoids a partial-register update.
3102 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3103 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
3104 [(set GR16:$dst, 0)]>;
3105 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
3106 "xor{l}\t$dst, $dst",
3107 [(set GR32:$dst, 0)]>;
3110 //===----------------------------------------------------------------------===//
3111 // Thread Local Storage Instructions
3114 // All calls clobber the non-callee saved registers. ESP is marked as
3115 // a use to prevent stack-pointer assignments that appear immediately
3116 // before calls from potentially appearing dead.
3117 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3118 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3119 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3120 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3122 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3123 "leal\t$sym, %eax; "
3124 "call\t___tls_get_addr@PLT",
3125 [(X86tlsaddr tls32addr:$sym)]>,
3126 Requires<[In32BitMode]>;
3128 let AddedComplexity = 5 in
3129 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3130 "movl\t%gs:$src, $dst",
3131 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3133 let AddedComplexity = 5 in
3134 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3135 "movl\t%fs:$src, $dst",
3136 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3138 //===----------------------------------------------------------------------===//
3139 // DWARF Pseudo Instructions
3142 def DWARF_LOC : I<0, Pseudo, (outs),
3143 (ins i32imm:$line, i32imm:$col, i32imm:$file),
3144 ".loc\t${file:debug} ${line:debug} ${col:debug}",
3145 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
3148 //===----------------------------------------------------------------------===//
3149 // EH Pseudo Instructions
3151 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3153 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3154 "ret\t#eh_return, addr: $addr",
3155 [(X86ehret GR32:$addr)]>;
3159 //===----------------------------------------------------------------------===//
3163 // Atomic swap. These are just normal xchg instructions. But since a memory
3164 // operand is referenced, the atomicity is ensured.
3165 let Constraints = "$val = $dst" in {
3166 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3167 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3168 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3169 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3170 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3171 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3173 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3174 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3175 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3178 // Atomic compare and swap.
3179 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3180 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3182 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3183 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3185 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3186 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
3189 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3192 let Defs = [AX, EFLAGS], Uses = [AX] in {
3193 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3195 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3196 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3198 let Defs = [AL, EFLAGS], Uses = [AL] in {
3199 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3201 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3202 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3205 // Atomic exchange and add
3206 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3207 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3209 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3210 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3212 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3214 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3215 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3217 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3219 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3220 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3224 // Atomic exchange, and, or, xor
3225 let Constraints = "$val = $dst", Defs = [EFLAGS],
3226 usesCustomDAGSchedInserter = 1 in {
3227 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3228 "#ATOMAND32 PSEUDO!",
3229 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3230 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3231 "#ATOMOR32 PSEUDO!",
3232 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
3233 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3234 "#ATOMXOR32 PSEUDO!",
3235 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
3236 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3237 "#ATOMNAND32 PSEUDO!",
3238 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
3239 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3240 "#ATOMMIN32 PSEUDO!",
3241 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
3242 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3243 "#ATOMMAX32 PSEUDO!",
3244 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
3245 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3246 "#ATOMUMIN32 PSEUDO!",
3247 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
3248 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3249 "#ATOMUMAX32 PSEUDO!",
3250 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
3252 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3253 "#ATOMAND16 PSEUDO!",
3254 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
3255 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3256 "#ATOMOR16 PSEUDO!",
3257 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
3258 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3259 "#ATOMXOR16 PSEUDO!",
3260 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
3261 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3262 "#ATOMNAND16 PSEUDO!",
3263 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
3264 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3265 "#ATOMMIN16 PSEUDO!",
3266 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
3267 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3268 "#ATOMMAX16 PSEUDO!",
3269 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
3270 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3271 "#ATOMUMIN16 PSEUDO!",
3272 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
3273 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3274 "#ATOMUMAX16 PSEUDO!",
3275 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
3277 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3278 "#ATOMAND8 PSEUDO!",
3279 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
3280 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3282 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
3283 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3284 "#ATOMXOR8 PSEUDO!",
3285 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
3286 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3287 "#ATOMNAND8 PSEUDO!",
3288 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
3291 let Constraints = "$val1 = $dst1, $val2 = $dst2",
3292 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
3293 Uses = [EAX, EBX, ECX, EDX],
3294 mayLoad = 1, mayStore = 1,
3295 usesCustomDAGSchedInserter = 1 in {
3296 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3297 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3298 "#ATOMAND6432 PSEUDO!", []>;
3299 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3300 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3301 "#ATOMOR6432 PSEUDO!", []>;
3302 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3303 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3304 "#ATOMXOR6432 PSEUDO!", []>;
3305 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3306 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3307 "#ATOMNAND6432 PSEUDO!", []>;
3308 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3309 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3310 "#ATOMADD6432 PSEUDO!", []>;
3311 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3312 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3313 "#ATOMSUB6432 PSEUDO!", []>;
3314 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3315 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3316 "#ATOMSWAP6432 PSEUDO!", []>;
3319 //===----------------------------------------------------------------------===//
3320 // Non-Instruction Patterns
3321 //===----------------------------------------------------------------------===//
3323 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
3324 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
3325 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
3326 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
3327 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
3328 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
3330 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
3331 (ADD32ri GR32:$src1, tconstpool:$src2)>;
3332 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
3333 (ADD32ri GR32:$src1, tjumptable:$src2)>;
3334 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
3335 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
3336 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
3337 (ADD32ri GR32:$src1, texternalsym:$src2)>;
3339 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
3340 (MOV32mi addr:$dst, tglobaladdr:$src)>;
3341 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
3342 (MOV32mi addr:$dst, texternalsym:$src)>;
3346 def : Pat<(X86tailcall GR32:$dst),
3349 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
3351 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
3354 def : Pat<(X86tcret GR32:$dst, imm:$off),
3355 (TCRETURNri GR32:$dst, imm:$off)>;
3357 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
3358 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3360 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
3361 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3363 def : Pat<(X86call (i32 tglobaladdr:$dst)),
3364 (CALLpcrel32 tglobaladdr:$dst)>;
3365 def : Pat<(X86call (i32 texternalsym:$dst)),
3366 (CALLpcrel32 texternalsym:$dst)>;
3367 def : Pat<(X86call (i32 imm:$dst)),
3368 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
3370 // X86 specific add which produces a flag.
3371 def : Pat<(addc GR32:$src1, GR32:$src2),
3372 (ADD32rr GR32:$src1, GR32:$src2)>;
3373 def : Pat<(addc GR32:$src1, (load addr:$src2)),
3374 (ADD32rm GR32:$src1, addr:$src2)>;
3375 def : Pat<(addc GR32:$src1, imm:$src2),
3376 (ADD32ri GR32:$src1, imm:$src2)>;
3377 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
3378 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3380 def : Pat<(subc GR32:$src1, GR32:$src2),
3381 (SUB32rr GR32:$src1, GR32:$src2)>;
3382 def : Pat<(subc GR32:$src1, (load addr:$src2)),
3383 (SUB32rm GR32:$src1, addr:$src2)>;
3384 def : Pat<(subc GR32:$src1, imm:$src2),
3385 (SUB32ri GR32:$src1, imm:$src2)>;
3386 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
3387 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3391 // TEST R,R is smaller than CMP R,0
3392 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
3393 (TEST8rr GR8:$src1, GR8:$src1)>;
3394 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
3395 (TEST16rr GR16:$src1, GR16:$src1)>;
3396 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
3397 (TEST32rr GR32:$src1, GR32:$src1)>;
3399 // Conditional moves with folded loads with operands swapped and conditions
3401 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
3402 (CMOVAE16rm GR16:$src2, addr:$src1)>;
3403 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
3404 (CMOVAE32rm GR32:$src2, addr:$src1)>;
3405 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
3406 (CMOVB16rm GR16:$src2, addr:$src1)>;
3407 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
3408 (CMOVB32rm GR32:$src2, addr:$src1)>;
3409 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
3410 (CMOVNE16rm GR16:$src2, addr:$src1)>;
3411 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
3412 (CMOVNE32rm GR32:$src2, addr:$src1)>;
3413 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
3414 (CMOVE16rm GR16:$src2, addr:$src1)>;
3415 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
3416 (CMOVE32rm GR32:$src2, addr:$src1)>;
3417 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
3418 (CMOVA16rm GR16:$src2, addr:$src1)>;
3419 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
3420 (CMOVA32rm GR32:$src2, addr:$src1)>;
3421 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
3422 (CMOVBE16rm GR16:$src2, addr:$src1)>;
3423 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
3424 (CMOVBE32rm GR32:$src2, addr:$src1)>;
3425 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
3426 (CMOVGE16rm GR16:$src2, addr:$src1)>;
3427 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
3428 (CMOVGE32rm GR32:$src2, addr:$src1)>;
3429 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
3430 (CMOVL16rm GR16:$src2, addr:$src1)>;
3431 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
3432 (CMOVL32rm GR32:$src2, addr:$src1)>;
3433 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
3434 (CMOVG16rm GR16:$src2, addr:$src1)>;
3435 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
3436 (CMOVG32rm GR32:$src2, addr:$src1)>;
3437 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
3438 (CMOVLE16rm GR16:$src2, addr:$src1)>;
3439 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
3440 (CMOVLE32rm GR32:$src2, addr:$src1)>;
3441 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
3442 (CMOVNP16rm GR16:$src2, addr:$src1)>;
3443 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
3444 (CMOVNP32rm GR32:$src2, addr:$src1)>;
3445 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
3446 (CMOVP16rm GR16:$src2, addr:$src1)>;
3447 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
3448 (CMOVP32rm GR32:$src2, addr:$src1)>;
3449 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
3450 (CMOVNS16rm GR16:$src2, addr:$src1)>;
3451 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
3452 (CMOVNS32rm GR32:$src2, addr:$src1)>;
3453 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
3454 (CMOVS16rm GR16:$src2, addr:$src1)>;
3455 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
3456 (CMOVS32rm GR32:$src2, addr:$src1)>;
3457 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
3458 (CMOVNO16rm GR16:$src2, addr:$src1)>;
3459 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
3460 (CMOVNO32rm GR32:$src2, addr:$src1)>;
3461 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
3462 (CMOVO16rm GR16:$src2, addr:$src1)>;
3463 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
3464 (CMOVO32rm GR32:$src2, addr:$src1)>;
3466 // zextload bool -> zextload byte
3467 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3468 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3469 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3471 // extload bool -> extload byte
3472 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3473 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>,
3474 Requires<[In32BitMode]>;
3475 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3476 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>,
3477 Requires<[In32BitMode]>;
3478 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
3479 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
3482 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>,
3483 Requires<[In32BitMode]>;
3484 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>,
3485 Requires<[In32BitMode]>;
3486 def : Pat<(i32 (anyext GR16:$src)),
3487 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
3489 // (and (i32 load), 255) -> (zextload i8)
3490 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
3491 (MOVZX32rm8 addr:$src)>;
3492 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
3493 (MOVZX32rm16 addr:$src)>;
3495 //===----------------------------------------------------------------------===//
3497 //===----------------------------------------------------------------------===//
3499 // Odd encoding trick: -128 fits into an 8-bit immediate field while
3500 // +128 doesn't, so in this special case use a sub instead of an add.
3501 def : Pat<(add GR16:$src1, 128),
3502 (SUB16ri8 GR16:$src1, -128)>;
3503 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
3504 (SUB16mi8 addr:$dst, -128)>;
3505 def : Pat<(add GR32:$src1, 128),
3506 (SUB32ri8 GR32:$src1, -128)>;
3507 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
3508 (SUB32mi8 addr:$dst, -128)>;
3510 // r & (2^16-1) ==> movz
3511 def : Pat<(and GR32:$src1, 0xffff),
3512 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
3513 // r & (2^8-1) ==> movz
3514 def : Pat<(and GR32:$src1, 0xff),
3515 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src1, GR32_ABCD),
3517 Requires<[In32BitMode]>;
3518 // r & (2^8-1) ==> movz
3519 def : Pat<(and GR16:$src1, 0xff),
3520 (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD),
3522 Requires<[In32BitMode]>;
3524 // sext_inreg patterns
3525 def : Pat<(sext_inreg GR32:$src, i16),
3526 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
3527 def : Pat<(sext_inreg GR32:$src, i8),
3528 (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3530 Requires<[In32BitMode]>;
3531 def : Pat<(sext_inreg GR16:$src, i8),
3532 (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3534 Requires<[In32BitMode]>;
3537 def : Pat<(i16 (trunc GR32:$src)),
3538 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
3539 def : Pat<(i8 (trunc GR32:$src)),
3540 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3542 Requires<[In32BitMode]>;
3543 def : Pat<(i8 (trunc GR16:$src)),
3544 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3546 Requires<[In32BitMode]>;
3548 // h-register tricks
3549 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
3550 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3551 x86_subreg_8bit_hi)>,
3552 Requires<[In32BitMode]>;
3553 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
3554 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3555 x86_subreg_8bit_hi)>,
3556 Requires<[In32BitMode]>;
3557 def : Pat<(srl_su GR16:$src, (i8 8)),
3560 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3561 x86_subreg_8bit_hi)),
3563 Requires<[In32BitMode]>;
3564 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
3565 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3566 x86_subreg_8bit_hi))>,
3567 Requires<[In32BitMode]>;
3568 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
3569 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3570 x86_subreg_8bit_hi))>,
3571 Requires<[In32BitMode]>;
3573 // (shl x, 1) ==> (add x, x)
3574 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
3575 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
3576 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
3578 // (shl x (and y, 31)) ==> (shl x, y)
3579 def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
3580 (SHL8rCL GR8:$src1)>;
3581 def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
3582 (SHL16rCL GR16:$src1)>;
3583 def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
3584 (SHL32rCL GR32:$src1)>;
3585 def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3586 (SHL8mCL addr:$dst)>;
3587 def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3588 (SHL16mCL addr:$dst)>;
3589 def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3590 (SHL32mCL addr:$dst)>;
3592 def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
3593 (SHR8rCL GR8:$src1)>;
3594 def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
3595 (SHR16rCL GR16:$src1)>;
3596 def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
3597 (SHR32rCL GR32:$src1)>;
3598 def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3599 (SHR8mCL addr:$dst)>;
3600 def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3601 (SHR16mCL addr:$dst)>;
3602 def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3603 (SHR32mCL addr:$dst)>;
3605 def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
3606 (SAR8rCL GR8:$src1)>;
3607 def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
3608 (SAR16rCL GR16:$src1)>;
3609 def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
3610 (SAR32rCL GR32:$src1)>;
3611 def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3612 (SAR8mCL addr:$dst)>;
3613 def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3614 (SAR16mCL addr:$dst)>;
3615 def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3616 (SAR32mCL addr:$dst)>;
3618 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
3619 def : Pat<(or (srl GR32:$src1, CL:$amt),
3620 (shl GR32:$src2, (sub 32, CL:$amt))),
3621 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3623 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
3624 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3625 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3627 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
3628 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3629 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3631 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3632 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3634 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3636 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3637 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3639 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
3640 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3641 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3643 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
3644 def : Pat<(or (shl GR32:$src1, CL:$amt),
3645 (srl GR32:$src2, (sub 32, CL:$amt))),
3646 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3648 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
3649 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3650 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3652 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
3653 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3654 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3656 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3657 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3659 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3661 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3662 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3664 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
3665 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3666 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3668 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
3669 def : Pat<(or (srl GR16:$src1, CL:$amt),
3670 (shl GR16:$src2, (sub 16, CL:$amt))),
3671 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3673 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
3674 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3675 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3677 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
3678 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3679 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3681 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3682 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3684 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3686 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3687 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3689 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
3690 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3691 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3693 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
3694 def : Pat<(or (shl GR16:$src1, CL:$amt),
3695 (srl GR16:$src2, (sub 16, CL:$amt))),
3696 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3698 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
3699 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3700 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3702 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
3703 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3704 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3706 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3707 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3709 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3711 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3712 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3714 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
3715 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3716 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3718 //===----------------------------------------------------------------------===//
3719 // EFLAGS-defining Patterns
3720 //===----------------------------------------------------------------------===//
3722 // Register-Register Addition with EFLAGS result
3723 def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
3725 (ADD8rr GR8:$src1, GR8:$src2)>;
3726 def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
3728 (ADD16rr GR16:$src1, GR16:$src2)>;
3729 def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
3731 (ADD32rr GR32:$src1, GR32:$src2)>;
3733 // Register-Memory Addition with EFLAGS result
3734 def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
3736 (ADD8rm GR8:$src1, addr:$src2)>;
3737 def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
3739 (ADD16rm GR16:$src1, addr:$src2)>;
3740 def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
3742 (ADD32rm GR32:$src1, addr:$src2)>;
3744 // Register-Integer Addition with EFLAGS result
3745 def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
3747 (ADD8ri GR8:$src1, imm:$src2)>;
3748 def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
3750 (ADD16ri GR16:$src1, imm:$src2)>;
3751 def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
3753 (ADD32ri GR32:$src1, imm:$src2)>;
3754 def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
3756 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
3757 def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
3759 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3761 // Memory-Register Addition with EFLAGS result
3762 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
3765 (ADD8mr addr:$dst, GR8:$src2)>;
3766 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
3769 (ADD16mr addr:$dst, GR16:$src2)>;
3770 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
3773 (ADD32mr addr:$dst, GR32:$src2)>;
3775 // Memory-Integer Addition with EFLAGS result
3776 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
3779 (ADD8mi addr:$dst, imm:$src2)>;
3780 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
3783 (ADD16mi addr:$dst, imm:$src2)>;
3784 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
3787 (ADD32mi addr:$dst, imm:$src2)>;
3788 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
3791 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
3792 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
3795 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
3797 // Register-Register Subtraction with EFLAGS result
3798 def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
3800 (SUB8rr GR8:$src1, GR8:$src2)>;
3801 def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
3803 (SUB16rr GR16:$src1, GR16:$src2)>;
3804 def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
3806 (SUB32rr GR32:$src1, GR32:$src2)>;
3808 // Register-Memory Subtraction with EFLAGS result
3809 def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
3811 (SUB8rm GR8:$src1, addr:$src2)>;
3812 def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
3814 (SUB16rm GR16:$src1, addr:$src2)>;
3815 def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
3817 (SUB32rm GR32:$src1, addr:$src2)>;
3819 // Register-Integer Subtraction with EFLAGS result
3820 def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
3822 (SUB8ri GR8:$src1, imm:$src2)>;
3823 def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
3825 (SUB16ri GR16:$src1, imm:$src2)>;
3826 def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
3828 (SUB32ri GR32:$src1, imm:$src2)>;
3829 def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
3831 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
3832 def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
3834 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3836 // Memory-Register Subtraction with EFLAGS result
3837 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
3840 (SUB8mr addr:$dst, GR8:$src2)>;
3841 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
3844 (SUB16mr addr:$dst, GR16:$src2)>;
3845 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
3848 (SUB32mr addr:$dst, GR32:$src2)>;
3850 // Memory-Integer Subtraction with EFLAGS result
3851 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
3854 (SUB8mi addr:$dst, imm:$src2)>;
3855 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
3858 (SUB16mi addr:$dst, imm:$src2)>;
3859 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
3862 (SUB32mi addr:$dst, imm:$src2)>;
3863 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
3866 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
3867 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
3870 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
3873 // Register-Register Signed Integer Multiply with EFLAGS result
3874 def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
3876 (IMUL16rr GR16:$src1, GR16:$src2)>;
3877 def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
3879 (IMUL32rr GR32:$src1, GR32:$src2)>;
3881 // Register-Memory Signed Integer Multiply with EFLAGS result
3882 def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
3884 (IMUL16rm GR16:$src1, addr:$src2)>;
3885 def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
3887 (IMUL32rm GR32:$src1, addr:$src2)>;
3889 // Register-Integer Signed Integer Multiply with EFLAGS result
3890 def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
3892 (IMUL16rri GR16:$src1, imm:$src2)>;
3893 def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
3895 (IMUL32rri GR32:$src1, imm:$src2)>;
3896 def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
3898 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
3899 def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
3901 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
3903 // Memory-Integer Signed Integer Multiply with EFLAGS result
3904 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
3906 (IMUL16rmi addr:$src1, imm:$src2)>;
3907 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
3909 (IMUL32rmi addr:$src1, imm:$src2)>;
3910 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
3912 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
3913 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
3915 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
3917 // Optimize multiply by 2 with EFLAGS result.
3918 let AddedComplexity = 2 in {
3919 def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
3921 (ADD16rr GR16:$src1, GR16:$src1)>;
3923 def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
3925 (ADD32rr GR32:$src1, GR32:$src1)>;
3928 // INC and DEC with EFLAGS result. Note that these do not set CF.
3929 def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
3931 def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
3934 def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
3936 def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
3940 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
3941 (INC16r GR16:$src)>, Requires<[In32BitMode]>;
3942 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
3944 (INC16m addr:$dst)>, Requires<[In32BitMode]>;
3945 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
3946 (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
3947 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
3949 (DEC16m addr:$dst)>, Requires<[In32BitMode]>;
3951 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
3952 (INC32r GR32:$src)>, Requires<[In32BitMode]>;
3953 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
3955 (INC32m addr:$dst)>, Requires<[In32BitMode]>;
3956 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
3957 (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
3958 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
3960 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
3962 //===----------------------------------------------------------------------===//
3963 // Floating Point Stack Support
3964 //===----------------------------------------------------------------------===//
3966 include "X86InstrFPStack.td"
3968 //===----------------------------------------------------------------------===//
3970 //===----------------------------------------------------------------------===//
3972 include "X86Instr64bit.td"
3974 //===----------------------------------------------------------------------===//
3975 // XMM Floating point support (requires SSE / SSE2)
3976 //===----------------------------------------------------------------------===//
3978 include "X86InstrSSE.td"
3980 //===----------------------------------------------------------------------===//
3981 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
3982 //===----------------------------------------------------------------------===//
3984 include "X86InstrMMX.td"