1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
33 def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
37 def SDTX86BrCond : SDTypeProfile<0, 3,
38 [SDTCisVT<0, OtherVT>,
39 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
41 def SDTX86SetCC : SDTypeProfile<1, 2,
43 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
47 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
49 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
50 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
51 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
53 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
54 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
57 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
59 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
63 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
65 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
67 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
69 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
71 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
73 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
75 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
77 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
78 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
79 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
80 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
82 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
84 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
86 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
87 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
89 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
91 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
92 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
94 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
95 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
97 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
98 [SDNPHasChain, SDNPMayStore,
99 SDNPMayLoad, SDNPMemOperand]>;
100 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
101 [SDNPHasChain, SDNPMayStore,
102 SDNPMayLoad, SDNPMemOperand]>;
103 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
104 [SDNPHasChain, SDNPMayStore,
105 SDNPMayLoad, SDNPMemOperand]>;
106 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
107 [SDNPHasChain, SDNPMayStore,
108 SDNPMayLoad, SDNPMemOperand]>;
109 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
110 [SDNPHasChain, SDNPMayStore,
111 SDNPMayLoad, SDNPMemOperand]>;
112 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
113 [SDNPHasChain, SDNPMayStore,
114 SDNPMayLoad, SDNPMemOperand]>;
115 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
116 [SDNPHasChain, SDNPMayStore,
117 SDNPMayLoad, SDNPMemOperand]>;
118 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
119 [SDNPHasChain, SDNPOptInFlag]>;
121 def X86vastart_save_xmm_regs :
122 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
123 SDT_X86VASTART_SAVE_XMM_REGS,
126 def X86callseq_start :
127 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
128 [SDNPHasChain, SDNPOutFlag]>;
130 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
131 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
133 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
134 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
136 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
137 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
138 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
139 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
142 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
143 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
145 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
146 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
148 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
149 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
150 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
151 SDT_X86SegmentBaseAddress, []>;
153 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
156 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
157 [SDNPHasChain, SDNPOptInFlag]>;
159 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags>;
160 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
161 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags>;
162 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>;
163 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
164 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
166 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
168 //===----------------------------------------------------------------------===//
169 // X86 Operand Definitions.
172 def i32imm_pcrel : Operand<i32> {
173 let PrintMethod = "print_pcrel_imm";
176 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
177 // the index operand of an address, to conform to x86 encoding restrictions.
178 def ptr_rc_nosp : PointerLikeRegClass<1>;
180 // *mem - Operand definitions for the funky X86 addressing mode operands.
182 def X86MemAsmOperand : AsmOperandClass {
186 class X86MemOperand<string printMethod> : Operand<iPTR> {
187 let PrintMethod = printMethod;
188 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
189 let ParserMatchClass = X86MemAsmOperand;
192 def opaque32mem : X86MemOperand<"printopaquemem">;
193 def opaque48mem : X86MemOperand<"printopaquemem">;
194 def opaque80mem : X86MemOperand<"printopaquemem">;
196 def i8mem : X86MemOperand<"printi8mem">;
197 def i16mem : X86MemOperand<"printi16mem">;
198 def i32mem : X86MemOperand<"printi32mem">;
199 def i64mem : X86MemOperand<"printi64mem">;
200 def i128mem : X86MemOperand<"printi128mem">;
201 def i256mem : X86MemOperand<"printi256mem">;
202 def f32mem : X86MemOperand<"printf32mem">;
203 def f64mem : X86MemOperand<"printf64mem">;
204 def f80mem : X86MemOperand<"printf80mem">;
205 def f128mem : X86MemOperand<"printf128mem">;
206 def f256mem : X86MemOperand<"printf256mem">;
208 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
209 // plain GR64, so that it doesn't potentially require a REX prefix.
210 def i8mem_NOREX : Operand<i64> {
211 let PrintMethod = "printi8mem";
212 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
213 let ParserMatchClass = X86MemAsmOperand;
216 def lea32mem : Operand<i32> {
217 let PrintMethod = "printlea32mem";
218 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
219 let ParserMatchClass = X86MemAsmOperand;
222 def SSECC : Operand<i8> {
223 let PrintMethod = "printSSECC";
226 def piclabel: Operand<i32> {
227 let PrintMethod = "printPICLabel";
230 def ImmSExt8AsmOperand : AsmOperandClass {
231 let Name = "ImmSExt8";
232 let SuperClass = ImmAsmOperand;
235 // A couple of more descriptive operand definitions.
236 // 16-bits but only 8 bits are significant.
237 def i16i8imm : Operand<i16> {
238 let ParserMatchClass = ImmSExt8AsmOperand;
240 // 32-bits but only 8 bits are significant.
241 def i32i8imm : Operand<i32> {
242 let ParserMatchClass = ImmSExt8AsmOperand;
245 // Branch targets have OtherVT type and print as pc-relative values.
246 def brtarget : Operand<OtherVT> {
247 let PrintMethod = "print_pcrel_imm";
250 def brtarget8 : Operand<OtherVT> {
251 let PrintMethod = "print_pcrel_imm";
254 //===----------------------------------------------------------------------===//
255 // X86 Complex Pattern Definitions.
258 // Define X86 specific addressing mode.
259 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
260 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
261 [add, sub, mul, X86mul_imm, shl, or, frameindex],
263 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
264 [tglobaltlsaddr], []>;
266 //===----------------------------------------------------------------------===//
267 // X86 Instruction Predicate Definitions.
268 def HasMMX : Predicate<"Subtarget->hasMMX()">;
269 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
270 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
271 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
272 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
273 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
274 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
275 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
276 def HasAVX : Predicate<"Subtarget->hasAVX()">;
277 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
278 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
279 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
280 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
281 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
282 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
283 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
284 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
285 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
286 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
287 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
288 "TM.getCodeModel() != CodeModel::Kernel">;
289 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
290 "TM.getCodeModel() == CodeModel::Kernel">;
291 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
292 def OptForSpeed : Predicate<"!OptForSize">;
293 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
294 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
296 //===----------------------------------------------------------------------===//
297 // X86 Instruction Format Definitions.
300 include "X86InstrFormats.td"
302 //===----------------------------------------------------------------------===//
303 // Pattern fragments...
306 // X86 specific condition code. These correspond to CondCode in
307 // X86InstrInfo.h. They must be kept in synch.
308 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
309 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
310 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
311 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
312 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
313 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
314 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
315 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
316 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
317 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
318 def X86_COND_NO : PatLeaf<(i8 10)>;
319 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
320 def X86_COND_NS : PatLeaf<(i8 12)>;
321 def X86_COND_O : PatLeaf<(i8 13)>;
322 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
323 def X86_COND_S : PatLeaf<(i8 15)>;
325 def i16immSExt8 : PatLeaf<(i16 imm), [{
326 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
327 // sign extended field.
328 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
331 def i32immSExt8 : PatLeaf<(i32 imm), [{
332 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
333 // sign extended field.
334 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
337 // Helper fragments for loads.
338 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
339 // known to be 32-bit aligned or better. Ditto for i8 to i16.
340 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
341 LoadSDNode *LD = cast<LoadSDNode>(N);
342 if (const Value *Src = LD->getSrcValue())
343 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
344 if (PT->getAddressSpace() > 255)
346 ISD::LoadExtType ExtType = LD->getExtensionType();
347 if (ExtType == ISD::NON_EXTLOAD)
349 if (ExtType == ISD::EXTLOAD)
350 return LD->getAlignment() >= 2 && !LD->isVolatile();
354 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
355 LoadSDNode *LD = cast<LoadSDNode>(N);
356 if (const Value *Src = LD->getSrcValue())
357 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
358 if (PT->getAddressSpace() > 255)
360 ISD::LoadExtType ExtType = LD->getExtensionType();
361 if (ExtType == ISD::EXTLOAD)
362 return LD->getAlignment() >= 2 && !LD->isVolatile();
366 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
367 LoadSDNode *LD = cast<LoadSDNode>(N);
368 if (const Value *Src = LD->getSrcValue())
369 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
370 if (PT->getAddressSpace() > 255)
372 ISD::LoadExtType ExtType = LD->getExtensionType();
373 if (ExtType == ISD::NON_EXTLOAD)
375 if (ExtType == ISD::EXTLOAD)
376 return LD->getAlignment() >= 4 && !LD->isVolatile();
380 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
381 LoadSDNode *LD = cast<LoadSDNode>(N);
382 if (const Value *Src = LD->getSrcValue())
383 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
384 if (PT->getAddressSpace() > 255)
386 if (LD->isVolatile())
388 ISD::LoadExtType ExtType = LD->getExtensionType();
389 if (ExtType == ISD::NON_EXTLOAD)
391 if (ExtType == ISD::EXTLOAD)
392 return LD->getAlignment() >= 4;
396 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
397 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
398 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
399 return PT->getAddressSpace() == 256;
403 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
404 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
405 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
406 return PT->getAddressSpace() == 257;
410 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{
411 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
412 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
413 if (PT->getAddressSpace() > 255)
417 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{
418 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
419 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
420 if (PT->getAddressSpace() > 255)
425 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{
426 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
427 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
428 if (PT->getAddressSpace() > 255)
432 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{
433 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
434 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
435 if (PT->getAddressSpace() > 255)
439 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{
440 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
441 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
442 if (PT->getAddressSpace() > 255)
447 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
448 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
449 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
451 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
452 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
453 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
454 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
455 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
456 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
458 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
459 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
460 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
461 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
462 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
463 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
466 // An 'and' node with a single use.
467 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
468 return N->hasOneUse();
470 // An 'srl' node with a single use.
471 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
472 return N->hasOneUse();
474 // An 'trunc' node with a single use.
475 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
476 return N->hasOneUse();
479 // 'shld' and 'shrd' instruction patterns. Note that even though these have
480 // the srl and shl in their patterns, the C++ code must still check for them,
481 // because predicates are tested before children nodes are explored.
483 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
484 (or (srl node:$src1, node:$amt1),
485 (shl node:$src2, node:$amt2)), [{
486 assert(N->getOpcode() == ISD::OR);
487 return N->getOperand(0).getOpcode() == ISD::SRL &&
488 N->getOperand(1).getOpcode() == ISD::SHL &&
489 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
490 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
491 N->getOperand(0).getConstantOperandVal(1) ==
492 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
495 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
496 (or (shl node:$src1, node:$amt1),
497 (srl node:$src2, node:$amt2)), [{
498 assert(N->getOpcode() == ISD::OR);
499 return N->getOperand(0).getOpcode() == ISD::SHL &&
500 N->getOperand(1).getOpcode() == ISD::SRL &&
501 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
502 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
503 N->getOperand(0).getConstantOperandVal(1) ==
504 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
507 //===----------------------------------------------------------------------===//
508 // Instruction list...
511 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
512 // a stack adjustment and the codegen must know that they may modify the stack
513 // pointer before prolog-epilog rewriting occurs.
514 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
515 // sub / add which can clobber EFLAGS.
516 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
517 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
519 [(X86callseq_start timm:$amt)]>,
520 Requires<[In32BitMode]>;
521 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
523 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
524 Requires<[In32BitMode]>;
527 // x86-64 va_start lowering magic.
528 let usesCustomDAGSchedInserter = 1 in
529 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
532 i64imm:$regsavefi, i64imm:$offset,
534 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
535 [(X86vastart_save_xmm_regs GR8:$al,
540 let neverHasSideEffects = 1 in {
541 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
542 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
543 "nopl\t$zero", []>, TB;
547 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int 3", []>;
548 def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
551 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
552 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
556 //===----------------------------------------------------------------------===//
557 // Control Flow Instructions...
560 // Return instructions.
561 let isTerminator = 1, isReturn = 1, isBarrier = 1,
562 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
563 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
566 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
568 [(X86retflag timm:$amt)]>;
571 // All branches are RawFrm, Void, Branch, and Terminators
572 let isBranch = 1, isTerminator = 1 in
573 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
574 I<opcode, RawFrm, (outs), ins, asm, pattern>;
576 let isBranch = 1, isBarrier = 1 in {
577 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
578 def JMP8 : IBr<0xEB, (ins brtarget8:$dst), "jmp\t$dst", []>;
582 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
583 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
584 [(brind GR32:$dst)]>;
585 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
586 [(brind (loadi32 addr:$dst))]>;
588 def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
589 (ins i16imm:$seg, i16imm:$off),
590 "ljmp{w}\t$seg, $off", []>, OpSize;
591 def FARJMP32i : Iseg32<0xEA, RawFrm, (outs),
592 (ins i16imm:$seg, i32imm:$off),
593 "ljmp{l}\t$seg, $off", []>;
595 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
596 "ljmp{w}\t{*}$dst", []>, OpSize;
597 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
598 "ljmp{l}\t{*}$dst", []>;
601 // Conditional branches
602 let Uses = [EFLAGS] in {
603 // Short conditional jumps
604 def JO8 : IBr<0x70, (ins brtarget8:$dst), "jo\t$dst", []>;
605 def JNO8 : IBr<0x71, (ins brtarget8:$dst), "jno\t$dst", []>;
606 def JB8 : IBr<0x72, (ins brtarget8:$dst), "jb\t$dst", []>;
607 def JAE8 : IBr<0x73, (ins brtarget8:$dst), "jae\t$dst", []>;
608 def JE8 : IBr<0x74, (ins brtarget8:$dst), "je\t$dst", []>;
609 def JNE8 : IBr<0x75, (ins brtarget8:$dst), "jne\t$dst", []>;
610 def JBE8 : IBr<0x76, (ins brtarget8:$dst), "jbe\t$dst", []>;
611 def JA8 : IBr<0x77, (ins brtarget8:$dst), "ja\t$dst", []>;
612 def JS8 : IBr<0x78, (ins brtarget8:$dst), "js\t$dst", []>;
613 def JNS8 : IBr<0x79, (ins brtarget8:$dst), "jns\t$dst", []>;
614 def JP8 : IBr<0x7A, (ins brtarget8:$dst), "jp\t$dst", []>;
615 def JNP8 : IBr<0x7B, (ins brtarget8:$dst), "jnp\t$dst", []>;
616 def JL8 : IBr<0x7C, (ins brtarget8:$dst), "jl\t$dst", []>;
617 def JGE8 : IBr<0x7D, (ins brtarget8:$dst), "jge\t$dst", []>;
618 def JLE8 : IBr<0x7E, (ins brtarget8:$dst), "jle\t$dst", []>;
619 def JG8 : IBr<0x7F, (ins brtarget8:$dst), "jg\t$dst", []>;
621 def JCXZ8 : IBr<0xE3, (ins brtarget8:$dst), "jcxz\t$dst", []>;
623 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
624 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
625 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
626 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
627 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
628 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
629 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
630 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
631 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
632 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
633 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
634 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
636 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
637 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
638 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
639 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
640 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
641 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
642 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
643 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
645 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
646 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
647 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
648 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
649 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
650 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
651 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
652 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
653 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
654 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
655 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
656 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
659 //===----------------------------------------------------------------------===//
660 // Call Instructions...
663 // All calls clobber the non-callee saved registers. ESP is marked as
664 // a use to prevent stack-pointer assignments that appear immediately
665 // before calls from potentially appearing dead. Uses for argument
666 // registers are added manually.
667 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
668 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
669 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
670 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
672 def CALLpcrel32 : Ii32<0xE8, RawFrm,
673 (outs), (ins i32imm_pcrel:$dst,variable_ops),
675 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
676 "call\t{*}$dst", [(X86call GR32:$dst)]>;
677 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
678 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
680 def FARCALL16i : Iseg16<0x9A, RawFrm, (outs),
681 (ins i16imm:$seg, i16imm:$off),
682 "lcall{w}\t$seg, $off", []>, OpSize;
683 def FARCALL32i : Iseg32<0x9A, RawFrm, (outs),
684 (ins i16imm:$seg, i32imm:$off),
685 "lcall{l}\t$seg, $off", []>;
687 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
688 "lcall{w}\t{*}$dst", []>, OpSize;
689 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
690 "lcall{l}\t{*}$dst", []>;
695 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
696 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops),
697 "#TC_RETURN $dst $offset",
700 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
701 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops),
702 "#TC_RETURN $dst $offset",
705 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
707 def TAILJMPd : IBr<0xE9, (ins i32imm_pcrel:$dst), "jmp\t$dst # TAILCALL",
709 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
710 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
712 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
713 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
714 "jmp\t{*}$dst # TAILCALL", []>;
716 //===----------------------------------------------------------------------===//
717 // Miscellaneous Instructions...
719 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
720 def LEAVE : I<0xC9, RawFrm,
721 (outs), (ins), "leave", []>;
723 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
725 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
727 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
728 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
730 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
732 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
733 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
736 let mayStore = 1 in {
737 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
739 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
740 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
742 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
744 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
745 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
749 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
750 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
751 "push{l}\t$imm", []>;
752 def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
753 "push{l}\t$imm", []>;
754 def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
755 "push{l}\t$imm", []>;
758 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
759 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
760 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
761 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
763 let isTwoAddress = 1 in // GR32 = bswap GR32
764 def BSWAP32r : I<0xC8, AddRegFrm,
765 (outs GR32:$dst), (ins GR32:$src),
767 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
770 // Bit scan instructions.
771 let Defs = [EFLAGS] in {
772 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
773 "bsf{w}\t{$src, $dst|$dst, $src}",
774 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
775 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
776 "bsf{w}\t{$src, $dst|$dst, $src}",
777 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
778 (implicit EFLAGS)]>, TB;
779 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
780 "bsf{l}\t{$src, $dst|$dst, $src}",
781 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
782 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
783 "bsf{l}\t{$src, $dst|$dst, $src}",
784 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
785 (implicit EFLAGS)]>, TB;
787 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
788 "bsr{w}\t{$src, $dst|$dst, $src}",
789 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
790 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
791 "bsr{w}\t{$src, $dst|$dst, $src}",
792 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
793 (implicit EFLAGS)]>, TB;
794 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
795 "bsr{l}\t{$src, $dst|$dst, $src}",
796 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
797 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
798 "bsr{l}\t{$src, $dst|$dst, $src}",
799 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
800 (implicit EFLAGS)]>, TB;
803 let neverHasSideEffects = 1 in
804 def LEA16r : I<0x8D, MRMSrcMem,
805 (outs GR16:$dst), (ins i32mem:$src),
806 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
807 let isReMaterializable = 1 in
808 def LEA32r : I<0x8D, MRMSrcMem,
809 (outs GR32:$dst), (ins lea32mem:$src),
810 "lea{l}\t{$src|$dst}, {$dst|$src}",
811 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
813 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
814 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
815 [(X86rep_movs i8)]>, REP;
816 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
817 [(X86rep_movs i16)]>, REP, OpSize;
818 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
819 [(X86rep_movs i32)]>, REP;
822 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
823 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
824 [(X86rep_stos i8)]>, REP;
825 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
826 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
827 [(X86rep_stos i16)]>, REP, OpSize;
828 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
829 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
830 [(X86rep_stos i32)]>, REP;
832 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
833 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
834 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
836 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
837 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
838 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
840 let Defs = [RAX, RDX] in
841 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
844 let isBarrier = 1, hasCtrlDep = 1 in {
845 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
848 def SYSCALL : I<0x05, RawFrm,
849 (outs), (ins), "syscall", []>, TB;
850 def SYSRET : I<0x07, RawFrm,
851 (outs), (ins), "sysret", []>, TB;
852 def SYSENTER : I<0x34, RawFrm,
853 (outs), (ins), "sysenter", []>, TB;
854 def SYSEXIT : I<0x35, RawFrm,
855 (outs), (ins), "sysexit", []>, TB;
857 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
860 //===----------------------------------------------------------------------===//
861 // Input/Output Instructions...
863 let Defs = [AL], Uses = [DX] in
864 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
865 "in{b}\t{%dx, %al|%AL, %DX}", []>;
866 let Defs = [AX], Uses = [DX] in
867 def IN16rr : I<0xED, RawFrm, (outs), (ins),
868 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
869 let Defs = [EAX], Uses = [DX] in
870 def IN32rr : I<0xED, RawFrm, (outs), (ins),
871 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
874 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
875 "in{b}\t{$port, %al|%AL, $port}", []>;
877 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
878 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
880 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
881 "in{l}\t{$port, %eax|%EAX, $port}", []>;
883 let Uses = [DX, AL] in
884 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
885 "out{b}\t{%al, %dx|%DX, %AL}", []>;
886 let Uses = [DX, AX] in
887 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
888 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
889 let Uses = [DX, EAX] in
890 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
891 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
894 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
895 "out{b}\t{%al, $port|$port, %AL}", []>;
897 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
898 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
900 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
901 "out{l}\t{%eax, $port|$port, %EAX}", []>;
903 //===----------------------------------------------------------------------===//
904 // Move Instructions...
906 let neverHasSideEffects = 1 in {
907 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
908 "mov{b}\t{$src, $dst|$dst, $src}", []>;
909 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
910 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
911 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
912 "mov{l}\t{$src, $dst|$dst, $src}", []>;
914 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
915 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
916 "mov{b}\t{$src, $dst|$dst, $src}",
917 [(set GR8:$dst, imm:$src)]>;
918 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
919 "mov{w}\t{$src, $dst|$dst, $src}",
920 [(set GR16:$dst, imm:$src)]>, OpSize;
921 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
922 "mov{l}\t{$src, $dst|$dst, $src}",
923 [(set GR32:$dst, imm:$src)]>;
925 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
926 "mov{b}\t{$src, $dst|$dst, $src}",
927 [(store (i8 imm:$src), addr:$dst)]>;
928 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
929 "mov{w}\t{$src, $dst|$dst, $src}",
930 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
931 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
932 "mov{l}\t{$src, $dst|$dst, $src}",
933 [(store (i32 imm:$src), addr:$dst)]>;
935 def MOV8o8a : Ii8 <0xA0, RawFrm, (outs), (ins i8imm:$src),
936 "mov{b}\t{$src, %al|%al, $src}", []>;
937 def MOV16o16a : Ii16 <0xA1, RawFrm, (outs), (ins i16imm:$src),
938 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
939 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins i32imm:$src),
940 "mov{l}\t{$src, %eax|%eax, $src}", []>;
942 def MOV8ao8 : Ii8 <0xA2, RawFrm, (outs i8imm:$dst), (ins),
943 "mov{b}\t{%al, $dst|$dst, %al}", []>;
944 def MOV16ao16 : Ii16 <0xA3, RawFrm, (outs i16imm:$dst), (ins),
945 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize;
946 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs i32imm:$dst), (ins),
947 "mov{l}\t{%eax, $dst|$dst, %eax}", []>;
949 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
950 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
951 "mov{b}\t{$src, $dst|$dst, $src}",
952 [(set GR8:$dst, (loadi8 addr:$src))]>;
953 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
954 "mov{w}\t{$src, $dst|$dst, $src}",
955 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
956 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
957 "mov{l}\t{$src, $dst|$dst, $src}",
958 [(set GR32:$dst, (loadi32 addr:$src))]>;
961 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
962 "mov{b}\t{$src, $dst|$dst, $src}",
963 [(store GR8:$src, addr:$dst)]>;
964 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
965 "mov{w}\t{$src, $dst|$dst, $src}",
966 [(store GR16:$src, addr:$dst)]>, OpSize;
967 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
968 "mov{l}\t{$src, $dst|$dst, $src}",
969 [(store GR32:$src, addr:$dst)]>;
971 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
972 // that they can be used for copying and storing h registers, which can't be
973 // encoded when a REX prefix is present.
974 let neverHasSideEffects = 1 in
975 def MOV8rr_NOREX : I<0x88, MRMDestReg,
976 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
977 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
979 def MOV8mr_NOREX : I<0x88, MRMDestMem,
980 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
981 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
983 canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
984 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
985 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
986 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
988 //===----------------------------------------------------------------------===//
989 // Fixed-Register Multiplication and Division Instructions...
992 // Extra precision multiplication
993 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
994 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
995 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
996 // This probably ought to be moved to a def : Pat<> if the
997 // syntax can be accepted.
998 [(set AL, (mul AL, GR8:$src)),
999 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1001 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1002 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1004 []>, OpSize; // AX,DX = AX*GR16
1006 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1007 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1009 []>; // EAX,EDX = EAX*GR32
1011 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1012 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1014 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1015 // This probably ought to be moved to a def : Pat<> if the
1016 // syntax can be accepted.
1017 [(set AL, (mul AL, (loadi8 addr:$src))),
1018 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1020 let mayLoad = 1, neverHasSideEffects = 1 in {
1021 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1022 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1024 []>, OpSize; // AX,DX = AX*[mem16]
1026 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1027 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1029 []>; // EAX,EDX = EAX*[mem32]
1032 let neverHasSideEffects = 1 in {
1033 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1034 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1036 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1037 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1038 OpSize; // AX,DX = AX*GR16
1039 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1040 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1041 // EAX,EDX = EAX*GR32
1042 let mayLoad = 1 in {
1043 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1044 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1045 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1046 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1047 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1048 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1049 let Defs = [EAX,EDX], Uses = [EAX] in
1050 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1051 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1053 } // neverHasSideEffects
1055 // unsigned division/remainder
1056 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1057 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1058 "div{b}\t$src", []>;
1059 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1060 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1061 "div{w}\t$src", []>, OpSize;
1062 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1063 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1064 "div{l}\t$src", []>;
1065 let mayLoad = 1 in {
1066 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1067 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1068 "div{b}\t$src", []>;
1069 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1070 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1071 "div{w}\t$src", []>, OpSize;
1072 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1073 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
1074 "div{l}\t$src", []>;
1077 // Signed division/remainder.
1078 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1079 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1080 "idiv{b}\t$src", []>;
1081 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1082 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1083 "idiv{w}\t$src", []>, OpSize;
1084 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1085 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1086 "idiv{l}\t$src", []>;
1087 let mayLoad = 1, mayLoad = 1 in {
1088 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1089 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1090 "idiv{b}\t$src", []>;
1091 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1092 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1093 "idiv{w}\t$src", []>, OpSize;
1094 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1095 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
1096 "idiv{l}\t$src", []>;
1099 //===----------------------------------------------------------------------===//
1100 // Two address Instructions.
1102 let isTwoAddress = 1 in {
1104 // Conditional moves
1105 let Uses = [EFLAGS] in {
1107 // X86 doesn't have 8-bit conditional moves. Use a customDAGSchedInserter to
1108 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1109 // however that requires promoting the operands, and can induce additional
1110 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1111 // clobber EFLAGS, because if one of the operands is zero, the expansion
1112 // could involve an xor.
1113 let usesCustomDAGSchedInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in
1114 def CMOV_GR8 : I<0, Pseudo,
1115 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1116 "#CMOV_GR8 PSEUDO!",
1117 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1118 imm:$cond, EFLAGS))]>;
1120 let isCommutable = 1 in {
1121 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1122 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1123 "cmovb\t{$src2, $dst|$dst, $src2}",
1124 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1125 X86_COND_B, EFLAGS))]>,
1127 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1128 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1129 "cmovb\t{$src2, $dst|$dst, $src2}",
1130 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1131 X86_COND_B, EFLAGS))]>,
1133 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1134 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1135 "cmovae\t{$src2, $dst|$dst, $src2}",
1136 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1137 X86_COND_AE, EFLAGS))]>,
1139 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1140 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1141 "cmovae\t{$src2, $dst|$dst, $src2}",
1142 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1143 X86_COND_AE, EFLAGS))]>,
1145 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1146 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1147 "cmove\t{$src2, $dst|$dst, $src2}",
1148 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1149 X86_COND_E, EFLAGS))]>,
1151 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1152 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1153 "cmove\t{$src2, $dst|$dst, $src2}",
1154 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1155 X86_COND_E, EFLAGS))]>,
1157 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1158 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1159 "cmovne\t{$src2, $dst|$dst, $src2}",
1160 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1161 X86_COND_NE, EFLAGS))]>,
1163 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1164 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1165 "cmovne\t{$src2, $dst|$dst, $src2}",
1166 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1167 X86_COND_NE, EFLAGS))]>,
1169 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1170 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1171 "cmovbe\t{$src2, $dst|$dst, $src2}",
1172 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1173 X86_COND_BE, EFLAGS))]>,
1175 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1176 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1177 "cmovbe\t{$src2, $dst|$dst, $src2}",
1178 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1179 X86_COND_BE, EFLAGS))]>,
1181 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1182 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1183 "cmova\t{$src2, $dst|$dst, $src2}",
1184 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1185 X86_COND_A, EFLAGS))]>,
1187 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1188 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1189 "cmova\t{$src2, $dst|$dst, $src2}",
1190 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1191 X86_COND_A, EFLAGS))]>,
1193 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1194 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1195 "cmovl\t{$src2, $dst|$dst, $src2}",
1196 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1197 X86_COND_L, EFLAGS))]>,
1199 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1200 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1201 "cmovl\t{$src2, $dst|$dst, $src2}",
1202 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1203 X86_COND_L, EFLAGS))]>,
1205 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1206 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1207 "cmovge\t{$src2, $dst|$dst, $src2}",
1208 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1209 X86_COND_GE, EFLAGS))]>,
1211 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1212 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1213 "cmovge\t{$src2, $dst|$dst, $src2}",
1214 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1215 X86_COND_GE, EFLAGS))]>,
1217 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1218 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1219 "cmovle\t{$src2, $dst|$dst, $src2}",
1220 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1221 X86_COND_LE, EFLAGS))]>,
1223 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1224 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1225 "cmovle\t{$src2, $dst|$dst, $src2}",
1226 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1227 X86_COND_LE, EFLAGS))]>,
1229 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1230 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1231 "cmovg\t{$src2, $dst|$dst, $src2}",
1232 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1233 X86_COND_G, EFLAGS))]>,
1235 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1236 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1237 "cmovg\t{$src2, $dst|$dst, $src2}",
1238 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1239 X86_COND_G, EFLAGS))]>,
1241 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1242 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1243 "cmovs\t{$src2, $dst|$dst, $src2}",
1244 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1245 X86_COND_S, EFLAGS))]>,
1247 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1248 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1249 "cmovs\t{$src2, $dst|$dst, $src2}",
1250 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1251 X86_COND_S, EFLAGS))]>,
1253 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1254 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1255 "cmovns\t{$src2, $dst|$dst, $src2}",
1256 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1257 X86_COND_NS, EFLAGS))]>,
1259 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1260 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1261 "cmovns\t{$src2, $dst|$dst, $src2}",
1262 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1263 X86_COND_NS, EFLAGS))]>,
1265 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1266 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1267 "cmovp\t{$src2, $dst|$dst, $src2}",
1268 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1269 X86_COND_P, EFLAGS))]>,
1271 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1272 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1273 "cmovp\t{$src2, $dst|$dst, $src2}",
1274 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1275 X86_COND_P, EFLAGS))]>,
1277 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1278 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1279 "cmovnp\t{$src2, $dst|$dst, $src2}",
1280 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1281 X86_COND_NP, EFLAGS))]>,
1283 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1284 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1285 "cmovnp\t{$src2, $dst|$dst, $src2}",
1286 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1287 X86_COND_NP, EFLAGS))]>,
1289 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1290 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1291 "cmovo\t{$src2, $dst|$dst, $src2}",
1292 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1293 X86_COND_O, EFLAGS))]>,
1295 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1296 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1297 "cmovo\t{$src2, $dst|$dst, $src2}",
1298 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1299 X86_COND_O, EFLAGS))]>,
1301 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1302 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1303 "cmovno\t{$src2, $dst|$dst, $src2}",
1304 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1305 X86_COND_NO, EFLAGS))]>,
1307 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1308 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1309 "cmovno\t{$src2, $dst|$dst, $src2}",
1310 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1311 X86_COND_NO, EFLAGS))]>,
1313 } // isCommutable = 1
1315 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1316 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1317 "cmovb\t{$src2, $dst|$dst, $src2}",
1318 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1319 X86_COND_B, EFLAGS))]>,
1321 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1322 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1323 "cmovb\t{$src2, $dst|$dst, $src2}",
1324 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1325 X86_COND_B, EFLAGS))]>,
1327 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1328 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1329 "cmovae\t{$src2, $dst|$dst, $src2}",
1330 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1331 X86_COND_AE, EFLAGS))]>,
1333 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1334 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1335 "cmovae\t{$src2, $dst|$dst, $src2}",
1336 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1337 X86_COND_AE, EFLAGS))]>,
1339 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1340 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1341 "cmove\t{$src2, $dst|$dst, $src2}",
1342 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1343 X86_COND_E, EFLAGS))]>,
1345 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1346 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1347 "cmove\t{$src2, $dst|$dst, $src2}",
1348 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1349 X86_COND_E, EFLAGS))]>,
1351 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1352 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1353 "cmovne\t{$src2, $dst|$dst, $src2}",
1354 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1355 X86_COND_NE, EFLAGS))]>,
1357 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1358 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1359 "cmovne\t{$src2, $dst|$dst, $src2}",
1360 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1361 X86_COND_NE, EFLAGS))]>,
1363 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1364 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1365 "cmovbe\t{$src2, $dst|$dst, $src2}",
1366 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1367 X86_COND_BE, EFLAGS))]>,
1369 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1370 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1371 "cmovbe\t{$src2, $dst|$dst, $src2}",
1372 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1373 X86_COND_BE, EFLAGS))]>,
1375 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1376 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1377 "cmova\t{$src2, $dst|$dst, $src2}",
1378 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1379 X86_COND_A, EFLAGS))]>,
1381 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1382 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1383 "cmova\t{$src2, $dst|$dst, $src2}",
1384 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1385 X86_COND_A, EFLAGS))]>,
1387 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1388 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1389 "cmovl\t{$src2, $dst|$dst, $src2}",
1390 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1391 X86_COND_L, EFLAGS))]>,
1393 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1394 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1395 "cmovl\t{$src2, $dst|$dst, $src2}",
1396 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1397 X86_COND_L, EFLAGS))]>,
1399 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1400 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1401 "cmovge\t{$src2, $dst|$dst, $src2}",
1402 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1403 X86_COND_GE, EFLAGS))]>,
1405 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1406 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1407 "cmovge\t{$src2, $dst|$dst, $src2}",
1408 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1409 X86_COND_GE, EFLAGS))]>,
1411 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1412 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1413 "cmovle\t{$src2, $dst|$dst, $src2}",
1414 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1415 X86_COND_LE, EFLAGS))]>,
1417 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1418 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1419 "cmovle\t{$src2, $dst|$dst, $src2}",
1420 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1421 X86_COND_LE, EFLAGS))]>,
1423 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1424 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1425 "cmovg\t{$src2, $dst|$dst, $src2}",
1426 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1427 X86_COND_G, EFLAGS))]>,
1429 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1430 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1431 "cmovg\t{$src2, $dst|$dst, $src2}",
1432 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1433 X86_COND_G, EFLAGS))]>,
1435 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1436 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1437 "cmovs\t{$src2, $dst|$dst, $src2}",
1438 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1439 X86_COND_S, EFLAGS))]>,
1441 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1442 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1443 "cmovs\t{$src2, $dst|$dst, $src2}",
1444 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1445 X86_COND_S, EFLAGS))]>,
1447 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1448 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1449 "cmovns\t{$src2, $dst|$dst, $src2}",
1450 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1451 X86_COND_NS, EFLAGS))]>,
1453 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1454 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1455 "cmovns\t{$src2, $dst|$dst, $src2}",
1456 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1457 X86_COND_NS, EFLAGS))]>,
1459 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1460 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1461 "cmovp\t{$src2, $dst|$dst, $src2}",
1462 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1463 X86_COND_P, EFLAGS))]>,
1465 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1466 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1467 "cmovp\t{$src2, $dst|$dst, $src2}",
1468 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1469 X86_COND_P, EFLAGS))]>,
1471 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1472 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1473 "cmovnp\t{$src2, $dst|$dst, $src2}",
1474 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1475 X86_COND_NP, EFLAGS))]>,
1477 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1478 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1479 "cmovnp\t{$src2, $dst|$dst, $src2}",
1480 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1481 X86_COND_NP, EFLAGS))]>,
1483 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1484 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1485 "cmovo\t{$src2, $dst|$dst, $src2}",
1486 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1487 X86_COND_O, EFLAGS))]>,
1489 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1490 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1491 "cmovo\t{$src2, $dst|$dst, $src2}",
1492 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1493 X86_COND_O, EFLAGS))]>,
1495 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1496 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1497 "cmovno\t{$src2, $dst|$dst, $src2}",
1498 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1499 X86_COND_NO, EFLAGS))]>,
1501 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1502 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1503 "cmovno\t{$src2, $dst|$dst, $src2}",
1504 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1505 X86_COND_NO, EFLAGS))]>,
1507 } // Uses = [EFLAGS]
1510 // unary instructions
1511 let CodeSize = 2 in {
1512 let Defs = [EFLAGS] in {
1513 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1514 [(set GR8:$dst, (ineg GR8:$src)),
1515 (implicit EFLAGS)]>;
1516 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1517 [(set GR16:$dst, (ineg GR16:$src)),
1518 (implicit EFLAGS)]>, OpSize;
1519 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1520 [(set GR32:$dst, (ineg GR32:$src)),
1521 (implicit EFLAGS)]>;
1522 let isTwoAddress = 0 in {
1523 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1524 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1525 (implicit EFLAGS)]>;
1526 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1527 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1528 (implicit EFLAGS)]>, OpSize;
1529 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1530 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1531 (implicit EFLAGS)]>;
1533 } // Defs = [EFLAGS]
1535 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1536 let AddedComplexity = 15 in {
1537 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1538 [(set GR8:$dst, (not GR8:$src))]>;
1539 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1540 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1541 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1542 [(set GR32:$dst, (not GR32:$src))]>;
1544 let isTwoAddress = 0 in {
1545 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1546 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1547 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1548 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1549 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1550 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1554 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1555 let Defs = [EFLAGS] in {
1557 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1558 [(set GR8:$dst, (add GR8:$src, 1)),
1559 (implicit EFLAGS)]>;
1560 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1561 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1562 [(set GR16:$dst, (add GR16:$src, 1)),
1563 (implicit EFLAGS)]>,
1564 OpSize, Requires<[In32BitMode]>;
1565 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1566 [(set GR32:$dst, (add GR32:$src, 1)),
1567 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1569 let isTwoAddress = 0, CodeSize = 2 in {
1570 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1571 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1572 (implicit EFLAGS)]>;
1573 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1574 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1575 (implicit EFLAGS)]>,
1576 OpSize, Requires<[In32BitMode]>;
1577 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1578 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1579 (implicit EFLAGS)]>,
1580 Requires<[In32BitMode]>;
1584 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1585 [(set GR8:$dst, (add GR8:$src, -1)),
1586 (implicit EFLAGS)]>;
1587 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1588 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1589 [(set GR16:$dst, (add GR16:$src, -1)),
1590 (implicit EFLAGS)]>,
1591 OpSize, Requires<[In32BitMode]>;
1592 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1593 [(set GR32:$dst, (add GR32:$src, -1)),
1594 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1597 let isTwoAddress = 0, CodeSize = 2 in {
1598 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1599 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1600 (implicit EFLAGS)]>;
1601 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1602 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1603 (implicit EFLAGS)]>,
1604 OpSize, Requires<[In32BitMode]>;
1605 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1606 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1607 (implicit EFLAGS)]>,
1608 Requires<[In32BitMode]>;
1610 } // Defs = [EFLAGS]
1612 // Logical operators...
1613 let Defs = [EFLAGS] in {
1614 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1615 def AND8rr : I<0x20, MRMDestReg,
1616 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1617 "and{b}\t{$src2, $dst|$dst, $src2}",
1618 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
1619 (implicit EFLAGS)]>;
1620 def AND16rr : I<0x21, MRMDestReg,
1621 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1622 "and{w}\t{$src2, $dst|$dst, $src2}",
1623 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
1624 (implicit EFLAGS)]>, OpSize;
1625 def AND32rr : I<0x21, MRMDestReg,
1626 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1627 "and{l}\t{$src2, $dst|$dst, $src2}",
1628 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
1629 (implicit EFLAGS)]>;
1632 def AND8rm : I<0x22, MRMSrcMem,
1633 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1634 "and{b}\t{$src2, $dst|$dst, $src2}",
1635 [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
1636 (implicit EFLAGS)]>;
1637 def AND16rm : I<0x23, MRMSrcMem,
1638 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1639 "and{w}\t{$src2, $dst|$dst, $src2}",
1640 [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
1641 (implicit EFLAGS)]>, OpSize;
1642 def AND32rm : I<0x23, MRMSrcMem,
1643 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1644 "and{l}\t{$src2, $dst|$dst, $src2}",
1645 [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
1646 (implicit EFLAGS)]>;
1648 def AND8ri : Ii8<0x80, MRM4r,
1649 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1650 "and{b}\t{$src2, $dst|$dst, $src2}",
1651 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
1652 (implicit EFLAGS)]>;
1653 def AND16ri : Ii16<0x81, MRM4r,
1654 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1655 "and{w}\t{$src2, $dst|$dst, $src2}",
1656 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
1657 (implicit EFLAGS)]>, OpSize;
1658 def AND32ri : Ii32<0x81, MRM4r,
1659 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1660 "and{l}\t{$src2, $dst|$dst, $src2}",
1661 [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
1662 (implicit EFLAGS)]>;
1663 def AND16ri8 : Ii8<0x83, MRM4r,
1664 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1665 "and{w}\t{$src2, $dst|$dst, $src2}",
1666 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
1667 (implicit EFLAGS)]>,
1669 def AND32ri8 : Ii8<0x83, MRM4r,
1670 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1671 "and{l}\t{$src2, $dst|$dst, $src2}",
1672 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
1673 (implicit EFLAGS)]>;
1675 let isTwoAddress = 0 in {
1676 def AND8mr : I<0x20, MRMDestMem,
1677 (outs), (ins i8mem :$dst, GR8 :$src),
1678 "and{b}\t{$src, $dst|$dst, $src}",
1679 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1680 (implicit EFLAGS)]>;
1681 def AND16mr : I<0x21, MRMDestMem,
1682 (outs), (ins i16mem:$dst, GR16:$src),
1683 "and{w}\t{$src, $dst|$dst, $src}",
1684 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1685 (implicit EFLAGS)]>,
1687 def AND32mr : I<0x21, MRMDestMem,
1688 (outs), (ins i32mem:$dst, GR32:$src),
1689 "and{l}\t{$src, $dst|$dst, $src}",
1690 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1691 (implicit EFLAGS)]>;
1692 def AND8mi : Ii8<0x80, MRM4m,
1693 (outs), (ins i8mem :$dst, i8imm :$src),
1694 "and{b}\t{$src, $dst|$dst, $src}",
1695 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1696 (implicit EFLAGS)]>;
1697 def AND16mi : Ii16<0x81, MRM4m,
1698 (outs), (ins i16mem:$dst, i16imm:$src),
1699 "and{w}\t{$src, $dst|$dst, $src}",
1700 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1701 (implicit EFLAGS)]>,
1703 def AND32mi : Ii32<0x81, MRM4m,
1704 (outs), (ins i32mem:$dst, i32imm:$src),
1705 "and{l}\t{$src, $dst|$dst, $src}",
1706 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1707 (implicit EFLAGS)]>;
1708 def AND16mi8 : Ii8<0x83, MRM4m,
1709 (outs), (ins i16mem:$dst, i16i8imm :$src),
1710 "and{w}\t{$src, $dst|$dst, $src}",
1711 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1712 (implicit EFLAGS)]>,
1714 def AND32mi8 : Ii8<0x83, MRM4m,
1715 (outs), (ins i32mem:$dst, i32i8imm :$src),
1716 "and{l}\t{$src, $dst|$dst, $src}",
1717 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1718 (implicit EFLAGS)]>;
1720 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1721 "and{b}\t{$src, %al|%al, $src}", []>;
1722 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1723 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1724 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1725 "and{l}\t{$src, %eax|%eax, $src}", []>;
1730 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1731 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1732 "or{b}\t{$src2, $dst|$dst, $src2}",
1733 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
1734 (implicit EFLAGS)]>;
1735 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1736 "or{w}\t{$src2, $dst|$dst, $src2}",
1737 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
1738 (implicit EFLAGS)]>, OpSize;
1739 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1740 "or{l}\t{$src2, $dst|$dst, $src2}",
1741 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
1742 (implicit EFLAGS)]>;
1744 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1745 "or{b}\t{$src2, $dst|$dst, $src2}",
1746 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
1747 (implicit EFLAGS)]>;
1748 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1749 "or{w}\t{$src2, $dst|$dst, $src2}",
1750 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
1751 (implicit EFLAGS)]>, OpSize;
1752 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1753 "or{l}\t{$src2, $dst|$dst, $src2}",
1754 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
1755 (implicit EFLAGS)]>;
1757 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1758 "or{b}\t{$src2, $dst|$dst, $src2}",
1759 [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
1760 (implicit EFLAGS)]>;
1761 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1762 "or{w}\t{$src2, $dst|$dst, $src2}",
1763 [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
1764 (implicit EFLAGS)]>, OpSize;
1765 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1766 "or{l}\t{$src2, $dst|$dst, $src2}",
1767 [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
1768 (implicit EFLAGS)]>;
1770 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1771 "or{w}\t{$src2, $dst|$dst, $src2}",
1772 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
1773 (implicit EFLAGS)]>, OpSize;
1774 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1775 "or{l}\t{$src2, $dst|$dst, $src2}",
1776 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
1777 (implicit EFLAGS)]>;
1778 let isTwoAddress = 0 in {
1779 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1780 "or{b}\t{$src, $dst|$dst, $src}",
1781 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1782 (implicit EFLAGS)]>;
1783 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1784 "or{w}\t{$src, $dst|$dst, $src}",
1785 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1786 (implicit EFLAGS)]>, OpSize;
1787 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1788 "or{l}\t{$src, $dst|$dst, $src}",
1789 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1790 (implicit EFLAGS)]>;
1791 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1792 "or{b}\t{$src, $dst|$dst, $src}",
1793 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1794 (implicit EFLAGS)]>;
1795 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1796 "or{w}\t{$src, $dst|$dst, $src}",
1797 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1798 (implicit EFLAGS)]>,
1800 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1801 "or{l}\t{$src, $dst|$dst, $src}",
1802 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1803 (implicit EFLAGS)]>;
1804 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1805 "or{w}\t{$src, $dst|$dst, $src}",
1806 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1807 (implicit EFLAGS)]>,
1809 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1810 "or{l}\t{$src, $dst|$dst, $src}",
1811 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1812 (implicit EFLAGS)]>;
1814 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
1815 "or{b}\t{$src, %al|%al, $src}", []>;
1816 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
1817 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1818 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
1819 "or{l}\t{$src, %eax|%eax, $src}", []>;
1820 } // isTwoAddress = 0
1823 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1824 def XOR8rr : I<0x30, MRMDestReg,
1825 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1826 "xor{b}\t{$src2, $dst|$dst, $src2}",
1827 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
1828 (implicit EFLAGS)]>;
1829 def XOR16rr : I<0x31, MRMDestReg,
1830 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1831 "xor{w}\t{$src2, $dst|$dst, $src2}",
1832 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
1833 (implicit EFLAGS)]>, OpSize;
1834 def XOR32rr : I<0x31, MRMDestReg,
1835 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1836 "xor{l}\t{$src2, $dst|$dst, $src2}",
1837 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
1838 (implicit EFLAGS)]>;
1839 } // isCommutable = 1
1841 def XOR8rm : I<0x32, MRMSrcMem ,
1842 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1843 "xor{b}\t{$src2, $dst|$dst, $src2}",
1844 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
1845 (implicit EFLAGS)]>;
1846 def XOR16rm : I<0x33, MRMSrcMem ,
1847 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1848 "xor{w}\t{$src2, $dst|$dst, $src2}",
1849 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
1850 (implicit EFLAGS)]>,
1852 def XOR32rm : I<0x33, MRMSrcMem ,
1853 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1854 "xor{l}\t{$src2, $dst|$dst, $src2}",
1855 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
1856 (implicit EFLAGS)]>;
1858 def XOR8ri : Ii8<0x80, MRM6r,
1859 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1860 "xor{b}\t{$src2, $dst|$dst, $src2}",
1861 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
1862 (implicit EFLAGS)]>;
1863 def XOR16ri : Ii16<0x81, MRM6r,
1864 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1865 "xor{w}\t{$src2, $dst|$dst, $src2}",
1866 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
1867 (implicit EFLAGS)]>, OpSize;
1868 def XOR32ri : Ii32<0x81, MRM6r,
1869 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1870 "xor{l}\t{$src2, $dst|$dst, $src2}",
1871 [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
1872 (implicit EFLAGS)]>;
1873 def XOR16ri8 : Ii8<0x83, MRM6r,
1874 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1875 "xor{w}\t{$src2, $dst|$dst, $src2}",
1876 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
1877 (implicit EFLAGS)]>,
1879 def XOR32ri8 : Ii8<0x83, MRM6r,
1880 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1881 "xor{l}\t{$src2, $dst|$dst, $src2}",
1882 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
1883 (implicit EFLAGS)]>;
1885 let isTwoAddress = 0 in {
1886 def XOR8mr : I<0x30, MRMDestMem,
1887 (outs), (ins i8mem :$dst, GR8 :$src),
1888 "xor{b}\t{$src, $dst|$dst, $src}",
1889 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
1890 (implicit EFLAGS)]>;
1891 def XOR16mr : I<0x31, MRMDestMem,
1892 (outs), (ins i16mem:$dst, GR16:$src),
1893 "xor{w}\t{$src, $dst|$dst, $src}",
1894 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
1895 (implicit EFLAGS)]>,
1897 def XOR32mr : I<0x31, MRMDestMem,
1898 (outs), (ins i32mem:$dst, GR32:$src),
1899 "xor{l}\t{$src, $dst|$dst, $src}",
1900 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
1901 (implicit EFLAGS)]>;
1902 def XOR8mi : Ii8<0x80, MRM6m,
1903 (outs), (ins i8mem :$dst, i8imm :$src),
1904 "xor{b}\t{$src, $dst|$dst, $src}",
1905 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
1906 (implicit EFLAGS)]>;
1907 def XOR16mi : Ii16<0x81, MRM6m,
1908 (outs), (ins i16mem:$dst, i16imm:$src),
1909 "xor{w}\t{$src, $dst|$dst, $src}",
1910 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
1911 (implicit EFLAGS)]>,
1913 def XOR32mi : Ii32<0x81, MRM6m,
1914 (outs), (ins i32mem:$dst, i32imm:$src),
1915 "xor{l}\t{$src, $dst|$dst, $src}",
1916 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
1917 (implicit EFLAGS)]>;
1918 def XOR16mi8 : Ii8<0x83, MRM6m,
1919 (outs), (ins i16mem:$dst, i16i8imm :$src),
1920 "xor{w}\t{$src, $dst|$dst, $src}",
1921 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
1922 (implicit EFLAGS)]>,
1924 def XOR32mi8 : Ii8<0x83, MRM6m,
1925 (outs), (ins i32mem:$dst, i32i8imm :$src),
1926 "xor{l}\t{$src, $dst|$dst, $src}",
1927 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
1928 (implicit EFLAGS)]>;
1930 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
1931 "xor{b}\t{$src, %al|%al, $src}", []>;
1932 def XOR16i16 : Ii16 <0x35, RawFrm, (outs), (ins i16imm:$src),
1933 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1934 def XOR32i32 : Ii32 <0x35, RawFrm, (outs), (ins i32imm:$src),
1935 "xor{l}\t{$src, %eax|%eax, $src}", []>;
1936 } // isTwoAddress = 0
1937 } // Defs = [EFLAGS]
1939 // Shift instructions
1940 let Defs = [EFLAGS] in {
1941 let Uses = [CL] in {
1942 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1943 "shl{b}\t{%cl, $dst|$dst, CL}",
1944 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1945 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1946 "shl{w}\t{%cl, $dst|$dst, CL}",
1947 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1948 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1949 "shl{l}\t{%cl, $dst|$dst, CL}",
1950 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1953 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1954 "shl{b}\t{$src2, $dst|$dst, $src2}",
1955 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1956 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1957 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1958 "shl{w}\t{$src2, $dst|$dst, $src2}",
1959 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1960 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1961 "shl{l}\t{$src2, $dst|$dst, $src2}",
1962 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1963 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1965 } // isConvertibleToThreeAddress = 1
1967 let isTwoAddress = 0 in {
1968 let Uses = [CL] in {
1969 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1970 "shl{b}\t{%cl, $dst|$dst, CL}",
1971 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1972 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1973 "shl{w}\t{%cl, $dst|$dst, CL}",
1974 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1975 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1976 "shl{l}\t{%cl, $dst|$dst, CL}",
1977 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1979 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1980 "shl{b}\t{$src, $dst|$dst, $src}",
1981 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1982 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1983 "shl{w}\t{$src, $dst|$dst, $src}",
1984 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1986 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1987 "shl{l}\t{$src, $dst|$dst, $src}",
1988 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1991 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1993 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1994 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1996 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1998 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2000 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2003 let Uses = [CL] in {
2004 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
2005 "shr{b}\t{%cl, $dst|$dst, CL}",
2006 [(set GR8:$dst, (srl GR8:$src, CL))]>;
2007 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
2008 "shr{w}\t{%cl, $dst|$dst, CL}",
2009 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
2010 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
2011 "shr{l}\t{%cl, $dst|$dst, CL}",
2012 [(set GR32:$dst, (srl GR32:$src, CL))]>;
2015 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2016 "shr{b}\t{$src2, $dst|$dst, $src2}",
2017 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2018 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2019 "shr{w}\t{$src2, $dst|$dst, $src2}",
2020 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2021 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2022 "shr{l}\t{$src2, $dst|$dst, $src2}",
2023 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2026 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2028 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2029 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2031 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2032 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2034 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2036 let isTwoAddress = 0 in {
2037 let Uses = [CL] in {
2038 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2039 "shr{b}\t{%cl, $dst|$dst, CL}",
2040 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2041 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2042 "shr{w}\t{%cl, $dst|$dst, CL}",
2043 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2045 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2046 "shr{l}\t{%cl, $dst|$dst, CL}",
2047 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2049 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2050 "shr{b}\t{$src, $dst|$dst, $src}",
2051 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2052 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2053 "shr{w}\t{$src, $dst|$dst, $src}",
2054 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2056 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2057 "shr{l}\t{$src, $dst|$dst, $src}",
2058 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2061 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2063 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2064 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2066 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2067 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2069 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2072 let Uses = [CL] in {
2073 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
2074 "sar{b}\t{%cl, $dst|$dst, CL}",
2075 [(set GR8:$dst, (sra GR8:$src, CL))]>;
2076 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
2077 "sar{w}\t{%cl, $dst|$dst, CL}",
2078 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
2079 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
2080 "sar{l}\t{%cl, $dst|$dst, CL}",
2081 [(set GR32:$dst, (sra GR32:$src, CL))]>;
2084 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2085 "sar{b}\t{$src2, $dst|$dst, $src2}",
2086 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2087 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2088 "sar{w}\t{$src2, $dst|$dst, $src2}",
2089 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2091 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2092 "sar{l}\t{$src2, $dst|$dst, $src2}",
2093 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2096 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2098 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2099 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2101 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2102 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2104 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2106 let isTwoAddress = 0 in {
2107 let Uses = [CL] in {
2108 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2109 "sar{b}\t{%cl, $dst|$dst, CL}",
2110 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2111 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2112 "sar{w}\t{%cl, $dst|$dst, CL}",
2113 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2114 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2115 "sar{l}\t{%cl, $dst|$dst, CL}",
2116 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2118 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2119 "sar{b}\t{$src, $dst|$dst, $src}",
2120 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2121 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2122 "sar{w}\t{$src, $dst|$dst, $src}",
2123 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2125 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2126 "sar{l}\t{$src, $dst|$dst, $src}",
2127 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2130 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2132 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2133 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2135 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2137 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2139 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2142 // Rotate instructions
2143 // FIXME: provide shorter instructions when imm8 == 1
2144 let Uses = [CL] in {
2145 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
2146 "rol{b}\t{%cl, $dst|$dst, CL}",
2147 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
2148 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
2149 "rol{w}\t{%cl, $dst|$dst, CL}",
2150 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
2151 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
2152 "rol{l}\t{%cl, $dst|$dst, CL}",
2153 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2156 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2157 "rol{b}\t{$src2, $dst|$dst, $src2}",
2158 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2159 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2160 "rol{w}\t{$src2, $dst|$dst, $src2}",
2161 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2162 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2163 "rol{l}\t{$src2, $dst|$dst, $src2}",
2164 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2167 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2169 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2170 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2172 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2173 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2175 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2177 let isTwoAddress = 0 in {
2178 let Uses = [CL] in {
2179 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2180 "rol{b}\t{%cl, $dst|$dst, CL}",
2181 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2182 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2183 "rol{w}\t{%cl, $dst|$dst, CL}",
2184 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2185 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2186 "rol{l}\t{%cl, $dst|$dst, CL}",
2187 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2189 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2190 "rol{b}\t{$src, $dst|$dst, $src}",
2191 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2192 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2193 "rol{w}\t{$src, $dst|$dst, $src}",
2194 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2196 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2197 "rol{l}\t{$src, $dst|$dst, $src}",
2198 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2201 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2203 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2204 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2206 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2208 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2210 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2213 let Uses = [CL] in {
2214 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2215 "ror{b}\t{%cl, $dst|$dst, CL}",
2216 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2217 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2218 "ror{w}\t{%cl, $dst|$dst, CL}",
2219 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2220 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2221 "ror{l}\t{%cl, $dst|$dst, CL}",
2222 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2225 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2226 "ror{b}\t{$src2, $dst|$dst, $src2}",
2227 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2228 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2229 "ror{w}\t{$src2, $dst|$dst, $src2}",
2230 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2231 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2232 "ror{l}\t{$src2, $dst|$dst, $src2}",
2233 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2236 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2238 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2239 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2241 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2242 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2244 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2246 let isTwoAddress = 0 in {
2247 let Uses = [CL] in {
2248 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2249 "ror{b}\t{%cl, $dst|$dst, CL}",
2250 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2251 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2252 "ror{w}\t{%cl, $dst|$dst, CL}",
2253 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2254 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2255 "ror{l}\t{%cl, $dst|$dst, CL}",
2256 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2258 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2259 "ror{b}\t{$src, $dst|$dst, $src}",
2260 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2261 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2262 "ror{w}\t{$src, $dst|$dst, $src}",
2263 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2265 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2266 "ror{l}\t{$src, $dst|$dst, $src}",
2267 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2270 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2272 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2273 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2275 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2277 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2279 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2284 // Double shift instructions (generalizations of rotate)
2285 let Uses = [CL] in {
2286 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2287 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2288 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2289 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2290 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2291 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2292 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2293 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2294 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2296 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2297 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2298 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2302 let isCommutable = 1 in { // These instructions commute to each other.
2303 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2304 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2305 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2306 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2309 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2310 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2311 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2312 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2315 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2316 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2317 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2318 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2321 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2322 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2323 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2324 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2329 let isTwoAddress = 0 in {
2330 let Uses = [CL] in {
2331 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2332 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2333 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2335 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2336 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2337 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2340 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2341 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2342 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2343 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2344 (i8 imm:$src3)), addr:$dst)]>,
2346 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2347 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2348 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2349 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2350 (i8 imm:$src3)), addr:$dst)]>,
2353 let Uses = [CL] in {
2354 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2355 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2356 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2357 addr:$dst)]>, TB, OpSize;
2358 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2359 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2360 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2361 addr:$dst)]>, TB, OpSize;
2363 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2364 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2365 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2366 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2367 (i8 imm:$src3)), addr:$dst)]>,
2369 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2370 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2371 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2372 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2373 (i8 imm:$src3)), addr:$dst)]>,
2376 } // Defs = [EFLAGS]
2380 let Defs = [EFLAGS] in {
2381 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2382 // Register-Register Addition
2383 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2384 (ins GR8 :$src1, GR8 :$src2),
2385 "add{b}\t{$src2, $dst|$dst, $src2}",
2386 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
2387 (implicit EFLAGS)]>;
2389 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2390 // Register-Register Addition
2391 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2392 (ins GR16:$src1, GR16:$src2),
2393 "add{w}\t{$src2, $dst|$dst, $src2}",
2394 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2395 (implicit EFLAGS)]>, OpSize;
2396 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2397 (ins GR32:$src1, GR32:$src2),
2398 "add{l}\t{$src2, $dst|$dst, $src2}",
2399 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2400 (implicit EFLAGS)]>;
2401 } // end isConvertibleToThreeAddress
2402 } // end isCommutable
2404 // Register-Memory Addition
2405 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2406 (ins GR8 :$src1, i8mem :$src2),
2407 "add{b}\t{$src2, $dst|$dst, $src2}",
2408 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2409 (implicit EFLAGS)]>;
2410 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2411 (ins GR16:$src1, i16mem:$src2),
2412 "add{w}\t{$src2, $dst|$dst, $src2}",
2413 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2414 (implicit EFLAGS)]>, OpSize;
2415 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2416 (ins GR32:$src1, i32mem:$src2),
2417 "add{l}\t{$src2, $dst|$dst, $src2}",
2418 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2419 (implicit EFLAGS)]>;
2421 // Register-Integer Addition
2422 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2423 "add{b}\t{$src2, $dst|$dst, $src2}",
2424 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2425 (implicit EFLAGS)]>;
2427 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2428 // Register-Integer Addition
2429 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2430 (ins GR16:$src1, i16imm:$src2),
2431 "add{w}\t{$src2, $dst|$dst, $src2}",
2432 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2433 (implicit EFLAGS)]>, OpSize;
2434 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2435 (ins GR32:$src1, i32imm:$src2),
2436 "add{l}\t{$src2, $dst|$dst, $src2}",
2437 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2438 (implicit EFLAGS)]>;
2439 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2440 (ins GR16:$src1, i16i8imm:$src2),
2441 "add{w}\t{$src2, $dst|$dst, $src2}",
2442 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2443 (implicit EFLAGS)]>, OpSize;
2444 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2445 (ins GR32:$src1, i32i8imm:$src2),
2446 "add{l}\t{$src2, $dst|$dst, $src2}",
2447 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2448 (implicit EFLAGS)]>;
2451 let isTwoAddress = 0 in {
2452 // Memory-Register Addition
2453 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2454 "add{b}\t{$src2, $dst|$dst, $src2}",
2455 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2456 (implicit EFLAGS)]>;
2457 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2458 "add{w}\t{$src2, $dst|$dst, $src2}",
2459 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2460 (implicit EFLAGS)]>, OpSize;
2461 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2462 "add{l}\t{$src2, $dst|$dst, $src2}",
2463 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2464 (implicit EFLAGS)]>;
2465 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2466 "add{b}\t{$src2, $dst|$dst, $src2}",
2467 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2468 (implicit EFLAGS)]>;
2469 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2470 "add{w}\t{$src2, $dst|$dst, $src2}",
2471 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2472 (implicit EFLAGS)]>, OpSize;
2473 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2474 "add{l}\t{$src2, $dst|$dst, $src2}",
2475 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2476 (implicit EFLAGS)]>;
2477 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2478 "add{w}\t{$src2, $dst|$dst, $src2}",
2479 [(store (add (load addr:$dst), i16immSExt8:$src2),
2481 (implicit EFLAGS)]>, OpSize;
2482 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2483 "add{l}\t{$src2, $dst|$dst, $src2}",
2484 [(store (add (load addr:$dst), i32immSExt8:$src2),
2486 (implicit EFLAGS)]>;
2489 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2490 "add{b}\t{$src, %al|%al, $src}", []>;
2491 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2492 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2493 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2494 "add{l}\t{$src, %eax|%eax, $src}", []>;
2497 let Uses = [EFLAGS] in {
2498 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2499 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2500 "adc{b}\t{$src2, $dst|$dst, $src2}",
2501 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2502 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2503 (ins GR16:$src1, GR16:$src2),
2504 "adc{w}\t{$src2, $dst|$dst, $src2}",
2505 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2506 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2507 (ins GR32:$src1, GR32:$src2),
2508 "adc{l}\t{$src2, $dst|$dst, $src2}",
2509 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2511 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2512 (ins GR8:$src1, i8mem:$src2),
2513 "adc{b}\t{$src2, $dst|$dst, $src2}",
2514 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2515 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2516 (ins GR16:$src1, i16mem:$src2),
2517 "adc{w}\t{$src2, $dst|$dst, $src2}",
2518 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2520 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2521 (ins GR32:$src1, i32mem:$src2),
2522 "adc{l}\t{$src2, $dst|$dst, $src2}",
2523 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2524 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2525 "adc{b}\t{$src2, $dst|$dst, $src2}",
2526 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2527 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2528 (ins GR16:$src1, i16imm:$src2),
2529 "adc{w}\t{$src2, $dst|$dst, $src2}",
2530 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2531 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2532 (ins GR16:$src1, i16i8imm:$src2),
2533 "adc{w}\t{$src2, $dst|$dst, $src2}",
2534 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2536 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2537 (ins GR32:$src1, i32imm:$src2),
2538 "adc{l}\t{$src2, $dst|$dst, $src2}",
2539 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2540 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2541 (ins GR32:$src1, i32i8imm:$src2),
2542 "adc{l}\t{$src2, $dst|$dst, $src2}",
2543 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2545 let isTwoAddress = 0 in {
2546 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2547 "adc{b}\t{$src2, $dst|$dst, $src2}",
2548 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2549 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2550 "adc{w}\t{$src2, $dst|$dst, $src2}",
2551 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2553 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2554 "adc{l}\t{$src2, $dst|$dst, $src2}",
2555 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2556 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2557 "adc{b}\t{$src2, $dst|$dst, $src2}",
2558 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2559 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2560 "adc{w}\t{$src2, $dst|$dst, $src2}",
2561 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2563 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2564 "adc{w}\t{$src2, $dst|$dst, $src2}",
2565 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2567 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2568 "adc{l}\t{$src2, $dst|$dst, $src2}",
2569 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2570 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2571 "adc{l}\t{$src2, $dst|$dst, $src2}",
2572 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2574 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2575 "adc{b}\t{$src, %al|%al, $src}", []>;
2576 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2577 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2578 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2579 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2581 } // Uses = [EFLAGS]
2583 // Register-Register Subtraction
2584 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2585 "sub{b}\t{$src2, $dst|$dst, $src2}",
2586 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2587 (implicit EFLAGS)]>;
2588 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2589 "sub{w}\t{$src2, $dst|$dst, $src2}",
2590 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2591 (implicit EFLAGS)]>, OpSize;
2592 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2593 "sub{l}\t{$src2, $dst|$dst, $src2}",
2594 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2595 (implicit EFLAGS)]>;
2597 // Register-Memory Subtraction
2598 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2599 (ins GR8 :$src1, i8mem :$src2),
2600 "sub{b}\t{$src2, $dst|$dst, $src2}",
2601 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2602 (implicit EFLAGS)]>;
2603 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2604 (ins GR16:$src1, i16mem:$src2),
2605 "sub{w}\t{$src2, $dst|$dst, $src2}",
2606 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2607 (implicit EFLAGS)]>, OpSize;
2608 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2609 (ins GR32:$src1, i32mem:$src2),
2610 "sub{l}\t{$src2, $dst|$dst, $src2}",
2611 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2612 (implicit EFLAGS)]>;
2614 // Register-Integer Subtraction
2615 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2616 (ins GR8:$src1, i8imm:$src2),
2617 "sub{b}\t{$src2, $dst|$dst, $src2}",
2618 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2619 (implicit EFLAGS)]>;
2620 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2621 (ins GR16:$src1, i16imm:$src2),
2622 "sub{w}\t{$src2, $dst|$dst, $src2}",
2623 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2624 (implicit EFLAGS)]>, OpSize;
2625 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2626 (ins GR32:$src1, i32imm:$src2),
2627 "sub{l}\t{$src2, $dst|$dst, $src2}",
2628 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2629 (implicit EFLAGS)]>;
2630 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2631 (ins GR16:$src1, i16i8imm:$src2),
2632 "sub{w}\t{$src2, $dst|$dst, $src2}",
2633 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2634 (implicit EFLAGS)]>, OpSize;
2635 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2636 (ins GR32:$src1, i32i8imm:$src2),
2637 "sub{l}\t{$src2, $dst|$dst, $src2}",
2638 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2639 (implicit EFLAGS)]>;
2641 let isTwoAddress = 0 in {
2642 // Memory-Register Subtraction
2643 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2644 "sub{b}\t{$src2, $dst|$dst, $src2}",
2645 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2646 (implicit EFLAGS)]>;
2647 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2648 "sub{w}\t{$src2, $dst|$dst, $src2}",
2649 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2650 (implicit EFLAGS)]>, OpSize;
2651 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2652 "sub{l}\t{$src2, $dst|$dst, $src2}",
2653 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2654 (implicit EFLAGS)]>;
2656 // Memory-Integer Subtraction
2657 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2658 "sub{b}\t{$src2, $dst|$dst, $src2}",
2659 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2660 (implicit EFLAGS)]>;
2661 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2662 "sub{w}\t{$src2, $dst|$dst, $src2}",
2663 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2664 (implicit EFLAGS)]>, OpSize;
2665 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2666 "sub{l}\t{$src2, $dst|$dst, $src2}",
2667 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2668 (implicit EFLAGS)]>;
2669 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2670 "sub{w}\t{$src2, $dst|$dst, $src2}",
2671 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2673 (implicit EFLAGS)]>, OpSize;
2674 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2675 "sub{l}\t{$src2, $dst|$dst, $src2}",
2676 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2678 (implicit EFLAGS)]>;
2680 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
2681 "sub{b}\t{$src, %al|%al, $src}", []>;
2682 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
2683 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2684 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
2685 "sub{l}\t{$src, %eax|%eax, $src}", []>;
2688 let Uses = [EFLAGS] in {
2689 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
2690 (ins GR8:$src1, GR8:$src2),
2691 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2692 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
2693 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
2694 (ins GR16:$src1, GR16:$src2),
2695 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2696 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
2697 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
2698 (ins GR32:$src1, GR32:$src2),
2699 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2700 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2702 let isTwoAddress = 0 in {
2703 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2704 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2705 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
2706 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2707 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2708 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
2710 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2711 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2712 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2713 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2714 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2715 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2716 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
2717 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2718 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2720 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2721 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2722 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2724 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2725 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2726 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2727 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2728 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2729 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2731 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
2732 "sbb{b}\t{$src, %al|%al, $src}", []>;
2733 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
2734 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2735 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
2736 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
2738 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
2739 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2740 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
2741 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
2742 (ins GR16:$src1, i16mem:$src2),
2743 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2744 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
2746 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
2747 (ins GR32:$src1, i32mem:$src2),
2748 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2749 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2750 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2751 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2752 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
2753 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
2754 (ins GR16:$src1, i16imm:$src2),
2755 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2756 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
2757 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
2758 (ins GR16:$src1, i16i8imm:$src2),
2759 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2760 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
2762 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
2763 (ins GR32:$src1, i32imm:$src2),
2764 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2765 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2766 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
2767 (ins GR32:$src1, i32i8imm:$src2),
2768 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2769 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2770 } // Uses = [EFLAGS]
2771 } // Defs = [EFLAGS]
2773 let Defs = [EFLAGS] in {
2774 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2775 // Register-Register Signed Integer Multiply
2776 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2777 "imul{w}\t{$src2, $dst|$dst, $src2}",
2778 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
2779 (implicit EFLAGS)]>, TB, OpSize;
2780 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2781 "imul{l}\t{$src2, $dst|$dst, $src2}",
2782 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
2783 (implicit EFLAGS)]>, TB;
2786 // Register-Memory Signed Integer Multiply
2787 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
2788 (ins GR16:$src1, i16mem:$src2),
2789 "imul{w}\t{$src2, $dst|$dst, $src2}",
2790 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
2791 (implicit EFLAGS)]>, TB, OpSize;
2792 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2793 "imul{l}\t{$src2, $dst|$dst, $src2}",
2794 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
2795 (implicit EFLAGS)]>, TB;
2796 } // Defs = [EFLAGS]
2797 } // end Two Address instructions
2799 // Suprisingly enough, these are not two address instructions!
2800 let Defs = [EFLAGS] in {
2801 // Register-Integer Signed Integer Multiply
2802 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2803 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2804 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2805 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
2806 (implicit EFLAGS)]>, OpSize;
2807 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2808 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2809 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2810 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
2811 (implicit EFLAGS)]>;
2812 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2813 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2814 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2815 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
2816 (implicit EFLAGS)]>, OpSize;
2817 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2818 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2819 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2820 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
2821 (implicit EFLAGS)]>;
2823 // Memory-Integer Signed Integer Multiply
2824 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2825 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2826 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2827 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
2828 (implicit EFLAGS)]>, OpSize;
2829 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2830 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2831 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2832 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
2833 (implicit EFLAGS)]>;
2834 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2835 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2836 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2837 [(set GR16:$dst, (mul (load addr:$src1),
2838 i16immSExt8:$src2)),
2839 (implicit EFLAGS)]>, OpSize;
2840 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2841 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2842 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2843 [(set GR32:$dst, (mul (load addr:$src1),
2844 i32immSExt8:$src2)),
2845 (implicit EFLAGS)]>;
2846 } // Defs = [EFLAGS]
2848 //===----------------------------------------------------------------------===//
2849 // Test instructions are just like AND, except they don't generate a result.
2851 let Defs = [EFLAGS] in {
2852 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2853 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2854 "test{b}\t{$src2, $src1|$src1, $src2}",
2855 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
2856 (implicit EFLAGS)]>;
2857 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2858 "test{w}\t{$src2, $src1|$src1, $src2}",
2859 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
2860 (implicit EFLAGS)]>,
2862 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2863 "test{l}\t{$src2, $src1|$src1, $src2}",
2864 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
2865 (implicit EFLAGS)]>;
2868 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
2869 "test{b}\t{$src, %al|%al, $src}", []>;
2870 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
2871 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2872 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
2873 "test{l}\t{$src, %eax|%eax, $src}", []>;
2875 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2876 "test{b}\t{$src2, $src1|$src1, $src2}",
2877 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2878 (implicit EFLAGS)]>;
2879 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2880 "test{w}\t{$src2, $src1|$src1, $src2}",
2881 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2882 (implicit EFLAGS)]>, OpSize;
2883 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2884 "test{l}\t{$src2, $src1|$src1, $src2}",
2885 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2886 (implicit EFLAGS)]>;
2888 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2889 (outs), (ins GR8:$src1, i8imm:$src2),
2890 "test{b}\t{$src2, $src1|$src1, $src2}",
2891 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
2892 (implicit EFLAGS)]>;
2893 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2894 (outs), (ins GR16:$src1, i16imm:$src2),
2895 "test{w}\t{$src2, $src1|$src1, $src2}",
2896 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
2897 (implicit EFLAGS)]>, OpSize;
2898 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2899 (outs), (ins GR32:$src1, i32imm:$src2),
2900 "test{l}\t{$src2, $src1|$src1, $src2}",
2901 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
2902 (implicit EFLAGS)]>;
2904 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2905 (outs), (ins i8mem:$src1, i8imm:$src2),
2906 "test{b}\t{$src2, $src1|$src1, $src2}",
2907 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2908 (implicit EFLAGS)]>;
2909 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2910 (outs), (ins i16mem:$src1, i16imm:$src2),
2911 "test{w}\t{$src2, $src1|$src1, $src2}",
2912 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2913 (implicit EFLAGS)]>, OpSize;
2914 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2915 (outs), (ins i32mem:$src1, i32imm:$src2),
2916 "test{l}\t{$src2, $src1|$src1, $src2}",
2917 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2918 (implicit EFLAGS)]>;
2919 } // Defs = [EFLAGS]
2922 // Condition code ops, incl. set if equal/not equal/...
2923 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2924 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2925 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2926 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2928 let Uses = [EFLAGS] in {
2929 def SETEr : I<0x94, MRM0r,
2930 (outs GR8 :$dst), (ins),
2932 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2934 def SETEm : I<0x94, MRM0m,
2935 (outs), (ins i8mem:$dst),
2937 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2940 def SETNEr : I<0x95, MRM0r,
2941 (outs GR8 :$dst), (ins),
2943 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2945 def SETNEm : I<0x95, MRM0m,
2946 (outs), (ins i8mem:$dst),
2948 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2951 def SETLr : I<0x9C, MRM0r,
2952 (outs GR8 :$dst), (ins),
2954 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2955 TB; // GR8 = < signed
2956 def SETLm : I<0x9C, MRM0m,
2957 (outs), (ins i8mem:$dst),
2959 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2960 TB; // [mem8] = < signed
2962 def SETGEr : I<0x9D, MRM0r,
2963 (outs GR8 :$dst), (ins),
2965 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2966 TB; // GR8 = >= signed
2967 def SETGEm : I<0x9D, MRM0m,
2968 (outs), (ins i8mem:$dst),
2970 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2971 TB; // [mem8] = >= signed
2973 def SETLEr : I<0x9E, MRM0r,
2974 (outs GR8 :$dst), (ins),
2976 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2977 TB; // GR8 = <= signed
2978 def SETLEm : I<0x9E, MRM0m,
2979 (outs), (ins i8mem:$dst),
2981 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2982 TB; // [mem8] = <= signed
2984 def SETGr : I<0x9F, MRM0r,
2985 (outs GR8 :$dst), (ins),
2987 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2988 TB; // GR8 = > signed
2989 def SETGm : I<0x9F, MRM0m,
2990 (outs), (ins i8mem:$dst),
2992 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2993 TB; // [mem8] = > signed
2995 def SETBr : I<0x92, MRM0r,
2996 (outs GR8 :$dst), (ins),
2998 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2999 TB; // GR8 = < unsign
3000 def SETBm : I<0x92, MRM0m,
3001 (outs), (ins i8mem:$dst),
3003 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3004 TB; // [mem8] = < unsign
3006 def SETAEr : I<0x93, MRM0r,
3007 (outs GR8 :$dst), (ins),
3009 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3010 TB; // GR8 = >= unsign
3011 def SETAEm : I<0x93, MRM0m,
3012 (outs), (ins i8mem:$dst),
3014 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3015 TB; // [mem8] = >= unsign
3017 def SETBEr : I<0x96, MRM0r,
3018 (outs GR8 :$dst), (ins),
3020 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3021 TB; // GR8 = <= unsign
3022 def SETBEm : I<0x96, MRM0m,
3023 (outs), (ins i8mem:$dst),
3025 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3026 TB; // [mem8] = <= unsign
3028 def SETAr : I<0x97, MRM0r,
3029 (outs GR8 :$dst), (ins),
3031 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3032 TB; // GR8 = > signed
3033 def SETAm : I<0x97, MRM0m,
3034 (outs), (ins i8mem:$dst),
3036 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3037 TB; // [mem8] = > signed
3039 def SETSr : I<0x98, MRM0r,
3040 (outs GR8 :$dst), (ins),
3042 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3043 TB; // GR8 = <sign bit>
3044 def SETSm : I<0x98, MRM0m,
3045 (outs), (ins i8mem:$dst),
3047 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3048 TB; // [mem8] = <sign bit>
3049 def SETNSr : I<0x99, MRM0r,
3050 (outs GR8 :$dst), (ins),
3052 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3053 TB; // GR8 = !<sign bit>
3054 def SETNSm : I<0x99, MRM0m,
3055 (outs), (ins i8mem:$dst),
3057 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3058 TB; // [mem8] = !<sign bit>
3060 def SETPr : I<0x9A, MRM0r,
3061 (outs GR8 :$dst), (ins),
3063 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3065 def SETPm : I<0x9A, MRM0m,
3066 (outs), (ins i8mem:$dst),
3068 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3069 TB; // [mem8] = parity
3070 def SETNPr : I<0x9B, MRM0r,
3071 (outs GR8 :$dst), (ins),
3073 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3074 TB; // GR8 = not parity
3075 def SETNPm : I<0x9B, MRM0m,
3076 (outs), (ins i8mem:$dst),
3078 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3079 TB; // [mem8] = not parity
3081 def SETOr : I<0x90, MRM0r,
3082 (outs GR8 :$dst), (ins),
3084 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3085 TB; // GR8 = overflow
3086 def SETOm : I<0x90, MRM0m,
3087 (outs), (ins i8mem:$dst),
3089 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3090 TB; // [mem8] = overflow
3091 def SETNOr : I<0x91, MRM0r,
3092 (outs GR8 :$dst), (ins),
3094 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3095 TB; // GR8 = not overflow
3096 def SETNOm : I<0x91, MRM0m,
3097 (outs), (ins i8mem:$dst),
3099 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3100 TB; // [mem8] = not overflow
3101 } // Uses = [EFLAGS]
3104 // Integer comparisons
3105 let Defs = [EFLAGS] in {
3106 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3107 "cmp{b}\t{$src, %al|%al, $src}", []>;
3108 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3109 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3110 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3111 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3113 def CMP8rr : I<0x38, MRMDestReg,
3114 (outs), (ins GR8 :$src1, GR8 :$src2),
3115 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3116 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
3117 def CMP16rr : I<0x39, MRMDestReg,
3118 (outs), (ins GR16:$src1, GR16:$src2),
3119 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3120 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
3121 def CMP32rr : I<0x39, MRMDestReg,
3122 (outs), (ins GR32:$src1, GR32:$src2),
3123 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3124 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
3125 def CMP8mr : I<0x38, MRMDestMem,
3126 (outs), (ins i8mem :$src1, GR8 :$src2),
3127 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3128 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
3129 (implicit EFLAGS)]>;
3130 def CMP16mr : I<0x39, MRMDestMem,
3131 (outs), (ins i16mem:$src1, GR16:$src2),
3132 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3133 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
3134 (implicit EFLAGS)]>, OpSize;
3135 def CMP32mr : I<0x39, MRMDestMem,
3136 (outs), (ins i32mem:$src1, GR32:$src2),
3137 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3138 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
3139 (implicit EFLAGS)]>;
3140 def CMP8rm : I<0x3A, MRMSrcMem,
3141 (outs), (ins GR8 :$src1, i8mem :$src2),
3142 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3143 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
3144 (implicit EFLAGS)]>;
3145 def CMP16rm : I<0x3B, MRMSrcMem,
3146 (outs), (ins GR16:$src1, i16mem:$src2),
3147 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3148 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
3149 (implicit EFLAGS)]>, OpSize;
3150 def CMP32rm : I<0x3B, MRMSrcMem,
3151 (outs), (ins GR32:$src1, i32mem:$src2),
3152 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3153 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
3154 (implicit EFLAGS)]>;
3155 def CMP8ri : Ii8<0x80, MRM7r,
3156 (outs), (ins GR8:$src1, i8imm:$src2),
3157 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3158 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
3159 def CMP16ri : Ii16<0x81, MRM7r,
3160 (outs), (ins GR16:$src1, i16imm:$src2),
3161 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3162 [(X86cmp GR16:$src1, imm:$src2),
3163 (implicit EFLAGS)]>, OpSize;
3164 def CMP32ri : Ii32<0x81, MRM7r,
3165 (outs), (ins GR32:$src1, i32imm:$src2),
3166 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3167 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
3168 def CMP8mi : Ii8 <0x80, MRM7m,
3169 (outs), (ins i8mem :$src1, i8imm :$src2),
3170 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3171 [(X86cmp (loadi8 addr:$src1), imm:$src2),
3172 (implicit EFLAGS)]>;
3173 def CMP16mi : Ii16<0x81, MRM7m,
3174 (outs), (ins i16mem:$src1, i16imm:$src2),
3175 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3176 [(X86cmp (loadi16 addr:$src1), imm:$src2),
3177 (implicit EFLAGS)]>, OpSize;
3178 def CMP32mi : Ii32<0x81, MRM7m,
3179 (outs), (ins i32mem:$src1, i32imm:$src2),
3180 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3181 [(X86cmp (loadi32 addr:$src1), imm:$src2),
3182 (implicit EFLAGS)]>;
3183 def CMP16ri8 : Ii8<0x83, MRM7r,
3184 (outs), (ins GR16:$src1, i16i8imm:$src2),
3185 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3186 [(X86cmp GR16:$src1, i16immSExt8:$src2),
3187 (implicit EFLAGS)]>, OpSize;
3188 def CMP16mi8 : Ii8<0x83, MRM7m,
3189 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3190 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3191 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
3192 (implicit EFLAGS)]>, OpSize;
3193 def CMP32mi8 : Ii8<0x83, MRM7m,
3194 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3195 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3196 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
3197 (implicit EFLAGS)]>;
3198 def CMP32ri8 : Ii8<0x83, MRM7r,
3199 (outs), (ins GR32:$src1, i32i8imm:$src2),
3200 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3201 [(X86cmp GR32:$src1, i32immSExt8:$src2),
3202 (implicit EFLAGS)]>;
3203 } // Defs = [EFLAGS]
3206 // TODO: BTC, BTR, and BTS
3207 let Defs = [EFLAGS] in {
3208 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3209 "bt{w}\t{$src2, $src1|$src1, $src2}",
3210 [(X86bt GR16:$src1, GR16:$src2),
3211 (implicit EFLAGS)]>, OpSize, TB;
3212 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3213 "bt{l}\t{$src2, $src1|$src1, $src2}",
3214 [(X86bt GR32:$src1, GR32:$src2),
3215 (implicit EFLAGS)]>, TB;
3217 // Unlike with the register+register form, the memory+register form of the
3218 // bt instruction does not ignore the high bits of the index. From ISel's
3219 // perspective, this is pretty bizarre. Disable these instructions for now.
3220 //def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3221 // "bt{w}\t{$src2, $src1|$src1, $src2}",
3222 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3223 // (implicit EFLAGS)]>, OpSize, TB, Requires<[FastBTMem]>;
3224 //def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3225 // "bt{l}\t{$src2, $src1|$src1, $src2}",
3226 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3227 // (implicit EFLAGS)]>, TB, Requires<[FastBTMem]>;
3229 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3230 "bt{w}\t{$src2, $src1|$src1, $src2}",
3231 [(X86bt GR16:$src1, i16immSExt8:$src2),
3232 (implicit EFLAGS)]>, OpSize, TB;
3233 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3234 "bt{l}\t{$src2, $src1|$src1, $src2}",
3235 [(X86bt GR32:$src1, i32immSExt8:$src2),
3236 (implicit EFLAGS)]>, TB;
3237 // Note that these instructions don't need FastBTMem because that
3238 // only applies when the other operand is in a register. When it's
3239 // an immediate, bt is still fast.
3240 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3241 "bt{w}\t{$src2, $src1|$src1, $src2}",
3242 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
3243 (implicit EFLAGS)]>, OpSize, TB;
3244 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3245 "bt{l}\t{$src2, $src1|$src1, $src2}",
3246 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
3247 (implicit EFLAGS)]>, TB;
3248 } // Defs = [EFLAGS]
3250 // Sign/Zero extenders
3251 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3252 // of the register here. This has a smaller encoding and avoids a
3253 // partial-register update.
3254 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3255 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3256 [(set GR16:$dst, (sext GR8:$src))]>, TB;
3257 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3258 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3259 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3260 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3261 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3262 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3263 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3264 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3265 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3266 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3267 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3268 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3269 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3270 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3271 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3273 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3274 // of the register here. This has a smaller encoding and avoids a
3275 // partial-register update.
3276 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3277 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3278 [(set GR16:$dst, (zext GR8:$src))]>, TB;
3279 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3280 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3281 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3282 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3283 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3284 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3285 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3286 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3287 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3288 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3289 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3290 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3291 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3292 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3293 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3295 // These are the same as the regular regular MOVZX32rr8 and MOVZX32rm8
3296 // except that they use GR32_NOREX for the output operand register class
3297 // instead of GR32. This allows them to operate on h registers on x86-64.
3298 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3299 (outs GR32_NOREX:$dst), (ins GR8:$src),
3300 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3303 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3304 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3305 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3308 let neverHasSideEffects = 1 in {
3309 let Defs = [AX], Uses = [AL] in
3310 def CBW : I<0x98, RawFrm, (outs), (ins),
3311 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3312 let Defs = [EAX], Uses = [AX] in
3313 def CWDE : I<0x98, RawFrm, (outs), (ins),
3314 "{cwtl|cwde}", []>; // EAX = signext(AX)
3316 let Defs = [AX,DX], Uses = [AX] in
3317 def CWD : I<0x99, RawFrm, (outs), (ins),
3318 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3319 let Defs = [EAX,EDX], Uses = [EAX] in
3320 def CDQ : I<0x99, RawFrm, (outs), (ins),
3321 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3324 //===----------------------------------------------------------------------===//
3325 // Alias Instructions
3326 //===----------------------------------------------------------------------===//
3328 // Alias instructions that map movr0 to xor.
3329 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3330 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3331 isCodeGenOnly = 1 in {
3332 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
3333 "xor{b}\t$dst, $dst",
3334 [(set GR8:$dst, 0)]>;
3335 // Use xorl instead of xorw since we don't care about the high 16 bits,
3336 // it's smaller, and it avoids a partial-register update.
3337 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3338 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
3339 [(set GR16:$dst, 0)]>;
3340 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
3341 "xor{l}\t$dst, $dst",
3342 [(set GR32:$dst, 0)]>;
3345 //===----------------------------------------------------------------------===//
3346 // Thread Local Storage Instructions
3349 // All calls clobber the non-callee saved registers. ESP is marked as
3350 // a use to prevent stack-pointer assignments that appear immediately
3351 // before calls from potentially appearing dead.
3352 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3353 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3354 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3355 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3357 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3358 "leal\t$sym, %eax; "
3359 "call\t___tls_get_addr@PLT",
3360 [(X86tlsaddr tls32addr:$sym)]>,
3361 Requires<[In32BitMode]>;
3363 let AddedComplexity = 5, isCodeGenOnly = 1 in
3364 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3365 "movl\t%gs:$src, $dst",
3366 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3368 let AddedComplexity = 5, isCodeGenOnly = 1 in
3369 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3370 "movl\t%fs:$src, $dst",
3371 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3373 //===----------------------------------------------------------------------===//
3374 // DWARF Pseudo Instructions
3377 def DWARF_LOC : I<0, Pseudo, (outs),
3378 (ins i32imm:$line, i32imm:$col, i32imm:$file),
3379 ".loc\t$file $line $col",
3380 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
3383 //===----------------------------------------------------------------------===//
3384 // EH Pseudo Instructions
3386 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3387 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3388 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3389 "ret\t#eh_return, addr: $addr",
3390 [(X86ehret GR32:$addr)]>;
3394 //===----------------------------------------------------------------------===//
3398 // Atomic swap. These are just normal xchg instructions. But since a memory
3399 // operand is referenced, the atomicity is ensured.
3400 let Constraints = "$val = $dst" in {
3401 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3402 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3403 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3404 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3405 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3406 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3408 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3409 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3410 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3413 // Atomic compare and swap.
3414 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3415 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3417 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3418 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3420 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3421 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
3424 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3427 let Defs = [AX, EFLAGS], Uses = [AX] in {
3428 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3430 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3431 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3433 let Defs = [AL, EFLAGS], Uses = [AL] in {
3434 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3436 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3437 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3440 // Atomic exchange and add
3441 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3442 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3444 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3445 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3447 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3449 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3450 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3452 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3454 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3455 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3459 // Optimized codegen when the non-memory output is not used.
3460 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3461 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3463 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3464 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3466 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3467 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3469 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3470 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3472 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3473 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3475 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3476 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3478 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3479 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3481 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3482 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3484 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3486 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3488 "inc{b}\t$dst", []>, LOCK;
3489 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3491 "inc{w}\t$dst", []>, OpSize, LOCK;
3492 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3494 "inc{l}\t$dst", []>, LOCK;
3496 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3498 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3499 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3501 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3502 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3504 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3505 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3507 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3508 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3510 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3511 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3513 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3514 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3516 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3517 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3519 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3521 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3523 "dec{b}\t$dst", []>, LOCK;
3524 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3526 "dec{w}\t$dst", []>, OpSize, LOCK;
3527 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3529 "dec{l}\t$dst", []>, LOCK;
3531 // Atomic exchange, and, or, xor
3532 let Constraints = "$val = $dst", Defs = [EFLAGS],
3533 usesCustomDAGSchedInserter = 1 in {
3534 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3535 "#ATOMAND32 PSEUDO!",
3536 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3537 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3538 "#ATOMOR32 PSEUDO!",
3539 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
3540 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3541 "#ATOMXOR32 PSEUDO!",
3542 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
3543 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3544 "#ATOMNAND32 PSEUDO!",
3545 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
3546 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3547 "#ATOMMIN32 PSEUDO!",
3548 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
3549 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3550 "#ATOMMAX32 PSEUDO!",
3551 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
3552 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3553 "#ATOMUMIN32 PSEUDO!",
3554 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
3555 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3556 "#ATOMUMAX32 PSEUDO!",
3557 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
3559 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3560 "#ATOMAND16 PSEUDO!",
3561 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
3562 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3563 "#ATOMOR16 PSEUDO!",
3564 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
3565 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3566 "#ATOMXOR16 PSEUDO!",
3567 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
3568 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3569 "#ATOMNAND16 PSEUDO!",
3570 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
3571 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3572 "#ATOMMIN16 PSEUDO!",
3573 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
3574 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3575 "#ATOMMAX16 PSEUDO!",
3576 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
3577 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3578 "#ATOMUMIN16 PSEUDO!",
3579 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
3580 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3581 "#ATOMUMAX16 PSEUDO!",
3582 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
3584 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3585 "#ATOMAND8 PSEUDO!",
3586 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
3587 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3589 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
3590 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3591 "#ATOMXOR8 PSEUDO!",
3592 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
3593 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3594 "#ATOMNAND8 PSEUDO!",
3595 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
3598 let Constraints = "$val1 = $dst1, $val2 = $dst2",
3599 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
3600 Uses = [EAX, EBX, ECX, EDX],
3601 mayLoad = 1, mayStore = 1,
3602 usesCustomDAGSchedInserter = 1 in {
3603 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3604 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3605 "#ATOMAND6432 PSEUDO!", []>;
3606 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3607 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3608 "#ATOMOR6432 PSEUDO!", []>;
3609 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3610 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3611 "#ATOMXOR6432 PSEUDO!", []>;
3612 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3613 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3614 "#ATOMNAND6432 PSEUDO!", []>;
3615 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3616 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3617 "#ATOMADD6432 PSEUDO!", []>;
3618 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3619 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3620 "#ATOMSUB6432 PSEUDO!", []>;
3621 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3622 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3623 "#ATOMSWAP6432 PSEUDO!", []>;
3626 //===----------------------------------------------------------------------===//
3627 // Non-Instruction Patterns
3628 //===----------------------------------------------------------------------===//
3630 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
3631 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
3632 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
3633 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
3634 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
3635 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
3637 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
3638 (ADD32ri GR32:$src1, tconstpool:$src2)>;
3639 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
3640 (ADD32ri GR32:$src1, tjumptable:$src2)>;
3641 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
3642 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
3643 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
3644 (ADD32ri GR32:$src1, texternalsym:$src2)>;
3646 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
3647 (MOV32mi addr:$dst, tglobaladdr:$src)>;
3648 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
3649 (MOV32mi addr:$dst, texternalsym:$src)>;
3653 def : Pat<(X86tcret GR32:$dst, imm:$off),
3654 (TCRETURNri GR32:$dst, imm:$off)>;
3656 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
3657 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3659 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
3660 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3662 // Normal calls, with various flavors of addresses.
3663 def : Pat<(X86call (i32 tglobaladdr:$dst)),
3664 (CALLpcrel32 tglobaladdr:$dst)>;
3665 def : Pat<(X86call (i32 texternalsym:$dst)),
3666 (CALLpcrel32 texternalsym:$dst)>;
3667 def : Pat<(X86call (i32 imm:$dst)),
3668 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
3670 // X86 specific add which produces a flag.
3671 def : Pat<(addc GR32:$src1, GR32:$src2),
3672 (ADD32rr GR32:$src1, GR32:$src2)>;
3673 def : Pat<(addc GR32:$src1, (load addr:$src2)),
3674 (ADD32rm GR32:$src1, addr:$src2)>;
3675 def : Pat<(addc GR32:$src1, imm:$src2),
3676 (ADD32ri GR32:$src1, imm:$src2)>;
3677 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
3678 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3680 def : Pat<(subc GR32:$src1, GR32:$src2),
3681 (SUB32rr GR32:$src1, GR32:$src2)>;
3682 def : Pat<(subc GR32:$src1, (load addr:$src2)),
3683 (SUB32rm GR32:$src1, addr:$src2)>;
3684 def : Pat<(subc GR32:$src1, imm:$src2),
3685 (SUB32ri GR32:$src1, imm:$src2)>;
3686 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
3687 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3691 // TEST R,R is smaller than CMP R,0
3692 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
3693 (TEST8rr GR8:$src1, GR8:$src1)>;
3694 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
3695 (TEST16rr GR16:$src1, GR16:$src1)>;
3696 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
3697 (TEST32rr GR32:$src1, GR32:$src1)>;
3699 // Conditional moves with folded loads with operands swapped and conditions
3701 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
3702 (CMOVAE16rm GR16:$src2, addr:$src1)>;
3703 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
3704 (CMOVAE32rm GR32:$src2, addr:$src1)>;
3705 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
3706 (CMOVB16rm GR16:$src2, addr:$src1)>;
3707 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
3708 (CMOVB32rm GR32:$src2, addr:$src1)>;
3709 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
3710 (CMOVNE16rm GR16:$src2, addr:$src1)>;
3711 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
3712 (CMOVNE32rm GR32:$src2, addr:$src1)>;
3713 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
3714 (CMOVE16rm GR16:$src2, addr:$src1)>;
3715 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
3716 (CMOVE32rm GR32:$src2, addr:$src1)>;
3717 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
3718 (CMOVA16rm GR16:$src2, addr:$src1)>;
3719 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
3720 (CMOVA32rm GR32:$src2, addr:$src1)>;
3721 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
3722 (CMOVBE16rm GR16:$src2, addr:$src1)>;
3723 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
3724 (CMOVBE32rm GR32:$src2, addr:$src1)>;
3725 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
3726 (CMOVGE16rm GR16:$src2, addr:$src1)>;
3727 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
3728 (CMOVGE32rm GR32:$src2, addr:$src1)>;
3729 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
3730 (CMOVL16rm GR16:$src2, addr:$src1)>;
3731 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
3732 (CMOVL32rm GR32:$src2, addr:$src1)>;
3733 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
3734 (CMOVG16rm GR16:$src2, addr:$src1)>;
3735 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
3736 (CMOVG32rm GR32:$src2, addr:$src1)>;
3737 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
3738 (CMOVLE16rm GR16:$src2, addr:$src1)>;
3739 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
3740 (CMOVLE32rm GR32:$src2, addr:$src1)>;
3741 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
3742 (CMOVNP16rm GR16:$src2, addr:$src1)>;
3743 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
3744 (CMOVNP32rm GR32:$src2, addr:$src1)>;
3745 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
3746 (CMOVP16rm GR16:$src2, addr:$src1)>;
3747 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
3748 (CMOVP32rm GR32:$src2, addr:$src1)>;
3749 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
3750 (CMOVNS16rm GR16:$src2, addr:$src1)>;
3751 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
3752 (CMOVNS32rm GR32:$src2, addr:$src1)>;
3753 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
3754 (CMOVS16rm GR16:$src2, addr:$src1)>;
3755 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
3756 (CMOVS32rm GR32:$src2, addr:$src1)>;
3757 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
3758 (CMOVNO16rm GR16:$src2, addr:$src1)>;
3759 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
3760 (CMOVNO32rm GR32:$src2, addr:$src1)>;
3761 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
3762 (CMOVO16rm GR16:$src2, addr:$src1)>;
3763 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
3764 (CMOVO32rm GR32:$src2, addr:$src1)>;
3766 // zextload bool -> zextload byte
3767 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3768 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3769 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3771 // extload bool -> extload byte
3772 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3773 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3774 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3775 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
3776 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
3777 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
3779 // anyext. Define these to do an explicit zero-extend to
3780 // avoid partial-register updates.
3781 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
3782 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
3783 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
3785 // (and (i32 load), 255) -> (zextload i8)
3786 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
3787 (MOVZX32rm8 addr:$src)>;
3788 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
3789 (MOVZX32rm16 addr:$src)>;
3791 //===----------------------------------------------------------------------===//
3793 //===----------------------------------------------------------------------===//
3795 // Odd encoding trick: -128 fits into an 8-bit immediate field while
3796 // +128 doesn't, so in this special case use a sub instead of an add.
3797 def : Pat<(add GR16:$src1, 128),
3798 (SUB16ri8 GR16:$src1, -128)>;
3799 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
3800 (SUB16mi8 addr:$dst, -128)>;
3801 def : Pat<(add GR32:$src1, 128),
3802 (SUB32ri8 GR32:$src1, -128)>;
3803 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
3804 (SUB32mi8 addr:$dst, -128)>;
3806 // r & (2^16-1) ==> movz
3807 def : Pat<(and GR32:$src1, 0xffff),
3808 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
3809 // r & (2^8-1) ==> movz
3810 def : Pat<(and GR32:$src1, 0xff),
3811 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src1, GR32_ABCD),
3813 Requires<[In32BitMode]>;
3814 // r & (2^8-1) ==> movz
3815 def : Pat<(and GR16:$src1, 0xff),
3816 (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD),
3818 Requires<[In32BitMode]>;
3820 // sext_inreg patterns
3821 def : Pat<(sext_inreg GR32:$src, i16),
3822 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
3823 def : Pat<(sext_inreg GR32:$src, i8),
3824 (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3826 Requires<[In32BitMode]>;
3827 def : Pat<(sext_inreg GR16:$src, i8),
3828 (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3830 Requires<[In32BitMode]>;
3833 def : Pat<(i16 (trunc GR32:$src)),
3834 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
3835 def : Pat<(i8 (trunc GR32:$src)),
3836 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3838 Requires<[In32BitMode]>;
3839 def : Pat<(i8 (trunc GR16:$src)),
3840 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3842 Requires<[In32BitMode]>;
3844 // h-register tricks
3845 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
3846 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3847 x86_subreg_8bit_hi)>,
3848 Requires<[In32BitMode]>;
3849 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
3850 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3851 x86_subreg_8bit_hi)>,
3852 Requires<[In32BitMode]>;
3853 def : Pat<(srl_su GR16:$src, (i8 8)),
3856 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3857 x86_subreg_8bit_hi)),
3859 Requires<[In32BitMode]>;
3860 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
3861 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3862 x86_subreg_8bit_hi))>,
3863 Requires<[In32BitMode]>;
3864 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
3865 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3866 x86_subreg_8bit_hi))>,
3867 Requires<[In32BitMode]>;
3868 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
3869 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3870 x86_subreg_8bit_hi))>,
3871 Requires<[In32BitMode]>;
3873 // (shl x, 1) ==> (add x, x)
3874 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
3875 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
3876 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
3878 // (shl x (and y, 31)) ==> (shl x, y)
3879 def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
3880 (SHL8rCL GR8:$src1)>;
3881 def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
3882 (SHL16rCL GR16:$src1)>;
3883 def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
3884 (SHL32rCL GR32:$src1)>;
3885 def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3886 (SHL8mCL addr:$dst)>;
3887 def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3888 (SHL16mCL addr:$dst)>;
3889 def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3890 (SHL32mCL addr:$dst)>;
3892 def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
3893 (SHR8rCL GR8:$src1)>;
3894 def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
3895 (SHR16rCL GR16:$src1)>;
3896 def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
3897 (SHR32rCL GR32:$src1)>;
3898 def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3899 (SHR8mCL addr:$dst)>;
3900 def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3901 (SHR16mCL addr:$dst)>;
3902 def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3903 (SHR32mCL addr:$dst)>;
3905 def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
3906 (SAR8rCL GR8:$src1)>;
3907 def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
3908 (SAR16rCL GR16:$src1)>;
3909 def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
3910 (SAR32rCL GR32:$src1)>;
3911 def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3912 (SAR8mCL addr:$dst)>;
3913 def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3914 (SAR16mCL addr:$dst)>;
3915 def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3916 (SAR32mCL addr:$dst)>;
3918 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
3919 def : Pat<(or (srl GR32:$src1, CL:$amt),
3920 (shl GR32:$src2, (sub 32, CL:$amt))),
3921 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3923 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
3924 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3925 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3927 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
3928 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3929 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3931 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3932 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3934 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3936 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3937 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3939 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
3940 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3941 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3943 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
3944 def : Pat<(or (shl GR32:$src1, CL:$amt),
3945 (srl GR32:$src2, (sub 32, CL:$amt))),
3946 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3948 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
3949 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3950 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3952 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
3953 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3954 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3956 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3957 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3959 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3961 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3962 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3964 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
3965 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3966 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3968 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
3969 def : Pat<(or (srl GR16:$src1, CL:$amt),
3970 (shl GR16:$src2, (sub 16, CL:$amt))),
3971 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3973 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
3974 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3975 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3977 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
3978 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3979 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3981 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3982 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3984 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3986 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3987 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3989 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
3990 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3991 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3993 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
3994 def : Pat<(or (shl GR16:$src1, CL:$amt),
3995 (srl GR16:$src2, (sub 16, CL:$amt))),
3996 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3998 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
3999 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4000 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4002 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
4003 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4004 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4006 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4007 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4009 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4011 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
4012 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4014 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
4015 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
4016 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4018 //===----------------------------------------------------------------------===//
4019 // EFLAGS-defining Patterns
4020 //===----------------------------------------------------------------------===//
4022 // Register-Register Addition with EFLAGS result
4023 def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
4025 (ADD8rr GR8:$src1, GR8:$src2)>;
4026 def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
4028 (ADD16rr GR16:$src1, GR16:$src2)>;
4029 def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
4031 (ADD32rr GR32:$src1, GR32:$src2)>;
4033 // Register-Memory Addition with EFLAGS result
4034 def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
4036 (ADD8rm GR8:$src1, addr:$src2)>;
4037 def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
4039 (ADD16rm GR16:$src1, addr:$src2)>;
4040 def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
4042 (ADD32rm GR32:$src1, addr:$src2)>;
4044 // Register-Integer Addition with EFLAGS result
4045 def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
4047 (ADD8ri GR8:$src1, imm:$src2)>;
4048 def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
4050 (ADD16ri GR16:$src1, imm:$src2)>;
4051 def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
4053 (ADD32ri GR32:$src1, imm:$src2)>;
4054 def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
4056 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4057 def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
4059 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4061 // Memory-Register Addition with EFLAGS result
4062 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
4065 (ADD8mr addr:$dst, GR8:$src2)>;
4066 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
4069 (ADD16mr addr:$dst, GR16:$src2)>;
4070 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
4073 (ADD32mr addr:$dst, GR32:$src2)>;
4075 // Memory-Integer Addition with EFLAGS result
4076 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
4079 (ADD8mi addr:$dst, imm:$src2)>;
4080 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
4083 (ADD16mi addr:$dst, imm:$src2)>;
4084 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
4087 (ADD32mi addr:$dst, imm:$src2)>;
4088 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4091 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
4092 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4095 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
4097 // Register-Register Subtraction with EFLAGS result
4098 def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
4100 (SUB8rr GR8:$src1, GR8:$src2)>;
4101 def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
4103 (SUB16rr GR16:$src1, GR16:$src2)>;
4104 def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
4106 (SUB32rr GR32:$src1, GR32:$src2)>;
4108 // Register-Memory Subtraction with EFLAGS result
4109 def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
4111 (SUB8rm GR8:$src1, addr:$src2)>;
4112 def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
4114 (SUB16rm GR16:$src1, addr:$src2)>;
4115 def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
4117 (SUB32rm GR32:$src1, addr:$src2)>;
4119 // Register-Integer Subtraction with EFLAGS result
4120 def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
4122 (SUB8ri GR8:$src1, imm:$src2)>;
4123 def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
4125 (SUB16ri GR16:$src1, imm:$src2)>;
4126 def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
4128 (SUB32ri GR32:$src1, imm:$src2)>;
4129 def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
4131 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4132 def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
4134 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4136 // Memory-Register Subtraction with EFLAGS result
4137 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
4140 (SUB8mr addr:$dst, GR8:$src2)>;
4141 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
4144 (SUB16mr addr:$dst, GR16:$src2)>;
4145 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
4148 (SUB32mr addr:$dst, GR32:$src2)>;
4150 // Memory-Integer Subtraction with EFLAGS result
4151 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
4154 (SUB8mi addr:$dst, imm:$src2)>;
4155 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
4158 (SUB16mi addr:$dst, imm:$src2)>;
4159 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
4162 (SUB32mi addr:$dst, imm:$src2)>;
4163 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4166 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
4167 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4170 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
4173 // Register-Register Signed Integer Multiply with EFLAGS result
4174 def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
4176 (IMUL16rr GR16:$src1, GR16:$src2)>;
4177 def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
4179 (IMUL32rr GR32:$src1, GR32:$src2)>;
4181 // Register-Memory Signed Integer Multiply with EFLAGS result
4182 def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
4184 (IMUL16rm GR16:$src1, addr:$src2)>;
4185 def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
4187 (IMUL32rm GR32:$src1, addr:$src2)>;
4189 // Register-Integer Signed Integer Multiply with EFLAGS result
4190 def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
4192 (IMUL16rri GR16:$src1, imm:$src2)>;
4193 def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
4195 (IMUL32rri GR32:$src1, imm:$src2)>;
4196 def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
4198 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4199 def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
4201 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4203 // Memory-Integer Signed Integer Multiply with EFLAGS result
4204 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
4206 (IMUL16rmi addr:$src1, imm:$src2)>;
4207 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
4209 (IMUL32rmi addr:$src1, imm:$src2)>;
4210 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
4212 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4213 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
4215 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4217 // Optimize multiply by 2 with EFLAGS result.
4218 let AddedComplexity = 2 in {
4219 def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
4221 (ADD16rr GR16:$src1, GR16:$src1)>;
4223 def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
4225 (ADD32rr GR32:$src1, GR32:$src1)>;
4228 // INC and DEC with EFLAGS result. Note that these do not set CF.
4229 def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
4231 def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
4234 def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
4236 def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
4240 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
4241 (INC16r GR16:$src)>, Requires<[In32BitMode]>;
4242 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
4244 (INC16m addr:$dst)>, Requires<[In32BitMode]>;
4245 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
4246 (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
4247 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
4249 (DEC16m addr:$dst)>, Requires<[In32BitMode]>;
4251 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
4252 (INC32r GR32:$src)>, Requires<[In32BitMode]>;
4253 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
4255 (INC32m addr:$dst)>, Requires<[In32BitMode]>;
4256 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
4257 (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
4258 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
4260 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
4262 // -disable-16bit support.
4263 def : Pat<(truncstorei16 (i32 imm:$src), addr:$dst),
4264 (MOV16mi addr:$dst, imm:$src)>;
4265 def : Pat<(truncstorei16 GR32:$src, addr:$dst),
4266 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
4267 def : Pat<(i32 (sextloadi16 addr:$dst)),
4268 (MOVSX32rm16 addr:$dst)>;
4269 def : Pat<(i32 (zextloadi16 addr:$dst)),
4270 (MOVZX32rm16 addr:$dst)>;
4271 def : Pat<(i32 (extloadi16 addr:$dst)),
4272 (MOVZX32rm16 addr:$dst)>;
4274 //===----------------------------------------------------------------------===//
4275 // Floating Point Stack Support
4276 //===----------------------------------------------------------------------===//
4278 include "X86InstrFPStack.td"
4280 //===----------------------------------------------------------------------===//
4282 //===----------------------------------------------------------------------===//
4284 include "X86Instr64bit.td"
4286 //===----------------------------------------------------------------------===//
4287 // XMM Floating point support (requires SSE / SSE2)
4288 //===----------------------------------------------------------------------===//
4290 include "X86InstrSSE.td"
4292 //===----------------------------------------------------------------------===//
4293 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
4294 //===----------------------------------------------------------------------===//
4296 include "X86InstrMMX.td"