1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 //def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
36 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
41 SDTCisInt<0>, SDTCisVT<1, i32>]>;
43 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
44 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
50 // RES1, RES2, FLAGS = op LHS, RHS
51 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
55 SDTCisInt<0>, SDTCisVT<1, i32>]>;
56 def SDTX86BrCond : SDTypeProfile<0, 3,
57 [SDTCisVT<0, OtherVT>,
58 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
60 def SDTX86SetCC : SDTypeProfile<1, 2,
62 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
63 def SDTX86SetCC_C : SDTypeProfile<1, 2,
65 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
67 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
69 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
71 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
73 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
75 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
76 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
77 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
79 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
80 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
83 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
85 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
89 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
95 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
97 def SDTX86Void : SDTypeProfile<0, 0, []>;
99 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
101 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
103 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
105 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
107 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
109 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
111 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
113 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
115 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
117 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
118 [SDNPHasChain,SDNPSideEffect]>;
119 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
121 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
123 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
127 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
128 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
129 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
130 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
132 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
133 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
135 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
136 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
138 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
139 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
141 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
143 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
144 [SDNPHasChain, SDNPSideEffect]>;
146 def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand,
147 [SDNPHasChain, SDNPSideEffect]>;
149 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
150 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
151 SDNPMayLoad, SDNPMemOperand]>;
152 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
153 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
154 SDNPMayLoad, SDNPMemOperand]>;
155 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
156 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
157 SDNPMayLoad, SDNPMemOperand]>;
159 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
160 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
162 def X86vastart_save_xmm_regs :
163 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
164 SDT_X86VASTART_SAVE_XMM_REGS,
165 [SDNPHasChain, SDNPVariadic]>;
167 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
168 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
170 def X86callseq_start :
171 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
172 [SDNPHasChain, SDNPOutGlue]>;
174 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
175 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
177 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
178 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
181 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
182 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
183 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
184 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
187 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
188 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
189 def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void,
190 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
191 def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void,
192 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
194 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
195 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
197 def X86RecoverFrameAlloc : SDNode<"ISD::FRAME_ALLOC_RECOVER",
198 SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
201 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
202 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
204 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
205 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
207 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
210 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
211 SDTypeProfile<1, 1, [SDTCisInt<0>,
213 [SDNPHasChain, SDNPSideEffect]>;
214 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
215 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
216 [SDNPHasChain, SDNPSideEffect]>;
218 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
219 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
221 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
223 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
224 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
226 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
228 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
229 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
231 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
232 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
233 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
235 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
237 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
240 def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>;
242 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
244 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
245 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
247 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
250 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
251 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
253 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL,
254 [SDNPHasChain, SDNPOutGlue]>;
256 //===----------------------------------------------------------------------===//
257 // X86 Operand Definitions.
260 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
261 // the index operand of an address, to conform to x86 encoding restrictions.
262 def ptr_rc_nosp : PointerLikeRegClass<1>;
264 // *mem - Operand definitions for the funky X86 addressing mode operands.
266 def X86MemAsmOperand : AsmOperandClass {
269 let RenderMethod = "addMemOperands" in {
270 def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; }
271 def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; }
272 def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; }
273 def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; }
274 def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; }
275 def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; }
276 def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; }
277 def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; }
278 // Gather mem operands
279 def X86MemVX32Operand : AsmOperandClass { let Name = "MemVX32"; }
280 def X86MemVY32Operand : AsmOperandClass { let Name = "MemVY32"; }
281 def X86MemVZ32Operand : AsmOperandClass { let Name = "MemVZ32"; }
282 def X86MemVX64Operand : AsmOperandClass { let Name = "MemVX64"; }
283 def X86MemVY64Operand : AsmOperandClass { let Name = "MemVY64"; }
284 def X86MemVZ64Operand : AsmOperandClass { let Name = "MemVZ64"; }
287 def X86AbsMemAsmOperand : AsmOperandClass {
289 let SuperClasses = [X86MemAsmOperand];
292 class X86MemOperand<string printMethod,
293 AsmOperandClass parserMatchClass = X86MemAsmOperand> : Operand<iPTR> {
294 let PrintMethod = printMethod;
295 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
296 let ParserMatchClass = parserMatchClass;
297 let OperandType = "OPERAND_MEMORY";
300 // Gather mem operands
301 class X86VMemOperand<RegisterClass RC, string printMethod,
302 AsmOperandClass parserMatchClass>
303 : X86MemOperand<printMethod, parserMatchClass> {
304 let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, i8imm);
307 def anymem : X86MemOperand<"printanymem">;
309 def opaque32mem : X86MemOperand<"printopaquemem">;
310 def opaque48mem : X86MemOperand<"printopaquemem">;
311 def opaque80mem : X86MemOperand<"printopaquemem">;
312 def opaque512mem : X86MemOperand<"printopaquemem">;
314 def i8mem : X86MemOperand<"printi8mem", X86Mem8AsmOperand>;
315 def i16mem : X86MemOperand<"printi16mem", X86Mem16AsmOperand>;
316 def i32mem : X86MemOperand<"printi32mem", X86Mem32AsmOperand>;
317 def i64mem : X86MemOperand<"printi64mem", X86Mem64AsmOperand>;
318 def i128mem : X86MemOperand<"printi128mem", X86Mem128AsmOperand>;
319 def i256mem : X86MemOperand<"printi256mem", X86Mem256AsmOperand>;
320 def i512mem : X86MemOperand<"printi512mem", X86Mem512AsmOperand>;
321 def f32mem : X86MemOperand<"printf32mem", X86Mem32AsmOperand>;
322 def f64mem : X86MemOperand<"printf64mem", X86Mem64AsmOperand>;
323 def f80mem : X86MemOperand<"printf80mem", X86Mem80AsmOperand>;
324 def f128mem : X86MemOperand<"printf128mem", X86Mem128AsmOperand>;
325 def f256mem : X86MemOperand<"printf256mem", X86Mem256AsmOperand>;
326 def f512mem : X86MemOperand<"printf512mem", X86Mem512AsmOperand>;
328 def v512mem : X86VMemOperand<VR512, "printf512mem", X86Mem512AsmOperand>;
330 // Gather mem operands
331 def vx32mem : X86VMemOperand<VR128, "printi32mem", X86MemVX32Operand>;
332 def vy32mem : X86VMemOperand<VR256, "printi32mem", X86MemVY32Operand>;
333 def vx64mem : X86VMemOperand<VR128, "printi64mem", X86MemVX64Operand>;
334 def vy64mem : X86VMemOperand<VR256, "printi64mem", X86MemVY64Operand>;
335 def vy64xmem : X86VMemOperand<VR256X, "printi64mem", X86MemVY64Operand>;
336 def vz32mem : X86VMemOperand<VR512, "printi32mem", X86MemVZ32Operand>;
337 def vz64mem : X86VMemOperand<VR512, "printi64mem", X86MemVZ64Operand>;
339 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
340 // plain GR64, so that it doesn't potentially require a REX prefix.
341 def i8mem_NOREX : Operand<i64> {
342 let PrintMethod = "printi8mem";
343 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
344 let ParserMatchClass = X86Mem8AsmOperand;
345 let OperandType = "OPERAND_MEMORY";
348 // GPRs available for tailcall.
349 // It represents GR32_TC, GR64_TC or GR64_TCW64.
350 def ptr_rc_tailcall : PointerLikeRegClass<2>;
352 // Special i32mem for addresses of load folding tail calls. These are not
353 // allowed to use callee-saved registers since they must be scheduled
354 // after callee-saved register are popped.
355 def i32mem_TC : Operand<i32> {
356 let PrintMethod = "printi32mem";
357 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
359 let ParserMatchClass = X86Mem32AsmOperand;
360 let OperandType = "OPERAND_MEMORY";
363 // Special i64mem for addresses of load folding tail calls. These are not
364 // allowed to use callee-saved registers since they must be scheduled
365 // after callee-saved register are popped.
366 def i64mem_TC : Operand<i64> {
367 let PrintMethod = "printi64mem";
368 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
369 ptr_rc_tailcall, i32imm, i8imm);
370 let ParserMatchClass = X86Mem64AsmOperand;
371 let OperandType = "OPERAND_MEMORY";
374 let OperandType = "OPERAND_PCREL",
375 ParserMatchClass = X86AbsMemAsmOperand,
376 PrintMethod = "printPCRelImm" in {
377 def i32imm_pcrel : Operand<i32>;
378 def i16imm_pcrel : Operand<i16>;
380 // Branch targets have OtherVT type and print as pc-relative values.
381 def brtarget : Operand<OtherVT>;
382 def brtarget8 : Operand<OtherVT>;
386 // Special parsers to detect mode to disambiguate.
387 def X86AbsMem16AsmOperand : AsmOperandClass {
388 let Name = "AbsMem16";
389 let RenderMethod = "addAbsMemOperands";
390 let SuperClasses = [X86AbsMemAsmOperand];
393 def X86AbsMem32AsmOperand : AsmOperandClass {
394 let Name = "AbsMem32";
395 let RenderMethod = "addAbsMemOperands";
396 let SuperClasses = [X86AbsMemAsmOperand];
399 // Branch targets have OtherVT type and print as pc-relative values.
400 let OperandType = "OPERAND_PCREL",
401 PrintMethod = "printPCRelImm" in {
402 let ParserMatchClass = X86AbsMem16AsmOperand in
403 def brtarget16 : Operand<OtherVT>;
404 let ParserMatchClass = X86AbsMem32AsmOperand in
405 def brtarget32 : Operand<OtherVT>;
408 let RenderMethod = "addSrcIdxOperands" in {
409 def X86SrcIdx8Operand : AsmOperandClass {
410 let Name = "SrcIdx8";
411 let SuperClasses = [X86Mem8AsmOperand];
413 def X86SrcIdx16Operand : AsmOperandClass {
414 let Name = "SrcIdx16";
415 let SuperClasses = [X86Mem16AsmOperand];
417 def X86SrcIdx32Operand : AsmOperandClass {
418 let Name = "SrcIdx32";
419 let SuperClasses = [X86Mem32AsmOperand];
421 def X86SrcIdx64Operand : AsmOperandClass {
422 let Name = "SrcIdx64";
423 let SuperClasses = [X86Mem64AsmOperand];
425 } // RenderMethod = "addSrcIdxOperands"
427 let RenderMethod = "addDstIdxOperands" in {
428 def X86DstIdx8Operand : AsmOperandClass {
429 let Name = "DstIdx8";
430 let SuperClasses = [X86Mem8AsmOperand];
432 def X86DstIdx16Operand : AsmOperandClass {
433 let Name = "DstIdx16";
434 let SuperClasses = [X86Mem16AsmOperand];
436 def X86DstIdx32Operand : AsmOperandClass {
437 let Name = "DstIdx32";
438 let SuperClasses = [X86Mem32AsmOperand];
440 def X86DstIdx64Operand : AsmOperandClass {
441 let Name = "DstIdx64";
442 let SuperClasses = [X86Mem64AsmOperand];
444 } // RenderMethod = "addDstIdxOperands"
446 let RenderMethod = "addMemOffsOperands" in {
447 def X86MemOffs16_8AsmOperand : AsmOperandClass {
448 let Name = "MemOffs16_8";
449 let SuperClasses = [X86Mem8AsmOperand];
451 def X86MemOffs16_16AsmOperand : AsmOperandClass {
452 let Name = "MemOffs16_16";
453 let SuperClasses = [X86Mem16AsmOperand];
455 def X86MemOffs16_32AsmOperand : AsmOperandClass {
456 let Name = "MemOffs16_32";
457 let SuperClasses = [X86Mem32AsmOperand];
459 def X86MemOffs32_8AsmOperand : AsmOperandClass {
460 let Name = "MemOffs32_8";
461 let SuperClasses = [X86Mem8AsmOperand];
463 def X86MemOffs32_16AsmOperand : AsmOperandClass {
464 let Name = "MemOffs32_16";
465 let SuperClasses = [X86Mem16AsmOperand];
467 def X86MemOffs32_32AsmOperand : AsmOperandClass {
468 let Name = "MemOffs32_32";
469 let SuperClasses = [X86Mem32AsmOperand];
471 def X86MemOffs32_64AsmOperand : AsmOperandClass {
472 let Name = "MemOffs32_64";
473 let SuperClasses = [X86Mem64AsmOperand];
475 def X86MemOffs64_8AsmOperand : AsmOperandClass {
476 let Name = "MemOffs64_8";
477 let SuperClasses = [X86Mem8AsmOperand];
479 def X86MemOffs64_16AsmOperand : AsmOperandClass {
480 let Name = "MemOffs64_16";
481 let SuperClasses = [X86Mem16AsmOperand];
483 def X86MemOffs64_32AsmOperand : AsmOperandClass {
484 let Name = "MemOffs64_32";
485 let SuperClasses = [X86Mem32AsmOperand];
487 def X86MemOffs64_64AsmOperand : AsmOperandClass {
488 let Name = "MemOffs64_64";
489 let SuperClasses = [X86Mem64AsmOperand];
491 } // RenderMethod = "addMemOffsOperands"
493 class X86SrcIdxOperand<string printMethod, AsmOperandClass parserMatchClass>
494 : X86MemOperand<printMethod, parserMatchClass> {
495 let MIOperandInfo = (ops ptr_rc, i8imm);
498 class X86DstIdxOperand<string printMethod, AsmOperandClass parserMatchClass>
499 : X86MemOperand<printMethod, parserMatchClass> {
500 let MIOperandInfo = (ops ptr_rc);
503 def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>;
504 def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>;
505 def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>;
506 def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>;
507 def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>;
508 def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>;
509 def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>;
510 def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>;
512 class X86MemOffsOperand<Operand immOperand, string printMethod,
513 AsmOperandClass parserMatchClass>
514 : X86MemOperand<printMethod, parserMatchClass> {
515 let MIOperandInfo = (ops immOperand, i8imm);
518 def offset16_8 : X86MemOffsOperand<i16imm, "printMemOffs8",
519 X86MemOffs16_8AsmOperand>;
520 def offset16_16 : X86MemOffsOperand<i16imm, "printMemOffs16",
521 X86MemOffs16_16AsmOperand>;
522 def offset16_32 : X86MemOffsOperand<i16imm, "printMemOffs32",
523 X86MemOffs16_32AsmOperand>;
524 def offset32_8 : X86MemOffsOperand<i32imm, "printMemOffs8",
525 X86MemOffs32_8AsmOperand>;
526 def offset32_16 : X86MemOffsOperand<i32imm, "printMemOffs16",
527 X86MemOffs32_16AsmOperand>;
528 def offset32_32 : X86MemOffsOperand<i32imm, "printMemOffs32",
529 X86MemOffs32_32AsmOperand>;
530 def offset32_64 : X86MemOffsOperand<i32imm, "printMemOffs64",
531 X86MemOffs32_64AsmOperand>;
532 def offset64_8 : X86MemOffsOperand<i64imm, "printMemOffs8",
533 X86MemOffs64_8AsmOperand>;
534 def offset64_16 : X86MemOffsOperand<i64imm, "printMemOffs16",
535 X86MemOffs64_16AsmOperand>;
536 def offset64_32 : X86MemOffsOperand<i64imm, "printMemOffs32",
537 X86MemOffs64_32AsmOperand>;
538 def offset64_64 : X86MemOffsOperand<i64imm, "printMemOffs64",
539 X86MemOffs64_64AsmOperand>;
541 def SSECC : Operand<i8> {
542 let PrintMethod = "printSSEAVXCC";
543 let OperandType = "OPERAND_IMMEDIATE";
546 def i8immZExt3 : ImmLeaf<i8, [{
547 return Imm >= 0 && Imm < 8;
550 def AVXCC : Operand<i8> {
551 let PrintMethod = "printSSEAVXCC";
552 let OperandType = "OPERAND_IMMEDIATE";
555 def i8immZExt5 : ImmLeaf<i8, [{
556 return Imm >= 0 && Imm < 32;
559 def AVX512ICC : Operand<i8> {
560 let PrintMethod = "printSSEAVXCC";
561 let OperandType = "OPERAND_IMMEDIATE";
564 class ImmSExtAsmOperandClass : AsmOperandClass {
565 let SuperClasses = [ImmAsmOperand];
566 let RenderMethod = "addImmOperands";
569 def X86GR32orGR64AsmOperand : AsmOperandClass {
570 let Name = "GR32orGR64";
573 def GR32orGR64 : RegisterOperand<GR32> {
574 let ParserMatchClass = X86GR32orGR64AsmOperand;
577 def AVX512RC : Operand<i32> {
578 let PrintMethod = "printRoundingControl";
579 let OperandType = "OPERAND_IMMEDIATE";
582 // Sign-extended immediate classes. We don't need to define the full lattice
583 // here because there is no instruction with an ambiguity between ImmSExti64i32
586 // The strange ranges come from the fact that the assembler always works with
587 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
588 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
591 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
592 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
593 let Name = "ImmSExti64i32";
596 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
597 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
598 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
599 let Name = "ImmSExti16i8";
600 let SuperClasses = [ImmSExti64i32AsmOperand];
603 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
604 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
605 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
606 let Name = "ImmSExti32i8";
610 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
611 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
612 let Name = "ImmSExti64i8";
613 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
614 ImmSExti64i32AsmOperand];
617 // Unsigned immediate used by SSE/AVX instructions
619 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
620 def ImmUnsignedi8AsmOperand : AsmOperandClass {
621 let Name = "ImmUnsignedi8";
622 let RenderMethod = "addImmOperands";
625 // A couple of more descriptive operand definitions.
626 // 16-bits but only 8 bits are significant.
627 def i16i8imm : Operand<i16> {
628 let ParserMatchClass = ImmSExti16i8AsmOperand;
629 let OperandType = "OPERAND_IMMEDIATE";
631 // 32-bits but only 8 bits are significant.
632 def i32i8imm : Operand<i32> {
633 let ParserMatchClass = ImmSExti32i8AsmOperand;
634 let OperandType = "OPERAND_IMMEDIATE";
637 // 64-bits but only 32 bits are significant.
638 def i64i32imm : Operand<i64> {
639 let ParserMatchClass = ImmSExti64i32AsmOperand;
640 let OperandType = "OPERAND_IMMEDIATE";
643 // 64-bits but only 8 bits are significant.
644 def i64i8imm : Operand<i64> {
645 let ParserMatchClass = ImmSExti64i8AsmOperand;
646 let OperandType = "OPERAND_IMMEDIATE";
649 // Unsigned 8-bit immediate used by SSE/AVX instructions.
650 def u8imm : Operand<i8> {
651 let PrintMethod = "printU8Imm";
652 let ParserMatchClass = ImmUnsignedi8AsmOperand;
653 let OperandType = "OPERAND_IMMEDIATE";
656 // 32-bit immediate but only 8-bits are significant and they are unsigned.
657 // Used by some SSE/AVX instructions that use intrinsics.
658 def i32u8imm : Operand<i32> {
659 let PrintMethod = "printU8Imm";
660 let ParserMatchClass = ImmUnsignedi8AsmOperand;
661 let OperandType = "OPERAND_IMMEDIATE";
664 // 64-bits but only 32 bits are significant, and those bits are treated as being
666 def i64i32imm_pcrel : Operand<i64> {
667 let PrintMethod = "printPCRelImm";
668 let ParserMatchClass = X86AbsMemAsmOperand;
669 let OperandType = "OPERAND_PCREL";
672 def lea64_32mem : Operand<i32> {
673 let PrintMethod = "printanymem";
674 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
675 let ParserMatchClass = X86MemAsmOperand;
678 // Memory operands that use 64-bit pointers in both ILP32 and LP64.
679 def lea64mem : Operand<i64> {
680 let PrintMethod = "printanymem";
681 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
682 let ParserMatchClass = X86MemAsmOperand;
686 //===----------------------------------------------------------------------===//
687 // X86 Complex Pattern Definitions.
690 // Define X86 specific addressing mode.
691 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
692 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
693 [add, sub, mul, X86mul_imm, shl, or, frameindex],
695 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
696 def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr",
697 [add, sub, mul, X86mul_imm, shl, or,
698 frameindex, X86WrapperRIP],
701 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
702 [tglobaltlsaddr], []>;
704 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
705 [tglobaltlsaddr], []>;
707 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
708 [add, sub, mul, X86mul_imm, shl, or, frameindex,
711 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
712 [tglobaltlsaddr], []>;
714 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
715 [tglobaltlsaddr], []>;
717 //===----------------------------------------------------------------------===//
718 // X86 Instruction Predicate Definitions.
719 def HasCMov : Predicate<"Subtarget->hasCMov()">;
720 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
722 def HasMMX : Predicate<"Subtarget->hasMMX()">;
723 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
724 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
725 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
726 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
727 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
728 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
729 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
730 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
731 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
732 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
733 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
734 def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">;
735 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
736 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
737 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
738 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
739 def HasAVX : Predicate<"Subtarget->hasAVX()">;
740 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
741 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
742 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">,
743 AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">;
744 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
745 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
746 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
747 def HasCDI : Predicate<"Subtarget->hasCDI()">;
748 def HasPFI : Predicate<"Subtarget->hasPFI()">;
749 def HasERI : Predicate<"Subtarget->hasERI()">;
750 def HasDQI : Predicate<"Subtarget->hasDQI()">;
751 def NoDQI : Predicate<"!Subtarget->hasDQI()">;
752 def HasBWI : Predicate<"Subtarget->hasBWI()">;
753 def HasVLX : Predicate<"Subtarget->hasVLX()">,
754 AssemblerPredicate<"FeatureVLX", "AVX-512 VLX ISA">;
755 def NoVLX : Predicate<"!Subtarget->hasVLX()">;
757 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
758 def HasAES : Predicate<"Subtarget->hasAES()">;
759 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
760 def HasFMA : Predicate<"Subtarget->hasFMA()">;
761 def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">;
762 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
763 def HasXOP : Predicate<"Subtarget->hasXOP()">;
764 def HasTBM : Predicate<"Subtarget->hasTBM()">;
765 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
766 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
767 def HasF16C : Predicate<"Subtarget->hasF16C()">;
768 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
769 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
770 def HasBMI : Predicate<"Subtarget->hasBMI()">;
771 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
772 def HasRTM : Predicate<"Subtarget->hasRTM()">;
773 def HasHLE : Predicate<"Subtarget->hasHLE()">;
774 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
775 def HasADX : Predicate<"Subtarget->hasADX()">;
776 def HasSHA : Predicate<"Subtarget->hasSHA()">;
777 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
778 def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
779 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
780 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
781 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
782 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
783 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
784 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
785 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
786 AssemblerPredicate<"Mode64Bit", "64-bit mode">;
787 def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">;
788 def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">;
789 def In16BitMode : Predicate<"Subtarget->is16Bit()">,
790 AssemblerPredicate<"Mode16Bit", "16-bit mode">;
791 def Not16BitMode : Predicate<"!Subtarget->is16Bit()">,
792 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">;
793 def In32BitMode : Predicate<"Subtarget->is32Bit()">,
794 AssemblerPredicate<"Mode32Bit", "32-bit mode">;
795 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
796 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
797 def IsPS4 : Predicate<"Subtarget->isTargetPS4()">;
798 def NotPS4 : Predicate<"!Subtarget->isTargetPS4()">;
799 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
800 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
801 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
802 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
803 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
804 "TM.getCodeModel() != CodeModel::Kernel">;
805 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
806 "TM.getCodeModel() == CodeModel::Kernel">;
807 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
808 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
809 def OptForSize : Predicate<"OptForSize">;
810 def OptForSpeed : Predicate<"!OptForSize">;
811 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
812 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
813 def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">;
814 def NotSlowIncDec : Predicate<"!Subtarget->slowIncDec()">;
815 def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">;
817 //===----------------------------------------------------------------------===//
818 // X86 Instruction Format Definitions.
821 include "X86InstrFormats.td"
823 //===----------------------------------------------------------------------===//
824 // Pattern fragments.
827 // X86 specific condition code. These correspond to CondCode in
828 // X86InstrInfo.h. They must be kept in synch.
829 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
830 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
831 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
832 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
833 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
834 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
835 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
836 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
837 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
838 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
839 def X86_COND_NO : PatLeaf<(i8 10)>;
840 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
841 def X86_COND_NS : PatLeaf<(i8 12)>;
842 def X86_COND_O : PatLeaf<(i8 13)>;
843 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
844 def X86_COND_S : PatLeaf<(i8 15)>;
846 // Predicate used to help when pattern matching LZCNT/TZCNT.
847 def X86_COND_E_OR_NE : ImmLeaf<i8, [{
848 return (Imm == X86::COND_E) || (Imm == X86::COND_NE);
851 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
852 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
853 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
854 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
857 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
860 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
862 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
864 def i64immZExt32SExt8 : ImmLeaf<i64, [{
865 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
868 // Helper fragments for loads.
869 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
870 // known to be 32-bit aligned or better. Ditto for i8 to i16.
871 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
872 LoadSDNode *LD = cast<LoadSDNode>(N);
873 ISD::LoadExtType ExtType = LD->getExtensionType();
874 if (ExtType == ISD::NON_EXTLOAD)
876 if (ExtType == ISD::EXTLOAD)
877 return LD->getAlignment() >= 2 && !LD->isVolatile();
881 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
882 LoadSDNode *LD = cast<LoadSDNode>(N);
883 ISD::LoadExtType ExtType = LD->getExtensionType();
884 if (ExtType == ISD::EXTLOAD)
885 return LD->getAlignment() >= 2 && !LD->isVolatile();
889 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
890 LoadSDNode *LD = cast<LoadSDNode>(N);
891 ISD::LoadExtType ExtType = LD->getExtensionType();
892 if (ExtType == ISD::NON_EXTLOAD)
894 if (ExtType == ISD::EXTLOAD)
895 return LD->getAlignment() >= 4 && !LD->isVolatile();
899 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
900 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
901 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
902 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
903 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
905 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
906 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
907 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
908 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
909 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
910 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
912 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
913 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
914 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
915 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
916 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
917 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
918 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
919 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
920 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
921 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
923 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
924 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
925 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
926 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
927 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
928 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
929 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
930 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
931 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
932 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
935 // An 'and' node with a single use.
936 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
937 return N->hasOneUse();
939 // An 'srl' node with a single use.
940 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
941 return N->hasOneUse();
943 // An 'trunc' node with a single use.
944 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
945 return N->hasOneUse();
948 //===----------------------------------------------------------------------===//
953 let hasSideEffects = 0, SchedRW = [WriteZero] in {
954 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
955 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero),
956 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
957 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero),
958 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
962 // Constructing a stack frame.
963 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
964 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
966 let SchedRW = [WriteALU] in {
967 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in
968 def LEAVE : I<0xC9, RawFrm,
969 (outs), (ins), "leave", [], IIC_LEAVE>,
970 Requires<[Not64BitMode]>;
972 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in
973 def LEAVE64 : I<0xC9, RawFrm,
974 (outs), (ins), "leave", [], IIC_LEAVE>,
975 Requires<[In64BitMode]>;
978 //===----------------------------------------------------------------------===//
979 // Miscellaneous Instructions.
982 let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in {
983 let mayLoad = 1, SchedRW = [WriteLoad] in {
984 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
985 IIC_POP_REG16>, OpSize16;
986 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
987 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
988 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
989 IIC_POP_REG>, OpSize16;
990 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
991 IIC_POP_MEM>, OpSize16;
992 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
993 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
994 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
995 IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>;
996 } // mayLoad, SchedRW
998 let mayStore = 1, SchedRW = [WriteStore] in {
999 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
1000 IIC_PUSH_REG>, OpSize16;
1001 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
1002 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
1003 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
1004 IIC_PUSH_REG>, OpSize16;
1005 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
1006 IIC_PUSH_MEM>, OpSize16;
1007 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
1008 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
1009 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
1010 IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>;
1012 def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
1013 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1014 Requires<[Not64BitMode]>;
1015 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
1016 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1017 Requires<[Not64BitMode]>;
1018 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1019 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1020 Requires<[Not64BitMode]>;
1021 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
1022 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1023 Requires<[Not64BitMode]>;
1024 } // mayStore, SchedRW
1027 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
1028 SchedRW = [WriteLoad] in {
1029 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>,
1031 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
1032 OpSize32, Requires<[Not64BitMode]>;
1035 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0,
1036 SchedRW = [WriteStore] in {
1037 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
1039 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
1040 OpSize32, Requires<[Not64BitMode]>;
1043 let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in {
1044 let mayLoad = 1, SchedRW = [WriteLoad] in {
1045 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1046 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
1047 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1048 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
1049 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [],
1050 IIC_POP_MEM>, OpSize32, Requires<[In64BitMode]>;
1051 } // mayLoad, SchedRW
1052 let mayStore = 1, SchedRW = [WriteStore] in {
1053 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1054 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1055 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1056 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1057 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
1058 IIC_PUSH_MEM>, OpSize32, Requires<[In64BitMode]>;
1059 } // mayStore, SchedRW
1062 let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1,
1063 SchedRW = [WriteStore] in {
1064 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
1065 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
1066 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1067 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1068 Requires<[In64BitMode]>;
1069 def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
1070 "push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1071 Requires<[In64BitMode]>;
1074 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
1075 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
1076 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>;
1077 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in
1078 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
1079 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>;
1081 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
1082 mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in {
1083 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>,
1084 OpSize32, Requires<[Not64BitMode]>;
1085 def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>,
1086 OpSize16, Requires<[Not64BitMode]>;
1088 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
1089 mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
1090 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>,
1091 OpSize32, Requires<[Not64BitMode]>;
1092 def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>,
1093 OpSize16, Requires<[Not64BitMode]>;
1096 let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
1097 // GR32 = bswap GR32
1098 def BSWAP32r : I<0xC8, AddRegFrm,
1099 (outs GR32:$dst), (ins GR32:$src),
1101 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB;
1103 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
1105 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
1106 } // Constraints = "$src = $dst", SchedRW
1108 // Bit scan instructions.
1109 let Defs = [EFLAGS] in {
1110 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1111 "bsf{w}\t{$src, $dst|$dst, $src}",
1112 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
1113 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1114 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1115 "bsf{w}\t{$src, $dst|$dst, $src}",
1116 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
1117 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1118 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1119 "bsf{l}\t{$src, $dst|$dst, $src}",
1120 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
1121 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1122 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1123 "bsf{l}\t{$src, $dst|$dst, $src}",
1124 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
1125 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1126 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1127 "bsf{q}\t{$src, $dst|$dst, $src}",
1128 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
1129 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1130 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1131 "bsf{q}\t{$src, $dst|$dst, $src}",
1132 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
1133 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1135 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1136 "bsr{w}\t{$src, $dst|$dst, $src}",
1137 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))],
1138 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1139 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1140 "bsr{w}\t{$src, $dst|$dst, $src}",
1141 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
1142 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1143 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1144 "bsr{l}\t{$src, $dst|$dst, $src}",
1145 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
1146 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1147 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1148 "bsr{l}\t{$src, $dst|$dst, $src}",
1149 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
1150 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1151 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1152 "bsr{q}\t{$src, $dst|$dst, $src}",
1153 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))],
1154 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1155 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1156 "bsr{q}\t{$src, $dst|$dst, $src}",
1157 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
1158 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1159 } // Defs = [EFLAGS]
1161 let SchedRW = [WriteMicrocoded] in {
1162 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1163 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
1164 def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src),
1165 "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1166 def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src),
1167 "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16;
1168 def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src),
1169 "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize32;
1170 def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src),
1171 "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1174 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1175 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
1176 def STOSB : I<0xAA, RawFrmDst, (outs dstidx8:$dst), (ins),
1177 "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>;
1178 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
1179 def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins),
1180 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16;
1181 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
1182 def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins),
1183 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32;
1184 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
1185 def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins),
1186 "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>;
1188 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1189 let Defs = [EDI,EFLAGS], Uses = [AL,EDI,EFLAGS] in
1190 def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst),
1191 "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>;
1192 let Defs = [EDI,EFLAGS], Uses = [AX,EDI,EFLAGS] in
1193 def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst),
1194 "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16;
1195 let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,EFLAGS] in
1196 def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst),
1197 "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32;
1198 let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,EFLAGS] in
1199 def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst),
1200 "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>;
1202 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1203 let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,EFLAGS] in {
1204 def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src),
1205 "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1206 def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src),
1207 "cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16;
1208 def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src),
1209 "cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize32;
1210 def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src),
1211 "cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1215 //===----------------------------------------------------------------------===//
1216 // Move Instructions.
1218 let SchedRW = [WriteMove] in {
1219 let hasSideEffects = 0 in {
1220 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1221 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1222 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1223 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1224 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1225 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1226 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1227 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1230 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1231 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1232 "mov{b}\t{$src, $dst|$dst, $src}",
1233 [(set GR8:$dst, imm:$src)], IIC_MOV>;
1234 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1235 "mov{w}\t{$src, $dst|$dst, $src}",
1236 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize16;
1237 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1238 "mov{l}\t{$src, $dst|$dst, $src}",
1239 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize32;
1240 def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1241 "mov{q}\t{$src, $dst|$dst, $src}",
1242 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
1244 let isReMaterializable = 1 in {
1245 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
1246 "movabs{q}\t{$src, $dst|$dst, $src}",
1247 [(set GR64:$dst, imm:$src)], IIC_MOV>;
1250 // Longer forms that use a ModR/M byte. Needed for disassembler
1251 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1252 def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src),
1253 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1254 def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src),
1255 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1256 def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src),
1257 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1261 let SchedRW = [WriteStore] in {
1262 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1263 "mov{b}\t{$src, $dst|$dst, $src}",
1264 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
1265 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1266 "mov{w}\t{$src, $dst|$dst, $src}",
1267 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
1268 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1269 "mov{l}\t{$src, $dst|$dst, $src}",
1270 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32;
1271 def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1272 "mov{q}\t{$src, $dst|$dst, $src}",
1273 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
1276 let hasSideEffects = 0 in {
1278 /// Memory offset versions of moves. The immediate is an address mode sized
1279 /// offset from the segment base.
1280 let SchedRW = [WriteALU] in {
1281 let mayLoad = 1 in {
1283 def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src),
1284 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
1287 def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src),
1288 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1291 def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src),
1292 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1295 def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src),
1296 "mov{q}\t{$src, %rax|rax, $src}", [], IIC_MOV_MEM>,
1300 def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src),
1301 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, AdSize16;
1303 def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src),
1304 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1307 def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src),
1308 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1311 let mayStore = 1 in {
1313 def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs offset32_8:$dst), (ins),
1314 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize32;
1316 def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_16:$dst), (ins),
1317 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1320 def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_32:$dst), (ins),
1321 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1324 def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs offset32_64:$dst), (ins),
1325 "mov{q}\t{%rax, $dst|$dst, rax}", [], IIC_MOV_MEM>,
1329 def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs offset16_8:$dst), (ins),
1330 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize16;
1332 def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_16:$dst), (ins),
1333 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1336 def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_32:$dst), (ins),
1337 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1342 // These forms all have full 64-bit absolute addresses in their instructions
1343 // and use the movabs mnemonic to indicate this specific form.
1344 let mayLoad = 1 in {
1346 def MOV8ao64 : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src),
1347 "movabs{b}\t{$src, %al|al, $src}", []>, AdSize64;
1349 def MOV16ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src),
1350 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16, AdSize64;
1352 def MOV32ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src),
1353 "movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32,
1356 def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src),
1357 "movabs{q}\t{$src, %rax|rax, $src}", []>, AdSize64;
1360 let mayStore = 1 in {
1362 def MOV8o64a : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset64_8:$dst), (ins),
1363 "movabs{b}\t{%al, $dst|$dst, al}", []>, AdSize64;
1365 def MOV16o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_16:$dst), (ins),
1366 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16, AdSize64;
1368 def MOV32o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_32:$dst), (ins),
1369 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32,
1372 def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs offset64_64:$dst), (ins),
1373 "movabs{q}\t{%rax, $dst|$dst, rax}", []>, AdSize64;
1375 } // hasSideEffects = 0
1377 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
1378 SchedRW = [WriteMove] in {
1379 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1380 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1381 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1382 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1383 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1384 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1385 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1386 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1389 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1390 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1391 "mov{b}\t{$src, $dst|$dst, $src}",
1392 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1393 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1394 "mov{w}\t{$src, $dst|$dst, $src}",
1395 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize16;
1396 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1397 "mov{l}\t{$src, $dst|$dst, $src}",
1398 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32;
1399 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1400 "mov{q}\t{$src, $dst|$dst, $src}",
1401 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1404 let SchedRW = [WriteStore] in {
1405 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1406 "mov{b}\t{$src, $dst|$dst, $src}",
1407 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1408 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1409 "mov{w}\t{$src, $dst|$dst, $src}",
1410 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
1411 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1412 "mov{l}\t{$src, $dst|$dst, $src}",
1413 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32;
1414 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1415 "mov{q}\t{$src, $dst|$dst, $src}",
1416 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1419 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1420 // that they can be used for copying and storing h registers, which can't be
1421 // encoded when a REX prefix is present.
1422 let isCodeGenOnly = 1 in {
1423 let hasSideEffects = 0 in
1424 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1425 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1426 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
1428 let mayStore = 1, hasSideEffects = 0 in
1429 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1430 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1431 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1432 IIC_MOV_MEM>, Sched<[WriteStore]>;
1433 let mayLoad = 1, hasSideEffects = 0,
1434 canFoldAsLoad = 1, isReMaterializable = 1 in
1435 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1436 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1437 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1438 IIC_MOV_MEM>, Sched<[WriteLoad]>;
1442 // Condition code ops, incl. set if equal/not equal/...
1443 let SchedRW = [WriteALU] in {
1444 let Defs = [EFLAGS], Uses = [AH] in
1445 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1446 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
1447 let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in
1448 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1449 IIC_AHF>; // AH = flags
1452 //===----------------------------------------------------------------------===//
1453 // Bit tests instructions: BT, BTS, BTR, BTC.
1455 let Defs = [EFLAGS] in {
1456 let SchedRW = [WriteALU] in {
1457 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1458 "bt{w}\t{$src2, $src1|$src1, $src2}",
1459 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1461 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1462 "bt{l}\t{$src2, $src1|$src1, $src2}",
1463 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,
1465 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1466 "bt{q}\t{$src2, $src1|$src1, $src2}",
1467 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1470 // Unlike with the register+register form, the memory+register form of the
1471 // bt instruction does not ignore the high bits of the index. From ISel's
1472 // perspective, this is pretty bizarre. Make these instructions disassembly
1475 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
1476 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1477 "bt{w}\t{$src2, $src1|$src1, $src2}",
1478 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1479 // (implicit EFLAGS)]
1481 >, OpSize16, TB, Requires<[FastBTMem]>;
1482 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1483 "bt{l}\t{$src2, $src1|$src1, $src2}",
1484 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1485 // (implicit EFLAGS)]
1487 >, OpSize32, TB, Requires<[FastBTMem]>;
1488 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1489 "bt{q}\t{$src2, $src1|$src1, $src2}",
1490 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1491 // (implicit EFLAGS)]
1496 let SchedRW = [WriteALU] in {
1497 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1498 "bt{w}\t{$src2, $src1|$src1, $src2}",
1499 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1500 IIC_BT_RI>, OpSize16, TB;
1501 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1502 "bt{l}\t{$src2, $src1|$src1, $src2}",
1503 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1504 IIC_BT_RI>, OpSize32, TB;
1505 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1506 "bt{q}\t{$src2, $src1|$src1, $src2}",
1507 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1511 // Note that these instructions don't need FastBTMem because that
1512 // only applies when the other operand is in a register. When it's
1513 // an immediate, bt is still fast.
1514 let SchedRW = [WriteALU] in {
1515 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1516 "bt{w}\t{$src2, $src1|$src1, $src2}",
1517 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1518 ], IIC_BT_MI>, OpSize16, TB;
1519 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1520 "bt{l}\t{$src2, $src1|$src1, $src2}",
1521 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1522 ], IIC_BT_MI>, OpSize32, TB;
1523 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1524 "bt{q}\t{$src2, $src1|$src1, $src2}",
1525 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1526 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1529 let hasSideEffects = 0 in {
1530 let SchedRW = [WriteALU] in {
1531 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1532 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1534 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1535 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1537 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1538 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1541 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1542 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1543 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1545 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1546 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1548 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1549 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1552 let SchedRW = [WriteALU] in {
1553 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1554 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1556 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1557 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1559 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1560 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1563 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1564 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1565 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1567 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1568 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1570 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1571 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1574 let SchedRW = [WriteALU] in {
1575 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1576 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1578 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1579 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1581 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1582 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1585 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1586 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1587 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1589 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1590 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1592 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1593 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1596 let SchedRW = [WriteALU] in {
1597 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1598 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1600 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1601 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1603 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1604 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1607 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1608 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1609 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1611 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1612 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1614 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1615 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1618 let SchedRW = [WriteALU] in {
1619 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1620 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1622 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1623 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1625 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1626 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1629 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1630 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1631 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1633 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1634 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1636 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1637 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1640 let SchedRW = [WriteALU] in {
1641 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1642 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1644 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1645 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1647 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1648 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1651 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1652 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1653 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1655 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1656 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1658 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1659 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1661 } // hasSideEffects = 0
1662 } // Defs = [EFLAGS]
1665 //===----------------------------------------------------------------------===//
1669 // Atomic swap. These are just normal xchg instructions. But since a memory
1670 // operand is referenced, the atomicity is ensured.
1671 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
1672 InstrItinClass itin> {
1673 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
1674 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
1675 (ins GR8:$val, i8mem:$ptr),
1676 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
1679 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
1681 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
1682 (ins GR16:$val, i16mem:$ptr),
1683 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
1686 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
1688 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
1689 (ins GR32:$val, i32mem:$ptr),
1690 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
1693 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
1695 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
1696 (ins GR64:$val, i64mem:$ptr),
1697 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
1700 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
1705 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
1707 // Swap between registers.
1708 let SchedRW = [WriteALU] in {
1709 let Constraints = "$val = $dst" in {
1710 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1711 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1712 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1713 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1715 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1716 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1718 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1719 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1722 // Swap between EAX and other registers.
1723 let Uses = [AX], Defs = [AX] in
1724 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1725 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16;
1726 let Uses = [EAX], Defs = [EAX] in
1727 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1728 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1729 OpSize32, Requires<[Not64BitMode]>;
1730 let Uses = [EAX], Defs = [EAX] in
1731 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1732 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1733 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1734 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1735 OpSize32, Requires<[In64BitMode]>;
1736 let Uses = [RAX], Defs = [RAX] in
1737 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1738 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>;
1741 let SchedRW = [WriteALU] in {
1742 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1743 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1744 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1745 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1747 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1748 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1750 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1751 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1754 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1755 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1756 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1757 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1758 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1760 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1761 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1763 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1764 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1768 let SchedRW = [WriteALU] in {
1769 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1770 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1771 IIC_CMPXCHG_REG8>, TB;
1772 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1773 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1774 IIC_CMPXCHG_REG>, TB, OpSize16;
1775 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1776 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1777 IIC_CMPXCHG_REG>, TB, OpSize32;
1778 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1779 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1780 IIC_CMPXCHG_REG>, TB;
1783 let SchedRW = [WriteALULd, WriteRMW] in {
1784 let mayLoad = 1, mayStore = 1 in {
1785 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1786 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1787 IIC_CMPXCHG_MEM8>, TB;
1788 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1789 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1790 IIC_CMPXCHG_MEM>, TB, OpSize16;
1791 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1792 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1793 IIC_CMPXCHG_MEM>, TB, OpSize32;
1794 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1795 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1796 IIC_CMPXCHG_MEM>, TB;
1799 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1800 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1801 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1803 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1804 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1805 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1806 TB, Requires<[HasCmpxchg16b]>;
1810 // Lock instruction prefix
1811 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1813 // Rex64 instruction prefix
1814 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>,
1815 Requires<[In64BitMode]>;
1817 // Data16 instruction prefix
1818 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1820 // Repeat string operation instruction prefixes
1821 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1822 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1823 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1824 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1825 // Repeat while not equal (used with CMPS and SCAS)
1826 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1830 // String manipulation instructions
1831 let SchedRW = [WriteMicrocoded] in {
1832 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1833 let Defs = [AL,ESI], Uses = [ESI,EFLAGS] in
1834 def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src),
1835 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>;
1836 let Defs = [AX,ESI], Uses = [ESI,EFLAGS] in
1837 def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src),
1838 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16;
1839 let Defs = [EAX,ESI], Uses = [ESI,EFLAGS] in
1840 def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src),
1841 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32;
1842 let Defs = [RAX,ESI], Uses = [ESI,EFLAGS] in
1843 def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),
1844 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>;
1847 let SchedRW = [WriteSystem] in {
1848 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1849 let Defs = [ESI], Uses = [DX,ESI,EFLAGS] in {
1850 def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src),
1851 "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>;
1852 def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src),
1853 "outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16;
1854 def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src),
1855 "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32;
1858 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1859 let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in {
1860 def INSB : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins),
1861 "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
1862 def INSW : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins),
1863 "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
1864 def INSL : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins),
1865 "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32;
1869 // Flag instructions
1870 let SchedRW = [WriteALU] in {
1871 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1872 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1873 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1874 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1875 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1876 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1877 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1879 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1882 // Table lookup instructions
1883 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,
1886 let SchedRW = [WriteMicrocoded] in {
1887 // ASCII Adjust After Addition
1888 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1889 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1890 Requires<[Not64BitMode]>;
1892 // ASCII Adjust AX Before Division
1893 // sets AL, AH and EFLAGS and uses AL and AH
1894 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1895 "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>;
1897 // ASCII Adjust AX After Multiply
1898 // sets AL, AH and EFLAGS and uses AL
1899 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1900 "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>;
1902 // ASCII Adjust AL After Subtraction - sets
1903 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1904 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1905 Requires<[Not64BitMode]>;
1907 // Decimal Adjust AL after Addition
1908 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1909 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1910 Requires<[Not64BitMode]>;
1912 // Decimal Adjust AL after Subtraction
1913 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1914 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1915 Requires<[Not64BitMode]>;
1918 let SchedRW = [WriteSystem] in {
1919 // Check Array Index Against Bounds
1920 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1921 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,
1922 Requires<[Not64BitMode]>;
1923 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1924 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize32,
1925 Requires<[Not64BitMode]>;
1927 // Adjust RPL Field of Segment Selector
1928 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1929 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1930 Requires<[Not64BitMode]>;
1931 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1932 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1933 Requires<[Not64BitMode]>;
1936 //===----------------------------------------------------------------------===//
1937 // MOVBE Instructions
1939 let Predicates = [HasMOVBE] in {
1940 let SchedRW = [WriteALULd] in {
1941 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1942 "movbe{w}\t{$src, $dst|$dst, $src}",
1943 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1945 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1946 "movbe{l}\t{$src, $dst|$dst, $src}",
1947 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1949 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1950 "movbe{q}\t{$src, $dst|$dst, $src}",
1951 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
1954 let SchedRW = [WriteStore] in {
1955 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1956 "movbe{w}\t{$src, $dst|$dst, $src}",
1957 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1959 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1960 "movbe{l}\t{$src, $dst|$dst, $src}",
1961 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1963 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1964 "movbe{q}\t{$src, $dst|$dst, $src}",
1965 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
1970 //===----------------------------------------------------------------------===//
1971 // RDRAND Instruction
1973 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1974 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1976 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
1977 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1979 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, TB;
1980 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1982 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
1985 //===----------------------------------------------------------------------===//
1986 // RDSEED Instruction
1988 let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
1989 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
1991 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
1992 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
1994 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB;
1995 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
1997 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
2000 //===----------------------------------------------------------------------===//
2001 // LZCNT Instruction
2003 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
2004 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2005 "lzcnt{w}\t{$src, $dst|$dst, $src}",
2006 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
2008 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2009 "lzcnt{w}\t{$src, $dst|$dst, $src}",
2010 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
2011 (implicit EFLAGS)]>, XS, OpSize16;
2013 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2014 "lzcnt{l}\t{$src, $dst|$dst, $src}",
2015 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS,
2017 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2018 "lzcnt{l}\t{$src, $dst|$dst, $src}",
2019 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
2020 (implicit EFLAGS)]>, XS, OpSize32;
2022 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2023 "lzcnt{q}\t{$src, $dst|$dst, $src}",
2024 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
2026 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2027 "lzcnt{q}\t{$src, $dst|$dst, $src}",
2028 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
2029 (implicit EFLAGS)]>, XS;
2032 let Predicates = [HasLZCNT] in {
2033 def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
2034 (X86cmp GR16:$src, (i16 0))),
2035 (LZCNT16rr GR16:$src)>;
2036 def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
2037 (X86cmp GR32:$src, (i32 0))),
2038 (LZCNT32rr GR32:$src)>;
2039 def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
2040 (X86cmp GR64:$src, (i64 0))),
2041 (LZCNT64rr GR64:$src)>;
2042 def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_E_OR_NE),
2043 (X86cmp GR16:$src, (i16 0))),
2044 (LZCNT16rr GR16:$src)>;
2045 def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_E_OR_NE),
2046 (X86cmp GR32:$src, (i32 0))),
2047 (LZCNT32rr GR32:$src)>;
2048 def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_E_OR_NE),
2049 (X86cmp GR64:$src, (i64 0))),
2050 (LZCNT64rr GR64:$src)>;
2052 def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
2053 (X86cmp (loadi16 addr:$src), (i16 0))),
2054 (LZCNT16rm addr:$src)>;
2055 def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
2056 (X86cmp (loadi32 addr:$src), (i32 0))),
2057 (LZCNT32rm addr:$src)>;
2058 def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
2059 (X86cmp (loadi64 addr:$src), (i64 0))),
2060 (LZCNT64rm addr:$src)>;
2061 def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
2062 (X86cmp (loadi16 addr:$src), (i16 0))),
2063 (LZCNT16rm addr:$src)>;
2064 def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
2065 (X86cmp (loadi32 addr:$src), (i32 0))),
2066 (LZCNT32rm addr:$src)>;
2067 def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
2068 (X86cmp (loadi64 addr:$src), (i64 0))),
2069 (LZCNT64rm addr:$src)>;
2072 //===----------------------------------------------------------------------===//
2075 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2076 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2077 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2078 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
2080 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2081 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2082 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
2083 (implicit EFLAGS)]>, XS, OpSize16;
2085 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2086 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2087 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS,
2089 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2090 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2091 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
2092 (implicit EFLAGS)]>, XS, OpSize32;
2094 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2095 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2096 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
2098 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2099 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2100 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
2101 (implicit EFLAGS)]>, XS;
2104 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
2105 RegisterClass RC, X86MemOperand x86memop> {
2106 let hasSideEffects = 0 in {
2107 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
2108 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2111 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
2112 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2117 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2118 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>;
2119 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
2120 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>;
2121 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W;
2122 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>;
2123 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W;
2126 //===----------------------------------------------------------------------===//
2127 // Pattern fragments to auto generate BMI instructions.
2128 //===----------------------------------------------------------------------===//
2130 let Predicates = [HasBMI] in {
2131 // FIXME: patterns for the load versions are not implemented
2132 def : Pat<(and GR32:$src, (add GR32:$src, -1)),
2133 (BLSR32rr GR32:$src)>;
2134 def : Pat<(and GR64:$src, (add GR64:$src, -1)),
2135 (BLSR64rr GR64:$src)>;
2137 def : Pat<(xor GR32:$src, (add GR32:$src, -1)),
2138 (BLSMSK32rr GR32:$src)>;
2139 def : Pat<(xor GR64:$src, (add GR64:$src, -1)),
2140 (BLSMSK64rr GR64:$src)>;
2142 def : Pat<(and GR32:$src, (ineg GR32:$src)),
2143 (BLSI32rr GR32:$src)>;
2144 def : Pat<(and GR64:$src, (ineg GR64:$src)),
2145 (BLSI64rr GR64:$src)>;
2148 let Predicates = [HasBMI] in {
2149 def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
2150 (X86cmp GR16:$src, (i16 0))),
2151 (TZCNT16rr GR16:$src)>;
2152 def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
2153 (X86cmp GR32:$src, (i32 0))),
2154 (TZCNT32rr GR32:$src)>;
2155 def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
2156 (X86cmp GR64:$src, (i64 0))),
2157 (TZCNT64rr GR64:$src)>;
2158 def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_E_OR_NE),
2159 (X86cmp GR16:$src, (i16 0))),
2160 (TZCNT16rr GR16:$src)>;
2161 def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_E_OR_NE),
2162 (X86cmp GR32:$src, (i32 0))),
2163 (TZCNT32rr GR32:$src)>;
2164 def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_E_OR_NE),
2165 (X86cmp GR64:$src, (i64 0))),
2166 (TZCNT64rr GR64:$src)>;
2168 def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
2169 (X86cmp (loadi16 addr:$src), (i16 0))),
2170 (TZCNT16rm addr:$src)>;
2171 def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
2172 (X86cmp (loadi32 addr:$src), (i32 0))),
2173 (TZCNT32rm addr:$src)>;
2174 def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
2175 (X86cmp (loadi64 addr:$src), (i64 0))),
2176 (TZCNT64rm addr:$src)>;
2177 def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
2178 (X86cmp (loadi16 addr:$src), (i16 0))),
2179 (TZCNT16rm addr:$src)>;
2180 def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
2181 (X86cmp (loadi32 addr:$src), (i32 0))),
2182 (TZCNT32rm addr:$src)>;
2183 def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
2184 (X86cmp (loadi64 addr:$src), (i64 0))),
2185 (TZCNT64rm addr:$src)>;
2189 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
2190 X86MemOperand x86memop, Intrinsic Int,
2192 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2193 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2194 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
2196 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
2197 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2198 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
2199 (implicit EFLAGS)]>, T8PS, VEX_4VOp3;
2202 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2203 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
2204 int_x86_bmi_bextr_32, loadi32>;
2205 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
2206 int_x86_bmi_bextr_64, loadi64>, VEX_W;
2209 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
2210 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
2211 int_x86_bmi_bzhi_32, loadi32>;
2212 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
2213 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
2217 def CountTrailingOnes : SDNodeXForm<imm, [{
2218 // Count the trailing ones in the immediate.
2219 return getI8Imm(countTrailingOnes(N->getZExtValue()));
2222 def BZHIMask : ImmLeaf<i64, [{
2223 return isMask_64(Imm) && (countTrailingOnes<uint64_t>(Imm) > 32);
2226 let Predicates = [HasBMI2] in {
2227 def : Pat<(and GR64:$src, BZHIMask:$mask),
2228 (BZHI64rr GR64:$src,
2229 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2230 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>;
2232 def : Pat<(and GR32:$src, (add (shl 1, GR8:$lz), -1)),
2233 (BZHI32rr GR32:$src,
2234 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2236 def : Pat<(and (loadi32 addr:$src), (add (shl 1, GR8:$lz), -1)),
2237 (BZHI32rm addr:$src,
2238 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2240 def : Pat<(and GR64:$src, (add (shl 1, GR8:$lz), -1)),
2241 (BZHI64rr GR64:$src,
2242 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2244 def : Pat<(and (loadi64 addr:$src), (add (shl 1, GR8:$lz), -1)),
2245 (BZHI64rm addr:$src,
2246 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2249 let Predicates = [HasBMI] in {
2250 def : Pat<(X86bextr GR32:$src1, GR32:$src2),
2251 (BEXTR32rr GR32:$src1, GR32:$src2)>;
2252 def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2),
2253 (BEXTR32rm addr:$src1, GR32:$src2)>;
2254 def : Pat<(X86bextr GR64:$src1, GR64:$src2),
2255 (BEXTR64rr GR64:$src1, GR64:$src2)>;
2256 def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2),
2257 (BEXTR64rm addr:$src1, GR64:$src2)>;
2260 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
2261 X86MemOperand x86memop, Intrinsic Int,
2263 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2264 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2265 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
2267 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2268 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2269 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
2272 let Predicates = [HasBMI2] in {
2273 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
2274 int_x86_bmi_pdep_32, loadi32>, T8XD;
2275 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
2276 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
2277 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
2278 int_x86_bmi_pext_32, loadi32>, T8XS;
2279 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
2280 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
2283 //===----------------------------------------------------------------------===//
2286 let Predicates = [HasTBM], Defs = [EFLAGS] in {
2288 multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr,
2289 X86MemOperand x86memop, PatFrag ld_frag,
2290 Intrinsic Int, Operand immtype,
2291 SDPatternOperator immoperator> {
2292 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
2293 !strconcat(OpcodeStr,
2294 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2295 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>,
2297 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst),
2298 (ins x86memop:$src1, immtype:$cntl),
2299 !strconcat(OpcodeStr,
2300 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2301 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>,
2305 defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32,
2306 int_x86_tbm_bextri_u32, i32imm, imm>;
2307 let ImmT = Imm32S in
2308 defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64,
2309 int_x86_tbm_bextri_u64, i64i32imm,
2310 i64immSExt32>, VEX_W;
2312 multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem,
2313 RegisterClass RC, string OpcodeStr,
2314 X86MemOperand x86memop, PatFrag ld_frag> {
2315 let hasSideEffects = 0 in {
2316 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src),
2317 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2320 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src),
2321 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2326 multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr,
2327 Format FormReg, Format FormMem> {
2328 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem,
2330 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem,
2334 defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
2335 defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>;
2336 defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>;
2337 defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>;
2338 defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>;
2339 defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>;
2340 defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>;
2341 defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>;
2342 defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>;
2345 //===----------------------------------------------------------------------===//
2346 // Pattern fragments to auto generate TBM instructions.
2347 //===----------------------------------------------------------------------===//
2349 let Predicates = [HasTBM] in {
2350 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)),
2351 (BEXTRI32ri GR32:$src1, imm:$src2)>;
2352 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)),
2353 (BEXTRI32mi addr:$src1, imm:$src2)>;
2354 def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2),
2355 (BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>;
2356 def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2),
2357 (BEXTRI64mi addr:$src1, i64immSExt32:$src2)>;
2359 // FIXME: patterns for the load versions are not implemented
2360 def : Pat<(and GR32:$src, (add GR32:$src, 1)),
2361 (BLCFILL32rr GR32:$src)>;
2362 def : Pat<(and GR64:$src, (add GR64:$src, 1)),
2363 (BLCFILL64rr GR64:$src)>;
2365 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
2366 (BLCI32rr GR32:$src)>;
2367 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
2368 (BLCI64rr GR64:$src)>;
2370 // Extra patterns because opt can optimize the above patterns to this.
2371 def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
2372 (BLCI32rr GR32:$src)>;
2373 def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
2374 (BLCI64rr GR64:$src)>;
2376 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
2377 (BLCIC32rr GR32:$src)>;
2378 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),
2379 (BLCIC64rr GR64:$src)>;
2381 def : Pat<(xor GR32:$src, (add GR32:$src, 1)),
2382 (BLCMSK32rr GR32:$src)>;
2383 def : Pat<(xor GR64:$src, (add GR64:$src, 1)),
2384 (BLCMSK64rr GR64:$src)>;
2386 def : Pat<(or GR32:$src, (add GR32:$src, 1)),
2387 (BLCS32rr GR32:$src)>;
2388 def : Pat<(or GR64:$src, (add GR64:$src, 1)),
2389 (BLCS64rr GR64:$src)>;
2391 def : Pat<(or GR32:$src, (add GR32:$src, -1)),
2392 (BLSFILL32rr GR32:$src)>;
2393 def : Pat<(or GR64:$src, (add GR64:$src, -1)),
2394 (BLSFILL64rr GR64:$src)>;
2396 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
2397 (BLSIC32rr GR32:$src)>;
2398 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)),
2399 (BLSIC64rr GR64:$src)>;
2401 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)),
2402 (T1MSKC32rr GR32:$src)>;
2403 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)),
2404 (T1MSKC64rr GR64:$src)>;
2406 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)),
2407 (TZMSK32rr GR32:$src)>;
2408 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)),
2409 (TZMSK64rr GR64:$src)>;
2412 //===----------------------------------------------------------------------===//
2413 // Memory Instructions
2416 def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2417 "clflushopt\t$src", []>, PD;
2418 def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", []>, PD;
2419 def PCOMMIT : I<0xAE, MRM_F8, (outs), (ins), "pcommit", []>, PD;
2422 //===----------------------------------------------------------------------===//
2424 //===----------------------------------------------------------------------===//
2426 include "X86InstrArithmetic.td"
2427 include "X86InstrCMovSetCC.td"
2428 include "X86InstrExtension.td"
2429 include "X86InstrControl.td"
2430 include "X86InstrShiftRotate.td"
2432 // X87 Floating Point Stack.
2433 include "X86InstrFPStack.td"
2435 // SIMD support (SSE, MMX and AVX)
2436 include "X86InstrFragmentsSIMD.td"
2438 // FMA - Fused Multiply-Add support (requires FMA)
2439 include "X86InstrFMA.td"
2442 include "X86InstrXOP.td"
2444 // SSE, MMX and 3DNow! vector support.
2445 include "X86InstrSSE.td"
2446 include "X86InstrAVX512.td"
2447 include "X86InstrMMX.td"
2448 include "X86Instr3DNow.td"
2450 include "X86InstrVMX.td"
2451 include "X86InstrSVM.td"
2453 include "X86InstrTSX.td"
2454 include "X86InstrSGX.td"
2456 // System instructions.
2457 include "X86InstrSystem.td"
2459 // Compiler Pseudo Instructions and Pat Patterns
2460 include "X86InstrCompiler.td"
2462 //===----------------------------------------------------------------------===//
2463 // Assembler Mnemonic Aliases
2464 //===----------------------------------------------------------------------===//
2466 def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>;
2467 def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>;
2468 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;
2470 def : MnemonicAlias<"cbw", "cbtw", "att">;
2471 def : MnemonicAlias<"cwde", "cwtl", "att">;
2472 def : MnemonicAlias<"cwd", "cwtd", "att">;
2473 def : MnemonicAlias<"cdq", "cltd", "att">;
2474 def : MnemonicAlias<"cdqe", "cltq", "att">;
2475 def : MnemonicAlias<"cqo", "cqto", "att">;
2477 // In 64-bit mode lret maps to lretl; it is not ambiguous with lretq.
2478 def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>;
2479 def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>;
2481 def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>;
2482 def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>;
2484 def : MnemonicAlias<"loopz", "loope", "att">;
2485 def : MnemonicAlias<"loopnz", "loopne", "att">;
2487 def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>;
2488 def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>;
2489 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>;
2490 def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>;
2491 def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>;
2492 def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>;
2493 def : MnemonicAlias<"popfd", "popfl", "att">;
2495 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
2496 // all modes. However: "push (addr)" and "push $42" should default to
2497 // pushl/pushq depending on the current mode. Similar for "pop %bx"
2498 def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>;
2499 def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>;
2500 def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>;
2501 def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>;
2502 def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>;
2503 def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
2504 def : MnemonicAlias<"pushfd", "pushfl", "att">;
2506 def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>;
2507 def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>;
2508 def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>;
2509 def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>;
2510 def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>;
2511 def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>;
2513 def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>;
2514 def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>;
2515 def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>;
2516 def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>;
2518 def : MnemonicAlias<"repe", "rep", "att">;
2519 def : MnemonicAlias<"repz", "rep", "att">;
2520 def : MnemonicAlias<"repnz", "repne", "att">;
2522 def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>;
2523 def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>;
2524 def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>;
2526 def : MnemonicAlias<"salb", "shlb", "att">;
2527 def : MnemonicAlias<"salw", "shlw", "att">;
2528 def : MnemonicAlias<"sall", "shll", "att">;
2529 def : MnemonicAlias<"salq", "shlq", "att">;
2531 def : MnemonicAlias<"smovb", "movsb", "att">;
2532 def : MnemonicAlias<"smovw", "movsw", "att">;
2533 def : MnemonicAlias<"smovl", "movsl", "att">;
2534 def : MnemonicAlias<"smovq", "movsq", "att">;
2536 def : MnemonicAlias<"ud2a", "ud2", "att">;
2537 def : MnemonicAlias<"verrw", "verr", "att">;
2539 // System instruction aliases.
2540 def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>;
2541 def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>;
2542 def : MnemonicAlias<"sysret", "sysretl", "att">;
2543 def : MnemonicAlias<"sysexit", "sysexitl", "att">;
2545 def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>;
2546 def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>;
2547 def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>;
2548 def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>;
2549 def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>;
2550 def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>;
2551 def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>;
2552 def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>;
2553 def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>;
2554 def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>;
2555 def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>;
2556 def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>;
2559 // Floating point stack aliases.
2560 def : MnemonicAlias<"fcmovz", "fcmove", "att">;
2561 def : MnemonicAlias<"fcmova", "fcmovnbe", "att">;
2562 def : MnemonicAlias<"fcmovnae", "fcmovb", "att">;
2563 def : MnemonicAlias<"fcmovna", "fcmovbe", "att">;
2564 def : MnemonicAlias<"fcmovae", "fcmovnb", "att">;
2565 def : MnemonicAlias<"fcomip", "fcompi", "att">;
2566 def : MnemonicAlias<"fildq", "fildll", "att">;
2567 def : MnemonicAlias<"fistpq", "fistpll", "att">;
2568 def : MnemonicAlias<"fisttpq", "fisttpll", "att">;
2569 def : MnemonicAlias<"fldcww", "fldcw", "att">;
2570 def : MnemonicAlias<"fnstcww", "fnstcw", "att">;
2571 def : MnemonicAlias<"fnstsww", "fnstsw", "att">;
2572 def : MnemonicAlias<"fucomip", "fucompi", "att">;
2573 def : MnemonicAlias<"fwait", "wait">;
2575 def : MnemonicAlias<"fxsaveq", "fxsave64", "att">;
2576 def : MnemonicAlias<"fxrstorq", "fxrstor64", "att">;
2577 def : MnemonicAlias<"xsaveq", "xsave64", "att">;
2578 def : MnemonicAlias<"xrstorq", "xrstor64", "att">;
2579 def : MnemonicAlias<"xsaveoptq", "xsaveopt64", "att">;
2582 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond,
2584 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
2585 !strconcat(Prefix, NewCond, Suffix), VariantName>;
2587 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
2588 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
2589 /// example "setz" -> "sete".
2590 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix,
2592 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb
2593 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete
2594 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe
2595 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae
2596 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae
2597 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle
2598 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge
2599 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne
2600 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp
2601 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp
2603 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb
2604 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta
2605 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl
2606 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg
2609 // Aliases for set<CC>
2610 defm : IntegerCondCodeMnemonicAlias<"set", "">;
2611 // Aliases for j<CC>
2612 defm : IntegerCondCodeMnemonicAlias<"j", "">;
2613 // Aliases for cmov<CC>{w,l,q}
2614 defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">;
2615 defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">;
2616 defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">;
2617 // No size suffix for intel-style asm.
2618 defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">;
2621 //===----------------------------------------------------------------------===//
2622 // Assembler Instruction Aliases
2623 //===----------------------------------------------------------------------===//
2625 // aad/aam default to base 10 if no operand is specified.
2626 def : InstAlias<"aad", (AAD8i8 10)>;
2627 def : InstAlias<"aam", (AAM8i8 10)>;
2629 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
2630 // Likewise for btc/btr/bts.
2631 def : InstAlias<"bt {$imm, $mem|$mem, $imm}",
2632 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2633 def : InstAlias<"btc {$imm, $mem|$mem, $imm}",
2634 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2635 def : InstAlias<"btr {$imm, $mem|$mem, $imm}",
2636 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2637 def : InstAlias<"bts {$imm, $mem|$mem, $imm}",
2638 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2641 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>;
2642 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>;
2643 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>;
2644 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;
2646 // lods aliases. Accept the destination being omitted because it's implicit
2647 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2648 // in the destination.
2649 def : InstAlias<"lodsb $src", (LODSB srcidx8:$src), 0>;
2650 def : InstAlias<"lodsw $src", (LODSW srcidx16:$src), 0>;
2651 def : InstAlias<"lods{l|d} $src", (LODSL srcidx32:$src), 0>;
2652 def : InstAlias<"lodsq $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2653 def : InstAlias<"lods {$src, %al|al, $src}", (LODSB srcidx8:$src), 0>;
2654 def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>;
2655 def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>;
2656 def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2658 // stos aliases. Accept the source being omitted because it's implicit in
2659 // the mnemonic, or the mnemonic suffix being omitted because it's implicit
2661 def : InstAlias<"stosb $dst", (STOSB dstidx8:$dst), 0>;
2662 def : InstAlias<"stosw $dst", (STOSW dstidx16:$dst), 0>;
2663 def : InstAlias<"stos{l|d} $dst", (STOSL dstidx32:$dst), 0>;
2664 def : InstAlias<"stosq $dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2665 def : InstAlias<"stos {%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>;
2666 def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>;
2667 def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>;
2668 def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2670 // scas aliases. Accept the destination being omitted because it's implicit
2671 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2672 // in the destination.
2673 def : InstAlias<"scasb $dst", (SCASB dstidx8:$dst), 0>;
2674 def : InstAlias<"scasw $dst", (SCASW dstidx16:$dst), 0>;
2675 def : InstAlias<"scas{l|d} $dst", (SCASL dstidx32:$dst), 0>;
2676 def : InstAlias<"scasq $dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2677 def : InstAlias<"scas {$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>;
2678 def : InstAlias<"scas {$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>;
2679 def : InstAlias<"scas {$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>;
2680 def : InstAlias<"scas {$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2682 // div and idiv aliases for explicit A register.
2683 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
2684 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
2685 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>;
2686 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>;
2687 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>;
2688 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>;
2689 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>;
2690 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>;
2691 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>;
2692 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>;
2693 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>;
2694 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>;
2695 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>;
2696 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>;
2697 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;
2698 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;
2702 // Various unary fpstack operations default to operating on on ST1.
2703 // For example, "fxch" -> "fxch %st(1)"
2704 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
2705 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
2706 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
2707 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
2708 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
2709 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
2710 def : InstAlias<"fxch", (XCH_F ST1), 0>;
2711 def : InstAlias<"fcom", (COM_FST0r ST1), 0>;
2712 def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>;
2713 def : InstAlias<"fcomi", (COM_FIr ST1), 0>;
2714 def : InstAlias<"fcompi", (COM_FIPr ST1), 0>;
2715 def : InstAlias<"fucom", (UCOM_Fr ST1), 0>;
2716 def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>;
2717 def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>;
2718 def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>;
2720 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
2721 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
2722 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
2724 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
2725 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"),
2726 (Inst RST:$op), EmitAlias>;
2727 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"),
2728 (Inst ST0), EmitAlias>;
2731 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
2732 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
2733 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
2734 defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>;
2735 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
2736 defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>;
2737 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
2738 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
2739 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
2740 defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>;
2741 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
2742 defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>;
2743 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
2744 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
2745 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
2746 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
2749 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
2750 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
2751 // solely because gas supports it.
2752 def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>;
2753 def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>;
2754 def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>;
2755 def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>;
2756 def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>;
2757 def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>;
2759 // We accept "fnstsw %eax" even though it only writes %ax.
2760 def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>;
2761 def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>;
2762 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
2764 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
2765 // this is compatible with what GAS does.
2766 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2767 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2768 def : InstAlias<"lcall {*}$dst", (FARCALL32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2769 def : InstAlias<"ljmp {*}$dst", (FARJMP32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2770 def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2771 def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2772 def : InstAlias<"lcall {*}$dst", (FARCALL16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2773 def : InstAlias<"ljmp {*}$dst", (FARJMP16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2775 def : InstAlias<"call {*}$dst", (CALL64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
2776 def : InstAlias<"jmp {*}$dst", (JMP64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
2777 def : InstAlias<"call {*}$dst", (CALL32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
2778 def : InstAlias<"jmp {*}$dst", (JMP32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
2779 def : InstAlias<"call {*}$dst", (CALL16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2780 def : InstAlias<"jmp {*}$dst", (JMP16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2783 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
2784 def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>;
2785 def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>;
2786 def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>;
2787 def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>;
2788 def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>;
2789 def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>;
2791 // inb %dx -> inb %al, %dx
2792 def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;
2793 def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;
2794 def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>;
2795 def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>;
2796 def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>;
2797 def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>;
2800 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
2801 def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2802 def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2803 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2804 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2805 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
2806 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
2807 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2808 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2810 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
2811 // the move. All segment/mem forms are equivalent, this has the shortest
2813 def : InstAlias<"mov {$mem, $seg|$seg, $mem}", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem), 0>;
2814 def : InstAlias<"mov {$seg, $mem|$mem, $seg}", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg), 0>;
2816 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
2817 def : InstAlias<"movq {$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>;
2819 // Match 'movq GR64, MMX' as an alias for movd.
2820 def : InstAlias<"movq {$src, $dst|$dst, $src}",
2821 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
2822 def : InstAlias<"movq {$src, $dst|$dst, $src}",
2823 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
2826 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
2827 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
2828 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
2829 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
2830 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
2831 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
2832 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
2835 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
2836 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
2837 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
2838 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
2839 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
2840 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
2841 // Note: No GR32->GR64 movzx form.
2843 // outb %dx -> outb %al, %dx
2844 def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>;
2845 def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>;
2846 def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>;
2847 def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>;
2848 def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>;
2849 def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>;
2851 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
2852 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
2853 // errors, since its encoding is the most compact.
2854 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>;
2856 // shld/shrd op,op -> shld op, op, CL
2857 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;
2858 def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>;
2859 def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>;
2860 def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>;
2861 def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>;
2862 def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>;
2864 def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>;
2865 def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>;
2866 def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>;
2867 def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>;
2868 def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>;
2869 def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>;
2871 /* FIXME: This is disabled because the asm matcher is currently incapable of
2872 * matching a fixed immediate like $1.
2873 // "shl X, $1" is an alias for "shl X".
2874 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
2875 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2876 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
2877 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2878 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
2879 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2880 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
2881 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2882 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
2883 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2884 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
2885 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2886 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
2887 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2888 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
2889 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2890 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2893 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2894 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
2895 defm : ShiftRotateByOneAlias<"rol", "ROL">;
2896 defm : ShiftRotateByOneAlias<"ror", "ROR">;
2899 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
2900 def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}",
2901 (TEST8rm GR8 :$val, i8mem :$mem), 0>;
2902 def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}",
2903 (TEST16rm GR16:$val, i16mem:$mem), 0>;
2904 def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}",
2905 (TEST32rm GR32:$val, i32mem:$mem), 0>;
2906 def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}",
2907 (TEST64rm GR64:$val, i64mem:$mem), 0>;
2909 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
2910 def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}",
2911 (XCHG8rm GR8 :$val, i8mem :$mem), 0>;
2912 def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}",
2913 (XCHG16rm GR16:$val, i16mem:$mem), 0>;
2914 def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}",
2915 (XCHG32rm GR32:$val, i32mem:$mem), 0>;
2916 def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}",
2917 (XCHG64rm GR64:$val, i64mem:$mem), 0>;
2919 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
2920 def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>;
2921 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
2922 (XCHG32ar GR32:$src), 0>, Requires<[Not64BitMode]>;
2923 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
2924 (XCHG32ar64 GR32_NOAX:$src), 0>, Requires<[In64BitMode]>;
2925 def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>;