1 //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
29 def SDTX86Cmov_NEW : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 def SDTX86BrCond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>;
35 def SDTX86BrCond_NEW : SDTypeProfile<0, 3,
36 [SDTCisVT<0, OtherVT>,
37 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
39 def SDTX86SetCC : SDTypeProfile<1, 1,
40 [SDTCisVT<0, i8>, SDTCisVT<1, i8>]>;
41 def SDTX86SetCC_NEW : SDTypeProfile<1, 2,
43 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86Ret : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>;
47 def SDT_X86CallSeqStart : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
48 def SDT_X86CallSeqEnd : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>,
51 def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
53 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
55 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
57 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
59 def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
63 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
66 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
68 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest,
69 [SDNPHasChain, SDNPOutFlag]>;
70 def X86cmp_new : SDNode<"X86ISD::CMP_NEW" , SDTX86CmpTest>;
72 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov,
73 [SDNPInFlag, SDNPOutFlag]>;
74 def X86cmov_new: SDNode<"X86ISD::CMOV_NEW", SDTX86Cmov_NEW>;
75 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
76 [SDNPHasChain, SDNPInFlag]>;
77 def X86brcond_new : SDNode<"X86ISD::BRCOND_NEW", SDTX86BrCond_NEW,
79 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC,
80 [SDNPInFlag, SDNPOutFlag]>;
81 def X86setcc_new : SDNode<"X86ISD::SETCC_NEW", SDTX86SetCC_NEW>;
83 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
84 [SDNPHasChain, SDNPOptInFlag]>;
86 def X86callseq_start :
87 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
88 [SDNPHasChain, SDNPOutFlag]>;
90 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
91 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
93 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
94 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
96 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
97 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
99 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
100 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
101 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
102 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
104 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
105 [SDNPHasChain, SDNPOutFlag]>;
107 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
108 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
110 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
111 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
112 def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
114 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
118 //===----------------------------------------------------------------------===//
119 // X86 Operand Definitions.
122 // *mem - Operand definitions for the funky X86 addressing mode operands.
124 class X86MemOperand<string printMethod> : Operand<iPTR> {
125 let PrintMethod = printMethod;
126 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
129 def i8mem : X86MemOperand<"printi8mem">;
130 def i16mem : X86MemOperand<"printi16mem">;
131 def i32mem : X86MemOperand<"printi32mem">;
132 def i64mem : X86MemOperand<"printi64mem">;
133 def i128mem : X86MemOperand<"printi128mem">;
134 def f32mem : X86MemOperand<"printf32mem">;
135 def f64mem : X86MemOperand<"printf64mem">;
136 def f80mem : X86MemOperand<"printf80mem">;
137 def f128mem : X86MemOperand<"printf128mem">;
139 def lea32mem : Operand<i32> {
140 let PrintMethod = "printi32mem";
141 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
144 def SSECC : Operand<i8> {
145 let PrintMethod = "printSSECC";
148 def piclabel: Operand<i32> {
149 let PrintMethod = "printPICLabel";
152 // A couple of more descriptive operand definitions.
153 // 16-bits but only 8 bits are significant.
154 def i16i8imm : Operand<i16>;
155 // 32-bits but only 8 bits are significant.
156 def i32i8imm : Operand<i32>;
158 // Branch targets have OtherVT type.
159 def brtarget : Operand<OtherVT>;
161 //===----------------------------------------------------------------------===//
162 // X86 Complex Pattern Definitions.
165 // Define X86 specific addressing mode.
166 def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
167 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
168 [add, mul, shl, or, frameindex], []>;
170 //===----------------------------------------------------------------------===//
171 // X86 Instruction Predicate Definitions.
172 def HasMMX : Predicate<"Subtarget->hasMMX()">;
173 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
174 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
175 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
176 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
177 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
178 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
179 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
180 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
181 def HasLow4G : Predicate<"Subtarget->hasLow4GUserSpaceAddress()">;
182 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
183 def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
184 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
186 //===----------------------------------------------------------------------===//
187 // X86 Instruction Format Definitions.
190 include "X86InstrFormats.td"
192 //===----------------------------------------------------------------------===//
193 // Pattern fragments...
196 // X86 specific condition code. These correspond to CondCode in
197 // X86InstrInfo.h. They must be kept in synch.
198 def X86_COND_A : PatLeaf<(i8 0)>;
199 def X86_COND_AE : PatLeaf<(i8 1)>;
200 def X86_COND_B : PatLeaf<(i8 2)>;
201 def X86_COND_BE : PatLeaf<(i8 3)>;
202 def X86_COND_E : PatLeaf<(i8 4)>;
203 def X86_COND_G : PatLeaf<(i8 5)>;
204 def X86_COND_GE : PatLeaf<(i8 6)>;
205 def X86_COND_L : PatLeaf<(i8 7)>;
206 def X86_COND_LE : PatLeaf<(i8 8)>;
207 def X86_COND_NE : PatLeaf<(i8 9)>;
208 def X86_COND_NO : PatLeaf<(i8 10)>;
209 def X86_COND_NP : PatLeaf<(i8 11)>;
210 def X86_COND_NS : PatLeaf<(i8 12)>;
211 def X86_COND_O : PatLeaf<(i8 13)>;
212 def X86_COND_P : PatLeaf<(i8 14)>;
213 def X86_COND_S : PatLeaf<(i8 15)>;
215 def i16immSExt8 : PatLeaf<(i16 imm), [{
216 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
217 // sign extended field.
218 return (int16_t)N->getValue() == (int8_t)N->getValue();
221 def i32immSExt8 : PatLeaf<(i32 imm), [{
222 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
223 // sign extended field.
224 return (int32_t)N->getValue() == (int8_t)N->getValue();
227 // Helper fragments for loads.
228 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
229 def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>;
230 def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>;
231 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
233 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
234 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
235 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
237 def sextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (sextloadi1 node:$ptr))>;
238 def sextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (sextloadi1 node:$ptr))>;
239 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
240 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
241 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
243 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
244 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
245 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
246 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
247 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
248 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
250 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
251 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
252 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
253 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
254 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
255 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
257 //===----------------------------------------------------------------------===//
258 // Instruction list...
261 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
262 // a stack adjustment and the codegen must know that they may modify the stack
263 // pointer before prolog-epilog rewriting occurs.
264 let Defs = [ESP], Uses = [ESP] in {
265 def ADJCALLSTACKDOWN : I<0, Pseudo, (outs), (ins i32imm:$amt), "#ADJCALLSTACKDOWN",
266 [(X86callseq_start imm:$amt)]>;
267 def ADJCALLSTACKUP : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
269 [(X86callseq_end imm:$amt1, imm:$amt2)]>;
271 def IMPLICIT_USE : I<0, Pseudo, (outs), (ins variable_ops),
272 "#IMPLICIT_USE", []>;
273 def IMPLICIT_DEF : I<0, Pseudo, (outs variable_ops), (ins),
274 "#IMPLICIT_DEF", []>;
275 def IMPLICIT_DEF_GR8 : I<0, Pseudo, (outs GR8:$dst), (ins),
276 "#IMPLICIT_DEF $dst",
277 [(set GR8:$dst, (undef))]>;
278 def IMPLICIT_DEF_GR16 : I<0, Pseudo, (outs GR16:$dst), (ins),
279 "#IMPLICIT_DEF $dst",
280 [(set GR16:$dst, (undef))]>;
281 def IMPLICIT_DEF_GR32 : I<0, Pseudo, (outs GR32:$dst), (ins),
282 "#IMPLICIT_DEF $dst",
283 [(set GR32:$dst, (undef))]>;
286 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
289 //===----------------------------------------------------------------------===//
290 // Control Flow Instructions...
293 // Return instructions.
294 let isTerminator = 1, isReturn = 1, isBarrier = 1,
296 def RET : I<0xC3, RawFrm, (outs), (ins), "ret", [(X86retflag 0)]>;
297 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), "ret\t$amt",
298 [(X86retflag imm:$amt)]>;
301 // All branches are RawFrm, Void, Branch, and Terminators
302 let isBranch = 1, isTerminator = 1 in
303 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
304 I<opcode, RawFrm, (outs), ins, asm, pattern>;
307 let isBranch = 1, isBarrier = 1 in
308 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
310 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
311 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
312 [(brind GR32:$dst)]>;
313 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
314 [(brind (loadi32 addr:$dst))]>;
317 // Conditional branches
318 let Uses = [EFLAGS] in {
319 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
320 [(X86brcond bb:$dst, X86_COND_E)]>, TB;
321 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
322 [(X86brcond bb:$dst, X86_COND_NE)]>, TB;
323 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
324 [(X86brcond bb:$dst, X86_COND_L)]>, TB;
325 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
326 [(X86brcond bb:$dst, X86_COND_LE)]>, TB;
327 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
328 [(X86brcond bb:$dst, X86_COND_G)]>, TB;
329 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
330 [(X86brcond bb:$dst, X86_COND_GE)]>, TB;
332 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
333 [(X86brcond bb:$dst, X86_COND_B)]>, TB;
334 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
335 [(X86brcond bb:$dst, X86_COND_BE)]>, TB;
336 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
337 [(X86brcond bb:$dst, X86_COND_A)]>, TB;
338 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
339 [(X86brcond bb:$dst, X86_COND_AE)]>, TB;
341 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
342 [(X86brcond bb:$dst, X86_COND_S)]>, TB;
343 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
344 [(X86brcond bb:$dst, X86_COND_NS)]>, TB;
345 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
346 [(X86brcond bb:$dst, X86_COND_P)]>, TB;
347 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
348 [(X86brcond bb:$dst, X86_COND_NP)]>, TB;
349 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
350 [(X86brcond bb:$dst, X86_COND_O)]>, TB;
351 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
352 [(X86brcond bb:$dst, X86_COND_NO)]>, TB;
355 let Uses = [EFLAGS] in {
356 def NEW_JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
357 [(X86brcond_new bb:$dst, X86_COND_E, EFLAGS)]>, TB;
358 def NEW_JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
359 [(X86brcond_new bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
360 def NEW_JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
361 [(X86brcond_new bb:$dst, X86_COND_L, EFLAGS)]>, TB;
362 def NEW_JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
363 [(X86brcond_new bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
364 def NEW_JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
365 [(X86brcond_new bb:$dst, X86_COND_G, EFLAGS)]>, TB;
366 def NEW_JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
367 [(X86brcond_new bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
369 def NEW_JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
370 [(X86brcond_new bb:$dst, X86_COND_B, EFLAGS)]>, TB;
371 def NEW_JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
372 [(X86brcond_new bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
373 def NEW_JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
374 [(X86brcond_new bb:$dst, X86_COND_A, EFLAGS)]>, TB;
375 def NEW_JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
376 [(X86brcond_new bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
378 def NEW_JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
379 [(X86brcond_new bb:$dst, X86_COND_S, EFLAGS)]>, TB;
380 def NEW_JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
381 [(X86brcond_new bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
382 def NEW_JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
383 [(X86brcond_new bb:$dst, X86_COND_P, EFLAGS)]>, TB;
384 def NEW_JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
385 [(X86brcond_new bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
386 def NEW_JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
387 [(X86brcond_new bb:$dst, X86_COND_O, EFLAGS)]>, TB;
388 def NEW_JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
389 [(X86brcond_new bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
392 //===----------------------------------------------------------------------===//
393 // Call Instructions...
396 // All calls clobber the non-callee saved registers...
397 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
398 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
399 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, EFLAGS] in {
400 def CALLpcrel32 : I<0xE8, RawFrm, (outs), (ins i32imm:$dst, variable_ops),
401 "call\t${dst:call}", []>;
402 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
403 "call\t{*}$dst", [(X86call GR32:$dst)]>;
404 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
405 "call\t{*}$dst", []>;
409 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
410 def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAIL CALL",
412 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
413 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp\t{*}$dst # TAIL CALL",
415 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
416 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
417 "jmp\t{*}$dst # TAIL CALL", []>;
419 //===----------------------------------------------------------------------===//
420 // Miscellaneous Instructions...
422 let Defs = [EBP, ESP], Uses = [EBP, ESP] in
423 def LEAVE : I<0xC9, RawFrm,
424 (outs), (ins), "leave", []>;
426 let Defs = [ESP], Uses = [ESP] in {
427 def POP32r : I<0x58, AddRegFrm,
428 (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
430 def PUSH32r : I<0x50, AddRegFrm,
431 (outs), (ins GR32:$reg), "push{l}\t$reg", []>;
434 def MovePCtoStack : I<0, Pseudo, (outs), (ins piclabel:$label),
437 let isTwoAddress = 1 in // GR32 = bswap GR32
438 def BSWAP32r : I<0xC8, AddRegFrm,
439 (outs GR32:$dst), (ins GR32:$src),
441 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
443 // FIXME: Model xchg* as two address instructions?
444 def XCHG8rr : I<0x86, MRMDestReg, // xchg GR8, GR8
445 (outs), (ins GR8:$src1, GR8:$src2),
446 "xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
447 def XCHG16rr : I<0x87, MRMDestReg, // xchg GR16, GR16
448 (outs), (ins GR16:$src1, GR16:$src2),
449 "xchg{w}\t{$src2|$src1}, {$src1|$src2}", []>, OpSize;
450 def XCHG32rr : I<0x87, MRMDestReg, // xchg GR32, GR32
451 (outs), (ins GR32:$src1, GR32:$src2),
452 "xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
454 def XCHG8mr : I<0x86, MRMDestMem,
455 (outs), (ins i8mem:$src1, GR8:$src2),
456 "xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
457 def XCHG16mr : I<0x87, MRMDestMem,
458 (outs), (ins i16mem:$src1, GR16:$src2),
459 "xchg{w}\t{$src2|$src1}, {$src1|$src2}", []>, OpSize;
460 def XCHG32mr : I<0x87, MRMDestMem,
461 (outs), (ins i32mem:$src1, GR32:$src2),
462 "xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
463 def XCHG8rm : I<0x86, MRMSrcMem,
464 (outs), (ins GR8:$src1, i8mem:$src2),
465 "xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
466 def XCHG16rm : I<0x87, MRMSrcMem,
467 (outs), (ins GR16:$src1, i16mem:$src2),
468 "xchg{w}\t{$src2|$src1}, {$src1|$src2}", []>, OpSize;
469 def XCHG32rm : I<0x87, MRMSrcMem,
470 (outs), (ins GR32:$src1, i32mem:$src2),
471 "xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
473 def LEA16r : I<0x8D, MRMSrcMem,
474 (outs GR16:$dst), (ins i32mem:$src),
475 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
476 def LEA32r : I<0x8D, MRMSrcMem,
477 (outs GR32:$dst), (ins lea32mem:$src),
478 "lea{l}\t{$src|$dst}, {$dst|$src}",
479 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
481 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
482 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
483 [(X86rep_movs i8)]>, REP;
484 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
485 [(X86rep_movs i16)]>, REP, OpSize;
486 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
487 [(X86rep_movs i32)]>, REP;
490 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
491 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
492 [(X86rep_stos i8)]>, REP;
493 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
494 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
495 [(X86rep_stos i16)]>, REP, OpSize;
496 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
497 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
498 [(X86rep_stos i32)]>, REP;
500 let Defs = [RAX, RDX] in
501 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
504 //===----------------------------------------------------------------------===//
505 // Input/Output Instructions...
507 let Defs = [AL], Uses = [DX] in
508 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
509 "in{b}\t{%dx, %al|%AL, %DX}", []>;
510 let Defs = [AX], Uses = [DX] in
511 def IN16rr : I<0xED, RawFrm, (outs), (ins),
512 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
513 let Defs = [EAX], Uses = [DX] in
514 def IN32rr : I<0xED, RawFrm, (outs), (ins),
515 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
518 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
519 "in{b}\t{$port, %al|%AL, $port}", []>;
521 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
522 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
524 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
525 "in{l}\t{$port, %eax|%EAX, $port}", []>;
527 let Uses = [DX, AL] in
528 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
529 "out{b}\t{%al, %dx|%DX, %AL}", []>;
530 let Uses = [DX, AX] in
531 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
532 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
533 let Uses = [DX, EAX] in
534 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
535 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
538 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
539 "out{b}\t{%al, $port|$port, %AL}", []>;
541 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
542 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
544 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
545 "out{l}\t{%eax, $port|$port, %EAX}", []>;
547 //===----------------------------------------------------------------------===//
548 // Move Instructions...
550 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
551 "mov{b}\t{$src, $dst|$dst, $src}", []>;
552 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
553 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
554 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
555 "mov{l}\t{$src, $dst|$dst, $src}", []>;
556 let isReMaterializable = 1 in {
557 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
558 "mov{b}\t{$src, $dst|$dst, $src}",
559 [(set GR8:$dst, imm:$src)]>;
560 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
561 "mov{w}\t{$src, $dst|$dst, $src}",
562 [(set GR16:$dst, imm:$src)]>, OpSize;
563 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
564 "mov{l}\t{$src, $dst|$dst, $src}",
565 [(set GR32:$dst, imm:$src)]>;
567 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
568 "mov{b}\t{$src, $dst|$dst, $src}",
569 [(store (i8 imm:$src), addr:$dst)]>;
570 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
571 "mov{w}\t{$src, $dst|$dst, $src}",
572 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
573 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
574 "mov{l}\t{$src, $dst|$dst, $src}",
575 [(store (i32 imm:$src), addr:$dst)]>;
578 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
579 "mov{b}\t{$src, $dst|$dst, $src}",
580 [(set GR8:$dst, (load addr:$src))]>;
581 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
582 "mov{w}\t{$src, $dst|$dst, $src}",
583 [(set GR16:$dst, (load addr:$src))]>, OpSize;
584 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
585 "mov{l}\t{$src, $dst|$dst, $src}",
586 [(set GR32:$dst, (load addr:$src))]>;
589 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
590 "mov{b}\t{$src, $dst|$dst, $src}",
591 [(store GR8:$src, addr:$dst)]>;
592 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
593 "mov{w}\t{$src, $dst|$dst, $src}",
594 [(store GR16:$src, addr:$dst)]>, OpSize;
595 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
596 "mov{l}\t{$src, $dst|$dst, $src}",
597 [(store GR32:$src, addr:$dst)]>;
599 //===----------------------------------------------------------------------===//
600 // Fixed-Register Multiplication and Division Instructions...
603 // Extra precision multiplication
604 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
605 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
606 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
607 // This probably ought to be moved to a def : Pat<> if the
608 // syntax can be accepted.
609 [(set AL, (mul AL, GR8:$src))]>; // AL,AH = AL*GR8
610 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
611 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>,
612 OpSize; // AX,DX = AX*GR16
613 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
614 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l}\t$src", []>;
615 // EAX,EDX = EAX*GR32
616 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
617 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
619 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
620 // This probably ought to be moved to a def : Pat<> if the
621 // syntax can be accepted.
622 [(set AL, (mul AL, (loadi8 addr:$src)))]>; // AL,AH = AL*[mem8]
623 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
624 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
625 "mul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
626 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
627 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
628 "mul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
630 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
631 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
633 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
634 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
635 OpSize; // AX,DX = AX*GR16
636 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
637 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
638 // EAX,EDX = EAX*GR32
639 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
640 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
641 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
642 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
643 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
644 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
645 let Defs = [EAX,EDX], Uses = [EAX] in
646 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
647 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
649 // unsigned division/remainder
650 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
651 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
653 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
654 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
655 "div{w}\t$src", []>, OpSize;
656 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
657 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
659 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
660 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
662 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
663 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
664 "div{w}\t$src", []>, OpSize;
665 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
666 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
669 // Signed division/remainder.
670 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
671 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
672 "idiv{b}\t$src", []>;
673 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
674 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
675 "idiv{w}\t$src", []>, OpSize;
676 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
677 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
678 "idiv{l}\t$src", []>;
679 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
680 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
681 "idiv{b}\t$src", []>;
682 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
683 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
684 "idiv{w}\t$src", []>, OpSize;
685 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
686 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
687 "idiv{l}\t$src", []>;
690 //===----------------------------------------------------------------------===//
691 // Two address Instructions...
693 let isTwoAddress = 1 in {
696 let Uses = [EFLAGS] in {
697 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
698 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
699 "cmovb\t{$src2, $dst|$dst, $src2}",
700 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
703 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
704 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
705 "cmovb\t{$src2, $dst|$dst, $src2}",
706 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
709 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
710 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
711 "cmovb\t{$src2, $dst|$dst, $src2}",
712 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
715 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
716 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
717 "cmovb\t{$src2, $dst|$dst, $src2}",
718 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
722 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
723 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
724 "cmovae\t{$src2, $dst|$dst, $src2}",
725 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
728 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
729 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
730 "cmovae\t{$src2, $dst|$dst, $src2}",
731 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
734 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
735 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
736 "cmovae\t{$src2, $dst|$dst, $src2}",
737 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
740 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
741 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
742 "cmovae\t{$src2, $dst|$dst, $src2}",
743 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
747 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
748 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
749 "cmove\t{$src2, $dst|$dst, $src2}",
750 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
753 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
754 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
755 "cmove\t{$src2, $dst|$dst, $src2}",
756 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
759 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
760 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
761 "cmove\t{$src2, $dst|$dst, $src2}",
762 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
765 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
766 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
767 "cmove\t{$src2, $dst|$dst, $src2}",
768 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
772 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
773 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
774 "cmovne\t{$src2, $dst|$dst, $src2}",
775 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
778 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
779 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
780 "cmovne\t{$src2, $dst|$dst, $src2}",
781 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
784 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
785 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
786 "cmovne\t{$src2, $dst|$dst, $src2}",
787 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
790 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
791 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
792 "cmovne\t{$src2, $dst|$dst, $src2}",
793 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
797 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
798 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
799 "cmovbe\t{$src2, $dst|$dst, $src2}",
800 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
803 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
804 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
805 "cmovbe\t{$src2, $dst|$dst, $src2}",
806 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
809 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
810 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
811 "cmovbe\t{$src2, $dst|$dst, $src2}",
812 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
815 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
816 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
817 "cmovbe\t{$src2, $dst|$dst, $src2}",
818 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
822 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
823 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
824 "cmova\t{$src2, $dst|$dst, $src2}",
825 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
828 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
829 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
830 "cmova\t{$src2, $dst|$dst, $src2}",
831 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
834 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
835 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
836 "cmova\t{$src2, $dst|$dst, $src2}",
837 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
840 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
841 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
842 "cmova\t{$src2, $dst|$dst, $src2}",
843 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
847 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
848 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
849 "cmovl\t{$src2, $dst|$dst, $src2}",
850 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
853 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
854 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
855 "cmovl\t{$src2, $dst|$dst, $src2}",
856 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
859 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
860 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
861 "cmovl\t{$src2, $dst|$dst, $src2}",
862 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
865 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
866 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
867 "cmovl\t{$src2, $dst|$dst, $src2}",
868 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
872 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
873 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
874 "cmovge\t{$src2, $dst|$dst, $src2}",
875 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
878 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
879 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
880 "cmovge\t{$src2, $dst|$dst, $src2}",
881 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
884 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
885 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
886 "cmovge\t{$src2, $dst|$dst, $src2}",
887 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
890 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
891 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
892 "cmovge\t{$src2, $dst|$dst, $src2}",
893 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
897 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
898 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
899 "cmovle\t{$src2, $dst|$dst, $src2}",
900 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
903 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
904 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
905 "cmovle\t{$src2, $dst|$dst, $src2}",
906 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
909 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
910 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
911 "cmovle\t{$src2, $dst|$dst, $src2}",
912 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
915 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
916 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
917 "cmovle\t{$src2, $dst|$dst, $src2}",
918 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
922 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
923 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
924 "cmovg\t{$src2, $dst|$dst, $src2}",
925 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
928 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
929 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
930 "cmovg\t{$src2, $dst|$dst, $src2}",
931 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
934 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
935 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
936 "cmovg\t{$src2, $dst|$dst, $src2}",
937 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
940 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
941 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
942 "cmovg\t{$src2, $dst|$dst, $src2}",
943 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
947 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
948 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
949 "cmovs\t{$src2, $dst|$dst, $src2}",
950 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
953 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
954 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
955 "cmovs\t{$src2, $dst|$dst, $src2}",
956 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
959 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
960 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
961 "cmovs\t{$src2, $dst|$dst, $src2}",
962 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
965 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
966 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
967 "cmovs\t{$src2, $dst|$dst, $src2}",
968 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
972 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
973 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
974 "cmovns\t{$src2, $dst|$dst, $src2}",
975 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
978 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
979 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
980 "cmovns\t{$src2, $dst|$dst, $src2}",
981 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
984 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
985 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
986 "cmovns\t{$src2, $dst|$dst, $src2}",
987 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
990 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
991 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
992 "cmovns\t{$src2, $dst|$dst, $src2}",
993 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
997 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
998 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
999 "cmovp\t{$src2, $dst|$dst, $src2}",
1000 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1003 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1004 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1005 "cmovp\t{$src2, $dst|$dst, $src2}",
1006 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1009 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1010 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1011 "cmovp\t{$src2, $dst|$dst, $src2}",
1012 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1015 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1016 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1017 "cmovp\t{$src2, $dst|$dst, $src2}",
1018 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1022 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1023 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1024 "cmovnp\t{$src2, $dst|$dst, $src2}",
1025 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1028 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1029 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1030 "cmovnp\t{$src2, $dst|$dst, $src2}",
1031 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1034 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1035 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1036 "cmovnp\t{$src2, $dst|$dst, $src2}",
1037 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1040 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1041 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1042 "cmovnp\t{$src2, $dst|$dst, $src2}",
1043 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1048 def NEW_CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1049 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1050 "cmovb\t{$src2, $dst|$dst, $src2}",
1051 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1052 X86_COND_B, EFLAGS))]>,
1054 def NEW_CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1055 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1056 "cmovb\t{$src2, $dst|$dst, $src2}",
1057 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1058 X86_COND_B, EFLAGS))]>,
1060 def NEW_CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1061 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1062 "cmovb\t{$src2, $dst|$dst, $src2}",
1063 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1064 X86_COND_B, EFLAGS))]>,
1066 def NEW_CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1067 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1068 "cmovb\t{$src2, $dst|$dst, $src2}",
1069 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1070 X86_COND_B, EFLAGS))]>,
1073 def NEW_CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1074 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1075 "cmovae\t{$src2, $dst|$dst, $src2}",
1076 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1077 X86_COND_AE, EFLAGS))]>,
1079 def NEW_CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1080 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1081 "cmovae\t{$src2, $dst|$dst, $src2}",
1082 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1083 X86_COND_AE, EFLAGS))]>,
1085 def NEW_CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1086 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1087 "cmovae\t{$src2, $dst|$dst, $src2}",
1088 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1089 X86_COND_AE, EFLAGS))]>,
1091 def NEW_CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1092 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1093 "cmovae\t{$src2, $dst|$dst, $src2}",
1094 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1095 X86_COND_AE, EFLAGS))]>,
1098 def NEW_CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1099 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1100 "cmove\t{$src2, $dst|$dst, $src2}",
1101 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1102 X86_COND_E, EFLAGS))]>,
1104 def NEW_CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1105 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1106 "cmove\t{$src2, $dst|$dst, $src2}",
1107 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1108 X86_COND_E, EFLAGS))]>,
1110 def NEW_CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1111 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1112 "cmove\t{$src2, $dst|$dst, $src2}",
1113 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1114 X86_COND_E, EFLAGS))]>,
1116 def NEW_CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1117 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1118 "cmove\t{$src2, $dst|$dst, $src2}",
1119 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1120 X86_COND_E, EFLAGS))]>,
1123 def NEW_CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1124 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1125 "cmovne\t{$src2, $dst|$dst, $src2}",
1126 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1127 X86_COND_NE, EFLAGS))]>,
1129 def NEW_CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1130 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1131 "cmovne\t{$src2, $dst|$dst, $src2}",
1132 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1133 X86_COND_NE, EFLAGS))]>,
1135 def NEW_CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1136 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1137 "cmovne\t{$src2, $dst|$dst, $src2}",
1138 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1139 X86_COND_NE, EFLAGS))]>,
1141 def NEW_CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1142 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1143 "cmovne\t{$src2, $dst|$dst, $src2}",
1144 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1145 X86_COND_NE, EFLAGS))]>,
1148 def NEW_CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1149 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1150 "cmovbe\t{$src2, $dst|$dst, $src2}",
1151 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1152 X86_COND_BE, EFLAGS))]>,
1154 def NEW_CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1155 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1156 "cmovbe\t{$src2, $dst|$dst, $src2}",
1157 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1158 X86_COND_BE, EFLAGS))]>,
1160 def NEW_CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1161 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1162 "cmovbe\t{$src2, $dst|$dst, $src2}",
1163 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1164 X86_COND_BE, EFLAGS))]>,
1166 def NEW_CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1167 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1168 "cmovbe\t{$src2, $dst|$dst, $src2}",
1169 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1170 X86_COND_BE, EFLAGS))]>,
1173 def NEW_CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1174 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1175 "cmova\t{$src2, $dst|$dst, $src2}",
1176 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1177 X86_COND_A, EFLAGS))]>,
1179 def NEW_CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1180 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1181 "cmova\t{$src2, $dst|$dst, $src2}",
1182 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1183 X86_COND_A, EFLAGS))]>,
1185 def NEW_CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1186 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1187 "cmova\t{$src2, $dst|$dst, $src2}",
1188 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1189 X86_COND_A, EFLAGS))]>,
1191 def NEW_CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1192 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1193 "cmova\t{$src2, $dst|$dst, $src2}",
1194 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1195 X86_COND_A, EFLAGS))]>,
1198 def NEW_CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1199 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1200 "cmovl\t{$src2, $dst|$dst, $src2}",
1201 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1202 X86_COND_L, EFLAGS))]>,
1204 def NEW_CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1205 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1206 "cmovl\t{$src2, $dst|$dst, $src2}",
1207 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1208 X86_COND_L, EFLAGS))]>,
1210 def NEW_CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1211 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1212 "cmovl\t{$src2, $dst|$dst, $src2}",
1213 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1214 X86_COND_L, EFLAGS))]>,
1216 def NEW_CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1217 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1218 "cmovl\t{$src2, $dst|$dst, $src2}",
1219 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1220 X86_COND_L, EFLAGS))]>,
1223 def NEW_CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1224 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1225 "cmovge\t{$src2, $dst|$dst, $src2}",
1226 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1227 X86_COND_GE, EFLAGS))]>,
1229 def NEW_CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1230 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1231 "cmovge\t{$src2, $dst|$dst, $src2}",
1232 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1233 X86_COND_GE, EFLAGS))]>,
1235 def NEW_CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1236 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1237 "cmovge\t{$src2, $dst|$dst, $src2}",
1238 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1239 X86_COND_GE, EFLAGS))]>,
1241 def NEW_CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1242 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1243 "cmovge\t{$src2, $dst|$dst, $src2}",
1244 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1245 X86_COND_GE, EFLAGS))]>,
1248 def NEW_CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1249 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1250 "cmovle\t{$src2, $dst|$dst, $src2}",
1251 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1252 X86_COND_LE, EFLAGS))]>,
1254 def NEW_CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1255 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1256 "cmovle\t{$src2, $dst|$dst, $src2}",
1257 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1258 X86_COND_LE, EFLAGS))]>,
1260 def NEW_CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1261 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1262 "cmovle\t{$src2, $dst|$dst, $src2}",
1263 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1264 X86_COND_LE, EFLAGS))]>,
1266 def NEW_CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1267 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1268 "cmovle\t{$src2, $dst|$dst, $src2}",
1269 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1270 X86_COND_LE, EFLAGS))]>,
1273 def NEW_CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1274 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1275 "cmovg\t{$src2, $dst|$dst, $src2}",
1276 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1277 X86_COND_G, EFLAGS))]>,
1279 def NEW_CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1280 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1281 "cmovg\t{$src2, $dst|$dst, $src2}",
1282 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1283 X86_COND_G, EFLAGS))]>,
1285 def NEW_CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1286 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1287 "cmovg\t{$src2, $dst|$dst, $src2}",
1288 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1289 X86_COND_G, EFLAGS))]>,
1291 def NEW_CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1292 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1293 "cmovg\t{$src2, $dst|$dst, $src2}",
1294 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1295 X86_COND_G, EFLAGS))]>,
1298 def NEW_CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1299 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1300 "cmovs\t{$src2, $dst|$dst, $src2}",
1301 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1302 X86_COND_S, EFLAGS))]>,
1304 def NEW_CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1305 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1306 "cmovs\t{$src2, $dst|$dst, $src2}",
1307 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1308 X86_COND_S, EFLAGS))]>,
1310 def NEW_CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1311 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1312 "cmovs\t{$src2, $dst|$dst, $src2}",
1313 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1314 X86_COND_S, EFLAGS))]>,
1316 def NEW_CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1317 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1318 "cmovs\t{$src2, $dst|$dst, $src2}",
1319 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1320 X86_COND_S, EFLAGS))]>,
1323 def NEW_CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1324 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1325 "cmovns\t{$src2, $dst|$dst, $src2}",
1326 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1327 X86_COND_NS, EFLAGS))]>,
1329 def NEW_CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1330 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1331 "cmovns\t{$src2, $dst|$dst, $src2}",
1332 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1333 X86_COND_NS, EFLAGS))]>,
1335 def NEW_CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1336 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1337 "cmovns\t{$src2, $dst|$dst, $src2}",
1338 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1339 X86_COND_NS, EFLAGS))]>,
1341 def NEW_CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1342 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1343 "cmovns\t{$src2, $dst|$dst, $src2}",
1344 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1345 X86_COND_NS, EFLAGS))]>,
1348 def NEW_CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1349 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1350 "cmovp\t{$src2, $dst|$dst, $src2}",
1351 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1352 X86_COND_P, EFLAGS))]>,
1354 def NEW_CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1355 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1356 "cmovp\t{$src2, $dst|$dst, $src2}",
1357 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1358 X86_COND_P, EFLAGS))]>,
1360 def NEW_CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1361 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1362 "cmovp\t{$src2, $dst|$dst, $src2}",
1363 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1364 X86_COND_P, EFLAGS))]>,
1366 def NEW_CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1367 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1368 "cmovp\t{$src2, $dst|$dst, $src2}",
1369 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1370 X86_COND_P, EFLAGS))]>,
1373 def NEW_CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1374 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1375 "cmovnp\t{$src2, $dst|$dst, $src2}",
1376 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1377 X86_COND_NP, EFLAGS))]>,
1379 def NEW_CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1380 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1381 "cmovnp\t{$src2, $dst|$dst, $src2}",
1382 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1383 X86_COND_NP, EFLAGS))]>,
1385 def NEW_CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1386 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1387 "cmovnp\t{$src2, $dst|$dst, $src2}",
1388 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1389 X86_COND_NP, EFLAGS))]>,
1391 def NEW_CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1392 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1393 "cmovnp\t{$src2, $dst|$dst, $src2}",
1394 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1395 X86_COND_NP, EFLAGS))]>,
1397 } // Uses = [EFLAGS]
1400 // unary instructions
1401 let CodeSize = 2 in {
1402 let Defs = [EFLAGS] in {
1403 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1404 [(set GR8:$dst, (ineg GR8:$src))]>;
1405 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1406 [(set GR16:$dst, (ineg GR16:$src))]>, OpSize;
1407 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1408 [(set GR32:$dst, (ineg GR32:$src))]>;
1409 let isTwoAddress = 0 in {
1410 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1411 [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
1412 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1413 [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1414 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1415 [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
1418 } // Defs = [EFLAGS]
1420 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1421 [(set GR8:$dst, (not GR8:$src))]>;
1422 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1423 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1424 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1425 [(set GR32:$dst, (not GR32:$src))]>;
1426 let isTwoAddress = 0 in {
1427 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1428 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1429 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1430 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1431 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1432 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1436 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1437 let Defs = [EFLAGS] in {
1439 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1440 [(set GR8:$dst, (add GR8:$src, 1))]>;
1441 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1442 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1443 [(set GR16:$dst, (add GR16:$src, 1))]>,
1444 OpSize, Requires<[In32BitMode]>;
1445 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1446 [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>;
1448 let isTwoAddress = 0, CodeSize = 2 in {
1449 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1450 [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
1451 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1452 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>, OpSize;
1453 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1454 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>;
1458 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1459 [(set GR8:$dst, (add GR8:$src, -1))]>;
1460 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1461 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1462 [(set GR16:$dst, (add GR16:$src, -1))]>,
1463 OpSize, Requires<[In32BitMode]>;
1464 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1465 [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>;
1468 let isTwoAddress = 0, CodeSize = 2 in {
1469 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1470 [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
1471 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1472 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>, OpSize;
1473 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1474 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>;
1476 } // Defs = [EFLAGS]
1478 // Logical operators...
1479 let Defs = [EFLAGS] in {
1480 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1481 def AND8rr : I<0x20, MRMDestReg,
1482 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1483 "and{b}\t{$src2, $dst|$dst, $src2}",
1484 [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>;
1485 def AND16rr : I<0x21, MRMDestReg,
1486 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1487 "and{w}\t{$src2, $dst|$dst, $src2}",
1488 [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize;
1489 def AND32rr : I<0x21, MRMDestReg,
1490 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1491 "and{l}\t{$src2, $dst|$dst, $src2}",
1492 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
1495 def AND8rm : I<0x22, MRMSrcMem,
1496 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1497 "and{b}\t{$src2, $dst|$dst, $src2}",
1498 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>;
1499 def AND16rm : I<0x23, MRMSrcMem,
1500 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1501 "and{w}\t{$src2, $dst|$dst, $src2}",
1502 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize;
1503 def AND32rm : I<0x23, MRMSrcMem,
1504 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1505 "and{l}\t{$src2, $dst|$dst, $src2}",
1506 [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>;
1508 def AND8ri : Ii8<0x80, MRM4r,
1509 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1510 "and{b}\t{$src2, $dst|$dst, $src2}",
1511 [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>;
1512 def AND16ri : Ii16<0x81, MRM4r,
1513 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1514 "and{w}\t{$src2, $dst|$dst, $src2}",
1515 [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize;
1516 def AND32ri : Ii32<0x81, MRM4r,
1517 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1518 "and{l}\t{$src2, $dst|$dst, $src2}",
1519 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
1520 def AND16ri8 : Ii8<0x83, MRM4r,
1521 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1522 "and{w}\t{$src2, $dst|$dst, $src2}",
1523 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>,
1525 def AND32ri8 : Ii8<0x83, MRM4r,
1526 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1527 "and{l}\t{$src2, $dst|$dst, $src2}",
1528 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>;
1530 let isTwoAddress = 0 in {
1531 def AND8mr : I<0x20, MRMDestMem,
1532 (outs), (ins i8mem :$dst, GR8 :$src),
1533 "and{b}\t{$src, $dst|$dst, $src}",
1534 [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>;
1535 def AND16mr : I<0x21, MRMDestMem,
1536 (outs), (ins i16mem:$dst, GR16:$src),
1537 "and{w}\t{$src, $dst|$dst, $src}",
1538 [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>,
1540 def AND32mr : I<0x21, MRMDestMem,
1541 (outs), (ins i32mem:$dst, GR32:$src),
1542 "and{l}\t{$src, $dst|$dst, $src}",
1543 [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>;
1544 def AND8mi : Ii8<0x80, MRM4m,
1545 (outs), (ins i8mem :$dst, i8imm :$src),
1546 "and{b}\t{$src, $dst|$dst, $src}",
1547 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1548 def AND16mi : Ii16<0x81, MRM4m,
1549 (outs), (ins i16mem:$dst, i16imm:$src),
1550 "and{w}\t{$src, $dst|$dst, $src}",
1551 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1553 def AND32mi : Ii32<0x81, MRM4m,
1554 (outs), (ins i32mem:$dst, i32imm:$src),
1555 "and{l}\t{$src, $dst|$dst, $src}",
1556 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1557 def AND16mi8 : Ii8<0x83, MRM4m,
1558 (outs), (ins i16mem:$dst, i16i8imm :$src),
1559 "and{w}\t{$src, $dst|$dst, $src}",
1560 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1562 def AND32mi8 : Ii8<0x83, MRM4m,
1563 (outs), (ins i32mem:$dst, i32i8imm :$src),
1564 "and{l}\t{$src, $dst|$dst, $src}",
1565 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1569 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1570 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1571 "or{b}\t{$src2, $dst|$dst, $src2}",
1572 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
1573 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1574 "or{w}\t{$src2, $dst|$dst, $src2}",
1575 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize;
1576 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1577 "or{l}\t{$src2, $dst|$dst, $src2}",
1578 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
1580 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1581 "or{b}\t{$src2, $dst|$dst, $src2}",
1582 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
1583 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1584 "or{w}\t{$src2, $dst|$dst, $src2}",
1585 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize;
1586 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1587 "or{l}\t{$src2, $dst|$dst, $src2}",
1588 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>;
1590 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1591 "or{b}\t{$src2, $dst|$dst, $src2}",
1592 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
1593 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1594 "or{w}\t{$src2, $dst|$dst, $src2}",
1595 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize;
1596 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1597 "or{l}\t{$src2, $dst|$dst, $src2}",
1598 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
1600 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1601 "or{w}\t{$src2, $dst|$dst, $src2}",
1602 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1603 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1604 "or{l}\t{$src2, $dst|$dst, $src2}",
1605 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>;
1606 let isTwoAddress = 0 in {
1607 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1608 "or{b}\t{$src, $dst|$dst, $src}",
1609 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
1610 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1611 "or{w}\t{$src, $dst|$dst, $src}",
1612 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize;
1613 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1614 "or{l}\t{$src, $dst|$dst, $src}",
1615 [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>;
1616 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1617 "or{b}\t{$src, $dst|$dst, $src}",
1618 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1619 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1620 "or{w}\t{$src, $dst|$dst, $src}",
1621 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1623 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1624 "or{l}\t{$src, $dst|$dst, $src}",
1625 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1626 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1627 "or{w}\t{$src, $dst|$dst, $src}",
1628 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1630 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1631 "or{l}\t{$src, $dst|$dst, $src}",
1632 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1636 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1637 def XOR8rr : I<0x30, MRMDestReg,
1638 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1639 "xor{b}\t{$src2, $dst|$dst, $src2}",
1640 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>;
1641 def XOR16rr : I<0x31, MRMDestReg,
1642 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1643 "xor{w}\t{$src2, $dst|$dst, $src2}",
1644 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize;
1645 def XOR32rr : I<0x31, MRMDestReg,
1646 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1647 "xor{l}\t{$src2, $dst|$dst, $src2}",
1648 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
1651 def XOR8rm : I<0x32, MRMSrcMem ,
1652 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1653 "xor{b}\t{$src2, $dst|$dst, $src2}",
1654 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>;
1655 def XOR16rm : I<0x33, MRMSrcMem ,
1656 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1657 "xor{w}\t{$src2, $dst|$dst, $src2}",
1658 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>, OpSize;
1659 def XOR32rm : I<0x33, MRMSrcMem ,
1660 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1661 "xor{l}\t{$src2, $dst|$dst, $src2}",
1662 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>;
1664 def XOR8ri : Ii8<0x80, MRM6r,
1665 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1666 "xor{b}\t{$src2, $dst|$dst, $src2}",
1667 [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>;
1668 def XOR16ri : Ii16<0x81, MRM6r,
1669 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1670 "xor{w}\t{$src2, $dst|$dst, $src2}",
1671 [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize;
1672 def XOR32ri : Ii32<0x81, MRM6r,
1673 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1674 "xor{l}\t{$src2, $dst|$dst, $src2}",
1675 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
1676 def XOR16ri8 : Ii8<0x83, MRM6r,
1677 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1678 "xor{w}\t{$src2, $dst|$dst, $src2}",
1679 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>,
1681 def XOR32ri8 : Ii8<0x83, MRM6r,
1682 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1683 "xor{l}\t{$src2, $dst|$dst, $src2}",
1684 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>;
1685 let isTwoAddress = 0 in {
1686 def XOR8mr : I<0x30, MRMDestMem,
1687 (outs), (ins i8mem :$dst, GR8 :$src),
1688 "xor{b}\t{$src, $dst|$dst, $src}",
1689 [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>;
1690 def XOR16mr : I<0x31, MRMDestMem,
1691 (outs), (ins i16mem:$dst, GR16:$src),
1692 "xor{w}\t{$src, $dst|$dst, $src}",
1693 [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>,
1695 def XOR32mr : I<0x31, MRMDestMem,
1696 (outs), (ins i32mem:$dst, GR32:$src),
1697 "xor{l}\t{$src, $dst|$dst, $src}",
1698 [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>;
1699 def XOR8mi : Ii8<0x80, MRM6m,
1700 (outs), (ins i8mem :$dst, i8imm :$src),
1701 "xor{b}\t{$src, $dst|$dst, $src}",
1702 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1703 def XOR16mi : Ii16<0x81, MRM6m,
1704 (outs), (ins i16mem:$dst, i16imm:$src),
1705 "xor{w}\t{$src, $dst|$dst, $src}",
1706 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1708 def XOR32mi : Ii32<0x81, MRM6m,
1709 (outs), (ins i32mem:$dst, i32imm:$src),
1710 "xor{l}\t{$src, $dst|$dst, $src}",
1711 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1712 def XOR16mi8 : Ii8<0x83, MRM6m,
1713 (outs), (ins i16mem:$dst, i16i8imm :$src),
1714 "xor{w}\t{$src, $dst|$dst, $src}",
1715 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1717 def XOR32mi8 : Ii8<0x83, MRM6m,
1718 (outs), (ins i32mem:$dst, i32i8imm :$src),
1719 "xor{l}\t{$src, $dst|$dst, $src}",
1720 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1722 } // Defs = [EFLAGS]
1724 // Shift instructions
1725 let Defs = [EFLAGS] in {
1726 let Uses = [CL] in {
1727 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1728 "shl{b}\t{%cl, $dst|$dst, %CL}",
1729 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1730 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1731 "shl{w}\t{%cl, $dst|$dst, %CL}",
1732 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1733 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1734 "shl{l}\t{%cl, $dst|$dst, %CL}",
1735 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1738 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1739 "shl{b}\t{$src2, $dst|$dst, $src2}",
1740 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1741 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1742 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1743 "shl{w}\t{$src2, $dst|$dst, $src2}",
1744 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1745 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1746 "shl{l}\t{$src2, $dst|$dst, $src2}",
1747 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1750 // Shift left by one. Not used because (add x, x) is slightly cheaper.
1751 def SHL8r1 : I<0xD0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
1752 "shl{b}\t$dst", []>;
1753 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
1754 "shl{w}\t$dst", []>, OpSize;
1755 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
1756 "shl{l}\t$dst", []>;
1758 let isTwoAddress = 0 in {
1759 let Uses = [CL] in {
1760 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1761 "shl{b}\t{%cl, $dst|$dst, %CL}",
1762 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1763 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1764 "shl{w}\t{%cl, $dst|$dst, %CL}",
1765 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1766 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1767 "shl{l}\t{%cl, $dst|$dst, %CL}",
1768 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1770 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1771 "shl{b}\t{$src, $dst|$dst, $src}",
1772 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1773 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1774 "shl{w}\t{$src, $dst|$dst, $src}",
1775 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1777 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1778 "shl{l}\t{$src, $dst|$dst, $src}",
1779 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1782 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1784 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1785 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1787 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1789 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1791 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1794 let Uses = [CL] in {
1795 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1796 "shr{b}\t{%cl, $dst|$dst, %CL}",
1797 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1798 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1799 "shr{w}\t{%cl, $dst|$dst, %CL}",
1800 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1801 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1802 "shr{l}\t{%cl, $dst|$dst, %CL}",
1803 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1806 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1807 "shr{b}\t{$src2, $dst|$dst, $src2}",
1808 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1809 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1810 "shr{w}\t{$src2, $dst|$dst, $src2}",
1811 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1812 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1813 "shr{l}\t{$src2, $dst|$dst, $src2}",
1814 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1817 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1819 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1820 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1822 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1823 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1825 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1827 let isTwoAddress = 0 in {
1828 let Uses = [CL] in {
1829 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1830 "shr{b}\t{%cl, $dst|$dst, %CL}",
1831 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1832 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1833 "shr{w}\t{%cl, $dst|$dst, %CL}",
1834 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1836 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1837 "shr{l}\t{%cl, $dst|$dst, %CL}",
1838 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1840 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1841 "shr{b}\t{$src, $dst|$dst, $src}",
1842 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1843 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1844 "shr{w}\t{$src, $dst|$dst, $src}",
1845 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1847 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1848 "shr{l}\t{$src, $dst|$dst, $src}",
1849 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1852 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1854 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1855 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1857 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1858 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1860 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1863 let Uses = [CL] in {
1864 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1865 "sar{b}\t{%cl, $dst|$dst, %CL}",
1866 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1867 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1868 "sar{w}\t{%cl, $dst|$dst, %CL}",
1869 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1870 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1871 "sar{l}\t{%cl, $dst|$dst, %CL}",
1872 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1875 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1876 "sar{b}\t{$src2, $dst|$dst, $src2}",
1877 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1878 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1879 "sar{w}\t{$src2, $dst|$dst, $src2}",
1880 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1882 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1883 "sar{l}\t{$src2, $dst|$dst, $src2}",
1884 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1887 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1889 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1890 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1892 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1893 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1895 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1897 let isTwoAddress = 0 in {
1898 let Uses = [CL] in {
1899 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1900 "sar{b}\t{%cl, $dst|$dst, %CL}",
1901 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
1902 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1903 "sar{w}\t{%cl, $dst|$dst, %CL}",
1904 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1905 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1906 "sar{l}\t{%cl, $dst|$dst, %CL}",
1907 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1909 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1910 "sar{b}\t{$src, $dst|$dst, $src}",
1911 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1912 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1913 "sar{w}\t{$src, $dst|$dst, $src}",
1914 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1916 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1917 "sar{l}\t{$src, $dst|$dst, $src}",
1918 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1921 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1923 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1924 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1926 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1928 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
1930 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1933 // Rotate instructions
1934 // FIXME: provide shorter instructions when imm8 == 1
1935 let Uses = [CL] in {
1936 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
1937 "rol{b}\t{%cl, $dst|$dst, %CL}",
1938 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
1939 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
1940 "rol{w}\t{%cl, $dst|$dst, %CL}",
1941 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
1942 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
1943 "rol{l}\t{%cl, $dst|$dst, %CL}",
1944 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
1947 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1948 "rol{b}\t{$src2, $dst|$dst, $src2}",
1949 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1950 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1951 "rol{w}\t{$src2, $dst|$dst, $src2}",
1952 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1953 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1954 "rol{l}\t{$src2, $dst|$dst, $src2}",
1955 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1958 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1960 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1961 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
1963 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1964 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1966 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1968 let isTwoAddress = 0 in {
1969 let Uses = [CL] in {
1970 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
1971 "rol{b}\t{%cl, $dst|$dst, %CL}",
1972 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
1973 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
1974 "rol{w}\t{%cl, $dst|$dst, %CL}",
1975 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1976 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
1977 "rol{l}\t{%cl, $dst|$dst, %CL}",
1978 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
1980 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
1981 "rol{b}\t{$src, $dst|$dst, $src}",
1982 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1983 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
1984 "rol{w}\t{$src, $dst|$dst, $src}",
1985 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1987 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
1988 "rol{l}\t{$src, $dst|$dst, $src}",
1989 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1992 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
1994 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1995 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
1997 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1999 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2001 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2004 let Uses = [CL] in {
2005 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2006 "ror{b}\t{%cl, $dst|$dst, %CL}",
2007 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2008 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2009 "ror{w}\t{%cl, $dst|$dst, %CL}",
2010 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2011 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2012 "ror{l}\t{%cl, $dst|$dst, %CL}",
2013 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2016 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2017 "ror{b}\t{$src2, $dst|$dst, $src2}",
2018 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2019 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2020 "ror{w}\t{$src2, $dst|$dst, $src2}",
2021 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2022 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2023 "ror{l}\t{$src2, $dst|$dst, $src2}",
2024 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2027 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2029 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2030 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2032 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2033 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2035 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2037 let isTwoAddress = 0 in {
2038 let Uses = [CL] in {
2039 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2040 "ror{b}\t{%cl, $dst|$dst, %CL}",
2041 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2042 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2043 "ror{w}\t{%cl, $dst|$dst, %CL}",
2044 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2045 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2046 "ror{l}\t{%cl, $dst|$dst, %CL}",
2047 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2049 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2050 "ror{b}\t{$src, $dst|$dst, $src}",
2051 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2052 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2053 "ror{w}\t{$src, $dst|$dst, $src}",
2054 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2056 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2057 "ror{l}\t{$src, $dst|$dst, $src}",
2058 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2061 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2063 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2064 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2066 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2068 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2070 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2075 // Double shift instructions (generalizations of rotate)
2076 let Uses = [CL] in {
2077 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2078 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2079 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2080 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2081 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2082 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2083 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2084 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2085 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2087 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2088 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2089 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2093 let isCommutable = 1 in { // These instructions commute to each other.
2094 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2095 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2096 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2097 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2100 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2101 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2102 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2103 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2106 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2107 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2108 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2109 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2112 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2113 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2114 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2115 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2120 let isTwoAddress = 0 in {
2121 let Uses = [CL] in {
2122 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2123 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2124 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2126 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2127 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2128 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2131 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2132 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2133 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2134 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2135 (i8 imm:$src3)), addr:$dst)]>,
2137 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2138 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2139 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2140 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2141 (i8 imm:$src3)), addr:$dst)]>,
2144 let Uses = [CL] in {
2145 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2146 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2147 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2148 addr:$dst)]>, TB, OpSize;
2149 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2150 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2151 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2152 addr:$dst)]>, TB, OpSize;
2154 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2155 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2156 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2157 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2158 (i8 imm:$src3)), addr:$dst)]>,
2160 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2161 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2162 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2163 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2164 (i8 imm:$src3)), addr:$dst)]>,
2167 } // Defs = [EFLAGS]
2171 let Defs = [EFLAGS] in {
2172 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2173 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2174 (ins GR8 :$src1, GR8 :$src2),
2175 "add{b}\t{$src2, $dst|$dst, $src2}",
2176 [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>;
2177 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2178 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2179 (ins GR16:$src1, GR16:$src2),
2180 "add{w}\t{$src2, $dst|$dst, $src2}",
2181 [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize;
2182 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2183 (ins GR32:$src1, GR32:$src2),
2184 "add{l}\t{$src2, $dst|$dst, $src2}",
2185 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
2186 } // end isConvertibleToThreeAddress
2187 } // end isCommutable
2188 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2189 (ins GR8 :$src1, i8mem :$src2),
2190 "add{b}\t{$src2, $dst|$dst, $src2}",
2191 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>;
2192 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2193 (ins GR16:$src1, i16mem:$src2),
2194 "add{w}\t{$src2, $dst|$dst, $src2}",
2195 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>,OpSize;
2196 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2197 (ins GR32:$src1, i32mem:$src2),
2198 "add{l}\t{$src2, $dst|$dst, $src2}",
2199 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>;
2201 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2202 "add{b}\t{$src2, $dst|$dst, $src2}",
2203 [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>;
2205 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2206 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2207 (ins GR16:$src1, i16imm:$src2),
2208 "add{w}\t{$src2, $dst|$dst, $src2}",
2209 [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize;
2210 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2211 (ins GR32:$src1, i32imm:$src2),
2212 "add{l}\t{$src2, $dst|$dst, $src2}",
2213 [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>;
2214 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2215 (ins GR16:$src1, i16i8imm:$src2),
2216 "add{w}\t{$src2, $dst|$dst, $src2}",
2217 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2218 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2219 (ins GR32:$src1, i32i8imm:$src2),
2220 "add{l}\t{$src2, $dst|$dst, $src2}",
2221 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>;
2224 let isTwoAddress = 0 in {
2225 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2226 "add{b}\t{$src2, $dst|$dst, $src2}",
2227 [(store (add (load addr:$dst), GR8:$src2), addr:$dst)]>;
2228 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2229 "add{w}\t{$src2, $dst|$dst, $src2}",
2230 [(store (add (load addr:$dst), GR16:$src2), addr:$dst)]>,
2232 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2233 "add{l}\t{$src2, $dst|$dst, $src2}",
2234 [(store (add (load addr:$dst), GR32:$src2), addr:$dst)]>;
2235 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2236 "add{b}\t{$src2, $dst|$dst, $src2}",
2237 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2238 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2239 "add{w}\t{$src2, $dst|$dst, $src2}",
2240 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2242 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2243 "add{l}\t{$src2, $dst|$dst, $src2}",
2244 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2245 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2246 "add{w}\t{$src2, $dst|$dst, $src2}",
2247 [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2249 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2250 "add{l}\t{$src2, $dst|$dst, $src2}",
2251 [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2254 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2255 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2256 "adc{l}\t{$src2, $dst|$dst, $src2}",
2257 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2259 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2260 "adc{l}\t{$src2, $dst|$dst, $src2}",
2261 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2262 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2263 "adc{l}\t{$src2, $dst|$dst, $src2}",
2264 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2265 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2266 "adc{l}\t{$src2, $dst|$dst, $src2}",
2267 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2269 let isTwoAddress = 0 in {
2270 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2271 "adc{l}\t{$src2, $dst|$dst, $src2}",
2272 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2273 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2274 "adc{l}\t{$src2, $dst|$dst, $src2}",
2275 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2276 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2277 "adc{l}\t{$src2, $dst|$dst, $src2}",
2278 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2281 def SUB8rr : I<0x28, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
2282 "sub{b}\t{$src2, $dst|$dst, $src2}",
2283 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2))]>;
2284 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2285 "sub{w}\t{$src2, $dst|$dst, $src2}",
2286 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2))]>, OpSize;
2287 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2288 "sub{l}\t{$src2, $dst|$dst, $src2}",
2289 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
2290 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
2291 "sub{b}\t{$src2, $dst|$dst, $src2}",
2292 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2)))]>;
2293 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2294 "sub{w}\t{$src2, $dst|$dst, $src2}",
2295 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2)))]>, OpSize;
2296 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2297 "sub{l}\t{$src2, $dst|$dst, $src2}",
2298 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2)))]>;
2300 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2301 "sub{b}\t{$src2, $dst|$dst, $src2}",
2302 [(set GR8:$dst, (sub GR8:$src1, imm:$src2))]>;
2303 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2304 "sub{w}\t{$src2, $dst|$dst, $src2}",
2305 [(set GR16:$dst, (sub GR16:$src1, imm:$src2))]>, OpSize;
2306 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2307 "sub{l}\t{$src2, $dst|$dst, $src2}",
2308 [(set GR32:$dst, (sub GR32:$src1, imm:$src2))]>;
2309 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2310 "sub{w}\t{$src2, $dst|$dst, $src2}",
2311 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2))]>,
2313 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2314 "sub{l}\t{$src2, $dst|$dst, $src2}",
2315 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2))]>;
2316 let isTwoAddress = 0 in {
2317 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2318 "sub{b}\t{$src2, $dst|$dst, $src2}",
2319 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst)]>;
2320 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2321 "sub{w}\t{$src2, $dst|$dst, $src2}",
2322 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst)]>,
2324 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2325 "sub{l}\t{$src2, $dst|$dst, $src2}",
2326 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst)]>;
2327 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2328 "sub{b}\t{$src2, $dst|$dst, $src2}",
2329 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2330 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2331 "sub{w}\t{$src2, $dst|$dst, $src2}",
2332 [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2334 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2335 "sub{l}\t{$src2, $dst|$dst, $src2}",
2336 [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2337 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2338 "sub{w}\t{$src2, $dst|$dst, $src2}",
2339 [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2341 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2342 "sub{l}\t{$src2, $dst|$dst, $src2}",
2343 [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2346 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2347 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2348 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2350 let isTwoAddress = 0 in {
2351 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2352 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2353 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2354 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2355 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2356 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2357 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2358 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2359 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2360 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2361 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2362 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2364 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2365 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2366 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2367 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2368 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2369 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2370 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2371 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2372 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2373 } // Defs = [EFLAGS]
2375 let Defs = [EFLAGS] in {
2376 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2377 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2378 "imul{w}\t{$src2, $dst|$dst, $src2}",
2379 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2))]>, TB, OpSize;
2380 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2381 "imul{l}\t{$src2, $dst|$dst, $src2}",
2382 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>, TB;
2384 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2385 "imul{w}\t{$src2, $dst|$dst, $src2}",
2386 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2)))]>,
2388 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2389 "imul{l}\t{$src2, $dst|$dst, $src2}",
2390 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2)))]>, TB;
2391 } // Defs = [EFLAGS]
2392 } // end Two Address instructions
2394 // Suprisingly enough, these are not two address instructions!
2395 let Defs = [EFLAGS] in {
2396 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2397 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2398 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2399 [(set GR16:$dst, (mul GR16:$src1, imm:$src2))]>, OpSize;
2400 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2401 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2402 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2403 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
2404 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2405 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2406 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2407 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2))]>,
2409 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2410 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2411 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2412 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2))]>;
2414 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2415 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2416 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2417 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2))]>,
2419 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2420 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2421 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2422 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2))]>;
2423 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2424 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2425 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2426 [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>,
2428 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2429 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2430 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2431 [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>;
2432 } // Defs = [EFLAGS]
2434 //===----------------------------------------------------------------------===//
2435 // Test instructions are just like AND, except they don't generate a result.
2437 let Defs = [EFLAGS] in {
2438 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2439 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2440 "test{b}\t{$src2, $src1|$src1, $src2}",
2441 [(X86cmp (and GR8:$src1, GR8:$src2), 0)]>;
2442 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2443 "test{w}\t{$src2, $src1|$src1, $src2}",
2444 [(X86cmp (and GR16:$src1, GR16:$src2), 0)]>, OpSize;
2445 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2446 "test{l}\t{$src2, $src1|$src1, $src2}",
2447 [(X86cmp (and GR32:$src1, GR32:$src2), 0)]>;
2450 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2451 "test{b}\t{$src2, $src1|$src1, $src2}",
2452 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0)]>;
2453 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2454 "test{w}\t{$src2, $src1|$src1, $src2}",
2455 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0)]>,
2457 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2458 "test{l}\t{$src2, $src1|$src1, $src2}",
2459 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0)]>;
2461 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2462 (outs), (ins GR8:$src1, i8imm:$src2),
2463 "test{b}\t{$src2, $src1|$src1, $src2}",
2464 [(X86cmp (and GR8:$src1, imm:$src2), 0)]>;
2465 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2466 (outs), (ins GR16:$src1, i16imm:$src2),
2467 "test{w}\t{$src2, $src1|$src1, $src2}",
2468 [(X86cmp (and GR16:$src1, imm:$src2), 0)]>, OpSize;
2469 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2470 (outs), (ins GR32:$src1, i32imm:$src2),
2471 "test{l}\t{$src2, $src1|$src1, $src2}",
2472 [(X86cmp (and GR32:$src1, imm:$src2), 0)]>;
2474 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2475 (outs), (ins i8mem:$src1, i8imm:$src2),
2476 "test{b}\t{$src2, $src1|$src1, $src2}",
2477 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0)]>;
2478 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2479 (outs), (ins i16mem:$src1, i16imm:$src2),
2480 "test{w}\t{$src2, $src1|$src1, $src2}",
2481 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0)]>,
2483 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2484 (outs), (ins i32mem:$src1, i32imm:$src2),
2485 "test{l}\t{$src2, $src1|$src1, $src2}",
2486 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0)]>;
2487 } // Defs = [EFLAGS]
2490 let Defs = [EFLAGS] in {
2491 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2492 def NEW_TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2493 "test{b}\t{$src2, $src1|$src1, $src2}",
2494 [(X86cmp_new (and GR8:$src1, GR8:$src2), 0),
2495 (implicit EFLAGS)]>;
2496 def NEW_TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2497 "test{w}\t{$src2, $src1|$src1, $src2}",
2498 [(X86cmp_new (and GR16:$src1, GR16:$src2), 0),
2499 (implicit EFLAGS)]>,
2501 def NEW_TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2502 "test{l}\t{$src2, $src1|$src1, $src2}",
2503 [(X86cmp_new (and GR32:$src1, GR32:$src2), 0),
2504 (implicit EFLAGS)]>;
2507 def NEW_TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2508 "test{b}\t{$src2, $src1|$src1, $src2}",
2509 [(X86cmp_new (and GR8:$src1, (loadi8 addr:$src2)), 0),
2510 (implicit EFLAGS)]>;
2511 def NEW_TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2512 "test{w}\t{$src2, $src1|$src1, $src2}",
2513 [(X86cmp_new (and GR16:$src1, (loadi16 addr:$src2)), 0),
2514 (implicit EFLAGS)]>, OpSize;
2515 def NEW_TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2516 "test{l}\t{$src2, $src1|$src1, $src2}",
2517 [(X86cmp_new (and GR32:$src1, (loadi32 addr:$src2)), 0),
2518 (implicit EFLAGS)]>;
2520 def NEW_TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2521 (outs), (ins GR8:$src1, i8imm:$src2),
2522 "test{b}\t{$src2, $src1|$src1, $src2}",
2523 [(X86cmp_new (and GR8:$src1, imm:$src2), 0),
2524 (implicit EFLAGS)]>;
2525 def NEW_TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2526 (outs), (ins GR16:$src1, i16imm:$src2),
2527 "test{w}\t{$src2, $src1|$src1, $src2}",
2528 [(X86cmp_new (and GR16:$src1, imm:$src2), 0),
2529 (implicit EFLAGS)]>, OpSize;
2530 def NEW_TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2531 (outs), (ins GR32:$src1, i32imm:$src2),
2532 "test{l}\t{$src2, $src1|$src1, $src2}",
2533 [(X86cmp_new (and GR32:$src1, imm:$src2), 0),
2534 (implicit EFLAGS)]>;
2536 def NEW_TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2537 (outs), (ins i8mem:$src1, i8imm:$src2),
2538 "test{b}\t{$src2, $src1|$src1, $src2}",
2539 [(X86cmp_new (and (loadi8 addr:$src1), imm:$src2), 0),
2540 (implicit EFLAGS)]>;
2541 def NEW_TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2542 (outs), (ins i16mem:$src1, i16imm:$src2),
2543 "test{w}\t{$src2, $src1|$src1, $src2}",
2544 [(X86cmp_new (and (loadi16 addr:$src1), imm:$src2), 0),
2545 (implicit EFLAGS)]>, OpSize;
2546 def NEW_TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2547 (outs), (ins i32mem:$src1, i32imm:$src2),
2548 "test{l}\t{$src2, $src1|$src1, $src2}",
2549 [(X86cmp_new (and (loadi32 addr:$src1), imm:$src2), 0),
2550 (implicit EFLAGS)]>;
2551 } // Defs = [EFLAGS]
2554 // Condition code ops, incl. set if equal/not equal/...
2555 let Defs = [EFLAGS], Uses = [AH] in
2556 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2557 let Defs = [AH], Uses = [EFLAGS] in
2558 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2560 let Uses = [EFLAGS] in {
2561 def SETEr : I<0x94, MRM0r,
2562 (outs GR8 :$dst), (ins),
2564 [(set GR8:$dst, (X86setcc X86_COND_E))]>,
2566 def SETEm : I<0x94, MRM0m,
2567 (outs), (ins i8mem:$dst),
2569 [(store (X86setcc X86_COND_E), addr:$dst)]>,
2571 def SETNEr : I<0x95, MRM0r,
2572 (outs GR8 :$dst), (ins),
2574 [(set GR8:$dst, (X86setcc X86_COND_NE))]>,
2576 def SETNEm : I<0x95, MRM0m,
2577 (outs), (ins i8mem:$dst),
2579 [(store (X86setcc X86_COND_NE), addr:$dst)]>,
2581 def SETLr : I<0x9C, MRM0r,
2582 (outs GR8 :$dst), (ins),
2584 [(set GR8:$dst, (X86setcc X86_COND_L))]>,
2585 TB; // GR8 = < signed
2586 def SETLm : I<0x9C, MRM0m,
2587 (outs), (ins i8mem:$dst),
2589 [(store (X86setcc X86_COND_L), addr:$dst)]>,
2590 TB; // [mem8] = < signed
2591 def SETGEr : I<0x9D, MRM0r,
2592 (outs GR8 :$dst), (ins),
2594 [(set GR8:$dst, (X86setcc X86_COND_GE))]>,
2595 TB; // GR8 = >= signed
2596 def SETGEm : I<0x9D, MRM0m,
2597 (outs), (ins i8mem:$dst),
2599 [(store (X86setcc X86_COND_GE), addr:$dst)]>,
2600 TB; // [mem8] = >= signed
2601 def SETLEr : I<0x9E, MRM0r,
2602 (outs GR8 :$dst), (ins),
2604 [(set GR8:$dst, (X86setcc X86_COND_LE))]>,
2605 TB; // GR8 = <= signed
2606 def SETLEm : I<0x9E, MRM0m,
2607 (outs), (ins i8mem:$dst),
2609 [(store (X86setcc X86_COND_LE), addr:$dst)]>,
2610 TB; // [mem8] = <= signed
2611 def SETGr : I<0x9F, MRM0r,
2612 (outs GR8 :$dst), (ins),
2614 [(set GR8:$dst, (X86setcc X86_COND_G))]>,
2615 TB; // GR8 = > signed
2616 def SETGm : I<0x9F, MRM0m,
2617 (outs), (ins i8mem:$dst),
2619 [(store (X86setcc X86_COND_G), addr:$dst)]>,
2620 TB; // [mem8] = > signed
2622 def SETBr : I<0x92, MRM0r,
2623 (outs GR8 :$dst), (ins),
2625 [(set GR8:$dst, (X86setcc X86_COND_B))]>,
2626 TB; // GR8 = < unsign
2627 def SETBm : I<0x92, MRM0m,
2628 (outs), (ins i8mem:$dst),
2630 [(store (X86setcc X86_COND_B), addr:$dst)]>,
2631 TB; // [mem8] = < unsign
2632 def SETAEr : I<0x93, MRM0r,
2633 (outs GR8 :$dst), (ins),
2635 [(set GR8:$dst, (X86setcc X86_COND_AE))]>,
2636 TB; // GR8 = >= unsign
2637 def SETAEm : I<0x93, MRM0m,
2638 (outs), (ins i8mem:$dst),
2640 [(store (X86setcc X86_COND_AE), addr:$dst)]>,
2641 TB; // [mem8] = >= unsign
2642 def SETBEr : I<0x96, MRM0r,
2643 (outs GR8 :$dst), (ins),
2645 [(set GR8:$dst, (X86setcc X86_COND_BE))]>,
2646 TB; // GR8 = <= unsign
2647 def SETBEm : I<0x96, MRM0m,
2648 (outs), (ins i8mem:$dst),
2650 [(store (X86setcc X86_COND_BE), addr:$dst)]>,
2651 TB; // [mem8] = <= unsign
2652 def SETAr : I<0x97, MRM0r,
2653 (outs GR8 :$dst), (ins),
2655 [(set GR8:$dst, (X86setcc X86_COND_A))]>,
2656 TB; // GR8 = > signed
2657 def SETAm : I<0x97, MRM0m,
2658 (outs), (ins i8mem:$dst),
2660 [(store (X86setcc X86_COND_A), addr:$dst)]>,
2661 TB; // [mem8] = > signed
2663 def SETSr : I<0x98, MRM0r,
2664 (outs GR8 :$dst), (ins),
2666 [(set GR8:$dst, (X86setcc X86_COND_S))]>,
2667 TB; // GR8 = <sign bit>
2668 def SETSm : I<0x98, MRM0m,
2669 (outs), (ins i8mem:$dst),
2671 [(store (X86setcc X86_COND_S), addr:$dst)]>,
2672 TB; // [mem8] = <sign bit>
2673 def SETNSr : I<0x99, MRM0r,
2674 (outs GR8 :$dst), (ins),
2676 [(set GR8:$dst, (X86setcc X86_COND_NS))]>,
2677 TB; // GR8 = !<sign bit>
2678 def SETNSm : I<0x99, MRM0m,
2679 (outs), (ins i8mem:$dst),
2681 [(store (X86setcc X86_COND_NS), addr:$dst)]>,
2682 TB; // [mem8] = !<sign bit>
2683 def SETPr : I<0x9A, MRM0r,
2684 (outs GR8 :$dst), (ins),
2686 [(set GR8:$dst, (X86setcc X86_COND_P))]>,
2688 def SETPm : I<0x9A, MRM0m,
2689 (outs), (ins i8mem:$dst),
2691 [(store (X86setcc X86_COND_P), addr:$dst)]>,
2692 TB; // [mem8] = parity
2693 def SETNPr : I<0x9B, MRM0r,
2694 (outs GR8 :$dst), (ins),
2696 [(set GR8:$dst, (X86setcc X86_COND_NP))]>,
2697 TB; // GR8 = not parity
2698 def SETNPm : I<0x9B, MRM0m,
2699 (outs), (ins i8mem:$dst),
2701 [(store (X86setcc X86_COND_NP), addr:$dst)]>,
2702 TB; // [mem8] = not parity
2703 } // Uses = [EFLAGS]
2705 let Uses = [EFLAGS] in {
2706 def NEW_SETEr : I<0x94, MRM0r,
2707 (outs GR8 :$dst), (ins),
2709 [(set GR8:$dst, (X86setcc_new X86_COND_E, EFLAGS))]>,
2711 def NEW_SETEm : I<0x94, MRM0m,
2712 (outs), (ins i8mem:$dst),
2714 [(store (X86setcc_new X86_COND_E, EFLAGS), addr:$dst)]>,
2716 def NEW_SETNEr : I<0x95, MRM0r,
2717 (outs GR8 :$dst), (ins),
2719 [(set GR8:$dst, (X86setcc_new X86_COND_NE, EFLAGS))]>,
2721 def NEW_SETNEm : I<0x95, MRM0m,
2722 (outs), (ins i8mem:$dst),
2724 [(store (X86setcc_new X86_COND_NE, EFLAGS), addr:$dst)]>,
2726 def NEW_SETLr : I<0x9C, MRM0r,
2727 (outs GR8 :$dst), (ins),
2729 [(set GR8:$dst, (X86setcc_new X86_COND_L, EFLAGS))]>,
2730 TB; // GR8 = < signed
2731 def NEW_SETLm : I<0x9C, MRM0m,
2732 (outs), (ins i8mem:$dst),
2734 [(store (X86setcc_new X86_COND_L, EFLAGS), addr:$dst)]>,
2735 TB; // [mem8] = < signed
2736 def NEW_SETGEr : I<0x9D, MRM0r,
2737 (outs GR8 :$dst), (ins),
2739 [(set GR8:$dst, (X86setcc_new X86_COND_GE, EFLAGS))]>,
2740 TB; // GR8 = >= signed
2741 def NEW_SETGEm : I<0x9D, MRM0m,
2742 (outs), (ins i8mem:$dst),
2744 [(store (X86setcc_new X86_COND_GE, EFLAGS), addr:$dst)]>,
2745 TB; // [mem8] = >= signed
2746 def NEW_SETLEr : I<0x9E, MRM0r,
2747 (outs GR8 :$dst), (ins),
2749 [(set GR8:$dst, (X86setcc_new X86_COND_LE, EFLAGS))]>,
2750 TB; // GR8 = <= signed
2751 def NEW_SETLEm : I<0x9E, MRM0m,
2752 (outs), (ins i8mem:$dst),
2754 [(store (X86setcc_new X86_COND_LE, EFLAGS), addr:$dst)]>,
2755 TB; // [mem8] = <= signed
2756 def NEW_SETGr : I<0x9F, MRM0r,
2757 (outs GR8 :$dst), (ins),
2759 [(set GR8:$dst, (X86setcc_new X86_COND_G, EFLAGS))]>,
2760 TB; // GR8 = > signed
2761 def NEW_SETGm : I<0x9F, MRM0m,
2762 (outs), (ins i8mem:$dst),
2764 [(store (X86setcc_new X86_COND_G, EFLAGS), addr:$dst)]>,
2765 TB; // [mem8] = > signed
2767 def NEW_SETBr : I<0x92, MRM0r,
2768 (outs GR8 :$dst), (ins),
2770 [(set GR8:$dst, (X86setcc_new X86_COND_B, EFLAGS))]>,
2771 TB; // GR8 = < unsign
2772 def NEW_SETBm : I<0x92, MRM0m,
2773 (outs), (ins i8mem:$dst),
2775 [(store (X86setcc_new X86_COND_B, EFLAGS), addr:$dst)]>,
2776 TB; // [mem8] = < unsign
2777 def NEW_SETAEr : I<0x93, MRM0r,
2778 (outs GR8 :$dst), (ins),
2780 [(set GR8:$dst, (X86setcc_new X86_COND_AE, EFLAGS))]>,
2781 TB; // GR8 = >= unsign
2782 def NEW_SETAEm : I<0x93, MRM0m,
2783 (outs), (ins i8mem:$dst),
2785 [(store (X86setcc_new X86_COND_AE, EFLAGS), addr:$dst)]>,
2786 TB; // [mem8] = >= unsign
2787 def NEW_SETBEr : I<0x96, MRM0r,
2788 (outs GR8 :$dst), (ins),
2790 [(set GR8:$dst, (X86setcc_new X86_COND_BE, EFLAGS))]>,
2791 TB; // GR8 = <= unsign
2792 def NEW_SETBEm : I<0x96, MRM0m,
2793 (outs), (ins i8mem:$dst),
2795 [(store (X86setcc_new X86_COND_BE, EFLAGS), addr:$dst)]>,
2796 TB; // [mem8] = <= unsign
2797 def NEW_SETAr : I<0x97, MRM0r,
2798 (outs GR8 :$dst), (ins),
2800 [(set GR8:$dst, (X86setcc_new X86_COND_A, EFLAGS))]>,
2801 TB; // GR8 = > signed
2802 def NEW_SETAm : I<0x97, MRM0m,
2803 (outs), (ins i8mem:$dst),
2805 [(store (X86setcc_new X86_COND_A, EFLAGS), addr:$dst)]>,
2806 TB; // [mem8] = > signed
2808 def NEW_SETSr : I<0x98, MRM0r,
2809 (outs GR8 :$dst), (ins),
2811 [(set GR8:$dst, (X86setcc_new X86_COND_S, EFLAGS))]>,
2812 TB; // GR8 = <sign bit>
2813 def NEW_SETSm : I<0x98, MRM0m,
2814 (outs), (ins i8mem:$dst),
2816 [(store (X86setcc_new X86_COND_S, EFLAGS), addr:$dst)]>,
2817 TB; // [mem8] = <sign bit>
2818 def NEW_SETNSr : I<0x99, MRM0r,
2819 (outs GR8 :$dst), (ins),
2821 [(set GR8:$dst, (X86setcc_new X86_COND_NS, EFLAGS))]>,
2822 TB; // GR8 = !<sign bit>
2823 def NEW_SETNSm : I<0x99, MRM0m,
2824 (outs), (ins i8mem:$dst),
2826 [(store (X86setcc_new X86_COND_NS, EFLAGS), addr:$dst)]>,
2827 TB; // [mem8] = !<sign bit>
2828 def NEW_SETPr : I<0x9A, MRM0r,
2829 (outs GR8 :$dst), (ins),
2831 [(set GR8:$dst, (X86setcc_new X86_COND_P, EFLAGS))]>,
2833 def NEW_SETPm : I<0x9A, MRM0m,
2834 (outs), (ins i8mem:$dst),
2836 [(store (X86setcc_new X86_COND_P, EFLAGS), addr:$dst)]>,
2837 TB; // [mem8] = parity
2838 def NEW_SETNPr : I<0x9B, MRM0r,
2839 (outs GR8 :$dst), (ins),
2841 [(set GR8:$dst, (X86setcc_new X86_COND_NP, EFLAGS))]>,
2842 TB; // GR8 = not parity
2843 def NEW_SETNPm : I<0x9B, MRM0m,
2844 (outs), (ins i8mem:$dst),
2846 [(store (X86setcc_new X86_COND_NP, EFLAGS), addr:$dst)]>,
2847 TB; // [mem8] = not parity
2848 } // Uses = [EFLAGS]
2851 //def : Pat<(X86setcc_new X86_COND_E, EFLAGS), (SETEr)>;
2853 // Integer comparisons
2854 let Defs = [EFLAGS] in {
2855 def CMP8rr : I<0x38, MRMDestReg,
2856 (outs), (ins GR8 :$src1, GR8 :$src2),
2857 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2858 [(X86cmp GR8:$src1, GR8:$src2)]>;
2859 def CMP16rr : I<0x39, MRMDestReg,
2860 (outs), (ins GR16:$src1, GR16:$src2),
2861 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2862 [(X86cmp GR16:$src1, GR16:$src2)]>, OpSize;
2863 def CMP32rr : I<0x39, MRMDestReg,
2864 (outs), (ins GR32:$src1, GR32:$src2),
2865 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2866 [(X86cmp GR32:$src1, GR32:$src2)]>;
2867 def CMP8mr : I<0x38, MRMDestMem,
2868 (outs), (ins i8mem :$src1, GR8 :$src2),
2869 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2870 [(X86cmp (loadi8 addr:$src1), GR8:$src2)]>;
2871 def CMP16mr : I<0x39, MRMDestMem,
2872 (outs), (ins i16mem:$src1, GR16:$src2),
2873 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2874 [(X86cmp (loadi16 addr:$src1), GR16:$src2)]>, OpSize;
2875 def CMP32mr : I<0x39, MRMDestMem,
2876 (outs), (ins i32mem:$src1, GR32:$src2),
2877 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2878 [(X86cmp (loadi32 addr:$src1), GR32:$src2)]>;
2879 def CMP8rm : I<0x3A, MRMSrcMem,
2880 (outs), (ins GR8 :$src1, i8mem :$src2),
2881 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2882 [(X86cmp GR8:$src1, (loadi8 addr:$src2))]>;
2883 def CMP16rm : I<0x3B, MRMSrcMem,
2884 (outs), (ins GR16:$src1, i16mem:$src2),
2885 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2886 [(X86cmp GR16:$src1, (loadi16 addr:$src2))]>, OpSize;
2887 def CMP32rm : I<0x3B, MRMSrcMem,
2888 (outs), (ins GR32:$src1, i32mem:$src2),
2889 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2890 [(X86cmp GR32:$src1, (loadi32 addr:$src2))]>;
2891 def CMP8ri : Ii8<0x80, MRM7r,
2892 (outs), (ins GR8:$src1, i8imm:$src2),
2893 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2894 [(X86cmp GR8:$src1, imm:$src2)]>;
2895 def CMP16ri : Ii16<0x81, MRM7r,
2896 (outs), (ins GR16:$src1, i16imm:$src2),
2897 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2898 [(X86cmp GR16:$src1, imm:$src2)]>, OpSize;
2899 def CMP32ri : Ii32<0x81, MRM7r,
2900 (outs), (ins GR32:$src1, i32imm:$src2),
2901 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2902 [(X86cmp GR32:$src1, imm:$src2)]>;
2903 def CMP8mi : Ii8 <0x80, MRM7m,
2904 (outs), (ins i8mem :$src1, i8imm :$src2),
2905 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2906 [(X86cmp (loadi8 addr:$src1), imm:$src2)]>;
2907 def CMP16mi : Ii16<0x81, MRM7m,
2908 (outs), (ins i16mem:$src1, i16imm:$src2),
2909 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2910 [(X86cmp (loadi16 addr:$src1), imm:$src2)]>, OpSize;
2911 def CMP32mi : Ii32<0x81, MRM7m,
2912 (outs), (ins i32mem:$src1, i32imm:$src2),
2913 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2914 [(X86cmp (loadi32 addr:$src1), imm:$src2)]>;
2915 def CMP16ri8 : Ii8<0x83, MRM7r,
2916 (outs), (ins GR16:$src1, i16i8imm:$src2),
2917 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2918 [(X86cmp GR16:$src1, i16immSExt8:$src2)]>, OpSize;
2919 def CMP16mi8 : Ii8<0x83, MRM7m,
2920 (outs), (ins i16mem:$src1, i16i8imm:$src2),
2921 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2922 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2)]>, OpSize;
2923 def CMP32mi8 : Ii8<0x83, MRM7m,
2924 (outs), (ins i32mem:$src1, i32i8imm:$src2),
2925 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2926 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2)]>;
2927 def CMP32ri8 : Ii8<0x83, MRM7r,
2928 (outs), (ins GR32:$src1, i32i8imm:$src2),
2929 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2930 [(X86cmp GR32:$src1, i32immSExt8:$src2)]>;
2931 } // Defs = [EFLAGS]
2933 let Defs = [EFLAGS] in {
2934 def NEW_CMP8rr : I<0x38, MRMDestReg,
2935 (outs), (ins GR8 :$src1, GR8 :$src2),
2936 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2937 [(X86cmp_new GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2938 def NEW_CMP16rr : I<0x39, MRMDestReg,
2939 (outs), (ins GR16:$src1, GR16:$src2),
2940 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2941 [(X86cmp_new GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
2942 def NEW_CMP32rr : I<0x39, MRMDestReg,
2943 (outs), (ins GR32:$src1, GR32:$src2),
2944 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2945 [(X86cmp_new GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
2946 def NEW_CMP8mr : I<0x38, MRMDestMem,
2947 (outs), (ins i8mem :$src1, GR8 :$src2),
2948 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2949 [(X86cmp_new (loadi8 addr:$src1), GR8:$src2),
2950 (implicit EFLAGS)]>;
2951 def NEW_CMP16mr : I<0x39, MRMDestMem,
2952 (outs), (ins i16mem:$src1, GR16:$src2),
2953 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2954 [(X86cmp_new (loadi16 addr:$src1), GR16:$src2),
2955 (implicit EFLAGS)]>, OpSize;
2956 def NEW_CMP32mr : I<0x39, MRMDestMem,
2957 (outs), (ins i32mem:$src1, GR32:$src2),
2958 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2959 [(X86cmp_new (loadi32 addr:$src1), GR32:$src2),
2960 (implicit EFLAGS)]>;
2961 def NEW_CMP8rm : I<0x3A, MRMSrcMem,
2962 (outs), (ins GR8 :$src1, i8mem :$src2),
2963 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2964 [(X86cmp_new GR8:$src1, (loadi8 addr:$src2)),
2965 (implicit EFLAGS)]>;
2966 def NEW_CMP16rm : I<0x3B, MRMSrcMem,
2967 (outs), (ins GR16:$src1, i16mem:$src2),
2968 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2969 [(X86cmp_new GR16:$src1, (loadi16 addr:$src2)),
2970 (implicit EFLAGS)]>, OpSize;
2971 def NEW_CMP32rm : I<0x3B, MRMSrcMem,
2972 (outs), (ins GR32:$src1, i32mem:$src2),
2973 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2974 [(X86cmp_new GR32:$src1, (loadi32 addr:$src2)),
2975 (implicit EFLAGS)]>;
2976 def NEW_CMP8ri : Ii8<0x80, MRM7r,
2977 (outs), (ins GR8:$src1, i8imm:$src2),
2978 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2979 [(X86cmp_new GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
2980 def NEW_CMP16ri : Ii16<0x81, MRM7r,
2981 (outs), (ins GR16:$src1, i16imm:$src2),
2982 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2983 [(X86cmp_new GR16:$src1, imm:$src2),
2984 (implicit EFLAGS)]>, OpSize;
2985 def NEW_CMP32ri : Ii32<0x81, MRM7r,
2986 (outs), (ins GR32:$src1, i32imm:$src2),
2987 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2988 [(X86cmp_new GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
2989 def NEW_CMP8mi : Ii8 <0x80, MRM7m,
2990 (outs), (ins i8mem :$src1, i8imm :$src2),
2991 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2992 [(X86cmp_new (loadi8 addr:$src1), imm:$src2),
2993 (implicit EFLAGS)]>;
2994 def NEW_CMP16mi : Ii16<0x81, MRM7m,
2995 (outs), (ins i16mem:$src1, i16imm:$src2),
2996 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2997 [(X86cmp_new (loadi16 addr:$src1), imm:$src2),
2998 (implicit EFLAGS)]>, OpSize;
2999 def NEW_CMP32mi : Ii32<0x81, MRM7m,
3000 (outs), (ins i32mem:$src1, i32imm:$src2),
3001 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3002 [(X86cmp_new (loadi32 addr:$src1), imm:$src2),
3003 (implicit EFLAGS)]>;
3004 def NEW_CMP16ri8 : Ii8<0x83, MRM7r,
3005 (outs), (ins GR16:$src1, i16i8imm:$src2),
3006 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3007 [(X86cmp_new GR16:$src1, i16immSExt8:$src2),
3008 (implicit EFLAGS)]>, OpSize;
3009 def NEW_CMP16mi8 : Ii8<0x83, MRM7m,
3010 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3011 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3012 [(X86cmp_new (loadi16 addr:$src1), i16immSExt8:$src2),
3013 (implicit EFLAGS)]>, OpSize;
3014 def NEW_CMP32mi8 : Ii8<0x83, MRM7m,
3015 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3016 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3017 [(X86cmp_new (loadi32 addr:$src1), i32immSExt8:$src2),
3018 (implicit EFLAGS)]>;
3019 def NEW_CMP32ri8 : Ii8<0x83, MRM7r,
3020 (outs), (ins GR32:$src1, i32i8imm:$src2),
3021 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3022 [(X86cmp_new GR32:$src1, i32immSExt8:$src2),
3023 (implicit EFLAGS)]>;
3024 } // Defs = [EFLAGS]
3026 // Sign/Zero extenders
3027 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3028 "movs{bw|x}\t{$src, $dst|$dst, $src}",
3029 [(set GR16:$dst, (sext GR8:$src))]>, TB, OpSize;
3030 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3031 "movs{bw|x}\t{$src, $dst|$dst, $src}",
3032 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize;
3033 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3034 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3035 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3036 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3037 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3038 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3039 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3040 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3041 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3042 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3043 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3044 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3046 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3047 "movz{bw|x}\t{$src, $dst|$dst, $src}",
3048 [(set GR16:$dst, (zext GR8:$src))]>, TB, OpSize;
3049 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3050 "movz{bw|x}\t{$src, $dst|$dst, $src}",
3051 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize;
3052 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3053 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3054 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3055 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3056 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3057 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3058 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3059 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3060 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3061 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3062 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3063 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3065 let Defs = [AX], Uses = [AL] in
3066 def CBW : I<0x98, RawFrm, (outs), (ins),
3067 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3068 let Defs = [EAX], Uses = [AX] in
3069 def CWDE : I<0x98, RawFrm, (outs), (ins),
3070 "{cwtl|cwde}", []>; // EAX = signext(AX)
3072 let Defs = [AX,DX], Uses = [AX] in
3073 def CWD : I<0x99, RawFrm, (outs), (ins),
3074 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3075 let Defs = [EAX,EDX], Uses = [EAX] in
3076 def CDQ : I<0x99, RawFrm, (outs), (ins),
3077 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3080 //===----------------------------------------------------------------------===//
3081 // Alias Instructions
3082 //===----------------------------------------------------------------------===//
3084 // Alias instructions that map movr0 to xor.
3085 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3086 let Defs = [EFLAGS], isReMaterializable = 1 in {
3087 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
3088 "xor{b}\t$dst, $dst",
3089 [(set GR8:$dst, 0)]>;
3090 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3091 "xor{w}\t$dst, $dst",
3092 [(set GR16:$dst, 0)]>, OpSize;
3093 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
3094 "xor{l}\t$dst, $dst",
3095 [(set GR32:$dst, 0)]>;
3098 // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
3099 // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
3100 def MOV16to16_ : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16:$src),
3101 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
3102 def MOV32to32_ : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32:$src),
3103 "mov{l}\t{$src, $dst|$dst, $src}", []>;
3105 def MOV16_rr : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16_:$src),
3106 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
3107 def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src),
3108 "mov{l}\t{$src, $dst|$dst, $src}", []>;
3110 def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src),
3111 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
3112 def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src),
3113 "mov{l}\t{$src, $dst|$dst, $src}", []>;
3115 def MOV16_mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16_:$src),
3116 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
3117 def MOV32_mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32_:$src),
3118 "mov{l}\t{$src, $dst|$dst, $src}", []>;
3120 //===----------------------------------------------------------------------===//
3121 // Thread Local Storage Instructions
3125 def TLS_addr : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
3126 "leal\t${sym:mem}(,%ebx,1), $dst",
3127 [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
3129 let AddedComplexity = 10 in
3130 def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
3131 "movl\t%gs:($src), $dst",
3132 [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
3134 let AddedComplexity = 15 in
3135 def TLS_gs_ri : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
3136 "movl\t%gs:${src:mem}, $dst",
3138 (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>;
3140 def TLS_tp : I<0, Pseudo, (outs GR32:$dst), (ins),
3141 "movl\t%gs:0, $dst",
3142 [(set GR32:$dst, X86TLStp)]>;
3144 //===----------------------------------------------------------------------===//
3145 // DWARF Pseudo Instructions
3148 def DWARF_LOC : I<0, Pseudo, (outs),
3149 (ins i32imm:$line, i32imm:$col, i32imm:$file),
3150 ".loc\t${file:debug} ${line:debug} ${col:debug}",
3151 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
3154 //===----------------------------------------------------------------------===//
3155 // EH Pseudo Instructions
3157 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3159 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3160 "ret\t#eh_return, addr: $addr",
3161 [(X86ehret GR32:$addr)]>;
3165 //===----------------------------------------------------------------------===//
3166 // Non-Instruction Patterns
3167 //===----------------------------------------------------------------------===//
3169 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
3170 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
3171 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
3172 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)), (MOV32ri tglobaltlsaddr:$dst)>;
3173 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
3174 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
3176 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
3177 (ADD32ri GR32:$src1, tconstpool:$src2)>;
3178 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
3179 (ADD32ri GR32:$src1, tjumptable:$src2)>;
3180 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
3181 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
3182 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
3183 (ADD32ri GR32:$src1, texternalsym:$src2)>;
3185 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
3186 (MOV32mi addr:$dst, tglobaladdr:$src)>;
3187 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
3188 (MOV32mi addr:$dst, texternalsym:$src)>;
3191 def : Pat<(X86tailcall GR32:$dst),
3192 (CALL32r GR32:$dst)>;
3194 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
3195 (CALLpcrel32 tglobaladdr:$dst)>;
3196 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
3197 (CALLpcrel32 texternalsym:$dst)>;
3199 def : Pat<(X86call (i32 tglobaladdr:$dst)),
3200 (CALLpcrel32 tglobaladdr:$dst)>;
3201 def : Pat<(X86call (i32 texternalsym:$dst)),
3202 (CALLpcrel32 texternalsym:$dst)>;
3204 // X86 specific add which produces a flag.
3205 def : Pat<(addc GR32:$src1, GR32:$src2),
3206 (ADD32rr GR32:$src1, GR32:$src2)>;
3207 def : Pat<(addc GR32:$src1, (load addr:$src2)),
3208 (ADD32rm GR32:$src1, addr:$src2)>;
3209 def : Pat<(addc GR32:$src1, imm:$src2),
3210 (ADD32ri GR32:$src1, imm:$src2)>;
3211 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
3212 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3214 def : Pat<(subc GR32:$src1, GR32:$src2),
3215 (SUB32rr GR32:$src1, GR32:$src2)>;
3216 def : Pat<(subc GR32:$src1, (load addr:$src2)),
3217 (SUB32rm GR32:$src1, addr:$src2)>;
3218 def : Pat<(subc GR32:$src1, imm:$src2),
3219 (SUB32ri GR32:$src1, imm:$src2)>;
3220 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
3221 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3223 def : Pat<(truncstorei1 (i8 imm:$src), addr:$dst),
3224 (MOV8mi addr:$dst, imm:$src)>;
3225 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
3226 (MOV8mr addr:$dst, GR8:$src)>;
3230 // TEST R,R is smaller than CMP R,0
3231 def : Pat<(X86cmp GR8:$src1, 0),
3232 (TEST8rr GR8:$src1, GR8:$src1)>;
3233 def : Pat<(X86cmp GR16:$src1, 0),
3234 (TEST16rr GR16:$src1, GR16:$src1)>;
3235 def : Pat<(X86cmp GR32:$src1, 0),
3236 (TEST32rr GR32:$src1, GR32:$src1)>;
3238 def : Pat<(parallel (X86cmp_new GR8:$src1, 0), (implicit EFLAGS)),
3239 (NEW_TEST8rr GR8:$src1, GR8:$src1)>;
3240 def : Pat<(parallel (X86cmp_new GR16:$src1, 0), (implicit EFLAGS)),
3241 (NEW_TEST16rr GR16:$src1, GR16:$src1)>;
3242 def : Pat<(parallel (X86cmp_new GR32:$src1, 0), (implicit EFLAGS)),
3243 (NEW_TEST32rr GR32:$src1, GR32:$src1)>;
3245 // {s|z}extload bool -> {s|z}extload byte
3246 def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>;
3247 def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>;
3248 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3249 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3250 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3252 // extload bool -> extload byte
3253 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3254 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3255 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3256 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
3257 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
3258 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
3261 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
3262 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
3263 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
3264 def : Pat<(i16 (anyext (loadi8 addr:$src))), (MOVZX16rm8 addr:$src)>;
3265 def : Pat<(i32 (anyext (loadi8 addr:$src))), (MOVZX32rm8 addr:$src)>;
3266 def : Pat<(i32 (anyext (loadi16 addr:$src))), (MOVZX32rm16 addr:$src)>;
3268 //===----------------------------------------------------------------------===//
3270 //===----------------------------------------------------------------------===//
3272 // (shl x, 1) ==> (add x, x)
3273 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
3274 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
3275 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
3277 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
3278 def : Pat<(or (srl GR32:$src1, CL:$amt),
3279 (shl GR32:$src2, (sub 32, CL:$amt))),
3280 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3282 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
3283 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3284 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3286 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
3287 def : Pat<(or (shl GR32:$src1, CL:$amt),
3288 (srl GR32:$src2, (sub 32, CL:$amt))),
3289 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3291 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
3292 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3293 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3295 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
3296 def : Pat<(or (srl GR16:$src1, CL:$amt),
3297 (shl GR16:$src2, (sub 16, CL:$amt))),
3298 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3300 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
3301 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3302 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3304 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
3305 def : Pat<(or (shl GR16:$src1, CL:$amt),
3306 (srl GR16:$src2, (sub 16, CL:$amt))),
3307 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3309 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
3310 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3311 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3314 //===----------------------------------------------------------------------===//
3315 // Floating Point Stack Support
3316 //===----------------------------------------------------------------------===//
3318 include "X86InstrFPStack.td"
3320 //===----------------------------------------------------------------------===//
3322 //===----------------------------------------------------------------------===//
3324 include "X86InstrX86-64.td"
3326 //===----------------------------------------------------------------------===//
3327 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
3328 //===----------------------------------------------------------------------===//
3330 include "X86InstrMMX.td"
3332 //===----------------------------------------------------------------------===//
3333 // XMM Floating point support (requires SSE / SSE2)
3334 //===----------------------------------------------------------------------===//
3336 include "X86InstrSSE.td"