1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
35 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
49 // RES1, RES2, FLAGS = op LHS, RHS
50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
54 SDTCisInt<0>, SDTCisVT<1, i32>]>;
55 def SDTX86BrCond : SDTypeProfile<0, 3,
56 [SDTCisVT<0, OtherVT>,
57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 def SDTX86SetCC : SDTypeProfile<1, 2,
61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
62 def SDTX86SetCC_C : SDTypeProfile<1, 2,
64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
66 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
68 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
70 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
72 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
74 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
75 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
76 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
78 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
79 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
82 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
84 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
88 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
94 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
96 def SDTX86Void : SDTypeProfile<0, 0, []>;
98 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
100 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
102 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
104 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
106 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
108 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
110 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
112 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
114 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
116 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
117 [SDNPHasChain,SDNPSideEffect]>;
118 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
120 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
122 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
126 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
127 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
128 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
129 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
131 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
132 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
134 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
135 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
137 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
138 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
140 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
142 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
143 [SDNPHasChain, SDNPSideEffect]>;
145 def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand,
146 [SDNPHasChain, SDNPSideEffect]>;
148 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
149 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
150 SDNPMayLoad, SDNPMemOperand]>;
151 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
152 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
153 SDNPMayLoad, SDNPMemOperand]>;
154 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
155 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
156 SDNPMayLoad, SDNPMemOperand]>;
158 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
159 [SDNPHasChain, SDNPMayStore,
160 SDNPMayLoad, SDNPMemOperand]>;
161 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
162 [SDNPHasChain, SDNPMayStore,
163 SDNPMayLoad, SDNPMemOperand]>;
164 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
165 [SDNPHasChain, SDNPMayStore,
166 SDNPMayLoad, SDNPMemOperand]>;
167 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
168 [SDNPHasChain, SDNPMayStore,
169 SDNPMayLoad, SDNPMemOperand]>;
170 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
171 [SDNPHasChain, SDNPMayStore,
172 SDNPMayLoad, SDNPMemOperand]>;
173 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
174 [SDNPHasChain, SDNPMayStore,
175 SDNPMayLoad, SDNPMemOperand]>;
176 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
177 [SDNPHasChain, SDNPMayStore,
178 SDNPMayLoad, SDNPMemOperand]>;
179 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
180 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
182 def X86vastart_save_xmm_regs :
183 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
184 SDT_X86VASTART_SAVE_XMM_REGS,
185 [SDNPHasChain, SDNPVariadic]>;
187 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
188 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
190 def X86callseq_start :
191 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
192 [SDNPHasChain, SDNPOutGlue]>;
194 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
195 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
197 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
198 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
201 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
202 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
203 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
204 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
207 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
208 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
210 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
211 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
213 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
214 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
216 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
217 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
219 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
222 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
223 SDTypeProfile<1, 1, [SDTCisInt<0>,
225 [SDNPHasChain, SDNPSideEffect]>;
226 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
227 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
228 [SDNPHasChain, SDNPSideEffect]>;
230 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
231 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
233 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
235 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
236 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
238 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
240 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
241 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
243 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
244 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
245 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
247 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
249 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
251 def X86andn_flag : SDNode<"X86ISD::ANDN", SDTBinaryArithWithFlags>;
253 def X86blsi : SDNode<"X86ISD::BLSI", SDTIntUnaryOp>;
254 def X86blsmsk : SDNode<"X86ISD::BLSMSK", SDTIntUnaryOp>;
255 def X86blsr : SDNode<"X86ISD::BLSR", SDTIntUnaryOp>;
257 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
259 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
260 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
262 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
265 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
266 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
268 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL,
269 [SDNPHasChain, SDNPOutGlue]>;
271 //===----------------------------------------------------------------------===//
272 // X86 Operand Definitions.
275 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
276 // the index operand of an address, to conform to x86 encoding restrictions.
277 def ptr_rc_nosp : PointerLikeRegClass<1>;
279 // *mem - Operand definitions for the funky X86 addressing mode operands.
281 def X86MemAsmOperand : AsmOperandClass {
282 let Name = "Mem"; let PredicateMethod = "isMem";
284 def X86Mem8AsmOperand : AsmOperandClass {
285 let Name = "Mem8"; let PredicateMethod = "isMem8";
287 def X86Mem16AsmOperand : AsmOperandClass {
288 let Name = "Mem16"; let PredicateMethod = "isMem16";
290 def X86Mem32AsmOperand : AsmOperandClass {
291 let Name = "Mem32"; let PredicateMethod = "isMem32";
293 def X86Mem64AsmOperand : AsmOperandClass {
294 let Name = "Mem64"; let PredicateMethod = "isMem64";
296 def X86Mem80AsmOperand : AsmOperandClass {
297 let Name = "Mem80"; let PredicateMethod = "isMem80";
299 def X86Mem128AsmOperand : AsmOperandClass {
300 let Name = "Mem128"; let PredicateMethod = "isMem128";
302 def X86Mem256AsmOperand : AsmOperandClass {
303 let Name = "Mem256"; let PredicateMethod = "isMem256";
306 // Gather mem operands
307 def X86MemVX32Operand : AsmOperandClass {
308 let Name = "MemVX32"; let PredicateMethod = "isMemVX32";
310 def X86MemVY32Operand : AsmOperandClass {
311 let Name = "MemVY32"; let PredicateMethod = "isMemVY32";
313 def X86MemVX64Operand : AsmOperandClass {
314 let Name = "MemVX64"; let PredicateMethod = "isMemVX64";
316 def X86MemVY64Operand : AsmOperandClass {
317 let Name = "MemVY64"; let PredicateMethod = "isMemVY64";
320 def X86AbsMemAsmOperand : AsmOperandClass {
322 let SuperClasses = [X86MemAsmOperand];
324 class X86MemOperand<string printMethod> : Operand<iPTR> {
325 let PrintMethod = printMethod;
326 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
327 let ParserMatchClass = X86MemAsmOperand;
330 let OperandType = "OPERAND_MEMORY" in {
331 def opaque32mem : X86MemOperand<"printopaquemem">;
332 def opaque48mem : X86MemOperand<"printopaquemem">;
333 def opaque80mem : X86MemOperand<"printopaquemem">;
334 def opaque512mem : X86MemOperand<"printopaquemem">;
336 def i8mem : X86MemOperand<"printi8mem"> {
337 let ParserMatchClass = X86Mem8AsmOperand; }
338 def i16mem : X86MemOperand<"printi16mem"> {
339 let ParserMatchClass = X86Mem16AsmOperand; }
340 def i32mem : X86MemOperand<"printi32mem"> {
341 let ParserMatchClass = X86Mem32AsmOperand; }
342 def i64mem : X86MemOperand<"printi64mem"> {
343 let ParserMatchClass = X86Mem64AsmOperand; }
344 def i128mem : X86MemOperand<"printi128mem"> {
345 let ParserMatchClass = X86Mem128AsmOperand; }
346 def i256mem : X86MemOperand<"printi256mem"> {
347 let ParserMatchClass = X86Mem256AsmOperand; }
348 def f32mem : X86MemOperand<"printf32mem"> {
349 let ParserMatchClass = X86Mem32AsmOperand; }
350 def f64mem : X86MemOperand<"printf64mem"> {
351 let ParserMatchClass = X86Mem64AsmOperand; }
352 def f80mem : X86MemOperand<"printf80mem"> {
353 let ParserMatchClass = X86Mem80AsmOperand; }
354 def f128mem : X86MemOperand<"printf128mem"> {
355 let ParserMatchClass = X86Mem128AsmOperand; }
356 def f256mem : X86MemOperand<"printf256mem">{
357 let ParserMatchClass = X86Mem256AsmOperand; }
359 // Gather mem operands
360 def vx32mem : X86MemOperand<"printi32mem">{
361 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
362 let ParserMatchClass = X86MemVX32Operand; }
363 def vy32mem : X86MemOperand<"printi32mem">{
364 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
365 let ParserMatchClass = X86MemVY32Operand; }
366 def vx64mem : X86MemOperand<"printi64mem">{
367 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
368 let ParserMatchClass = X86MemVX64Operand; }
369 def vy64mem : X86MemOperand<"printi64mem">{
370 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
371 let ParserMatchClass = X86MemVY64Operand; }
374 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
375 // plain GR64, so that it doesn't potentially require a REX prefix.
376 def i8mem_NOREX : Operand<i64> {
377 let PrintMethod = "printi8mem";
378 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
379 let ParserMatchClass = X86Mem8AsmOperand;
380 let OperandType = "OPERAND_MEMORY";
383 // GPRs available for tailcall.
384 // It represents GR32_TC, GR64_TC or GR64_TCW64.
385 def ptr_rc_tailcall : PointerLikeRegClass<2>;
387 // Special i32mem for addresses of load folding tail calls. These are not
388 // allowed to use callee-saved registers since they must be scheduled
389 // after callee-saved register are popped.
390 def i32mem_TC : Operand<i32> {
391 let PrintMethod = "printi32mem";
392 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
394 let ParserMatchClass = X86Mem32AsmOperand;
395 let OperandType = "OPERAND_MEMORY";
398 // Special i64mem for addresses of load folding tail calls. These are not
399 // allowed to use callee-saved registers since they must be scheduled
400 // after callee-saved register are popped.
401 def i64mem_TC : Operand<i64> {
402 let PrintMethod = "printi64mem";
403 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
404 ptr_rc_tailcall, i32imm, i8imm);
405 let ParserMatchClass = X86Mem64AsmOperand;
406 let OperandType = "OPERAND_MEMORY";
409 let OperandType = "OPERAND_PCREL",
410 ParserMatchClass = X86AbsMemAsmOperand,
411 PrintMethod = "printPCRelImm" in {
412 def i32imm_pcrel : Operand<i32>;
413 def i16imm_pcrel : Operand<i16>;
415 def offset8 : Operand<i64>;
416 def offset16 : Operand<i64>;
417 def offset32 : Operand<i64>;
418 def offset64 : Operand<i64>;
420 // Branch targets have OtherVT type and print as pc-relative values.
421 def brtarget : Operand<OtherVT>;
422 def brtarget8 : Operand<OtherVT>;
426 def SSECC : Operand<i8> {
427 let PrintMethod = "printSSECC";
428 let OperandType = "OPERAND_IMMEDIATE";
431 def AVXCC : Operand<i8> {
432 let PrintMethod = "printAVXCC";
433 let OperandType = "OPERAND_IMMEDIATE";
436 class ImmSExtAsmOperandClass : AsmOperandClass {
437 let SuperClasses = [ImmAsmOperand];
438 let RenderMethod = "addImmOperands";
441 class ImmZExtAsmOperandClass : AsmOperandClass {
442 let SuperClasses = [ImmAsmOperand];
443 let RenderMethod = "addImmOperands";
446 // Sign-extended immediate classes. We don't need to define the full lattice
447 // here because there is no instruction with an ambiguity between ImmSExti64i32
450 // The strange ranges come from the fact that the assembler always works with
451 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
452 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
455 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
456 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
457 let Name = "ImmSExti64i32";
460 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
461 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
462 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
463 let Name = "ImmSExti16i8";
464 let SuperClasses = [ImmSExti64i32AsmOperand];
467 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
468 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
469 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
470 let Name = "ImmSExti32i8";
474 def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass {
475 let Name = "ImmZExtu32u8";
480 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
481 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
482 let Name = "ImmSExti64i8";
483 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
484 ImmSExti64i32AsmOperand];
487 // A couple of more descriptive operand definitions.
488 // 16-bits but only 8 bits are significant.
489 def i16i8imm : Operand<i16> {
490 let ParserMatchClass = ImmSExti16i8AsmOperand;
491 let OperandType = "OPERAND_IMMEDIATE";
493 // 32-bits but only 8 bits are significant.
494 def i32i8imm : Operand<i32> {
495 let ParserMatchClass = ImmSExti32i8AsmOperand;
496 let OperandType = "OPERAND_IMMEDIATE";
498 // 32-bits but only 8 bits are significant, and those 8 bits are unsigned.
499 def u32u8imm : Operand<i32> {
500 let ParserMatchClass = ImmZExtu32u8AsmOperand;
501 let OperandType = "OPERAND_IMMEDIATE";
504 // 64-bits but only 32 bits are significant.
505 def i64i32imm : Operand<i64> {
506 let ParserMatchClass = ImmSExti64i32AsmOperand;
507 let OperandType = "OPERAND_IMMEDIATE";
510 // 64-bits but only 32 bits are significant, and those bits are treated as being
512 def i64i32imm_pcrel : Operand<i64> {
513 let PrintMethod = "printPCRelImm";
514 let ParserMatchClass = X86AbsMemAsmOperand;
515 let OperandType = "OPERAND_PCREL";
518 // 64-bits but only 8 bits are significant.
519 def i64i8imm : Operand<i64> {
520 let ParserMatchClass = ImmSExti64i8AsmOperand;
521 let OperandType = "OPERAND_IMMEDIATE";
524 def lea64_32mem : Operand<i32> {
525 let PrintMethod = "printi32mem";
526 let AsmOperandLowerMethod = "lower_lea64_32mem";
527 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm);
528 let ParserMatchClass = X86MemAsmOperand;
531 // Memory operands that use 64-bit pointers in both ILP32 and LP64.
532 def lea64mem : Operand<i64> {
533 let PrintMethod = "printi64mem";
534 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
535 let ParserMatchClass = X86MemAsmOperand;
539 //===----------------------------------------------------------------------===//
540 // X86 Complex Pattern Definitions.
543 // Define X86 specific addressing mode.
544 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
545 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
546 [add, sub, mul, X86mul_imm, shl, or, frameindex],
548 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
549 def lea64_32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
550 [add, sub, mul, X86mul_imm, shl, or,
551 frameindex, X86WrapperRIP],
554 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
555 [tglobaltlsaddr], []>;
557 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
558 [tglobaltlsaddr], []>;
560 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
561 [add, sub, mul, X86mul_imm, shl, or, frameindex,
564 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
565 [tglobaltlsaddr], []>;
567 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
568 [tglobaltlsaddr], []>;
570 //===----------------------------------------------------------------------===//
571 // X86 Instruction Predicate Definitions.
572 def HasCMov : Predicate<"Subtarget->hasCMov()">;
573 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
575 def HasMMX : Predicate<"Subtarget->hasMMX()">;
576 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
577 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
578 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
579 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
580 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
581 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
582 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
583 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
584 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
585 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
586 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
587 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
588 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
589 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
590 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
591 def HasAVX : Predicate<"Subtarget->hasAVX()">;
592 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
593 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
595 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
596 def HasAES : Predicate<"Subtarget->hasAES()">;
597 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
598 def HasFMA : Predicate<"Subtarget->hasFMA()">;
599 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
600 def HasXOP : Predicate<"Subtarget->hasXOP()">;
601 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
602 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
603 def HasF16C : Predicate<"Subtarget->hasF16C()">;
604 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
605 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
606 def HasBMI : Predicate<"Subtarget->hasBMI()">;
607 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
608 def HasRTM : Predicate<"Subtarget->hasRTM()">;
609 def HasHLE : Predicate<"Subtarget->hasHLE()">;
610 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
611 def HasADX : Predicate<"Subtarget->hasADX()">;
612 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
613 def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
614 def HasPrefetchW : Predicate<"Subtarget->has3DNow() || Subtarget->hasPRFCHW()">;
615 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
616 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
617 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
618 def In32BitMode : Predicate<"!Subtarget->is64Bit()">,
619 AssemblerPredicate<"!Mode64Bit", "32-bit mode">;
620 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
621 AssemblerPredicate<"Mode64Bit", "64-bit mode">;
622 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
623 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
624 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
625 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
626 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
627 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
628 "TM.getCodeModel() != CodeModel::Kernel">;
629 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
630 "TM.getCodeModel() == CodeModel::Kernel">;
631 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
632 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
633 def OptForSize : Predicate<"OptForSize">;
634 def OptForSpeed : Predicate<"!OptForSize">;
635 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
636 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
637 def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">;
639 //===----------------------------------------------------------------------===//
640 // X86 Instruction Format Definitions.
643 include "X86InstrFormats.td"
645 //===----------------------------------------------------------------------===//
646 // Pattern fragments.
649 // X86 specific condition code. These correspond to CondCode in
650 // X86InstrInfo.h. They must be kept in synch.
651 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
652 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
653 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
654 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
655 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
656 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
657 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
658 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
659 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
660 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
661 def X86_COND_NO : PatLeaf<(i8 10)>;
662 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
663 def X86_COND_NS : PatLeaf<(i8 12)>;
664 def X86_COND_O : PatLeaf<(i8 13)>;
665 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
666 def X86_COND_S : PatLeaf<(i8 15)>;
668 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
669 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
670 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
671 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
674 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
677 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
679 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
681 def i64immZExt32SExt8 : ImmLeaf<i64, [{
682 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
685 // Helper fragments for loads.
686 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
687 // known to be 32-bit aligned or better. Ditto for i8 to i16.
688 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
689 LoadSDNode *LD = cast<LoadSDNode>(N);
690 ISD::LoadExtType ExtType = LD->getExtensionType();
691 if (ExtType == ISD::NON_EXTLOAD)
693 if (ExtType == ISD::EXTLOAD)
694 return LD->getAlignment() >= 2 && !LD->isVolatile();
698 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
699 LoadSDNode *LD = cast<LoadSDNode>(N);
700 ISD::LoadExtType ExtType = LD->getExtensionType();
701 if (ExtType == ISD::EXTLOAD)
702 return LD->getAlignment() >= 2 && !LD->isVolatile();
706 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
707 LoadSDNode *LD = cast<LoadSDNode>(N);
708 ISD::LoadExtType ExtType = LD->getExtensionType();
709 if (ExtType == ISD::NON_EXTLOAD)
711 if (ExtType == ISD::EXTLOAD)
712 return LD->getAlignment() >= 4 && !LD->isVolatile();
716 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
717 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
718 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
719 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
720 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
722 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
723 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
724 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
725 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
726 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
727 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
729 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
730 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
731 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
732 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
733 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
734 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
735 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
736 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
737 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
738 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
740 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
741 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
742 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
743 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
744 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
745 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
746 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
747 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
748 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
749 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
752 // An 'and' node with a single use.
753 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
754 return N->hasOneUse();
756 // An 'srl' node with a single use.
757 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
758 return N->hasOneUse();
760 // An 'trunc' node with a single use.
761 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
762 return N->hasOneUse();
765 //===----------------------------------------------------------------------===//
770 let neverHasSideEffects = 1, SchedRW = [WriteZero] in {
771 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
772 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
773 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize;
774 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
775 "nop{l}\t$zero", [], IIC_NOP>, TB;
779 // Constructing a stack frame.
780 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
781 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
783 let SchedRW = [WriteALU] in {
784 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
785 def LEAVE : I<0xC9, RawFrm,
786 (outs), (ins), "leave", [], IIC_LEAVE>,
787 Requires<[In32BitMode]>;
789 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
790 def LEAVE64 : I<0xC9, RawFrm,
791 (outs), (ins), "leave", [], IIC_LEAVE>,
792 Requires<[In64BitMode]>;
795 //===----------------------------------------------------------------------===//
796 // Miscellaneous Instructions.
799 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
800 let mayLoad = 1, SchedRW = [WriteLoad] in {
801 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
802 IIC_POP_REG16>, OpSize;
803 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
805 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
806 IIC_POP_REG>, OpSize;
807 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", [],
808 IIC_POP_MEM>, OpSize;
809 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
811 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", [],
814 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, OpSize;
815 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
816 Requires<[In32BitMode]>;
817 } // mayLoad, SchedRW
819 let mayStore = 1, SchedRW = [WriteStore] in {
820 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
821 IIC_PUSH_REG>, OpSize;
822 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
824 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
825 IIC_PUSH_REG>, OpSize;
826 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
829 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
831 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
834 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
835 "push{l}\t$imm", [], IIC_PUSH_IMM>;
836 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
837 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize;
838 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
839 "push{l}\t$imm", [], IIC_PUSH_IMM>;
841 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
843 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
844 Requires<[In32BitMode]>;
846 } // mayStore, SchedRW
849 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
850 let mayLoad = 1, SchedRW = [WriteLoad] in {
851 def POP64r : I<0x58, AddRegFrm,
852 (outs GR64:$reg), (ins), "pop{q}\t$reg", [], IIC_POP_REG>;
853 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
855 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", [],
857 } // mayLoad, SchedRW
858 let mayStore = 1, SchedRW = [WriteStore] in {
859 def PUSH64r : I<0x50, AddRegFrm,
860 (outs), (ins GR64:$reg), "push{q}\t$reg", [], IIC_PUSH_REG>;
861 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
863 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
865 } // mayStore, SchedRW
868 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1,
869 SchedRW = [WriteStore] in {
870 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
871 "push{q}\t$imm", [], IIC_PUSH_IMM>;
872 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
873 "push{q}\t$imm", [], IIC_PUSH_IMM>;
874 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
875 "push{q}\t$imm", [], IIC_PUSH_IMM>;
878 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
879 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
880 Requires<[In64BitMode]>, Sched<[WriteLoad]>;
881 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
882 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
883 Requires<[In64BitMode]>, Sched<[WriteStore]>;
885 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
886 mayLoad = 1, neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
887 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l|d}", [], IIC_POP_A>,
888 Requires<[In32BitMode]>;
890 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
891 mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
892 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l|d}", [], IIC_PUSH_A>,
893 Requires<[In32BitMode]>;
896 let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
898 def BSWAP32r : I<0xC8, AddRegFrm,
899 (outs GR32:$dst), (ins GR32:$src),
901 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, TB;
903 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
905 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
906 } // Constraints = "$src = $dst", SchedRW
908 // Bit scan instructions.
909 let Defs = [EFLAGS] in {
910 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
911 "bsf{w}\t{$src, $dst|$dst, $src}",
912 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
913 IIC_BSF>, TB, OpSize, Sched<[WriteShift]>;
914 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
915 "bsf{w}\t{$src, $dst|$dst, $src}",
916 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
917 IIC_BSF>, TB, OpSize, Sched<[WriteShiftLd]>;
918 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
919 "bsf{l}\t{$src, $dst|$dst, $src}",
920 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))], IIC_BSF>, TB,
922 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
923 "bsf{l}\t{$src, $dst|$dst, $src}",
924 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
925 IIC_BSF>, TB, Sched<[WriteShiftLd]>;
926 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
927 "bsf{q}\t{$src, $dst|$dst, $src}",
928 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
929 IIC_BSF>, TB, Sched<[WriteShift]>;
930 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
931 "bsf{q}\t{$src, $dst|$dst, $src}",
932 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
933 IIC_BSF>, TB, Sched<[WriteShiftLd]>;
935 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
936 "bsr{w}\t{$src, $dst|$dst, $src}",
937 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))], IIC_BSR>,
938 TB, OpSize, Sched<[WriteShift]>;
939 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
940 "bsr{w}\t{$src, $dst|$dst, $src}",
941 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
943 OpSize, Sched<[WriteShiftLd]>;
944 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
945 "bsr{l}\t{$src, $dst|$dst, $src}",
946 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))], IIC_BSR>, TB,
948 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
949 "bsr{l}\t{$src, $dst|$dst, $src}",
950 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
951 IIC_BSR>, TB, Sched<[WriteShiftLd]>;
952 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
953 "bsr{q}\t{$src, $dst|$dst, $src}",
954 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], IIC_BSR>, TB,
956 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
957 "bsr{q}\t{$src, $dst|$dst, $src}",
958 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
959 IIC_BSR>, TB, Sched<[WriteShiftLd]>;
962 let SchedRW = [WriteMicrocoded] in {
963 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
964 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
965 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", [], IIC_MOVS>;
966 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", [], IIC_MOVS>, OpSize;
967 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", [], IIC_MOVS>;
968 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", [], IIC_MOVS>;
971 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
972 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
973 def STOSB : I<0xAA, RawFrm, (outs), (ins), "stosb", [], IIC_STOS>;
974 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
975 def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", [], IIC_STOS>, OpSize;
976 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
977 def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", [], IIC_STOS>;
978 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
979 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", [], IIC_STOS>;
981 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", [], IIC_SCAS>;
982 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", [], IIC_SCAS>, OpSize;
983 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", [], IIC_SCAS>;
984 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", [], IIC_SCAS>;
986 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", [], IIC_CMPS>;
987 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", [], IIC_CMPS>, OpSize;
988 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", [], IIC_CMPS>;
989 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", [], IIC_CMPS>;
992 //===----------------------------------------------------------------------===//
993 // Move Instructions.
995 let SchedRW = [WriteMove] in {
996 let neverHasSideEffects = 1 in {
997 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
998 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
999 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1000 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
1001 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1002 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1003 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1004 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1007 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1008 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1009 "mov{b}\t{$src, $dst|$dst, $src}",
1010 [(set GR8:$dst, imm:$src)], IIC_MOV>;
1011 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1012 "mov{w}\t{$src, $dst|$dst, $src}",
1013 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize;
1014 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1015 "mov{l}\t{$src, $dst|$dst, $src}",
1016 [(set GR32:$dst, imm:$src)], IIC_MOV>;
1017 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
1018 "movabs{q}\t{$src, $dst|$dst, $src}",
1019 [(set GR64:$dst, imm:$src)], IIC_MOV>;
1020 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1021 "mov{q}\t{$src, $dst|$dst, $src}",
1022 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
1026 let SchedRW = [WriteStore] in {
1027 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1028 "mov{b}\t{$src, $dst|$dst, $src}",
1029 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
1030 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1031 "mov{w}\t{$src, $dst|$dst, $src}",
1032 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize;
1033 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1034 "mov{l}\t{$src, $dst|$dst, $src}",
1035 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>;
1036 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1037 "mov{q}\t{$src, $dst|$dst, $src}",
1038 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
1041 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
1042 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
1043 let SchedRW = [WriteALU] in {
1044 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
1045 "mov{b}\t{$src, %al|AL, $src}", [], IIC_MOV_MEM>,
1046 Requires<[In32BitMode]>;
1047 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
1048 "mov{w}\t{$src, %ax|AL, $src}", [], IIC_MOV_MEM>, OpSize,
1049 Requires<[In32BitMode]>;
1050 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1051 "mov{l}\t{$src, %eax|EAX, $src}", [], IIC_MOV_MEM>,
1052 Requires<[In32BitMode]>;
1053 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1054 "mov{b}\t{%al, $dst|$dst, AL}", [], IIC_MOV_MEM>,
1055 Requires<[In32BitMode]>;
1056 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1057 "mov{w}\t{%ax, $dst|$dst, AL}", [], IIC_MOV_MEM>, OpSize,
1058 Requires<[In32BitMode]>;
1059 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1060 "mov{l}\t{%eax, $dst|$dst, EAX}", [], IIC_MOV_MEM>,
1061 Requires<[In32BitMode]>;
1064 // FIXME: These definitions are utterly broken
1065 // Just leave them commented out for now because they're useless outside
1066 // of the large code model, and most compilers won't generate the instructions
1069 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
1070 "mov{q}\t{$src, %rax|RAX, $src}", []>;
1071 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
1072 "mov{q}\t{$src, %rax|RAX, $src}", []>;
1073 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
1074 "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
1075 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
1076 "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
1080 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
1081 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1082 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1083 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1084 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
1085 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1086 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1087 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1088 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1091 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1092 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1093 "mov{b}\t{$src, $dst|$dst, $src}",
1094 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1095 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1096 "mov{w}\t{$src, $dst|$dst, $src}",
1097 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize;
1098 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1099 "mov{l}\t{$src, $dst|$dst, $src}",
1100 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>;
1101 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1102 "mov{q}\t{$src, $dst|$dst, $src}",
1103 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1106 let SchedRW = [WriteStore] in {
1107 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1108 "mov{b}\t{$src, $dst|$dst, $src}",
1109 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1110 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1111 "mov{w}\t{$src, $dst|$dst, $src}",
1112 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize;
1113 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1114 "mov{l}\t{$src, $dst|$dst, $src}",
1115 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>;
1116 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1117 "mov{q}\t{$src, $dst|$dst, $src}",
1118 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1121 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1122 // that they can be used for copying and storing h registers, which can't be
1123 // encoded when a REX prefix is present.
1124 let isCodeGenOnly = 1 in {
1125 let neverHasSideEffects = 1 in
1126 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1127 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1128 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
1131 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1132 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1133 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1134 IIC_MOV_MEM>, Sched<[WriteStore]>;
1135 let mayLoad = 1, neverHasSideEffects = 1,
1136 canFoldAsLoad = 1, isReMaterializable = 1 in
1137 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1138 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1139 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1140 IIC_MOV_MEM>, Sched<[WriteLoad]>;
1144 // Condition code ops, incl. set if equal/not equal/...
1145 let SchedRW = [WriteALU] in {
1146 let Defs = [EFLAGS], Uses = [AH] in
1147 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1148 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
1149 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
1150 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1151 IIC_AHF>; // AH = flags
1154 //===----------------------------------------------------------------------===//
1155 // Bit tests instructions: BT, BTS, BTR, BTC.
1157 let Defs = [EFLAGS] in {
1158 let SchedRW = [WriteALU] in {
1159 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1160 "bt{w}\t{$src2, $src1|$src1, $src2}",
1161 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1163 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1164 "bt{l}\t{$src2, $src1|$src1, $src2}",
1165 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>, TB;
1166 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1167 "bt{q}\t{$src2, $src1|$src1, $src2}",
1168 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1171 // Unlike with the register+register form, the memory+register form of the
1172 // bt instruction does not ignore the high bits of the index. From ISel's
1173 // perspective, this is pretty bizarre. Make these instructions disassembly
1176 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
1177 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1178 "bt{w}\t{$src2, $src1|$src1, $src2}",
1179 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1180 // (implicit EFLAGS)]
1182 >, OpSize, TB, Requires<[FastBTMem]>;
1183 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1184 "bt{l}\t{$src2, $src1|$src1, $src2}",
1185 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1186 // (implicit EFLAGS)]
1188 >, TB, Requires<[FastBTMem]>;
1189 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1190 "bt{q}\t{$src2, $src1|$src1, $src2}",
1191 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1192 // (implicit EFLAGS)]
1197 let SchedRW = [WriteALU] in {
1198 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1199 "bt{w}\t{$src2, $src1|$src1, $src2}",
1200 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1201 IIC_BT_RI>, OpSize, TB;
1202 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1203 "bt{l}\t{$src2, $src1|$src1, $src2}",
1204 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1206 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1207 "bt{q}\t{$src2, $src1|$src1, $src2}",
1208 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1212 // Note that these instructions don't need FastBTMem because that
1213 // only applies when the other operand is in a register. When it's
1214 // an immediate, bt is still fast.
1215 let SchedRW = [WriteALU] in {
1216 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1217 "bt{w}\t{$src2, $src1|$src1, $src2}",
1218 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1219 ], IIC_BT_MI>, OpSize, TB;
1220 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1221 "bt{l}\t{$src2, $src1|$src1, $src2}",
1222 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1224 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1225 "bt{q}\t{$src2, $src1|$src1, $src2}",
1226 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1227 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1230 let hasSideEffects = 0 in {
1231 let SchedRW = [WriteALU] in {
1232 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1233 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1235 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1236 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1237 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1238 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1241 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1242 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1243 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1245 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1246 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1247 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1248 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1251 let SchedRW = [WriteALU] in {
1252 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1253 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1255 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1256 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1257 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1258 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1261 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1262 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1263 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1265 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1266 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1267 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1268 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1271 let SchedRW = [WriteALU] in {
1272 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1273 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1275 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1276 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1277 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1278 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1281 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1282 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1283 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1285 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1286 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1287 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1288 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1291 let SchedRW = [WriteALU] in {
1292 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1293 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1295 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1296 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1297 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1298 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1301 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1302 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1303 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1305 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1306 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1307 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1308 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1311 let SchedRW = [WriteALU] in {
1312 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1313 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1315 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1316 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1317 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1318 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1321 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1322 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1323 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1325 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1326 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1327 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1328 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1331 let SchedRW = [WriteALU] in {
1332 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1333 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1335 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1336 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1337 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1338 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1341 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1342 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1343 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1345 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1346 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1347 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1348 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1350 } // hasSideEffects = 0
1351 } // Defs = [EFLAGS]
1354 //===----------------------------------------------------------------------===//
1358 // Atomic swap. These are just normal xchg instructions. But since a memory
1359 // operand is referenced, the atomicity is ensured.
1360 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
1361 InstrItinClass itin> {
1362 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
1363 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
1364 (ins GR8:$val, i8mem:$ptr),
1365 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
1368 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
1370 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
1371 (ins GR16:$val, i16mem:$ptr),
1372 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
1375 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
1377 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
1378 (ins GR32:$val, i32mem:$ptr),
1379 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
1382 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
1384 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
1385 (ins GR64:$val, i64mem:$ptr),
1386 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
1389 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
1394 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
1396 // Swap between registers.
1397 let SchedRW = [WriteALU] in {
1398 let Constraints = "$val = $dst" in {
1399 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1400 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1401 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1402 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, OpSize;
1403 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1404 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1405 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1406 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1409 // Swap between EAX and other registers.
1410 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1411 "xchg{w}\t{$src, %ax|AX, $src}", [], IIC_XCHG_REG>, OpSize;
1412 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1413 "xchg{l}\t{$src, %eax|EAX, $src}", [], IIC_XCHG_REG>,
1414 Requires<[In32BitMode]>;
1415 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1416 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1417 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1418 "xchg{l}\t{$src, %eax|EAX, $src}", [], IIC_XCHG_REG>,
1419 Requires<[In64BitMode]>;
1420 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1421 "xchg{q}\t{$src, %rax|RAX, $src}", [], IIC_XCHG_REG>;
1424 let SchedRW = [WriteALU] in {
1425 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1426 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1427 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1428 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1430 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1431 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1432 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1433 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1436 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1437 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1438 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1439 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1440 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1442 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1443 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1444 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1445 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1449 let SchedRW = [WriteALU] in {
1450 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1451 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1452 IIC_CMPXCHG_REG8>, TB;
1453 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1454 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1455 IIC_CMPXCHG_REG>, TB, OpSize;
1456 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1457 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1458 IIC_CMPXCHG_REG>, TB;
1459 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1460 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1461 IIC_CMPXCHG_REG>, TB;
1464 let SchedRW = [WriteALULd, WriteRMW] in {
1465 let mayLoad = 1, mayStore = 1 in {
1466 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1467 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1468 IIC_CMPXCHG_MEM8>, TB;
1469 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1470 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1471 IIC_CMPXCHG_MEM>, TB, OpSize;
1472 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1473 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1474 IIC_CMPXCHG_MEM>, TB;
1475 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1476 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1477 IIC_CMPXCHG_MEM>, TB;
1480 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1481 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1482 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1484 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1485 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1486 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1487 TB, Requires<[HasCmpxchg16b]>;
1491 // Lock instruction prefix
1492 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1494 // Rex64 instruction prefix
1495 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>;
1497 // Data16 instruction prefix
1498 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1500 // Repeat string operation instruction prefixes
1501 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1502 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1503 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1504 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1505 // Repeat while not equal (used with CMPS and SCAS)
1506 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1510 // String manipulation instructions
1511 let SchedRW = [WriteMicrocoded] in {
1512 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", [], IIC_LODS>;
1513 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", [], IIC_LODS>, OpSize;
1514 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", [], IIC_LODS>;
1515 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", [], IIC_LODS>;
1518 let SchedRW = [WriteSystem] in {
1519 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", [], IIC_OUTS>;
1520 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", [], IIC_OUTS>, OpSize;
1521 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", [], IIC_OUTS>;
1524 // Flag instructions
1525 let SchedRW = [WriteALU] in {
1526 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1527 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1528 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1529 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1530 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1531 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1532 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1534 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1537 // Table lookup instructions
1538 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,
1541 let SchedRW = [WriteMicrocoded] in {
1542 // ASCII Adjust After Addition
1543 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1544 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1545 Requires<[In32BitMode]>;
1547 // ASCII Adjust AX Before Division
1548 // sets AL, AH and EFLAGS and uses AL and AH
1549 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1550 "aad\t$src", [], IIC_AAD>, Requires<[In32BitMode]>;
1552 // ASCII Adjust AX After Multiply
1553 // sets AL, AH and EFLAGS and uses AL
1554 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1555 "aam\t$src", [], IIC_AAM>, Requires<[In32BitMode]>;
1557 // ASCII Adjust AL After Subtraction - sets
1558 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1559 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1560 Requires<[In32BitMode]>;
1562 // Decimal Adjust AL after Addition
1563 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1564 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1565 Requires<[In32BitMode]>;
1567 // Decimal Adjust AL after Subtraction
1568 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1569 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1570 Requires<[In32BitMode]>;
1573 let SchedRW = [WriteSystem] in {
1574 // Check Array Index Against Bounds
1575 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1576 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize,
1577 Requires<[In32BitMode]>;
1578 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1579 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>,
1580 Requires<[In32BitMode]>;
1582 // Adjust RPL Field of Segment Selector
1583 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1584 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1585 Requires<[In32BitMode]>;
1586 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1587 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1588 Requires<[In32BitMode]>;
1591 //===----------------------------------------------------------------------===//
1592 // MOVBE Instructions
1594 let Predicates = [HasMOVBE] in {
1595 let SchedRW = [WriteALULd] in {
1596 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1597 "movbe{w}\t{$src, $dst|$dst, $src}",
1598 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1600 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1601 "movbe{l}\t{$src, $dst|$dst, $src}",
1602 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1604 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1605 "movbe{q}\t{$src, $dst|$dst, $src}",
1606 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
1609 let SchedRW = [WriteStore] in {
1610 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1611 "movbe{w}\t{$src, $dst|$dst, $src}",
1612 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1614 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1615 "movbe{l}\t{$src, $dst|$dst, $src}",
1616 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1618 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1619 "movbe{q}\t{$src, $dst|$dst, $src}",
1620 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
1625 //===----------------------------------------------------------------------===//
1626 // RDRAND Instruction
1628 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1629 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1631 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize, TB;
1632 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1634 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, TB;
1635 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1637 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
1640 //===----------------------------------------------------------------------===//
1641 // RDSEED Instruction
1643 let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
1644 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
1646 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize, TB;
1647 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
1649 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, TB;
1650 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
1652 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
1655 //===----------------------------------------------------------------------===//
1656 // LZCNT Instruction
1658 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
1659 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1660 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1661 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
1663 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1664 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1665 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
1666 (implicit EFLAGS)]>, XS, OpSize;
1668 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1669 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1670 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS;
1671 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1672 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1673 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
1674 (implicit EFLAGS)]>, XS;
1676 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1677 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1678 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
1680 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1681 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1682 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
1683 (implicit EFLAGS)]>, XS;
1686 //===----------------------------------------------------------------------===//
1689 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1690 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1691 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1692 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
1694 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1695 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1696 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
1697 (implicit EFLAGS)]>, XS, OpSize;
1699 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1700 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1701 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS;
1702 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1703 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1704 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
1705 (implicit EFLAGS)]>, XS;
1707 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1708 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1709 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
1711 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1712 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1713 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
1714 (implicit EFLAGS)]>, XS;
1717 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
1718 RegisterClass RC, X86MemOperand x86memop, SDNode OpNode,
1720 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
1721 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1722 [(set RC:$dst, (OpNode RC:$src)), (implicit EFLAGS)]>, T8, VEX_4V;
1723 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
1724 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1725 [(set RC:$dst, (OpNode (ld_frag addr:$src))), (implicit EFLAGS)]>,
1729 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1730 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem,
1732 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem,
1733 X86blsr, loadi64>, VEX_W;
1734 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem,
1735 X86blsmsk, loadi32>;
1736 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem,
1737 X86blsmsk, loadi64>, VEX_W;
1738 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem,
1740 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem,
1741 X86blsi, loadi64>, VEX_W;
1744 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
1745 X86MemOperand x86memop, Intrinsic Int,
1747 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1748 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1749 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
1751 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
1752 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1753 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
1754 (implicit EFLAGS)]>, T8, VEX_4VOp3;
1757 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1758 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
1759 int_x86_bmi_bextr_32, loadi32>;
1760 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
1761 int_x86_bmi_bextr_64, loadi64>, VEX_W;
1764 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
1765 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
1766 int_x86_bmi_bzhi_32, loadi32>;
1767 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
1768 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
1771 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
1772 X86MemOperand x86memop, Intrinsic Int,
1774 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1775 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1776 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
1778 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1779 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1780 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
1783 let Predicates = [HasBMI2] in {
1784 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
1785 int_x86_bmi_pdep_32, loadi32>, T8XD;
1786 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
1787 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
1788 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
1789 int_x86_bmi_pext_32, loadi32>, T8XS;
1790 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
1791 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
1794 //===----------------------------------------------------------------------===//
1796 //===----------------------------------------------------------------------===//
1798 include "X86InstrArithmetic.td"
1799 include "X86InstrCMovSetCC.td"
1800 include "X86InstrExtension.td"
1801 include "X86InstrControl.td"
1802 include "X86InstrShiftRotate.td"
1804 // X87 Floating Point Stack.
1805 include "X86InstrFPStack.td"
1807 // SIMD support (SSE, MMX and AVX)
1808 include "X86InstrFragmentsSIMD.td"
1810 // FMA - Fused Multiply-Add support (requires FMA)
1811 include "X86InstrFMA.td"
1814 include "X86InstrXOP.td"
1816 // SSE, MMX and 3DNow! vector support.
1817 include "X86InstrSSE.td"
1818 include "X86InstrMMX.td"
1819 include "X86Instr3DNow.td"
1821 include "X86InstrVMX.td"
1822 include "X86InstrSVM.td"
1824 include "X86InstrTSX.td"
1826 // System instructions.
1827 include "X86InstrSystem.td"
1829 // Compiler Pseudo Instructions and Pat Patterns
1830 include "X86InstrCompiler.td"
1832 //===----------------------------------------------------------------------===//
1833 // Assembler Mnemonic Aliases
1834 //===----------------------------------------------------------------------===//
1836 def : MnemonicAlias<"call", "calll">, Requires<[In32BitMode]>;
1837 def : MnemonicAlias<"call", "callq">, Requires<[In64BitMode]>;
1839 def : MnemonicAlias<"cbw", "cbtw">;
1840 def : MnemonicAlias<"cwde", "cwtl">;
1841 def : MnemonicAlias<"cwd", "cwtd">;
1842 def : MnemonicAlias<"cdq", "cltd">;
1843 def : MnemonicAlias<"cdqe", "cltq">;
1844 def : MnemonicAlias<"cqo", "cqto">;
1846 // lret maps to lretl, it is not ambiguous with lretq.
1847 def : MnemonicAlias<"lret", "lretl">;
1849 def : MnemonicAlias<"leavel", "leave">, Requires<[In32BitMode]>;
1850 def : MnemonicAlias<"leaveq", "leave">, Requires<[In64BitMode]>;
1852 def : MnemonicAlias<"loopz", "loope">;
1853 def : MnemonicAlias<"loopnz", "loopne">;
1855 def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
1856 def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
1857 def : MnemonicAlias<"popf", "popfl">, Requires<[In32BitMode]>;
1858 def : MnemonicAlias<"popf", "popfq">, Requires<[In64BitMode]>;
1859 def : MnemonicAlias<"popfd", "popfl">;
1861 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
1862 // all modes. However: "push (addr)" and "push $42" should default to
1863 // pushl/pushq depending on the current mode. Similar for "pop %bx"
1864 def : MnemonicAlias<"push", "pushl">, Requires<[In32BitMode]>;
1865 def : MnemonicAlias<"push", "pushq">, Requires<[In64BitMode]>;
1866 def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
1867 def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1868 def : MnemonicAlias<"pushfd", "pushfl">;
1870 def : MnemonicAlias<"repe", "rep">;
1871 def : MnemonicAlias<"repz", "rep">;
1872 def : MnemonicAlias<"repnz", "repne">;
1874 def : MnemonicAlias<"retl", "ret">, Requires<[In32BitMode]>;
1875 def : MnemonicAlias<"retq", "ret">, Requires<[In64BitMode]>;
1877 def : MnemonicAlias<"salb", "shlb">;
1878 def : MnemonicAlias<"salw", "shlw">;
1879 def : MnemonicAlias<"sall", "shll">;
1880 def : MnemonicAlias<"salq", "shlq">;
1882 def : MnemonicAlias<"smovb", "movsb">;
1883 def : MnemonicAlias<"smovw", "movsw">;
1884 def : MnemonicAlias<"smovl", "movsl">;
1885 def : MnemonicAlias<"smovq", "movsq">;
1887 def : MnemonicAlias<"ud2a", "ud2">;
1888 def : MnemonicAlias<"verrw", "verr">;
1890 // System instruction aliases.
1891 def : MnemonicAlias<"iret", "iretl">;
1892 def : MnemonicAlias<"sysret", "sysretl">;
1893 def : MnemonicAlias<"sysexit", "sysexitl">;
1895 def : MnemonicAlias<"lgdtl", "lgdt">, Requires<[In32BitMode]>;
1896 def : MnemonicAlias<"lgdtq", "lgdt">, Requires<[In64BitMode]>;
1897 def : MnemonicAlias<"lidtl", "lidt">, Requires<[In32BitMode]>;
1898 def : MnemonicAlias<"lidtq", "lidt">, Requires<[In64BitMode]>;
1899 def : MnemonicAlias<"sgdtl", "sgdt">, Requires<[In32BitMode]>;
1900 def : MnemonicAlias<"sgdtq", "sgdt">, Requires<[In64BitMode]>;
1901 def : MnemonicAlias<"sidtl", "sidt">, Requires<[In32BitMode]>;
1902 def : MnemonicAlias<"sidtq", "sidt">, Requires<[In64BitMode]>;
1905 // Floating point stack aliases.
1906 def : MnemonicAlias<"fcmovz", "fcmove">;
1907 def : MnemonicAlias<"fcmova", "fcmovnbe">;
1908 def : MnemonicAlias<"fcmovnae", "fcmovb">;
1909 def : MnemonicAlias<"fcmovna", "fcmovbe">;
1910 def : MnemonicAlias<"fcmovae", "fcmovnb">;
1911 def : MnemonicAlias<"fcomip", "fcompi">;
1912 def : MnemonicAlias<"fildq", "fildll">;
1913 def : MnemonicAlias<"fistpq", "fistpll">;
1914 def : MnemonicAlias<"fisttpq", "fisttpll">;
1915 def : MnemonicAlias<"fldcww", "fldcw">;
1916 def : MnemonicAlias<"fnstcww", "fnstcw">;
1917 def : MnemonicAlias<"fnstsww", "fnstsw">;
1918 def : MnemonicAlias<"fucomip", "fucompi">;
1919 def : MnemonicAlias<"fwait", "wait">;
1922 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond>
1923 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
1924 !strconcat(Prefix, NewCond, Suffix)>;
1926 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
1927 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
1928 /// example "setz" -> "sete".
1929 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix> {
1930 def C : CondCodeAlias<Prefix, Suffix, "c", "b">; // setc -> setb
1931 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e">; // setz -> sete
1932 def NA : CondCodeAlias<Prefix, Suffix, "na", "be">; // setna -> setbe
1933 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae">; // setnb -> setae
1934 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae">; // setnc -> setae
1935 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le">; // setng -> setle
1936 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge">; // setnl -> setge
1937 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne">; // setnz -> setne
1938 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p">; // setpe -> setp
1939 def PO : CondCodeAlias<Prefix, Suffix, "po", "np">; // setpo -> setnp
1941 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b">; // setnae -> setb
1942 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a">; // setnbe -> seta
1943 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l">; // setnge -> setl
1944 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g">; // setnle -> setg
1947 // Aliases for set<CC>
1948 defm : IntegerCondCodeMnemonicAlias<"set", "">;
1949 // Aliases for j<CC>
1950 defm : IntegerCondCodeMnemonicAlias<"j", "">;
1951 // Aliases for cmov<CC>{w,l,q}
1952 defm : IntegerCondCodeMnemonicAlias<"cmov", "w">;
1953 defm : IntegerCondCodeMnemonicAlias<"cmov", "l">;
1954 defm : IntegerCondCodeMnemonicAlias<"cmov", "q">;
1957 //===----------------------------------------------------------------------===//
1958 // Assembler Instruction Aliases
1959 //===----------------------------------------------------------------------===//
1961 // aad/aam default to base 10 if no operand is specified.
1962 def : InstAlias<"aad", (AAD8i8 10)>;
1963 def : InstAlias<"aam", (AAM8i8 10)>;
1965 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
1966 def : InstAlias<"bt $imm, $mem", (BT32mi8 i32mem:$mem, i32i8imm:$imm)>;
1969 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>;
1970 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>;
1971 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
1972 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
1974 // div and idiv aliases for explicit A register.
1975 def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>;
1976 def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>;
1977 def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>;
1978 def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>;
1979 def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>;
1980 def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>;
1981 def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>;
1982 def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>;
1983 def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>;
1984 def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>;
1985 def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>;
1986 def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>;
1987 def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>;
1988 def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>;
1989 def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>;
1990 def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>;
1994 // Various unary fpstack operations default to operating on on ST1.
1995 // For example, "fxch" -> "fxch %st(1)"
1996 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
1997 def : InstAlias<"fsubp", (SUBR_FPrST0 ST1)>;
1998 def : InstAlias<"fsubrp", (SUB_FPrST0 ST1)>;
1999 def : InstAlias<"fmulp", (MUL_FPrST0 ST1)>;
2000 def : InstAlias<"fdivp", (DIVR_FPrST0 ST1)>;
2001 def : InstAlias<"fdivrp", (DIV_FPrST0 ST1)>;
2002 def : InstAlias<"fxch", (XCH_F ST1)>;
2003 def : InstAlias<"fcom", (COM_FST0r ST1)>;
2004 def : InstAlias<"fcomp", (COMP_FST0r ST1)>;
2005 def : InstAlias<"fcomi", (COM_FIr ST1)>;
2006 def : InstAlias<"fcompi", (COM_FIPr ST1)>;
2007 def : InstAlias<"fucom", (UCOM_Fr ST1)>;
2008 def : InstAlias<"fucomp", (UCOM_FPr ST1)>;
2009 def : InstAlias<"fucomi", (UCOM_FIr ST1)>;
2010 def : InstAlias<"fucompi", (UCOM_FIPr ST1)>;
2012 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
2013 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
2014 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
2016 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
2017 def : InstAlias<!strconcat(Mnemonic, " $op, %st(0)"),
2018 (Inst RST:$op), EmitAlias>;
2019 def : InstAlias<!strconcat(Mnemonic, " %st(0), %st(0)"),
2020 (Inst ST0), EmitAlias>;
2023 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
2024 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
2025 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
2026 defm : FpUnaryAlias<"fsubp", SUBR_FPrST0>;
2027 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
2028 defm : FpUnaryAlias<"fsubrp", SUB_FPrST0>;
2029 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
2030 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
2031 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
2032 defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>;
2033 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
2034 defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>;
2035 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
2036 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
2037 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
2038 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
2041 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
2042 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
2043 // solely because gas supports it.
2044 def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op), 0>;
2045 def : InstAlias<"fmulp %st(0), $op", (MUL_FPrST0 RST:$op)>;
2046 def : InstAlias<"fsubp %st(0), $op", (SUBR_FPrST0 RST:$op)>;
2047 def : InstAlias<"fsubrp %st(0), $op", (SUB_FPrST0 RST:$op)>;
2048 def : InstAlias<"fdivp %st(0), $op", (DIVR_FPrST0 RST:$op)>;
2049 def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>;
2051 // We accept "fnstsw %eax" even though it only writes %ax.
2052 def : InstAlias<"fnstsw %eax", (FNSTSW16r)>;
2053 def : InstAlias<"fnstsw %al" , (FNSTSW16r)>;
2054 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
2056 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
2057 // this is compatible with what GAS does.
2058 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2059 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2060 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>;
2061 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>;
2063 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
2064 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
2065 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
2066 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
2067 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
2068 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
2069 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
2071 // inb %dx -> inb %al, %dx
2072 def : InstAlias<"inb %dx", (IN8rr)>;
2073 def : InstAlias<"inw %dx", (IN16rr)>;
2074 def : InstAlias<"inl %dx", (IN32rr)>;
2075 def : InstAlias<"inb $port", (IN8ri i8imm:$port)>;
2076 def : InstAlias<"inw $port", (IN16ri i8imm:$port)>;
2077 def : InstAlias<"inl $port", (IN32ri i8imm:$port)>;
2080 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
2081 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2082 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2083 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
2084 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
2085 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2086 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2088 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
2089 // the move. All segment/mem forms are equivalent, this has the shortest
2091 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
2092 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
2094 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
2095 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
2097 // Match 'movq GR64, MMX' as an alias for movd.
2098 def : InstAlias<"movq $src, $dst",
2099 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
2100 def : InstAlias<"movq $src, $dst",
2101 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
2103 // movsd with no operands (as opposed to the SSE scalar move of a double) is an
2104 // alias for movsl. (as in rep; movsd)
2105 def : InstAlias<"movsd", (MOVSD)>;
2108 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
2109 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
2110 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
2111 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
2112 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
2113 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
2114 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
2117 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
2118 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
2119 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
2120 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
2121 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
2122 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
2123 // Note: No GR32->GR64 movzx form.
2125 // outb %dx -> outb %al, %dx
2126 def : InstAlias<"outb %dx", (OUT8rr)>;
2127 def : InstAlias<"outw %dx", (OUT16rr)>;
2128 def : InstAlias<"outl %dx", (OUT32rr)>;
2129 def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>;
2130 def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>;
2131 def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>;
2133 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
2134 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
2135 // errors, since its encoding is the most compact.
2136 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
2138 // shld/shrd op,op -> shld op, op, CL
2139 def : InstAlias<"shldw $r2, $r1", (SHLD16rrCL GR16:$r1, GR16:$r2)>;
2140 def : InstAlias<"shldl $r2, $r1", (SHLD32rrCL GR32:$r1, GR32:$r2)>;
2141 def : InstAlias<"shldq $r2, $r1", (SHLD64rrCL GR64:$r1, GR64:$r2)>;
2142 def : InstAlias<"shrdw $r2, $r1", (SHRD16rrCL GR16:$r1, GR16:$r2)>;
2143 def : InstAlias<"shrdl $r2, $r1", (SHRD32rrCL GR32:$r1, GR32:$r2)>;
2144 def : InstAlias<"shrdq $r2, $r1", (SHRD64rrCL GR64:$r1, GR64:$r2)>;
2146 def : InstAlias<"shldw $reg, $mem", (SHLD16mrCL i16mem:$mem, GR16:$reg)>;
2147 def : InstAlias<"shldl $reg, $mem", (SHLD32mrCL i32mem:$mem, GR32:$reg)>;
2148 def : InstAlias<"shldq $reg, $mem", (SHLD64mrCL i64mem:$mem, GR64:$reg)>;
2149 def : InstAlias<"shrdw $reg, $mem", (SHRD16mrCL i16mem:$mem, GR16:$reg)>;
2150 def : InstAlias<"shrdl $reg, $mem", (SHRD32mrCL i32mem:$mem, GR32:$reg)>;
2151 def : InstAlias<"shrdq $reg, $mem", (SHRD64mrCL i64mem:$mem, GR64:$reg)>;
2153 /* FIXME: This is disabled because the asm matcher is currently incapable of
2154 * matching a fixed immediate like $1.
2155 // "shl X, $1" is an alias for "shl X".
2156 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
2157 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2158 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
2159 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2160 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
2161 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2162 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
2163 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2164 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
2165 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2166 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
2167 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2168 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
2169 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2170 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
2171 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2172 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2175 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2176 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
2177 defm : ShiftRotateByOneAlias<"rol", "ROL">;
2178 defm : ShiftRotateByOneAlias<"ror", "ROR">;
2181 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
2182 def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>;
2183 def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>;
2184 def : InstAlias<"testl $val, $mem", (TEST32rm GR32:$val, i32mem:$mem)>;
2185 def : InstAlias<"testq $val, $mem", (TEST64rm GR64:$val, i64mem:$mem)>;
2187 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
2188 def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>;
2189 def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>;
2190 def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>;
2191 def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>;
2193 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
2194 def : InstAlias<"xchgw %ax, $src", (XCHG16ar GR16:$src)>;
2195 def : InstAlias<"xchgl %eax, $src", (XCHG32ar GR32:$src)>, Requires<[In32BitMode]>;
2196 def : InstAlias<"xchgl %eax, $src", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
2197 def : InstAlias<"xchgq %rax, $src", (XCHG64ar GR64:$src)>;