1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
35 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
49 // RES1, RES2, FLAGS = op LHS, RHS
50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
54 SDTCisInt<0>, SDTCisVT<1, i32>]>;
55 def SDTX86BrCond : SDTypeProfile<0, 3,
56 [SDTCisVT<0, OtherVT>,
57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 def SDTX86SetCC : SDTypeProfile<1, 2,
61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
62 def SDTX86SetCC_C : SDTypeProfile<1, 2,
64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
66 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
68 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
70 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
72 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
74 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
75 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
76 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
78 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
79 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
82 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
84 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
88 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
94 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
96 def SDTX86Void : SDTypeProfile<0, 0, []>;
98 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
100 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
102 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
104 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
106 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
108 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
110 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
112 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
114 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
116 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
117 [SDNPHasChain,SDNPSideEffect]>;
118 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
120 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
122 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
126 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
127 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
128 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
129 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
131 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
132 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
134 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
135 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
137 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
138 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
140 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
142 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
143 [SDNPHasChain, SDNPSideEffect]>;
145 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
146 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
147 SDNPMayLoad, SDNPMemOperand]>;
148 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
149 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
150 SDNPMayLoad, SDNPMemOperand]>;
151 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
152 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
153 SDNPMayLoad, SDNPMemOperand]>;
155 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
156 [SDNPHasChain, SDNPMayStore,
157 SDNPMayLoad, SDNPMemOperand]>;
158 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
159 [SDNPHasChain, SDNPMayStore,
160 SDNPMayLoad, SDNPMemOperand]>;
161 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
162 [SDNPHasChain, SDNPMayStore,
163 SDNPMayLoad, SDNPMemOperand]>;
164 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
165 [SDNPHasChain, SDNPMayStore,
166 SDNPMayLoad, SDNPMemOperand]>;
167 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
168 [SDNPHasChain, SDNPMayStore,
169 SDNPMayLoad, SDNPMemOperand]>;
170 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
171 [SDNPHasChain, SDNPMayStore,
172 SDNPMayLoad, SDNPMemOperand]>;
173 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
174 [SDNPHasChain, SDNPMayStore,
175 SDNPMayLoad, SDNPMemOperand]>;
176 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
177 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
179 def X86vastart_save_xmm_regs :
180 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
181 SDT_X86VASTART_SAVE_XMM_REGS,
182 [SDNPHasChain, SDNPVariadic]>;
184 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
185 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
187 def X86callseq_start :
188 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
189 [SDNPHasChain, SDNPOutGlue]>;
191 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
192 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
194 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
195 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
198 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
199 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
200 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
201 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
204 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
205 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
207 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
208 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
210 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
211 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
213 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
214 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
216 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
219 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
220 SDTypeProfile<1, 1, [SDTCisInt<0>,
222 [SDNPHasChain, SDNPSideEffect]>;
223 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
224 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
225 [SDNPHasChain, SDNPSideEffect]>;
227 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
228 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
230 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
232 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
233 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
235 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
237 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
238 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
240 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
241 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
242 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
244 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
246 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
248 def X86andn_flag : SDNode<"X86ISD::ANDN", SDTBinaryArithWithFlags>;
250 def X86blsi : SDNode<"X86ISD::BLSI", SDTIntUnaryOp>;
251 def X86blsmsk : SDNode<"X86ISD::BLSMSK", SDTIntUnaryOp>;
252 def X86blsr : SDNode<"X86ISD::BLSR", SDTIntUnaryOp>;
254 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
256 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
257 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
259 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
262 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
263 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
265 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL,
266 [SDNPHasChain, SDNPOutGlue]>;
268 //===----------------------------------------------------------------------===//
269 // X86 Operand Definitions.
272 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
273 // the index operand of an address, to conform to x86 encoding restrictions.
274 def ptr_rc_nosp : PointerLikeRegClass<1>;
276 // *mem - Operand definitions for the funky X86 addressing mode operands.
278 def X86MemAsmOperand : AsmOperandClass {
279 let Name = "Mem"; let PredicateMethod = "isMem";
281 def X86Mem8AsmOperand : AsmOperandClass {
282 let Name = "Mem8"; let PredicateMethod = "isMem8";
284 def X86Mem16AsmOperand : AsmOperandClass {
285 let Name = "Mem16"; let PredicateMethod = "isMem16";
287 def X86Mem32AsmOperand : AsmOperandClass {
288 let Name = "Mem32"; let PredicateMethod = "isMem32";
290 def X86Mem64AsmOperand : AsmOperandClass {
291 let Name = "Mem64"; let PredicateMethod = "isMem64";
293 def X86Mem80AsmOperand : AsmOperandClass {
294 let Name = "Mem80"; let PredicateMethod = "isMem80";
296 def X86Mem128AsmOperand : AsmOperandClass {
297 let Name = "Mem128"; let PredicateMethod = "isMem128";
299 def X86Mem256AsmOperand : AsmOperandClass {
300 let Name = "Mem256"; let PredicateMethod = "isMem256";
303 // Gather mem operands
304 def X86MemVX32Operand : AsmOperandClass {
305 let Name = "MemVX32"; let PredicateMethod = "isMemVX32";
307 def X86MemVY32Operand : AsmOperandClass {
308 let Name = "MemVY32"; let PredicateMethod = "isMemVY32";
310 def X86MemVX64Operand : AsmOperandClass {
311 let Name = "MemVX64"; let PredicateMethod = "isMemVX64";
313 def X86MemVY64Operand : AsmOperandClass {
314 let Name = "MemVY64"; let PredicateMethod = "isMemVY64";
317 def X86AbsMemAsmOperand : AsmOperandClass {
319 let SuperClasses = [X86MemAsmOperand];
321 class X86MemOperand<string printMethod> : Operand<iPTR> {
322 let PrintMethod = printMethod;
323 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
324 let ParserMatchClass = X86MemAsmOperand;
327 let OperandType = "OPERAND_MEMORY" in {
328 def opaque32mem : X86MemOperand<"printopaquemem">;
329 def opaque48mem : X86MemOperand<"printopaquemem">;
330 def opaque80mem : X86MemOperand<"printopaquemem">;
331 def opaque512mem : X86MemOperand<"printopaquemem">;
333 def i8mem : X86MemOperand<"printi8mem"> {
334 let ParserMatchClass = X86Mem8AsmOperand; }
335 def i16mem : X86MemOperand<"printi16mem"> {
336 let ParserMatchClass = X86Mem16AsmOperand; }
337 def i32mem : X86MemOperand<"printi32mem"> {
338 let ParserMatchClass = X86Mem32AsmOperand; }
339 def i64mem : X86MemOperand<"printi64mem"> {
340 let ParserMatchClass = X86Mem64AsmOperand; }
341 def i128mem : X86MemOperand<"printi128mem"> {
342 let ParserMatchClass = X86Mem128AsmOperand; }
343 def i256mem : X86MemOperand<"printi256mem"> {
344 let ParserMatchClass = X86Mem256AsmOperand; }
345 def f32mem : X86MemOperand<"printf32mem"> {
346 let ParserMatchClass = X86Mem32AsmOperand; }
347 def f64mem : X86MemOperand<"printf64mem"> {
348 let ParserMatchClass = X86Mem64AsmOperand; }
349 def f80mem : X86MemOperand<"printf80mem"> {
350 let ParserMatchClass = X86Mem80AsmOperand; }
351 def f128mem : X86MemOperand<"printf128mem"> {
352 let ParserMatchClass = X86Mem128AsmOperand; }
353 def f256mem : X86MemOperand<"printf256mem">{
354 let ParserMatchClass = X86Mem256AsmOperand; }
356 // Gather mem operands
357 def vx32mem : X86MemOperand<"printi32mem">{
358 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
359 let ParserMatchClass = X86MemVX32Operand; }
360 def vy32mem : X86MemOperand<"printi32mem">{
361 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
362 let ParserMatchClass = X86MemVY32Operand; }
363 def vx64mem : X86MemOperand<"printi64mem">{
364 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
365 let ParserMatchClass = X86MemVX64Operand; }
366 def vy64mem : X86MemOperand<"printi64mem">{
367 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
368 let ParserMatchClass = X86MemVY64Operand; }
371 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
372 // plain GR64, so that it doesn't potentially require a REX prefix.
373 def i8mem_NOREX : Operand<i64> {
374 let PrintMethod = "printi8mem";
375 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
376 let ParserMatchClass = X86Mem8AsmOperand;
377 let OperandType = "OPERAND_MEMORY";
380 // GPRs available for tailcall.
381 // It represents GR32_TC, GR64_TC or GR64_TCW64.
382 def ptr_rc_tailcall : PointerLikeRegClass<2>;
384 // Special i32mem for addresses of load folding tail calls. These are not
385 // allowed to use callee-saved registers since they must be scheduled
386 // after callee-saved register are popped.
387 def i32mem_TC : Operand<i32> {
388 let PrintMethod = "printi32mem";
389 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
391 let ParserMatchClass = X86Mem32AsmOperand;
392 let OperandType = "OPERAND_MEMORY";
395 // Special i64mem for addresses of load folding tail calls. These are not
396 // allowed to use callee-saved registers since they must be scheduled
397 // after callee-saved register are popped.
398 def i64mem_TC : Operand<i64> {
399 let PrintMethod = "printi64mem";
400 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
401 ptr_rc_tailcall, i32imm, i8imm);
402 let ParserMatchClass = X86Mem64AsmOperand;
403 let OperandType = "OPERAND_MEMORY";
406 let OperandType = "OPERAND_PCREL",
407 ParserMatchClass = X86AbsMemAsmOperand,
408 PrintMethod = "printPCRelImm" in {
409 def i32imm_pcrel : Operand<i32>;
410 def i16imm_pcrel : Operand<i16>;
412 def offset8 : Operand<i64>;
413 def offset16 : Operand<i64>;
414 def offset32 : Operand<i64>;
415 def offset64 : Operand<i64>;
417 // Branch targets have OtherVT type and print as pc-relative values.
418 def brtarget : Operand<OtherVT>;
419 def brtarget8 : Operand<OtherVT>;
423 def SSECC : Operand<i8> {
424 let PrintMethod = "printSSECC";
425 let OperandType = "OPERAND_IMMEDIATE";
428 def AVXCC : Operand<i8> {
429 let PrintMethod = "printAVXCC";
430 let OperandType = "OPERAND_IMMEDIATE";
433 class ImmSExtAsmOperandClass : AsmOperandClass {
434 let SuperClasses = [ImmAsmOperand];
435 let RenderMethod = "addImmOperands";
438 class ImmZExtAsmOperandClass : AsmOperandClass {
439 let SuperClasses = [ImmAsmOperand];
440 let RenderMethod = "addImmOperands";
443 // Sign-extended immediate classes. We don't need to define the full lattice
444 // here because there is no instruction with an ambiguity between ImmSExti64i32
447 // The strange ranges come from the fact that the assembler always works with
448 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
449 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
452 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
453 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
454 let Name = "ImmSExti64i32";
457 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
458 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
459 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
460 let Name = "ImmSExti16i8";
461 let SuperClasses = [ImmSExti64i32AsmOperand];
464 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
465 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
466 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
467 let Name = "ImmSExti32i8";
471 def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass {
472 let Name = "ImmZExtu32u8";
477 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
478 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
479 let Name = "ImmSExti64i8";
480 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
481 ImmSExti64i32AsmOperand];
484 // A couple of more descriptive operand definitions.
485 // 16-bits but only 8 bits are significant.
486 def i16i8imm : Operand<i16> {
487 let ParserMatchClass = ImmSExti16i8AsmOperand;
488 let OperandType = "OPERAND_IMMEDIATE";
490 // 32-bits but only 8 bits are significant.
491 def i32i8imm : Operand<i32> {
492 let ParserMatchClass = ImmSExti32i8AsmOperand;
493 let OperandType = "OPERAND_IMMEDIATE";
495 // 32-bits but only 8 bits are significant, and those 8 bits are unsigned.
496 def u32u8imm : Operand<i32> {
497 let ParserMatchClass = ImmZExtu32u8AsmOperand;
498 let OperandType = "OPERAND_IMMEDIATE";
501 // 64-bits but only 32 bits are significant.
502 def i64i32imm : Operand<i64> {
503 let ParserMatchClass = ImmSExti64i32AsmOperand;
504 let OperandType = "OPERAND_IMMEDIATE";
507 // 64-bits but only 32 bits are significant, and those bits are treated as being
509 def i64i32imm_pcrel : Operand<i64> {
510 let PrintMethod = "printPCRelImm";
511 let ParserMatchClass = X86AbsMemAsmOperand;
512 let OperandType = "OPERAND_PCREL";
515 // 64-bits but only 8 bits are significant.
516 def i64i8imm : Operand<i64> {
517 let ParserMatchClass = ImmSExti64i8AsmOperand;
518 let OperandType = "OPERAND_IMMEDIATE";
521 def lea64_32mem : Operand<i32> {
522 let PrintMethod = "printi32mem";
523 let AsmOperandLowerMethod = "lower_lea64_32mem";
524 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm);
525 let ParserMatchClass = X86MemAsmOperand;
529 //===----------------------------------------------------------------------===//
530 // X86 Complex Pattern Definitions.
533 // Define X86 specific addressing mode.
534 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
535 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
536 [add, sub, mul, X86mul_imm, shl, or, frameindex],
538 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
539 [tglobaltlsaddr], []>;
541 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
542 [tglobaltlsaddr], []>;
544 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
545 [add, sub, mul, X86mul_imm, shl, or, frameindex,
548 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
549 [tglobaltlsaddr], []>;
551 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
552 [tglobaltlsaddr], []>;
554 //===----------------------------------------------------------------------===//
555 // X86 Instruction Predicate Definitions.
556 def HasCMov : Predicate<"Subtarget->hasCMov()">;
557 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
559 def HasMMX : Predicate<"Subtarget->hasMMX()">;
560 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
561 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
562 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
563 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
564 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
565 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
566 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
567 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
568 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
569 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
570 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
571 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
572 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
573 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
574 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
575 def HasAVX : Predicate<"Subtarget->hasAVX()">;
576 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
577 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
579 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
580 def HasAES : Predicate<"Subtarget->hasAES()">;
581 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
582 def HasFMA : Predicate<"Subtarget->hasFMA()">;
583 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
584 def HasXOP : Predicate<"Subtarget->hasXOP()">;
585 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
586 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
587 def HasF16C : Predicate<"Subtarget->hasF16C()">;
588 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
589 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
590 def HasBMI : Predicate<"Subtarget->hasBMI()">;
591 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
592 def HasRTM : Predicate<"Subtarget->hasRTM()">;
593 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
594 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
595 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
596 def In32BitMode : Predicate<"!Subtarget->is64Bit()">,
597 AssemblerPredicate<"!Mode64Bit", "32-bit mode">;
598 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
599 AssemblerPredicate<"Mode64Bit", "64-bit mode">;
600 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
601 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
602 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
603 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
604 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
605 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
606 "TM.getCodeModel() != CodeModel::Kernel">;
607 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
608 "TM.getCodeModel() == CodeModel::Kernel">;
609 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
610 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
611 def OptForSize : Predicate<"OptForSize">;
612 def OptForSpeed : Predicate<"!OptForSize">;
613 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
614 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
616 //===----------------------------------------------------------------------===//
617 // X86 Instruction Format Definitions.
620 include "X86InstrFormats.td"
622 //===----------------------------------------------------------------------===//
623 // Pattern fragments.
626 // X86 specific condition code. These correspond to CondCode in
627 // X86InstrInfo.h. They must be kept in synch.
628 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
629 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
630 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
631 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
632 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
633 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
634 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
635 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
636 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
637 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
638 def X86_COND_NO : PatLeaf<(i8 10)>;
639 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
640 def X86_COND_NS : PatLeaf<(i8 12)>;
641 def X86_COND_O : PatLeaf<(i8 13)>;
642 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
643 def X86_COND_S : PatLeaf<(i8 15)>;
645 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
646 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
647 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
648 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
651 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
654 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
656 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
658 def i64immZExt32SExt8 : ImmLeaf<i64, [{
659 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
662 // Helper fragments for loads.
663 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
664 // known to be 32-bit aligned or better. Ditto for i8 to i16.
665 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
666 LoadSDNode *LD = cast<LoadSDNode>(N);
667 ISD::LoadExtType ExtType = LD->getExtensionType();
668 if (ExtType == ISD::NON_EXTLOAD)
670 if (ExtType == ISD::EXTLOAD)
671 return LD->getAlignment() >= 2 && !LD->isVolatile();
675 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
676 LoadSDNode *LD = cast<LoadSDNode>(N);
677 ISD::LoadExtType ExtType = LD->getExtensionType();
678 if (ExtType == ISD::EXTLOAD)
679 return LD->getAlignment() >= 2 && !LD->isVolatile();
683 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
684 LoadSDNode *LD = cast<LoadSDNode>(N);
685 ISD::LoadExtType ExtType = LD->getExtensionType();
686 if (ExtType == ISD::NON_EXTLOAD)
688 if (ExtType == ISD::EXTLOAD)
689 return LD->getAlignment() >= 4 && !LD->isVolatile();
693 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
694 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
695 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
696 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
697 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
699 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
700 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
701 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
702 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
703 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
704 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
706 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
707 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
708 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
709 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
710 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
711 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
712 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
713 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
714 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
715 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
717 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
718 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
719 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
720 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
721 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
722 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
723 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
724 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
725 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
726 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
729 // An 'and' node with a single use.
730 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
731 return N->hasOneUse();
733 // An 'srl' node with a single use.
734 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
735 return N->hasOneUse();
737 // An 'trunc' node with a single use.
738 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
739 return N->hasOneUse();
742 //===----------------------------------------------------------------------===//
747 let neverHasSideEffects = 1 in {
748 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
749 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
750 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize;
751 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
752 "nop{l}\t$zero", [], IIC_NOP>, TB;
756 // Constructing a stack frame.
757 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
758 "enter\t$len, $lvl", [], IIC_ENTER>;
760 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
761 def LEAVE : I<0xC9, RawFrm,
762 (outs), (ins), "leave", [], IIC_LEAVE>,
763 Requires<[In32BitMode]>;
765 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
766 def LEAVE64 : I<0xC9, RawFrm,
767 (outs), (ins), "leave", [], IIC_LEAVE>,
768 Requires<[In64BitMode]>;
770 //===----------------------------------------------------------------------===//
771 // Miscellaneous Instructions.
774 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
776 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
777 IIC_POP_REG16>, OpSize;
778 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
780 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
781 IIC_POP_REG>, OpSize;
782 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", [],
783 IIC_POP_MEM>, OpSize;
784 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
786 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", [],
789 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, OpSize;
790 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
791 Requires<[In32BitMode]>;
794 let mayStore = 1 in {
795 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
796 IIC_PUSH_REG>, OpSize;
797 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
799 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
800 IIC_PUSH_REG>, OpSize;
801 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
804 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
806 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
809 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
810 "push{l}\t$imm", [], IIC_PUSH_IMM>;
811 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
812 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize;
813 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
814 "push{l}\t$imm", [], IIC_PUSH_IMM>;
816 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
818 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
819 Requires<[In32BitMode]>;
824 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
826 def POP64r : I<0x58, AddRegFrm,
827 (outs GR64:$reg), (ins), "pop{q}\t$reg", [], IIC_POP_REG>;
828 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
830 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", [],
833 let mayStore = 1 in {
834 def PUSH64r : I<0x50, AddRegFrm,
835 (outs), (ins GR64:$reg), "push{q}\t$reg", [], IIC_PUSH_REG>;
836 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
838 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
843 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
844 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
845 "push{q}\t$imm", [], IIC_PUSH_IMM>;
846 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
847 "push{q}\t$imm", [], IIC_PUSH_IMM>;
848 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
849 "push{q}\t$imm", [], IIC_PUSH_IMM>;
852 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
853 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
854 Requires<[In64BitMode]>;
855 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
856 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
857 Requires<[In64BitMode]>;
861 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
862 mayLoad=1, neverHasSideEffects=1 in {
863 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", [], IIC_POP_A>,
864 Requires<[In32BitMode]>;
866 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
867 mayStore=1, neverHasSideEffects=1 in {
868 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", [], IIC_PUSH_A>,
869 Requires<[In32BitMode]>;
872 let Constraints = "$src = $dst" in { // GR32 = bswap GR32
873 def BSWAP32r : I<0xC8, AddRegFrm,
874 (outs GR32:$dst), (ins GR32:$src),
876 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, TB;
878 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
880 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
881 } // Constraints = "$src = $dst"
883 // Bit scan instructions.
884 let Defs = [EFLAGS] in {
885 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
886 "bsf{w}\t{$src, $dst|$dst, $src}",
887 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
888 IIC_BSF>, TB, OpSize;
889 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
890 "bsf{w}\t{$src, $dst|$dst, $src}",
891 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
892 IIC_BSF>, TB, OpSize;
893 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
894 "bsf{l}\t{$src, $dst|$dst, $src}",
895 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))], IIC_BSF>, TB;
896 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
897 "bsf{l}\t{$src, $dst|$dst, $src}",
898 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
900 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
901 "bsf{q}\t{$src, $dst|$dst, $src}",
902 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
904 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
905 "bsf{q}\t{$src, $dst|$dst, $src}",
906 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
909 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
910 "bsr{w}\t{$src, $dst|$dst, $src}",
911 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))], IIC_BSR>,
913 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
914 "bsr{w}\t{$src, $dst|$dst, $src}",
915 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
918 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
919 "bsr{l}\t{$src, $dst|$dst, $src}",
920 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))], IIC_BSR>, TB;
921 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
922 "bsr{l}\t{$src, $dst|$dst, $src}",
923 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
925 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
926 "bsr{q}\t{$src, $dst|$dst, $src}",
927 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], IIC_BSR>, TB;
928 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
929 "bsr{q}\t{$src, $dst|$dst, $src}",
930 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
935 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
936 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
937 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", [], IIC_MOVS>;
938 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", [], IIC_MOVS>, OpSize;
939 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", [], IIC_MOVS>;
940 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", [], IIC_MOVS>;
943 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
944 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
945 def STOSB : I<0xAA, RawFrm, (outs), (ins), "stosb", [], IIC_STOS>;
946 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
947 def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", [], IIC_STOS>, OpSize;
948 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
949 def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", [], IIC_STOS>;
950 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
951 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", [], IIC_STOS>;
953 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", [], IIC_SCAS>;
954 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", [], IIC_SCAS>, OpSize;
955 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", [], IIC_SCAS>;
956 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", [], IIC_SCAS>;
958 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", [], IIC_CMPS>;
959 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", [], IIC_CMPS>, OpSize;
960 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", [], IIC_CMPS>;
961 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", [], IIC_CMPS>;
964 //===----------------------------------------------------------------------===//
965 // Move Instructions.
968 let neverHasSideEffects = 1 in {
969 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
970 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
971 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
972 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
973 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
974 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
975 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
976 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
978 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
979 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
980 "mov{b}\t{$src, $dst|$dst, $src}",
981 [(set GR8:$dst, imm:$src)], IIC_MOV>;
982 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
983 "mov{w}\t{$src, $dst|$dst, $src}",
984 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize;
985 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
986 "mov{l}\t{$src, $dst|$dst, $src}",
987 [(set GR32:$dst, imm:$src)], IIC_MOV>;
988 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
989 "movabs{q}\t{$src, $dst|$dst, $src}",
990 [(set GR64:$dst, imm:$src)], IIC_MOV>;
991 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
992 "mov{q}\t{$src, $dst|$dst, $src}",
993 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
996 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
997 "mov{b}\t{$src, $dst|$dst, $src}",
998 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
999 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1000 "mov{w}\t{$src, $dst|$dst, $src}",
1001 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize;
1002 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1003 "mov{l}\t{$src, $dst|$dst, $src}",
1004 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>;
1005 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1006 "mov{q}\t{$src, $dst|$dst, $src}",
1007 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
1009 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
1010 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
1011 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
1012 "mov{b}\t{$src, %al|AL, $src}", [], IIC_MOV_MEM>,
1013 Requires<[In32BitMode]>;
1014 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
1015 "mov{w}\t{$src, %ax|AL, $src}", [], IIC_MOV_MEM>, OpSize,
1016 Requires<[In32BitMode]>;
1017 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1018 "mov{l}\t{$src, %eax|EAX, $src}", [], IIC_MOV_MEM>,
1019 Requires<[In32BitMode]>;
1020 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1021 "mov{b}\t{%al, $dst|$dst, AL}", [], IIC_MOV_MEM>,
1022 Requires<[In32BitMode]>;
1023 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1024 "mov{w}\t{%ax, $dst|$dst, AL}", [], IIC_MOV_MEM>, OpSize,
1025 Requires<[In32BitMode]>;
1026 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1027 "mov{l}\t{%eax, $dst|$dst, EAX}", [], IIC_MOV_MEM>,
1028 Requires<[In32BitMode]>;
1030 // FIXME: These definitions are utterly broken
1031 // Just leave them commented out for now because they're useless outside
1032 // of the large code model, and most compilers won't generate the instructions
1035 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
1036 "mov{q}\t{$src, %rax|RAX, $src}", []>;
1037 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
1038 "mov{q}\t{$src, %rax|RAX, $src}", []>;
1039 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
1040 "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
1041 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
1042 "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
1046 let isCodeGenOnly = 1 in {
1047 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1048 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1049 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1050 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
1051 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1052 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1053 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1054 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1057 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1058 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1059 "mov{b}\t{$src, $dst|$dst, $src}",
1060 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1061 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1062 "mov{w}\t{$src, $dst|$dst, $src}",
1063 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize;
1064 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1065 "mov{l}\t{$src, $dst|$dst, $src}",
1066 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>;
1067 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1068 "mov{q}\t{$src, $dst|$dst, $src}",
1069 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1072 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1073 "mov{b}\t{$src, $dst|$dst, $src}",
1074 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1075 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1076 "mov{w}\t{$src, $dst|$dst, $src}",
1077 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize;
1078 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1079 "mov{l}\t{$src, $dst|$dst, $src}",
1080 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>;
1081 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1082 "mov{q}\t{$src, $dst|$dst, $src}",
1083 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1085 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1086 // that they can be used for copying and storing h registers, which can't be
1087 // encoded when a REX prefix is present.
1088 let isCodeGenOnly = 1 in {
1089 let neverHasSideEffects = 1 in
1090 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1091 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1092 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>;
1094 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1095 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1096 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1098 let mayLoad = 1, neverHasSideEffects = 1,
1099 canFoldAsLoad = 1, isReMaterializable = 1 in
1100 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1101 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1102 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1107 // Condition code ops, incl. set if equal/not equal/...
1108 let Defs = [EFLAGS], Uses = [AH] in
1109 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1110 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
1111 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
1112 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1113 IIC_AHF>; // AH = flags
1116 //===----------------------------------------------------------------------===//
1117 // Bit tests instructions: BT, BTS, BTR, BTC.
1119 let Defs = [EFLAGS] in {
1120 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1121 "bt{w}\t{$src2, $src1|$src1, $src2}",
1122 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1124 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1125 "bt{l}\t{$src2, $src1|$src1, $src2}",
1126 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>, TB;
1127 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1128 "bt{q}\t{$src2, $src1|$src1, $src2}",
1129 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1131 // Unlike with the register+register form, the memory+register form of the
1132 // bt instruction does not ignore the high bits of the index. From ISel's
1133 // perspective, this is pretty bizarre. Make these instructions disassembly
1136 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1137 "bt{w}\t{$src2, $src1|$src1, $src2}",
1138 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1139 // (implicit EFLAGS)]
1141 >, OpSize, TB, Requires<[FastBTMem]>;
1142 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1143 "bt{l}\t{$src2, $src1|$src1, $src2}",
1144 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1145 // (implicit EFLAGS)]
1147 >, TB, Requires<[FastBTMem]>;
1148 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1149 "bt{q}\t{$src2, $src1|$src1, $src2}",
1150 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1151 // (implicit EFLAGS)]
1155 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1156 "bt{w}\t{$src2, $src1|$src1, $src2}",
1157 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1158 IIC_BT_RI>, OpSize, TB;
1159 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1160 "bt{l}\t{$src2, $src1|$src1, $src2}",
1161 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1163 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1164 "bt{q}\t{$src2, $src1|$src1, $src2}",
1165 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1168 // Note that these instructions don't need FastBTMem because that
1169 // only applies when the other operand is in a register. When it's
1170 // an immediate, bt is still fast.
1171 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1172 "bt{w}\t{$src2, $src1|$src1, $src2}",
1173 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1174 ], IIC_BT_MI>, OpSize, TB;
1175 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1176 "bt{l}\t{$src2, $src1|$src1, $src2}",
1177 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1179 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1180 "bt{q}\t{$src2, $src1|$src1, $src2}",
1181 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1182 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1185 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1186 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1188 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1189 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1190 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1191 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1192 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1193 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1195 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1196 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1197 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1198 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1199 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1200 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1202 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1203 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1204 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1205 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1206 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1207 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1209 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1210 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1211 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1212 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1214 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1215 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1217 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1218 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1219 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1220 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1221 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1222 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1224 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1225 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1226 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1227 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1228 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1229 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1231 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1232 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1233 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1234 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1235 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1236 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1238 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1239 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1240 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1241 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1243 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1244 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1246 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1247 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1248 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1249 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1250 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1251 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1253 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1254 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1255 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1256 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1257 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1258 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1260 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1261 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1262 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1263 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1264 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1265 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1267 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1268 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1269 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1270 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1271 } // Defs = [EFLAGS]
1274 //===----------------------------------------------------------------------===//
1278 // Atomic swap. These are just normal xchg instructions. But since a memory
1279 // operand is referenced, the atomicity is ensured.
1280 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
1281 InstrItinClass itin> {
1282 let Constraints = "$val = $dst" in {
1283 def #NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
1284 (ins GR8:$val, i8mem:$ptr),
1285 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
1288 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
1290 def #NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
1291 (ins GR16:$val, i16mem:$ptr),
1292 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
1295 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
1297 def #NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
1298 (ins GR32:$val, i32mem:$ptr),
1299 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
1302 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
1304 def #NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
1305 (ins GR64:$val, i64mem:$ptr),
1306 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
1309 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
1314 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
1316 // Swap between registers.
1317 let Constraints = "$val = $dst" in {
1318 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1319 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1320 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1321 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, OpSize;
1322 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1323 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1324 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1325 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1328 // Swap between EAX and other registers.
1329 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1330 "xchg{w}\t{$src, %ax|AX, $src}", [], IIC_XCHG_REG>, OpSize;
1331 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1332 "xchg{l}\t{$src, %eax|EAX, $src}", [], IIC_XCHG_REG>,
1333 Requires<[In32BitMode]>;
1334 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1335 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1336 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1337 "xchg{l}\t{$src, %eax|EAX, $src}", [], IIC_XCHG_REG>,
1338 Requires<[In64BitMode]>;
1339 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1340 "xchg{q}\t{$src, %rax|RAX, $src}", [], IIC_XCHG_REG>;
1344 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1345 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1346 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1347 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1349 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1350 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1351 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1352 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1354 let mayLoad = 1, mayStore = 1 in {
1355 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1356 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1357 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1358 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1360 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1361 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1362 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1363 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1367 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1368 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1369 IIC_CMPXCHG_REG8>, TB;
1370 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1371 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1372 IIC_CMPXCHG_REG>, TB, OpSize;
1373 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1374 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1375 IIC_CMPXCHG_REG>, TB;
1376 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1377 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1378 IIC_CMPXCHG_REG>, TB;
1380 let mayLoad = 1, mayStore = 1 in {
1381 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1382 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1383 IIC_CMPXCHG_MEM8>, TB;
1384 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1385 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1386 IIC_CMPXCHG_MEM>, TB, OpSize;
1387 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1388 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1389 IIC_CMPXCHG_MEM>, TB;
1390 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1391 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1392 IIC_CMPXCHG_MEM>, TB;
1395 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1396 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1397 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1399 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1400 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1401 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1402 TB, Requires<[HasCmpxchg16b]>;
1406 // Lock instruction prefix
1407 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1409 // Rex64 instruction prefix
1410 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>;
1412 // Data16 instruction prefix
1413 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1415 // Repeat string operation instruction prefixes
1416 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1417 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1418 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1419 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1420 // Repeat while not equal (used with CMPS and SCAS)
1421 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1425 // String manipulation instructions
1426 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", [], IIC_LODS>;
1427 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", [], IIC_LODS>, OpSize;
1428 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", [], IIC_LODS>;
1429 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", [], IIC_LODS>;
1431 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", [], IIC_OUTS>;
1432 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", [], IIC_OUTS>, OpSize;
1433 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", [], IIC_OUTS>;
1436 // Flag instructions
1437 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1438 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1439 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1440 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1441 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1442 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1443 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1445 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1447 // Table lookup instructions
1448 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>;
1450 // ASCII Adjust After Addition
1451 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1452 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1453 Requires<[In32BitMode]>;
1455 // ASCII Adjust AX Before Division
1456 // sets AL, AH and EFLAGS and uses AL and AH
1457 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1458 "aad\t$src", [], IIC_AAD>, Requires<[In32BitMode]>;
1460 // ASCII Adjust AX After Multiply
1461 // sets AL, AH and EFLAGS and uses AL
1462 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1463 "aam\t$src", [], IIC_AAM>, Requires<[In32BitMode]>;
1465 // ASCII Adjust AL After Subtraction - sets
1466 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1467 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1468 Requires<[In32BitMode]>;
1470 // Decimal Adjust AL after Addition
1471 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1472 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1473 Requires<[In32BitMode]>;
1475 // Decimal Adjust AL after Subtraction
1476 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1477 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1478 Requires<[In32BitMode]>;
1480 // Check Array Index Against Bounds
1481 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1482 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize,
1483 Requires<[In32BitMode]>;
1484 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1485 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>,
1486 Requires<[In32BitMode]>;
1488 // Adjust RPL Field of Segment Selector
1489 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$src), (ins GR16:$dst),
1490 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1491 Requires<[In32BitMode]>;
1492 def ARPL16mr : I<0x63, MRMSrcMem, (outs GR16:$src), (ins i16mem:$dst),
1493 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1494 Requires<[In32BitMode]>;
1496 //===----------------------------------------------------------------------===//
1497 // MOVBE Instructions
1499 let Predicates = [HasMOVBE] in {
1500 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1501 "movbe{w}\t{$src, $dst|$dst, $src}",
1502 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1504 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1505 "movbe{l}\t{$src, $dst|$dst, $src}",
1506 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1508 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1509 "movbe{q}\t{$src, $dst|$dst, $src}",
1510 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
1512 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1513 "movbe{w}\t{$src, $dst|$dst, $src}",
1514 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1516 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1517 "movbe{l}\t{$src, $dst|$dst, $src}",
1518 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1520 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1521 "movbe{q}\t{$src, $dst|$dst, $src}",
1522 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
1526 //===----------------------------------------------------------------------===//
1527 // RDRAND Instruction
1529 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1530 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1532 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize, TB;
1533 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1535 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, TB;
1536 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1538 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
1541 //===----------------------------------------------------------------------===//
1542 // LZCNT Instruction
1544 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
1545 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1546 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1547 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
1549 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1550 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1551 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
1552 (implicit EFLAGS)]>, XS, OpSize;
1554 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1555 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1556 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS;
1557 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1558 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1559 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
1560 (implicit EFLAGS)]>, XS;
1562 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1563 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1564 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
1566 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1567 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1568 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
1569 (implicit EFLAGS)]>, XS;
1572 //===----------------------------------------------------------------------===//
1575 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1576 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1577 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1578 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
1580 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1581 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1582 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
1583 (implicit EFLAGS)]>, XS, OpSize;
1585 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1586 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1587 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS;
1588 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1589 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1590 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
1591 (implicit EFLAGS)]>, XS;
1593 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1594 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1595 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
1597 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1598 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1599 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
1600 (implicit EFLAGS)]>, XS;
1603 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
1604 RegisterClass RC, X86MemOperand x86memop, SDNode OpNode,
1606 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
1607 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1608 [(set RC:$dst, (OpNode RC:$src)), (implicit EFLAGS)]>, T8, VEX_4V;
1609 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
1610 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1611 [(set RC:$dst, (OpNode (ld_frag addr:$src))), (implicit EFLAGS)]>,
1615 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1616 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem,
1618 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem,
1619 X86blsr, loadi64>, VEX_W;
1620 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem,
1621 X86blsmsk, loadi32>;
1622 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem,
1623 X86blsmsk, loadi64>, VEX_W;
1624 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem,
1626 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem,
1627 X86blsi, loadi64>, VEX_W;
1630 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
1631 X86MemOperand x86memop, Intrinsic Int,
1633 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1634 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1635 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
1637 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
1638 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1639 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
1640 (implicit EFLAGS)]>, T8, VEX_4VOp3;
1643 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1644 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
1645 int_x86_bmi_bextr_32, loadi32>;
1646 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
1647 int_x86_bmi_bextr_64, loadi64>, VEX_W;
1650 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
1651 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
1652 int_x86_bmi_bzhi_32, loadi32>;
1653 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
1654 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
1657 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
1658 X86MemOperand x86memop, Intrinsic Int,
1660 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1661 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1662 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
1664 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1665 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1666 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
1669 let Predicates = [HasBMI2] in {
1670 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
1671 int_x86_bmi_pdep_32, loadi32>, T8XD;
1672 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
1673 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
1674 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
1675 int_x86_bmi_pext_32, loadi32>, T8XS;
1676 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
1677 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
1680 //===----------------------------------------------------------------------===//
1682 //===----------------------------------------------------------------------===//
1684 include "X86InstrArithmetic.td"
1685 include "X86InstrCMovSetCC.td"
1686 include "X86InstrExtension.td"
1687 include "X86InstrControl.td"
1688 include "X86InstrShiftRotate.td"
1690 // X87 Floating Point Stack.
1691 include "X86InstrFPStack.td"
1693 // SIMD support (SSE, MMX and AVX)
1694 include "X86InstrFragmentsSIMD.td"
1696 // FMA - Fused Multiply-Add support (requires FMA)
1697 include "X86InstrFMA.td"
1700 include "X86InstrXOP.td"
1702 // SSE, MMX and 3DNow! vector support.
1703 include "X86InstrSSE.td"
1704 include "X86InstrMMX.td"
1705 include "X86Instr3DNow.td"
1707 include "X86InstrVMX.td"
1708 include "X86InstrSVM.td"
1710 include "X86InstrTSX.td"
1712 // System instructions.
1713 include "X86InstrSystem.td"
1715 // Compiler Pseudo Instructions and Pat Patterns
1716 include "X86InstrCompiler.td"
1718 //===----------------------------------------------------------------------===//
1719 // Assembler Mnemonic Aliases
1720 //===----------------------------------------------------------------------===//
1722 def : MnemonicAlias<"call", "calll">, Requires<[In32BitMode]>;
1723 def : MnemonicAlias<"call", "callq">, Requires<[In64BitMode]>;
1725 def : MnemonicAlias<"cbw", "cbtw">;
1726 def : MnemonicAlias<"cwde", "cwtl">;
1727 def : MnemonicAlias<"cwd", "cwtd">;
1728 def : MnemonicAlias<"cdq", "cltd">;
1729 def : MnemonicAlias<"cdqe", "cltq">;
1730 def : MnemonicAlias<"cqo", "cqto">;
1732 // lret maps to lretl, it is not ambiguous with lretq.
1733 def : MnemonicAlias<"lret", "lretl">;
1735 def : MnemonicAlias<"leavel", "leave">, Requires<[In32BitMode]>;
1736 def : MnemonicAlias<"leaveq", "leave">, Requires<[In64BitMode]>;
1738 def : MnemonicAlias<"loopz", "loope">;
1739 def : MnemonicAlias<"loopnz", "loopne">;
1741 def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
1742 def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
1743 def : MnemonicAlias<"popf", "popfl">, Requires<[In32BitMode]>;
1744 def : MnemonicAlias<"popf", "popfq">, Requires<[In64BitMode]>;
1745 def : MnemonicAlias<"popfd", "popfl">;
1747 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
1748 // all modes. However: "push (addr)" and "push $42" should default to
1749 // pushl/pushq depending on the current mode. Similar for "pop %bx"
1750 def : MnemonicAlias<"push", "pushl">, Requires<[In32BitMode]>;
1751 def : MnemonicAlias<"push", "pushq">, Requires<[In64BitMode]>;
1752 def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
1753 def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1754 def : MnemonicAlias<"pushfd", "pushfl">;
1756 def : MnemonicAlias<"repe", "rep">;
1757 def : MnemonicAlias<"repz", "rep">;
1758 def : MnemonicAlias<"repnz", "repne">;
1760 def : MnemonicAlias<"retl", "ret">, Requires<[In32BitMode]>;
1761 def : MnemonicAlias<"retq", "ret">, Requires<[In64BitMode]>;
1763 def : MnemonicAlias<"salb", "shlb">;
1764 def : MnemonicAlias<"salw", "shlw">;
1765 def : MnemonicAlias<"sall", "shll">;
1766 def : MnemonicAlias<"salq", "shlq">;
1768 def : MnemonicAlias<"smovb", "movsb">;
1769 def : MnemonicAlias<"smovw", "movsw">;
1770 def : MnemonicAlias<"smovl", "movsl">;
1771 def : MnemonicAlias<"smovq", "movsq">;
1773 def : MnemonicAlias<"ud2a", "ud2">;
1774 def : MnemonicAlias<"verrw", "verr">;
1776 // System instruction aliases.
1777 def : MnemonicAlias<"iret", "iretl">;
1778 def : MnemonicAlias<"sysret", "sysretl">;
1779 def : MnemonicAlias<"sysexit", "sysexitl">;
1781 def : MnemonicAlias<"lgdtl", "lgdt">, Requires<[In32BitMode]>;
1782 def : MnemonicAlias<"lgdtq", "lgdt">, Requires<[In64BitMode]>;
1783 def : MnemonicAlias<"lidtl", "lidt">, Requires<[In32BitMode]>;
1784 def : MnemonicAlias<"lidtq", "lidt">, Requires<[In64BitMode]>;
1785 def : MnemonicAlias<"sgdtl", "sgdt">, Requires<[In32BitMode]>;
1786 def : MnemonicAlias<"sgdtq", "sgdt">, Requires<[In64BitMode]>;
1787 def : MnemonicAlias<"sidtl", "sidt">, Requires<[In32BitMode]>;
1788 def : MnemonicAlias<"sidtq", "sidt">, Requires<[In64BitMode]>;
1791 // Floating point stack aliases.
1792 def : MnemonicAlias<"fcmovz", "fcmove">;
1793 def : MnemonicAlias<"fcmova", "fcmovnbe">;
1794 def : MnemonicAlias<"fcmovnae", "fcmovb">;
1795 def : MnemonicAlias<"fcmovna", "fcmovbe">;
1796 def : MnemonicAlias<"fcmovae", "fcmovnb">;
1797 def : MnemonicAlias<"fcomip", "fcompi">;
1798 def : MnemonicAlias<"fildq", "fildll">;
1799 def : MnemonicAlias<"fistpq", "fistpll">;
1800 def : MnemonicAlias<"fisttpq", "fisttpll">;
1801 def : MnemonicAlias<"fldcww", "fldcw">;
1802 def : MnemonicAlias<"fnstcww", "fnstcw">;
1803 def : MnemonicAlias<"fnstsww", "fnstsw">;
1804 def : MnemonicAlias<"fucomip", "fucompi">;
1805 def : MnemonicAlias<"fwait", "wait">;
1808 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond>
1809 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
1810 !strconcat(Prefix, NewCond, Suffix)>;
1812 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
1813 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
1814 /// example "setz" -> "sete".
1815 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix> {
1816 def C : CondCodeAlias<Prefix, Suffix, "c", "b">; // setc -> setb
1817 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e">; // setz -> sete
1818 def NA : CondCodeAlias<Prefix, Suffix, "na", "be">; // setna -> setbe
1819 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae">; // setnb -> setae
1820 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae">; // setnc -> setae
1821 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le">; // setng -> setle
1822 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge">; // setnl -> setge
1823 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne">; // setnz -> setne
1824 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p">; // setpe -> setp
1825 def PO : CondCodeAlias<Prefix, Suffix, "po", "np">; // setpo -> setnp
1827 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b">; // setnae -> setb
1828 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a">; // setnbe -> seta
1829 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l">; // setnge -> setl
1830 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g">; // setnle -> setg
1833 // Aliases for set<CC>
1834 defm : IntegerCondCodeMnemonicAlias<"set", "">;
1835 // Aliases for j<CC>
1836 defm : IntegerCondCodeMnemonicAlias<"j", "">;
1837 // Aliases for cmov<CC>{w,l,q}
1838 defm : IntegerCondCodeMnemonicAlias<"cmov", "w">;
1839 defm : IntegerCondCodeMnemonicAlias<"cmov", "l">;
1840 defm : IntegerCondCodeMnemonicAlias<"cmov", "q">;
1843 //===----------------------------------------------------------------------===//
1844 // Assembler Instruction Aliases
1845 //===----------------------------------------------------------------------===//
1847 // aad/aam default to base 10 if no operand is specified.
1848 def : InstAlias<"aad", (AAD8i8 10)>;
1849 def : InstAlias<"aam", (AAM8i8 10)>;
1851 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
1852 def : InstAlias<"bt $imm, $mem", (BT32mi8 i32mem:$mem, i32i8imm:$imm)>;
1855 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>;
1856 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>;
1857 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
1858 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
1860 // div and idiv aliases for explicit A register.
1861 def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>;
1862 def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>;
1863 def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>;
1864 def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>;
1865 def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>;
1866 def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>;
1867 def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>;
1868 def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>;
1869 def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>;
1870 def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>;
1871 def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>;
1872 def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>;
1873 def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>;
1874 def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>;
1875 def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>;
1876 def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>;
1880 // Various unary fpstack operations default to operating on on ST1.
1881 // For example, "fxch" -> "fxch %st(1)"
1882 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
1883 def : InstAlias<"fsubp", (SUBR_FPrST0 ST1)>;
1884 def : InstAlias<"fsubrp", (SUB_FPrST0 ST1)>;
1885 def : InstAlias<"fmulp", (MUL_FPrST0 ST1)>;
1886 def : InstAlias<"fdivp", (DIVR_FPrST0 ST1)>;
1887 def : InstAlias<"fdivrp", (DIV_FPrST0 ST1)>;
1888 def : InstAlias<"fxch", (XCH_F ST1)>;
1889 def : InstAlias<"fcomi", (COM_FIr ST1)>;
1890 def : InstAlias<"fcompi", (COM_FIPr ST1)>;
1891 def : InstAlias<"fucom", (UCOM_Fr ST1)>;
1892 def : InstAlias<"fucomp", (UCOM_FPr ST1)>;
1893 def : InstAlias<"fucomi", (UCOM_FIr ST1)>;
1894 def : InstAlias<"fucompi", (UCOM_FIPr ST1)>;
1896 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
1897 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
1898 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
1900 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
1901 def : InstAlias<!strconcat(Mnemonic, " $op, %st(0)"),
1902 (Inst RST:$op), EmitAlias>;
1903 def : InstAlias<!strconcat(Mnemonic, " %st(0), %st(0)"),
1904 (Inst ST0), EmitAlias>;
1907 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
1908 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
1909 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
1910 defm : FpUnaryAlias<"fsubp", SUBR_FPrST0>;
1911 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
1912 defm : FpUnaryAlias<"fsubrp", SUB_FPrST0>;
1913 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
1914 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
1915 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
1916 defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>;
1917 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
1918 defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>;
1919 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
1920 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
1921 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
1922 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
1925 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
1926 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
1927 // solely because gas supports it.
1928 def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op), 0>;
1929 def : InstAlias<"fmulp %st(0), $op", (MUL_FPrST0 RST:$op)>;
1930 def : InstAlias<"fsubp %st(0), $op", (SUBR_FPrST0 RST:$op)>;
1931 def : InstAlias<"fsubrp %st(0), $op", (SUB_FPrST0 RST:$op)>;
1932 def : InstAlias<"fdivp %st(0), $op", (DIVR_FPrST0 RST:$op)>;
1933 def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>;
1935 // We accept "fnstsw %eax" even though it only writes %ax.
1936 def : InstAlias<"fnstsw %eax", (FNSTSW16r)>;
1937 def : InstAlias<"fnstsw %al" , (FNSTSW16r)>;
1938 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
1940 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
1941 // this is compatible with what GAS does.
1942 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1943 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1944 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>;
1945 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>;
1947 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
1948 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
1949 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
1950 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
1951 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
1952 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
1953 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
1955 // inb %dx -> inb %al, %dx
1956 def : InstAlias<"inb %dx", (IN8rr)>;
1957 def : InstAlias<"inw %dx", (IN16rr)>;
1958 def : InstAlias<"inl %dx", (IN32rr)>;
1959 def : InstAlias<"inb $port", (IN8ri i8imm:$port)>;
1960 def : InstAlias<"inw $port", (IN16ri i8imm:$port)>;
1961 def : InstAlias<"inl $port", (IN32ri i8imm:$port)>;
1964 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
1965 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1966 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1967 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
1968 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
1969 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1970 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1972 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
1973 // the move. All segment/mem forms are equivalent, this has the shortest
1975 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
1976 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
1978 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
1979 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
1981 // Match 'movq GR64, MMX' as an alias for movd.
1982 def : InstAlias<"movq $src, $dst",
1983 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
1984 def : InstAlias<"movq $src, $dst",
1985 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
1987 // movsd with no operands (as opposed to the SSE scalar move of a double) is an
1988 // alias for movsl. (as in rep; movsd)
1989 def : InstAlias<"movsd", (MOVSD)>;
1992 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
1993 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
1994 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
1995 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
1996 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
1997 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
1998 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
2001 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
2002 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
2003 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
2004 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
2005 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
2006 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
2007 // Note: No GR32->GR64 movzx form.
2009 // outb %dx -> outb %al, %dx
2010 def : InstAlias<"outb %dx", (OUT8rr)>;
2011 def : InstAlias<"outw %dx", (OUT16rr)>;
2012 def : InstAlias<"outl %dx", (OUT32rr)>;
2013 def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>;
2014 def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>;
2015 def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>;
2017 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
2018 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
2019 // errors, since its encoding is the most compact.
2020 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
2022 // shld/shrd op,op -> shld op, op, CL
2023 def : InstAlias<"shldw $r2, $r1", (SHLD16rrCL GR16:$r1, GR16:$r2)>;
2024 def : InstAlias<"shldl $r2, $r1", (SHLD32rrCL GR32:$r1, GR32:$r2)>;
2025 def : InstAlias<"shldq $r2, $r1", (SHLD64rrCL GR64:$r1, GR64:$r2)>;
2026 def : InstAlias<"shrdw $r2, $r1", (SHRD16rrCL GR16:$r1, GR16:$r2)>;
2027 def : InstAlias<"shrdl $r2, $r1", (SHRD32rrCL GR32:$r1, GR32:$r2)>;
2028 def : InstAlias<"shrdq $r2, $r1", (SHRD64rrCL GR64:$r1, GR64:$r2)>;
2030 def : InstAlias<"shldw $reg, $mem", (SHLD16mrCL i16mem:$mem, GR16:$reg)>;
2031 def : InstAlias<"shldl $reg, $mem", (SHLD32mrCL i32mem:$mem, GR32:$reg)>;
2032 def : InstAlias<"shldq $reg, $mem", (SHLD64mrCL i64mem:$mem, GR64:$reg)>;
2033 def : InstAlias<"shrdw $reg, $mem", (SHRD16mrCL i16mem:$mem, GR16:$reg)>;
2034 def : InstAlias<"shrdl $reg, $mem", (SHRD32mrCL i32mem:$mem, GR32:$reg)>;
2035 def : InstAlias<"shrdq $reg, $mem", (SHRD64mrCL i64mem:$mem, GR64:$reg)>;
2037 /* FIXME: This is disabled because the asm matcher is currently incapable of
2038 * matching a fixed immediate like $1.
2039 // "shl X, $1" is an alias for "shl X".
2040 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
2041 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2042 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
2043 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2044 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
2045 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2046 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
2047 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2048 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
2049 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2050 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
2051 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2052 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
2053 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2054 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
2055 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2056 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2059 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2060 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
2061 defm : ShiftRotateByOneAlias<"rol", "ROL">;
2062 defm : ShiftRotateByOneAlias<"ror", "ROR">;
2065 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
2066 def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>;
2067 def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>;
2068 def : InstAlias<"testl $val, $mem", (TEST32rm GR32:$val, i32mem:$mem)>;
2069 def : InstAlias<"testq $val, $mem", (TEST64rm GR64:$val, i64mem:$mem)>;
2071 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
2072 def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>;
2073 def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>;
2074 def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>;
2075 def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>;
2077 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
2078 def : InstAlias<"xchgw %ax, $src", (XCHG16ar GR16:$src)>;
2079 def : InstAlias<"xchgl %eax, $src", (XCHG32ar GR32:$src)>, Requires<[In32BitMode]>;
2080 def : InstAlias<"xchgl %eax, $src", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
2081 def : InstAlias<"xchgq %rax, $src", (XCHG64ar GR64:$src)>;