1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
35 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
49 // RES1, RES2, FLAGS = op LHS, RHS
50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
54 SDTCisInt<0>, SDTCisVT<1, i32>]>;
55 def SDTX86BrCond : SDTypeProfile<0, 3,
56 [SDTCisVT<0, OtherVT>,
57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 def SDTX86SetCC : SDTypeProfile<1, 2,
61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
62 def SDTX86SetCC_C : SDTypeProfile<1, 2,
64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
66 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
68 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
70 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
72 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
74 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
75 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
76 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
78 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
79 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
82 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
84 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
88 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
94 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
96 def SDTX86Void : SDTypeProfile<0, 0, []>;
98 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
100 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
102 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
104 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
106 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
108 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
110 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
112 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
114 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
116 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
118 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
120 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
122 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
126 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
127 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
128 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
129 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
131 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
132 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
134 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
135 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
137 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
138 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
140 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
142 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
143 [SDNPHasChain, SDNPSideEffect]>;
145 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
146 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
147 SDNPMayLoad, SDNPMemOperand]>;
148 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
149 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
150 SDNPMayLoad, SDNPMemOperand]>;
151 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
152 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
153 SDNPMayLoad, SDNPMemOperand]>;
155 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
156 [SDNPHasChain, SDNPMayStore,
157 SDNPMayLoad, SDNPMemOperand]>;
158 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
159 [SDNPHasChain, SDNPMayStore,
160 SDNPMayLoad, SDNPMemOperand]>;
161 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
162 [SDNPHasChain, SDNPMayStore,
163 SDNPMayLoad, SDNPMemOperand]>;
164 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
165 [SDNPHasChain, SDNPMayStore,
166 SDNPMayLoad, SDNPMemOperand]>;
167 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
168 [SDNPHasChain, SDNPMayStore,
169 SDNPMayLoad, SDNPMemOperand]>;
170 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
171 [SDNPHasChain, SDNPMayStore,
172 SDNPMayLoad, SDNPMemOperand]>;
173 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
174 [SDNPHasChain, SDNPMayStore,
175 SDNPMayLoad, SDNPMemOperand]>;
176 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
177 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
179 def X86vastart_save_xmm_regs :
180 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
181 SDT_X86VASTART_SAVE_XMM_REGS,
182 [SDNPHasChain, SDNPVariadic]>;
184 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
185 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
187 def X86callseq_start :
188 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
189 [SDNPHasChain, SDNPOutGlue]>;
191 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
192 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
194 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
195 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
198 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
199 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
200 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
201 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
204 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
205 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
207 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
208 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
210 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
211 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
213 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
214 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
216 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
219 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
220 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
222 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
224 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
225 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
227 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
229 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
230 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
232 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
233 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
234 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
236 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
238 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
240 def X86andn_flag : SDNode<"X86ISD::ANDN", SDTBinaryArithWithFlags>;
242 def X86blsi_flag : SDNode<"X86ISD::BLSI", SDTUnaryArithWithFlags>;
243 def X86blsmsk_flag : SDNode<"X86ISD::BLSMSK", SDTUnaryArithWithFlags>;
244 def X86blsr_flag : SDNode<"X86ISD::BLSR", SDTUnaryArithWithFlags>;
246 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
248 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
249 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
251 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
254 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
255 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
257 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL,
258 [SDNPHasChain, SDNPOutGlue]>;
260 //===----------------------------------------------------------------------===//
261 // X86 Operand Definitions.
264 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
265 // the index operand of an address, to conform to x86 encoding restrictions.
266 def ptr_rc_nosp : PointerLikeRegClass<1>;
268 // *mem - Operand definitions for the funky X86 addressing mode operands.
270 def X86MemAsmOperand : AsmOperandClass {
271 let Name = "Mem"; let PredicateMethod = "isMem";
273 def X86Mem8AsmOperand : AsmOperandClass {
274 let Name = "Mem8"; let PredicateMethod = "isMem8";
276 def X86Mem16AsmOperand : AsmOperandClass {
277 let Name = "Mem16"; let PredicateMethod = "isMem16";
279 def X86Mem32AsmOperand : AsmOperandClass {
280 let Name = "Mem32"; let PredicateMethod = "isMem32";
282 def X86Mem64AsmOperand : AsmOperandClass {
283 let Name = "Mem64"; let PredicateMethod = "isMem64";
285 def X86Mem80AsmOperand : AsmOperandClass {
286 let Name = "Mem80"; let PredicateMethod = "isMem80";
288 def X86Mem128AsmOperand : AsmOperandClass {
289 let Name = "Mem128"; let PredicateMethod = "isMem128";
291 def X86Mem256AsmOperand : AsmOperandClass {
292 let Name = "Mem256"; let PredicateMethod = "isMem256";
295 // Gather mem operands
296 def X86MemVX32Operand : AsmOperandClass {
297 let Name = "MemVX32"; let PredicateMethod = "isMemVX32";
299 def X86MemVY32Operand : AsmOperandClass {
300 let Name = "MemVY32"; let PredicateMethod = "isMemVY32";
302 def X86MemVX64Operand : AsmOperandClass {
303 let Name = "MemVX64"; let PredicateMethod = "isMemVX64";
305 def X86MemVY64Operand : AsmOperandClass {
306 let Name = "MemVY64"; let PredicateMethod = "isMemVY64";
309 def X86AbsMemAsmOperand : AsmOperandClass {
311 let SuperClasses = [X86MemAsmOperand];
313 class X86MemOperand<string printMethod> : Operand<iPTR> {
314 let PrintMethod = printMethod;
315 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
316 let ParserMatchClass = X86MemAsmOperand;
319 let OperandType = "OPERAND_MEMORY" in {
320 def opaque32mem : X86MemOperand<"printopaquemem">;
321 def opaque48mem : X86MemOperand<"printopaquemem">;
322 def opaque80mem : X86MemOperand<"printopaquemem">;
323 def opaque512mem : X86MemOperand<"printopaquemem">;
325 def i8mem : X86MemOperand<"printi8mem"> {
326 let ParserMatchClass = X86Mem8AsmOperand; }
327 def i16mem : X86MemOperand<"printi16mem"> {
328 let ParserMatchClass = X86Mem16AsmOperand; }
329 def i32mem : X86MemOperand<"printi32mem"> {
330 let ParserMatchClass = X86Mem32AsmOperand; }
331 def i64mem : X86MemOperand<"printi64mem"> {
332 let ParserMatchClass = X86Mem64AsmOperand; }
333 def i128mem : X86MemOperand<"printi128mem"> {
334 let ParserMatchClass = X86Mem128AsmOperand; }
335 def i256mem : X86MemOperand<"printi256mem"> {
336 let ParserMatchClass = X86Mem256AsmOperand; }
337 def f32mem : X86MemOperand<"printf32mem"> {
338 let ParserMatchClass = X86Mem32AsmOperand; }
339 def f64mem : X86MemOperand<"printf64mem"> {
340 let ParserMatchClass = X86Mem64AsmOperand; }
341 def f80mem : X86MemOperand<"printf80mem"> {
342 let ParserMatchClass = X86Mem80AsmOperand; }
343 def f128mem : X86MemOperand<"printf128mem"> {
344 let ParserMatchClass = X86Mem128AsmOperand; }
345 def f256mem : X86MemOperand<"printf256mem">{
346 let ParserMatchClass = X86Mem256AsmOperand; }
348 // Gather mem operands
349 def vx32mem : X86MemOperand<"printi32mem">{
350 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
351 let ParserMatchClass = X86MemVX32Operand; }
352 def vy32mem : X86MemOperand<"printi32mem">{
353 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
354 let ParserMatchClass = X86MemVY32Operand; }
355 def vx64mem : X86MemOperand<"printi64mem">{
356 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
357 let ParserMatchClass = X86MemVX64Operand; }
358 def vy64mem : X86MemOperand<"printi64mem">{
359 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
360 let ParserMatchClass = X86MemVY64Operand; }
363 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
364 // plain GR64, so that it doesn't potentially require a REX prefix.
365 def i8mem_NOREX : Operand<i64> {
366 let PrintMethod = "printi8mem";
367 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
368 let ParserMatchClass = X86Mem8AsmOperand;
369 let OperandType = "OPERAND_MEMORY";
372 // GPRs available for tailcall.
373 // It represents GR32_TC, GR64_TC or GR64_TCW64.
374 def ptr_rc_tailcall : PointerLikeRegClass<2>;
376 // Special i32mem for addresses of load folding tail calls. These are not
377 // allowed to use callee-saved registers since they must be scheduled
378 // after callee-saved register are popped.
379 def i32mem_TC : Operand<i32> {
380 let PrintMethod = "printi32mem";
381 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
383 let ParserMatchClass = X86Mem32AsmOperand;
384 let OperandType = "OPERAND_MEMORY";
387 // Special i64mem for addresses of load folding tail calls. These are not
388 // allowed to use callee-saved registers since they must be scheduled
389 // after callee-saved register are popped.
390 def i64mem_TC : Operand<i64> {
391 let PrintMethod = "printi64mem";
392 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
393 ptr_rc_tailcall, i32imm, i8imm);
394 let ParserMatchClass = X86Mem64AsmOperand;
395 let OperandType = "OPERAND_MEMORY";
398 let OperandType = "OPERAND_PCREL",
399 ParserMatchClass = X86AbsMemAsmOperand,
400 PrintMethod = "print_pcrel_imm" in {
401 def i32imm_pcrel : Operand<i32>;
402 def i16imm_pcrel : Operand<i16>;
404 def offset8 : Operand<i64>;
405 def offset16 : Operand<i64>;
406 def offset32 : Operand<i64>;
407 def offset64 : Operand<i64>;
409 // Branch targets have OtherVT type and print as pc-relative values.
410 def brtarget : Operand<OtherVT>;
411 def brtarget8 : Operand<OtherVT>;
415 def SSECC : Operand<i8> {
416 let PrintMethod = "printSSECC";
417 let OperandType = "OPERAND_IMMEDIATE";
420 def AVXCC : Operand<i8> {
421 let PrintMethod = "printSSECC";
422 let OperandType = "OPERAND_IMMEDIATE";
425 class ImmSExtAsmOperandClass : AsmOperandClass {
426 let SuperClasses = [ImmAsmOperand];
427 let RenderMethod = "addImmOperands";
430 class ImmZExtAsmOperandClass : AsmOperandClass {
431 let SuperClasses = [ImmAsmOperand];
432 let RenderMethod = "addImmOperands";
435 // Sign-extended immediate classes. We don't need to define the full lattice
436 // here because there is no instruction with an ambiguity between ImmSExti64i32
439 // The strange ranges come from the fact that the assembler always works with
440 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
441 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
444 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
445 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
446 let Name = "ImmSExti64i32";
449 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
450 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
451 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
452 let Name = "ImmSExti16i8";
453 let SuperClasses = [ImmSExti64i32AsmOperand];
456 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
457 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
458 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
459 let Name = "ImmSExti32i8";
463 def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass {
464 let Name = "ImmZExtu32u8";
469 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
470 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
471 let Name = "ImmSExti64i8";
472 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
473 ImmSExti64i32AsmOperand];
476 // A couple of more descriptive operand definitions.
477 // 16-bits but only 8 bits are significant.
478 def i16i8imm : Operand<i16> {
479 let ParserMatchClass = ImmSExti16i8AsmOperand;
480 let OperandType = "OPERAND_IMMEDIATE";
482 // 32-bits but only 8 bits are significant.
483 def i32i8imm : Operand<i32> {
484 let ParserMatchClass = ImmSExti32i8AsmOperand;
485 let OperandType = "OPERAND_IMMEDIATE";
487 // 32-bits but only 8 bits are significant, and those 8 bits are unsigned.
488 def u32u8imm : Operand<i32> {
489 let ParserMatchClass = ImmZExtu32u8AsmOperand;
490 let OperandType = "OPERAND_IMMEDIATE";
493 // 64-bits but only 32 bits are significant.
494 def i64i32imm : Operand<i64> {
495 let ParserMatchClass = ImmSExti64i32AsmOperand;
496 let OperandType = "OPERAND_IMMEDIATE";
499 // 64-bits but only 32 bits are significant, and those bits are treated as being
501 def i64i32imm_pcrel : Operand<i64> {
502 let PrintMethod = "print_pcrel_imm";
503 let ParserMatchClass = X86AbsMemAsmOperand;
504 let OperandType = "OPERAND_PCREL";
507 // 64-bits but only 8 bits are significant.
508 def i64i8imm : Operand<i64> {
509 let ParserMatchClass = ImmSExti64i8AsmOperand;
510 let OperandType = "OPERAND_IMMEDIATE";
513 def lea64_32mem : Operand<i32> {
514 let PrintMethod = "printi32mem";
515 let AsmOperandLowerMethod = "lower_lea64_32mem";
516 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm);
517 let ParserMatchClass = X86MemAsmOperand;
521 //===----------------------------------------------------------------------===//
522 // X86 Complex Pattern Definitions.
525 // Define X86 specific addressing mode.
526 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
527 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
528 [add, sub, mul, X86mul_imm, shl, or, frameindex],
530 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
531 [tglobaltlsaddr], []>;
533 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
534 [tglobaltlsaddr], []>;
536 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
537 [add, sub, mul, X86mul_imm, shl, or, frameindex,
540 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
541 [tglobaltlsaddr], []>;
543 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
544 [tglobaltlsaddr], []>;
546 //===----------------------------------------------------------------------===//
547 // X86 Instruction Predicate Definitions.
548 def HasCMov : Predicate<"Subtarget->hasCMov()">;
549 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
551 def HasMMX : Predicate<"Subtarget->hasMMX()">;
552 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
553 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
554 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
555 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
556 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
557 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
558 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
559 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
560 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
561 def HasAVX : Predicate<"Subtarget->hasAVX()">;
562 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
564 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
565 def HasAES : Predicate<"Subtarget->hasAES()">;
566 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
567 def HasFMA : Predicate<"Subtarget->hasFMA()">;
568 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
569 def HasXOP : Predicate<"Subtarget->hasXOP()">;
570 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
571 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
572 def HasF16C : Predicate<"Subtarget->hasF16C()">;
573 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
574 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
575 def HasBMI : Predicate<"Subtarget->hasBMI()">;
576 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
577 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
578 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
579 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
580 def In32BitMode : Predicate<"!Subtarget->is64Bit()">,
581 AssemblerPredicate<"!Mode64Bit">;
582 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
583 AssemblerPredicate<"Mode64Bit">;
584 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
585 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
586 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
587 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
588 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
589 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
590 "TM.getCodeModel() != CodeModel::Kernel">;
591 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
592 "TM.getCodeModel() == CodeModel::Kernel">;
593 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
594 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
595 def OptForSize : Predicate<"OptForSize">;
596 def OptForSpeed : Predicate<"!OptForSize">;
597 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
598 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
600 //===----------------------------------------------------------------------===//
601 // X86 Instruction Format Definitions.
604 include "X86InstrFormats.td"
606 //===----------------------------------------------------------------------===//
607 // Pattern fragments.
610 // X86 specific condition code. These correspond to CondCode in
611 // X86InstrInfo.h. They must be kept in synch.
612 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
613 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
614 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
615 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
616 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
617 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
618 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
619 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
620 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
621 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
622 def X86_COND_NO : PatLeaf<(i8 10)>;
623 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
624 def X86_COND_NS : PatLeaf<(i8 12)>;
625 def X86_COND_O : PatLeaf<(i8 13)>;
626 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
627 def X86_COND_S : PatLeaf<(i8 15)>;
629 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
630 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
631 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
632 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
635 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
638 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
640 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
642 def i64immZExt32SExt8 : ImmLeaf<i64, [{
643 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
646 // Helper fragments for loads.
647 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
648 // known to be 32-bit aligned or better. Ditto for i8 to i16.
649 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
650 LoadSDNode *LD = cast<LoadSDNode>(N);
651 ISD::LoadExtType ExtType = LD->getExtensionType();
652 if (ExtType == ISD::NON_EXTLOAD)
654 if (ExtType == ISD::EXTLOAD)
655 return LD->getAlignment() >= 2 && !LD->isVolatile();
659 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
660 LoadSDNode *LD = cast<LoadSDNode>(N);
661 ISD::LoadExtType ExtType = LD->getExtensionType();
662 if (ExtType == ISD::EXTLOAD)
663 return LD->getAlignment() >= 2 && !LD->isVolatile();
667 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
668 LoadSDNode *LD = cast<LoadSDNode>(N);
669 ISD::LoadExtType ExtType = LD->getExtensionType();
670 if (ExtType == ISD::NON_EXTLOAD)
672 if (ExtType == ISD::EXTLOAD)
673 return LD->getAlignment() >= 4 && !LD->isVolatile();
677 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
678 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
679 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
680 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
681 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
683 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
684 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
685 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
686 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
687 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
688 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
690 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
691 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
692 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
693 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
694 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
695 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
696 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
697 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
698 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
699 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
701 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
702 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
703 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
704 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
705 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
706 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
707 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
708 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
709 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
710 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
713 // An 'and' node with a single use.
714 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
715 return N->hasOneUse();
717 // An 'srl' node with a single use.
718 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
719 return N->hasOneUse();
721 // An 'trunc' node with a single use.
722 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
723 return N->hasOneUse();
726 //===----------------------------------------------------------------------===//
731 let neverHasSideEffects = 1 in {
732 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
733 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
734 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize;
735 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
736 "nop{l}\t$zero", [], IIC_NOP>, TB;
740 // Constructing a stack frame.
741 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
742 "enter\t$len, $lvl", [], IIC_ENTER>;
744 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
745 def LEAVE : I<0xC9, RawFrm,
746 (outs), (ins), "leave", [], IIC_LEAVE>,
747 Requires<[In32BitMode]>;
749 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
750 def LEAVE64 : I<0xC9, RawFrm,
751 (outs), (ins), "leave", [], IIC_LEAVE>,
752 Requires<[In64BitMode]>;
754 //===----------------------------------------------------------------------===//
755 // Miscellaneous Instructions.
758 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
760 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
761 IIC_POP_REG16>, OpSize;
762 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
764 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
765 IIC_POP_REG>, OpSize;
766 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", [],
767 IIC_POP_MEM>, OpSize;
768 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
770 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", [],
773 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, OpSize;
774 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
775 Requires<[In32BitMode]>;
778 let mayStore = 1 in {
779 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
780 IIC_PUSH_REG>, OpSize;
781 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
783 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
784 IIC_PUSH_REG>, OpSize;
785 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
788 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
790 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
793 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
794 "push{l}\t$imm", [], IIC_PUSH_IMM>;
795 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
796 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize;
797 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
798 "push{l}\t$imm", [], IIC_PUSH_IMM>;
800 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
802 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
803 Requires<[In32BitMode]>;
808 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
810 def POP64r : I<0x58, AddRegFrm,
811 (outs GR64:$reg), (ins), "pop{q}\t$reg", [], IIC_POP_REG>;
812 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
814 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", [],
817 let mayStore = 1 in {
818 def PUSH64r : I<0x50, AddRegFrm,
819 (outs), (ins GR64:$reg), "push{q}\t$reg", [], IIC_PUSH_REG>;
820 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
822 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
827 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
828 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
829 "push{q}\t$imm", [], IIC_PUSH_IMM>;
830 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
831 "push{q}\t$imm", [], IIC_PUSH_IMM>;
832 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
833 "push{q}\t$imm", [], IIC_PUSH_IMM>;
836 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
837 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
838 Requires<[In64BitMode]>;
839 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
840 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
841 Requires<[In64BitMode]>;
845 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
846 mayLoad=1, neverHasSideEffects=1 in {
847 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", [], IIC_POP_A>,
848 Requires<[In32BitMode]>;
850 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
851 mayStore=1, neverHasSideEffects=1 in {
852 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", [], IIC_PUSH_A>,
853 Requires<[In32BitMode]>;
856 let Constraints = "$src = $dst" in { // GR32 = bswap GR32
857 def BSWAP32r : I<0xC8, AddRegFrm,
858 (outs GR32:$dst), (ins GR32:$src),
860 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, TB;
862 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
864 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
865 } // Constraints = "$src = $dst"
867 // Bit scan instructions.
868 let Defs = [EFLAGS] in {
869 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
870 "bsf{w}\t{$src, $dst|$dst, $src}",
871 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
872 IIC_BSF>, TB, OpSize;
873 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
874 "bsf{w}\t{$src, $dst|$dst, $src}",
875 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
876 IIC_BSF>, TB, OpSize;
877 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
878 "bsf{l}\t{$src, $dst|$dst, $src}",
879 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))], IIC_BSF>, TB;
880 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
881 "bsf{l}\t{$src, $dst|$dst, $src}",
882 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
884 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
885 "bsf{q}\t{$src, $dst|$dst, $src}",
886 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
888 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
889 "bsf{q}\t{$src, $dst|$dst, $src}",
890 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
893 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
894 "bsr{w}\t{$src, $dst|$dst, $src}",
895 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))], IIC_BSR>,
897 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
898 "bsr{w}\t{$src, $dst|$dst, $src}",
899 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
902 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
903 "bsr{l}\t{$src, $dst|$dst, $src}",
904 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))], IIC_BSR>, TB;
905 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
906 "bsr{l}\t{$src, $dst|$dst, $src}",
907 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
909 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
910 "bsr{q}\t{$src, $dst|$dst, $src}",
911 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], IIC_BSR>, TB;
912 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
913 "bsr{q}\t{$src, $dst|$dst, $src}",
914 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
919 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
920 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
921 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", [], IIC_MOVS>;
922 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", [], IIC_MOVS>, OpSize;
923 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", [], IIC_MOVS>;
924 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", [], IIC_MOVS>;
927 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
928 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
929 def STOSB : I<0xAA, RawFrm, (outs), (ins), "stosb", [], IIC_STOS>;
930 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
931 def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", [], IIC_STOS>, OpSize;
932 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
933 def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", [], IIC_STOS>;
934 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
935 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", [], IIC_STOS>;
937 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", [], IIC_SCAS>;
938 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", [], IIC_SCAS>, OpSize;
939 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", [], IIC_SCAS>;
940 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", [], IIC_SCAS>;
942 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", [], IIC_CMPS>;
943 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", [], IIC_CMPS>, OpSize;
944 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", [], IIC_CMPS>;
945 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", [], IIC_CMPS>;
948 //===----------------------------------------------------------------------===//
949 // Move Instructions.
952 let neverHasSideEffects = 1 in {
953 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
954 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
955 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
956 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
957 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
958 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
959 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
960 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
962 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
963 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
964 "mov{b}\t{$src, $dst|$dst, $src}",
965 [(set GR8:$dst, imm:$src)], IIC_MOV>;
966 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
967 "mov{w}\t{$src, $dst|$dst, $src}",
968 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize;
969 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
970 "mov{l}\t{$src, $dst|$dst, $src}",
971 [(set GR32:$dst, imm:$src)], IIC_MOV>;
972 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
973 "movabs{q}\t{$src, $dst|$dst, $src}",
974 [(set GR64:$dst, imm:$src)], IIC_MOV>;
975 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
976 "mov{q}\t{$src, $dst|$dst, $src}",
977 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
980 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
981 "mov{b}\t{$src, $dst|$dst, $src}",
982 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
983 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
984 "mov{w}\t{$src, $dst|$dst, $src}",
985 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize;
986 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
987 "mov{l}\t{$src, $dst|$dst, $src}",
988 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>;
989 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
990 "mov{q}\t{$src, $dst|$dst, $src}",
991 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
993 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
994 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
995 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
996 "mov{b}\t{$src, %al|AL, $src}", [], IIC_MOV_MEM>,
997 Requires<[In32BitMode]>;
998 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
999 "mov{w}\t{$src, %ax|AL, $src}", [], IIC_MOV_MEM>, OpSize,
1000 Requires<[In32BitMode]>;
1001 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1002 "mov{l}\t{$src, %eax|EAX, $src}", [], IIC_MOV_MEM>,
1003 Requires<[In32BitMode]>;
1004 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1005 "mov{b}\t{%al, $dst|$dst, AL}", [], IIC_MOV_MEM>,
1006 Requires<[In32BitMode]>;
1007 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1008 "mov{w}\t{%ax, $dst|$dst, AL}", [], IIC_MOV_MEM>, OpSize,
1009 Requires<[In32BitMode]>;
1010 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1011 "mov{l}\t{%eax, $dst|$dst, EAX}", [], IIC_MOV_MEM>,
1012 Requires<[In32BitMode]>;
1014 // FIXME: These definitions are utterly broken
1015 // Just leave them commented out for now because they're useless outside
1016 // of the large code model, and most compilers won't generate the instructions
1019 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
1020 "mov{q}\t{$src, %rax|RAX, $src}", []>;
1021 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
1022 "mov{q}\t{$src, %rax|RAX, $src}", []>;
1023 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
1024 "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
1025 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
1026 "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
1030 let isCodeGenOnly = 1 in {
1031 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1032 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1033 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1034 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
1035 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1036 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1037 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1038 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1041 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1042 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1043 "mov{b}\t{$src, $dst|$dst, $src}",
1044 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1045 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1046 "mov{w}\t{$src, $dst|$dst, $src}",
1047 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize;
1048 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1049 "mov{l}\t{$src, $dst|$dst, $src}",
1050 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>;
1051 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1052 "mov{q}\t{$src, $dst|$dst, $src}",
1053 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1056 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1057 "mov{b}\t{$src, $dst|$dst, $src}",
1058 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1059 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1060 "mov{w}\t{$src, $dst|$dst, $src}",
1061 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize;
1062 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1063 "mov{l}\t{$src, $dst|$dst, $src}",
1064 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>;
1065 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1066 "mov{q}\t{$src, $dst|$dst, $src}",
1067 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1069 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1070 // that they can be used for copying and storing h registers, which can't be
1071 // encoded when a REX prefix is present.
1072 let isCodeGenOnly = 1 in {
1073 let neverHasSideEffects = 1 in
1074 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1075 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1076 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>;
1078 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1079 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1080 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1082 let mayLoad = 1, neverHasSideEffects = 1,
1083 canFoldAsLoad = 1, isReMaterializable = 1 in
1084 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1085 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1086 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1091 // Condition code ops, incl. set if equal/not equal/...
1092 let Defs = [EFLAGS], Uses = [AH] in
1093 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1094 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
1095 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
1096 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1097 IIC_AHF>; // AH = flags
1100 //===----------------------------------------------------------------------===//
1101 // Bit tests instructions: BT, BTS, BTR, BTC.
1103 let Defs = [EFLAGS] in {
1104 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1105 "bt{w}\t{$src2, $src1|$src1, $src2}",
1106 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1108 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1109 "bt{l}\t{$src2, $src1|$src1, $src2}",
1110 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>, TB;
1111 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1112 "bt{q}\t{$src2, $src1|$src1, $src2}",
1113 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1115 // Unlike with the register+register form, the memory+register form of the
1116 // bt instruction does not ignore the high bits of the index. From ISel's
1117 // perspective, this is pretty bizarre. Make these instructions disassembly
1120 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1121 "bt{w}\t{$src2, $src1|$src1, $src2}",
1122 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1123 // (implicit EFLAGS)]
1125 >, OpSize, TB, Requires<[FastBTMem]>;
1126 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1127 "bt{l}\t{$src2, $src1|$src1, $src2}",
1128 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1129 // (implicit EFLAGS)]
1131 >, TB, Requires<[FastBTMem]>;
1132 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1133 "bt{q}\t{$src2, $src1|$src1, $src2}",
1134 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1135 // (implicit EFLAGS)]
1139 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1140 "bt{w}\t{$src2, $src1|$src1, $src2}",
1141 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1142 IIC_BT_RI>, OpSize, TB;
1143 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1144 "bt{l}\t{$src2, $src1|$src1, $src2}",
1145 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1147 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1148 "bt{q}\t{$src2, $src1|$src1, $src2}",
1149 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1152 // Note that these instructions don't need FastBTMem because that
1153 // only applies when the other operand is in a register. When it's
1154 // an immediate, bt is still fast.
1155 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1156 "bt{w}\t{$src2, $src1|$src1, $src2}",
1157 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1158 ], IIC_BT_MI>, OpSize, TB;
1159 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1160 "bt{l}\t{$src2, $src1|$src1, $src2}",
1161 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1163 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1164 "bt{q}\t{$src2, $src1|$src1, $src2}",
1165 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1166 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1169 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1170 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1172 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1173 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1174 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1175 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1176 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1177 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1179 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1180 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1181 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1182 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1183 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1184 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1186 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1187 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1188 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1189 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1190 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1191 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1193 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1194 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1195 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1196 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1198 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1199 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1201 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1202 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1203 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1204 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1205 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1206 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1208 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1209 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1210 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1211 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1212 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1213 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1215 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1216 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1217 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1218 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1219 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1220 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1222 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1223 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1224 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1225 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1227 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1228 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1230 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1231 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1232 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1233 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1234 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1235 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1237 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1238 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1239 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1240 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1241 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1242 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1244 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1245 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1246 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1247 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1248 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1249 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1251 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1252 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1253 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1254 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1255 } // Defs = [EFLAGS]
1258 //===----------------------------------------------------------------------===//
1263 // Atomic swap. These are just normal xchg instructions. But since a memory
1264 // operand is referenced, the atomicity is ensured.
1265 let Constraints = "$val = $dst" in {
1266 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
1267 "xchg{b}\t{$val, $ptr|$ptr, $val}",
1268 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))],
1270 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),(ins GR16:$val, i16mem:$ptr),
1271 "xchg{w}\t{$val, $ptr|$ptr, $val}",
1272 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))],
1275 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),(ins GR32:$val, i32mem:$ptr),
1276 "xchg{l}\t{$val, $ptr|$ptr, $val}",
1277 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))],
1279 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),(ins GR64:$val,i64mem:$ptr),
1280 "xchg{q}\t{$val, $ptr|$ptr, $val}",
1281 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))],
1284 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1285 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1286 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1287 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, OpSize;
1288 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1289 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1290 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1291 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1294 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1295 "xchg{w}\t{$src, %ax|AX, $src}", [], IIC_XCHG_REG>, OpSize;
1296 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1297 "xchg{l}\t{$src, %eax|EAX, $src}", [], IIC_XCHG_REG>,
1298 Requires<[In32BitMode]>;
1299 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1300 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1301 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1302 "xchg{l}\t{$src, %eax|EAX, $src}", [], IIC_XCHG_REG>,
1303 Requires<[In64BitMode]>;
1304 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1305 "xchg{q}\t{$src, %rax|RAX, $src}", [], IIC_XCHG_REG>;
1309 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1310 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1311 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1312 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1314 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1315 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1316 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1317 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1319 let mayLoad = 1, mayStore = 1 in {
1320 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1321 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1322 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1323 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1325 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1326 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1327 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1328 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1332 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1333 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1334 IIC_CMPXCHG_REG8>, TB;
1335 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1336 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1337 IIC_CMPXCHG_REG>, TB, OpSize;
1338 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1339 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1340 IIC_CMPXCHG_REG>, TB;
1341 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1342 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1343 IIC_CMPXCHG_REG>, TB;
1345 let mayLoad = 1, mayStore = 1 in {
1346 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1347 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1348 IIC_CMPXCHG_MEM8>, TB;
1349 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1350 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1351 IIC_CMPXCHG_MEM>, TB, OpSize;
1352 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1353 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1354 IIC_CMPXCHG_MEM>, TB;
1355 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1356 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1357 IIC_CMPXCHG_MEM>, TB;
1360 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1361 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1362 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1364 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1365 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1366 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1367 TB, Requires<[HasCmpxchg16b]>;
1371 // Lock instruction prefix
1372 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1374 // Rex64 instruction prefix
1375 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>;
1377 // Data16 instruction prefix
1378 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1380 // Repeat string operation instruction prefixes
1381 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1382 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1383 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1384 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1385 // Repeat while not equal (used with CMPS and SCAS)
1386 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1390 // String manipulation instructions
1391 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", [], IIC_LODS>;
1392 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", [], IIC_LODS>, OpSize;
1393 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", [], IIC_LODS>;
1394 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", [], IIC_LODS>;
1396 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", [], IIC_OUTS>;
1397 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", [], IIC_OUTS>, OpSize;
1398 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", [], IIC_OUTS>;
1401 // Flag instructions
1402 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1403 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1404 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1405 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1406 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1407 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1408 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1410 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1412 // Table lookup instructions
1413 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>;
1415 // ASCII Adjust After Addition
1416 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1417 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1418 Requires<[In32BitMode]>;
1420 // ASCII Adjust AX Before Division
1421 // sets AL, AH and EFLAGS and uses AL and AH
1422 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1423 "aad\t$src", [], IIC_AAD>, Requires<[In32BitMode]>;
1425 // ASCII Adjust AX After Multiply
1426 // sets AL, AH and EFLAGS and uses AL
1427 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1428 "aam\t$src", [], IIC_AAM>, Requires<[In32BitMode]>;
1430 // ASCII Adjust AL After Subtraction - sets
1431 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1432 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1433 Requires<[In32BitMode]>;
1435 // Decimal Adjust AL after Addition
1436 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1437 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1438 Requires<[In32BitMode]>;
1440 // Decimal Adjust AL after Subtraction
1441 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1442 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1443 Requires<[In32BitMode]>;
1445 // Check Array Index Against Bounds
1446 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1447 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize,
1448 Requires<[In32BitMode]>;
1449 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1450 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>,
1451 Requires<[In32BitMode]>;
1453 // Adjust RPL Field of Segment Selector
1454 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$src), (ins GR16:$dst),
1455 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1456 Requires<[In32BitMode]>;
1457 def ARPL16mr : I<0x63, MRMSrcMem, (outs GR16:$src), (ins i16mem:$dst),
1458 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1459 Requires<[In32BitMode]>;
1461 //===----------------------------------------------------------------------===//
1462 // MOVBE Instructions
1464 let Predicates = [HasMOVBE] in {
1465 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1466 "movbe{w}\t{$src, $dst|$dst, $src}",
1467 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1469 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1470 "movbe{l}\t{$src, $dst|$dst, $src}",
1471 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1473 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1474 "movbe{q}\t{$src, $dst|$dst, $src}",
1475 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
1477 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1478 "movbe{w}\t{$src, $dst|$dst, $src}",
1479 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1481 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1482 "movbe{l}\t{$src, $dst|$dst, $src}",
1483 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1485 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1486 "movbe{q}\t{$src, $dst|$dst, $src}",
1487 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
1491 //===----------------------------------------------------------------------===//
1492 // RDRAND Instruction
1494 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1495 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1497 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize, TB;
1498 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1500 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, TB;
1501 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1503 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
1506 //===----------------------------------------------------------------------===//
1507 // LZCNT Instruction
1509 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
1510 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1511 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1512 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
1514 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1515 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1516 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
1517 (implicit EFLAGS)]>, XS, OpSize;
1519 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1520 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1521 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS;
1522 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1523 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1524 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
1525 (implicit EFLAGS)]>, XS;
1527 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1528 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1529 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
1531 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1532 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1533 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
1534 (implicit EFLAGS)]>, XS;
1537 //===----------------------------------------------------------------------===//
1540 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1541 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1542 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1543 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
1545 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1546 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1547 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
1548 (implicit EFLAGS)]>, XS, OpSize;
1550 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1551 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1552 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS;
1553 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1554 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1555 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
1556 (implicit EFLAGS)]>, XS;
1558 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1559 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1560 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
1562 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1563 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1564 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
1565 (implicit EFLAGS)]>, XS;
1568 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
1569 RegisterClass RC, X86MemOperand x86memop, SDNode OpNode,
1571 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
1572 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1573 [(set RC:$dst, EFLAGS, (OpNode RC:$src))]>, T8, VEX_4V;
1574 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
1575 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1576 [(set RC:$dst, EFLAGS, (OpNode (ld_frag addr:$src)))]>,
1580 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1581 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem,
1582 X86blsr_flag, loadi32>;
1583 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem,
1584 X86blsr_flag, loadi64>, VEX_W;
1585 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem,
1586 X86blsmsk_flag, loadi32>;
1587 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem,
1588 X86blsmsk_flag, loadi64>, VEX_W;
1589 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem,
1590 X86blsi_flag, loadi32>;
1591 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem,
1592 X86blsi_flag, loadi64>, VEX_W;
1595 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
1596 X86MemOperand x86memop, Intrinsic Int,
1598 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1599 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1600 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
1602 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
1603 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1604 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
1605 (implicit EFLAGS)]>, T8, VEX_4VOp3;
1608 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1609 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
1610 int_x86_bmi_bextr_32, loadi32>;
1611 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
1612 int_x86_bmi_bextr_64, loadi64>, VEX_W;
1615 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
1616 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
1617 int_x86_bmi_bzhi_32, loadi32>;
1618 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
1619 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
1622 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
1623 X86MemOperand x86memop, Intrinsic Int,
1625 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1626 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1627 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
1629 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1630 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1631 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
1634 let Predicates = [HasBMI2] in {
1635 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
1636 int_x86_bmi_pdep_32, loadi32>, T8XD;
1637 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
1638 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
1639 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
1640 int_x86_bmi_pext_32, loadi32>, T8XS;
1641 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
1642 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
1645 //===----------------------------------------------------------------------===//
1647 //===----------------------------------------------------------------------===//
1649 include "X86InstrArithmetic.td"
1650 include "X86InstrCMovSetCC.td"
1651 include "X86InstrExtension.td"
1652 include "X86InstrControl.td"
1653 include "X86InstrShiftRotate.td"
1655 // X87 Floating Point Stack.
1656 include "X86InstrFPStack.td"
1658 // SIMD support (SSE, MMX and AVX)
1659 include "X86InstrFragmentsSIMD.td"
1661 // FMA - Fused Multiply-Add support (requires FMA)
1662 include "X86InstrFMA.td"
1665 include "X86InstrXOP.td"
1667 // SSE, MMX and 3DNow! vector support.
1668 include "X86InstrSSE.td"
1669 include "X86InstrMMX.td"
1670 include "X86Instr3DNow.td"
1672 include "X86InstrVMX.td"
1673 include "X86InstrSVM.td"
1675 // System instructions.
1676 include "X86InstrSystem.td"
1678 // Compiler Pseudo Instructions and Pat Patterns
1679 include "X86InstrCompiler.td"
1681 //===----------------------------------------------------------------------===//
1682 // Assembler Mnemonic Aliases
1683 //===----------------------------------------------------------------------===//
1685 def : MnemonicAlias<"call", "calll">, Requires<[In32BitMode]>;
1686 def : MnemonicAlias<"call", "callq">, Requires<[In64BitMode]>;
1688 def : MnemonicAlias<"cbw", "cbtw">;
1689 def : MnemonicAlias<"cwde", "cwtl">;
1690 def : MnemonicAlias<"cwd", "cwtd">;
1691 def : MnemonicAlias<"cdq", "cltd">;
1692 def : MnemonicAlias<"cdqe", "cltq">;
1693 def : MnemonicAlias<"cqo", "cqto">;
1695 // lret maps to lretl, it is not ambiguous with lretq.
1696 def : MnemonicAlias<"lret", "lretl">;
1698 def : MnemonicAlias<"leavel", "leave">, Requires<[In32BitMode]>;
1699 def : MnemonicAlias<"leaveq", "leave">, Requires<[In64BitMode]>;
1701 def : MnemonicAlias<"loopz", "loope">;
1702 def : MnemonicAlias<"loopnz", "loopne">;
1704 def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
1705 def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
1706 def : MnemonicAlias<"popf", "popfl">, Requires<[In32BitMode]>;
1707 def : MnemonicAlias<"popf", "popfq">, Requires<[In64BitMode]>;
1708 def : MnemonicAlias<"popfd", "popfl">;
1710 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
1711 // all modes. However: "push (addr)" and "push $42" should default to
1712 // pushl/pushq depending on the current mode. Similar for "pop %bx"
1713 def : MnemonicAlias<"push", "pushl">, Requires<[In32BitMode]>;
1714 def : MnemonicAlias<"push", "pushq">, Requires<[In64BitMode]>;
1715 def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
1716 def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1717 def : MnemonicAlias<"pushfd", "pushfl">;
1719 def : MnemonicAlias<"repe", "rep">;
1720 def : MnemonicAlias<"repz", "rep">;
1721 def : MnemonicAlias<"repnz", "repne">;
1723 def : MnemonicAlias<"retl", "ret">, Requires<[In32BitMode]>;
1724 def : MnemonicAlias<"retq", "ret">, Requires<[In64BitMode]>;
1726 def : MnemonicAlias<"salb", "shlb">;
1727 def : MnemonicAlias<"salw", "shlw">;
1728 def : MnemonicAlias<"sall", "shll">;
1729 def : MnemonicAlias<"salq", "shlq">;
1731 def : MnemonicAlias<"smovb", "movsb">;
1732 def : MnemonicAlias<"smovw", "movsw">;
1733 def : MnemonicAlias<"smovl", "movsl">;
1734 def : MnemonicAlias<"smovq", "movsq">;
1736 def : MnemonicAlias<"ud2a", "ud2">;
1737 def : MnemonicAlias<"verrw", "verr">;
1739 // System instruction aliases.
1740 def : MnemonicAlias<"iret", "iretl">;
1741 def : MnemonicAlias<"sysret", "sysretl">;
1742 def : MnemonicAlias<"sysexit", "sysexitl">;
1744 def : MnemonicAlias<"lgdtl", "lgdt">, Requires<[In32BitMode]>;
1745 def : MnemonicAlias<"lgdtq", "lgdt">, Requires<[In64BitMode]>;
1746 def : MnemonicAlias<"lidtl", "lidt">, Requires<[In32BitMode]>;
1747 def : MnemonicAlias<"lidtq", "lidt">, Requires<[In64BitMode]>;
1748 def : MnemonicAlias<"sgdtl", "sgdt">, Requires<[In32BitMode]>;
1749 def : MnemonicAlias<"sgdtq", "sgdt">, Requires<[In64BitMode]>;
1750 def : MnemonicAlias<"sidtl", "sidt">, Requires<[In32BitMode]>;
1751 def : MnemonicAlias<"sidtq", "sidt">, Requires<[In64BitMode]>;
1754 // Floating point stack aliases.
1755 def : MnemonicAlias<"fcmovz", "fcmove">;
1756 def : MnemonicAlias<"fcmova", "fcmovnbe">;
1757 def : MnemonicAlias<"fcmovnae", "fcmovb">;
1758 def : MnemonicAlias<"fcmovna", "fcmovbe">;
1759 def : MnemonicAlias<"fcmovae", "fcmovnb">;
1760 def : MnemonicAlias<"fcomip", "fcompi">;
1761 def : MnemonicAlias<"fildq", "fildll">;
1762 def : MnemonicAlias<"fistpq", "fistpll">;
1763 def : MnemonicAlias<"fisttpq", "fisttpll">;
1764 def : MnemonicAlias<"fldcww", "fldcw">;
1765 def : MnemonicAlias<"fnstcww", "fnstcw">;
1766 def : MnemonicAlias<"fnstsww", "fnstsw">;
1767 def : MnemonicAlias<"fucomip", "fucompi">;
1768 def : MnemonicAlias<"fwait", "wait">;
1771 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond>
1772 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
1773 !strconcat(Prefix, NewCond, Suffix)>;
1775 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
1776 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
1777 /// example "setz" -> "sete".
1778 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix> {
1779 def C : CondCodeAlias<Prefix, Suffix, "c", "b">; // setc -> setb
1780 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e">; // setz -> sete
1781 def NA : CondCodeAlias<Prefix, Suffix, "na", "be">; // setna -> setbe
1782 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae">; // setnb -> setae
1783 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae">; // setnc -> setae
1784 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le">; // setng -> setle
1785 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge">; // setnl -> setge
1786 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne">; // setnz -> setne
1787 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p">; // setpe -> setp
1788 def PO : CondCodeAlias<Prefix, Suffix, "po", "np">; // setpo -> setnp
1790 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b">; // setnae -> setb
1791 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a">; // setnbe -> seta
1792 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l">; // setnge -> setl
1793 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g">; // setnle -> setg
1796 // Aliases for set<CC>
1797 defm : IntegerCondCodeMnemonicAlias<"set", "">;
1798 // Aliases for j<CC>
1799 defm : IntegerCondCodeMnemonicAlias<"j", "">;
1800 // Aliases for cmov<CC>{w,l,q}
1801 defm : IntegerCondCodeMnemonicAlias<"cmov", "w">;
1802 defm : IntegerCondCodeMnemonicAlias<"cmov", "l">;
1803 defm : IntegerCondCodeMnemonicAlias<"cmov", "q">;
1806 //===----------------------------------------------------------------------===//
1807 // Assembler Instruction Aliases
1808 //===----------------------------------------------------------------------===//
1810 // aad/aam default to base 10 if no operand is specified.
1811 def : InstAlias<"aad", (AAD8i8 10)>;
1812 def : InstAlias<"aam", (AAM8i8 10)>;
1814 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
1815 def : InstAlias<"bt $imm, $mem", (BT32mi8 i32mem:$mem, i32i8imm:$imm)>;
1818 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>;
1819 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>;
1820 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
1821 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
1823 // div and idiv aliases for explicit A register.
1824 def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>;
1825 def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>;
1826 def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>;
1827 def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>;
1828 def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>;
1829 def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>;
1830 def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>;
1831 def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>;
1832 def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>;
1833 def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>;
1834 def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>;
1835 def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>;
1836 def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>;
1837 def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>;
1838 def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>;
1839 def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>;
1843 // Various unary fpstack operations default to operating on on ST1.
1844 // For example, "fxch" -> "fxch %st(1)"
1845 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
1846 def : InstAlias<"fsubp", (SUBR_FPrST0 ST1)>;
1847 def : InstAlias<"fsubrp", (SUB_FPrST0 ST1)>;
1848 def : InstAlias<"fmulp", (MUL_FPrST0 ST1)>;
1849 def : InstAlias<"fdivp", (DIVR_FPrST0 ST1)>;
1850 def : InstAlias<"fdivrp", (DIV_FPrST0 ST1)>;
1851 def : InstAlias<"fxch", (XCH_F ST1)>;
1852 def : InstAlias<"fcomi", (COM_FIr ST1)>;
1853 def : InstAlias<"fcompi", (COM_FIPr ST1)>;
1854 def : InstAlias<"fucom", (UCOM_Fr ST1)>;
1855 def : InstAlias<"fucomp", (UCOM_FPr ST1)>;
1856 def : InstAlias<"fucomi", (UCOM_FIr ST1)>;
1857 def : InstAlias<"fucompi", (UCOM_FIPr ST1)>;
1859 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
1860 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
1861 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
1863 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
1864 def : InstAlias<!strconcat(Mnemonic, " $op, %st(0)"),
1865 (Inst RST:$op), EmitAlias>;
1866 def : InstAlias<!strconcat(Mnemonic, " %st(0), %st(0)"),
1867 (Inst ST0), EmitAlias>;
1870 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
1871 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
1872 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
1873 defm : FpUnaryAlias<"fsubp", SUBR_FPrST0>;
1874 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
1875 defm : FpUnaryAlias<"fsubrp", SUB_FPrST0>;
1876 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
1877 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
1878 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
1879 defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>;
1880 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
1881 defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>;
1882 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
1883 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
1884 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
1885 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
1888 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
1889 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
1890 // solely because gas supports it.
1891 def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op), 0>;
1892 def : InstAlias<"fmulp %st(0), $op", (MUL_FPrST0 RST:$op)>;
1893 def : InstAlias<"fsubp %st(0), $op", (SUBR_FPrST0 RST:$op)>;
1894 def : InstAlias<"fsubrp %st(0), $op", (SUB_FPrST0 RST:$op)>;
1895 def : InstAlias<"fdivp %st(0), $op", (DIVR_FPrST0 RST:$op)>;
1896 def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>;
1898 // We accept "fnstsw %eax" even though it only writes %ax.
1899 def : InstAlias<"fnstsw %eax", (FNSTSW16r)>;
1900 def : InstAlias<"fnstsw %al" , (FNSTSW16r)>;
1901 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
1903 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
1904 // this is compatible with what GAS does.
1905 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1906 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1907 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>;
1908 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>;
1910 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
1911 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
1912 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
1913 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
1914 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
1915 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
1916 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
1918 // inb %dx -> inb %al, %dx
1919 def : InstAlias<"inb %dx", (IN8rr)>;
1920 def : InstAlias<"inw %dx", (IN16rr)>;
1921 def : InstAlias<"inl %dx", (IN32rr)>;
1922 def : InstAlias<"inb $port", (IN8ri i8imm:$port)>;
1923 def : InstAlias<"inw $port", (IN16ri i8imm:$port)>;
1924 def : InstAlias<"inl $port", (IN32ri i8imm:$port)>;
1927 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
1928 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1929 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1930 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
1931 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
1932 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1933 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1935 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
1936 // the move. All segment/mem forms are equivalent, this has the shortest
1938 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
1939 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
1941 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
1942 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
1944 // Match 'movq GR64, MMX' as an alias for movd.
1945 def : InstAlias<"movq $src, $dst",
1946 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
1947 def : InstAlias<"movq $src, $dst",
1948 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
1950 // movsd with no operands (as opposed to the SSE scalar move of a double) is an
1951 // alias for movsl. (as in rep; movsd)
1952 def : InstAlias<"movsd", (MOVSD)>;
1955 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
1956 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
1957 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
1958 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
1959 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
1960 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
1961 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
1964 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
1965 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
1966 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
1967 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
1968 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
1969 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
1970 // Note: No GR32->GR64 movzx form.
1972 // outb %dx -> outb %al, %dx
1973 def : InstAlias<"outb %dx", (OUT8rr)>;
1974 def : InstAlias<"outw %dx", (OUT16rr)>;
1975 def : InstAlias<"outl %dx", (OUT32rr)>;
1976 def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>;
1977 def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>;
1978 def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>;
1980 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
1981 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
1982 // errors, since its encoding is the most compact.
1983 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
1985 // shld/shrd op,op -> shld op, op, CL
1986 def : InstAlias<"shldw $r2, $r1", (SHLD16rrCL GR16:$r1, GR16:$r2)>;
1987 def : InstAlias<"shldl $r2, $r1", (SHLD32rrCL GR32:$r1, GR32:$r2)>;
1988 def : InstAlias<"shldq $r2, $r1", (SHLD64rrCL GR64:$r1, GR64:$r2)>;
1989 def : InstAlias<"shrdw $r2, $r1", (SHRD16rrCL GR16:$r1, GR16:$r2)>;
1990 def : InstAlias<"shrdl $r2, $r1", (SHRD32rrCL GR32:$r1, GR32:$r2)>;
1991 def : InstAlias<"shrdq $r2, $r1", (SHRD64rrCL GR64:$r1, GR64:$r2)>;
1993 def : InstAlias<"shldw $reg, $mem", (SHLD16mrCL i16mem:$mem, GR16:$reg)>;
1994 def : InstAlias<"shldl $reg, $mem", (SHLD32mrCL i32mem:$mem, GR32:$reg)>;
1995 def : InstAlias<"shldq $reg, $mem", (SHLD64mrCL i64mem:$mem, GR64:$reg)>;
1996 def : InstAlias<"shrdw $reg, $mem", (SHRD16mrCL i16mem:$mem, GR16:$reg)>;
1997 def : InstAlias<"shrdl $reg, $mem", (SHRD32mrCL i32mem:$mem, GR32:$reg)>;
1998 def : InstAlias<"shrdq $reg, $mem", (SHRD64mrCL i64mem:$mem, GR64:$reg)>;
2000 /* FIXME: This is disabled because the asm matcher is currently incapable of
2001 * matching a fixed immediate like $1.
2002 // "shl X, $1" is an alias for "shl X".
2003 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
2004 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2005 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
2006 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2007 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
2008 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2009 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
2010 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2011 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
2012 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2013 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
2014 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2015 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
2016 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2017 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
2018 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2019 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2022 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2023 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
2024 defm : ShiftRotateByOneAlias<"rol", "ROL">;
2025 defm : ShiftRotateByOneAlias<"ror", "ROR">;
2028 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
2029 def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>;
2030 def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>;
2031 def : InstAlias<"testl $val, $mem", (TEST32rm GR32:$val, i32mem:$mem)>;
2032 def : InstAlias<"testq $val, $mem", (TEST64rm GR64:$val, i64mem:$mem)>;
2034 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
2035 def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>;
2036 def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>;
2037 def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>;
2038 def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>;
2040 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
2041 def : InstAlias<"xchgw %ax, $src", (XCHG16ar GR16:$src)>;
2042 def : InstAlias<"xchgl %eax, $src", (XCHG32ar GR32:$src)>, Requires<[In32BitMode]>;
2043 def : InstAlias<"xchgl %eax, $src", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
2044 def : InstAlias<"xchgq %rax, $src", (XCHG64ar GR64:$src)>;