3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
33 def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
37 def SDTX86BrCond : SDTypeProfile<0, 3,
38 [SDTCisVT<0, OtherVT>,
39 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
41 def SDTX86SetCC : SDTypeProfile<1, 2,
43 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
44 def SDTX86SetCC_C : SDTypeProfile<1, 2,
46 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
48 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
50 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
52 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
53 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
54 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
56 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
57 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
60 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
62 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
66 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
68 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
70 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
72 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
74 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
76 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
78 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
80 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
81 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
82 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
83 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
85 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
87 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
89 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
90 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
92 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
93 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
95 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
96 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
98 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
99 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
101 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
102 [SDNPHasChain, SDNPMayStore,
103 SDNPMayLoad, SDNPMemOperand]>;
104 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
105 [SDNPHasChain, SDNPMayStore,
106 SDNPMayLoad, SDNPMemOperand]>;
107 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
108 [SDNPHasChain, SDNPMayStore,
109 SDNPMayLoad, SDNPMemOperand]>;
110 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
111 [SDNPHasChain, SDNPMayStore,
112 SDNPMayLoad, SDNPMemOperand]>;
113 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
114 [SDNPHasChain, SDNPMayStore,
115 SDNPMayLoad, SDNPMemOperand]>;
116 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
117 [SDNPHasChain, SDNPMayStore,
118 SDNPMayLoad, SDNPMemOperand]>;
119 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
120 [SDNPHasChain, SDNPMayStore,
121 SDNPMayLoad, SDNPMemOperand]>;
122 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
123 [SDNPHasChain, SDNPOptInFlag]>;
125 def X86vastart_save_xmm_regs :
126 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
127 SDT_X86VASTART_SAVE_XMM_REGS,
130 def X86callseq_start :
131 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
132 [SDNPHasChain, SDNPOutFlag]>;
134 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
135 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
137 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
138 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
140 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
141 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
142 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
143 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
146 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
147 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
149 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
150 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
152 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
153 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
154 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
155 SDT_X86SegmentBaseAddress, []>;
157 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
160 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
161 [SDNPHasChain, SDNPOptInFlag]>;
163 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
165 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
166 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
168 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
170 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
171 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
172 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
174 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
176 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
179 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
181 //===----------------------------------------------------------------------===//
182 // X86 Operand Definitions.
185 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
186 // the index operand of an address, to conform to x86 encoding restrictions.
187 def ptr_rc_nosp : PointerLikeRegClass<1>;
189 // *mem - Operand definitions for the funky X86 addressing mode operands.
191 def X86MemAsmOperand : AsmOperandClass {
195 def X86AbsMemAsmOperand : AsmOperandClass {
197 let SuperClass = X86MemAsmOperand;
199 def X86NoSegMemAsmOperand : AsmOperandClass {
200 let Name = "NoSegMem";
201 let SuperClass = X86MemAsmOperand;
203 class X86MemOperand<string printMethod> : Operand<iPTR> {
204 let PrintMethod = printMethod;
205 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
206 let ParserMatchClass = X86MemAsmOperand;
209 def opaque32mem : X86MemOperand<"printopaquemem">;
210 def opaque48mem : X86MemOperand<"printopaquemem">;
211 def opaque80mem : X86MemOperand<"printopaquemem">;
212 def opaque512mem : X86MemOperand<"printopaquemem">;
214 def i8mem : X86MemOperand<"printi8mem">;
215 def i16mem : X86MemOperand<"printi16mem">;
216 def i32mem : X86MemOperand<"printi32mem">;
217 def i64mem : X86MemOperand<"printi64mem">;
218 def i128mem : X86MemOperand<"printi128mem">;
219 //def i256mem : X86MemOperand<"printi256mem">;
220 def f32mem : X86MemOperand<"printf32mem">;
221 def f64mem : X86MemOperand<"printf64mem">;
222 def f80mem : X86MemOperand<"printf80mem">;
223 def f128mem : X86MemOperand<"printf128mem">;
224 //def f256mem : X86MemOperand<"printf256mem">;
226 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
227 // plain GR64, so that it doesn't potentially require a REX prefix.
228 def i8mem_NOREX : Operand<i64> {
229 let PrintMethod = "printi8mem";
230 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
231 let ParserMatchClass = X86MemAsmOperand;
234 def lea32mem : Operand<i32> {
235 let PrintMethod = "printlea32mem";
236 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
237 let ParserMatchClass = X86NoSegMemAsmOperand;
240 let ParserMatchClass = X86AbsMemAsmOperand,
241 PrintMethod = "print_pcrel_imm" in {
242 def i32imm_pcrel : Operand<i32>;
244 def offset8 : Operand<i64>;
245 def offset16 : Operand<i64>;
246 def offset32 : Operand<i64>;
247 def offset64 : Operand<i64>;
249 // Branch targets have OtherVT type and print as pc-relative values.
250 def brtarget : Operand<OtherVT>;
251 def brtarget8 : Operand<OtherVT>;
255 def SSECC : Operand<i8> {
256 let PrintMethod = "printSSECC";
259 def ImmSExt8AsmOperand : AsmOperandClass {
260 let Name = "ImmSExt8";
261 let SuperClass = ImmAsmOperand;
264 // A couple of more descriptive operand definitions.
265 // 16-bits but only 8 bits are significant.
266 def i16i8imm : Operand<i16> {
267 let ParserMatchClass = ImmSExt8AsmOperand;
269 // 32-bits but only 8 bits are significant.
270 def i32i8imm : Operand<i32> {
271 let ParserMatchClass = ImmSExt8AsmOperand;
274 //===----------------------------------------------------------------------===//
275 // X86 Complex Pattern Definitions.
278 // Define X86 specific addressing mode.
279 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
280 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
281 [add, sub, mul, X86mul_imm, shl, or, frameindex],
283 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
284 [tglobaltlsaddr], []>;
286 //===----------------------------------------------------------------------===//
287 // X86 Instruction Predicate Definitions.
288 def HasMMX : Predicate<"Subtarget->hasMMX()">;
289 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
290 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
291 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
292 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
293 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
294 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
295 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
296 def HasAVX : Predicate<"Subtarget->hasAVX()">;
297 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
298 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
299 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
300 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
301 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
302 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
303 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
304 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
305 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
306 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
307 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
308 "TM.getCodeModel() != CodeModel::Kernel">;
309 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
310 "TM.getCodeModel() == CodeModel::Kernel">;
311 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
312 def OptForSize : Predicate<"OptForSize">;
313 def OptForSpeed : Predicate<"!OptForSize">;
314 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
315 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
317 //===----------------------------------------------------------------------===//
318 // X86 Instruction Format Definitions.
321 include "X86InstrFormats.td"
323 //===----------------------------------------------------------------------===//
324 // Pattern fragments...
327 // X86 specific condition code. These correspond to CondCode in
328 // X86InstrInfo.h. They must be kept in synch.
329 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
330 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
331 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
332 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
333 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
334 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
335 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
336 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
337 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
338 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
339 def X86_COND_NO : PatLeaf<(i8 10)>;
340 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
341 def X86_COND_NS : PatLeaf<(i8 12)>;
342 def X86_COND_O : PatLeaf<(i8 13)>;
343 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
344 def X86_COND_S : PatLeaf<(i8 15)>;
346 def immSext8 : PatLeaf<(imm), [{
347 return N->getSExtValue() == (int8_t)N->getSExtValue();
350 def i16immSExt8 : PatLeaf<(i16 immSext8)>;
351 def i32immSExt8 : PatLeaf<(i32 immSext8)>;
353 /// Load patterns: these constraint the match to the right address space.
354 def dsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
355 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
356 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
357 if (PT->getAddressSpace() > 255)
362 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
363 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
364 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
365 return PT->getAddressSpace() == 256;
369 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
370 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
371 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
372 return PT->getAddressSpace() == 257;
377 // Helper fragments for loads.
378 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
379 // known to be 32-bit aligned or better. Ditto for i8 to i16.
380 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
381 LoadSDNode *LD = cast<LoadSDNode>(N);
382 if (const Value *Src = LD->getSrcValue())
383 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
384 if (PT->getAddressSpace() > 255)
386 ISD::LoadExtType ExtType = LD->getExtensionType();
387 if (ExtType == ISD::NON_EXTLOAD)
389 if (ExtType == ISD::EXTLOAD)
390 return LD->getAlignment() >= 2 && !LD->isVolatile();
394 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
395 LoadSDNode *LD = cast<LoadSDNode>(N);
396 if (const Value *Src = LD->getSrcValue())
397 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
398 if (PT->getAddressSpace() > 255)
400 ISD::LoadExtType ExtType = LD->getExtensionType();
401 if (ExtType == ISD::EXTLOAD)
402 return LD->getAlignment() >= 2 && !LD->isVolatile();
406 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
407 LoadSDNode *LD = cast<LoadSDNode>(N);
408 if (const Value *Src = LD->getSrcValue())
409 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
410 if (PT->getAddressSpace() > 255)
412 ISD::LoadExtType ExtType = LD->getExtensionType();
413 if (ExtType == ISD::NON_EXTLOAD)
415 if (ExtType == ISD::EXTLOAD)
416 return LD->getAlignment() >= 4 && !LD->isVolatile();
420 def loadi8 : PatFrag<(ops node:$ptr), (i8 (dsload node:$ptr))>;
421 def loadi64 : PatFrag<(ops node:$ptr), (i64 (dsload node:$ptr))>;
422 def loadf32 : PatFrag<(ops node:$ptr), (f32 (dsload node:$ptr))>;
423 def loadf64 : PatFrag<(ops node:$ptr), (f64 (dsload node:$ptr))>;
424 def loadf80 : PatFrag<(ops node:$ptr), (f80 (dsload node:$ptr))>;
426 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
427 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
428 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
430 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
431 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
432 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
433 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
434 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
435 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
437 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
438 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
439 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
440 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
441 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
442 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
445 // An 'and' node with a single use.
446 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
447 return N->hasOneUse();
449 // An 'srl' node with a single use.
450 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
451 return N->hasOneUse();
453 // An 'trunc' node with a single use.
454 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
455 return N->hasOneUse();
458 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
459 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
460 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
461 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
463 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
464 APInt Mask = APInt::getAllOnesValue(BitWidth);
465 APInt KnownZero0, KnownOne0;
466 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
467 APInt KnownZero1, KnownOne1;
468 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
469 return (~KnownZero0 & ~KnownZero1) == 0;
473 // 'shld' and 'shrd' instruction patterns. Note that even though these have
474 // the srl and shl in their patterns, the C++ code must still check for them,
475 // because predicates are tested before children nodes are explored.
477 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
478 (or (srl node:$src1, node:$amt1),
479 (shl node:$src2, node:$amt2)), [{
480 assert(N->getOpcode() == ISD::OR);
481 return N->getOperand(0).getOpcode() == ISD::SRL &&
482 N->getOperand(1).getOpcode() == ISD::SHL &&
483 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
484 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
485 N->getOperand(0).getConstantOperandVal(1) ==
486 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
489 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
490 (or (shl node:$src1, node:$amt1),
491 (srl node:$src2, node:$amt2)), [{
492 assert(N->getOpcode() == ISD::OR);
493 return N->getOperand(0).getOpcode() == ISD::SHL &&
494 N->getOperand(1).getOpcode() == ISD::SRL &&
495 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
496 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
497 N->getOperand(0).getConstantOperandVal(1) ==
498 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
501 //===----------------------------------------------------------------------===//
502 // Instruction list...
505 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
506 // a stack adjustment and the codegen must know that they may modify the stack
507 // pointer before prolog-epilog rewriting occurs.
508 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
509 // sub / add which can clobber EFLAGS.
510 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
511 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
513 [(X86callseq_start timm:$amt)]>,
514 Requires<[In32BitMode]>;
515 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
517 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
518 Requires<[In32BitMode]>;
521 // x86-64 va_start lowering magic.
522 let usesCustomInserter = 1 in
523 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
526 i64imm:$regsavefi, i64imm:$offset,
528 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
529 [(X86vastart_save_xmm_regs GR8:$al,
534 let neverHasSideEffects = 1 in {
535 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
536 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
537 "nop{w}\t$zero", []>, TB, OpSize;
538 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
539 "nop{l}\t$zero", []>, TB;
543 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int\t3", []>;
544 def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
545 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize;
546 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>;
548 // PIC base construction. This expands to code that looks like this:
551 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
552 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
555 //===----------------------------------------------------------------------===//
556 // Control Flow Instructions.
559 // Return instructions.
560 let isTerminator = 1, isReturn = 1, isBarrier = 1,
561 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
562 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
565 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
567 [(X86retflag timm:$amt)]>;
568 def LRET : I <0xCB, RawFrm, (outs), (ins),
570 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
574 // Unconditional branches.
575 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
576 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
577 "jmp\t$dst", [(br bb:$dst)]>;
578 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
582 // Conditional Branches.
583 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
584 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
585 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
586 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
587 [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
591 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
592 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
593 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
594 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
595 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
596 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
597 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
598 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
599 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
600 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
601 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
602 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
603 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
604 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
605 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
606 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
608 // FIXME: What about the CX/RCX versions of this instruction?
609 let Uses = [ECX], isBranch = 1, isTerminator = 1 in
610 def JCXZ8 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
615 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
616 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
617 [(brind GR32:$dst)]>;
618 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
619 [(brind (loadi32 addr:$dst))]>;
621 def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
622 (ins i16imm:$seg, i16imm:$off),
623 "ljmp{w}\t$seg, $off", []>, OpSize;
624 def FARJMP32i : Iseg32<0xEA, RawFrm, (outs),
625 (ins i16imm:$seg, i32imm:$off),
626 "ljmp{l}\t$seg, $off", []>;
628 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
629 "ljmp{w}\t{*}$dst", []>, OpSize;
630 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
631 "ljmp{l}\t{*}$dst", []>;
637 def LOOP : I<0xE2, RawFrm, (ins brtarget8:$dst), (outs), "loop\t$dst", []>;
638 def LOOPE : I<0xE1, RawFrm, (ins brtarget8:$dst), (outs), "loope\t$dst", []>;
639 def LOOPNE : I<0xE0, RawFrm, (ins brtarget8:$dst), (outs), "loopne\t$dst", []>;
641 //===----------------------------------------------------------------------===//
642 // Call Instructions...
645 // All calls clobber the non-callee saved registers. ESP is marked as
646 // a use to prevent stack-pointer assignments that appear immediately
647 // before calls from potentially appearing dead. Uses for argument
648 // registers are added manually.
649 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
650 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
651 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
652 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
654 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
655 (outs), (ins i32imm_pcrel:$dst,variable_ops),
657 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
658 "call\t{*}$dst", [(X86call GR32:$dst)]>;
659 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
660 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
662 def FARCALL16i : Iseg16<0x9A, RawFrm, (outs),
663 (ins i16imm:$seg, i16imm:$off),
664 "lcall{w}\t$seg, $off", []>, OpSize;
665 def FARCALL32i : Iseg32<0x9A, RawFrm, (outs),
666 (ins i16imm:$seg, i32imm:$off),
667 "lcall{l}\t$seg, $off", []>;
669 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
670 "lcall{w}\t{*}$dst", []>, OpSize;
671 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
672 "lcall{l}\t{*}$dst", []>;
675 // Constructing a stack frame.
677 def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl),
678 "enter\t$len, $lvl", []>;
682 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
683 def TCRETURNdi : I<0, Pseudo, (outs),
684 (ins i32imm:$dst, i32imm:$offset, variable_ops),
685 "#TC_RETURN $dst $offset",
688 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
689 def TCRETURNri : I<0, Pseudo, (outs),
690 (ins GR32:$dst, i32imm:$offset, variable_ops),
691 "#TC_RETURN $dst $offset",
694 // FIXME: The should be pseudo instructions that are lowered when going to
696 let isCall = 1, isBranch = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
697 def TAILJMPd : Ii32<0xE9, RawFrm, (outs),(ins i32imm_pcrel:$dst,variable_ops),
698 "jmp\t$dst # TAILCALL",
700 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
701 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst, variable_ops),
702 "jmp{l}\t{*}$dst # TAILCALL",
704 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
705 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst, variable_ops),
706 "jmp\t{*}$dst # TAILCALL", []>;
708 //===----------------------------------------------------------------------===//
709 // Miscellaneous Instructions...
711 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
712 def LEAVE : I<0xC9, RawFrm,
713 (outs), (ins), "leave", []>;
715 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
716 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
717 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
718 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
719 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
720 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
721 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
722 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
724 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
726 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
728 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
729 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
731 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
733 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
734 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
737 let mayStore = 1 in {
738 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
740 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
741 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
743 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
745 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
746 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
750 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
751 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
752 "push{l}\t$imm", []>;
753 def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
754 "push{l}\t$imm", []>;
755 def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
756 "push{l}\t$imm", []>;
759 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
760 def POPF : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
761 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf{l}", []>;
763 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
764 def PUSHF : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
765 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf{l}", []>;
768 let isTwoAddress = 1 in // GR32 = bswap GR32
769 def BSWAP32r : I<0xC8, AddRegFrm,
770 (outs GR32:$dst), (ins GR32:$src),
772 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
775 // Bit scan instructions.
776 let Defs = [EFLAGS] in {
777 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
778 "bsf{w}\t{$src, $dst|$dst, $src}",
779 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
780 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
781 "bsf{w}\t{$src, $dst|$dst, $src}",
782 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
783 (implicit EFLAGS)]>, TB;
784 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
785 "bsf{l}\t{$src, $dst|$dst, $src}",
786 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
787 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
788 "bsf{l}\t{$src, $dst|$dst, $src}",
789 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
790 (implicit EFLAGS)]>, TB;
792 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
793 "bsr{w}\t{$src, $dst|$dst, $src}",
794 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
795 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
796 "bsr{w}\t{$src, $dst|$dst, $src}",
797 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
798 (implicit EFLAGS)]>, TB;
799 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
800 "bsr{l}\t{$src, $dst|$dst, $src}",
801 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
802 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
803 "bsr{l}\t{$src, $dst|$dst, $src}",
804 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
805 (implicit EFLAGS)]>, TB;
808 let neverHasSideEffects = 1 in
809 def LEA16r : I<0x8D, MRMSrcMem,
810 (outs GR16:$dst), (ins lea32mem:$src),
811 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
812 let isReMaterializable = 1 in
813 def LEA32r : I<0x8D, MRMSrcMem,
814 (outs GR32:$dst), (ins lea32mem:$src),
815 "lea{l}\t{$src|$dst}, {$dst|$src}",
816 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
818 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
819 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
820 [(X86rep_movs i8)]>, REP;
821 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
822 [(X86rep_movs i16)]>, REP, OpSize;
823 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
824 [(X86rep_movs i32)]>, REP;
827 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
828 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
829 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
830 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
831 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
834 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
835 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
836 [(X86rep_stos i8)]>, REP;
837 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
838 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
839 [(X86rep_stos i16)]>, REP, OpSize;
840 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
841 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
842 [(X86rep_stos i32)]>, REP;
844 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
845 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
846 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
847 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
848 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
849 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
850 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
852 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
853 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
854 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
856 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
857 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
858 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
860 let Defs = [RAX, RDX] in
861 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
864 let Defs = [RAX, RCX, RDX] in
865 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
867 let isBarrier = 1, hasCtrlDep = 1 in {
868 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
871 def SYSCALL : I<0x05, RawFrm,
872 (outs), (ins), "syscall", []>, TB;
873 def SYSRET : I<0x07, RawFrm,
874 (outs), (ins), "sysret", []>, TB;
875 def SYSENTER : I<0x34, RawFrm,
876 (outs), (ins), "sysenter", []>, TB;
877 def SYSEXIT : I<0x35, RawFrm,
878 (outs), (ins), "sysexit", []>, TB;
880 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
883 //===----------------------------------------------------------------------===//
884 // Input/Output Instructions...
886 let Defs = [AL], Uses = [DX] in
887 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
888 "in{b}\t{%dx, %al|%AL, %DX}", []>;
889 let Defs = [AX], Uses = [DX] in
890 def IN16rr : I<0xED, RawFrm, (outs), (ins),
891 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
892 let Defs = [EAX], Uses = [DX] in
893 def IN32rr : I<0xED, RawFrm, (outs), (ins),
894 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
897 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
898 "in{b}\t{$port, %al|%AL, $port}", []>;
900 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
901 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
903 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
904 "in{l}\t{$port, %eax|%EAX, $port}", []>;
906 let Uses = [DX, AL] in
907 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
908 "out{b}\t{%al, %dx|%DX, %AL}", []>;
909 let Uses = [DX, AX] in
910 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
911 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
912 let Uses = [DX, EAX] in
913 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
914 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
917 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
918 "out{b}\t{%al, $port|$port, %AL}", []>;
920 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
921 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
923 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
924 "out{l}\t{%eax, $port|$port, %EAX}", []>;
926 def IN8 : I<0x6C, RawFrm, (outs), (ins),
928 def IN16 : I<0x6D, RawFrm, (outs), (ins),
929 "ins{w}", []>, OpSize;
930 def IN32 : I<0x6D, RawFrm, (outs), (ins),
933 //===----------------------------------------------------------------------===//
934 // Move Instructions...
936 let neverHasSideEffects = 1 in {
937 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
938 "mov{b}\t{$src, $dst|$dst, $src}", []>;
939 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
940 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
941 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
942 "mov{l}\t{$src, $dst|$dst, $src}", []>;
944 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
945 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
946 "mov{b}\t{$src, $dst|$dst, $src}",
947 [(set GR8:$dst, imm:$src)]>;
948 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
949 "mov{w}\t{$src, $dst|$dst, $src}",
950 [(set GR16:$dst, imm:$src)]>, OpSize;
951 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
952 "mov{l}\t{$src, $dst|$dst, $src}",
953 [(set GR32:$dst, imm:$src)]>;
956 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
957 "mov{b}\t{$src, $dst|$dst, $src}",
958 [(store (i8 imm:$src), addr:$dst)]>;
959 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
960 "mov{w}\t{$src, $dst|$dst, $src}",
961 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
962 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
963 "mov{l}\t{$src, $dst|$dst, $src}",
964 [(store (i32 imm:$src), addr:$dst)]>;
966 def MOV8o8a : Ii8 <0xA0, RawFrm, (outs), (ins offset8:$src),
967 "mov{b}\t{$src, %al|%al, $src}", []>;
968 def MOV16o16a : Ii16 <0xA1, RawFrm, (outs), (ins offset16:$src),
969 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
970 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
971 "mov{l}\t{$src, %eax|%eax, $src}", []>;
973 def MOV8ao8 : Ii8 <0xA2, RawFrm, (outs offset8:$dst), (ins),
974 "mov{b}\t{%al, $dst|$dst, %al}", []>;
975 def MOV16ao16 : Ii16 <0xA3, RawFrm, (outs offset16:$dst), (ins),
976 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize;
977 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
978 "mov{l}\t{%eax, $dst|$dst, %eax}", []>;
980 // Moves to and from segment registers
981 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
982 "mov{w}\t{$src, $dst|$dst, $src}", []>;
983 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
984 "mov{w}\t{$src, $dst|$dst, $src}", []>;
985 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
986 "mov{w}\t{$src, $dst|$dst, $src}", []>;
987 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
988 "mov{w}\t{$src, $dst|$dst, $src}", []>;
990 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
991 "mov{b}\t{$src, $dst|$dst, $src}", []>;
992 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
993 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
994 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
995 "mov{l}\t{$src, $dst|$dst, $src}", []>;
997 let canFoldAsLoad = 1, isReMaterializable = 1 in {
998 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
999 "mov{b}\t{$src, $dst|$dst, $src}",
1000 [(set GR8:$dst, (loadi8 addr:$src))]>;
1001 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1002 "mov{w}\t{$src, $dst|$dst, $src}",
1003 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
1004 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1005 "mov{l}\t{$src, $dst|$dst, $src}",
1006 [(set GR32:$dst, (loadi32 addr:$src))]>;
1009 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1010 "mov{b}\t{$src, $dst|$dst, $src}",
1011 [(store GR8:$src, addr:$dst)]>;
1012 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1013 "mov{w}\t{$src, $dst|$dst, $src}",
1014 [(store GR16:$src, addr:$dst)]>, OpSize;
1015 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1016 "mov{l}\t{$src, $dst|$dst, $src}",
1017 [(store GR32:$src, addr:$dst)]>;
1019 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1020 // that they can be used for copying and storing h registers, which can't be
1021 // encoded when a REX prefix is present.
1022 let neverHasSideEffects = 1 in
1023 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1024 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1025 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1027 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1028 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1029 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1031 canFoldAsLoad = 1, isReMaterializable = 1 in
1032 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1033 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1034 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1036 // Moves to and from debug registers
1037 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
1038 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1039 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
1040 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1042 // Moves to and from control registers
1043 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG_32:$src),
1044 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1045 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_32:$dst), (ins GR32:$src),
1046 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1048 //===----------------------------------------------------------------------===//
1049 // Fixed-Register Multiplication and Division Instructions...
1052 // Extra precision multiplication
1054 // AL is really implied by AX, by the registers in Defs must match the
1055 // SDNode results (i8, i32).
1056 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1057 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
1058 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1059 // This probably ought to be moved to a def : Pat<> if the
1060 // syntax can be accepted.
1061 [(set AL, (mul AL, GR8:$src)),
1062 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1064 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1065 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1067 []>, OpSize; // AX,DX = AX*GR16
1069 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1070 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1072 []>; // EAX,EDX = EAX*GR32
1074 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1075 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1077 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1078 // This probably ought to be moved to a def : Pat<> if the
1079 // syntax can be accepted.
1080 [(set AL, (mul AL, (loadi8 addr:$src))),
1081 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1083 let mayLoad = 1, neverHasSideEffects = 1 in {
1084 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1085 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1087 []>, OpSize; // AX,DX = AX*[mem16]
1089 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1090 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1092 []>; // EAX,EDX = EAX*[mem32]
1095 let neverHasSideEffects = 1 in {
1096 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1097 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1099 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1100 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1101 OpSize; // AX,DX = AX*GR16
1102 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1103 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1104 // EAX,EDX = EAX*GR32
1105 let mayLoad = 1 in {
1106 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1107 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1108 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1109 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1110 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1111 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1112 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1113 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1114 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1116 } // neverHasSideEffects
1118 // unsigned division/remainder
1119 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1120 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1121 "div{b}\t$src", []>;
1122 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1123 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1124 "div{w}\t$src", []>, OpSize;
1125 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1126 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1127 "div{l}\t$src", []>;
1128 let mayLoad = 1 in {
1129 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1130 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1131 "div{b}\t$src", []>;
1132 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1133 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1134 "div{w}\t$src", []>, OpSize;
1135 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1136 // EDX:EAX/[mem32] = EAX,EDX
1137 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
1138 "div{l}\t$src", []>;
1141 // Signed division/remainder.
1142 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1143 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1144 "idiv{b}\t$src", []>;
1145 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1146 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1147 "idiv{w}\t$src", []>, OpSize;
1148 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1149 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1150 "idiv{l}\t$src", []>;
1151 let mayLoad = 1, mayLoad = 1 in {
1152 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1153 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1154 "idiv{b}\t$src", []>;
1155 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1156 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1157 "idiv{w}\t$src", []>, OpSize;
1158 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1159 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1160 // EDX:EAX/[mem32] = EAX,EDX
1161 "idiv{l}\t$src", []>;
1164 //===----------------------------------------------------------------------===//
1165 // Two address Instructions.
1167 let isTwoAddress = 1 in {
1169 // Conditional moves
1170 let Uses = [EFLAGS] in {
1172 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1173 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1174 // however that requires promoting the operands, and can induce additional
1175 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1176 // clobber EFLAGS, because if one of the operands is zero, the expansion
1177 // could involve an xor.
1178 let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in
1179 def CMOV_GR8 : I<0, Pseudo,
1180 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1181 "#CMOV_GR8 PSEUDO!",
1182 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1183 imm:$cond, EFLAGS))]>;
1185 let isCommutable = 1 in {
1186 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1187 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1188 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1189 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1190 X86_COND_B, EFLAGS))]>,
1192 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1193 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1194 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1195 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1196 X86_COND_B, EFLAGS))]>,
1198 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1199 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1200 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1201 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1202 X86_COND_AE, EFLAGS))]>,
1204 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1205 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1206 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1207 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1208 X86_COND_AE, EFLAGS))]>,
1210 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1211 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1212 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1213 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1214 X86_COND_E, EFLAGS))]>,
1216 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1217 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1218 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1219 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1220 X86_COND_E, EFLAGS))]>,
1222 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1223 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1224 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1225 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1226 X86_COND_NE, EFLAGS))]>,
1228 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1229 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1230 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1231 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1232 X86_COND_NE, EFLAGS))]>,
1234 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1235 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1236 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1237 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1238 X86_COND_BE, EFLAGS))]>,
1240 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1241 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1242 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1243 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1244 X86_COND_BE, EFLAGS))]>,
1246 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1247 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1248 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1249 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1250 X86_COND_A, EFLAGS))]>,
1252 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1253 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1254 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1255 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1256 X86_COND_A, EFLAGS))]>,
1258 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1259 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1260 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1261 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1262 X86_COND_L, EFLAGS))]>,
1264 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1265 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1266 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1267 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1268 X86_COND_L, EFLAGS))]>,
1270 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1271 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1272 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1273 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1274 X86_COND_GE, EFLAGS))]>,
1276 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1277 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1278 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1279 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1280 X86_COND_GE, EFLAGS))]>,
1282 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1283 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1284 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1285 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1286 X86_COND_LE, EFLAGS))]>,
1288 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1289 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1290 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1291 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1292 X86_COND_LE, EFLAGS))]>,
1294 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1295 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1296 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1297 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1298 X86_COND_G, EFLAGS))]>,
1300 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1301 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1302 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1303 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1304 X86_COND_G, EFLAGS))]>,
1306 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1307 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1308 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1309 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1310 X86_COND_S, EFLAGS))]>,
1312 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1313 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1314 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1315 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1316 X86_COND_S, EFLAGS))]>,
1318 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1319 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1320 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1321 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1322 X86_COND_NS, EFLAGS))]>,
1324 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1325 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1326 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1327 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1328 X86_COND_NS, EFLAGS))]>,
1330 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1331 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1332 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1333 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1334 X86_COND_P, EFLAGS))]>,
1336 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1337 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1338 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1339 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1340 X86_COND_P, EFLAGS))]>,
1342 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1343 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1344 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1345 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1346 X86_COND_NP, EFLAGS))]>,
1348 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1349 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1350 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1351 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1352 X86_COND_NP, EFLAGS))]>,
1354 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1355 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1356 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1357 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1358 X86_COND_O, EFLAGS))]>,
1360 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1361 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1362 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1363 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1364 X86_COND_O, EFLAGS))]>,
1366 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1367 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1368 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1369 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1370 X86_COND_NO, EFLAGS))]>,
1372 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1373 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1374 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1375 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1376 X86_COND_NO, EFLAGS))]>,
1378 } // isCommutable = 1
1380 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1381 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1382 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1383 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1384 X86_COND_B, EFLAGS))]>,
1386 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1387 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1388 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1389 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1390 X86_COND_B, EFLAGS))]>,
1392 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1393 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1394 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1395 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1396 X86_COND_AE, EFLAGS))]>,
1398 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1399 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1400 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1401 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1402 X86_COND_AE, EFLAGS))]>,
1404 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1405 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1406 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1407 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1408 X86_COND_E, EFLAGS))]>,
1410 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1411 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1412 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1413 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1414 X86_COND_E, EFLAGS))]>,
1416 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1417 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1418 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1419 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1420 X86_COND_NE, EFLAGS))]>,
1422 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1423 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1424 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1425 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1426 X86_COND_NE, EFLAGS))]>,
1428 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1429 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1430 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1431 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1432 X86_COND_BE, EFLAGS))]>,
1434 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1435 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1436 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1437 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1438 X86_COND_BE, EFLAGS))]>,
1440 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1441 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1442 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1443 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1444 X86_COND_A, EFLAGS))]>,
1446 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1447 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1448 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1449 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1450 X86_COND_A, EFLAGS))]>,
1452 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1453 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1454 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1455 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1456 X86_COND_L, EFLAGS))]>,
1458 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1459 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1460 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1461 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1462 X86_COND_L, EFLAGS))]>,
1464 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1465 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1466 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1467 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1468 X86_COND_GE, EFLAGS))]>,
1470 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1471 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1472 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1473 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1474 X86_COND_GE, EFLAGS))]>,
1476 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1477 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1478 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1479 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1480 X86_COND_LE, EFLAGS))]>,
1482 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1483 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1484 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1485 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1486 X86_COND_LE, EFLAGS))]>,
1488 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1489 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1490 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1491 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1492 X86_COND_G, EFLAGS))]>,
1494 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1495 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1496 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1497 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1498 X86_COND_G, EFLAGS))]>,
1500 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1501 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1502 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1503 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1504 X86_COND_S, EFLAGS))]>,
1506 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1507 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1508 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1509 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1510 X86_COND_S, EFLAGS))]>,
1512 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1513 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1514 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1515 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1516 X86_COND_NS, EFLAGS))]>,
1518 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1519 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1520 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1521 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1522 X86_COND_NS, EFLAGS))]>,
1524 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1525 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1526 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1527 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1528 X86_COND_P, EFLAGS))]>,
1530 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1531 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1532 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1533 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1534 X86_COND_P, EFLAGS))]>,
1536 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1537 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1538 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1539 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1540 X86_COND_NP, EFLAGS))]>,
1542 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1543 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1544 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1545 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1546 X86_COND_NP, EFLAGS))]>,
1548 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1549 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1550 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1551 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1552 X86_COND_O, EFLAGS))]>,
1554 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1555 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1556 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1557 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1558 X86_COND_O, EFLAGS))]>,
1560 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1561 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1562 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1563 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1564 X86_COND_NO, EFLAGS))]>,
1566 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1567 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1568 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1569 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1570 X86_COND_NO, EFLAGS))]>,
1572 } // Uses = [EFLAGS]
1575 // unary instructions
1576 let CodeSize = 2 in {
1577 let Defs = [EFLAGS] in {
1578 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1579 [(set GR8:$dst, (ineg GR8:$src)),
1580 (implicit EFLAGS)]>;
1581 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1582 [(set GR16:$dst, (ineg GR16:$src)),
1583 (implicit EFLAGS)]>, OpSize;
1584 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1585 [(set GR32:$dst, (ineg GR32:$src)),
1586 (implicit EFLAGS)]>;
1587 let isTwoAddress = 0 in {
1588 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1589 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1590 (implicit EFLAGS)]>;
1591 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1592 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1593 (implicit EFLAGS)]>, OpSize;
1594 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1595 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1596 (implicit EFLAGS)]>;
1598 } // Defs = [EFLAGS]
1600 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1601 let AddedComplexity = 15 in {
1602 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1603 [(set GR8:$dst, (not GR8:$src))]>;
1604 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1605 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1606 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1607 [(set GR32:$dst, (not GR32:$src))]>;
1609 let isTwoAddress = 0 in {
1610 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1611 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1612 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1613 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1614 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1615 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1619 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1620 let Defs = [EFLAGS] in {
1622 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1623 [(set GR8:$dst, (add GR8:$src, 1)),
1624 (implicit EFLAGS)]>;
1625 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1626 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1628 [(set GR16:$dst, (add GR16:$src, 1)),
1629 (implicit EFLAGS)]>,
1630 OpSize, Requires<[In32BitMode]>;
1631 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1633 [(set GR32:$dst, (add GR32:$src, 1)),
1634 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1636 let isTwoAddress = 0, CodeSize = 2 in {
1637 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1638 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1639 (implicit EFLAGS)]>;
1640 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1641 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1642 (implicit EFLAGS)]>,
1643 OpSize, Requires<[In32BitMode]>;
1644 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1645 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1646 (implicit EFLAGS)]>,
1647 Requires<[In32BitMode]>;
1651 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1652 [(set GR8:$dst, (add GR8:$src, -1)),
1653 (implicit EFLAGS)]>;
1654 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1655 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1657 [(set GR16:$dst, (add GR16:$src, -1)),
1658 (implicit EFLAGS)]>,
1659 OpSize, Requires<[In32BitMode]>;
1660 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1662 [(set GR32:$dst, (add GR32:$src, -1)),
1663 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1666 let isTwoAddress = 0, CodeSize = 2 in {
1667 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1668 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1669 (implicit EFLAGS)]>;
1670 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1671 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1672 (implicit EFLAGS)]>,
1673 OpSize, Requires<[In32BitMode]>;
1674 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1675 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1676 (implicit EFLAGS)]>,
1677 Requires<[In32BitMode]>;
1679 } // Defs = [EFLAGS]
1681 // Logical operators...
1682 let Defs = [EFLAGS] in {
1683 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1684 def AND8rr : I<0x20, MRMDestReg,
1685 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1686 "and{b}\t{$src2, $dst|$dst, $src2}",
1687 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
1688 (implicit EFLAGS)]>;
1689 def AND16rr : I<0x21, MRMDestReg,
1690 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1691 "and{w}\t{$src2, $dst|$dst, $src2}",
1692 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
1693 (implicit EFLAGS)]>, OpSize;
1694 def AND32rr : I<0x21, MRMDestReg,
1695 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1696 "and{l}\t{$src2, $dst|$dst, $src2}",
1697 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
1698 (implicit EFLAGS)]>;
1701 // AND instructions with the destination register in REG and the source register
1702 // in R/M. Included for the disassembler.
1703 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1704 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1705 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1706 (ins GR16:$src1, GR16:$src2),
1707 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1708 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1709 (ins GR32:$src1, GR32:$src2),
1710 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1712 def AND8rm : I<0x22, MRMSrcMem,
1713 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1714 "and{b}\t{$src2, $dst|$dst, $src2}",
1715 [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
1716 (implicit EFLAGS)]>;
1717 def AND16rm : I<0x23, MRMSrcMem,
1718 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1719 "and{w}\t{$src2, $dst|$dst, $src2}",
1720 [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
1721 (implicit EFLAGS)]>, OpSize;
1722 def AND32rm : I<0x23, MRMSrcMem,
1723 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1724 "and{l}\t{$src2, $dst|$dst, $src2}",
1725 [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
1726 (implicit EFLAGS)]>;
1728 def AND8ri : Ii8<0x80, MRM4r,
1729 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1730 "and{b}\t{$src2, $dst|$dst, $src2}",
1731 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
1732 (implicit EFLAGS)]>;
1733 def AND16ri : Ii16<0x81, MRM4r,
1734 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1735 "and{w}\t{$src2, $dst|$dst, $src2}",
1736 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
1737 (implicit EFLAGS)]>, OpSize;
1738 def AND32ri : Ii32<0x81, MRM4r,
1739 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1740 "and{l}\t{$src2, $dst|$dst, $src2}",
1741 [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
1742 (implicit EFLAGS)]>;
1743 def AND16ri8 : Ii8<0x83, MRM4r,
1744 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1745 "and{w}\t{$src2, $dst|$dst, $src2}",
1746 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
1747 (implicit EFLAGS)]>,
1749 def AND32ri8 : Ii8<0x83, MRM4r,
1750 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1751 "and{l}\t{$src2, $dst|$dst, $src2}",
1752 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
1753 (implicit EFLAGS)]>;
1755 let isTwoAddress = 0 in {
1756 def AND8mr : I<0x20, MRMDestMem,
1757 (outs), (ins i8mem :$dst, GR8 :$src),
1758 "and{b}\t{$src, $dst|$dst, $src}",
1759 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1760 (implicit EFLAGS)]>;
1761 def AND16mr : I<0x21, MRMDestMem,
1762 (outs), (ins i16mem:$dst, GR16:$src),
1763 "and{w}\t{$src, $dst|$dst, $src}",
1764 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1765 (implicit EFLAGS)]>,
1767 def AND32mr : I<0x21, MRMDestMem,
1768 (outs), (ins i32mem:$dst, GR32:$src),
1769 "and{l}\t{$src, $dst|$dst, $src}",
1770 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1771 (implicit EFLAGS)]>;
1772 def AND8mi : Ii8<0x80, MRM4m,
1773 (outs), (ins i8mem :$dst, i8imm :$src),
1774 "and{b}\t{$src, $dst|$dst, $src}",
1775 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1776 (implicit EFLAGS)]>;
1777 def AND16mi : Ii16<0x81, MRM4m,
1778 (outs), (ins i16mem:$dst, i16imm:$src),
1779 "and{w}\t{$src, $dst|$dst, $src}",
1780 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1781 (implicit EFLAGS)]>,
1783 def AND32mi : Ii32<0x81, MRM4m,
1784 (outs), (ins i32mem:$dst, i32imm:$src),
1785 "and{l}\t{$src, $dst|$dst, $src}",
1786 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1787 (implicit EFLAGS)]>;
1788 def AND16mi8 : Ii8<0x83, MRM4m,
1789 (outs), (ins i16mem:$dst, i16i8imm :$src),
1790 "and{w}\t{$src, $dst|$dst, $src}",
1791 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1792 (implicit EFLAGS)]>,
1794 def AND32mi8 : Ii8<0x83, MRM4m,
1795 (outs), (ins i32mem:$dst, i32i8imm :$src),
1796 "and{l}\t{$src, $dst|$dst, $src}",
1797 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1798 (implicit EFLAGS)]>;
1800 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1801 "and{b}\t{$src, %al|%al, $src}", []>;
1802 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1803 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1804 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1805 "and{l}\t{$src, %eax|%eax, $src}", []>;
1810 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1811 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1812 (ins GR8 :$src1, GR8 :$src2),
1813 "or{b}\t{$src2, $dst|$dst, $src2}",
1814 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
1815 (implicit EFLAGS)]>;
1816 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1817 (ins GR16:$src1, GR16:$src2),
1818 "or{w}\t{$src2, $dst|$dst, $src2}",
1819 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
1820 (implicit EFLAGS)]>, OpSize;
1821 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1822 (ins GR32:$src1, GR32:$src2),
1823 "or{l}\t{$src2, $dst|$dst, $src2}",
1824 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
1825 (implicit EFLAGS)]>;
1828 // OR instructions with the destination register in REG and the source register
1829 // in R/M. Included for the disassembler.
1830 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1831 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1832 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1833 (ins GR16:$src1, GR16:$src2),
1834 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1835 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1836 (ins GR32:$src1, GR32:$src2),
1837 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
1839 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst),
1840 (ins GR8 :$src1, i8mem :$src2),
1841 "or{b}\t{$src2, $dst|$dst, $src2}",
1842 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
1843 (implicit EFLAGS)]>;
1844 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst),
1845 (ins GR16:$src1, i16mem:$src2),
1846 "or{w}\t{$src2, $dst|$dst, $src2}",
1847 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
1848 (implicit EFLAGS)]>, OpSize;
1849 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst),
1850 (ins GR32:$src1, i32mem:$src2),
1851 "or{l}\t{$src2, $dst|$dst, $src2}",
1852 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
1853 (implicit EFLAGS)]>;
1855 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
1856 (ins GR8 :$src1, i8imm:$src2),
1857 "or{b}\t{$src2, $dst|$dst, $src2}",
1858 [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
1859 (implicit EFLAGS)]>;
1860 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
1861 (ins GR16:$src1, i16imm:$src2),
1862 "or{w}\t{$src2, $dst|$dst, $src2}",
1863 [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
1864 (implicit EFLAGS)]>, OpSize;
1865 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
1866 (ins GR32:$src1, i32imm:$src2),
1867 "or{l}\t{$src2, $dst|$dst, $src2}",
1868 [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
1869 (implicit EFLAGS)]>;
1871 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
1872 (ins GR16:$src1, i16i8imm:$src2),
1873 "or{w}\t{$src2, $dst|$dst, $src2}",
1874 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
1875 (implicit EFLAGS)]>, OpSize;
1876 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
1877 (ins GR32:$src1, i32i8imm:$src2),
1878 "or{l}\t{$src2, $dst|$dst, $src2}",
1879 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
1880 (implicit EFLAGS)]>;
1881 let isTwoAddress = 0 in {
1882 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1883 "or{b}\t{$src, $dst|$dst, $src}",
1884 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1885 (implicit EFLAGS)]>;
1886 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1887 "or{w}\t{$src, $dst|$dst, $src}",
1888 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1889 (implicit EFLAGS)]>, OpSize;
1890 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1891 "or{l}\t{$src, $dst|$dst, $src}",
1892 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1893 (implicit EFLAGS)]>;
1894 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1895 "or{b}\t{$src, $dst|$dst, $src}",
1896 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1897 (implicit EFLAGS)]>;
1898 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1899 "or{w}\t{$src, $dst|$dst, $src}",
1900 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1901 (implicit EFLAGS)]>,
1903 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1904 "or{l}\t{$src, $dst|$dst, $src}",
1905 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1906 (implicit EFLAGS)]>;
1907 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1908 "or{w}\t{$src, $dst|$dst, $src}",
1909 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1910 (implicit EFLAGS)]>,
1912 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1913 "or{l}\t{$src, $dst|$dst, $src}",
1914 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1915 (implicit EFLAGS)]>;
1917 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
1918 "or{b}\t{$src, %al|%al, $src}", []>;
1919 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
1920 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1921 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
1922 "or{l}\t{$src, %eax|%eax, $src}", []>;
1923 } // isTwoAddress = 0
1926 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1927 def XOR8rr : I<0x30, MRMDestReg,
1928 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1929 "xor{b}\t{$src2, $dst|$dst, $src2}",
1930 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
1931 (implicit EFLAGS)]>;
1932 def XOR16rr : I<0x31, MRMDestReg,
1933 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1934 "xor{w}\t{$src2, $dst|$dst, $src2}",
1935 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
1936 (implicit EFLAGS)]>, OpSize;
1937 def XOR32rr : I<0x31, MRMDestReg,
1938 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1939 "xor{l}\t{$src2, $dst|$dst, $src2}",
1940 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
1941 (implicit EFLAGS)]>;
1942 } // isCommutable = 1
1944 // XOR instructions with the destination register in REG and the source register
1945 // in R/M. Included for the disassembler.
1946 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1947 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
1948 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
1949 (ins GR16:$src1, GR16:$src2),
1950 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1951 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
1952 (ins GR32:$src1, GR32:$src2),
1953 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
1955 def XOR8rm : I<0x32, MRMSrcMem ,
1956 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1957 "xor{b}\t{$src2, $dst|$dst, $src2}",
1958 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
1959 (implicit EFLAGS)]>;
1960 def XOR16rm : I<0x33, MRMSrcMem ,
1961 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1962 "xor{w}\t{$src2, $dst|$dst, $src2}",
1963 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
1964 (implicit EFLAGS)]>,
1966 def XOR32rm : I<0x33, MRMSrcMem ,
1967 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1968 "xor{l}\t{$src2, $dst|$dst, $src2}",
1969 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
1970 (implicit EFLAGS)]>;
1972 def XOR8ri : Ii8<0x80, MRM6r,
1973 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1974 "xor{b}\t{$src2, $dst|$dst, $src2}",
1975 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
1976 (implicit EFLAGS)]>;
1977 def XOR16ri : Ii16<0x81, MRM6r,
1978 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1979 "xor{w}\t{$src2, $dst|$dst, $src2}",
1980 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
1981 (implicit EFLAGS)]>, OpSize;
1982 def XOR32ri : Ii32<0x81, MRM6r,
1983 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1984 "xor{l}\t{$src2, $dst|$dst, $src2}",
1985 [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
1986 (implicit EFLAGS)]>;
1987 def XOR16ri8 : Ii8<0x83, MRM6r,
1988 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1989 "xor{w}\t{$src2, $dst|$dst, $src2}",
1990 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
1991 (implicit EFLAGS)]>,
1993 def XOR32ri8 : Ii8<0x83, MRM6r,
1994 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1995 "xor{l}\t{$src2, $dst|$dst, $src2}",
1996 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
1997 (implicit EFLAGS)]>;
1999 let isTwoAddress = 0 in {
2000 def XOR8mr : I<0x30, MRMDestMem,
2001 (outs), (ins i8mem :$dst, GR8 :$src),
2002 "xor{b}\t{$src, $dst|$dst, $src}",
2003 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
2004 (implicit EFLAGS)]>;
2005 def XOR16mr : I<0x31, MRMDestMem,
2006 (outs), (ins i16mem:$dst, GR16:$src),
2007 "xor{w}\t{$src, $dst|$dst, $src}",
2008 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
2009 (implicit EFLAGS)]>,
2011 def XOR32mr : I<0x31, MRMDestMem,
2012 (outs), (ins i32mem:$dst, GR32:$src),
2013 "xor{l}\t{$src, $dst|$dst, $src}",
2014 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
2015 (implicit EFLAGS)]>;
2016 def XOR8mi : Ii8<0x80, MRM6m,
2017 (outs), (ins i8mem :$dst, i8imm :$src),
2018 "xor{b}\t{$src, $dst|$dst, $src}",
2019 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
2020 (implicit EFLAGS)]>;
2021 def XOR16mi : Ii16<0x81, MRM6m,
2022 (outs), (ins i16mem:$dst, i16imm:$src),
2023 "xor{w}\t{$src, $dst|$dst, $src}",
2024 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
2025 (implicit EFLAGS)]>,
2027 def XOR32mi : Ii32<0x81, MRM6m,
2028 (outs), (ins i32mem:$dst, i32imm:$src),
2029 "xor{l}\t{$src, $dst|$dst, $src}",
2030 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
2031 (implicit EFLAGS)]>;
2032 def XOR16mi8 : Ii8<0x83, MRM6m,
2033 (outs), (ins i16mem:$dst, i16i8imm :$src),
2034 "xor{w}\t{$src, $dst|$dst, $src}",
2035 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
2036 (implicit EFLAGS)]>,
2038 def XOR32mi8 : Ii8<0x83, MRM6m,
2039 (outs), (ins i32mem:$dst, i32i8imm :$src),
2040 "xor{l}\t{$src, $dst|$dst, $src}",
2041 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
2042 (implicit EFLAGS)]>;
2044 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
2045 "xor{b}\t{$src, %al|%al, $src}", []>;
2046 def XOR16i16 : Ii16 <0x35, RawFrm, (outs), (ins i16imm:$src),
2047 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2048 def XOR32i32 : Ii32 <0x35, RawFrm, (outs), (ins i32imm:$src),
2049 "xor{l}\t{$src, %eax|%eax, $src}", []>;
2050 } // isTwoAddress = 0
2051 } // Defs = [EFLAGS]
2053 // Shift instructions
2054 let Defs = [EFLAGS] in {
2055 let Uses = [CL] in {
2056 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
2057 "shl{b}\t{%cl, $dst|$dst, CL}",
2058 [(set GR8:$dst, (shl GR8:$src, CL))]>;
2059 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
2060 "shl{w}\t{%cl, $dst|$dst, CL}",
2061 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
2062 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
2063 "shl{l}\t{%cl, $dst|$dst, CL}",
2064 [(set GR32:$dst, (shl GR32:$src, CL))]>;
2067 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2068 "shl{b}\t{$src2, $dst|$dst, $src2}",
2069 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
2070 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2071 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2072 "shl{w}\t{$src2, $dst|$dst, $src2}",
2073 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2074 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2075 "shl{l}\t{$src2, $dst|$dst, $src2}",
2076 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
2078 // NOTE: We don't include patterns for shifts of a register by one, because
2079 // 'add reg,reg' is cheaper.
2081 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
2082 "shl{b}\t$dst", []>;
2083 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2084 "shl{w}\t$dst", []>, OpSize;
2085 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2086 "shl{l}\t$dst", []>;
2088 } // isConvertibleToThreeAddress = 1
2090 let isTwoAddress = 0 in {
2091 let Uses = [CL] in {
2092 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
2093 "shl{b}\t{%cl, $dst|$dst, CL}",
2094 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
2095 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
2096 "shl{w}\t{%cl, $dst|$dst, CL}",
2097 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2098 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
2099 "shl{l}\t{%cl, $dst|$dst, CL}",
2100 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
2102 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
2103 "shl{b}\t{$src, $dst|$dst, $src}",
2104 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2105 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
2106 "shl{w}\t{$src, $dst|$dst, $src}",
2107 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2109 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
2110 "shl{l}\t{$src, $dst|$dst, $src}",
2111 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2114 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
2116 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2117 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
2119 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2121 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2123 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2126 let Uses = [CL] in {
2127 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
2128 "shr{b}\t{%cl, $dst|$dst, CL}",
2129 [(set GR8:$dst, (srl GR8:$src, CL))]>;
2130 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
2131 "shr{w}\t{%cl, $dst|$dst, CL}",
2132 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
2133 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
2134 "shr{l}\t{%cl, $dst|$dst, CL}",
2135 [(set GR32:$dst, (srl GR32:$src, CL))]>;
2138 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2139 "shr{b}\t{$src2, $dst|$dst, $src2}",
2140 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2141 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2142 "shr{w}\t{$src2, $dst|$dst, $src2}",
2143 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2144 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2145 "shr{l}\t{$src2, $dst|$dst, $src2}",
2146 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2149 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2151 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2152 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2154 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2155 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2157 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2159 let isTwoAddress = 0 in {
2160 let Uses = [CL] in {
2161 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2162 "shr{b}\t{%cl, $dst|$dst, CL}",
2163 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2164 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2165 "shr{w}\t{%cl, $dst|$dst, CL}",
2166 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2168 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2169 "shr{l}\t{%cl, $dst|$dst, CL}",
2170 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2172 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2173 "shr{b}\t{$src, $dst|$dst, $src}",
2174 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2175 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2176 "shr{w}\t{$src, $dst|$dst, $src}",
2177 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2179 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2180 "shr{l}\t{$src, $dst|$dst, $src}",
2181 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2184 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2186 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2187 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2189 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2190 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2192 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2195 let Uses = [CL] in {
2196 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
2197 "sar{b}\t{%cl, $dst|$dst, CL}",
2198 [(set GR8:$dst, (sra GR8:$src, CL))]>;
2199 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
2200 "sar{w}\t{%cl, $dst|$dst, CL}",
2201 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
2202 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
2203 "sar{l}\t{%cl, $dst|$dst, CL}",
2204 [(set GR32:$dst, (sra GR32:$src, CL))]>;
2207 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2208 "sar{b}\t{$src2, $dst|$dst, $src2}",
2209 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2210 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2211 "sar{w}\t{$src2, $dst|$dst, $src2}",
2212 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2214 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2215 "sar{l}\t{$src2, $dst|$dst, $src2}",
2216 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2219 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2221 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2222 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2224 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2225 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2227 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2229 let isTwoAddress = 0 in {
2230 let Uses = [CL] in {
2231 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2232 "sar{b}\t{%cl, $dst|$dst, CL}",
2233 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2234 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2235 "sar{w}\t{%cl, $dst|$dst, CL}",
2236 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2237 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2238 "sar{l}\t{%cl, $dst|$dst, CL}",
2239 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2241 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2242 "sar{b}\t{$src, $dst|$dst, $src}",
2243 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2244 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2245 "sar{w}\t{$src, $dst|$dst, $src}",
2246 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2248 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2249 "sar{l}\t{$src, $dst|$dst, $src}",
2250 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2253 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2255 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2256 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2258 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2260 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2262 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2265 // Rotate instructions
2267 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2268 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2269 let Uses = [CL] in {
2270 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2271 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2273 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2274 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2276 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2277 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2278 let Uses = [CL] in {
2279 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2280 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2282 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2283 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2285 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2286 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2287 let Uses = [CL] in {
2288 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2289 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2291 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2292 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2294 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2295 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2296 let Uses = [CL] in {
2297 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2298 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2300 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2301 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2303 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2304 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2305 let Uses = [CL] in {
2306 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2307 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2309 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2310 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2312 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2313 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2314 let Uses = [CL] in {
2315 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2316 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2318 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2319 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2321 let isTwoAddress = 0 in {
2322 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
2323 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2324 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2325 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2326 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
2327 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2328 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2329 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2330 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
2331 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2332 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2333 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2334 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
2335 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2336 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2337 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2338 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
2339 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2340 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2341 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2342 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
2343 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2344 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2345 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2347 let Uses = [CL] in {
2348 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
2349 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2350 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
2351 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2352 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
2353 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2354 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
2355 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2356 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
2357 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2358 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
2359 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2363 // FIXME: provide shorter instructions when imm8 == 1
2364 let Uses = [CL] in {
2365 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
2366 "rol{b}\t{%cl, $dst|$dst, CL}",
2367 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
2368 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
2369 "rol{w}\t{%cl, $dst|$dst, CL}",
2370 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
2371 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
2372 "rol{l}\t{%cl, $dst|$dst, CL}",
2373 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2376 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2377 "rol{b}\t{$src2, $dst|$dst, $src2}",
2378 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2379 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2380 "rol{w}\t{$src2, $dst|$dst, $src2}",
2381 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2383 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2384 "rol{l}\t{$src2, $dst|$dst, $src2}",
2385 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2388 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2390 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2391 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2393 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2394 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2396 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2398 let isTwoAddress = 0 in {
2399 let Uses = [CL] in {
2400 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2401 "rol{b}\t{%cl, $dst|$dst, CL}",
2402 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2403 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2404 "rol{w}\t{%cl, $dst|$dst, CL}",
2405 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2406 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2407 "rol{l}\t{%cl, $dst|$dst, CL}",
2408 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2410 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2411 "rol{b}\t{$src, $dst|$dst, $src}",
2412 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2413 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2414 "rol{w}\t{$src, $dst|$dst, $src}",
2415 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2417 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2418 "rol{l}\t{$src, $dst|$dst, $src}",
2419 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2422 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2424 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2425 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2427 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2429 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2431 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2434 let Uses = [CL] in {
2435 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2436 "ror{b}\t{%cl, $dst|$dst, CL}",
2437 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2438 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2439 "ror{w}\t{%cl, $dst|$dst, CL}",
2440 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2441 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2442 "ror{l}\t{%cl, $dst|$dst, CL}",
2443 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2446 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2447 "ror{b}\t{$src2, $dst|$dst, $src2}",
2448 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2449 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2450 "ror{w}\t{$src2, $dst|$dst, $src2}",
2451 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2453 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2454 "ror{l}\t{$src2, $dst|$dst, $src2}",
2455 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2458 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2460 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2461 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2463 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2464 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2466 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2468 let isTwoAddress = 0 in {
2469 let Uses = [CL] in {
2470 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2471 "ror{b}\t{%cl, $dst|$dst, CL}",
2472 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2473 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2474 "ror{w}\t{%cl, $dst|$dst, CL}",
2475 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2476 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2477 "ror{l}\t{%cl, $dst|$dst, CL}",
2478 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2480 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2481 "ror{b}\t{$src, $dst|$dst, $src}",
2482 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2483 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2484 "ror{w}\t{$src, $dst|$dst, $src}",
2485 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2487 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2488 "ror{l}\t{$src, $dst|$dst, $src}",
2489 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2492 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2494 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2495 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2497 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2499 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2501 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2506 // Double shift instructions (generalizations of rotate)
2507 let Uses = [CL] in {
2508 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2509 (ins GR32:$src1, GR32:$src2),
2510 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2511 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2512 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2513 (ins GR32:$src1, GR32:$src2),
2514 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2515 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2516 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2517 (ins GR16:$src1, GR16:$src2),
2518 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2519 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2521 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2522 (ins GR16:$src1, GR16:$src2),
2523 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2524 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2528 let isCommutable = 1 in { // These instructions commute to each other.
2529 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2531 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2532 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2533 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2536 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2538 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2539 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2540 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2543 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2545 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2546 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2547 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2550 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2552 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2553 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2554 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2559 let isTwoAddress = 0 in {
2560 let Uses = [CL] in {
2561 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2562 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2563 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2565 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2566 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2567 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2570 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2571 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2572 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2573 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2574 (i8 imm:$src3)), addr:$dst)]>,
2576 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2577 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2578 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2579 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2580 (i8 imm:$src3)), addr:$dst)]>,
2583 let Uses = [CL] in {
2584 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2585 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2586 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2587 addr:$dst)]>, TB, OpSize;
2588 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2589 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2590 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2591 addr:$dst)]>, TB, OpSize;
2593 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2594 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2595 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2596 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2597 (i8 imm:$src3)), addr:$dst)]>,
2599 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2600 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2601 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2602 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2603 (i8 imm:$src3)), addr:$dst)]>,
2606 } // Defs = [EFLAGS]
2610 let Defs = [EFLAGS] in {
2611 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2612 // Register-Register Addition
2613 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2614 (ins GR8 :$src1, GR8 :$src2),
2615 "add{b}\t{$src2, $dst|$dst, $src2}",
2616 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
2617 (implicit EFLAGS)]>;
2619 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2620 // Register-Register Addition
2621 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2622 (ins GR16:$src1, GR16:$src2),
2623 "add{w}\t{$src2, $dst|$dst, $src2}",
2624 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2625 (implicit EFLAGS)]>, OpSize;
2626 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2627 (ins GR32:$src1, GR32:$src2),
2628 "add{l}\t{$src2, $dst|$dst, $src2}",
2629 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2630 (implicit EFLAGS)]>;
2631 } // end isConvertibleToThreeAddress
2632 } // end isCommutable
2634 // Register-Memory Addition
2635 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2636 (ins GR8 :$src1, i8mem :$src2),
2637 "add{b}\t{$src2, $dst|$dst, $src2}",
2638 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2639 (implicit EFLAGS)]>;
2640 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2641 (ins GR16:$src1, i16mem:$src2),
2642 "add{w}\t{$src2, $dst|$dst, $src2}",
2643 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2644 (implicit EFLAGS)]>, OpSize;
2645 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2646 (ins GR32:$src1, i32mem:$src2),
2647 "add{l}\t{$src2, $dst|$dst, $src2}",
2648 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2649 (implicit EFLAGS)]>;
2651 // Register-Register Addition - Equivalent to the normal rr forms (ADD8rr,
2652 // ADD16rr, and ADD32rr), but differently encoded.
2653 def ADD8mrmrr: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2654 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2655 def ADD16mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2656 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2657 def ADD32mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2658 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2660 // Register-Integer Addition
2661 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2662 "add{b}\t{$src2, $dst|$dst, $src2}",
2663 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2664 (implicit EFLAGS)]>;
2666 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2667 // Register-Integer Addition
2668 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2669 (ins GR16:$src1, i16imm:$src2),
2670 "add{w}\t{$src2, $dst|$dst, $src2}",
2671 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2672 (implicit EFLAGS)]>, OpSize;
2673 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2674 (ins GR32:$src1, i32imm:$src2),
2675 "add{l}\t{$src2, $dst|$dst, $src2}",
2676 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2677 (implicit EFLAGS)]>;
2678 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2679 (ins GR16:$src1, i16i8imm:$src2),
2680 "add{w}\t{$src2, $dst|$dst, $src2}",
2681 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2682 (implicit EFLAGS)]>, OpSize;
2683 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2684 (ins GR32:$src1, i32i8imm:$src2),
2685 "add{l}\t{$src2, $dst|$dst, $src2}",
2686 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2687 (implicit EFLAGS)]>;
2690 let isTwoAddress = 0 in {
2691 // Memory-Register Addition
2692 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2693 "add{b}\t{$src2, $dst|$dst, $src2}",
2694 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2695 (implicit EFLAGS)]>;
2696 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2697 "add{w}\t{$src2, $dst|$dst, $src2}",
2698 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2699 (implicit EFLAGS)]>, OpSize;
2700 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2701 "add{l}\t{$src2, $dst|$dst, $src2}",
2702 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2703 (implicit EFLAGS)]>;
2704 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2705 "add{b}\t{$src2, $dst|$dst, $src2}",
2706 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2707 (implicit EFLAGS)]>;
2708 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2709 "add{w}\t{$src2, $dst|$dst, $src2}",
2710 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2711 (implicit EFLAGS)]>, OpSize;
2712 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2713 "add{l}\t{$src2, $dst|$dst, $src2}",
2714 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2715 (implicit EFLAGS)]>;
2716 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2717 "add{w}\t{$src2, $dst|$dst, $src2}",
2718 [(store (add (load addr:$dst), i16immSExt8:$src2),
2720 (implicit EFLAGS)]>, OpSize;
2721 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2722 "add{l}\t{$src2, $dst|$dst, $src2}",
2723 [(store (add (load addr:$dst), i32immSExt8:$src2),
2725 (implicit EFLAGS)]>;
2728 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2729 "add{b}\t{$src, %al|%al, $src}", []>;
2730 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2731 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2732 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2733 "add{l}\t{$src, %eax|%eax, $src}", []>;
2736 let Uses = [EFLAGS] in {
2737 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2738 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2739 "adc{b}\t{$src2, $dst|$dst, $src2}",
2740 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2741 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2742 (ins GR16:$src1, GR16:$src2),
2743 "adc{w}\t{$src2, $dst|$dst, $src2}",
2744 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2745 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2746 (ins GR32:$src1, GR32:$src2),
2747 "adc{l}\t{$src2, $dst|$dst, $src2}",
2748 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2751 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2752 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2753 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2754 (ins GR16:$src1, GR16:$src2),
2755 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2756 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2757 (ins GR32:$src1, GR32:$src2),
2758 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2760 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2761 (ins GR8:$src1, i8mem:$src2),
2762 "adc{b}\t{$src2, $dst|$dst, $src2}",
2763 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2764 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2765 (ins GR16:$src1, i16mem:$src2),
2766 "adc{w}\t{$src2, $dst|$dst, $src2}",
2767 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2769 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2770 (ins GR32:$src1, i32mem:$src2),
2771 "adc{l}\t{$src2, $dst|$dst, $src2}",
2772 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2773 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2774 "adc{b}\t{$src2, $dst|$dst, $src2}",
2775 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2776 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2777 (ins GR16:$src1, i16imm:$src2),
2778 "adc{w}\t{$src2, $dst|$dst, $src2}",
2779 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2780 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2781 (ins GR16:$src1, i16i8imm:$src2),
2782 "adc{w}\t{$src2, $dst|$dst, $src2}",
2783 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2785 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2786 (ins GR32:$src1, i32imm:$src2),
2787 "adc{l}\t{$src2, $dst|$dst, $src2}",
2788 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2789 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2790 (ins GR32:$src1, i32i8imm:$src2),
2791 "adc{l}\t{$src2, $dst|$dst, $src2}",
2792 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2794 let isTwoAddress = 0 in {
2795 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2796 "adc{b}\t{$src2, $dst|$dst, $src2}",
2797 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2798 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2799 "adc{w}\t{$src2, $dst|$dst, $src2}",
2800 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2802 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2803 "adc{l}\t{$src2, $dst|$dst, $src2}",
2804 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2805 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2806 "adc{b}\t{$src2, $dst|$dst, $src2}",
2807 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2808 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2809 "adc{w}\t{$src2, $dst|$dst, $src2}",
2810 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2812 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2813 "adc{w}\t{$src2, $dst|$dst, $src2}",
2814 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2816 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2817 "adc{l}\t{$src2, $dst|$dst, $src2}",
2818 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2819 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2820 "adc{l}\t{$src2, $dst|$dst, $src2}",
2821 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2823 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2824 "adc{b}\t{$src, %al|%al, $src}", []>;
2825 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2826 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2827 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2828 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2830 } // Uses = [EFLAGS]
2832 // Register-Register Subtraction
2833 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2834 "sub{b}\t{$src2, $dst|$dst, $src2}",
2835 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2836 (implicit EFLAGS)]>;
2837 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2838 "sub{w}\t{$src2, $dst|$dst, $src2}",
2839 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2840 (implicit EFLAGS)]>, OpSize;
2841 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2842 "sub{l}\t{$src2, $dst|$dst, $src2}",
2843 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2844 (implicit EFLAGS)]>;
2846 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2847 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
2848 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
2849 (ins GR16:$src1, GR16:$src2),
2850 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2851 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
2852 (ins GR32:$src1, GR32:$src2),
2853 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
2855 // Register-Memory Subtraction
2856 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2857 (ins GR8 :$src1, i8mem :$src2),
2858 "sub{b}\t{$src2, $dst|$dst, $src2}",
2859 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2860 (implicit EFLAGS)]>;
2861 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2862 (ins GR16:$src1, i16mem:$src2),
2863 "sub{w}\t{$src2, $dst|$dst, $src2}",
2864 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2865 (implicit EFLAGS)]>, OpSize;
2866 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2867 (ins GR32:$src1, i32mem:$src2),
2868 "sub{l}\t{$src2, $dst|$dst, $src2}",
2869 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2870 (implicit EFLAGS)]>;
2872 // Register-Integer Subtraction
2873 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2874 (ins GR8:$src1, i8imm:$src2),
2875 "sub{b}\t{$src2, $dst|$dst, $src2}",
2876 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2877 (implicit EFLAGS)]>;
2878 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2879 (ins GR16:$src1, i16imm:$src2),
2880 "sub{w}\t{$src2, $dst|$dst, $src2}",
2881 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2882 (implicit EFLAGS)]>, OpSize;
2883 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2884 (ins GR32:$src1, i32imm:$src2),
2885 "sub{l}\t{$src2, $dst|$dst, $src2}",
2886 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2887 (implicit EFLAGS)]>;
2888 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2889 (ins GR16:$src1, i16i8imm:$src2),
2890 "sub{w}\t{$src2, $dst|$dst, $src2}",
2891 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2892 (implicit EFLAGS)]>, OpSize;
2893 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2894 (ins GR32:$src1, i32i8imm:$src2),
2895 "sub{l}\t{$src2, $dst|$dst, $src2}",
2896 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2897 (implicit EFLAGS)]>;
2899 let isTwoAddress = 0 in {
2900 // Memory-Register Subtraction
2901 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2902 "sub{b}\t{$src2, $dst|$dst, $src2}",
2903 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2904 (implicit EFLAGS)]>;
2905 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2906 "sub{w}\t{$src2, $dst|$dst, $src2}",
2907 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2908 (implicit EFLAGS)]>, OpSize;
2909 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2910 "sub{l}\t{$src2, $dst|$dst, $src2}",
2911 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2912 (implicit EFLAGS)]>;
2914 // Memory-Integer Subtraction
2915 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2916 "sub{b}\t{$src2, $dst|$dst, $src2}",
2917 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2918 (implicit EFLAGS)]>;
2919 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2920 "sub{w}\t{$src2, $dst|$dst, $src2}",
2921 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2922 (implicit EFLAGS)]>, OpSize;
2923 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2924 "sub{l}\t{$src2, $dst|$dst, $src2}",
2925 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2926 (implicit EFLAGS)]>;
2927 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2928 "sub{w}\t{$src2, $dst|$dst, $src2}",
2929 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2931 (implicit EFLAGS)]>, OpSize;
2932 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2933 "sub{l}\t{$src2, $dst|$dst, $src2}",
2934 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2936 (implicit EFLAGS)]>;
2938 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
2939 "sub{b}\t{$src, %al|%al, $src}", []>;
2940 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
2941 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2942 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
2943 "sub{l}\t{$src, %eax|%eax, $src}", []>;
2946 let Uses = [EFLAGS] in {
2947 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
2948 (ins GR8:$src1, GR8:$src2),
2949 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2950 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
2951 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
2952 (ins GR16:$src1, GR16:$src2),
2953 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2954 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
2955 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
2956 (ins GR32:$src1, GR32:$src2),
2957 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2958 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2960 let isTwoAddress = 0 in {
2961 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2962 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2963 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
2964 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2965 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2966 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
2968 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2969 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2970 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2971 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2972 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2973 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2974 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
2975 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2976 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2978 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2979 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2980 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2982 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2983 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2984 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2985 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2986 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2987 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2989 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
2990 "sbb{b}\t{$src, %al|%al, $src}", []>;
2991 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
2992 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2993 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
2994 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
2997 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2998 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
2999 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
3000 (ins GR16:$src1, GR16:$src2),
3001 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3002 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
3003 (ins GR32:$src1, GR32:$src2),
3004 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
3006 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
3007 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3008 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
3009 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
3010 (ins GR16:$src1, i16mem:$src2),
3011 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3012 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
3014 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
3015 (ins GR32:$src1, i32mem:$src2),
3016 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3017 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
3018 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
3019 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3020 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
3021 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
3022 (ins GR16:$src1, i16imm:$src2),
3023 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3024 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
3025 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
3026 (ins GR16:$src1, i16i8imm:$src2),
3027 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3028 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
3030 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
3031 (ins GR32:$src1, i32imm:$src2),
3032 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3033 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
3034 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
3035 (ins GR32:$src1, i32i8imm:$src2),
3036 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3037 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
3038 } // Uses = [EFLAGS]
3039 } // Defs = [EFLAGS]
3041 let Defs = [EFLAGS] in {
3042 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
3043 // Register-Register Signed Integer Multiply
3044 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3045 "imul{w}\t{$src2, $dst|$dst, $src2}",
3046 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
3047 (implicit EFLAGS)]>, TB, OpSize;
3048 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3049 "imul{l}\t{$src2, $dst|$dst, $src2}",
3050 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
3051 (implicit EFLAGS)]>, TB;
3054 // Register-Memory Signed Integer Multiply
3055 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
3056 (ins GR16:$src1, i16mem:$src2),
3057 "imul{w}\t{$src2, $dst|$dst, $src2}",
3058 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
3059 (implicit EFLAGS)]>, TB, OpSize;
3060 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
3061 (ins GR32:$src1, i32mem:$src2),
3062 "imul{l}\t{$src2, $dst|$dst, $src2}",
3063 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
3064 (implicit EFLAGS)]>, TB;
3065 } // Defs = [EFLAGS]
3066 } // end Two Address instructions
3068 // Suprisingly enough, these are not two address instructions!
3069 let Defs = [EFLAGS] in {
3070 // Register-Integer Signed Integer Multiply
3071 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
3072 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
3073 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3074 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
3075 (implicit EFLAGS)]>, OpSize;
3076 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
3077 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
3078 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3079 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
3080 (implicit EFLAGS)]>;
3081 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
3082 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
3083 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3084 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
3085 (implicit EFLAGS)]>, OpSize;
3086 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
3087 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
3088 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3089 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
3090 (implicit EFLAGS)]>;
3092 // Memory-Integer Signed Integer Multiply
3093 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
3094 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
3095 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3096 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
3097 (implicit EFLAGS)]>, OpSize;
3098 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
3099 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
3100 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3101 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
3102 (implicit EFLAGS)]>;
3103 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
3104 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
3105 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3106 [(set GR16:$dst, (mul (load addr:$src1),
3107 i16immSExt8:$src2)),
3108 (implicit EFLAGS)]>, OpSize;
3109 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
3110 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
3111 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3112 [(set GR32:$dst, (mul (load addr:$src1),
3113 i32immSExt8:$src2)),
3114 (implicit EFLAGS)]>;
3115 } // Defs = [EFLAGS]
3117 //===----------------------------------------------------------------------===//
3118 // Test instructions are just like AND, except they don't generate a result.
3120 let Defs = [EFLAGS] in {
3121 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
3122 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
3123 "test{b}\t{$src2, $src1|$src1, $src2}",
3124 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
3125 (implicit EFLAGS)]>;
3126 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3127 "test{w}\t{$src2, $src1|$src1, $src2}",
3128 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
3129 (implicit EFLAGS)]>,
3131 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3132 "test{l}\t{$src2, $src1|$src1, $src2}",
3133 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
3134 (implicit EFLAGS)]>;
3137 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
3138 "test{b}\t{$src, %al|%al, $src}", []>;
3139 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
3140 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3141 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
3142 "test{l}\t{$src, %eax|%eax, $src}", []>;
3144 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
3145 "test{b}\t{$src2, $src1|$src1, $src2}",
3146 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
3147 (implicit EFLAGS)]>;
3148 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
3149 "test{w}\t{$src2, $src1|$src1, $src2}",
3150 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
3151 (implicit EFLAGS)]>, OpSize;
3152 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
3153 "test{l}\t{$src2, $src1|$src1, $src2}",
3154 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
3155 (implicit EFLAGS)]>;
3157 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
3158 (outs), (ins GR8:$src1, i8imm:$src2),
3159 "test{b}\t{$src2, $src1|$src1, $src2}",
3160 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
3161 (implicit EFLAGS)]>;
3162 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
3163 (outs), (ins GR16:$src1, i16imm:$src2),
3164 "test{w}\t{$src2, $src1|$src1, $src2}",
3165 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
3166 (implicit EFLAGS)]>, OpSize;
3167 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
3168 (outs), (ins GR32:$src1, i32imm:$src2),
3169 "test{l}\t{$src2, $src1|$src1, $src2}",
3170 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
3171 (implicit EFLAGS)]>;
3173 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
3174 (outs), (ins i8mem:$src1, i8imm:$src2),
3175 "test{b}\t{$src2, $src1|$src1, $src2}",
3176 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
3177 (implicit EFLAGS)]>;
3178 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3179 (outs), (ins i16mem:$src1, i16imm:$src2),
3180 "test{w}\t{$src2, $src1|$src1, $src2}",
3181 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
3182 (implicit EFLAGS)]>, OpSize;
3183 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3184 (outs), (ins i32mem:$src1, i32imm:$src2),
3185 "test{l}\t{$src2, $src1|$src1, $src2}",
3186 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
3187 (implicit EFLAGS)]>;
3188 } // Defs = [EFLAGS]
3191 // Condition code ops, incl. set if equal/not equal/...
3192 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3193 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3194 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3195 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3197 let Uses = [EFLAGS] in {
3198 // Use sbb to materialize carry bit.
3199 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
3200 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
3201 // However, Pat<> can't replicate the destination reg into the inputs of the
3203 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
3205 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
3206 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3207 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
3208 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
3210 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
3211 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3214 def SETEr : I<0x94, MRM0r,
3215 (outs GR8 :$dst), (ins),
3217 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3219 def SETEm : I<0x94, MRM0m,
3220 (outs), (ins i8mem:$dst),
3222 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3225 def SETNEr : I<0x95, MRM0r,
3226 (outs GR8 :$dst), (ins),
3228 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3230 def SETNEm : I<0x95, MRM0m,
3231 (outs), (ins i8mem:$dst),
3233 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3236 def SETLr : I<0x9C, MRM0r,
3237 (outs GR8 :$dst), (ins),
3239 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3240 TB; // GR8 = < signed
3241 def SETLm : I<0x9C, MRM0m,
3242 (outs), (ins i8mem:$dst),
3244 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3245 TB; // [mem8] = < signed
3247 def SETGEr : I<0x9D, MRM0r,
3248 (outs GR8 :$dst), (ins),
3250 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3251 TB; // GR8 = >= signed
3252 def SETGEm : I<0x9D, MRM0m,
3253 (outs), (ins i8mem:$dst),
3255 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3256 TB; // [mem8] = >= signed
3258 def SETLEr : I<0x9E, MRM0r,
3259 (outs GR8 :$dst), (ins),
3261 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3262 TB; // GR8 = <= signed
3263 def SETLEm : I<0x9E, MRM0m,
3264 (outs), (ins i8mem:$dst),
3266 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3267 TB; // [mem8] = <= signed
3269 def SETGr : I<0x9F, MRM0r,
3270 (outs GR8 :$dst), (ins),
3272 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3273 TB; // GR8 = > signed
3274 def SETGm : I<0x9F, MRM0m,
3275 (outs), (ins i8mem:$dst),
3277 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3278 TB; // [mem8] = > signed
3280 def SETBr : I<0x92, MRM0r,
3281 (outs GR8 :$dst), (ins),
3283 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3284 TB; // GR8 = < unsign
3285 def SETBm : I<0x92, MRM0m,
3286 (outs), (ins i8mem:$dst),
3288 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3289 TB; // [mem8] = < unsign
3291 def SETAEr : I<0x93, MRM0r,
3292 (outs GR8 :$dst), (ins),
3294 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3295 TB; // GR8 = >= unsign
3296 def SETAEm : I<0x93, MRM0m,
3297 (outs), (ins i8mem:$dst),
3299 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3300 TB; // [mem8] = >= unsign
3302 def SETBEr : I<0x96, MRM0r,
3303 (outs GR8 :$dst), (ins),
3305 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3306 TB; // GR8 = <= unsign
3307 def SETBEm : I<0x96, MRM0m,
3308 (outs), (ins i8mem:$dst),
3310 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3311 TB; // [mem8] = <= unsign
3313 def SETAr : I<0x97, MRM0r,
3314 (outs GR8 :$dst), (ins),
3316 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3317 TB; // GR8 = > signed
3318 def SETAm : I<0x97, MRM0m,
3319 (outs), (ins i8mem:$dst),
3321 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3322 TB; // [mem8] = > signed
3324 def SETSr : I<0x98, MRM0r,
3325 (outs GR8 :$dst), (ins),
3327 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3328 TB; // GR8 = <sign bit>
3329 def SETSm : I<0x98, MRM0m,
3330 (outs), (ins i8mem:$dst),
3332 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3333 TB; // [mem8] = <sign bit>
3334 def SETNSr : I<0x99, MRM0r,
3335 (outs GR8 :$dst), (ins),
3337 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3338 TB; // GR8 = !<sign bit>
3339 def SETNSm : I<0x99, MRM0m,
3340 (outs), (ins i8mem:$dst),
3342 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3343 TB; // [mem8] = !<sign bit>
3345 def SETPr : I<0x9A, MRM0r,
3346 (outs GR8 :$dst), (ins),
3348 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3350 def SETPm : I<0x9A, MRM0m,
3351 (outs), (ins i8mem:$dst),
3353 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3354 TB; // [mem8] = parity
3355 def SETNPr : I<0x9B, MRM0r,
3356 (outs GR8 :$dst), (ins),
3358 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3359 TB; // GR8 = not parity
3360 def SETNPm : I<0x9B, MRM0m,
3361 (outs), (ins i8mem:$dst),
3363 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3364 TB; // [mem8] = not parity
3366 def SETOr : I<0x90, MRM0r,
3367 (outs GR8 :$dst), (ins),
3369 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3370 TB; // GR8 = overflow
3371 def SETOm : I<0x90, MRM0m,
3372 (outs), (ins i8mem:$dst),
3374 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3375 TB; // [mem8] = overflow
3376 def SETNOr : I<0x91, MRM0r,
3377 (outs GR8 :$dst), (ins),
3379 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3380 TB; // GR8 = not overflow
3381 def SETNOm : I<0x91, MRM0m,
3382 (outs), (ins i8mem:$dst),
3384 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3385 TB; // [mem8] = not overflow
3386 } // Uses = [EFLAGS]
3389 // Integer comparisons
3390 let Defs = [EFLAGS] in {
3391 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3392 "cmp{b}\t{$src, %al|%al, $src}", []>;
3393 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3394 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3395 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3396 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3398 def CMP8rr : I<0x38, MRMDestReg,
3399 (outs), (ins GR8 :$src1, GR8 :$src2),
3400 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3401 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
3402 def CMP16rr : I<0x39, MRMDestReg,
3403 (outs), (ins GR16:$src1, GR16:$src2),
3404 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3405 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
3406 def CMP32rr : I<0x39, MRMDestReg,
3407 (outs), (ins GR32:$src1, GR32:$src2),
3408 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3409 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
3410 def CMP8mr : I<0x38, MRMDestMem,
3411 (outs), (ins i8mem :$src1, GR8 :$src2),
3412 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3413 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
3414 (implicit EFLAGS)]>;
3415 def CMP16mr : I<0x39, MRMDestMem,
3416 (outs), (ins i16mem:$src1, GR16:$src2),
3417 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3418 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
3419 (implicit EFLAGS)]>, OpSize;
3420 def CMP32mr : I<0x39, MRMDestMem,
3421 (outs), (ins i32mem:$src1, GR32:$src2),
3422 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3423 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
3424 (implicit EFLAGS)]>;
3425 def CMP8rm : I<0x3A, MRMSrcMem,
3426 (outs), (ins GR8 :$src1, i8mem :$src2),
3427 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3428 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
3429 (implicit EFLAGS)]>;
3430 def CMP16rm : I<0x3B, MRMSrcMem,
3431 (outs), (ins GR16:$src1, i16mem:$src2),
3432 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3433 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
3434 (implicit EFLAGS)]>, OpSize;
3435 def CMP32rm : I<0x3B, MRMSrcMem,
3436 (outs), (ins GR32:$src1, i32mem:$src2),
3437 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3438 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
3439 (implicit EFLAGS)]>;
3440 def CMP8mrmrr : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3441 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3442 def CMP16mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3443 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3444 def CMP32mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3445 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3446 def CMP8ri : Ii8<0x80, MRM7r,
3447 (outs), (ins GR8:$src1, i8imm:$src2),
3448 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3449 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
3450 def CMP16ri : Ii16<0x81, MRM7r,
3451 (outs), (ins GR16:$src1, i16imm:$src2),
3452 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3453 [(X86cmp GR16:$src1, imm:$src2),
3454 (implicit EFLAGS)]>, OpSize;
3455 def CMP32ri : Ii32<0x81, MRM7r,
3456 (outs), (ins GR32:$src1, i32imm:$src2),
3457 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3458 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
3459 def CMP8mi : Ii8 <0x80, MRM7m,
3460 (outs), (ins i8mem :$src1, i8imm :$src2),
3461 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3462 [(X86cmp (loadi8 addr:$src1), imm:$src2),
3463 (implicit EFLAGS)]>;
3464 def CMP16mi : Ii16<0x81, MRM7m,
3465 (outs), (ins i16mem:$src1, i16imm:$src2),
3466 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3467 [(X86cmp (loadi16 addr:$src1), imm:$src2),
3468 (implicit EFLAGS)]>, OpSize;
3469 def CMP32mi : Ii32<0x81, MRM7m,
3470 (outs), (ins i32mem:$src1, i32imm:$src2),
3471 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3472 [(X86cmp (loadi32 addr:$src1), imm:$src2),
3473 (implicit EFLAGS)]>;
3474 def CMP16ri8 : Ii8<0x83, MRM7r,
3475 (outs), (ins GR16:$src1, i16i8imm:$src2),
3476 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3477 [(X86cmp GR16:$src1, i16immSExt8:$src2),
3478 (implicit EFLAGS)]>, OpSize;
3479 def CMP16mi8 : Ii8<0x83, MRM7m,
3480 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3481 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3482 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
3483 (implicit EFLAGS)]>, OpSize;
3484 def CMP32mi8 : Ii8<0x83, MRM7m,
3485 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3486 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3487 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
3488 (implicit EFLAGS)]>;
3489 def CMP32ri8 : Ii8<0x83, MRM7r,
3490 (outs), (ins GR32:$src1, i32i8imm:$src2),
3491 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3492 [(X86cmp GR32:$src1, i32immSExt8:$src2),
3493 (implicit EFLAGS)]>;
3494 } // Defs = [EFLAGS]
3497 // TODO: BTC, BTR, and BTS
3498 let Defs = [EFLAGS] in {
3499 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3500 "bt{w}\t{$src2, $src1|$src1, $src2}",
3501 [(X86bt GR16:$src1, GR16:$src2),
3502 (implicit EFLAGS)]>, OpSize, TB;
3503 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3504 "bt{l}\t{$src2, $src1|$src1, $src2}",
3505 [(X86bt GR32:$src1, GR32:$src2),
3506 (implicit EFLAGS)]>, TB;
3508 // Unlike with the register+register form, the memory+register form of the
3509 // bt instruction does not ignore the high bits of the index. From ISel's
3510 // perspective, this is pretty bizarre. Make these instructions disassembly
3513 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3514 "bt{w}\t{$src2, $src1|$src1, $src2}",
3515 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3516 // (implicit EFLAGS)]
3518 >, OpSize, TB, Requires<[FastBTMem]>;
3519 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3520 "bt{l}\t{$src2, $src1|$src1, $src2}",
3521 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3522 // (implicit EFLAGS)]
3524 >, TB, Requires<[FastBTMem]>;
3526 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3527 "bt{w}\t{$src2, $src1|$src1, $src2}",
3528 [(X86bt GR16:$src1, i16immSExt8:$src2),
3529 (implicit EFLAGS)]>, OpSize, TB;
3530 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3531 "bt{l}\t{$src2, $src1|$src1, $src2}",
3532 [(X86bt GR32:$src1, i32immSExt8:$src2),
3533 (implicit EFLAGS)]>, TB;
3534 // Note that these instructions don't need FastBTMem because that
3535 // only applies when the other operand is in a register. When it's
3536 // an immediate, bt is still fast.
3537 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3538 "bt{w}\t{$src2, $src1|$src1, $src2}",
3539 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
3540 (implicit EFLAGS)]>, OpSize, TB;
3541 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3542 "bt{l}\t{$src2, $src1|$src1, $src2}",
3543 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
3544 (implicit EFLAGS)]>, TB;
3546 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3547 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3548 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3549 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3550 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3551 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3552 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3553 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3554 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3555 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3556 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3557 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3558 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3559 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3560 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3561 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3563 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3564 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3565 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3566 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3567 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3568 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3569 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3570 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3571 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3572 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3573 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3574 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3575 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3576 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3577 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3578 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3580 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3581 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3582 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3583 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3584 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3585 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3586 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3587 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3588 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3589 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3590 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3591 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3592 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3593 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3594 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3595 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3596 } // Defs = [EFLAGS]
3598 // Sign/Zero extenders
3599 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3600 // of the register here. This has a smaller encoding and avoids a
3601 // partial-register update. Actual movsbw included for the disassembler.
3602 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3603 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3604 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3605 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3606 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3607 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3608 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3609 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3610 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3611 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3612 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3613 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3614 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3615 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3616 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3617 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3618 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3619 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3620 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3621 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3623 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3624 // of the register here. This has a smaller encoding and avoids a
3625 // partial-register update. Actual movzbw included for the disassembler.
3626 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3627 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3628 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3629 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3630 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3631 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3632 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3633 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3634 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3635 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3636 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3637 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3638 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3639 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3640 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3641 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3642 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3643 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3644 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3645 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3647 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
3648 // except that they use GR32_NOREX for the output operand register class
3649 // instead of GR32. This allows them to operate on h registers on x86-64.
3650 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3651 (outs GR32_NOREX:$dst), (ins GR8:$src),
3652 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3655 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3656 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3657 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3660 let neverHasSideEffects = 1 in {
3661 let Defs = [AX], Uses = [AL] in
3662 def CBW : I<0x98, RawFrm, (outs), (ins),
3663 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3664 let Defs = [EAX], Uses = [AX] in
3665 def CWDE : I<0x98, RawFrm, (outs), (ins),
3666 "{cwtl|cwde}", []>; // EAX = signext(AX)
3668 let Defs = [AX,DX], Uses = [AX] in
3669 def CWD : I<0x99, RawFrm, (outs), (ins),
3670 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3671 let Defs = [EAX,EDX], Uses = [EAX] in
3672 def CDQ : I<0x99, RawFrm, (outs), (ins),
3673 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3676 //===----------------------------------------------------------------------===//
3677 // Alias Instructions
3678 //===----------------------------------------------------------------------===//
3680 // Alias instructions that map movr0 to xor.
3681 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3682 // FIXME: Set encoding to pseudo.
3683 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3684 isCodeGenOnly = 1 in {
3685 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
3686 [(set GR8:$dst, 0)]>;
3688 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
3689 // encoding and avoids a partial-register update sometimes, but doing so
3690 // at isel time interferes with rematerialization in the current register
3691 // allocator. For now, this is rewritten when the instruction is lowered
3693 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3695 [(set GR16:$dst, 0)]>, OpSize;
3697 // FIXME: Set encoding to pseudo.
3698 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
3699 [(set GR32:$dst, 0)]>;
3702 //===----------------------------------------------------------------------===//
3703 // Thread Local Storage Instructions
3706 // All calls clobber the non-callee saved registers. ESP is marked as
3707 // a use to prevent stack-pointer assignments that appear immediately
3708 // before calls from potentially appearing dead.
3709 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3710 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3711 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3712 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3714 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3715 "leal\t$sym, %eax; "
3716 "call\t___tls_get_addr@PLT",
3717 [(X86tlsaddr tls32addr:$sym)]>,
3718 Requires<[In32BitMode]>;
3720 let AddedComplexity = 5, isCodeGenOnly = 1 in
3721 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3722 "movl\t%gs:$src, $dst",
3723 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3725 let AddedComplexity = 5, isCodeGenOnly = 1 in
3726 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3727 "movl\t%fs:$src, $dst",
3728 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3730 //===----------------------------------------------------------------------===//
3731 // EH Pseudo Instructions
3733 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3734 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3735 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3736 "ret\t#eh_return, addr: $addr",
3737 [(X86ehret GR32:$addr)]>;
3741 //===----------------------------------------------------------------------===//
3745 // Atomic swap. These are just normal xchg instructions. But since a memory
3746 // operand is referenced, the atomicity is ensured.
3747 let Constraints = "$val = $dst" in {
3748 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3749 (ins GR32:$val, i32mem:$ptr),
3750 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3751 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3752 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3753 (ins GR16:$val, i16mem:$ptr),
3754 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3755 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3757 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3758 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3759 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3761 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3762 "xchg{l}\t{$val, $src|$src, $val}", []>;
3763 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3764 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3765 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3766 "xchg{b}\t{$val, $src|$src, $val}", []>;
3769 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3770 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3771 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3772 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
3774 // Atomic compare and swap.
3775 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3776 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3778 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3779 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3781 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3782 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
3785 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3788 let Defs = [AX, EFLAGS], Uses = [AX] in {
3789 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3791 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3792 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3794 let Defs = [AL, EFLAGS], Uses = [AL] in {
3795 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3797 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3798 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3801 // Atomic exchange and add
3802 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3803 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
3805 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3806 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3808 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
3810 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3811 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3813 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3815 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3816 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3820 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3821 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3822 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3823 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3824 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3825 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3827 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3828 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3829 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3830 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3831 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3832 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3834 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3835 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3836 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3837 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3838 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3839 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3841 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3842 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3843 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3844 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3845 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3846 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3848 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
3849 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
3850 "cmpxchg8b\t$dst", []>, TB;
3852 // Optimized codegen when the non-memory output is not used.
3853 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3854 let Defs = [EFLAGS] in {
3855 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3857 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3858 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3860 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3861 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3863 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3864 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3866 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3867 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3869 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3870 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3872 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3873 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3875 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3876 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3878 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3880 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3882 "inc{b}\t$dst", []>, LOCK;
3883 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3885 "inc{w}\t$dst", []>, OpSize, LOCK;
3886 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3888 "inc{l}\t$dst", []>, LOCK;
3890 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3892 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3893 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3895 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3896 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3898 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3899 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3901 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3902 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3904 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3905 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3907 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3908 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3910 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3911 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3913 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3915 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3917 "dec{b}\t$dst", []>, LOCK;
3918 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3920 "dec{w}\t$dst", []>, OpSize, LOCK;
3921 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3923 "dec{l}\t$dst", []>, LOCK;
3926 // Atomic exchange, and, or, xor
3927 let Constraints = "$val = $dst", Defs = [EFLAGS],
3928 usesCustomInserter = 1 in {
3929 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3930 "#ATOMAND32 PSEUDO!",
3931 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3932 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3933 "#ATOMOR32 PSEUDO!",
3934 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
3935 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3936 "#ATOMXOR32 PSEUDO!",
3937 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
3938 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3939 "#ATOMNAND32 PSEUDO!",
3940 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
3941 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3942 "#ATOMMIN32 PSEUDO!",
3943 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
3944 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3945 "#ATOMMAX32 PSEUDO!",
3946 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
3947 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3948 "#ATOMUMIN32 PSEUDO!",
3949 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
3950 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3951 "#ATOMUMAX32 PSEUDO!",
3952 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
3954 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3955 "#ATOMAND16 PSEUDO!",
3956 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
3957 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3958 "#ATOMOR16 PSEUDO!",
3959 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
3960 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3961 "#ATOMXOR16 PSEUDO!",
3962 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
3963 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3964 "#ATOMNAND16 PSEUDO!",
3965 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
3966 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3967 "#ATOMMIN16 PSEUDO!",
3968 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
3969 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3970 "#ATOMMAX16 PSEUDO!",
3971 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
3972 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3973 "#ATOMUMIN16 PSEUDO!",
3974 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
3975 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3976 "#ATOMUMAX16 PSEUDO!",
3977 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
3979 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3980 "#ATOMAND8 PSEUDO!",
3981 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
3982 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3984 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
3985 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3986 "#ATOMXOR8 PSEUDO!",
3987 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
3988 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3989 "#ATOMNAND8 PSEUDO!",
3990 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
3993 let Constraints = "$val1 = $dst1, $val2 = $dst2",
3994 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
3995 Uses = [EAX, EBX, ECX, EDX],
3996 mayLoad = 1, mayStore = 1,
3997 usesCustomInserter = 1 in {
3998 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3999 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4000 "#ATOMAND6432 PSEUDO!", []>;
4001 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4002 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4003 "#ATOMOR6432 PSEUDO!", []>;
4004 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4005 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4006 "#ATOMXOR6432 PSEUDO!", []>;
4007 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4008 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4009 "#ATOMNAND6432 PSEUDO!", []>;
4010 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4011 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4012 "#ATOMADD6432 PSEUDO!", []>;
4013 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4014 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4015 "#ATOMSUB6432 PSEUDO!", []>;
4016 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4017 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4018 "#ATOMSWAP6432 PSEUDO!", []>;
4021 // Segmentation support instructions.
4023 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4024 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4025 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4026 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4028 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
4029 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
4030 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4031 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4032 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4034 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4035 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4036 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4037 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4038 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4039 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4040 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4041 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4043 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
4045 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
4046 "str{w}\t{$dst}", []>, TB;
4047 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
4048 "str{w}\t{$dst}", []>, TB;
4049 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
4050 "ltr{w}\t{$src}", []>, TB;
4051 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
4052 "ltr{w}\t{$src}", []>, TB;
4054 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
4055 "push{w}\t%fs", []>, OpSize, TB;
4056 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
4057 "push{l}\t%fs", []>, TB;
4058 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
4059 "push{w}\t%gs", []>, OpSize, TB;
4060 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
4061 "push{l}\t%gs", []>, TB;
4063 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
4064 "pop{w}\t%fs", []>, OpSize, TB;
4065 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
4066 "pop{l}\t%fs", []>, TB;
4067 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
4068 "pop{w}\t%gs", []>, OpSize, TB;
4069 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
4070 "pop{l}\t%gs", []>, TB;
4072 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4073 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4074 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4075 "lds{l}\t{$src, $dst|$dst, $src}", []>;
4076 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4077 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4078 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4079 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
4080 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4081 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4082 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4083 "les{l}\t{$src, $dst|$dst, $src}", []>;
4084 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4085 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4086 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4087 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4088 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4089 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4090 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4091 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4093 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
4094 "verr\t$seg", []>, TB;
4095 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
4096 "verr\t$seg", []>, TB;
4097 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
4098 "verw\t$seg", []>, TB;
4099 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
4100 "verw\t$seg", []>, TB;
4102 // Descriptor-table support instructions
4104 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
4105 "sgdt\t$dst", []>, TB;
4106 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
4107 "sidt\t$dst", []>, TB;
4108 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
4109 "sldt{w}\t$dst", []>, TB;
4110 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
4111 "sldt{w}\t$dst", []>, TB;
4112 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
4113 "lgdt\t$src", []>, TB;
4114 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
4115 "lidt\t$src", []>, TB;
4116 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
4117 "lldt{w}\t$src", []>, TB;
4118 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
4119 "lldt{w}\t$src", []>, TB;
4121 // Lock instruction prefix
4122 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
4124 // Repeat string operation instruction prefixes
4125 // These uses the DF flag in the EFLAGS register to inc or dec ECX
4126 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
4127 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
4128 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
4129 // Repeat while not equal (used with CMPS and SCAS)
4130 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
4133 // Segment override instruction prefixes
4134 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
4135 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
4136 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
4137 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
4138 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
4139 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
4141 // String manipulation instructions
4143 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
4144 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
4145 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
4147 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
4148 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
4149 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
4151 // CPU flow control instructions
4153 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
4154 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
4156 // FPU control instructions
4158 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
4160 // Flag instructions
4162 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
4163 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
4164 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
4165 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
4166 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
4167 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
4168 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
4170 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
4172 // Table lookup instructions
4174 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
4176 // Specialized register support
4178 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
4179 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
4180 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
4182 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
4183 "smsw{w}\t$dst", []>, OpSize, TB;
4184 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
4185 "smsw{l}\t$dst", []>, TB;
4186 // For memory operands, there is only a 16-bit form
4187 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
4188 "smsw{w}\t$dst", []>, TB;
4190 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
4191 "lmsw{w}\t$src", []>, TB;
4192 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
4193 "lmsw{w}\t$src", []>, TB;
4195 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
4197 // Cache instructions
4199 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
4200 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
4205 def INVEPT : I<0x80, RawFrm, (outs), (ins), "invept", []>, OpSize, T8;
4207 def INVVPID : I<0x81, RawFrm, (outs), (ins), "invvpid", []>, OpSize, T8;
4209 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
4210 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4211 "vmclear\t$vmcs", []>, OpSize, TB;
4213 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
4215 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
4216 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4217 "vmptrld\t$vmcs", []>, TB;
4218 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4219 "vmptrst\t$vmcs", []>, TB;
4220 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
4221 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4222 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
4223 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4224 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
4225 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4226 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4227 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4228 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4229 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4230 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4231 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4232 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4233 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4234 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4235 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4237 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
4238 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
4239 "vmxon\t{$vmxon}", []>, XD;
4241 //===----------------------------------------------------------------------===//
4242 // Non-Instruction Patterns
4243 //===----------------------------------------------------------------------===//
4245 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
4246 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
4247 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
4248 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
4249 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
4250 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
4251 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
4253 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
4254 (ADD32ri GR32:$src1, tconstpool:$src2)>;
4255 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
4256 (ADD32ri GR32:$src1, tjumptable:$src2)>;
4257 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
4258 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
4259 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
4260 (ADD32ri GR32:$src1, texternalsym:$src2)>;
4261 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
4262 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
4264 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
4265 (MOV32mi addr:$dst, tglobaladdr:$src)>;
4266 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
4267 (MOV32mi addr:$dst, texternalsym:$src)>;
4268 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
4269 (MOV32mi addr:$dst, tblockaddress:$src)>;
4273 def : Pat<(X86tcret GR32:$dst, imm:$off),
4274 (TCRETURNri GR32:$dst, imm:$off)>;
4276 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
4277 (TCRETURNdi texternalsym:$dst, imm:$off)>;
4279 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
4280 (TCRETURNdi texternalsym:$dst, imm:$off)>;
4282 // Normal calls, with various flavors of addresses.
4283 def : Pat<(X86call (i32 tglobaladdr:$dst)),
4284 (CALLpcrel32 tglobaladdr:$dst)>;
4285 def : Pat<(X86call (i32 texternalsym:$dst)),
4286 (CALLpcrel32 texternalsym:$dst)>;
4287 def : Pat<(X86call (i32 imm:$dst)),
4288 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
4290 // X86 specific add which produces a flag.
4291 def : Pat<(addc GR32:$src1, GR32:$src2),
4292 (ADD32rr GR32:$src1, GR32:$src2)>;
4293 def : Pat<(addc GR32:$src1, (load addr:$src2)),
4294 (ADD32rm GR32:$src1, addr:$src2)>;
4295 def : Pat<(addc GR32:$src1, imm:$src2),
4296 (ADD32ri GR32:$src1, imm:$src2)>;
4297 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
4298 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4300 def : Pat<(subc GR32:$src1, GR32:$src2),
4301 (SUB32rr GR32:$src1, GR32:$src2)>;
4302 def : Pat<(subc GR32:$src1, (load addr:$src2)),
4303 (SUB32rm GR32:$src1, addr:$src2)>;
4304 def : Pat<(subc GR32:$src1, imm:$src2),
4305 (SUB32ri GR32:$src1, imm:$src2)>;
4306 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
4307 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4311 // TEST R,R is smaller than CMP R,0
4312 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
4313 (TEST8rr GR8:$src1, GR8:$src1)>;
4314 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
4315 (TEST16rr GR16:$src1, GR16:$src1)>;
4316 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
4317 (TEST32rr GR32:$src1, GR32:$src1)>;
4319 // Conditional moves with folded loads with operands swapped and conditions
4321 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
4322 (CMOVAE16rm GR16:$src2, addr:$src1)>;
4323 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
4324 (CMOVAE32rm GR32:$src2, addr:$src1)>;
4325 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
4326 (CMOVB16rm GR16:$src2, addr:$src1)>;
4327 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
4328 (CMOVB32rm GR32:$src2, addr:$src1)>;
4329 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
4330 (CMOVNE16rm GR16:$src2, addr:$src1)>;
4331 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
4332 (CMOVNE32rm GR32:$src2, addr:$src1)>;
4333 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
4334 (CMOVE16rm GR16:$src2, addr:$src1)>;
4335 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
4336 (CMOVE32rm GR32:$src2, addr:$src1)>;
4337 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
4338 (CMOVA16rm GR16:$src2, addr:$src1)>;
4339 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
4340 (CMOVA32rm GR32:$src2, addr:$src1)>;
4341 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
4342 (CMOVBE16rm GR16:$src2, addr:$src1)>;
4343 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
4344 (CMOVBE32rm GR32:$src2, addr:$src1)>;
4345 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
4346 (CMOVGE16rm GR16:$src2, addr:$src1)>;
4347 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
4348 (CMOVGE32rm GR32:$src2, addr:$src1)>;
4349 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
4350 (CMOVL16rm GR16:$src2, addr:$src1)>;
4351 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
4352 (CMOVL32rm GR32:$src2, addr:$src1)>;
4353 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
4354 (CMOVG16rm GR16:$src2, addr:$src1)>;
4355 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
4356 (CMOVG32rm GR32:$src2, addr:$src1)>;
4357 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
4358 (CMOVLE16rm GR16:$src2, addr:$src1)>;
4359 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
4360 (CMOVLE32rm GR32:$src2, addr:$src1)>;
4361 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
4362 (CMOVNP16rm GR16:$src2, addr:$src1)>;
4363 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
4364 (CMOVNP32rm GR32:$src2, addr:$src1)>;
4365 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
4366 (CMOVP16rm GR16:$src2, addr:$src1)>;
4367 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
4368 (CMOVP32rm GR32:$src2, addr:$src1)>;
4369 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
4370 (CMOVNS16rm GR16:$src2, addr:$src1)>;
4371 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
4372 (CMOVNS32rm GR32:$src2, addr:$src1)>;
4373 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
4374 (CMOVS16rm GR16:$src2, addr:$src1)>;
4375 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
4376 (CMOVS32rm GR32:$src2, addr:$src1)>;
4377 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
4378 (CMOVNO16rm GR16:$src2, addr:$src1)>;
4379 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
4380 (CMOVNO32rm GR32:$src2, addr:$src1)>;
4381 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
4382 (CMOVO16rm GR16:$src2, addr:$src1)>;
4383 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
4384 (CMOVO32rm GR32:$src2, addr:$src1)>;
4386 // zextload bool -> zextload byte
4387 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4388 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4389 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4391 // extload bool -> extload byte
4392 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4393 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4394 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4395 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
4396 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
4397 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
4399 // anyext. Define these to do an explicit zero-extend to
4400 // avoid partial-register updates.
4401 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
4402 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
4403 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
4405 //===----------------------------------------------------------------------===//
4407 //===----------------------------------------------------------------------===//
4409 // Odd encoding trick: -128 fits into an 8-bit immediate field while
4410 // +128 doesn't, so in this special case use a sub instead of an add.
4411 def : Pat<(add GR16:$src1, 128),
4412 (SUB16ri8 GR16:$src1, -128)>;
4413 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
4414 (SUB16mi8 addr:$dst, -128)>;
4415 def : Pat<(add GR32:$src1, 128),
4416 (SUB32ri8 GR32:$src1, -128)>;
4417 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
4418 (SUB32mi8 addr:$dst, -128)>;
4420 // r & (2^16-1) ==> movz
4421 def : Pat<(and GR32:$src1, 0xffff),
4422 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
4423 // r & (2^8-1) ==> movz
4424 def : Pat<(and GR32:$src1, 0xff),
4425 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
4428 Requires<[In32BitMode]>;
4429 // r & (2^8-1) ==> movz
4430 def : Pat<(and GR16:$src1, 0xff),
4431 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
4434 Requires<[In32BitMode]>;
4436 // sext_inreg patterns
4437 def : Pat<(sext_inreg GR32:$src, i16),
4438 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
4439 def : Pat<(sext_inreg GR32:$src, i8),
4440 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4443 Requires<[In32BitMode]>;
4444 def : Pat<(sext_inreg GR16:$src, i8),
4445 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4448 Requires<[In32BitMode]>;
4451 def : Pat<(i16 (trunc GR32:$src)),
4452 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
4453 def : Pat<(i8 (trunc GR32:$src)),
4454 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4456 Requires<[In32BitMode]>;
4457 def : Pat<(i8 (trunc GR16:$src)),
4458 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4460 Requires<[In32BitMode]>;
4462 // h-register tricks
4463 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
4464 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4465 x86_subreg_8bit_hi)>,
4466 Requires<[In32BitMode]>;
4467 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
4468 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4469 x86_subreg_8bit_hi)>,
4470 Requires<[In32BitMode]>;
4471 def : Pat<(srl GR16:$src, (i8 8)),
4474 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4475 x86_subreg_8bit_hi)),
4477 Requires<[In32BitMode]>;
4478 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4479 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4481 x86_subreg_8bit_hi))>,
4482 Requires<[In32BitMode]>;
4483 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4484 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4486 x86_subreg_8bit_hi))>,
4487 Requires<[In32BitMode]>;
4488 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4489 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4491 x86_subreg_8bit_hi))>,
4492 Requires<[In32BitMode]>;
4494 // (shl x, 1) ==> (add x, x)
4495 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
4496 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
4497 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
4499 // (shl x (and y, 31)) ==> (shl x, y)
4500 def : Pat<(shl GR8:$src1, (and CL, 31)),
4501 (SHL8rCL GR8:$src1)>;
4502 def : Pat<(shl GR16:$src1, (and CL, 31)),
4503 (SHL16rCL GR16:$src1)>;
4504 def : Pat<(shl GR32:$src1, (and CL, 31)),
4505 (SHL32rCL GR32:$src1)>;
4506 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4507 (SHL8mCL addr:$dst)>;
4508 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4509 (SHL16mCL addr:$dst)>;
4510 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4511 (SHL32mCL addr:$dst)>;
4513 def : Pat<(srl GR8:$src1, (and CL, 31)),
4514 (SHR8rCL GR8:$src1)>;
4515 def : Pat<(srl GR16:$src1, (and CL, 31)),
4516 (SHR16rCL GR16:$src1)>;
4517 def : Pat<(srl GR32:$src1, (and CL, 31)),
4518 (SHR32rCL GR32:$src1)>;
4519 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4520 (SHR8mCL addr:$dst)>;
4521 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4522 (SHR16mCL addr:$dst)>;
4523 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4524 (SHR32mCL addr:$dst)>;
4526 def : Pat<(sra GR8:$src1, (and CL, 31)),
4527 (SAR8rCL GR8:$src1)>;
4528 def : Pat<(sra GR16:$src1, (and CL, 31)),
4529 (SAR16rCL GR16:$src1)>;
4530 def : Pat<(sra GR32:$src1, (and CL, 31)),
4531 (SAR32rCL GR32:$src1)>;
4532 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4533 (SAR8mCL addr:$dst)>;
4534 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4535 (SAR16mCL addr:$dst)>;
4536 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4537 (SAR32mCL addr:$dst)>;
4539 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
4540 def : Pat<(or (srl GR32:$src1, CL:$amt),
4541 (shl GR32:$src2, (sub 32, CL:$amt))),
4542 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4544 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
4545 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4546 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4548 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
4549 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4550 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4552 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4553 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4555 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4557 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm/*:$amt2*/)),
4558 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4560 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
4561 GR32:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4562 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4564 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
4565 def : Pat<(or (shl GR32:$src1, CL:$amt),
4566 (srl GR32:$src2, (sub 32, CL:$amt))),
4567 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4569 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
4570 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4571 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4573 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
4574 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4575 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4577 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4578 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4580 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4582 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm/*:$amt2*/)),
4583 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4585 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
4586 GR32:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4587 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4589 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
4590 def : Pat<(or (srl GR16:$src1, CL:$amt),
4591 (shl GR16:$src2, (sub 16, CL:$amt))),
4592 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4594 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
4595 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4596 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4598 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
4599 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4600 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4602 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4603 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4605 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4607 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm/*:$amt2*/)),
4608 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4610 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
4611 GR16:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4612 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4614 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
4615 def : Pat<(or (shl GR16:$src1, CL:$amt),
4616 (srl GR16:$src2, (sub 16, CL:$amt))),
4617 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4619 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
4620 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4621 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4623 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
4624 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4625 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4627 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4628 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4630 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4632 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm/*:$amt2*/)),
4633 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4635 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
4636 GR16:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4637 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4639 // (anyext (setcc_carry)) -> (setcc_carry)
4640 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4642 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4645 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
4646 let AddedComplexity = 5 in { // Try this before the selecting to OR
4647 def : Pat<(parallel (or_is_add GR16:$src1, imm:$src2),
4649 (ADD16ri GR16:$src1, imm:$src2)>;
4650 def : Pat<(parallel (or_is_add GR32:$src1, imm:$src2),
4652 (ADD32ri GR32:$src1, imm:$src2)>;
4653 def : Pat<(parallel (or_is_add GR16:$src1, i16immSExt8:$src2),
4655 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4656 def : Pat<(parallel (or_is_add GR32:$src1, i32immSExt8:$src2),
4658 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4659 def : Pat<(parallel (or_is_add GR16:$src1, GR16:$src2),
4661 (ADD16rr GR16:$src1, GR16:$src2)>;
4662 def : Pat<(parallel (or_is_add GR32:$src1, GR32:$src2),
4664 (ADD32rr GR32:$src1, GR32:$src2)>;
4665 } // AddedComplexity
4667 //===----------------------------------------------------------------------===//
4668 // EFLAGS-defining Patterns
4669 //===----------------------------------------------------------------------===//
4671 // Register-Register Addition with EFLAGS result
4672 def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
4674 (ADD8rr GR8:$src1, GR8:$src2)>;
4675 def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
4677 (ADD16rr GR16:$src1, GR16:$src2)>;
4678 def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
4680 (ADD32rr GR32:$src1, GR32:$src2)>;
4682 // Register-Memory Addition with EFLAGS result
4683 def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
4685 (ADD8rm GR8:$src1, addr:$src2)>;
4686 def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
4688 (ADD16rm GR16:$src1, addr:$src2)>;
4689 def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
4691 (ADD32rm GR32:$src1, addr:$src2)>;
4693 // Register-Integer Addition with EFLAGS result
4694 def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
4696 (ADD8ri GR8:$src1, imm:$src2)>;
4697 def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
4699 (ADD16ri GR16:$src1, imm:$src2)>;
4700 def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
4702 (ADD32ri GR32:$src1, imm:$src2)>;
4703 def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
4705 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4706 def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
4708 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4710 // Memory-Register Addition with EFLAGS result
4711 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
4714 (ADD8mr addr:$dst, GR8:$src2)>;
4715 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
4718 (ADD16mr addr:$dst, GR16:$src2)>;
4719 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
4722 (ADD32mr addr:$dst, GR32:$src2)>;
4724 // Memory-Integer Addition with EFLAGS result
4725 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
4728 (ADD8mi addr:$dst, imm:$src2)>;
4729 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
4732 (ADD16mi addr:$dst, imm:$src2)>;
4733 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
4736 (ADD32mi addr:$dst, imm:$src2)>;
4737 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4740 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
4741 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4744 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
4746 // Register-Register Subtraction with EFLAGS result
4747 def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
4749 (SUB8rr GR8:$src1, GR8:$src2)>;
4750 def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
4752 (SUB16rr GR16:$src1, GR16:$src2)>;
4753 def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
4755 (SUB32rr GR32:$src1, GR32:$src2)>;
4757 // Register-Memory Subtraction with EFLAGS result
4758 def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
4760 (SUB8rm GR8:$src1, addr:$src2)>;
4761 def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
4763 (SUB16rm GR16:$src1, addr:$src2)>;
4764 def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
4766 (SUB32rm GR32:$src1, addr:$src2)>;
4768 // Register-Integer Subtraction with EFLAGS result
4769 def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
4771 (SUB8ri GR8:$src1, imm:$src2)>;
4772 def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
4774 (SUB16ri GR16:$src1, imm:$src2)>;
4775 def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
4777 (SUB32ri GR32:$src1, imm:$src2)>;
4778 def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
4780 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4781 def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
4783 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4785 // Memory-Register Subtraction with EFLAGS result
4786 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
4789 (SUB8mr addr:$dst, GR8:$src2)>;
4790 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
4793 (SUB16mr addr:$dst, GR16:$src2)>;
4794 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
4797 (SUB32mr addr:$dst, GR32:$src2)>;
4799 // Memory-Integer Subtraction with EFLAGS result
4800 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
4803 (SUB8mi addr:$dst, imm:$src2)>;
4804 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
4807 (SUB16mi addr:$dst, imm:$src2)>;
4808 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
4811 (SUB32mi addr:$dst, imm:$src2)>;
4812 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4815 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
4816 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4819 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
4822 // Register-Register Signed Integer Multiply with EFLAGS result
4823 def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
4825 (IMUL16rr GR16:$src1, GR16:$src2)>;
4826 def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
4828 (IMUL32rr GR32:$src1, GR32:$src2)>;
4830 // Register-Memory Signed Integer Multiply with EFLAGS result
4831 def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
4833 (IMUL16rm GR16:$src1, addr:$src2)>;
4834 def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
4836 (IMUL32rm GR32:$src1, addr:$src2)>;
4838 // Register-Integer Signed Integer Multiply with EFLAGS result
4839 def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
4841 (IMUL16rri GR16:$src1, imm:$src2)>;
4842 def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
4844 (IMUL32rri GR32:$src1, imm:$src2)>;
4845 def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
4847 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4848 def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
4850 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4852 // Memory-Integer Signed Integer Multiply with EFLAGS result
4853 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
4855 (IMUL16rmi addr:$src1, imm:$src2)>;
4856 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
4858 (IMUL32rmi addr:$src1, imm:$src2)>;
4859 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
4861 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4862 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
4864 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4866 // Optimize multiply by 2 with EFLAGS result.
4867 let AddedComplexity = 2 in {
4868 def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
4870 (ADD16rr GR16:$src1, GR16:$src1)>;
4872 def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
4874 (ADD32rr GR32:$src1, GR32:$src1)>;
4877 // INC and DEC with EFLAGS result. Note that these do not set CF.
4878 def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
4880 def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
4883 def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
4885 def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
4889 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
4890 (INC16r GR16:$src)>, Requires<[In32BitMode]>;
4891 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
4893 (INC16m addr:$dst)>, Requires<[In32BitMode]>;
4894 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
4895 (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
4896 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
4898 (DEC16m addr:$dst)>, Requires<[In32BitMode]>;
4900 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
4901 (INC32r GR32:$src)>, Requires<[In32BitMode]>;
4902 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
4904 (INC32m addr:$dst)>, Requires<[In32BitMode]>;
4905 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
4906 (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
4907 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
4909 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
4911 // Register-Register Or with EFLAGS result
4912 def : Pat<(parallel (X86or_flag GR8:$src1, GR8:$src2),
4914 (OR8rr GR8:$src1, GR8:$src2)>;
4915 def : Pat<(parallel (X86or_flag GR16:$src1, GR16:$src2),
4917 (OR16rr GR16:$src1, GR16:$src2)>;
4918 def : Pat<(parallel (X86or_flag GR32:$src1, GR32:$src2),
4920 (OR32rr GR32:$src1, GR32:$src2)>;
4922 // Register-Memory Or with EFLAGS result
4923 def : Pat<(parallel (X86or_flag GR8:$src1, (loadi8 addr:$src2)),
4925 (OR8rm GR8:$src1, addr:$src2)>;
4926 def : Pat<(parallel (X86or_flag GR16:$src1, (loadi16 addr:$src2)),
4928 (OR16rm GR16:$src1, addr:$src2)>;
4929 def : Pat<(parallel (X86or_flag GR32:$src1, (loadi32 addr:$src2)),
4931 (OR32rm GR32:$src1, addr:$src2)>;
4933 // Register-Integer Or with EFLAGS result
4934 def : Pat<(parallel (X86or_flag GR8:$src1, imm:$src2),
4936 (OR8ri GR8:$src1, imm:$src2)>;
4937 def : Pat<(parallel (X86or_flag GR16:$src1, imm:$src2),
4939 (OR16ri GR16:$src1, imm:$src2)>;
4940 def : Pat<(parallel (X86or_flag GR32:$src1, imm:$src2),
4942 (OR32ri GR32:$src1, imm:$src2)>;
4943 def : Pat<(parallel (X86or_flag GR16:$src1, i16immSExt8:$src2),
4945 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4946 def : Pat<(parallel (X86or_flag GR32:$src1, i32immSExt8:$src2),
4948 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4950 // Memory-Register Or with EFLAGS result
4951 def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), GR8:$src2),
4954 (OR8mr addr:$dst, GR8:$src2)>;
4955 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), GR16:$src2),
4958 (OR16mr addr:$dst, GR16:$src2)>;
4959 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), GR32:$src2),
4962 (OR32mr addr:$dst, GR32:$src2)>;
4964 // Memory-Integer Or with EFLAGS result
4965 def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), imm:$src2),
4968 (OR8mi addr:$dst, imm:$src2)>;
4969 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), imm:$src2),
4972 (OR16mi addr:$dst, imm:$src2)>;
4973 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), imm:$src2),
4976 (OR32mi addr:$dst, imm:$src2)>;
4977 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4980 (OR16mi8 addr:$dst, i16immSExt8:$src2)>;
4981 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4984 (OR32mi8 addr:$dst, i32immSExt8:$src2)>;
4986 // Register-Register XOr with EFLAGS result
4987 def : Pat<(parallel (X86xor_flag GR8:$src1, GR8:$src2),
4989 (XOR8rr GR8:$src1, GR8:$src2)>;
4990 def : Pat<(parallel (X86xor_flag GR16:$src1, GR16:$src2),
4992 (XOR16rr GR16:$src1, GR16:$src2)>;
4993 def : Pat<(parallel (X86xor_flag GR32:$src1, GR32:$src2),
4995 (XOR32rr GR32:$src1, GR32:$src2)>;
4997 // Register-Memory XOr with EFLAGS result
4998 def : Pat<(parallel (X86xor_flag GR8:$src1, (loadi8 addr:$src2)),
5000 (XOR8rm GR8:$src1, addr:$src2)>;
5001 def : Pat<(parallel (X86xor_flag GR16:$src1, (loadi16 addr:$src2)),
5003 (XOR16rm GR16:$src1, addr:$src2)>;
5004 def : Pat<(parallel (X86xor_flag GR32:$src1, (loadi32 addr:$src2)),
5006 (XOR32rm GR32:$src1, addr:$src2)>;
5008 // Register-Integer XOr with EFLAGS result
5009 def : Pat<(parallel (X86xor_flag GR8:$src1, imm:$src2),
5011 (XOR8ri GR8:$src1, imm:$src2)>;
5012 def : Pat<(parallel (X86xor_flag GR16:$src1, imm:$src2),
5014 (XOR16ri GR16:$src1, imm:$src2)>;
5015 def : Pat<(parallel (X86xor_flag GR32:$src1, imm:$src2),
5017 (XOR32ri GR32:$src1, imm:$src2)>;
5018 def : Pat<(parallel (X86xor_flag GR16:$src1, i16immSExt8:$src2),
5020 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
5021 def : Pat<(parallel (X86xor_flag GR32:$src1, i32immSExt8:$src2),
5023 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
5025 // Memory-Register XOr with EFLAGS result
5026 def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), GR8:$src2),
5029 (XOR8mr addr:$dst, GR8:$src2)>;
5030 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), GR16:$src2),
5033 (XOR16mr addr:$dst, GR16:$src2)>;
5034 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), GR32:$src2),
5037 (XOR32mr addr:$dst, GR32:$src2)>;
5039 // Memory-Integer XOr with EFLAGS result
5040 def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), imm:$src2),
5043 (XOR8mi addr:$dst, imm:$src2)>;
5044 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), imm:$src2),
5047 (XOR16mi addr:$dst, imm:$src2)>;
5048 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), imm:$src2),
5051 (XOR32mi addr:$dst, imm:$src2)>;
5052 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), i16immSExt8:$src2),
5055 (XOR16mi8 addr:$dst, i16immSExt8:$src2)>;
5056 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), i32immSExt8:$src2),
5059 (XOR32mi8 addr:$dst, i32immSExt8:$src2)>;
5061 // Register-Register And with EFLAGS result
5062 def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2),
5064 (AND8rr GR8:$src1, GR8:$src2)>;
5065 def : Pat<(parallel (X86and_flag GR16:$src1, GR16:$src2),
5067 (AND16rr GR16:$src1, GR16:$src2)>;
5068 def : Pat<(parallel (X86and_flag GR32:$src1, GR32:$src2),
5070 (AND32rr GR32:$src1, GR32:$src2)>;
5072 // Register-Memory And with EFLAGS result
5073 def : Pat<(parallel (X86and_flag GR8:$src1, (loadi8 addr:$src2)),
5075 (AND8rm GR8:$src1, addr:$src2)>;
5076 def : Pat<(parallel (X86and_flag GR16:$src1, (loadi16 addr:$src2)),
5078 (AND16rm GR16:$src1, addr:$src2)>;
5079 def : Pat<(parallel (X86and_flag GR32:$src1, (loadi32 addr:$src2)),
5081 (AND32rm GR32:$src1, addr:$src2)>;
5083 // Register-Integer And with EFLAGS result
5084 def : Pat<(parallel (X86and_flag GR8:$src1, imm:$src2),
5086 (AND8ri GR8:$src1, imm:$src2)>;
5087 def : Pat<(parallel (X86and_flag GR16:$src1, imm:$src2),
5089 (AND16ri GR16:$src1, imm:$src2)>;
5090 def : Pat<(parallel (X86and_flag GR32:$src1, imm:$src2),
5092 (AND32ri GR32:$src1, imm:$src2)>;
5093 def : Pat<(parallel (X86and_flag GR16:$src1, i16immSExt8:$src2),
5095 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
5096 def : Pat<(parallel (X86and_flag GR32:$src1, i32immSExt8:$src2),
5098 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
5100 // Memory-Register And with EFLAGS result
5101 def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), GR8:$src2),
5104 (AND8mr addr:$dst, GR8:$src2)>;
5105 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), GR16:$src2),
5108 (AND16mr addr:$dst, GR16:$src2)>;
5109 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), GR32:$src2),
5112 (AND32mr addr:$dst, GR32:$src2)>;
5114 // Memory-Integer And with EFLAGS result
5115 def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), imm:$src2),
5118 (AND8mi addr:$dst, imm:$src2)>;
5119 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), imm:$src2),
5122 (AND16mi addr:$dst, imm:$src2)>;
5123 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), imm:$src2),
5126 (AND32mi addr:$dst, imm:$src2)>;
5127 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), i16immSExt8:$src2),
5130 (AND16mi8 addr:$dst, i16immSExt8:$src2)>;
5131 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), i32immSExt8:$src2),
5134 (AND32mi8 addr:$dst, i32immSExt8:$src2)>;
5136 // -disable-16bit support.
5137 def : Pat<(truncstorei16 (i32 imm:$src), addr:$dst),
5138 (MOV16mi addr:$dst, imm:$src)>;
5139 def : Pat<(truncstorei16 GR32:$src, addr:$dst),
5140 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
5141 def : Pat<(i32 (sextloadi16 addr:$dst)),
5142 (MOVSX32rm16 addr:$dst)>;
5143 def : Pat<(i32 (zextloadi16 addr:$dst)),
5144 (MOVZX32rm16 addr:$dst)>;
5145 def : Pat<(i32 (extloadi16 addr:$dst)),
5146 (MOVZX32rm16 addr:$dst)>;
5148 //===----------------------------------------------------------------------===//
5149 // Floating Point Stack Support
5150 //===----------------------------------------------------------------------===//
5152 include "X86InstrFPStack.td"
5154 //===----------------------------------------------------------------------===//
5156 //===----------------------------------------------------------------------===//
5158 include "X86Instr64bit.td"
5160 //===----------------------------------------------------------------------===//
5161 // SIMD support (SSE, MMX and AVX)
5162 //===----------------------------------------------------------------------===//
5164 include "X86InstrFragmentsSIMD.td"
5166 //===----------------------------------------------------------------------===//
5167 // XMM Floating point support (requires SSE / SSE2)
5168 //===----------------------------------------------------------------------===//
5170 include "X86InstrSSE.td"
5172 //===----------------------------------------------------------------------===//
5173 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
5174 //===----------------------------------------------------------------------===//
5176 include "X86InstrMMX.td"