3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
33 def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
37 def SDTX86BrCond : SDTypeProfile<0, 3,
38 [SDTCisVT<0, OtherVT>,
39 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
41 def SDTX86SetCC : SDTypeProfile<1, 2,
43 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
44 def SDTX86SetCC_C : SDTypeProfile<1, 2,
46 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
48 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
50 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
52 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
53 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
54 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
56 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
57 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
60 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
62 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
66 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
68 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
70 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
72 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
74 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
76 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
78 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
80 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
81 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
82 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
83 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
85 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
87 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
89 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
90 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
92 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
93 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
95 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
96 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
98 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
99 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
101 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
102 [SDNPHasChain, SDNPMayStore,
103 SDNPMayLoad, SDNPMemOperand]>;
104 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
105 [SDNPHasChain, SDNPMayStore,
106 SDNPMayLoad, SDNPMemOperand]>;
107 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
108 [SDNPHasChain, SDNPMayStore,
109 SDNPMayLoad, SDNPMemOperand]>;
110 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
111 [SDNPHasChain, SDNPMayStore,
112 SDNPMayLoad, SDNPMemOperand]>;
113 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
114 [SDNPHasChain, SDNPMayStore,
115 SDNPMayLoad, SDNPMemOperand]>;
116 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
117 [SDNPHasChain, SDNPMayStore,
118 SDNPMayLoad, SDNPMemOperand]>;
119 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
120 [SDNPHasChain, SDNPMayStore,
121 SDNPMayLoad, SDNPMemOperand]>;
122 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
123 [SDNPHasChain, SDNPOptInFlag]>;
125 def X86vastart_save_xmm_regs :
126 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
127 SDT_X86VASTART_SAVE_XMM_REGS,
130 def X86callseq_start :
131 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
132 [SDNPHasChain, SDNPOutFlag]>;
134 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
135 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
137 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
138 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
140 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
141 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
142 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
143 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
146 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
147 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
149 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
150 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
152 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
153 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
154 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
155 SDT_X86SegmentBaseAddress, []>;
157 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
160 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
161 [SDNPHasChain, SDNPOptInFlag]>;
163 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
165 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
166 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
168 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
170 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
171 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
172 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
174 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
176 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
179 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
181 //===----------------------------------------------------------------------===//
182 // X86 Operand Definitions.
185 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
186 // the index operand of an address, to conform to x86 encoding restrictions.
187 def ptr_rc_nosp : PointerLikeRegClass<1>;
189 // *mem - Operand definitions for the funky X86 addressing mode operands.
191 def X86MemAsmOperand : AsmOperandClass {
195 def X86AbsMemAsmOperand : AsmOperandClass {
197 let SuperClass = X86MemAsmOperand;
199 def X86NoSegMemAsmOperand : AsmOperandClass {
200 let Name = "NoSegMem";
201 let SuperClass = X86MemAsmOperand;
203 class X86MemOperand<string printMethod> : Operand<iPTR> {
204 let PrintMethod = printMethod;
205 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
206 let ParserMatchClass = X86MemAsmOperand;
209 def opaque32mem : X86MemOperand<"printopaquemem">;
210 def opaque48mem : X86MemOperand<"printopaquemem">;
211 def opaque80mem : X86MemOperand<"printopaquemem">;
212 def opaque512mem : X86MemOperand<"printopaquemem">;
214 def i8mem : X86MemOperand<"printi8mem">;
215 def i16mem : X86MemOperand<"printi16mem">;
216 def i32mem : X86MemOperand<"printi32mem">;
217 def i64mem : X86MemOperand<"printi64mem">;
218 def i128mem : X86MemOperand<"printi128mem">;
219 //def i256mem : X86MemOperand<"printi256mem">;
220 def f32mem : X86MemOperand<"printf32mem">;
221 def f64mem : X86MemOperand<"printf64mem">;
222 def f80mem : X86MemOperand<"printf80mem">;
223 def f128mem : X86MemOperand<"printf128mem">;
224 //def f256mem : X86MemOperand<"printf256mem">;
226 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
227 // plain GR64, so that it doesn't potentially require a REX prefix.
228 def i8mem_NOREX : Operand<i64> {
229 let PrintMethod = "printi8mem";
230 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
231 let ParserMatchClass = X86MemAsmOperand;
234 def lea32mem : Operand<i32> {
235 let PrintMethod = "printlea32mem";
236 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
237 let ParserMatchClass = X86NoSegMemAsmOperand;
240 let ParserMatchClass = X86AbsMemAsmOperand,
241 PrintMethod = "print_pcrel_imm" in {
242 def i32imm_pcrel : Operand<i32>;
244 def offset8 : Operand<i64>;
245 def offset16 : Operand<i64>;
246 def offset32 : Operand<i64>;
247 def offset64 : Operand<i64>;
249 // Branch targets have OtherVT type and print as pc-relative values.
250 def brtarget : Operand<OtherVT>;
251 def brtarget8 : Operand<OtherVT>;
255 def SSECC : Operand<i8> {
256 let PrintMethod = "printSSECC";
259 def ImmSExt8AsmOperand : AsmOperandClass {
260 let Name = "ImmSExt8";
261 let SuperClass = ImmAsmOperand;
264 // A couple of more descriptive operand definitions.
265 // 16-bits but only 8 bits are significant.
266 def i16i8imm : Operand<i16> {
267 let ParserMatchClass = ImmSExt8AsmOperand;
269 // 32-bits but only 8 bits are significant.
270 def i32i8imm : Operand<i32> {
271 let ParserMatchClass = ImmSExt8AsmOperand;
274 //===----------------------------------------------------------------------===//
275 // X86 Complex Pattern Definitions.
278 // Define X86 specific addressing mode.
279 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
280 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
281 [add, sub, mul, X86mul_imm, shl, or, frameindex],
283 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
284 [tglobaltlsaddr], []>;
286 //===----------------------------------------------------------------------===//
287 // X86 Instruction Predicate Definitions.
288 def HasMMX : Predicate<"Subtarget->hasMMX()">;
289 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
290 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
291 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
292 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
293 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
294 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
295 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
296 def HasAVX : Predicate<"Subtarget->hasAVX()">;
297 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
298 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
299 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
300 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
301 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
302 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
303 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
304 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
305 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
306 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
307 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
308 "TM.getCodeModel() != CodeModel::Kernel">;
309 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
310 "TM.getCodeModel() == CodeModel::Kernel">;
311 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
312 def OptForSize : Predicate<"OptForSize">;
313 def OptForSpeed : Predicate<"!OptForSize">;
314 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
315 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
317 //===----------------------------------------------------------------------===//
318 // X86 Instruction Format Definitions.
321 include "X86InstrFormats.td"
323 //===----------------------------------------------------------------------===//
324 // Pattern fragments...
327 // X86 specific condition code. These correspond to CondCode in
328 // X86InstrInfo.h. They must be kept in synch.
329 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
330 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
331 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
332 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
333 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
334 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
335 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
336 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
337 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
338 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
339 def X86_COND_NO : PatLeaf<(i8 10)>;
340 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
341 def X86_COND_NS : PatLeaf<(i8 12)>;
342 def X86_COND_O : PatLeaf<(i8 13)>;
343 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
344 def X86_COND_S : PatLeaf<(i8 15)>;
346 def i16immSExt8 : PatLeaf<(i16 imm), [{
347 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
348 // sign extended field.
349 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
352 def i32immSExt8 : PatLeaf<(i32 imm), [{
353 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
354 // sign extended field.
355 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
358 // Helper fragments for loads.
359 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
360 // known to be 32-bit aligned or better. Ditto for i8 to i16.
361 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
362 LoadSDNode *LD = cast<LoadSDNode>(N);
363 if (const Value *Src = LD->getSrcValue())
364 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
365 if (PT->getAddressSpace() > 255)
367 ISD::LoadExtType ExtType = LD->getExtensionType();
368 if (ExtType == ISD::NON_EXTLOAD)
370 if (ExtType == ISD::EXTLOAD)
371 return LD->getAlignment() >= 2 && !LD->isVolatile();
375 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),
377 LoadSDNode *LD = cast<LoadSDNode>(N);
378 if (const Value *Src = LD->getSrcValue())
379 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
380 if (PT->getAddressSpace() > 255)
382 ISD::LoadExtType ExtType = LD->getExtensionType();
383 if (ExtType == ISD::EXTLOAD)
384 return LD->getAlignment() >= 2 && !LD->isVolatile();
388 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
389 LoadSDNode *LD = cast<LoadSDNode>(N);
390 if (const Value *Src = LD->getSrcValue())
391 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
392 if (PT->getAddressSpace() > 255)
394 ISD::LoadExtType ExtType = LD->getExtensionType();
395 if (ExtType == ISD::NON_EXTLOAD)
397 if (ExtType == ISD::EXTLOAD)
398 return LD->getAlignment() >= 4 && !LD->isVolatile();
402 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
403 LoadSDNode *LD = cast<LoadSDNode>(N);
404 if (const Value *Src = LD->getSrcValue())
405 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
406 if (PT->getAddressSpace() > 255)
408 if (LD->isVolatile())
410 ISD::LoadExtType ExtType = LD->getExtensionType();
411 if (ExtType == ISD::NON_EXTLOAD)
413 if (ExtType == ISD::EXTLOAD)
414 return LD->getAlignment() >= 4;
418 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
419 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
420 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
421 return PT->getAddressSpace() == 256;
425 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
426 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
427 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
428 return PT->getAddressSpace() == 257;
432 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{
433 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
434 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
435 if (PT->getAddressSpace() > 255)
439 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{
440 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
441 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
442 if (PT->getAddressSpace() > 255)
447 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{
448 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
449 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
450 if (PT->getAddressSpace() > 255)
454 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{
455 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
456 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
457 if (PT->getAddressSpace() > 255)
461 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{
462 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
463 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
464 if (PT->getAddressSpace() > 255)
469 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
470 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
471 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
473 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
474 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
475 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
476 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
477 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
478 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
480 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
481 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
482 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
483 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
484 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
485 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
488 // An 'and' node with a single use.
489 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
490 return N->hasOneUse();
492 // An 'srl' node with a single use.
493 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
494 return N->hasOneUse();
496 // An 'trunc' node with a single use.
497 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
498 return N->hasOneUse();
501 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
502 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
503 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
504 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
506 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
507 APInt Mask = APInt::getAllOnesValue(BitWidth);
508 APInt KnownZero0, KnownOne0;
509 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
510 APInt KnownZero1, KnownOne1;
511 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
512 return (~KnownZero0 & ~KnownZero1) == 0;
516 // 'shld' and 'shrd' instruction patterns. Note that even though these have
517 // the srl and shl in their patterns, the C++ code must still check for them,
518 // because predicates are tested before children nodes are explored.
520 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
521 (or (srl node:$src1, node:$amt1),
522 (shl node:$src2, node:$amt2)), [{
523 assert(N->getOpcode() == ISD::OR);
524 return N->getOperand(0).getOpcode() == ISD::SRL &&
525 N->getOperand(1).getOpcode() == ISD::SHL &&
526 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
527 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
528 N->getOperand(0).getConstantOperandVal(1) ==
529 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
532 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
533 (or (shl node:$src1, node:$amt1),
534 (srl node:$src2, node:$amt2)), [{
535 assert(N->getOpcode() == ISD::OR);
536 return N->getOperand(0).getOpcode() == ISD::SHL &&
537 N->getOperand(1).getOpcode() == ISD::SRL &&
538 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
539 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
540 N->getOperand(0).getConstantOperandVal(1) ==
541 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
544 //===----------------------------------------------------------------------===//
545 // Instruction list...
548 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
549 // a stack adjustment and the codegen must know that they may modify the stack
550 // pointer before prolog-epilog rewriting occurs.
551 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
552 // sub / add which can clobber EFLAGS.
553 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
554 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
556 [(X86callseq_start timm:$amt)]>,
557 Requires<[In32BitMode]>;
558 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
560 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
561 Requires<[In32BitMode]>;
564 // x86-64 va_start lowering magic.
565 let usesCustomInserter = 1 in
566 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
569 i64imm:$regsavefi, i64imm:$offset,
571 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
572 [(X86vastart_save_xmm_regs GR8:$al,
577 let neverHasSideEffects = 1 in {
578 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
579 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
580 "nop{w}\t$zero", []>, TB, OpSize;
581 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
582 "nop{l}\t$zero", []>, TB;
586 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int\t3", []>;
587 def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
588 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize;
589 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>;
591 // PIC base construction. This expands to code that looks like this:
594 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
595 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
598 //===----------------------------------------------------------------------===//
599 // Control Flow Instructions.
602 // Return instructions.
603 let isTerminator = 1, isReturn = 1, isBarrier = 1,
604 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
605 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
608 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
610 [(X86retflag timm:$amt)]>;
611 def LRET : I <0xCB, RawFrm, (outs), (ins),
613 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
617 // Unconditional branches.
618 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
619 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
620 "jmp\t$dst", [(br bb:$dst)]>;
621 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
625 // Conditional Branches.
626 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
627 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
628 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
629 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
630 [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
634 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
635 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
636 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
637 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
638 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
639 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
640 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
641 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
642 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
643 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
644 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
645 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
646 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
647 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
648 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
649 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
651 // FIXME: What about the CX/RCX versions of this instruction?
652 let Uses = [ECX], isBranch = 1, isTerminator = 1 in
653 def JCXZ8 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
658 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
659 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
660 [(brind GR32:$dst)]>;
661 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
662 [(brind (loadi32 addr:$dst))]>;
664 def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
665 (ins i16imm:$seg, i16imm:$off),
666 "ljmp{w}\t$seg, $off", []>, OpSize;
667 def FARJMP32i : Iseg32<0xEA, RawFrm, (outs),
668 (ins i16imm:$seg, i32imm:$off),
669 "ljmp{l}\t$seg, $off", []>;
671 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
672 "ljmp{w}\t{*}$dst", []>, OpSize;
673 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
674 "ljmp{l}\t{*}$dst", []>;
680 def LOOP : I<0xE2, RawFrm, (ins brtarget8:$dst), (outs), "loop\t$dst", []>;
681 def LOOPE : I<0xE1, RawFrm, (ins brtarget8:$dst), (outs), "loope\t$dst", []>;
682 def LOOPNE : I<0xE0, RawFrm, (ins brtarget8:$dst), (outs), "loopne\t$dst", []>;
684 //===----------------------------------------------------------------------===//
685 // Call Instructions...
688 // All calls clobber the non-callee saved registers. ESP is marked as
689 // a use to prevent stack-pointer assignments that appear immediately
690 // before calls from potentially appearing dead. Uses for argument
691 // registers are added manually.
692 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
693 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
694 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
695 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
697 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
698 (outs), (ins i32imm_pcrel:$dst,variable_ops),
700 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
701 "call\t{*}$dst", [(X86call GR32:$dst)]>;
702 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
703 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
705 def FARCALL16i : Iseg16<0x9A, RawFrm, (outs),
706 (ins i16imm:$seg, i16imm:$off),
707 "lcall{w}\t$seg, $off", []>, OpSize;
708 def FARCALL32i : Iseg32<0x9A, RawFrm, (outs),
709 (ins i16imm:$seg, i32imm:$off),
710 "lcall{l}\t$seg, $off", []>;
712 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
713 "lcall{w}\t{*}$dst", []>, OpSize;
714 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
715 "lcall{l}\t{*}$dst", []>;
718 // Constructing a stack frame.
720 def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl),
721 "enter\t$len, $lvl", []>;
725 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
726 def TCRETURNdi : I<0, Pseudo, (outs),
727 (ins i32imm:$dst, i32imm:$offset, variable_ops),
728 "#TC_RETURN $dst $offset",
731 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
732 def TCRETURNri : I<0, Pseudo, (outs),
733 (ins GR32:$dst, i32imm:$offset, variable_ops),
734 "#TC_RETURN $dst $offset",
737 // FIXME: The should be pseudo instructions that are lowered when going to
739 let isCall = 1, isBranch = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
740 def TAILJMPd : Ii32<0xE9, RawFrm, (outs),(ins i32imm_pcrel:$dst,variable_ops),
741 "jmp\t$dst # TAILCALL",
743 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
744 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst, variable_ops),
745 "jmp{l}\t{*}$dst # TAILCALL",
747 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
748 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst, variable_ops),
749 "jmp\t{*}$dst # TAILCALL", []>;
751 //===----------------------------------------------------------------------===//
752 // Miscellaneous Instructions...
754 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
755 def LEAVE : I<0xC9, RawFrm,
756 (outs), (ins), "leave", []>;
758 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
759 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
760 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
761 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
762 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
763 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
764 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
765 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
767 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
769 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
771 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
772 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
774 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
776 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
777 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
780 let mayStore = 1 in {
781 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
783 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
784 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
786 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
788 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
789 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
793 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
794 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
795 "push{l}\t$imm", []>;
796 def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
797 "push{l}\t$imm", []>;
798 def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
799 "push{l}\t$imm", []>;
802 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
803 def POPF : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
804 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf{l}", []>;
806 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
807 def PUSHF : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
808 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf{l}", []>;
811 let isTwoAddress = 1 in // GR32 = bswap GR32
812 def BSWAP32r : I<0xC8, AddRegFrm,
813 (outs GR32:$dst), (ins GR32:$src),
815 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
818 // Bit scan instructions.
819 let Defs = [EFLAGS] in {
820 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
821 "bsf{w}\t{$src, $dst|$dst, $src}",
822 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
823 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
824 "bsf{w}\t{$src, $dst|$dst, $src}",
825 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
826 (implicit EFLAGS)]>, TB;
827 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
828 "bsf{l}\t{$src, $dst|$dst, $src}",
829 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
830 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
831 "bsf{l}\t{$src, $dst|$dst, $src}",
832 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
833 (implicit EFLAGS)]>, TB;
835 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
836 "bsr{w}\t{$src, $dst|$dst, $src}",
837 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
838 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
839 "bsr{w}\t{$src, $dst|$dst, $src}",
840 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
841 (implicit EFLAGS)]>, TB;
842 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
843 "bsr{l}\t{$src, $dst|$dst, $src}",
844 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
845 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
846 "bsr{l}\t{$src, $dst|$dst, $src}",
847 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
848 (implicit EFLAGS)]>, TB;
851 let neverHasSideEffects = 1 in
852 def LEA16r : I<0x8D, MRMSrcMem,
853 (outs GR16:$dst), (ins lea32mem:$src),
854 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
855 let isReMaterializable = 1 in
856 def LEA32r : I<0x8D, MRMSrcMem,
857 (outs GR32:$dst), (ins lea32mem:$src),
858 "lea{l}\t{$src|$dst}, {$dst|$src}",
859 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
861 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
862 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
863 [(X86rep_movs i8)]>, REP;
864 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
865 [(X86rep_movs i16)]>, REP, OpSize;
866 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
867 [(X86rep_movs i32)]>, REP;
870 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
871 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
872 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
873 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
874 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
877 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
878 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
879 [(X86rep_stos i8)]>, REP;
880 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
881 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
882 [(X86rep_stos i16)]>, REP, OpSize;
883 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
884 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
885 [(X86rep_stos i32)]>, REP;
887 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
888 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
889 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
890 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
891 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
892 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
893 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
895 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
896 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
897 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
899 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
900 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
901 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
903 let Defs = [RAX, RDX] in
904 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
907 let Defs = [RAX, RCX, RDX] in
908 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
910 let isBarrier = 1, hasCtrlDep = 1 in {
911 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
914 def SYSCALL : I<0x05, RawFrm,
915 (outs), (ins), "syscall", []>, TB;
916 def SYSRET : I<0x07, RawFrm,
917 (outs), (ins), "sysret", []>, TB;
918 def SYSENTER : I<0x34, RawFrm,
919 (outs), (ins), "sysenter", []>, TB;
920 def SYSEXIT : I<0x35, RawFrm,
921 (outs), (ins), "sysexit", []>, TB;
923 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
926 //===----------------------------------------------------------------------===//
927 // Input/Output Instructions...
929 let Defs = [AL], Uses = [DX] in
930 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
931 "in{b}\t{%dx, %al|%AL, %DX}", []>;
932 let Defs = [AX], Uses = [DX] in
933 def IN16rr : I<0xED, RawFrm, (outs), (ins),
934 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
935 let Defs = [EAX], Uses = [DX] in
936 def IN32rr : I<0xED, RawFrm, (outs), (ins),
937 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
940 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
941 "in{b}\t{$port, %al|%AL, $port}", []>;
943 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
944 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
946 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
947 "in{l}\t{$port, %eax|%EAX, $port}", []>;
949 let Uses = [DX, AL] in
950 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
951 "out{b}\t{%al, %dx|%DX, %AL}", []>;
952 let Uses = [DX, AX] in
953 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
954 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
955 let Uses = [DX, EAX] in
956 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
957 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
960 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
961 "out{b}\t{%al, $port|$port, %AL}", []>;
963 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
964 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
966 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
967 "out{l}\t{%eax, $port|$port, %EAX}", []>;
969 def IN8 : I<0x6C, RawFrm, (outs), (ins),
971 def IN16 : I<0x6D, RawFrm, (outs), (ins),
972 "ins{w}", []>, OpSize;
973 def IN32 : I<0x6D, RawFrm, (outs), (ins),
976 //===----------------------------------------------------------------------===//
977 // Move Instructions...
979 let neverHasSideEffects = 1 in {
980 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
981 "mov{b}\t{$src, $dst|$dst, $src}", []>;
982 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
983 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
984 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
985 "mov{l}\t{$src, $dst|$dst, $src}", []>;
987 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
988 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
989 "mov{b}\t{$src, $dst|$dst, $src}",
990 [(set GR8:$dst, imm:$src)]>;
991 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
992 "mov{w}\t{$src, $dst|$dst, $src}",
993 [(set GR16:$dst, imm:$src)]>, OpSize;
994 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
995 "mov{l}\t{$src, $dst|$dst, $src}",
996 [(set GR32:$dst, imm:$src)]>;
999 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1000 "mov{b}\t{$src, $dst|$dst, $src}",
1001 [(store (i8 imm:$src), addr:$dst)]>;
1002 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1003 "mov{w}\t{$src, $dst|$dst, $src}",
1004 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
1005 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1006 "mov{l}\t{$src, $dst|$dst, $src}",
1007 [(store (i32 imm:$src), addr:$dst)]>;
1009 def MOV8o8a : Ii8 <0xA0, RawFrm, (outs), (ins offset8:$src),
1010 "mov{b}\t{$src, %al|%al, $src}", []>;
1011 def MOV16o16a : Ii16 <0xA1, RawFrm, (outs), (ins offset16:$src),
1012 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1013 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1014 "mov{l}\t{$src, %eax|%eax, $src}", []>;
1016 def MOV8ao8 : Ii8 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1017 "mov{b}\t{%al, $dst|$dst, %al}", []>;
1018 def MOV16ao16 : Ii16 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1019 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize;
1020 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1021 "mov{l}\t{%eax, $dst|$dst, %eax}", []>;
1023 // Moves to and from segment registers
1024 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
1025 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1026 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
1027 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1028 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
1029 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1030 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
1031 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1033 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1034 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1035 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1036 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1037 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1038 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1040 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
1041 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1042 "mov{b}\t{$src, $dst|$dst, $src}",
1043 [(set GR8:$dst, (loadi8 addr:$src))]>;
1044 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1045 "mov{w}\t{$src, $dst|$dst, $src}",
1046 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
1047 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1048 "mov{l}\t{$src, $dst|$dst, $src}",
1049 [(set GR32:$dst, (loadi32 addr:$src))]>;
1052 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1053 "mov{b}\t{$src, $dst|$dst, $src}",
1054 [(store GR8:$src, addr:$dst)]>;
1055 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1056 "mov{w}\t{$src, $dst|$dst, $src}",
1057 [(store GR16:$src, addr:$dst)]>, OpSize;
1058 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1059 "mov{l}\t{$src, $dst|$dst, $src}",
1060 [(store GR32:$src, addr:$dst)]>;
1062 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1063 // that they can be used for copying and storing h registers, which can't be
1064 // encoded when a REX prefix is present.
1065 let neverHasSideEffects = 1 in
1066 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1067 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1068 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1070 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1071 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1072 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1074 canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1075 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1076 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1077 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1079 // Moves to and from debug registers
1080 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
1081 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1082 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
1083 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1085 // Moves to and from control registers
1086 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG_32:$src),
1087 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1088 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_32:$dst), (ins GR32:$src),
1089 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1091 //===----------------------------------------------------------------------===//
1092 // Fixed-Register Multiplication and Division Instructions...
1095 // Extra precision multiplication
1096 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1097 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
1098 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1099 // This probably ought to be moved to a def : Pat<> if the
1100 // syntax can be accepted.
1101 [(set AL, (mul AL, GR8:$src)),
1102 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1104 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1105 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1107 []>, OpSize; // AX,DX = AX*GR16
1109 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1110 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1112 []>; // EAX,EDX = EAX*GR32
1114 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1115 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1117 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1118 // This probably ought to be moved to a def : Pat<> if the
1119 // syntax can be accepted.
1120 [(set AL, (mul AL, (loadi8 addr:$src))),
1121 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1123 let mayLoad = 1, neverHasSideEffects = 1 in {
1124 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1125 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1127 []>, OpSize; // AX,DX = AX*[mem16]
1129 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1130 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1132 []>; // EAX,EDX = EAX*[mem32]
1135 let neverHasSideEffects = 1 in {
1136 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1137 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1139 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1140 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1141 OpSize; // AX,DX = AX*GR16
1142 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1143 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1144 // EAX,EDX = EAX*GR32
1145 let mayLoad = 1 in {
1146 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1147 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1148 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1149 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1150 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1151 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1152 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1153 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1154 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1156 } // neverHasSideEffects
1158 // unsigned division/remainder
1159 let Defs = [AX,EFLAGS], Uses = [AX] in
1160 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1161 "div{b}\t$src", []>;
1162 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1163 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1164 "div{w}\t$src", []>, OpSize;
1165 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1166 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1167 "div{l}\t$src", []>;
1168 let mayLoad = 1 in {
1169 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1170 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1171 "div{b}\t$src", []>;
1172 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1173 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1174 "div{w}\t$src", []>, OpSize;
1175 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1176 // EDX:EAX/[mem32] = EAX,EDX
1177 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
1178 "div{l}\t$src", []>;
1181 // Signed division/remainder.
1182 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1183 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1184 "idiv{b}\t$src", []>;
1185 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1186 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1187 "idiv{w}\t$src", []>, OpSize;
1188 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1189 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1190 "idiv{l}\t$src", []>;
1191 let mayLoad = 1, mayLoad = 1 in {
1192 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1193 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1194 "idiv{b}\t$src", []>;
1195 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1196 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1197 "idiv{w}\t$src", []>, OpSize;
1198 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1199 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1200 // EDX:EAX/[mem32] = EAX,EDX
1201 "idiv{l}\t$src", []>;
1204 //===----------------------------------------------------------------------===//
1205 // Two address Instructions.
1207 let isTwoAddress = 1 in {
1209 // Conditional moves
1210 let Uses = [EFLAGS] in {
1212 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1213 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1214 // however that requires promoting the operands, and can induce additional
1215 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1216 // clobber EFLAGS, because if one of the operands is zero, the expansion
1217 // could involve an xor.
1218 let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in
1219 def CMOV_GR8 : I<0, Pseudo,
1220 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1221 "#CMOV_GR8 PSEUDO!",
1222 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1223 imm:$cond, EFLAGS))]>;
1225 let isCommutable = 1 in {
1226 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1227 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1228 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1229 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1230 X86_COND_B, EFLAGS))]>,
1232 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1233 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1234 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1235 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1236 X86_COND_B, EFLAGS))]>,
1238 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1239 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1240 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1241 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1242 X86_COND_AE, EFLAGS))]>,
1244 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1245 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1246 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1247 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1248 X86_COND_AE, EFLAGS))]>,
1250 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1251 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1252 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1253 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1254 X86_COND_E, EFLAGS))]>,
1256 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1257 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1258 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1259 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1260 X86_COND_E, EFLAGS))]>,
1262 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1263 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1264 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1265 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1266 X86_COND_NE, EFLAGS))]>,
1268 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1269 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1270 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1271 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1272 X86_COND_NE, EFLAGS))]>,
1274 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1275 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1276 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1277 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1278 X86_COND_BE, EFLAGS))]>,
1280 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1281 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1282 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1283 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1284 X86_COND_BE, EFLAGS))]>,
1286 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1287 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1288 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1289 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1290 X86_COND_A, EFLAGS))]>,
1292 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1293 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1294 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1295 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1296 X86_COND_A, EFLAGS))]>,
1298 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1299 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1300 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1301 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1302 X86_COND_L, EFLAGS))]>,
1304 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1305 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1306 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1307 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1308 X86_COND_L, EFLAGS))]>,
1310 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1311 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1312 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1313 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1314 X86_COND_GE, EFLAGS))]>,
1316 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1317 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1318 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1319 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1320 X86_COND_GE, EFLAGS))]>,
1322 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1323 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1324 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1325 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1326 X86_COND_LE, EFLAGS))]>,
1328 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1329 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1330 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1331 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1332 X86_COND_LE, EFLAGS))]>,
1334 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1335 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1336 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1337 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1338 X86_COND_G, EFLAGS))]>,
1340 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1341 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1342 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1343 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1344 X86_COND_G, EFLAGS))]>,
1346 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1347 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1348 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1349 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1350 X86_COND_S, EFLAGS))]>,
1352 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1353 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1354 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1355 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1356 X86_COND_S, EFLAGS))]>,
1358 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1359 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1360 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1361 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1362 X86_COND_NS, EFLAGS))]>,
1364 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1365 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1366 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1367 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1368 X86_COND_NS, EFLAGS))]>,
1370 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1371 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1372 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1373 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1374 X86_COND_P, EFLAGS))]>,
1376 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1377 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1378 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1379 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1380 X86_COND_P, EFLAGS))]>,
1382 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1383 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1384 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1385 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1386 X86_COND_NP, EFLAGS))]>,
1388 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1389 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1390 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1391 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1392 X86_COND_NP, EFLAGS))]>,
1394 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1395 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1396 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1397 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1398 X86_COND_O, EFLAGS))]>,
1400 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1401 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1402 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1403 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1404 X86_COND_O, EFLAGS))]>,
1406 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1407 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1408 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1409 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1410 X86_COND_NO, EFLAGS))]>,
1412 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1413 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1414 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1415 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1416 X86_COND_NO, EFLAGS))]>,
1418 } // isCommutable = 1
1420 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1421 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1422 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1423 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1424 X86_COND_B, EFLAGS))]>,
1426 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1427 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1428 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1429 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1430 X86_COND_B, EFLAGS))]>,
1432 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1433 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1434 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1435 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1436 X86_COND_AE, EFLAGS))]>,
1438 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1439 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1440 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1441 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1442 X86_COND_AE, EFLAGS))]>,
1444 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1445 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1446 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1447 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1448 X86_COND_E, EFLAGS))]>,
1450 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1451 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1452 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1453 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1454 X86_COND_E, EFLAGS))]>,
1456 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1457 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1458 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1459 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1460 X86_COND_NE, EFLAGS))]>,
1462 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1463 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1464 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1465 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1466 X86_COND_NE, EFLAGS))]>,
1468 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1469 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1470 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1471 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1472 X86_COND_BE, EFLAGS))]>,
1474 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1475 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1476 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1477 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1478 X86_COND_BE, EFLAGS))]>,
1480 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1481 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1482 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1483 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1484 X86_COND_A, EFLAGS))]>,
1486 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1487 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1488 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1489 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1490 X86_COND_A, EFLAGS))]>,
1492 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1493 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1494 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1495 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1496 X86_COND_L, EFLAGS))]>,
1498 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1499 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1500 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1501 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1502 X86_COND_L, EFLAGS))]>,
1504 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1505 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1506 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1507 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1508 X86_COND_GE, EFLAGS))]>,
1510 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1511 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1512 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1513 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1514 X86_COND_GE, EFLAGS))]>,
1516 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1517 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1518 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1519 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1520 X86_COND_LE, EFLAGS))]>,
1522 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1523 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1524 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1525 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1526 X86_COND_LE, EFLAGS))]>,
1528 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1529 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1530 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1531 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1532 X86_COND_G, EFLAGS))]>,
1534 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1535 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1536 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1537 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1538 X86_COND_G, EFLAGS))]>,
1540 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1541 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1542 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1543 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1544 X86_COND_S, EFLAGS))]>,
1546 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1547 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1548 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1549 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1550 X86_COND_S, EFLAGS))]>,
1552 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1553 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1554 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1555 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1556 X86_COND_NS, EFLAGS))]>,
1558 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1559 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1560 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1561 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1562 X86_COND_NS, EFLAGS))]>,
1564 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1565 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1566 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1567 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1568 X86_COND_P, EFLAGS))]>,
1570 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1571 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1572 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1573 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1574 X86_COND_P, EFLAGS))]>,
1576 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1577 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1578 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1579 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1580 X86_COND_NP, EFLAGS))]>,
1582 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1583 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1584 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1585 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1586 X86_COND_NP, EFLAGS))]>,
1588 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1589 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1590 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1591 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1592 X86_COND_O, EFLAGS))]>,
1594 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1595 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1596 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1597 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1598 X86_COND_O, EFLAGS))]>,
1600 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1601 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1602 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1603 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1604 X86_COND_NO, EFLAGS))]>,
1606 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1607 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1608 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1609 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1610 X86_COND_NO, EFLAGS))]>,
1612 } // Uses = [EFLAGS]
1615 // unary instructions
1616 let CodeSize = 2 in {
1617 let Defs = [EFLAGS] in {
1618 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1619 [(set GR8:$dst, (ineg GR8:$src)),
1620 (implicit EFLAGS)]>;
1621 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1622 [(set GR16:$dst, (ineg GR16:$src)),
1623 (implicit EFLAGS)]>, OpSize;
1624 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1625 [(set GR32:$dst, (ineg GR32:$src)),
1626 (implicit EFLAGS)]>;
1627 let isTwoAddress = 0 in {
1628 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1629 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1630 (implicit EFLAGS)]>;
1631 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1632 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1633 (implicit EFLAGS)]>, OpSize;
1634 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1635 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1636 (implicit EFLAGS)]>;
1638 } // Defs = [EFLAGS]
1640 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1641 let AddedComplexity = 15 in {
1642 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1643 [(set GR8:$dst, (not GR8:$src))]>;
1644 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1645 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1646 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1647 [(set GR32:$dst, (not GR32:$src))]>;
1649 let isTwoAddress = 0 in {
1650 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1651 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1652 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1653 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1654 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1655 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1659 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1660 let Defs = [EFLAGS] in {
1662 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1663 [(set GR8:$dst, (add GR8:$src, 1)),
1664 (implicit EFLAGS)]>;
1665 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1666 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1668 [(set GR16:$dst, (add GR16:$src, 1)),
1669 (implicit EFLAGS)]>,
1670 OpSize, Requires<[In32BitMode]>;
1671 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1673 [(set GR32:$dst, (add GR32:$src, 1)),
1674 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1676 let isTwoAddress = 0, CodeSize = 2 in {
1677 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1678 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1679 (implicit EFLAGS)]>;
1680 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1681 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1682 (implicit EFLAGS)]>,
1683 OpSize, Requires<[In32BitMode]>;
1684 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1685 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1686 (implicit EFLAGS)]>,
1687 Requires<[In32BitMode]>;
1691 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1692 [(set GR8:$dst, (add GR8:$src, -1)),
1693 (implicit EFLAGS)]>;
1694 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1695 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1697 [(set GR16:$dst, (add GR16:$src, -1)),
1698 (implicit EFLAGS)]>,
1699 OpSize, Requires<[In32BitMode]>;
1700 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1702 [(set GR32:$dst, (add GR32:$src, -1)),
1703 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1706 let isTwoAddress = 0, CodeSize = 2 in {
1707 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1708 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1709 (implicit EFLAGS)]>;
1710 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1711 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1712 (implicit EFLAGS)]>,
1713 OpSize, Requires<[In32BitMode]>;
1714 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1715 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1716 (implicit EFLAGS)]>,
1717 Requires<[In32BitMode]>;
1719 } // Defs = [EFLAGS]
1721 // Logical operators...
1722 let Defs = [EFLAGS] in {
1723 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1724 def AND8rr : I<0x20, MRMDestReg,
1725 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1726 "and{b}\t{$src2, $dst|$dst, $src2}",
1727 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
1728 (implicit EFLAGS)]>;
1729 def AND16rr : I<0x21, MRMDestReg,
1730 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1731 "and{w}\t{$src2, $dst|$dst, $src2}",
1732 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
1733 (implicit EFLAGS)]>, OpSize;
1734 def AND32rr : I<0x21, MRMDestReg,
1735 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1736 "and{l}\t{$src2, $dst|$dst, $src2}",
1737 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
1738 (implicit EFLAGS)]>;
1741 // AND instructions with the destination register in REG and the source register
1742 // in R/M. Included for the disassembler.
1743 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1744 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1745 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1746 (ins GR16:$src1, GR16:$src2),
1747 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1748 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1749 (ins GR32:$src1, GR32:$src2),
1750 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1752 def AND8rm : I<0x22, MRMSrcMem,
1753 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1754 "and{b}\t{$src2, $dst|$dst, $src2}",
1755 [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
1756 (implicit EFLAGS)]>;
1757 def AND16rm : I<0x23, MRMSrcMem,
1758 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1759 "and{w}\t{$src2, $dst|$dst, $src2}",
1760 [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
1761 (implicit EFLAGS)]>, OpSize;
1762 def AND32rm : I<0x23, MRMSrcMem,
1763 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1764 "and{l}\t{$src2, $dst|$dst, $src2}",
1765 [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
1766 (implicit EFLAGS)]>;
1768 def AND8ri : Ii8<0x80, MRM4r,
1769 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1770 "and{b}\t{$src2, $dst|$dst, $src2}",
1771 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
1772 (implicit EFLAGS)]>;
1773 def AND16ri : Ii16<0x81, MRM4r,
1774 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1775 "and{w}\t{$src2, $dst|$dst, $src2}",
1776 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
1777 (implicit EFLAGS)]>, OpSize;
1778 def AND32ri : Ii32<0x81, MRM4r,
1779 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1780 "and{l}\t{$src2, $dst|$dst, $src2}",
1781 [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
1782 (implicit EFLAGS)]>;
1783 def AND16ri8 : Ii8<0x83, MRM4r,
1784 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1785 "and{w}\t{$src2, $dst|$dst, $src2}",
1786 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
1787 (implicit EFLAGS)]>,
1789 def AND32ri8 : Ii8<0x83, MRM4r,
1790 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1791 "and{l}\t{$src2, $dst|$dst, $src2}",
1792 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
1793 (implicit EFLAGS)]>;
1795 let isTwoAddress = 0 in {
1796 def AND8mr : I<0x20, MRMDestMem,
1797 (outs), (ins i8mem :$dst, GR8 :$src),
1798 "and{b}\t{$src, $dst|$dst, $src}",
1799 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1800 (implicit EFLAGS)]>;
1801 def AND16mr : I<0x21, MRMDestMem,
1802 (outs), (ins i16mem:$dst, GR16:$src),
1803 "and{w}\t{$src, $dst|$dst, $src}",
1804 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1805 (implicit EFLAGS)]>,
1807 def AND32mr : I<0x21, MRMDestMem,
1808 (outs), (ins i32mem:$dst, GR32:$src),
1809 "and{l}\t{$src, $dst|$dst, $src}",
1810 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1811 (implicit EFLAGS)]>;
1812 def AND8mi : Ii8<0x80, MRM4m,
1813 (outs), (ins i8mem :$dst, i8imm :$src),
1814 "and{b}\t{$src, $dst|$dst, $src}",
1815 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1816 (implicit EFLAGS)]>;
1817 def AND16mi : Ii16<0x81, MRM4m,
1818 (outs), (ins i16mem:$dst, i16imm:$src),
1819 "and{w}\t{$src, $dst|$dst, $src}",
1820 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1821 (implicit EFLAGS)]>,
1823 def AND32mi : Ii32<0x81, MRM4m,
1824 (outs), (ins i32mem:$dst, i32imm:$src),
1825 "and{l}\t{$src, $dst|$dst, $src}",
1826 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1827 (implicit EFLAGS)]>;
1828 def AND16mi8 : Ii8<0x83, MRM4m,
1829 (outs), (ins i16mem:$dst, i16i8imm :$src),
1830 "and{w}\t{$src, $dst|$dst, $src}",
1831 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1832 (implicit EFLAGS)]>,
1834 def AND32mi8 : Ii8<0x83, MRM4m,
1835 (outs), (ins i32mem:$dst, i32i8imm :$src),
1836 "and{l}\t{$src, $dst|$dst, $src}",
1837 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1838 (implicit EFLAGS)]>;
1840 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1841 "and{b}\t{$src, %al|%al, $src}", []>;
1842 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1843 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1844 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1845 "and{l}\t{$src, %eax|%eax, $src}", []>;
1850 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1851 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1852 (ins GR8 :$src1, GR8 :$src2),
1853 "or{b}\t{$src2, $dst|$dst, $src2}",
1854 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
1855 (implicit EFLAGS)]>;
1856 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1857 (ins GR16:$src1, GR16:$src2),
1858 "or{w}\t{$src2, $dst|$dst, $src2}",
1859 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
1860 (implicit EFLAGS)]>, OpSize;
1861 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1862 (ins GR32:$src1, GR32:$src2),
1863 "or{l}\t{$src2, $dst|$dst, $src2}",
1864 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
1865 (implicit EFLAGS)]>;
1868 // OR instructions with the destination register in REG and the source register
1869 // in R/M. Included for the disassembler.
1870 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1871 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1872 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1873 (ins GR16:$src1, GR16:$src2),
1874 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1875 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1876 (ins GR32:$src1, GR32:$src2),
1877 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
1879 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst),
1880 (ins GR8 :$src1, i8mem :$src2),
1881 "or{b}\t{$src2, $dst|$dst, $src2}",
1882 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
1883 (implicit EFLAGS)]>;
1884 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst),
1885 (ins GR16:$src1, i16mem:$src2),
1886 "or{w}\t{$src2, $dst|$dst, $src2}",
1887 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
1888 (implicit EFLAGS)]>, OpSize;
1889 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst),
1890 (ins GR32:$src1, i32mem:$src2),
1891 "or{l}\t{$src2, $dst|$dst, $src2}",
1892 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
1893 (implicit EFLAGS)]>;
1895 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
1896 (ins GR8 :$src1, i8imm:$src2),
1897 "or{b}\t{$src2, $dst|$dst, $src2}",
1898 [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
1899 (implicit EFLAGS)]>;
1900 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
1901 (ins GR16:$src1, i16imm:$src2),
1902 "or{w}\t{$src2, $dst|$dst, $src2}",
1903 [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
1904 (implicit EFLAGS)]>, OpSize;
1905 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
1906 (ins GR32:$src1, i32imm:$src2),
1907 "or{l}\t{$src2, $dst|$dst, $src2}",
1908 [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
1909 (implicit EFLAGS)]>;
1911 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
1912 (ins GR16:$src1, i16i8imm:$src2),
1913 "or{w}\t{$src2, $dst|$dst, $src2}",
1914 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
1915 (implicit EFLAGS)]>, OpSize;
1916 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
1917 (ins GR32:$src1, i32i8imm:$src2),
1918 "or{l}\t{$src2, $dst|$dst, $src2}",
1919 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
1920 (implicit EFLAGS)]>;
1921 let isTwoAddress = 0 in {
1922 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1923 "or{b}\t{$src, $dst|$dst, $src}",
1924 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1925 (implicit EFLAGS)]>;
1926 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1927 "or{w}\t{$src, $dst|$dst, $src}",
1928 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1929 (implicit EFLAGS)]>, OpSize;
1930 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1931 "or{l}\t{$src, $dst|$dst, $src}",
1932 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1933 (implicit EFLAGS)]>;
1934 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1935 "or{b}\t{$src, $dst|$dst, $src}",
1936 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1937 (implicit EFLAGS)]>;
1938 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1939 "or{w}\t{$src, $dst|$dst, $src}",
1940 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1941 (implicit EFLAGS)]>,
1943 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1944 "or{l}\t{$src, $dst|$dst, $src}",
1945 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1946 (implicit EFLAGS)]>;
1947 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1948 "or{w}\t{$src, $dst|$dst, $src}",
1949 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1950 (implicit EFLAGS)]>,
1952 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1953 "or{l}\t{$src, $dst|$dst, $src}",
1954 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1955 (implicit EFLAGS)]>;
1957 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
1958 "or{b}\t{$src, %al|%al, $src}", []>;
1959 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
1960 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1961 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
1962 "or{l}\t{$src, %eax|%eax, $src}", []>;
1963 } // isTwoAddress = 0
1966 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1967 def XOR8rr : I<0x30, MRMDestReg,
1968 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1969 "xor{b}\t{$src2, $dst|$dst, $src2}",
1970 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
1971 (implicit EFLAGS)]>;
1972 def XOR16rr : I<0x31, MRMDestReg,
1973 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1974 "xor{w}\t{$src2, $dst|$dst, $src2}",
1975 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
1976 (implicit EFLAGS)]>, OpSize;
1977 def XOR32rr : I<0x31, MRMDestReg,
1978 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1979 "xor{l}\t{$src2, $dst|$dst, $src2}",
1980 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
1981 (implicit EFLAGS)]>;
1982 } // isCommutable = 1
1984 // XOR instructions with the destination register in REG and the source register
1985 // in R/M. Included for the disassembler.
1986 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1987 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
1988 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
1989 (ins GR16:$src1, GR16:$src2),
1990 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1991 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
1992 (ins GR32:$src1, GR32:$src2),
1993 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
1995 def XOR8rm : I<0x32, MRMSrcMem ,
1996 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1997 "xor{b}\t{$src2, $dst|$dst, $src2}",
1998 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
1999 (implicit EFLAGS)]>;
2000 def XOR16rm : I<0x33, MRMSrcMem ,
2001 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2002 "xor{w}\t{$src2, $dst|$dst, $src2}",
2003 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
2004 (implicit EFLAGS)]>,
2006 def XOR32rm : I<0x33, MRMSrcMem ,
2007 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2008 "xor{l}\t{$src2, $dst|$dst, $src2}",
2009 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
2010 (implicit EFLAGS)]>;
2012 def XOR8ri : Ii8<0x80, MRM6r,
2013 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2014 "xor{b}\t{$src2, $dst|$dst, $src2}",
2015 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
2016 (implicit EFLAGS)]>;
2017 def XOR16ri : Ii16<0x81, MRM6r,
2018 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2019 "xor{w}\t{$src2, $dst|$dst, $src2}",
2020 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
2021 (implicit EFLAGS)]>, OpSize;
2022 def XOR32ri : Ii32<0x81, MRM6r,
2023 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2024 "xor{l}\t{$src2, $dst|$dst, $src2}",
2025 [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
2026 (implicit EFLAGS)]>;
2027 def XOR16ri8 : Ii8<0x83, MRM6r,
2028 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2029 "xor{w}\t{$src2, $dst|$dst, $src2}",
2030 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
2031 (implicit EFLAGS)]>,
2033 def XOR32ri8 : Ii8<0x83, MRM6r,
2034 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2035 "xor{l}\t{$src2, $dst|$dst, $src2}",
2036 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
2037 (implicit EFLAGS)]>;
2039 let isTwoAddress = 0 in {
2040 def XOR8mr : I<0x30, MRMDestMem,
2041 (outs), (ins i8mem :$dst, GR8 :$src),
2042 "xor{b}\t{$src, $dst|$dst, $src}",
2043 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
2044 (implicit EFLAGS)]>;
2045 def XOR16mr : I<0x31, MRMDestMem,
2046 (outs), (ins i16mem:$dst, GR16:$src),
2047 "xor{w}\t{$src, $dst|$dst, $src}",
2048 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
2049 (implicit EFLAGS)]>,
2051 def XOR32mr : I<0x31, MRMDestMem,
2052 (outs), (ins i32mem:$dst, GR32:$src),
2053 "xor{l}\t{$src, $dst|$dst, $src}",
2054 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
2055 (implicit EFLAGS)]>;
2056 def XOR8mi : Ii8<0x80, MRM6m,
2057 (outs), (ins i8mem :$dst, i8imm :$src),
2058 "xor{b}\t{$src, $dst|$dst, $src}",
2059 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
2060 (implicit EFLAGS)]>;
2061 def XOR16mi : Ii16<0x81, MRM6m,
2062 (outs), (ins i16mem:$dst, i16imm:$src),
2063 "xor{w}\t{$src, $dst|$dst, $src}",
2064 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
2065 (implicit EFLAGS)]>,
2067 def XOR32mi : Ii32<0x81, MRM6m,
2068 (outs), (ins i32mem:$dst, i32imm:$src),
2069 "xor{l}\t{$src, $dst|$dst, $src}",
2070 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
2071 (implicit EFLAGS)]>;
2072 def XOR16mi8 : Ii8<0x83, MRM6m,
2073 (outs), (ins i16mem:$dst, i16i8imm :$src),
2074 "xor{w}\t{$src, $dst|$dst, $src}",
2075 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
2076 (implicit EFLAGS)]>,
2078 def XOR32mi8 : Ii8<0x83, MRM6m,
2079 (outs), (ins i32mem:$dst, i32i8imm :$src),
2080 "xor{l}\t{$src, $dst|$dst, $src}",
2081 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
2082 (implicit EFLAGS)]>;
2084 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
2085 "xor{b}\t{$src, %al|%al, $src}", []>;
2086 def XOR16i16 : Ii16 <0x35, RawFrm, (outs), (ins i16imm:$src),
2087 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2088 def XOR32i32 : Ii32 <0x35, RawFrm, (outs), (ins i32imm:$src),
2089 "xor{l}\t{$src, %eax|%eax, $src}", []>;
2090 } // isTwoAddress = 0
2091 } // Defs = [EFLAGS]
2093 // Shift instructions
2094 let Defs = [EFLAGS] in {
2095 let Uses = [CL] in {
2096 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
2097 "shl{b}\t{%cl, $dst|$dst, CL}",
2098 [(set GR8:$dst, (shl GR8:$src, CL))]>;
2099 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
2100 "shl{w}\t{%cl, $dst|$dst, CL}",
2101 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
2102 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
2103 "shl{l}\t{%cl, $dst|$dst, CL}",
2104 [(set GR32:$dst, (shl GR32:$src, CL))]>;
2107 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2108 "shl{b}\t{$src2, $dst|$dst, $src2}",
2109 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
2110 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2111 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2112 "shl{w}\t{$src2, $dst|$dst, $src2}",
2113 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2114 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2115 "shl{l}\t{$src2, $dst|$dst, $src2}",
2116 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
2118 // NOTE: We don't include patterns for shifts of a register by one, because
2119 // 'add reg,reg' is cheaper.
2121 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
2122 "shl{b}\t$dst", []>;
2123 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2124 "shl{w}\t$dst", []>, OpSize;
2125 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2126 "shl{l}\t$dst", []>;
2128 } // isConvertibleToThreeAddress = 1
2130 let isTwoAddress = 0 in {
2131 let Uses = [CL] in {
2132 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
2133 "shl{b}\t{%cl, $dst|$dst, CL}",
2134 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
2135 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
2136 "shl{w}\t{%cl, $dst|$dst, CL}",
2137 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2138 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
2139 "shl{l}\t{%cl, $dst|$dst, CL}",
2140 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
2142 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
2143 "shl{b}\t{$src, $dst|$dst, $src}",
2144 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2145 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
2146 "shl{w}\t{$src, $dst|$dst, $src}",
2147 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2149 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
2150 "shl{l}\t{$src, $dst|$dst, $src}",
2151 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2154 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
2156 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2157 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
2159 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2161 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2163 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2166 let Uses = [CL] in {
2167 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
2168 "shr{b}\t{%cl, $dst|$dst, CL}",
2169 [(set GR8:$dst, (srl GR8:$src, CL))]>;
2170 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
2171 "shr{w}\t{%cl, $dst|$dst, CL}",
2172 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
2173 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
2174 "shr{l}\t{%cl, $dst|$dst, CL}",
2175 [(set GR32:$dst, (srl GR32:$src, CL))]>;
2178 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2179 "shr{b}\t{$src2, $dst|$dst, $src2}",
2180 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2181 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2182 "shr{w}\t{$src2, $dst|$dst, $src2}",
2183 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2184 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2185 "shr{l}\t{$src2, $dst|$dst, $src2}",
2186 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2189 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2191 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2192 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2194 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2195 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2197 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2199 let isTwoAddress = 0 in {
2200 let Uses = [CL] in {
2201 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2202 "shr{b}\t{%cl, $dst|$dst, CL}",
2203 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2204 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2205 "shr{w}\t{%cl, $dst|$dst, CL}",
2206 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2208 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2209 "shr{l}\t{%cl, $dst|$dst, CL}",
2210 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2212 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2213 "shr{b}\t{$src, $dst|$dst, $src}",
2214 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2215 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2216 "shr{w}\t{$src, $dst|$dst, $src}",
2217 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2219 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2220 "shr{l}\t{$src, $dst|$dst, $src}",
2221 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2224 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2226 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2227 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2229 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2230 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2232 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2235 let Uses = [CL] in {
2236 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
2237 "sar{b}\t{%cl, $dst|$dst, CL}",
2238 [(set GR8:$dst, (sra GR8:$src, CL))]>;
2239 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
2240 "sar{w}\t{%cl, $dst|$dst, CL}",
2241 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
2242 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
2243 "sar{l}\t{%cl, $dst|$dst, CL}",
2244 [(set GR32:$dst, (sra GR32:$src, CL))]>;
2247 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2248 "sar{b}\t{$src2, $dst|$dst, $src2}",
2249 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2250 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2251 "sar{w}\t{$src2, $dst|$dst, $src2}",
2252 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2254 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2255 "sar{l}\t{$src2, $dst|$dst, $src2}",
2256 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2259 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2261 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2262 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2264 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2265 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2267 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2269 let isTwoAddress = 0 in {
2270 let Uses = [CL] in {
2271 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2272 "sar{b}\t{%cl, $dst|$dst, CL}",
2273 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2274 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2275 "sar{w}\t{%cl, $dst|$dst, CL}",
2276 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2277 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2278 "sar{l}\t{%cl, $dst|$dst, CL}",
2279 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2281 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2282 "sar{b}\t{$src, $dst|$dst, $src}",
2283 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2284 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2285 "sar{w}\t{$src, $dst|$dst, $src}",
2286 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2288 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2289 "sar{l}\t{$src, $dst|$dst, $src}",
2290 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2293 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2295 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2296 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2298 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2300 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2302 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2305 // Rotate instructions
2307 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2308 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2309 let Uses = [CL] in {
2310 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2311 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2313 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2314 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2316 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2317 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2318 let Uses = [CL] in {
2319 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2320 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2322 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2323 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2325 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2326 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2327 let Uses = [CL] in {
2328 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2329 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2331 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2332 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2334 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2335 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2336 let Uses = [CL] in {
2337 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2338 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2340 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2341 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2343 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2344 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2345 let Uses = [CL] in {
2346 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2347 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2349 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2350 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2352 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2353 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2354 let Uses = [CL] in {
2355 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2356 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2358 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2359 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2361 let isTwoAddress = 0 in {
2362 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
2363 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2364 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2365 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2366 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
2367 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2368 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2369 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2370 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
2371 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2372 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2373 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2374 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
2375 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2376 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2377 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2378 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
2379 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2380 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2381 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2382 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
2383 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2384 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2385 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2387 let Uses = [CL] in {
2388 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
2389 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2390 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
2391 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2392 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
2393 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2394 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
2395 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2396 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
2397 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2398 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
2399 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2403 // FIXME: provide shorter instructions when imm8 == 1
2404 let Uses = [CL] in {
2405 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
2406 "rol{b}\t{%cl, $dst|$dst, CL}",
2407 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
2408 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
2409 "rol{w}\t{%cl, $dst|$dst, CL}",
2410 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
2411 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
2412 "rol{l}\t{%cl, $dst|$dst, CL}",
2413 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2416 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2417 "rol{b}\t{$src2, $dst|$dst, $src2}",
2418 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2419 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2420 "rol{w}\t{$src2, $dst|$dst, $src2}",
2421 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2423 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2424 "rol{l}\t{$src2, $dst|$dst, $src2}",
2425 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2428 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2430 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2431 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2433 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2434 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2436 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2438 let isTwoAddress = 0 in {
2439 let Uses = [CL] in {
2440 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2441 "rol{b}\t{%cl, $dst|$dst, CL}",
2442 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2443 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2444 "rol{w}\t{%cl, $dst|$dst, CL}",
2445 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2446 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2447 "rol{l}\t{%cl, $dst|$dst, CL}",
2448 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2450 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2451 "rol{b}\t{$src, $dst|$dst, $src}",
2452 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2453 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2454 "rol{w}\t{$src, $dst|$dst, $src}",
2455 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2457 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2458 "rol{l}\t{$src, $dst|$dst, $src}",
2459 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2462 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2464 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2465 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2467 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2469 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2471 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2474 let Uses = [CL] in {
2475 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2476 "ror{b}\t{%cl, $dst|$dst, CL}",
2477 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2478 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2479 "ror{w}\t{%cl, $dst|$dst, CL}",
2480 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2481 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2482 "ror{l}\t{%cl, $dst|$dst, CL}",
2483 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2486 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2487 "ror{b}\t{$src2, $dst|$dst, $src2}",
2488 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2489 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2490 "ror{w}\t{$src2, $dst|$dst, $src2}",
2491 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2493 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2494 "ror{l}\t{$src2, $dst|$dst, $src2}",
2495 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2498 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2500 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2501 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2503 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2504 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2506 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2508 let isTwoAddress = 0 in {
2509 let Uses = [CL] in {
2510 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2511 "ror{b}\t{%cl, $dst|$dst, CL}",
2512 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2513 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2514 "ror{w}\t{%cl, $dst|$dst, CL}",
2515 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2516 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2517 "ror{l}\t{%cl, $dst|$dst, CL}",
2518 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2520 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2521 "ror{b}\t{$src, $dst|$dst, $src}",
2522 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2523 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2524 "ror{w}\t{$src, $dst|$dst, $src}",
2525 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2527 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2528 "ror{l}\t{$src, $dst|$dst, $src}",
2529 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2532 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2534 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2535 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2537 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2539 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2541 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2546 // Double shift instructions (generalizations of rotate)
2547 let Uses = [CL] in {
2548 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2549 (ins GR32:$src1, GR32:$src2),
2550 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2551 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2552 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2553 (ins GR32:$src1, GR32:$src2),
2554 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2555 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2556 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2557 (ins GR16:$src1, GR16:$src2),
2558 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2559 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2561 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2562 (ins GR16:$src1, GR16:$src2),
2563 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2564 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2568 let isCommutable = 1 in { // These instructions commute to each other.
2569 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2571 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2572 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2573 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2576 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2578 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2579 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2580 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2583 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2585 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2586 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2587 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2590 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2592 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2593 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2594 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2599 let isTwoAddress = 0 in {
2600 let Uses = [CL] in {
2601 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2602 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2603 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2605 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2606 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2607 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2610 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2611 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2612 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2613 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2614 (i8 imm:$src3)), addr:$dst)]>,
2616 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2617 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2618 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2619 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2620 (i8 imm:$src3)), addr:$dst)]>,
2623 let Uses = [CL] in {
2624 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2625 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2626 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2627 addr:$dst)]>, TB, OpSize;
2628 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2629 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2630 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2631 addr:$dst)]>, TB, OpSize;
2633 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2634 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2635 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2636 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2637 (i8 imm:$src3)), addr:$dst)]>,
2639 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2640 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2641 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2642 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2643 (i8 imm:$src3)), addr:$dst)]>,
2646 } // Defs = [EFLAGS]
2650 let Defs = [EFLAGS] in {
2651 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2652 // Register-Register Addition
2653 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2654 (ins GR8 :$src1, GR8 :$src2),
2655 "add{b}\t{$src2, $dst|$dst, $src2}",
2656 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
2657 (implicit EFLAGS)]>;
2659 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2660 // Register-Register Addition
2661 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2662 (ins GR16:$src1, GR16:$src2),
2663 "add{w}\t{$src2, $dst|$dst, $src2}",
2664 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2665 (implicit EFLAGS)]>, OpSize;
2666 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2667 (ins GR32:$src1, GR32:$src2),
2668 "add{l}\t{$src2, $dst|$dst, $src2}",
2669 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2670 (implicit EFLAGS)]>;
2671 } // end isConvertibleToThreeAddress
2672 } // end isCommutable
2674 // Register-Memory Addition
2675 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2676 (ins GR8 :$src1, i8mem :$src2),
2677 "add{b}\t{$src2, $dst|$dst, $src2}",
2678 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2679 (implicit EFLAGS)]>;
2680 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2681 (ins GR16:$src1, i16mem:$src2),
2682 "add{w}\t{$src2, $dst|$dst, $src2}",
2683 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2684 (implicit EFLAGS)]>, OpSize;
2685 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2686 (ins GR32:$src1, i32mem:$src2),
2687 "add{l}\t{$src2, $dst|$dst, $src2}",
2688 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2689 (implicit EFLAGS)]>;
2691 // Register-Register Addition - Equivalent to the normal rr forms (ADD8rr,
2692 // ADD16rr, and ADD32rr), but differently encoded.
2693 def ADD8mrmrr: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2694 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2695 def ADD16mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2696 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2697 def ADD32mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2698 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2700 // Register-Integer Addition
2701 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2702 "add{b}\t{$src2, $dst|$dst, $src2}",
2703 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2704 (implicit EFLAGS)]>;
2706 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2707 // Register-Integer Addition
2708 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2709 (ins GR16:$src1, i16imm:$src2),
2710 "add{w}\t{$src2, $dst|$dst, $src2}",
2711 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2712 (implicit EFLAGS)]>, OpSize;
2713 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2714 (ins GR32:$src1, i32imm:$src2),
2715 "add{l}\t{$src2, $dst|$dst, $src2}",
2716 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2717 (implicit EFLAGS)]>;
2718 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2719 (ins GR16:$src1, i16i8imm:$src2),
2720 "add{w}\t{$src2, $dst|$dst, $src2}",
2721 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2722 (implicit EFLAGS)]>, OpSize;
2723 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2724 (ins GR32:$src1, i32i8imm:$src2),
2725 "add{l}\t{$src2, $dst|$dst, $src2}",
2726 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2727 (implicit EFLAGS)]>;
2730 let isTwoAddress = 0 in {
2731 // Memory-Register Addition
2732 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2733 "add{b}\t{$src2, $dst|$dst, $src2}",
2734 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2735 (implicit EFLAGS)]>;
2736 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2737 "add{w}\t{$src2, $dst|$dst, $src2}",
2738 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2739 (implicit EFLAGS)]>, OpSize;
2740 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2741 "add{l}\t{$src2, $dst|$dst, $src2}",
2742 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2743 (implicit EFLAGS)]>;
2744 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2745 "add{b}\t{$src2, $dst|$dst, $src2}",
2746 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2747 (implicit EFLAGS)]>;
2748 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2749 "add{w}\t{$src2, $dst|$dst, $src2}",
2750 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2751 (implicit EFLAGS)]>, OpSize;
2752 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2753 "add{l}\t{$src2, $dst|$dst, $src2}",
2754 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2755 (implicit EFLAGS)]>;
2756 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2757 "add{w}\t{$src2, $dst|$dst, $src2}",
2758 [(store (add (load addr:$dst), i16immSExt8:$src2),
2760 (implicit EFLAGS)]>, OpSize;
2761 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2762 "add{l}\t{$src2, $dst|$dst, $src2}",
2763 [(store (add (load addr:$dst), i32immSExt8:$src2),
2765 (implicit EFLAGS)]>;
2768 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2769 "add{b}\t{$src, %al|%al, $src}", []>;
2770 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2771 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2772 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2773 "add{l}\t{$src, %eax|%eax, $src}", []>;
2776 let Uses = [EFLAGS] in {
2777 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2778 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2779 "adc{b}\t{$src2, $dst|$dst, $src2}",
2780 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2781 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2782 (ins GR16:$src1, GR16:$src2),
2783 "adc{w}\t{$src2, $dst|$dst, $src2}",
2784 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2785 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2786 (ins GR32:$src1, GR32:$src2),
2787 "adc{l}\t{$src2, $dst|$dst, $src2}",
2788 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2791 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2792 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2793 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2794 (ins GR16:$src1, GR16:$src2),
2795 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2796 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2797 (ins GR32:$src1, GR32:$src2),
2798 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2800 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2801 (ins GR8:$src1, i8mem:$src2),
2802 "adc{b}\t{$src2, $dst|$dst, $src2}",
2803 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2804 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2805 (ins GR16:$src1, i16mem:$src2),
2806 "adc{w}\t{$src2, $dst|$dst, $src2}",
2807 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2809 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2810 (ins GR32:$src1, i32mem:$src2),
2811 "adc{l}\t{$src2, $dst|$dst, $src2}",
2812 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2813 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2814 "adc{b}\t{$src2, $dst|$dst, $src2}",
2815 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2816 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2817 (ins GR16:$src1, i16imm:$src2),
2818 "adc{w}\t{$src2, $dst|$dst, $src2}",
2819 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2820 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2821 (ins GR16:$src1, i16i8imm:$src2),
2822 "adc{w}\t{$src2, $dst|$dst, $src2}",
2823 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2825 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2826 (ins GR32:$src1, i32imm:$src2),
2827 "adc{l}\t{$src2, $dst|$dst, $src2}",
2828 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2829 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2830 (ins GR32:$src1, i32i8imm:$src2),
2831 "adc{l}\t{$src2, $dst|$dst, $src2}",
2832 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2834 let isTwoAddress = 0 in {
2835 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2836 "adc{b}\t{$src2, $dst|$dst, $src2}",
2837 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2838 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2839 "adc{w}\t{$src2, $dst|$dst, $src2}",
2840 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2842 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2843 "adc{l}\t{$src2, $dst|$dst, $src2}",
2844 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2845 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2846 "adc{b}\t{$src2, $dst|$dst, $src2}",
2847 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2848 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2849 "adc{w}\t{$src2, $dst|$dst, $src2}",
2850 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2852 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2853 "adc{w}\t{$src2, $dst|$dst, $src2}",
2854 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2856 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2857 "adc{l}\t{$src2, $dst|$dst, $src2}",
2858 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2859 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2860 "adc{l}\t{$src2, $dst|$dst, $src2}",
2861 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2863 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2864 "adc{b}\t{$src, %al|%al, $src}", []>;
2865 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2866 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2867 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2868 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2870 } // Uses = [EFLAGS]
2872 // Register-Register Subtraction
2873 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2874 "sub{b}\t{$src2, $dst|$dst, $src2}",
2875 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2876 (implicit EFLAGS)]>;
2877 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2878 "sub{w}\t{$src2, $dst|$dst, $src2}",
2879 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2880 (implicit EFLAGS)]>, OpSize;
2881 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2882 "sub{l}\t{$src2, $dst|$dst, $src2}",
2883 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2884 (implicit EFLAGS)]>;
2886 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2887 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
2888 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
2889 (ins GR16:$src1, GR16:$src2),
2890 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2891 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
2892 (ins GR32:$src1, GR32:$src2),
2893 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
2895 // Register-Memory Subtraction
2896 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2897 (ins GR8 :$src1, i8mem :$src2),
2898 "sub{b}\t{$src2, $dst|$dst, $src2}",
2899 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2900 (implicit EFLAGS)]>;
2901 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2902 (ins GR16:$src1, i16mem:$src2),
2903 "sub{w}\t{$src2, $dst|$dst, $src2}",
2904 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2905 (implicit EFLAGS)]>, OpSize;
2906 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2907 (ins GR32:$src1, i32mem:$src2),
2908 "sub{l}\t{$src2, $dst|$dst, $src2}",
2909 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2910 (implicit EFLAGS)]>;
2912 // Register-Integer Subtraction
2913 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2914 (ins GR8:$src1, i8imm:$src2),
2915 "sub{b}\t{$src2, $dst|$dst, $src2}",
2916 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2917 (implicit EFLAGS)]>;
2918 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2919 (ins GR16:$src1, i16imm:$src2),
2920 "sub{w}\t{$src2, $dst|$dst, $src2}",
2921 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2922 (implicit EFLAGS)]>, OpSize;
2923 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2924 (ins GR32:$src1, i32imm:$src2),
2925 "sub{l}\t{$src2, $dst|$dst, $src2}",
2926 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2927 (implicit EFLAGS)]>;
2928 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2929 (ins GR16:$src1, i16i8imm:$src2),
2930 "sub{w}\t{$src2, $dst|$dst, $src2}",
2931 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2932 (implicit EFLAGS)]>, OpSize;
2933 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2934 (ins GR32:$src1, i32i8imm:$src2),
2935 "sub{l}\t{$src2, $dst|$dst, $src2}",
2936 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2937 (implicit EFLAGS)]>;
2939 let isTwoAddress = 0 in {
2940 // Memory-Register Subtraction
2941 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2942 "sub{b}\t{$src2, $dst|$dst, $src2}",
2943 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2944 (implicit EFLAGS)]>;
2945 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2946 "sub{w}\t{$src2, $dst|$dst, $src2}",
2947 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2948 (implicit EFLAGS)]>, OpSize;
2949 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2950 "sub{l}\t{$src2, $dst|$dst, $src2}",
2951 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2952 (implicit EFLAGS)]>;
2954 // Memory-Integer Subtraction
2955 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2956 "sub{b}\t{$src2, $dst|$dst, $src2}",
2957 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2958 (implicit EFLAGS)]>;
2959 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2960 "sub{w}\t{$src2, $dst|$dst, $src2}",
2961 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2962 (implicit EFLAGS)]>, OpSize;
2963 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2964 "sub{l}\t{$src2, $dst|$dst, $src2}",
2965 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2966 (implicit EFLAGS)]>;
2967 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2968 "sub{w}\t{$src2, $dst|$dst, $src2}",
2969 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2971 (implicit EFLAGS)]>, OpSize;
2972 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2973 "sub{l}\t{$src2, $dst|$dst, $src2}",
2974 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2976 (implicit EFLAGS)]>;
2978 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
2979 "sub{b}\t{$src, %al|%al, $src}", []>;
2980 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
2981 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2982 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
2983 "sub{l}\t{$src, %eax|%eax, $src}", []>;
2986 let Uses = [EFLAGS] in {
2987 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
2988 (ins GR8:$src1, GR8:$src2),
2989 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2990 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
2991 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
2992 (ins GR16:$src1, GR16:$src2),
2993 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2994 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
2995 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
2996 (ins GR32:$src1, GR32:$src2),
2997 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2998 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
3000 let isTwoAddress = 0 in {
3001 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3002 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3003 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
3004 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3005 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3006 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
3008 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3009 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3010 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
3011 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
3012 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3013 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
3014 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
3015 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3016 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
3018 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3019 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3020 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
3022 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
3023 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3024 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
3025 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3026 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3027 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
3029 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
3030 "sbb{b}\t{$src, %al|%al, $src}", []>;
3031 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
3032 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3033 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
3034 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
3037 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3038 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
3039 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
3040 (ins GR16:$src1, GR16:$src2),
3041 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3042 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
3043 (ins GR32:$src1, GR32:$src2),
3044 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
3046 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
3047 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3048 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
3049 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
3050 (ins GR16:$src1, i16mem:$src2),
3051 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3052 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
3054 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
3055 (ins GR32:$src1, i32mem:$src2),
3056 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3057 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
3058 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
3059 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3060 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
3061 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
3062 (ins GR16:$src1, i16imm:$src2),
3063 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3064 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
3065 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
3066 (ins GR16:$src1, i16i8imm:$src2),
3067 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3068 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
3070 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
3071 (ins GR32:$src1, i32imm:$src2),
3072 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3073 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
3074 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
3075 (ins GR32:$src1, i32i8imm:$src2),
3076 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3077 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
3078 } // Uses = [EFLAGS]
3079 } // Defs = [EFLAGS]
3081 let Defs = [EFLAGS] in {
3082 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
3083 // Register-Register Signed Integer Multiply
3084 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3085 "imul{w}\t{$src2, $dst|$dst, $src2}",
3086 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
3087 (implicit EFLAGS)]>, TB, OpSize;
3088 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3089 "imul{l}\t{$src2, $dst|$dst, $src2}",
3090 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
3091 (implicit EFLAGS)]>, TB;
3094 // Register-Memory Signed Integer Multiply
3095 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
3096 (ins GR16:$src1, i16mem:$src2),
3097 "imul{w}\t{$src2, $dst|$dst, $src2}",
3098 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
3099 (implicit EFLAGS)]>, TB, OpSize;
3100 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
3101 (ins GR32:$src1, i32mem:$src2),
3102 "imul{l}\t{$src2, $dst|$dst, $src2}",
3103 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
3104 (implicit EFLAGS)]>, TB;
3105 } // Defs = [EFLAGS]
3106 } // end Two Address instructions
3108 // Suprisingly enough, these are not two address instructions!
3109 let Defs = [EFLAGS] in {
3110 // Register-Integer Signed Integer Multiply
3111 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
3112 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
3113 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3114 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
3115 (implicit EFLAGS)]>, OpSize;
3116 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
3117 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
3118 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3119 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
3120 (implicit EFLAGS)]>;
3121 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
3122 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
3123 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3124 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
3125 (implicit EFLAGS)]>, OpSize;
3126 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
3127 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
3128 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3129 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
3130 (implicit EFLAGS)]>;
3132 // Memory-Integer Signed Integer Multiply
3133 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
3134 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
3135 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3136 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
3137 (implicit EFLAGS)]>, OpSize;
3138 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
3139 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
3140 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3141 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
3142 (implicit EFLAGS)]>;
3143 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
3144 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
3145 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3146 [(set GR16:$dst, (mul (load addr:$src1),
3147 i16immSExt8:$src2)),
3148 (implicit EFLAGS)]>, OpSize;
3149 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
3150 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
3151 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3152 [(set GR32:$dst, (mul (load addr:$src1),
3153 i32immSExt8:$src2)),
3154 (implicit EFLAGS)]>;
3155 } // Defs = [EFLAGS]
3157 //===----------------------------------------------------------------------===//
3158 // Test instructions are just like AND, except they don't generate a result.
3160 let Defs = [EFLAGS] in {
3161 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
3162 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
3163 "test{b}\t{$src2, $src1|$src1, $src2}",
3164 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
3165 (implicit EFLAGS)]>;
3166 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3167 "test{w}\t{$src2, $src1|$src1, $src2}",
3168 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
3169 (implicit EFLAGS)]>,
3171 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3172 "test{l}\t{$src2, $src1|$src1, $src2}",
3173 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
3174 (implicit EFLAGS)]>;
3177 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
3178 "test{b}\t{$src, %al|%al, $src}", []>;
3179 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
3180 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3181 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
3182 "test{l}\t{$src, %eax|%eax, $src}", []>;
3184 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
3185 "test{b}\t{$src2, $src1|$src1, $src2}",
3186 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
3187 (implicit EFLAGS)]>;
3188 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
3189 "test{w}\t{$src2, $src1|$src1, $src2}",
3190 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
3191 (implicit EFLAGS)]>, OpSize;
3192 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
3193 "test{l}\t{$src2, $src1|$src1, $src2}",
3194 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
3195 (implicit EFLAGS)]>;
3197 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
3198 (outs), (ins GR8:$src1, i8imm:$src2),
3199 "test{b}\t{$src2, $src1|$src1, $src2}",
3200 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
3201 (implicit EFLAGS)]>;
3202 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
3203 (outs), (ins GR16:$src1, i16imm:$src2),
3204 "test{w}\t{$src2, $src1|$src1, $src2}",
3205 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
3206 (implicit EFLAGS)]>, OpSize;
3207 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
3208 (outs), (ins GR32:$src1, i32imm:$src2),
3209 "test{l}\t{$src2, $src1|$src1, $src2}",
3210 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
3211 (implicit EFLAGS)]>;
3213 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
3214 (outs), (ins i8mem:$src1, i8imm:$src2),
3215 "test{b}\t{$src2, $src1|$src1, $src2}",
3216 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
3217 (implicit EFLAGS)]>;
3218 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3219 (outs), (ins i16mem:$src1, i16imm:$src2),
3220 "test{w}\t{$src2, $src1|$src1, $src2}",
3221 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
3222 (implicit EFLAGS)]>, OpSize;
3223 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3224 (outs), (ins i32mem:$src1, i32imm:$src2),
3225 "test{l}\t{$src2, $src1|$src1, $src2}",
3226 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
3227 (implicit EFLAGS)]>;
3228 } // Defs = [EFLAGS]
3231 // Condition code ops, incl. set if equal/not equal/...
3232 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3233 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3234 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3235 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3237 let Uses = [EFLAGS] in {
3238 // Use sbb to materialize carry bit.
3239 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
3240 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
3241 // However, Pat<> can't replicate the destination reg into the inputs of the
3243 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
3245 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
3246 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3247 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
3248 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
3250 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
3251 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3254 def SETEr : I<0x94, MRM0r,
3255 (outs GR8 :$dst), (ins),
3257 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3259 def SETEm : I<0x94, MRM0m,
3260 (outs), (ins i8mem:$dst),
3262 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3265 def SETNEr : I<0x95, MRM0r,
3266 (outs GR8 :$dst), (ins),
3268 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3270 def SETNEm : I<0x95, MRM0m,
3271 (outs), (ins i8mem:$dst),
3273 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3276 def SETLr : I<0x9C, MRM0r,
3277 (outs GR8 :$dst), (ins),
3279 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3280 TB; // GR8 = < signed
3281 def SETLm : I<0x9C, MRM0m,
3282 (outs), (ins i8mem:$dst),
3284 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3285 TB; // [mem8] = < signed
3287 def SETGEr : I<0x9D, MRM0r,
3288 (outs GR8 :$dst), (ins),
3290 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3291 TB; // GR8 = >= signed
3292 def SETGEm : I<0x9D, MRM0m,
3293 (outs), (ins i8mem:$dst),
3295 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3296 TB; // [mem8] = >= signed
3298 def SETLEr : I<0x9E, MRM0r,
3299 (outs GR8 :$dst), (ins),
3301 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3302 TB; // GR8 = <= signed
3303 def SETLEm : I<0x9E, MRM0m,
3304 (outs), (ins i8mem:$dst),
3306 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3307 TB; // [mem8] = <= signed
3309 def SETGr : I<0x9F, MRM0r,
3310 (outs GR8 :$dst), (ins),
3312 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3313 TB; // GR8 = > signed
3314 def SETGm : I<0x9F, MRM0m,
3315 (outs), (ins i8mem:$dst),
3317 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3318 TB; // [mem8] = > signed
3320 def SETBr : I<0x92, MRM0r,
3321 (outs GR8 :$dst), (ins),
3323 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3324 TB; // GR8 = < unsign
3325 def SETBm : I<0x92, MRM0m,
3326 (outs), (ins i8mem:$dst),
3328 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3329 TB; // [mem8] = < unsign
3331 def SETAEr : I<0x93, MRM0r,
3332 (outs GR8 :$dst), (ins),
3334 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3335 TB; // GR8 = >= unsign
3336 def SETAEm : I<0x93, MRM0m,
3337 (outs), (ins i8mem:$dst),
3339 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3340 TB; // [mem8] = >= unsign
3342 def SETBEr : I<0x96, MRM0r,
3343 (outs GR8 :$dst), (ins),
3345 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3346 TB; // GR8 = <= unsign
3347 def SETBEm : I<0x96, MRM0m,
3348 (outs), (ins i8mem:$dst),
3350 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3351 TB; // [mem8] = <= unsign
3353 def SETAr : I<0x97, MRM0r,
3354 (outs GR8 :$dst), (ins),
3356 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3357 TB; // GR8 = > signed
3358 def SETAm : I<0x97, MRM0m,
3359 (outs), (ins i8mem:$dst),
3361 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3362 TB; // [mem8] = > signed
3364 def SETSr : I<0x98, MRM0r,
3365 (outs GR8 :$dst), (ins),
3367 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3368 TB; // GR8 = <sign bit>
3369 def SETSm : I<0x98, MRM0m,
3370 (outs), (ins i8mem:$dst),
3372 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3373 TB; // [mem8] = <sign bit>
3374 def SETNSr : I<0x99, MRM0r,
3375 (outs GR8 :$dst), (ins),
3377 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3378 TB; // GR8 = !<sign bit>
3379 def SETNSm : I<0x99, MRM0m,
3380 (outs), (ins i8mem:$dst),
3382 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3383 TB; // [mem8] = !<sign bit>
3385 def SETPr : I<0x9A, MRM0r,
3386 (outs GR8 :$dst), (ins),
3388 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3390 def SETPm : I<0x9A, MRM0m,
3391 (outs), (ins i8mem:$dst),
3393 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3394 TB; // [mem8] = parity
3395 def SETNPr : I<0x9B, MRM0r,
3396 (outs GR8 :$dst), (ins),
3398 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3399 TB; // GR8 = not parity
3400 def SETNPm : I<0x9B, MRM0m,
3401 (outs), (ins i8mem:$dst),
3403 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3404 TB; // [mem8] = not parity
3406 def SETOr : I<0x90, MRM0r,
3407 (outs GR8 :$dst), (ins),
3409 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3410 TB; // GR8 = overflow
3411 def SETOm : I<0x90, MRM0m,
3412 (outs), (ins i8mem:$dst),
3414 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3415 TB; // [mem8] = overflow
3416 def SETNOr : I<0x91, MRM0r,
3417 (outs GR8 :$dst), (ins),
3419 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3420 TB; // GR8 = not overflow
3421 def SETNOm : I<0x91, MRM0m,
3422 (outs), (ins i8mem:$dst),
3424 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3425 TB; // [mem8] = not overflow
3426 } // Uses = [EFLAGS]
3429 // Integer comparisons
3430 let Defs = [EFLAGS] in {
3431 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3432 "cmp{b}\t{$src, %al|%al, $src}", []>;
3433 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3434 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3435 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3436 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3438 def CMP8rr : I<0x38, MRMDestReg,
3439 (outs), (ins GR8 :$src1, GR8 :$src2),
3440 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3441 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
3442 def CMP16rr : I<0x39, MRMDestReg,
3443 (outs), (ins GR16:$src1, GR16:$src2),
3444 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3445 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
3446 def CMP32rr : I<0x39, MRMDestReg,
3447 (outs), (ins GR32:$src1, GR32:$src2),
3448 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3449 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
3450 def CMP8mr : I<0x38, MRMDestMem,
3451 (outs), (ins i8mem :$src1, GR8 :$src2),
3452 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3453 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
3454 (implicit EFLAGS)]>;
3455 def CMP16mr : I<0x39, MRMDestMem,
3456 (outs), (ins i16mem:$src1, GR16:$src2),
3457 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3458 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
3459 (implicit EFLAGS)]>, OpSize;
3460 def CMP32mr : I<0x39, MRMDestMem,
3461 (outs), (ins i32mem:$src1, GR32:$src2),
3462 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3463 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
3464 (implicit EFLAGS)]>;
3465 def CMP8rm : I<0x3A, MRMSrcMem,
3466 (outs), (ins GR8 :$src1, i8mem :$src2),
3467 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3468 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
3469 (implicit EFLAGS)]>;
3470 def CMP16rm : I<0x3B, MRMSrcMem,
3471 (outs), (ins GR16:$src1, i16mem:$src2),
3472 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3473 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
3474 (implicit EFLAGS)]>, OpSize;
3475 def CMP32rm : I<0x3B, MRMSrcMem,
3476 (outs), (ins GR32:$src1, i32mem:$src2),
3477 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3478 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
3479 (implicit EFLAGS)]>;
3480 def CMP8mrmrr : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3481 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3482 def CMP16mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3483 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3484 def CMP32mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3485 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3486 def CMP8ri : Ii8<0x80, MRM7r,
3487 (outs), (ins GR8:$src1, i8imm:$src2),
3488 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3489 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
3490 def CMP16ri : Ii16<0x81, MRM7r,
3491 (outs), (ins GR16:$src1, i16imm:$src2),
3492 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3493 [(X86cmp GR16:$src1, imm:$src2),
3494 (implicit EFLAGS)]>, OpSize;
3495 def CMP32ri : Ii32<0x81, MRM7r,
3496 (outs), (ins GR32:$src1, i32imm:$src2),
3497 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3498 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
3499 def CMP8mi : Ii8 <0x80, MRM7m,
3500 (outs), (ins i8mem :$src1, i8imm :$src2),
3501 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3502 [(X86cmp (loadi8 addr:$src1), imm:$src2),
3503 (implicit EFLAGS)]>;
3504 def CMP16mi : Ii16<0x81, MRM7m,
3505 (outs), (ins i16mem:$src1, i16imm:$src2),
3506 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3507 [(X86cmp (loadi16 addr:$src1), imm:$src2),
3508 (implicit EFLAGS)]>, OpSize;
3509 def CMP32mi : Ii32<0x81, MRM7m,
3510 (outs), (ins i32mem:$src1, i32imm:$src2),
3511 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3512 [(X86cmp (loadi32 addr:$src1), imm:$src2),
3513 (implicit EFLAGS)]>;
3514 def CMP16ri8 : Ii8<0x83, MRM7r,
3515 (outs), (ins GR16:$src1, i16i8imm:$src2),
3516 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3517 [(X86cmp GR16:$src1, i16immSExt8:$src2),
3518 (implicit EFLAGS)]>, OpSize;
3519 def CMP16mi8 : Ii8<0x83, MRM7m,
3520 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3521 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3522 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
3523 (implicit EFLAGS)]>, OpSize;
3524 def CMP32mi8 : Ii8<0x83, MRM7m,
3525 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3526 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3527 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
3528 (implicit EFLAGS)]>;
3529 def CMP32ri8 : Ii8<0x83, MRM7r,
3530 (outs), (ins GR32:$src1, i32i8imm:$src2),
3531 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3532 [(X86cmp GR32:$src1, i32immSExt8:$src2),
3533 (implicit EFLAGS)]>;
3534 } // Defs = [EFLAGS]
3537 // TODO: BTC, BTR, and BTS
3538 let Defs = [EFLAGS] in {
3539 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3540 "bt{w}\t{$src2, $src1|$src1, $src2}",
3541 [(X86bt GR16:$src1, GR16:$src2),
3542 (implicit EFLAGS)]>, OpSize, TB;
3543 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3544 "bt{l}\t{$src2, $src1|$src1, $src2}",
3545 [(X86bt GR32:$src1, GR32:$src2),
3546 (implicit EFLAGS)]>, TB;
3548 // Unlike with the register+register form, the memory+register form of the
3549 // bt instruction does not ignore the high bits of the index. From ISel's
3550 // perspective, this is pretty bizarre. Make these instructions disassembly
3553 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3554 "bt{w}\t{$src2, $src1|$src1, $src2}",
3555 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3556 // (implicit EFLAGS)]
3558 >, OpSize, TB, Requires<[FastBTMem]>;
3559 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3560 "bt{l}\t{$src2, $src1|$src1, $src2}",
3561 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3562 // (implicit EFLAGS)]
3564 >, TB, Requires<[FastBTMem]>;
3566 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3567 "bt{w}\t{$src2, $src1|$src1, $src2}",
3568 [(X86bt GR16:$src1, i16immSExt8:$src2),
3569 (implicit EFLAGS)]>, OpSize, TB;
3570 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3571 "bt{l}\t{$src2, $src1|$src1, $src2}",
3572 [(X86bt GR32:$src1, i32immSExt8:$src2),
3573 (implicit EFLAGS)]>, TB;
3574 // Note that these instructions don't need FastBTMem because that
3575 // only applies when the other operand is in a register. When it's
3576 // an immediate, bt is still fast.
3577 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3578 "bt{w}\t{$src2, $src1|$src1, $src2}",
3579 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
3580 (implicit EFLAGS)]>, OpSize, TB;
3581 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3582 "bt{l}\t{$src2, $src1|$src1, $src2}",
3583 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
3584 (implicit EFLAGS)]>, TB;
3586 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3587 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3588 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3589 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3590 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3591 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3592 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3593 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3594 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3595 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3596 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3597 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3598 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3599 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3600 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3601 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3603 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3604 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3605 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3606 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3607 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3608 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3609 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3610 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3611 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3612 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3613 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3614 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3615 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3616 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3617 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3618 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3620 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3621 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3622 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3623 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3624 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3625 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3626 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3627 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3628 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3629 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3630 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3631 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3632 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3633 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3634 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3635 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3636 } // Defs = [EFLAGS]
3638 // Sign/Zero extenders
3639 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3640 // of the register here. This has a smaller encoding and avoids a
3641 // partial-register update. Actual movsbw included for the disassembler.
3642 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3643 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3644 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3645 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3646 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3647 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3648 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3649 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3650 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3651 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3652 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3653 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3654 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3655 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3656 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3657 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3658 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3659 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3660 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3661 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3663 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3664 // of the register here. This has a smaller encoding and avoids a
3665 // partial-register update. Actual movzbw included for the disassembler.
3666 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3667 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3668 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3669 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3670 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3671 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3672 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3673 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3674 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3675 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3676 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3677 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3678 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3679 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3680 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3681 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3682 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3683 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3684 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3685 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3687 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
3688 // except that they use GR32_NOREX for the output operand register class
3689 // instead of GR32. This allows them to operate on h registers on x86-64.
3690 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3691 (outs GR32_NOREX:$dst), (ins GR8:$src),
3692 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3695 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3696 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3697 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3700 let neverHasSideEffects = 1 in {
3701 let Defs = [AX], Uses = [AL] in
3702 def CBW : I<0x98, RawFrm, (outs), (ins),
3703 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3704 let Defs = [EAX], Uses = [AX] in
3705 def CWDE : I<0x98, RawFrm, (outs), (ins),
3706 "{cwtl|cwde}", []>; // EAX = signext(AX)
3708 let Defs = [AX,DX], Uses = [AX] in
3709 def CWD : I<0x99, RawFrm, (outs), (ins),
3710 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3711 let Defs = [EAX,EDX], Uses = [EAX] in
3712 def CDQ : I<0x99, RawFrm, (outs), (ins),
3713 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3716 //===----------------------------------------------------------------------===//
3717 // Alias Instructions
3718 //===----------------------------------------------------------------------===//
3720 // Alias instructions that map movr0 to xor.
3721 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3722 // FIXME: Set encoding to pseudo.
3723 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3724 isCodeGenOnly = 1 in {
3725 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
3726 [(set GR8:$dst, 0)]>;
3728 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
3729 // encoding and avoids a partial-register update sometimes, but doing so
3730 // at isel time interferes with rematerialization in the current register
3731 // allocator. For now, this is rewritten when the instruction is lowered
3733 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3735 [(set GR16:$dst, 0)]>, OpSize;
3737 // FIXME: Set encoding to pseudo.
3738 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
3739 [(set GR32:$dst, 0)]>;
3742 //===----------------------------------------------------------------------===//
3743 // Thread Local Storage Instructions
3746 // All calls clobber the non-callee saved registers. ESP is marked as
3747 // a use to prevent stack-pointer assignments that appear immediately
3748 // before calls from potentially appearing dead.
3749 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3750 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3751 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3752 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3754 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3755 "leal\t$sym, %eax; "
3756 "call\t___tls_get_addr@PLT",
3757 [(X86tlsaddr tls32addr:$sym)]>,
3758 Requires<[In32BitMode]>;
3760 let AddedComplexity = 5, isCodeGenOnly = 1 in
3761 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3762 "movl\t%gs:$src, $dst",
3763 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3765 let AddedComplexity = 5, isCodeGenOnly = 1 in
3766 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3767 "movl\t%fs:$src, $dst",
3768 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3770 //===----------------------------------------------------------------------===//
3771 // EH Pseudo Instructions
3773 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3774 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3775 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3776 "ret\t#eh_return, addr: $addr",
3777 [(X86ehret GR32:$addr)]>;
3781 //===----------------------------------------------------------------------===//
3785 // Atomic swap. These are just normal xchg instructions. But since a memory
3786 // operand is referenced, the atomicity is ensured.
3787 let Constraints = "$val = $dst" in {
3788 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3789 (ins GR32:$val, i32mem:$ptr),
3790 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3791 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3792 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3793 (ins GR16:$val, i16mem:$ptr),
3794 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3795 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3797 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3798 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3799 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3801 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3802 "xchg{l}\t{$val, $src|$src, $val}", []>;
3803 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3804 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3805 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3806 "xchg{b}\t{$val, $src|$src, $val}", []>;
3809 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3810 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3811 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3812 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
3814 // Atomic compare and swap.
3815 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3816 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3818 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3819 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3821 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3822 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
3825 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3828 let Defs = [AX, EFLAGS], Uses = [AX] in {
3829 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3831 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3832 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3834 let Defs = [AL, EFLAGS], Uses = [AL] in {
3835 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3837 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3838 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3841 // Atomic exchange and add
3842 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3843 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
3845 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3846 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3848 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
3850 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3851 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3853 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3855 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3856 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3860 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3861 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3862 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3863 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3864 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3865 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3867 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3868 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3869 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3870 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3871 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3872 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3874 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3875 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3876 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3877 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3878 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3879 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3881 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3882 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3883 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3884 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3885 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3886 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3888 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
3889 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
3890 "cmpxchg8b\t$dst", []>, TB;
3892 // Optimized codegen when the non-memory output is not used.
3893 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3894 let Defs = [EFLAGS] in {
3895 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3897 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3898 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3900 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3901 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3903 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3904 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3906 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3907 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3909 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3910 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3912 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3913 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3915 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3916 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3918 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3920 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3922 "inc{b}\t$dst", []>, LOCK;
3923 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3925 "inc{w}\t$dst", []>, OpSize, LOCK;
3926 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3928 "inc{l}\t$dst", []>, LOCK;
3930 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3932 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3933 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3935 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3936 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3938 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3939 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3941 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3942 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3944 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3945 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3947 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3948 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3950 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3951 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3953 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3955 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3957 "dec{b}\t$dst", []>, LOCK;
3958 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3960 "dec{w}\t$dst", []>, OpSize, LOCK;
3961 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3963 "dec{l}\t$dst", []>, LOCK;
3966 // Atomic exchange, and, or, xor
3967 let Constraints = "$val = $dst", Defs = [EFLAGS],
3968 usesCustomInserter = 1 in {
3969 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3970 "#ATOMAND32 PSEUDO!",
3971 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3972 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3973 "#ATOMOR32 PSEUDO!",
3974 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
3975 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3976 "#ATOMXOR32 PSEUDO!",
3977 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
3978 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3979 "#ATOMNAND32 PSEUDO!",
3980 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
3981 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3982 "#ATOMMIN32 PSEUDO!",
3983 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
3984 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3985 "#ATOMMAX32 PSEUDO!",
3986 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
3987 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3988 "#ATOMUMIN32 PSEUDO!",
3989 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
3990 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3991 "#ATOMUMAX32 PSEUDO!",
3992 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
3994 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3995 "#ATOMAND16 PSEUDO!",
3996 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
3997 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3998 "#ATOMOR16 PSEUDO!",
3999 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
4000 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4001 "#ATOMXOR16 PSEUDO!",
4002 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
4003 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4004 "#ATOMNAND16 PSEUDO!",
4005 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
4006 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
4007 "#ATOMMIN16 PSEUDO!",
4008 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
4009 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4010 "#ATOMMAX16 PSEUDO!",
4011 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
4012 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4013 "#ATOMUMIN16 PSEUDO!",
4014 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
4015 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4016 "#ATOMUMAX16 PSEUDO!",
4017 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
4019 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4020 "#ATOMAND8 PSEUDO!",
4021 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
4022 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4024 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
4025 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4026 "#ATOMXOR8 PSEUDO!",
4027 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
4028 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4029 "#ATOMNAND8 PSEUDO!",
4030 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
4033 let Constraints = "$val1 = $dst1, $val2 = $dst2",
4034 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
4035 Uses = [EAX, EBX, ECX, EDX],
4036 mayLoad = 1, mayStore = 1,
4037 usesCustomInserter = 1 in {
4038 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4039 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4040 "#ATOMAND6432 PSEUDO!", []>;
4041 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4042 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4043 "#ATOMOR6432 PSEUDO!", []>;
4044 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4045 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4046 "#ATOMXOR6432 PSEUDO!", []>;
4047 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4048 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4049 "#ATOMNAND6432 PSEUDO!", []>;
4050 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4051 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4052 "#ATOMADD6432 PSEUDO!", []>;
4053 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4054 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4055 "#ATOMSUB6432 PSEUDO!", []>;
4056 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4057 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4058 "#ATOMSWAP6432 PSEUDO!", []>;
4061 // Segmentation support instructions.
4063 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4064 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4065 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4066 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4068 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
4069 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
4070 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4071 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4072 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4074 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4075 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4076 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4077 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4078 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4079 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4080 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4081 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4083 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
4085 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
4086 "str{w}\t{$dst}", []>, TB;
4087 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
4088 "str{w}\t{$dst}", []>, TB;
4089 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
4090 "ltr{w}\t{$src}", []>, TB;
4091 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
4092 "ltr{w}\t{$src}", []>, TB;
4094 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
4095 "push{w}\t%fs", []>, OpSize, TB;
4096 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
4097 "push{l}\t%fs", []>, TB;
4098 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
4099 "push{w}\t%gs", []>, OpSize, TB;
4100 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
4101 "push{l}\t%gs", []>, TB;
4103 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
4104 "pop{w}\t%fs", []>, OpSize, TB;
4105 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
4106 "pop{l}\t%fs", []>, TB;
4107 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
4108 "pop{w}\t%gs", []>, OpSize, TB;
4109 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
4110 "pop{l}\t%gs", []>, TB;
4112 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4113 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4114 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4115 "lds{l}\t{$src, $dst|$dst, $src}", []>;
4116 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4117 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4118 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4119 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
4120 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4121 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4122 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4123 "les{l}\t{$src, $dst|$dst, $src}", []>;
4124 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4125 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4126 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4127 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4128 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4129 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4130 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4131 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4133 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
4134 "verr\t$seg", []>, TB;
4135 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
4136 "verr\t$seg", []>, TB;
4137 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
4138 "verw\t$seg", []>, TB;
4139 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
4140 "verw\t$seg", []>, TB;
4142 // Descriptor-table support instructions
4144 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
4145 "sgdt\t$dst", []>, TB;
4146 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
4147 "sidt\t$dst", []>, TB;
4148 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
4149 "sldt{w}\t$dst", []>, TB;
4150 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
4151 "sldt{w}\t$dst", []>, TB;
4152 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
4153 "lgdt\t$src", []>, TB;
4154 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
4155 "lidt\t$src", []>, TB;
4156 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
4157 "lldt{w}\t$src", []>, TB;
4158 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
4159 "lldt{w}\t$src", []>, TB;
4161 // Lock instruction prefix
4162 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
4164 // Repeat string operation instruction prefixes
4165 // These uses the DF flag in the EFLAGS register to inc or dec ECX
4166 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
4167 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
4168 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
4169 // Repeat while not equal (used with CMPS and SCAS)
4170 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
4173 // Segment override instruction prefixes
4174 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
4175 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
4176 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
4177 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
4178 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
4179 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
4181 // String manipulation instructions
4183 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
4184 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
4185 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
4187 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
4188 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
4189 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
4191 // CPU flow control instructions
4193 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
4194 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
4196 // FPU control instructions
4198 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
4200 // Flag instructions
4202 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
4203 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
4204 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
4205 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
4206 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
4207 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
4208 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
4210 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
4212 // Table lookup instructions
4214 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
4216 // Specialized register support
4218 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
4219 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
4220 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
4222 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
4223 "smsw{w}\t$dst", []>, OpSize, TB;
4224 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
4225 "smsw{l}\t$dst", []>, TB;
4226 // For memory operands, there is only a 16-bit form
4227 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
4228 "smsw{w}\t$dst", []>, TB;
4230 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
4231 "lmsw{w}\t$src", []>, TB;
4232 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
4233 "lmsw{w}\t$src", []>, TB;
4235 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
4237 // Cache instructions
4239 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
4240 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
4245 def INVEPT : I<0x80, RawFrm, (outs), (ins), "invept", []>, OpSize, T8;
4247 def INVVPID : I<0x81, RawFrm, (outs), (ins), "invvpid", []>, OpSize, T8;
4249 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
4250 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4251 "vmclear\t$vmcs", []>, OpSize, TB;
4253 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
4255 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
4256 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4257 "vmptrld\t$vmcs", []>, TB;
4258 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4259 "vmptrst\t$vmcs", []>, TB;
4260 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
4261 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4262 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
4263 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4264 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
4265 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4266 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4267 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4268 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4269 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4270 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4271 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4272 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4273 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4274 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4275 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4277 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
4278 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
4279 "vmxon\t{$vmxon}", []>, XD;
4281 //===----------------------------------------------------------------------===//
4282 // Non-Instruction Patterns
4283 //===----------------------------------------------------------------------===//
4285 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
4286 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
4287 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
4288 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
4289 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
4290 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
4291 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
4293 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
4294 (ADD32ri GR32:$src1, tconstpool:$src2)>;
4295 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
4296 (ADD32ri GR32:$src1, tjumptable:$src2)>;
4297 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
4298 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
4299 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
4300 (ADD32ri GR32:$src1, texternalsym:$src2)>;
4301 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
4302 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
4304 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
4305 (MOV32mi addr:$dst, tglobaladdr:$src)>;
4306 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
4307 (MOV32mi addr:$dst, texternalsym:$src)>;
4308 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
4309 (MOV32mi addr:$dst, tblockaddress:$src)>;
4313 def : Pat<(X86tcret GR32:$dst, imm:$off),
4314 (TCRETURNri GR32:$dst, imm:$off)>;
4316 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
4317 (TCRETURNdi texternalsym:$dst, imm:$off)>;
4319 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
4320 (TCRETURNdi texternalsym:$dst, imm:$off)>;
4322 // Normal calls, with various flavors of addresses.
4323 def : Pat<(X86call (i32 tglobaladdr:$dst)),
4324 (CALLpcrel32 tglobaladdr:$dst)>;
4325 def : Pat<(X86call (i32 texternalsym:$dst)),
4326 (CALLpcrel32 texternalsym:$dst)>;
4327 def : Pat<(X86call (i32 imm:$dst)),
4328 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
4330 // X86 specific add which produces a flag.
4331 def : Pat<(addc GR32:$src1, GR32:$src2),
4332 (ADD32rr GR32:$src1, GR32:$src2)>;
4333 def : Pat<(addc GR32:$src1, (load addr:$src2)),
4334 (ADD32rm GR32:$src1, addr:$src2)>;
4335 def : Pat<(addc GR32:$src1, imm:$src2),
4336 (ADD32ri GR32:$src1, imm:$src2)>;
4337 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
4338 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4340 def : Pat<(subc GR32:$src1, GR32:$src2),
4341 (SUB32rr GR32:$src1, GR32:$src2)>;
4342 def : Pat<(subc GR32:$src1, (load addr:$src2)),
4343 (SUB32rm GR32:$src1, addr:$src2)>;
4344 def : Pat<(subc GR32:$src1, imm:$src2),
4345 (SUB32ri GR32:$src1, imm:$src2)>;
4346 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
4347 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4351 // TEST R,R is smaller than CMP R,0
4352 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
4353 (TEST8rr GR8:$src1, GR8:$src1)>;
4354 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
4355 (TEST16rr GR16:$src1, GR16:$src1)>;
4356 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
4357 (TEST32rr GR32:$src1, GR32:$src1)>;
4359 // Conditional moves with folded loads with operands swapped and conditions
4361 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
4362 (CMOVAE16rm GR16:$src2, addr:$src1)>;
4363 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
4364 (CMOVAE32rm GR32:$src2, addr:$src1)>;
4365 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
4366 (CMOVB16rm GR16:$src2, addr:$src1)>;
4367 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
4368 (CMOVB32rm GR32:$src2, addr:$src1)>;
4369 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
4370 (CMOVNE16rm GR16:$src2, addr:$src1)>;
4371 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
4372 (CMOVNE32rm GR32:$src2, addr:$src1)>;
4373 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
4374 (CMOVE16rm GR16:$src2, addr:$src1)>;
4375 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
4376 (CMOVE32rm GR32:$src2, addr:$src1)>;
4377 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
4378 (CMOVA16rm GR16:$src2, addr:$src1)>;
4379 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
4380 (CMOVA32rm GR32:$src2, addr:$src1)>;
4381 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
4382 (CMOVBE16rm GR16:$src2, addr:$src1)>;
4383 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
4384 (CMOVBE32rm GR32:$src2, addr:$src1)>;
4385 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
4386 (CMOVGE16rm GR16:$src2, addr:$src1)>;
4387 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
4388 (CMOVGE32rm GR32:$src2, addr:$src1)>;
4389 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
4390 (CMOVL16rm GR16:$src2, addr:$src1)>;
4391 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
4392 (CMOVL32rm GR32:$src2, addr:$src1)>;
4393 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
4394 (CMOVG16rm GR16:$src2, addr:$src1)>;
4395 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
4396 (CMOVG32rm GR32:$src2, addr:$src1)>;
4397 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
4398 (CMOVLE16rm GR16:$src2, addr:$src1)>;
4399 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
4400 (CMOVLE32rm GR32:$src2, addr:$src1)>;
4401 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
4402 (CMOVNP16rm GR16:$src2, addr:$src1)>;
4403 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
4404 (CMOVNP32rm GR32:$src2, addr:$src1)>;
4405 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
4406 (CMOVP16rm GR16:$src2, addr:$src1)>;
4407 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
4408 (CMOVP32rm GR32:$src2, addr:$src1)>;
4409 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
4410 (CMOVNS16rm GR16:$src2, addr:$src1)>;
4411 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
4412 (CMOVNS32rm GR32:$src2, addr:$src1)>;
4413 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
4414 (CMOVS16rm GR16:$src2, addr:$src1)>;
4415 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
4416 (CMOVS32rm GR32:$src2, addr:$src1)>;
4417 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
4418 (CMOVNO16rm GR16:$src2, addr:$src1)>;
4419 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
4420 (CMOVNO32rm GR32:$src2, addr:$src1)>;
4421 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
4422 (CMOVO16rm GR16:$src2, addr:$src1)>;
4423 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
4424 (CMOVO32rm GR32:$src2, addr:$src1)>;
4426 // zextload bool -> zextload byte
4427 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4428 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4429 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4431 // extload bool -> extload byte
4432 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4433 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4434 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4435 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
4436 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
4437 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
4439 // anyext. Define these to do an explicit zero-extend to
4440 // avoid partial-register updates.
4441 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
4442 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
4443 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
4445 // (and (i32 load), 255) -> (zextload i8)
4446 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
4447 (MOVZX32rm8 addr:$src)>;
4448 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
4449 (MOVZX32rm16 addr:$src)>;
4451 //===----------------------------------------------------------------------===//
4453 //===----------------------------------------------------------------------===//
4455 // Odd encoding trick: -128 fits into an 8-bit immediate field while
4456 // +128 doesn't, so in this special case use a sub instead of an add.
4457 def : Pat<(add GR16:$src1, 128),
4458 (SUB16ri8 GR16:$src1, -128)>;
4459 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
4460 (SUB16mi8 addr:$dst, -128)>;
4461 def : Pat<(add GR32:$src1, 128),
4462 (SUB32ri8 GR32:$src1, -128)>;
4463 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
4464 (SUB32mi8 addr:$dst, -128)>;
4466 // r & (2^16-1) ==> movz
4467 def : Pat<(and GR32:$src1, 0xffff),
4468 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
4469 // r & (2^8-1) ==> movz
4470 def : Pat<(and GR32:$src1, 0xff),
4471 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
4474 Requires<[In32BitMode]>;
4475 // r & (2^8-1) ==> movz
4476 def : Pat<(and GR16:$src1, 0xff),
4477 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
4480 Requires<[In32BitMode]>;
4482 // sext_inreg patterns
4483 def : Pat<(sext_inreg GR32:$src, i16),
4484 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
4485 def : Pat<(sext_inreg GR32:$src, i8),
4486 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4489 Requires<[In32BitMode]>;
4490 def : Pat<(sext_inreg GR16:$src, i8),
4491 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4494 Requires<[In32BitMode]>;
4497 def : Pat<(i16 (trunc GR32:$src)),
4498 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
4499 def : Pat<(i8 (trunc GR32:$src)),
4500 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4502 Requires<[In32BitMode]>;
4503 def : Pat<(i8 (trunc GR16:$src)),
4504 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4506 Requires<[In32BitMode]>;
4508 // h-register tricks
4509 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
4510 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4511 x86_subreg_8bit_hi)>,
4512 Requires<[In32BitMode]>;
4513 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
4514 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4515 x86_subreg_8bit_hi)>,
4516 Requires<[In32BitMode]>;
4517 def : Pat<(srl GR16:$src, (i8 8)),
4520 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4521 x86_subreg_8bit_hi)),
4523 Requires<[In32BitMode]>;
4524 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4525 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4527 x86_subreg_8bit_hi))>,
4528 Requires<[In32BitMode]>;
4529 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4530 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4532 x86_subreg_8bit_hi))>,
4533 Requires<[In32BitMode]>;
4534 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4535 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4537 x86_subreg_8bit_hi))>,
4538 Requires<[In32BitMode]>;
4540 // (shl x, 1) ==> (add x, x)
4541 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
4542 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
4543 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
4545 // (shl x (and y, 31)) ==> (shl x, y)
4546 def : Pat<(shl GR8:$src1, (and CL, 31)),
4547 (SHL8rCL GR8:$src1)>;
4548 def : Pat<(shl GR16:$src1, (and CL, 31)),
4549 (SHL16rCL GR16:$src1)>;
4550 def : Pat<(shl GR32:$src1, (and CL, 31)),
4551 (SHL32rCL GR32:$src1)>;
4552 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4553 (SHL8mCL addr:$dst)>;
4554 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4555 (SHL16mCL addr:$dst)>;
4556 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4557 (SHL32mCL addr:$dst)>;
4559 def : Pat<(srl GR8:$src1, (and CL, 31)),
4560 (SHR8rCL GR8:$src1)>;
4561 def : Pat<(srl GR16:$src1, (and CL, 31)),
4562 (SHR16rCL GR16:$src1)>;
4563 def : Pat<(srl GR32:$src1, (and CL, 31)),
4564 (SHR32rCL GR32:$src1)>;
4565 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4566 (SHR8mCL addr:$dst)>;
4567 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4568 (SHR16mCL addr:$dst)>;
4569 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4570 (SHR32mCL addr:$dst)>;
4572 def : Pat<(sra GR8:$src1, (and CL, 31)),
4573 (SAR8rCL GR8:$src1)>;
4574 def : Pat<(sra GR16:$src1, (and CL, 31)),
4575 (SAR16rCL GR16:$src1)>;
4576 def : Pat<(sra GR32:$src1, (and CL, 31)),
4577 (SAR32rCL GR32:$src1)>;
4578 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4579 (SAR8mCL addr:$dst)>;
4580 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4581 (SAR16mCL addr:$dst)>;
4582 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4583 (SAR32mCL addr:$dst)>;
4585 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
4586 def : Pat<(or (srl GR32:$src1, CL:$amt),
4587 (shl GR32:$src2, (sub 32, CL:$amt))),
4588 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4590 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
4591 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4592 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4594 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
4595 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4596 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4598 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4599 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4601 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4603 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm/*:$amt2*/)),
4604 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4606 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
4607 GR32:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4608 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4610 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
4611 def : Pat<(or (shl GR32:$src1, CL:$amt),
4612 (srl GR32:$src2, (sub 32, CL:$amt))),
4613 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4615 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
4616 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4617 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4619 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
4620 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4621 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4623 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4624 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4626 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4628 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm/*:$amt2*/)),
4629 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4631 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
4632 GR32:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4633 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4635 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
4636 def : Pat<(or (srl GR16:$src1, CL:$amt),
4637 (shl GR16:$src2, (sub 16, CL:$amt))),
4638 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4640 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
4641 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4642 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4644 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
4645 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4646 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4648 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4649 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4651 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4653 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm/*:$amt2*/)),
4654 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4656 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
4657 GR16:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4658 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4660 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
4661 def : Pat<(or (shl GR16:$src1, CL:$amt),
4662 (srl GR16:$src2, (sub 16, CL:$amt))),
4663 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4665 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
4666 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4667 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4669 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
4670 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4671 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4673 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4674 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4676 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4678 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm/*:$amt2*/)),
4679 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4681 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
4682 GR16:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4683 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4685 // (anyext (setcc_carry)) -> (setcc_carry)
4686 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4688 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4691 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
4692 let AddedComplexity = 5 in { // Try this before the selecting to OR
4693 def : Pat<(parallel (or_is_add GR16:$src1, imm:$src2),
4695 (ADD16ri GR16:$src1, imm:$src2)>;
4696 def : Pat<(parallel (or_is_add GR32:$src1, imm:$src2),
4698 (ADD32ri GR32:$src1, imm:$src2)>;
4699 def : Pat<(parallel (or_is_add GR16:$src1, i16immSExt8:$src2),
4701 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4702 def : Pat<(parallel (or_is_add GR32:$src1, i32immSExt8:$src2),
4704 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4705 def : Pat<(parallel (or_is_add GR16:$src1, GR16:$src2),
4707 (ADD16rr GR16:$src1, GR16:$src2)>;
4708 def : Pat<(parallel (or_is_add GR32:$src1, GR32:$src2),
4710 (ADD32rr GR32:$src1, GR32:$src2)>;
4711 } // AddedComplexity
4713 //===----------------------------------------------------------------------===//
4714 // EFLAGS-defining Patterns
4715 //===----------------------------------------------------------------------===//
4717 // Register-Register Addition with EFLAGS result
4718 def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
4720 (ADD8rr GR8:$src1, GR8:$src2)>;
4721 def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
4723 (ADD16rr GR16:$src1, GR16:$src2)>;
4724 def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
4726 (ADD32rr GR32:$src1, GR32:$src2)>;
4728 // Register-Memory Addition with EFLAGS result
4729 def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
4731 (ADD8rm GR8:$src1, addr:$src2)>;
4732 def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
4734 (ADD16rm GR16:$src1, addr:$src2)>;
4735 def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
4737 (ADD32rm GR32:$src1, addr:$src2)>;
4739 // Register-Integer Addition with EFLAGS result
4740 def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
4742 (ADD8ri GR8:$src1, imm:$src2)>;
4743 def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
4745 (ADD16ri GR16:$src1, imm:$src2)>;
4746 def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
4748 (ADD32ri GR32:$src1, imm:$src2)>;
4749 def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
4751 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4752 def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
4754 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4756 // Memory-Register Addition with EFLAGS result
4757 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
4760 (ADD8mr addr:$dst, GR8:$src2)>;
4761 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
4764 (ADD16mr addr:$dst, GR16:$src2)>;
4765 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
4768 (ADD32mr addr:$dst, GR32:$src2)>;
4770 // Memory-Integer Addition with EFLAGS result
4771 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
4774 (ADD8mi addr:$dst, imm:$src2)>;
4775 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
4778 (ADD16mi addr:$dst, imm:$src2)>;
4779 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
4782 (ADD32mi addr:$dst, imm:$src2)>;
4783 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4786 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
4787 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4790 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
4792 // Register-Register Subtraction with EFLAGS result
4793 def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
4795 (SUB8rr GR8:$src1, GR8:$src2)>;
4796 def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
4798 (SUB16rr GR16:$src1, GR16:$src2)>;
4799 def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
4801 (SUB32rr GR32:$src1, GR32:$src2)>;
4803 // Register-Memory Subtraction with EFLAGS result
4804 def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
4806 (SUB8rm GR8:$src1, addr:$src2)>;
4807 def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
4809 (SUB16rm GR16:$src1, addr:$src2)>;
4810 def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
4812 (SUB32rm GR32:$src1, addr:$src2)>;
4814 // Register-Integer Subtraction with EFLAGS result
4815 def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
4817 (SUB8ri GR8:$src1, imm:$src2)>;
4818 def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
4820 (SUB16ri GR16:$src1, imm:$src2)>;
4821 def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
4823 (SUB32ri GR32:$src1, imm:$src2)>;
4824 def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
4826 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4827 def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
4829 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4831 // Memory-Register Subtraction with EFLAGS result
4832 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
4835 (SUB8mr addr:$dst, GR8:$src2)>;
4836 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
4839 (SUB16mr addr:$dst, GR16:$src2)>;
4840 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
4843 (SUB32mr addr:$dst, GR32:$src2)>;
4845 // Memory-Integer Subtraction with EFLAGS result
4846 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
4849 (SUB8mi addr:$dst, imm:$src2)>;
4850 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
4853 (SUB16mi addr:$dst, imm:$src2)>;
4854 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
4857 (SUB32mi addr:$dst, imm:$src2)>;
4858 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4861 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
4862 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4865 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
4868 // Register-Register Signed Integer Multiply with EFLAGS result
4869 def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
4871 (IMUL16rr GR16:$src1, GR16:$src2)>;
4872 def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
4874 (IMUL32rr GR32:$src1, GR32:$src2)>;
4876 // Register-Memory Signed Integer Multiply with EFLAGS result
4877 def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
4879 (IMUL16rm GR16:$src1, addr:$src2)>;
4880 def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
4882 (IMUL32rm GR32:$src1, addr:$src2)>;
4884 // Register-Integer Signed Integer Multiply with EFLAGS result
4885 def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
4887 (IMUL16rri GR16:$src1, imm:$src2)>;
4888 def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
4890 (IMUL32rri GR32:$src1, imm:$src2)>;
4891 def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
4893 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4894 def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
4896 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4898 // Memory-Integer Signed Integer Multiply with EFLAGS result
4899 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
4901 (IMUL16rmi addr:$src1, imm:$src2)>;
4902 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
4904 (IMUL32rmi addr:$src1, imm:$src2)>;
4905 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
4907 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4908 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
4910 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4912 // Optimize multiply by 2 with EFLAGS result.
4913 let AddedComplexity = 2 in {
4914 def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
4916 (ADD16rr GR16:$src1, GR16:$src1)>;
4918 def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
4920 (ADD32rr GR32:$src1, GR32:$src1)>;
4923 // INC and DEC with EFLAGS result. Note that these do not set CF.
4924 def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
4926 def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
4929 def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
4931 def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
4935 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
4936 (INC16r GR16:$src)>, Requires<[In32BitMode]>;
4937 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
4939 (INC16m addr:$dst)>, Requires<[In32BitMode]>;
4940 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
4941 (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
4942 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
4944 (DEC16m addr:$dst)>, Requires<[In32BitMode]>;
4946 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
4947 (INC32r GR32:$src)>, Requires<[In32BitMode]>;
4948 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
4950 (INC32m addr:$dst)>, Requires<[In32BitMode]>;
4951 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
4952 (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
4953 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
4955 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
4957 // Register-Register Or with EFLAGS result
4958 def : Pat<(parallel (X86or_flag GR8:$src1, GR8:$src2),
4960 (OR8rr GR8:$src1, GR8:$src2)>;
4961 def : Pat<(parallel (X86or_flag GR16:$src1, GR16:$src2),
4963 (OR16rr GR16:$src1, GR16:$src2)>;
4964 def : Pat<(parallel (X86or_flag GR32:$src1, GR32:$src2),
4966 (OR32rr GR32:$src1, GR32:$src2)>;
4968 // Register-Memory Or with EFLAGS result
4969 def : Pat<(parallel (X86or_flag GR8:$src1, (loadi8 addr:$src2)),
4971 (OR8rm GR8:$src1, addr:$src2)>;
4972 def : Pat<(parallel (X86or_flag GR16:$src1, (loadi16 addr:$src2)),
4974 (OR16rm GR16:$src1, addr:$src2)>;
4975 def : Pat<(parallel (X86or_flag GR32:$src1, (loadi32 addr:$src2)),
4977 (OR32rm GR32:$src1, addr:$src2)>;
4979 // Register-Integer Or with EFLAGS result
4980 def : Pat<(parallel (X86or_flag GR8:$src1, imm:$src2),
4982 (OR8ri GR8:$src1, imm:$src2)>;
4983 def : Pat<(parallel (X86or_flag GR16:$src1, imm:$src2),
4985 (OR16ri GR16:$src1, imm:$src2)>;
4986 def : Pat<(parallel (X86or_flag GR32:$src1, imm:$src2),
4988 (OR32ri GR32:$src1, imm:$src2)>;
4989 def : Pat<(parallel (X86or_flag GR16:$src1, i16immSExt8:$src2),
4991 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4992 def : Pat<(parallel (X86or_flag GR32:$src1, i32immSExt8:$src2),
4994 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4996 // Memory-Register Or with EFLAGS result
4997 def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), GR8:$src2),
5000 (OR8mr addr:$dst, GR8:$src2)>;
5001 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), GR16:$src2),
5004 (OR16mr addr:$dst, GR16:$src2)>;
5005 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), GR32:$src2),
5008 (OR32mr addr:$dst, GR32:$src2)>;
5010 // Memory-Integer Or with EFLAGS result
5011 def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), imm:$src2),
5014 (OR8mi addr:$dst, imm:$src2)>;
5015 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), imm:$src2),
5018 (OR16mi addr:$dst, imm:$src2)>;
5019 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), imm:$src2),
5022 (OR32mi addr:$dst, imm:$src2)>;
5023 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), i16immSExt8:$src2),
5026 (OR16mi8 addr:$dst, i16immSExt8:$src2)>;
5027 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), i32immSExt8:$src2),
5030 (OR32mi8 addr:$dst, i32immSExt8:$src2)>;
5032 // Register-Register XOr with EFLAGS result
5033 def : Pat<(parallel (X86xor_flag GR8:$src1, GR8:$src2),
5035 (XOR8rr GR8:$src1, GR8:$src2)>;
5036 def : Pat<(parallel (X86xor_flag GR16:$src1, GR16:$src2),
5038 (XOR16rr GR16:$src1, GR16:$src2)>;
5039 def : Pat<(parallel (X86xor_flag GR32:$src1, GR32:$src2),
5041 (XOR32rr GR32:$src1, GR32:$src2)>;
5043 // Register-Memory XOr with EFLAGS result
5044 def : Pat<(parallel (X86xor_flag GR8:$src1, (loadi8 addr:$src2)),
5046 (XOR8rm GR8:$src1, addr:$src2)>;
5047 def : Pat<(parallel (X86xor_flag GR16:$src1, (loadi16 addr:$src2)),
5049 (XOR16rm GR16:$src1, addr:$src2)>;
5050 def : Pat<(parallel (X86xor_flag GR32:$src1, (loadi32 addr:$src2)),
5052 (XOR32rm GR32:$src1, addr:$src2)>;
5054 // Register-Integer XOr with EFLAGS result
5055 def : Pat<(parallel (X86xor_flag GR8:$src1, imm:$src2),
5057 (XOR8ri GR8:$src1, imm:$src2)>;
5058 def : Pat<(parallel (X86xor_flag GR16:$src1, imm:$src2),
5060 (XOR16ri GR16:$src1, imm:$src2)>;
5061 def : Pat<(parallel (X86xor_flag GR32:$src1, imm:$src2),
5063 (XOR32ri GR32:$src1, imm:$src2)>;
5064 def : Pat<(parallel (X86xor_flag GR16:$src1, i16immSExt8:$src2),
5066 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
5067 def : Pat<(parallel (X86xor_flag GR32:$src1, i32immSExt8:$src2),
5069 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
5071 // Memory-Register XOr with EFLAGS result
5072 def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), GR8:$src2),
5075 (XOR8mr addr:$dst, GR8:$src2)>;
5076 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), GR16:$src2),
5079 (XOR16mr addr:$dst, GR16:$src2)>;
5080 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), GR32:$src2),
5083 (XOR32mr addr:$dst, GR32:$src2)>;
5085 // Memory-Integer XOr with EFLAGS result
5086 def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), imm:$src2),
5089 (XOR8mi addr:$dst, imm:$src2)>;
5090 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), imm:$src2),
5093 (XOR16mi addr:$dst, imm:$src2)>;
5094 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), imm:$src2),
5097 (XOR32mi addr:$dst, imm:$src2)>;
5098 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), i16immSExt8:$src2),
5101 (XOR16mi8 addr:$dst, i16immSExt8:$src2)>;
5102 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), i32immSExt8:$src2),
5105 (XOR32mi8 addr:$dst, i32immSExt8:$src2)>;
5107 // Register-Register And with EFLAGS result
5108 def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2),
5110 (AND8rr GR8:$src1, GR8:$src2)>;
5111 def : Pat<(parallel (X86and_flag GR16:$src1, GR16:$src2),
5113 (AND16rr GR16:$src1, GR16:$src2)>;
5114 def : Pat<(parallel (X86and_flag GR32:$src1, GR32:$src2),
5116 (AND32rr GR32:$src1, GR32:$src2)>;
5118 // Register-Memory And with EFLAGS result
5119 def : Pat<(parallel (X86and_flag GR8:$src1, (loadi8 addr:$src2)),
5121 (AND8rm GR8:$src1, addr:$src2)>;
5122 def : Pat<(parallel (X86and_flag GR16:$src1, (loadi16 addr:$src2)),
5124 (AND16rm GR16:$src1, addr:$src2)>;
5125 def : Pat<(parallel (X86and_flag GR32:$src1, (loadi32 addr:$src2)),
5127 (AND32rm GR32:$src1, addr:$src2)>;
5129 // Register-Integer And with EFLAGS result
5130 def : Pat<(parallel (X86and_flag GR8:$src1, imm:$src2),
5132 (AND8ri GR8:$src1, imm:$src2)>;
5133 def : Pat<(parallel (X86and_flag GR16:$src1, imm:$src2),
5135 (AND16ri GR16:$src1, imm:$src2)>;
5136 def : Pat<(parallel (X86and_flag GR32:$src1, imm:$src2),
5138 (AND32ri GR32:$src1, imm:$src2)>;
5139 def : Pat<(parallel (X86and_flag GR16:$src1, i16immSExt8:$src2),
5141 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
5142 def : Pat<(parallel (X86and_flag GR32:$src1, i32immSExt8:$src2),
5144 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
5146 // Memory-Register And with EFLAGS result
5147 def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), GR8:$src2),
5150 (AND8mr addr:$dst, GR8:$src2)>;
5151 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), GR16:$src2),
5154 (AND16mr addr:$dst, GR16:$src2)>;
5155 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), GR32:$src2),
5158 (AND32mr addr:$dst, GR32:$src2)>;
5160 // Memory-Integer And with EFLAGS result
5161 def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), imm:$src2),
5164 (AND8mi addr:$dst, imm:$src2)>;
5165 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), imm:$src2),
5168 (AND16mi addr:$dst, imm:$src2)>;
5169 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), imm:$src2),
5172 (AND32mi addr:$dst, imm:$src2)>;
5173 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), i16immSExt8:$src2),
5176 (AND16mi8 addr:$dst, i16immSExt8:$src2)>;
5177 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), i32immSExt8:$src2),
5180 (AND32mi8 addr:$dst, i32immSExt8:$src2)>;
5182 // -disable-16bit support.
5183 def : Pat<(truncstorei16 (i32 imm:$src), addr:$dst),
5184 (MOV16mi addr:$dst, imm:$src)>;
5185 def : Pat<(truncstorei16 GR32:$src, addr:$dst),
5186 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
5187 def : Pat<(i32 (sextloadi16 addr:$dst)),
5188 (MOVSX32rm16 addr:$dst)>;
5189 def : Pat<(i32 (zextloadi16 addr:$dst)),
5190 (MOVZX32rm16 addr:$dst)>;
5191 def : Pat<(i32 (extloadi16 addr:$dst)),
5192 (MOVZX32rm16 addr:$dst)>;
5194 //===----------------------------------------------------------------------===//
5195 // Floating Point Stack Support
5196 //===----------------------------------------------------------------------===//
5198 include "X86InstrFPStack.td"
5200 //===----------------------------------------------------------------------===//
5202 //===----------------------------------------------------------------------===//
5204 include "X86Instr64bit.td"
5206 //===----------------------------------------------------------------------===//
5207 // SIMD support (SSE, MMX and AVX)
5208 //===----------------------------------------------------------------------===//
5210 include "X86InstrFragmentsSIMD.td"
5212 //===----------------------------------------------------------------------===//
5213 // XMM Floating point support (requires SSE / SSE2)
5214 //===----------------------------------------------------------------------===//
5216 include "X86InstrSSE.td"
5218 //===----------------------------------------------------------------------===//
5219 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
5220 //===----------------------------------------------------------------------===//
5222 include "X86InstrMMX.td"