1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 //def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
36 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
41 SDTCisInt<0>, SDTCisVT<1, i32>]>;
43 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
44 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
50 // RES1, RES2, FLAGS = op LHS, RHS
51 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
55 SDTCisInt<0>, SDTCisVT<1, i32>]>;
56 def SDTX86BrCond : SDTypeProfile<0, 3,
57 [SDTCisVT<0, OtherVT>,
58 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
60 def SDTX86SetCC : SDTypeProfile<1, 2,
62 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
63 def SDTX86SetCC_C : SDTypeProfile<1, 2,
65 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
67 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
69 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
71 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
73 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
75 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
76 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
77 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
79 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
80 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
83 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
85 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
89 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
95 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
97 def SDTX86Void : SDTypeProfile<0, 0, []>;
99 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
101 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
103 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
105 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
107 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
109 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
111 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
113 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
115 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
116 [SDNPHasChain,SDNPSideEffect]>;
117 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
119 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
121 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
125 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
126 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
127 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
128 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
130 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
131 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
133 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
134 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
136 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
137 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
139 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
141 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
142 [SDNPHasChain, SDNPSideEffect]>;
144 def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand,
145 [SDNPHasChain, SDNPSideEffect]>;
147 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
148 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
149 SDNPMayLoad, SDNPMemOperand]>;
150 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
151 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
152 SDNPMayLoad, SDNPMemOperand]>;
153 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
154 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
155 SDNPMayLoad, SDNPMemOperand]>;
157 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
158 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
160 def X86vastart_save_xmm_regs :
161 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
162 SDT_X86VASTART_SAVE_XMM_REGS,
163 [SDNPHasChain, SDNPVariadic]>;
165 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
166 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
168 def X86callseq_start :
169 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
170 [SDNPHasChain, SDNPOutGlue]>;
172 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
173 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
175 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
176 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
179 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
180 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
181 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
182 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
185 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
186 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
187 def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void,
188 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
189 def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void,
190 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
192 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
193 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
195 def X86RecoverFrameAlloc : SDNode<"ISD::LOCAL_RECOVER",
196 SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
199 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
200 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
202 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
203 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
205 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
208 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
209 SDTypeProfile<1, 1, [SDTCisInt<0>,
211 [SDNPHasChain, SDNPSideEffect]>;
212 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
213 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
214 [SDNPHasChain, SDNPSideEffect]>;
216 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
217 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
219 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
221 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
222 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
224 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
226 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
227 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
229 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
230 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
231 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
233 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
235 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
238 def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>;
240 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
242 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
243 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
245 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
248 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
249 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
251 //===----------------------------------------------------------------------===//
252 // X86 Operand Definitions.
255 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
256 // the index operand of an address, to conform to x86 encoding restrictions.
257 def ptr_rc_nosp : PointerLikeRegClass<1>;
259 // *mem - Operand definitions for the funky X86 addressing mode operands.
261 def X86MemAsmOperand : AsmOperandClass {
264 let RenderMethod = "addMemOperands" in {
265 def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; }
266 def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; }
267 def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; }
268 def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; }
269 def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; }
270 def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; }
271 def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; }
272 def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; }
273 // Gather mem operands
274 def X86MemVX32Operand : AsmOperandClass { let Name = "MemVX32"; }
275 def X86MemVY32Operand : AsmOperandClass { let Name = "MemVY32"; }
276 def X86MemVZ32Operand : AsmOperandClass { let Name = "MemVZ32"; }
277 def X86MemVX64Operand : AsmOperandClass { let Name = "MemVX64"; }
278 def X86MemVY64Operand : AsmOperandClass { let Name = "MemVY64"; }
279 def X86MemVZ64Operand : AsmOperandClass { let Name = "MemVZ64"; }
280 def X86MemVX32XOperand : AsmOperandClass { let Name = "MemVX32X"; }
281 def X86MemVY32XOperand : AsmOperandClass { let Name = "MemVY32X"; }
282 def X86MemVX64XOperand : AsmOperandClass { let Name = "MemVX64X"; }
283 def X86MemVY64XOperand : AsmOperandClass { let Name = "MemVY64X"; }
286 def X86AbsMemAsmOperand : AsmOperandClass {
288 let SuperClasses = [X86MemAsmOperand];
291 class X86MemOperand<string printMethod,
292 AsmOperandClass parserMatchClass = X86MemAsmOperand> : Operand<iPTR> {
293 let PrintMethod = printMethod;
294 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
295 let ParserMatchClass = parserMatchClass;
296 let OperandType = "OPERAND_MEMORY";
299 // Gather mem operands
300 class X86VMemOperand<RegisterClass RC, string printMethod,
301 AsmOperandClass parserMatchClass>
302 : X86MemOperand<printMethod, parserMatchClass> {
303 let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, i8imm);
306 def anymem : X86MemOperand<"printanymem">;
308 def opaque32mem : X86MemOperand<"printopaquemem">;
309 def opaque48mem : X86MemOperand<"printopaquemem">;
310 def opaque80mem : X86MemOperand<"printopaquemem">;
311 def opaque512mem : X86MemOperand<"printopaquemem">;
313 def i8mem : X86MemOperand<"printi8mem", X86Mem8AsmOperand>;
314 def i16mem : X86MemOperand<"printi16mem", X86Mem16AsmOperand>;
315 def i32mem : X86MemOperand<"printi32mem", X86Mem32AsmOperand>;
316 def i64mem : X86MemOperand<"printi64mem", X86Mem64AsmOperand>;
317 def i128mem : X86MemOperand<"printi128mem", X86Mem128AsmOperand>;
318 def i256mem : X86MemOperand<"printi256mem", X86Mem256AsmOperand>;
319 def i512mem : X86MemOperand<"printi512mem", X86Mem512AsmOperand>;
320 def f32mem : X86MemOperand<"printf32mem", X86Mem32AsmOperand>;
321 def f64mem : X86MemOperand<"printf64mem", X86Mem64AsmOperand>;
322 def f80mem : X86MemOperand<"printf80mem", X86Mem80AsmOperand>;
323 def f128mem : X86MemOperand<"printf128mem", X86Mem128AsmOperand>;
324 def f256mem : X86MemOperand<"printf256mem", X86Mem256AsmOperand>;
325 def f512mem : X86MemOperand<"printf512mem", X86Mem512AsmOperand>;
327 def v512mem : X86VMemOperand<VR512, "printf512mem", X86Mem512AsmOperand>;
329 // Gather mem operands
330 def vx32mem : X86VMemOperand<VR128, "printi32mem", X86MemVX32Operand>;
331 def vy32mem : X86VMemOperand<VR256, "printi32mem", X86MemVY32Operand>;
332 def vx64mem : X86VMemOperand<VR128, "printi64mem", X86MemVX64Operand>;
333 def vy64mem : X86VMemOperand<VR256, "printi64mem", X86MemVY64Operand>;
335 def vx32xmem : X86VMemOperand<VR128X, "printi32mem", X86MemVX32XOperand>;
336 def vx64xmem : X86VMemOperand<VR128X, "printi32mem", X86MemVX64XOperand>;
337 def vy32xmem : X86VMemOperand<VR256X, "printi32mem", X86MemVY32XOperand>;
338 def vy64xmem : X86VMemOperand<VR256X, "printi64mem", X86MemVY64XOperand>;
339 def vz32mem : X86VMemOperand<VR512, "printi32mem", X86MemVZ32Operand>;
340 def vz64mem : X86VMemOperand<VR512, "printi64mem", X86MemVZ64Operand>;
342 // A version of i8mem for use on x86-64 and x32 that uses a NOREX GPR instead
343 // of a plain GPR, so that it doesn't potentially require a REX prefix.
344 def ptr_rc_norex : PointerLikeRegClass<2>;
345 def ptr_rc_norex_nosp : PointerLikeRegClass<3>;
347 def i8mem_NOREX : Operand<iPTR> {
348 let PrintMethod = "printi8mem";
349 let MIOperandInfo = (ops ptr_rc_norex, i8imm, ptr_rc_norex_nosp, i32imm, i8imm);
350 let ParserMatchClass = X86Mem8AsmOperand;
351 let OperandType = "OPERAND_MEMORY";
354 // GPRs available for tailcall.
355 // It represents GR32_TC, GR64_TC or GR64_TCW64.
356 def ptr_rc_tailcall : PointerLikeRegClass<4>;
358 // Special i32mem for addresses of load folding tail calls. These are not
359 // allowed to use callee-saved registers since they must be scheduled
360 // after callee-saved register are popped.
361 def i32mem_TC : Operand<i32> {
362 let PrintMethod = "printi32mem";
363 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
365 let ParserMatchClass = X86Mem32AsmOperand;
366 let OperandType = "OPERAND_MEMORY";
369 // Special i64mem for addresses of load folding tail calls. These are not
370 // allowed to use callee-saved registers since they must be scheduled
371 // after callee-saved register are popped.
372 def i64mem_TC : Operand<i64> {
373 let PrintMethod = "printi64mem";
374 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
375 ptr_rc_tailcall, i32imm, i8imm);
376 let ParserMatchClass = X86Mem64AsmOperand;
377 let OperandType = "OPERAND_MEMORY";
380 let OperandType = "OPERAND_PCREL",
381 ParserMatchClass = X86AbsMemAsmOperand,
382 PrintMethod = "printPCRelImm" in {
383 def i32imm_pcrel : Operand<i32>;
384 def i16imm_pcrel : Operand<i16>;
386 // Branch targets have OtherVT type and print as pc-relative values.
387 def brtarget : Operand<OtherVT>;
388 def brtarget8 : Operand<OtherVT>;
392 // Special parser to detect 16-bit mode to select 16-bit displacement.
393 def X86AbsMem16AsmOperand : AsmOperandClass {
394 let Name = "AbsMem16";
395 let RenderMethod = "addAbsMemOperands";
396 let SuperClasses = [X86AbsMemAsmOperand];
399 // Branch targets have OtherVT type and print as pc-relative values.
400 let OperandType = "OPERAND_PCREL",
401 PrintMethod = "printPCRelImm" in {
402 let ParserMatchClass = X86AbsMem16AsmOperand in
403 def brtarget16 : Operand<OtherVT>;
404 let ParserMatchClass = X86AbsMemAsmOperand in
405 def brtarget32 : Operand<OtherVT>;
408 let RenderMethod = "addSrcIdxOperands" in {
409 def X86SrcIdx8Operand : AsmOperandClass {
410 let Name = "SrcIdx8";
411 let SuperClasses = [X86Mem8AsmOperand];
413 def X86SrcIdx16Operand : AsmOperandClass {
414 let Name = "SrcIdx16";
415 let SuperClasses = [X86Mem16AsmOperand];
417 def X86SrcIdx32Operand : AsmOperandClass {
418 let Name = "SrcIdx32";
419 let SuperClasses = [X86Mem32AsmOperand];
421 def X86SrcIdx64Operand : AsmOperandClass {
422 let Name = "SrcIdx64";
423 let SuperClasses = [X86Mem64AsmOperand];
425 } // RenderMethod = "addSrcIdxOperands"
427 let RenderMethod = "addDstIdxOperands" in {
428 def X86DstIdx8Operand : AsmOperandClass {
429 let Name = "DstIdx8";
430 let SuperClasses = [X86Mem8AsmOperand];
432 def X86DstIdx16Operand : AsmOperandClass {
433 let Name = "DstIdx16";
434 let SuperClasses = [X86Mem16AsmOperand];
436 def X86DstIdx32Operand : AsmOperandClass {
437 let Name = "DstIdx32";
438 let SuperClasses = [X86Mem32AsmOperand];
440 def X86DstIdx64Operand : AsmOperandClass {
441 let Name = "DstIdx64";
442 let SuperClasses = [X86Mem64AsmOperand];
444 } // RenderMethod = "addDstIdxOperands"
446 let RenderMethod = "addMemOffsOperands" in {
447 def X86MemOffs16_8AsmOperand : AsmOperandClass {
448 let Name = "MemOffs16_8";
449 let SuperClasses = [X86Mem8AsmOperand];
451 def X86MemOffs16_16AsmOperand : AsmOperandClass {
452 let Name = "MemOffs16_16";
453 let SuperClasses = [X86Mem16AsmOperand];
455 def X86MemOffs16_32AsmOperand : AsmOperandClass {
456 let Name = "MemOffs16_32";
457 let SuperClasses = [X86Mem32AsmOperand];
459 def X86MemOffs32_8AsmOperand : AsmOperandClass {
460 let Name = "MemOffs32_8";
461 let SuperClasses = [X86Mem8AsmOperand];
463 def X86MemOffs32_16AsmOperand : AsmOperandClass {
464 let Name = "MemOffs32_16";
465 let SuperClasses = [X86Mem16AsmOperand];
467 def X86MemOffs32_32AsmOperand : AsmOperandClass {
468 let Name = "MemOffs32_32";
469 let SuperClasses = [X86Mem32AsmOperand];
471 def X86MemOffs32_64AsmOperand : AsmOperandClass {
472 let Name = "MemOffs32_64";
473 let SuperClasses = [X86Mem64AsmOperand];
475 def X86MemOffs64_8AsmOperand : AsmOperandClass {
476 let Name = "MemOffs64_8";
477 let SuperClasses = [X86Mem8AsmOperand];
479 def X86MemOffs64_16AsmOperand : AsmOperandClass {
480 let Name = "MemOffs64_16";
481 let SuperClasses = [X86Mem16AsmOperand];
483 def X86MemOffs64_32AsmOperand : AsmOperandClass {
484 let Name = "MemOffs64_32";
485 let SuperClasses = [X86Mem32AsmOperand];
487 def X86MemOffs64_64AsmOperand : AsmOperandClass {
488 let Name = "MemOffs64_64";
489 let SuperClasses = [X86Mem64AsmOperand];
491 } // RenderMethod = "addMemOffsOperands"
493 class X86SrcIdxOperand<string printMethod, AsmOperandClass parserMatchClass>
494 : X86MemOperand<printMethod, parserMatchClass> {
495 let MIOperandInfo = (ops ptr_rc, i8imm);
498 class X86DstIdxOperand<string printMethod, AsmOperandClass parserMatchClass>
499 : X86MemOperand<printMethod, parserMatchClass> {
500 let MIOperandInfo = (ops ptr_rc);
503 def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>;
504 def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>;
505 def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>;
506 def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>;
507 def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>;
508 def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>;
509 def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>;
510 def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>;
512 class X86MemOffsOperand<Operand immOperand, string printMethod,
513 AsmOperandClass parserMatchClass>
514 : X86MemOperand<printMethod, parserMatchClass> {
515 let MIOperandInfo = (ops immOperand, i8imm);
518 def offset16_8 : X86MemOffsOperand<i16imm, "printMemOffs8",
519 X86MemOffs16_8AsmOperand>;
520 def offset16_16 : X86MemOffsOperand<i16imm, "printMemOffs16",
521 X86MemOffs16_16AsmOperand>;
522 def offset16_32 : X86MemOffsOperand<i16imm, "printMemOffs32",
523 X86MemOffs16_32AsmOperand>;
524 def offset32_8 : X86MemOffsOperand<i32imm, "printMemOffs8",
525 X86MemOffs32_8AsmOperand>;
526 def offset32_16 : X86MemOffsOperand<i32imm, "printMemOffs16",
527 X86MemOffs32_16AsmOperand>;
528 def offset32_32 : X86MemOffsOperand<i32imm, "printMemOffs32",
529 X86MemOffs32_32AsmOperand>;
530 def offset32_64 : X86MemOffsOperand<i32imm, "printMemOffs64",
531 X86MemOffs32_64AsmOperand>;
532 def offset64_8 : X86MemOffsOperand<i64imm, "printMemOffs8",
533 X86MemOffs64_8AsmOperand>;
534 def offset64_16 : X86MemOffsOperand<i64imm, "printMemOffs16",
535 X86MemOffs64_16AsmOperand>;
536 def offset64_32 : X86MemOffsOperand<i64imm, "printMemOffs32",
537 X86MemOffs64_32AsmOperand>;
538 def offset64_64 : X86MemOffsOperand<i64imm, "printMemOffs64",
539 X86MemOffs64_64AsmOperand>;
541 def SSECC : Operand<i8> {
542 let PrintMethod = "printSSEAVXCC";
543 let OperandType = "OPERAND_IMMEDIATE";
546 def i8immZExt3 : ImmLeaf<i8, [{
547 return Imm >= 0 && Imm < 8;
550 def AVXCC : Operand<i8> {
551 let PrintMethod = "printSSEAVXCC";
552 let OperandType = "OPERAND_IMMEDIATE";
555 def i8immZExt5 : ImmLeaf<i8, [{
556 return Imm >= 0 && Imm < 32;
559 def AVX512ICC : Operand<i8> {
560 let PrintMethod = "printSSEAVXCC";
561 let OperandType = "OPERAND_IMMEDIATE";
564 def XOPCC : Operand<i8> {
565 let PrintMethod = "printXOPCC";
566 let OperandType = "OPERAND_IMMEDIATE";
569 class ImmSExtAsmOperandClass : AsmOperandClass {
570 let SuperClasses = [ImmAsmOperand];
571 let RenderMethod = "addImmOperands";
574 def X86GR32orGR64AsmOperand : AsmOperandClass {
575 let Name = "GR32orGR64";
578 def GR32orGR64 : RegisterOperand<GR32> {
579 let ParserMatchClass = X86GR32orGR64AsmOperand;
581 def AVX512RCOperand : AsmOperandClass {
582 let Name = "AVX512RC";
584 def AVX512RC : Operand<i32> {
585 let PrintMethod = "printRoundingControl";
586 let OperandType = "OPERAND_IMMEDIATE";
587 let ParserMatchClass = AVX512RCOperand;
590 // Sign-extended immediate classes. We don't need to define the full lattice
591 // here because there is no instruction with an ambiguity between ImmSExti64i32
594 // The strange ranges come from the fact that the assembler always works with
595 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
596 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
599 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
600 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
601 let Name = "ImmSExti64i32";
604 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
605 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
606 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
607 let Name = "ImmSExti16i8";
608 let SuperClasses = [ImmSExti64i32AsmOperand];
611 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
612 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
613 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
614 let Name = "ImmSExti32i8";
618 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
619 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
620 let Name = "ImmSExti64i8";
621 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
622 ImmSExti64i32AsmOperand];
625 // Unsigned immediate used by SSE/AVX instructions
627 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
628 def ImmUnsignedi8AsmOperand : AsmOperandClass {
629 let Name = "ImmUnsignedi8";
630 let RenderMethod = "addImmOperands";
633 // A couple of more descriptive operand definitions.
634 // 16-bits but only 8 bits are significant.
635 def i16i8imm : Operand<i16> {
636 let ParserMatchClass = ImmSExti16i8AsmOperand;
637 let OperandType = "OPERAND_IMMEDIATE";
639 // 32-bits but only 8 bits are significant.
640 def i32i8imm : Operand<i32> {
641 let ParserMatchClass = ImmSExti32i8AsmOperand;
642 let OperandType = "OPERAND_IMMEDIATE";
645 // 64-bits but only 32 bits are significant.
646 def i64i32imm : Operand<i64> {
647 let ParserMatchClass = ImmSExti64i32AsmOperand;
648 let OperandType = "OPERAND_IMMEDIATE";
651 // 64-bits but only 8 bits are significant.
652 def i64i8imm : Operand<i64> {
653 let ParserMatchClass = ImmSExti64i8AsmOperand;
654 let OperandType = "OPERAND_IMMEDIATE";
657 // Unsigned 8-bit immediate used by SSE/AVX instructions.
658 def u8imm : Operand<i8> {
659 let PrintMethod = "printU8Imm";
660 let ParserMatchClass = ImmUnsignedi8AsmOperand;
661 let OperandType = "OPERAND_IMMEDIATE";
664 // 32-bit immediate but only 8-bits are significant and they are unsigned.
665 // Used by some SSE/AVX instructions that use intrinsics.
666 def i32u8imm : Operand<i32> {
667 let PrintMethod = "printU8Imm";
668 let ParserMatchClass = ImmUnsignedi8AsmOperand;
669 let OperandType = "OPERAND_IMMEDIATE";
672 // 64-bits but only 32 bits are significant, and those bits are treated as being
674 def i64i32imm_pcrel : Operand<i64> {
675 let PrintMethod = "printPCRelImm";
676 let ParserMatchClass = X86AbsMemAsmOperand;
677 let OperandType = "OPERAND_PCREL";
680 def lea64_32mem : Operand<i32> {
681 let PrintMethod = "printanymem";
682 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
683 let ParserMatchClass = X86MemAsmOperand;
686 // Memory operands that use 64-bit pointers in both ILP32 and LP64.
687 def lea64mem : Operand<i64> {
688 let PrintMethod = "printanymem";
689 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
690 let ParserMatchClass = X86MemAsmOperand;
694 //===----------------------------------------------------------------------===//
695 // X86 Complex Pattern Definitions.
698 // Define X86 specific addressing mode.
699 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
700 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
701 [add, sub, mul, X86mul_imm, shl, or, frameindex],
703 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
704 def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr",
705 [add, sub, mul, X86mul_imm, shl, or,
706 frameindex, X86WrapperRIP],
709 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
710 [tglobaltlsaddr], []>;
712 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
713 [tglobaltlsaddr], []>;
715 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
716 [add, sub, mul, X86mul_imm, shl, or, frameindex,
719 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
720 [tglobaltlsaddr], []>;
722 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
723 [tglobaltlsaddr], []>;
725 def vectoraddr : ComplexPattern<iPTR, 5, "SelectVectorAddr", [],[SDNPWantParent]>;
727 //===----------------------------------------------------------------------===//
728 // X86 Instruction Predicate Definitions.
729 def HasCMov : Predicate<"Subtarget->hasCMov()">;
730 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
732 def HasMMX : Predicate<"Subtarget->hasMMX()">;
733 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
734 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
735 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
736 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
737 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
738 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
739 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
740 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
741 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
742 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
743 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
744 def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">;
745 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
746 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
747 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
748 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
749 def HasAVX : Predicate<"Subtarget->hasAVX()">;
750 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
751 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
752 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">,
753 AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">;
754 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
755 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
756 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
757 def HasCDI : Predicate<"Subtarget->hasCDI()">,
758 AssemblerPredicate<"FeatureCDI", "AVX-512 CD ISA">;
759 def HasPFI : Predicate<"Subtarget->hasPFI()">,
760 AssemblerPredicate<"FeaturePFI", "AVX-512 PF ISA">;
761 def HasERI : Predicate<"Subtarget->hasERI()">,
762 AssemblerPredicate<"FeatureERI", "AVX-512 ER ISA">;
763 def HasDQI : Predicate<"Subtarget->hasDQI()">,
764 AssemblerPredicate<"FeatureDQI", "AVX-512 DQ ISA">;
765 def NoDQI : Predicate<"!Subtarget->hasDQI()">;
766 def HasBWI : Predicate<"Subtarget->hasBWI()">,
767 AssemblerPredicate<"FeatureBWI", "AVX-512 BW ISA">;
768 def NoBWI : Predicate<"!Subtarget->hasBWI()">;
769 def HasVLX : Predicate<"Subtarget->hasVLX()">,
770 AssemblerPredicate<"FeatureVLX", "AVX-512 VL ISA">;
771 def NoVLX : Predicate<"!Subtarget->hasVLX()">;
772 def NoVLX_Or_NoBWI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasBWI()">;
774 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
775 def HasAES : Predicate<"Subtarget->hasAES()">;
776 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
777 def HasFMA : Predicate<"Subtarget->hasFMA()">;
778 def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">;
779 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
780 def HasXOP : Predicate<"Subtarget->hasXOP()">;
781 def HasTBM : Predicate<"Subtarget->hasTBM()">;
782 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
783 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
784 def HasF16C : Predicate<"Subtarget->hasF16C()">;
785 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
786 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
787 def HasBMI : Predicate<"Subtarget->hasBMI()">;
788 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
789 def HasRTM : Predicate<"Subtarget->hasRTM()">;
790 def HasHLE : Predicate<"Subtarget->hasHLE()">;
791 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
792 def HasADX : Predicate<"Subtarget->hasADX()">;
793 def HasSHA : Predicate<"Subtarget->hasSHA()">;
794 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
795 def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
796 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
797 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
798 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
799 def HasMPX : Predicate<"Subtarget->hasMPX()">;
800 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
801 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
802 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
803 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
804 AssemblerPredicate<"Mode64Bit", "64-bit mode">;
805 def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">;
806 def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">;
807 def In16BitMode : Predicate<"Subtarget->is16Bit()">,
808 AssemblerPredicate<"Mode16Bit", "16-bit mode">;
809 def Not16BitMode : Predicate<"!Subtarget->is16Bit()">,
810 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">;
811 def In32BitMode : Predicate<"Subtarget->is32Bit()">,
812 AssemblerPredicate<"Mode32Bit", "32-bit mode">;
813 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
814 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
815 def IsPS4 : Predicate<"Subtarget->isTargetPS4()">;
816 def NotPS4 : Predicate<"!Subtarget->isTargetPS4()">;
817 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
818 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
819 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
820 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
821 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
822 "TM.getCodeModel() != CodeModel::Kernel">;
823 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
824 "TM.getCodeModel() == CodeModel::Kernel">;
825 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
826 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
827 def OptForSize : Predicate<"OptForSize">;
828 def OptForSpeed : Predicate<"!OptForSize">;
829 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
830 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
831 def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">;
832 def NotSlowIncDec : Predicate<"!Subtarget->slowIncDec()">;
833 def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">;
835 //===----------------------------------------------------------------------===//
836 // X86 Instruction Format Definitions.
839 include "X86InstrFormats.td"
841 //===----------------------------------------------------------------------===//
842 // Pattern fragments.
845 // X86 specific condition code. These correspond to CondCode in
846 // X86InstrInfo.h. They must be kept in synch.
847 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
848 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
849 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
850 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
851 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
852 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
853 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
854 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
855 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
856 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
857 def X86_COND_NO : PatLeaf<(i8 10)>;
858 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
859 def X86_COND_NS : PatLeaf<(i8 12)>;
860 def X86_COND_O : PatLeaf<(i8 13)>;
861 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
862 def X86_COND_S : PatLeaf<(i8 15)>;
864 // Predicate used to help when pattern matching LZCNT/TZCNT.
865 def X86_COND_E_OR_NE : ImmLeaf<i8, [{
866 return (Imm == X86::COND_E) || (Imm == X86::COND_NE);
870 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
871 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
872 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
874 // If we have multiple users of an immediate, it's much smaller to reuse
875 // the register, rather than encode the immediate in every instruction.
876 // This has the risk of increasing register pressure from stretched live
877 // ranges, however, the immediates should be trivial to rematerialize by
878 // the RA in the event of high register pressure.
879 // TODO : This is currently enabled for stores and binary ops. There are more
880 // cases for which this can be enabled, though this catches the bulk of the
882 // TODO2 : This should really also be enabled under O2, but there's currently
883 // an issue with RA where we don't pull the constants into their users
884 // when we rematerialize them. I'll follow-up on enabling O2 after we fix that
886 // TODO3 : This is currently limited to single basic blocks (DAG creation
887 // pulls block immediates to the top and merges them if necessary).
888 // Eventually, it would be nice to allow ConstantHoisting to merge constants
889 // globally for potentially added savings.
891 def imm8_su : PatLeaf<(i8 imm), [{
892 return !shouldAvoidImmediateInstFormsForSize(N);
894 def imm16_su : PatLeaf<(i16 imm), [{
895 return !shouldAvoidImmediateInstFormsForSize(N);
897 def imm32_su : PatLeaf<(i32 imm), [{
898 return !shouldAvoidImmediateInstFormsForSize(N);
901 def i16immSExt8_su : PatLeaf<(i16immSExt8), [{
902 return !shouldAvoidImmediateInstFormsForSize(N);
904 def i32immSExt8_su : PatLeaf<(i32immSExt8), [{
905 return !shouldAvoidImmediateInstFormsForSize(N);
909 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
912 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
914 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
916 def i64immZExt32SExt8 : ImmLeaf<i64, [{
917 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
920 // Helper fragments for loads.
921 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
922 // known to be 32-bit aligned or better. Ditto for i8 to i16.
923 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
924 LoadSDNode *LD = cast<LoadSDNode>(N);
925 ISD::LoadExtType ExtType = LD->getExtensionType();
926 if (ExtType == ISD::NON_EXTLOAD)
928 if (ExtType == ISD::EXTLOAD)
929 return LD->getAlignment() >= 2 && !LD->isVolatile();
933 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
934 LoadSDNode *LD = cast<LoadSDNode>(N);
935 ISD::LoadExtType ExtType = LD->getExtensionType();
936 if (ExtType == ISD::EXTLOAD)
937 return LD->getAlignment() >= 2 && !LD->isVolatile();
941 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
942 LoadSDNode *LD = cast<LoadSDNode>(N);
943 ISD::LoadExtType ExtType = LD->getExtensionType();
944 if (ExtType == ISD::NON_EXTLOAD)
946 if (ExtType == ISD::EXTLOAD)
947 return LD->getAlignment() >= 4 && !LD->isVolatile();
951 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
952 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
953 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
954 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
955 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
957 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
958 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
959 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
960 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
961 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
962 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
964 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
965 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
966 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
967 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
968 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
969 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
970 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
971 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
972 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
973 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
975 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
976 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
977 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
978 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
979 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
980 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
981 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
982 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
983 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
984 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
987 // An 'and' node with a single use.
988 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
989 return N->hasOneUse();
991 // An 'srl' node with a single use.
992 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
993 return N->hasOneUse();
995 // An 'trunc' node with a single use.
996 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
997 return N->hasOneUse();
1000 //===----------------------------------------------------------------------===//
1001 // Instruction list.
1005 let hasSideEffects = 0, SchedRW = [WriteZero] in {
1006 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
1007 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero),
1008 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
1009 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero),
1010 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
1014 // Constructing a stack frame.
1015 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
1016 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
1018 let SchedRW = [WriteALU] in {
1019 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in
1020 def LEAVE : I<0xC9, RawFrm,
1021 (outs), (ins), "leave", [], IIC_LEAVE>,
1022 Requires<[Not64BitMode]>;
1024 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in
1025 def LEAVE64 : I<0xC9, RawFrm,
1026 (outs), (ins), "leave", [], IIC_LEAVE>,
1027 Requires<[In64BitMode]>;
1030 //===----------------------------------------------------------------------===//
1031 // Miscellaneous Instructions.
1034 let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in {
1035 let mayLoad = 1, SchedRW = [WriteLoad] in {
1036 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
1037 IIC_POP_REG16>, OpSize16;
1038 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
1039 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
1040 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
1041 IIC_POP_REG>, OpSize16;
1042 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
1043 IIC_POP_MEM>, OpSize16;
1044 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
1045 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
1046 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
1047 IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>;
1048 } // mayLoad, SchedRW
1050 let mayStore = 1, SchedRW = [WriteStore] in {
1051 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
1052 IIC_PUSH_REG>, OpSize16;
1053 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
1054 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
1055 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
1056 IIC_PUSH_REG>, OpSize16;
1057 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
1058 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
1060 def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
1061 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16;
1062 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1063 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16;
1065 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
1066 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1067 Requires<[Not64BitMode]>;
1068 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
1069 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1070 Requires<[Not64BitMode]>;
1071 } // mayStore, SchedRW
1073 let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in {
1074 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
1075 IIC_PUSH_MEM>, OpSize16;
1076 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
1077 IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>;
1078 } // mayLoad, mayStore, SchedRW
1082 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
1083 SchedRW = [WriteLoad] in {
1084 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>,
1086 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
1087 OpSize32, Requires<[Not64BitMode]>;
1090 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0,
1091 SchedRW = [WriteStore] in {
1092 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
1094 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
1095 OpSize32, Requires<[Not64BitMode]>;
1098 let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in {
1099 let mayLoad = 1, SchedRW = [WriteLoad] in {
1100 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1101 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
1102 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1103 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
1104 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [],
1105 IIC_POP_MEM>, OpSize32, Requires<[In64BitMode]>;
1106 } // mayLoad, SchedRW
1107 let mayStore = 1, SchedRW = [WriteStore] in {
1108 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1109 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1110 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1111 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1112 } // mayStore, SchedRW
1113 let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in {
1114 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
1115 IIC_PUSH_MEM>, OpSize32, Requires<[In64BitMode]>;
1116 } // mayLoad, mayStore, SchedRW
1119 let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1,
1120 SchedRW = [WriteStore] in {
1121 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
1122 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
1123 def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
1124 "push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1125 Requires<[In64BitMode]>;
1128 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
1129 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
1130 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>;
1131 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in
1132 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
1133 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>;
1135 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
1136 mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in {
1137 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>,
1138 OpSize32, Requires<[Not64BitMode]>;
1139 def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>,
1140 OpSize16, Requires<[Not64BitMode]>;
1142 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
1143 mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
1144 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>,
1145 OpSize32, Requires<[Not64BitMode]>;
1146 def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>,
1147 OpSize16, Requires<[Not64BitMode]>;
1150 let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
1151 // GR32 = bswap GR32
1152 def BSWAP32r : I<0xC8, AddRegFrm,
1153 (outs GR32:$dst), (ins GR32:$src),
1155 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB;
1157 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
1159 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
1160 } // Constraints = "$src = $dst", SchedRW
1162 // Bit scan instructions.
1163 let Defs = [EFLAGS] in {
1164 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1165 "bsf{w}\t{$src, $dst|$dst, $src}",
1166 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
1167 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1168 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1169 "bsf{w}\t{$src, $dst|$dst, $src}",
1170 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
1171 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1172 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1173 "bsf{l}\t{$src, $dst|$dst, $src}",
1174 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
1175 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1176 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1177 "bsf{l}\t{$src, $dst|$dst, $src}",
1178 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
1179 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1180 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1181 "bsf{q}\t{$src, $dst|$dst, $src}",
1182 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
1183 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1184 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1185 "bsf{q}\t{$src, $dst|$dst, $src}",
1186 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
1187 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1189 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1190 "bsr{w}\t{$src, $dst|$dst, $src}",
1191 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))],
1192 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1193 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1194 "bsr{w}\t{$src, $dst|$dst, $src}",
1195 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
1196 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1197 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1198 "bsr{l}\t{$src, $dst|$dst, $src}",
1199 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
1200 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1201 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1202 "bsr{l}\t{$src, $dst|$dst, $src}",
1203 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
1204 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1205 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1206 "bsr{q}\t{$src, $dst|$dst, $src}",
1207 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))],
1208 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1209 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1210 "bsr{q}\t{$src, $dst|$dst, $src}",
1211 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
1212 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1213 } // Defs = [EFLAGS]
1215 let SchedRW = [WriteMicrocoded] in {
1216 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1217 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
1218 def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src),
1219 "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1220 def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src),
1221 "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16;
1222 def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src),
1223 "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize32;
1224 def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src),
1225 "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1228 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1229 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
1230 def STOSB : I<0xAA, RawFrmDst, (outs dstidx8:$dst), (ins),
1231 "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>;
1232 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
1233 def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins),
1234 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16;
1235 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
1236 def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins),
1237 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32;
1238 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
1239 def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins),
1240 "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>;
1242 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1243 let Defs = [EDI,EFLAGS], Uses = [AL,EDI,EFLAGS] in
1244 def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst),
1245 "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>;
1246 let Defs = [EDI,EFLAGS], Uses = [AX,EDI,EFLAGS] in
1247 def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst),
1248 "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16;
1249 let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,EFLAGS] in
1250 def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst),
1251 "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32;
1252 let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,EFLAGS] in
1253 def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst),
1254 "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>;
1256 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1257 let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,EFLAGS] in {
1258 def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src),
1259 "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1260 def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src),
1261 "cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16;
1262 def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src),
1263 "cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize32;
1264 def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src),
1265 "cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1269 //===----------------------------------------------------------------------===//
1270 // Move Instructions.
1272 let SchedRW = [WriteMove] in {
1273 let hasSideEffects = 0 in {
1274 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1275 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1276 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1277 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1278 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1279 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1280 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1281 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1284 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1285 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1286 "mov{b}\t{$src, $dst|$dst, $src}",
1287 [(set GR8:$dst, imm:$src)], IIC_MOV>;
1288 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1289 "mov{w}\t{$src, $dst|$dst, $src}",
1290 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize16;
1291 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1292 "mov{l}\t{$src, $dst|$dst, $src}",
1293 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize32;
1294 def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1295 "mov{q}\t{$src, $dst|$dst, $src}",
1296 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
1298 let isReMaterializable = 1 in {
1299 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
1300 "movabs{q}\t{$src, $dst|$dst, $src}",
1301 [(set GR64:$dst, imm:$src)], IIC_MOV>;
1304 // Longer forms that use a ModR/M byte. Needed for disassembler
1305 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1306 def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src),
1307 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1308 def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src),
1309 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1310 def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src),
1311 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1315 let SchedRW = [WriteStore] in {
1316 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1317 "mov{b}\t{$src, $dst|$dst, $src}",
1318 [(store (i8 imm8_su:$src), addr:$dst)], IIC_MOV_MEM>;
1319 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1320 "mov{w}\t{$src, $dst|$dst, $src}",
1321 [(store (i16 imm16_su:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
1322 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1323 "mov{l}\t{$src, $dst|$dst, $src}",
1324 [(store (i32 imm32_su:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32;
1325 def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1326 "mov{q}\t{$src, $dst|$dst, $src}",
1327 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
1330 let hasSideEffects = 0 in {
1332 /// Memory offset versions of moves. The immediate is an address mode sized
1333 /// offset from the segment base.
1334 let SchedRW = [WriteALU] in {
1335 let mayLoad = 1 in {
1337 def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src),
1338 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
1341 def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src),
1342 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1345 def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src),
1346 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1349 def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src),
1350 "mov{q}\t{$src, %rax|rax, $src}", [], IIC_MOV_MEM>,
1354 def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src),
1355 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, AdSize16;
1357 def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src),
1358 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1361 def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src),
1362 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1365 let mayStore = 1 in {
1367 def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs offset32_8:$dst), (ins),
1368 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize32;
1370 def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_16:$dst), (ins),
1371 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1374 def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_32:$dst), (ins),
1375 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1378 def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs offset32_64:$dst), (ins),
1379 "mov{q}\t{%rax, $dst|$dst, rax}", [], IIC_MOV_MEM>,
1383 def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs offset16_8:$dst), (ins),
1384 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize16;
1386 def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_16:$dst), (ins),
1387 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1390 def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_32:$dst), (ins),
1391 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1396 // These forms all have full 64-bit absolute addresses in their instructions
1397 // and use the movabs mnemonic to indicate this specific form.
1398 let mayLoad = 1 in {
1400 def MOV8ao64 : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src),
1401 "movabs{b}\t{$src, %al|al, $src}", []>, AdSize64;
1403 def MOV16ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src),
1404 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16, AdSize64;
1406 def MOV32ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src),
1407 "movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32,
1410 def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src),
1411 "movabs{q}\t{$src, %rax|rax, $src}", []>, AdSize64;
1414 let mayStore = 1 in {
1416 def MOV8o64a : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset64_8:$dst), (ins),
1417 "movabs{b}\t{%al, $dst|$dst, al}", []>, AdSize64;
1419 def MOV16o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_16:$dst), (ins),
1420 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16, AdSize64;
1422 def MOV32o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_32:$dst), (ins),
1423 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32,
1426 def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs offset64_64:$dst), (ins),
1427 "movabs{q}\t{%rax, $dst|$dst, rax}", []>, AdSize64;
1429 } // hasSideEffects = 0
1431 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
1432 SchedRW = [WriteMove] in {
1433 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1434 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1435 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1436 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1437 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1438 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1439 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1440 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1443 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1444 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1445 "mov{b}\t{$src, $dst|$dst, $src}",
1446 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1447 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1448 "mov{w}\t{$src, $dst|$dst, $src}",
1449 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize16;
1450 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1451 "mov{l}\t{$src, $dst|$dst, $src}",
1452 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32;
1453 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1454 "mov{q}\t{$src, $dst|$dst, $src}",
1455 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1458 let SchedRW = [WriteStore] in {
1459 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1460 "mov{b}\t{$src, $dst|$dst, $src}",
1461 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1462 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1463 "mov{w}\t{$src, $dst|$dst, $src}",
1464 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
1465 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1466 "mov{l}\t{$src, $dst|$dst, $src}",
1467 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32;
1468 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1469 "mov{q}\t{$src, $dst|$dst, $src}",
1470 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1473 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1474 // that they can be used for copying and storing h registers, which can't be
1475 // encoded when a REX prefix is present.
1476 let isCodeGenOnly = 1 in {
1477 let hasSideEffects = 0 in
1478 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1479 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1480 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
1482 let mayStore = 1, hasSideEffects = 0 in
1483 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1484 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1485 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1486 IIC_MOV_MEM>, Sched<[WriteStore]>;
1487 let mayLoad = 1, hasSideEffects = 0,
1488 canFoldAsLoad = 1, isReMaterializable = 1 in
1489 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1490 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1491 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1492 IIC_MOV_MEM>, Sched<[WriteLoad]>;
1496 // Condition code ops, incl. set if equal/not equal/...
1497 let SchedRW = [WriteALU] in {
1498 let Defs = [EFLAGS], Uses = [AH] in
1499 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1500 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
1501 let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in
1502 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1503 IIC_AHF>; // AH = flags
1506 //===----------------------------------------------------------------------===//
1507 // Bit tests instructions: BT, BTS, BTR, BTC.
1509 let Defs = [EFLAGS] in {
1510 let SchedRW = [WriteALU] in {
1511 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1512 "bt{w}\t{$src2, $src1|$src1, $src2}",
1513 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1515 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1516 "bt{l}\t{$src2, $src1|$src1, $src2}",
1517 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,
1519 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1520 "bt{q}\t{$src2, $src1|$src1, $src2}",
1521 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1524 // Unlike with the register+register form, the memory+register form of the
1525 // bt instruction does not ignore the high bits of the index. From ISel's
1526 // perspective, this is pretty bizarre. Make these instructions disassembly
1529 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
1530 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1531 "bt{w}\t{$src2, $src1|$src1, $src2}",
1532 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1533 // (implicit EFLAGS)]
1535 >, OpSize16, TB, Requires<[FastBTMem]>;
1536 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1537 "bt{l}\t{$src2, $src1|$src1, $src2}",
1538 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1539 // (implicit EFLAGS)]
1541 >, OpSize32, TB, Requires<[FastBTMem]>;
1542 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1543 "bt{q}\t{$src2, $src1|$src1, $src2}",
1544 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1545 // (implicit EFLAGS)]
1550 let SchedRW = [WriteALU] in {
1551 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1552 "bt{w}\t{$src2, $src1|$src1, $src2}",
1553 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1554 IIC_BT_RI>, OpSize16, TB;
1555 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1556 "bt{l}\t{$src2, $src1|$src1, $src2}",
1557 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1558 IIC_BT_RI>, OpSize32, TB;
1559 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1560 "bt{q}\t{$src2, $src1|$src1, $src2}",
1561 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1565 // Note that these instructions don't need FastBTMem because that
1566 // only applies when the other operand is in a register. When it's
1567 // an immediate, bt is still fast.
1568 let SchedRW = [WriteALU] in {
1569 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1570 "bt{w}\t{$src2, $src1|$src1, $src2}",
1571 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1572 ], IIC_BT_MI>, OpSize16, TB;
1573 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1574 "bt{l}\t{$src2, $src1|$src1, $src2}",
1575 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1576 ], IIC_BT_MI>, OpSize32, TB;
1577 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1578 "bt{q}\t{$src2, $src1|$src1, $src2}",
1579 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1580 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1583 let hasSideEffects = 0 in {
1584 let SchedRW = [WriteALU] in {
1585 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1586 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1588 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1589 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1591 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1592 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1595 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1596 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1597 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1599 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1600 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1602 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1603 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1606 let SchedRW = [WriteALU] in {
1607 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1608 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1610 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1611 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1613 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1614 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1617 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1618 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1619 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1621 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1622 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1624 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1625 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1628 let SchedRW = [WriteALU] in {
1629 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1630 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1632 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1633 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1635 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1636 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1639 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1640 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1641 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1643 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1644 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1646 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1647 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1650 let SchedRW = [WriteALU] in {
1651 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1652 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1654 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1655 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1657 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1658 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1661 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1662 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1663 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1665 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1666 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1668 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1669 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1672 let SchedRW = [WriteALU] in {
1673 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1674 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1676 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1677 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1679 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1680 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1683 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1684 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1685 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1687 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1688 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1690 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1691 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1694 let SchedRW = [WriteALU] in {
1695 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1696 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1698 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1699 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1701 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1702 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1705 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1706 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1707 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1709 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1710 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1712 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1713 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1715 } // hasSideEffects = 0
1716 } // Defs = [EFLAGS]
1719 //===----------------------------------------------------------------------===//
1723 // Atomic swap. These are just normal xchg instructions. But since a memory
1724 // operand is referenced, the atomicity is ensured.
1725 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
1726 InstrItinClass itin> {
1727 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
1728 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
1729 (ins GR8:$val, i8mem:$ptr),
1730 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
1733 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
1735 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
1736 (ins GR16:$val, i16mem:$ptr),
1737 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
1740 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
1742 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
1743 (ins GR32:$val, i32mem:$ptr),
1744 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
1747 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
1749 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
1750 (ins GR64:$val, i64mem:$ptr),
1751 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
1754 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
1759 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
1761 // Swap between registers.
1762 let SchedRW = [WriteALU] in {
1763 let Constraints = "$val = $dst" in {
1764 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1765 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1766 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1767 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1769 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1770 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1772 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1773 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1776 // Swap between EAX and other registers.
1777 let Uses = [AX], Defs = [AX] in
1778 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1779 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16;
1780 let Uses = [EAX], Defs = [EAX] in
1781 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1782 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1783 OpSize32, Requires<[Not64BitMode]>;
1784 let Uses = [EAX], Defs = [EAX] in
1785 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1786 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1787 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1788 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1789 OpSize32, Requires<[In64BitMode]>;
1790 let Uses = [RAX], Defs = [RAX] in
1791 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1792 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>;
1795 let SchedRW = [WriteALU] in {
1796 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1797 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1798 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1799 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1801 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1802 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1804 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1805 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1808 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1809 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1810 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1811 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1812 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1814 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1815 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1817 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1818 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1822 let SchedRW = [WriteALU] in {
1823 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1824 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1825 IIC_CMPXCHG_REG8>, TB;
1826 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1827 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1828 IIC_CMPXCHG_REG>, TB, OpSize16;
1829 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1830 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1831 IIC_CMPXCHG_REG>, TB, OpSize32;
1832 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1833 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1834 IIC_CMPXCHG_REG>, TB;
1837 let SchedRW = [WriteALULd, WriteRMW] in {
1838 let mayLoad = 1, mayStore = 1 in {
1839 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1840 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1841 IIC_CMPXCHG_MEM8>, TB;
1842 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1843 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1844 IIC_CMPXCHG_MEM>, TB, OpSize16;
1845 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1846 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1847 IIC_CMPXCHG_MEM>, TB, OpSize32;
1848 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1849 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1850 IIC_CMPXCHG_MEM>, TB;
1853 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1854 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1855 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1857 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1858 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1859 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1860 TB, Requires<[HasCmpxchg16b]>;
1864 // Lock instruction prefix
1865 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1867 // Rex64 instruction prefix
1868 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>,
1869 Requires<[In64BitMode]>;
1871 // Data16 instruction prefix
1872 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1874 // Repeat string operation instruction prefixes
1875 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1876 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1877 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1878 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1879 // Repeat while not equal (used with CMPS and SCAS)
1880 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1884 // String manipulation instructions
1885 let SchedRW = [WriteMicrocoded] in {
1886 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1887 let Defs = [AL,ESI], Uses = [ESI,EFLAGS] in
1888 def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src),
1889 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>;
1890 let Defs = [AX,ESI], Uses = [ESI,EFLAGS] in
1891 def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src),
1892 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16;
1893 let Defs = [EAX,ESI], Uses = [ESI,EFLAGS] in
1894 def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src),
1895 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32;
1896 let Defs = [RAX,ESI], Uses = [ESI,EFLAGS] in
1897 def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),
1898 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>;
1901 let SchedRW = [WriteSystem] in {
1902 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1903 let Defs = [ESI], Uses = [DX,ESI,EFLAGS] in {
1904 def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src),
1905 "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>;
1906 def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src),
1907 "outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16;
1908 def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src),
1909 "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32;
1912 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1913 let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in {
1914 def INSB : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins),
1915 "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
1916 def INSW : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins),
1917 "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
1918 def INSL : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins),
1919 "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32;
1923 // Flag instructions
1924 let SchedRW = [WriteALU] in {
1925 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1926 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1927 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1928 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1929 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1930 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1931 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1933 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1936 // Table lookup instructions
1937 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,
1940 let SchedRW = [WriteMicrocoded] in {
1941 // ASCII Adjust After Addition
1942 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1943 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1944 Requires<[Not64BitMode]>;
1946 // ASCII Adjust AX Before Division
1947 // sets AL, AH and EFLAGS and uses AL and AH
1948 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1949 "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>;
1951 // ASCII Adjust AX After Multiply
1952 // sets AL, AH and EFLAGS and uses AL
1953 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1954 "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>;
1956 // ASCII Adjust AL After Subtraction - sets
1957 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1958 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1959 Requires<[Not64BitMode]>;
1961 // Decimal Adjust AL after Addition
1962 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1963 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1964 Requires<[Not64BitMode]>;
1966 // Decimal Adjust AL after Subtraction
1967 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1968 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1969 Requires<[Not64BitMode]>;
1972 let SchedRW = [WriteSystem] in {
1973 // Check Array Index Against Bounds
1974 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1975 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,
1976 Requires<[Not64BitMode]>;
1977 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1978 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize32,
1979 Requires<[Not64BitMode]>;
1981 // Adjust RPL Field of Segment Selector
1982 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1983 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1984 Requires<[Not64BitMode]>;
1985 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1986 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1987 Requires<[Not64BitMode]>;
1990 //===----------------------------------------------------------------------===//
1991 // MOVBE Instructions
1993 let Predicates = [HasMOVBE] in {
1994 let SchedRW = [WriteALULd] in {
1995 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1996 "movbe{w}\t{$src, $dst|$dst, $src}",
1997 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1999 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2000 "movbe{l}\t{$src, $dst|$dst, $src}",
2001 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
2003 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2004 "movbe{q}\t{$src, $dst|$dst, $src}",
2005 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
2008 let SchedRW = [WriteStore] in {
2009 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
2010 "movbe{w}\t{$src, $dst|$dst, $src}",
2011 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
2013 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2014 "movbe{l}\t{$src, $dst|$dst, $src}",
2015 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
2017 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2018 "movbe{q}\t{$src, $dst|$dst, $src}",
2019 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
2024 //===----------------------------------------------------------------------===//
2025 // RDRAND Instruction
2027 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
2028 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
2030 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
2031 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
2033 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, TB;
2034 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
2036 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
2039 //===----------------------------------------------------------------------===//
2040 // RDSEED Instruction
2042 let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
2043 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
2045 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
2046 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
2048 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB;
2049 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
2051 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
2054 //===----------------------------------------------------------------------===//
2055 // LZCNT Instruction
2057 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
2058 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2059 "lzcnt{w}\t{$src, $dst|$dst, $src}",
2060 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
2062 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2063 "lzcnt{w}\t{$src, $dst|$dst, $src}",
2064 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
2065 (implicit EFLAGS)]>, XS, OpSize16;
2067 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2068 "lzcnt{l}\t{$src, $dst|$dst, $src}",
2069 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS,
2071 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2072 "lzcnt{l}\t{$src, $dst|$dst, $src}",
2073 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
2074 (implicit EFLAGS)]>, XS, OpSize32;
2076 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2077 "lzcnt{q}\t{$src, $dst|$dst, $src}",
2078 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
2080 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2081 "lzcnt{q}\t{$src, $dst|$dst, $src}",
2082 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
2083 (implicit EFLAGS)]>, XS;
2086 let Predicates = [HasLZCNT] in {
2087 def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
2088 (X86cmp GR16:$src, (i16 0))),
2089 (LZCNT16rr GR16:$src)>;
2090 def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
2091 (X86cmp GR32:$src, (i32 0))),
2092 (LZCNT32rr GR32:$src)>;
2093 def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
2094 (X86cmp GR64:$src, (i64 0))),
2095 (LZCNT64rr GR64:$src)>;
2096 def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_E_OR_NE),
2097 (X86cmp GR16:$src, (i16 0))),
2098 (LZCNT16rr GR16:$src)>;
2099 def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_E_OR_NE),
2100 (X86cmp GR32:$src, (i32 0))),
2101 (LZCNT32rr GR32:$src)>;
2102 def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_E_OR_NE),
2103 (X86cmp GR64:$src, (i64 0))),
2104 (LZCNT64rr GR64:$src)>;
2106 def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
2107 (X86cmp (loadi16 addr:$src), (i16 0))),
2108 (LZCNT16rm addr:$src)>;
2109 def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
2110 (X86cmp (loadi32 addr:$src), (i32 0))),
2111 (LZCNT32rm addr:$src)>;
2112 def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
2113 (X86cmp (loadi64 addr:$src), (i64 0))),
2114 (LZCNT64rm addr:$src)>;
2115 def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
2116 (X86cmp (loadi16 addr:$src), (i16 0))),
2117 (LZCNT16rm addr:$src)>;
2118 def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
2119 (X86cmp (loadi32 addr:$src), (i32 0))),
2120 (LZCNT32rm addr:$src)>;
2121 def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
2122 (X86cmp (loadi64 addr:$src), (i64 0))),
2123 (LZCNT64rm addr:$src)>;
2126 //===----------------------------------------------------------------------===//
2129 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2130 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2131 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2132 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
2134 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2135 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2136 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
2137 (implicit EFLAGS)]>, XS, OpSize16;
2139 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2140 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2141 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS,
2143 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2144 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2145 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
2146 (implicit EFLAGS)]>, XS, OpSize32;
2148 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2149 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2150 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
2152 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2153 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2154 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
2155 (implicit EFLAGS)]>, XS;
2158 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
2159 RegisterClass RC, X86MemOperand x86memop> {
2160 let hasSideEffects = 0 in {
2161 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
2162 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2165 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
2166 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2171 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2172 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>;
2173 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
2174 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>;
2175 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W;
2176 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>;
2177 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W;
2180 //===----------------------------------------------------------------------===//
2181 // Pattern fragments to auto generate BMI instructions.
2182 //===----------------------------------------------------------------------===//
2184 let Predicates = [HasBMI] in {
2185 // FIXME: patterns for the load versions are not implemented
2186 def : Pat<(and GR32:$src, (add GR32:$src, -1)),
2187 (BLSR32rr GR32:$src)>;
2188 def : Pat<(and GR64:$src, (add GR64:$src, -1)),
2189 (BLSR64rr GR64:$src)>;
2191 def : Pat<(xor GR32:$src, (add GR32:$src, -1)),
2192 (BLSMSK32rr GR32:$src)>;
2193 def : Pat<(xor GR64:$src, (add GR64:$src, -1)),
2194 (BLSMSK64rr GR64:$src)>;
2196 def : Pat<(and GR32:$src, (ineg GR32:$src)),
2197 (BLSI32rr GR32:$src)>;
2198 def : Pat<(and GR64:$src, (ineg GR64:$src)),
2199 (BLSI64rr GR64:$src)>;
2202 let Predicates = [HasBMI] in {
2203 def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
2204 (X86cmp GR16:$src, (i16 0))),
2205 (TZCNT16rr GR16:$src)>;
2206 def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
2207 (X86cmp GR32:$src, (i32 0))),
2208 (TZCNT32rr GR32:$src)>;
2209 def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
2210 (X86cmp GR64:$src, (i64 0))),
2211 (TZCNT64rr GR64:$src)>;
2212 def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_E_OR_NE),
2213 (X86cmp GR16:$src, (i16 0))),
2214 (TZCNT16rr GR16:$src)>;
2215 def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_E_OR_NE),
2216 (X86cmp GR32:$src, (i32 0))),
2217 (TZCNT32rr GR32:$src)>;
2218 def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_E_OR_NE),
2219 (X86cmp GR64:$src, (i64 0))),
2220 (TZCNT64rr GR64:$src)>;
2222 def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
2223 (X86cmp (loadi16 addr:$src), (i16 0))),
2224 (TZCNT16rm addr:$src)>;
2225 def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
2226 (X86cmp (loadi32 addr:$src), (i32 0))),
2227 (TZCNT32rm addr:$src)>;
2228 def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
2229 (X86cmp (loadi64 addr:$src), (i64 0))),
2230 (TZCNT64rm addr:$src)>;
2231 def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
2232 (X86cmp (loadi16 addr:$src), (i16 0))),
2233 (TZCNT16rm addr:$src)>;
2234 def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
2235 (X86cmp (loadi32 addr:$src), (i32 0))),
2236 (TZCNT32rm addr:$src)>;
2237 def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
2238 (X86cmp (loadi64 addr:$src), (i64 0))),
2239 (TZCNT64rm addr:$src)>;
2243 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
2244 X86MemOperand x86memop, Intrinsic Int,
2246 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2247 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2248 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
2250 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
2251 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2252 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
2253 (implicit EFLAGS)]>, T8PS, VEX_4VOp3;
2256 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2257 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
2258 int_x86_bmi_bextr_32, loadi32>;
2259 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
2260 int_x86_bmi_bextr_64, loadi64>, VEX_W;
2263 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
2264 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
2265 int_x86_bmi_bzhi_32, loadi32>;
2266 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
2267 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
2271 def CountTrailingOnes : SDNodeXForm<imm, [{
2272 // Count the trailing ones in the immediate.
2273 return getI8Imm(countTrailingOnes(N->getZExtValue()), SDLoc(N));
2276 def BZHIMask : ImmLeaf<i64, [{
2277 return isMask_64(Imm) && (countTrailingOnes<uint64_t>(Imm) > 32);
2280 let Predicates = [HasBMI2] in {
2281 def : Pat<(and GR64:$src, BZHIMask:$mask),
2282 (BZHI64rr GR64:$src,
2283 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2284 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>;
2286 def : Pat<(and GR32:$src, (add (shl 1, GR8:$lz), -1)),
2287 (BZHI32rr GR32:$src,
2288 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2290 def : Pat<(and (loadi32 addr:$src), (add (shl 1, GR8:$lz), -1)),
2291 (BZHI32rm addr:$src,
2292 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2294 def : Pat<(and GR64:$src, (add (shl 1, GR8:$lz), -1)),
2295 (BZHI64rr GR64:$src,
2296 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2298 def : Pat<(and (loadi64 addr:$src), (add (shl 1, GR8:$lz), -1)),
2299 (BZHI64rm addr:$src,
2300 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2303 let Predicates = [HasBMI] in {
2304 def : Pat<(X86bextr GR32:$src1, GR32:$src2),
2305 (BEXTR32rr GR32:$src1, GR32:$src2)>;
2306 def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2),
2307 (BEXTR32rm addr:$src1, GR32:$src2)>;
2308 def : Pat<(X86bextr GR64:$src1, GR64:$src2),
2309 (BEXTR64rr GR64:$src1, GR64:$src2)>;
2310 def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2),
2311 (BEXTR64rm addr:$src1, GR64:$src2)>;
2314 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
2315 X86MemOperand x86memop, Intrinsic Int,
2317 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2318 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2319 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
2321 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2322 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2323 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
2326 let Predicates = [HasBMI2] in {
2327 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
2328 int_x86_bmi_pdep_32, loadi32>, T8XD;
2329 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
2330 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
2331 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
2332 int_x86_bmi_pext_32, loadi32>, T8XS;
2333 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
2334 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
2337 //===----------------------------------------------------------------------===//
2340 let Predicates = [HasTBM], Defs = [EFLAGS] in {
2342 multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr,
2343 X86MemOperand x86memop, PatFrag ld_frag,
2344 Intrinsic Int, Operand immtype,
2345 SDPatternOperator immoperator> {
2346 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
2347 !strconcat(OpcodeStr,
2348 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2349 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>,
2351 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst),
2352 (ins x86memop:$src1, immtype:$cntl),
2353 !strconcat(OpcodeStr,
2354 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2355 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>,
2359 defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32,
2360 int_x86_tbm_bextri_u32, i32imm, imm>;
2361 let ImmT = Imm32S in
2362 defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64,
2363 int_x86_tbm_bextri_u64, i64i32imm,
2364 i64immSExt32>, VEX_W;
2366 multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem,
2367 RegisterClass RC, string OpcodeStr,
2368 X86MemOperand x86memop, PatFrag ld_frag> {
2369 let hasSideEffects = 0 in {
2370 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src),
2371 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2374 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src),
2375 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2380 multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr,
2381 Format FormReg, Format FormMem> {
2382 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem,
2384 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem,
2388 defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
2389 defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>;
2390 defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>;
2391 defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>;
2392 defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>;
2393 defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>;
2394 defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>;
2395 defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>;
2396 defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>;
2399 //===----------------------------------------------------------------------===//
2400 // Pattern fragments to auto generate TBM instructions.
2401 //===----------------------------------------------------------------------===//
2403 let Predicates = [HasTBM] in {
2404 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)),
2405 (BEXTRI32ri GR32:$src1, imm:$src2)>;
2406 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)),
2407 (BEXTRI32mi addr:$src1, imm:$src2)>;
2408 def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2),
2409 (BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>;
2410 def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2),
2411 (BEXTRI64mi addr:$src1, i64immSExt32:$src2)>;
2413 // FIXME: patterns for the load versions are not implemented
2414 def : Pat<(and GR32:$src, (add GR32:$src, 1)),
2415 (BLCFILL32rr GR32:$src)>;
2416 def : Pat<(and GR64:$src, (add GR64:$src, 1)),
2417 (BLCFILL64rr GR64:$src)>;
2419 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
2420 (BLCI32rr GR32:$src)>;
2421 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
2422 (BLCI64rr GR64:$src)>;
2424 // Extra patterns because opt can optimize the above patterns to this.
2425 def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
2426 (BLCI32rr GR32:$src)>;
2427 def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
2428 (BLCI64rr GR64:$src)>;
2430 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
2431 (BLCIC32rr GR32:$src)>;
2432 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),
2433 (BLCIC64rr GR64:$src)>;
2435 def : Pat<(xor GR32:$src, (add GR32:$src, 1)),
2436 (BLCMSK32rr GR32:$src)>;
2437 def : Pat<(xor GR64:$src, (add GR64:$src, 1)),
2438 (BLCMSK64rr GR64:$src)>;
2440 def : Pat<(or GR32:$src, (add GR32:$src, 1)),
2441 (BLCS32rr GR32:$src)>;
2442 def : Pat<(or GR64:$src, (add GR64:$src, 1)),
2443 (BLCS64rr GR64:$src)>;
2445 def : Pat<(or GR32:$src, (add GR32:$src, -1)),
2446 (BLSFILL32rr GR32:$src)>;
2447 def : Pat<(or GR64:$src, (add GR64:$src, -1)),
2448 (BLSFILL64rr GR64:$src)>;
2450 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
2451 (BLSIC32rr GR32:$src)>;
2452 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)),
2453 (BLSIC64rr GR64:$src)>;
2455 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)),
2456 (T1MSKC32rr GR32:$src)>;
2457 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)),
2458 (T1MSKC64rr GR64:$src)>;
2460 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)),
2461 (TZMSK32rr GR32:$src)>;
2462 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)),
2463 (TZMSK64rr GR64:$src)>;
2466 //===----------------------------------------------------------------------===//
2467 // Memory Instructions
2470 def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2471 "clflushopt\t$src", []>, PD;
2472 def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", []>, PD;
2473 def PCOMMIT : I<0xAE, MRM_F8, (outs), (ins), "pcommit", []>, PD;
2476 //===----------------------------------------------------------------------===//
2478 //===----------------------------------------------------------------------===//
2480 include "X86InstrArithmetic.td"
2481 include "X86InstrCMovSetCC.td"
2482 include "X86InstrExtension.td"
2483 include "X86InstrControl.td"
2484 include "X86InstrShiftRotate.td"
2486 // X87 Floating Point Stack.
2487 include "X86InstrFPStack.td"
2489 // SIMD support (SSE, MMX and AVX)
2490 include "X86InstrFragmentsSIMD.td"
2492 // FMA - Fused Multiply-Add support (requires FMA)
2493 include "X86InstrFMA.td"
2496 include "X86InstrXOP.td"
2498 // SSE, MMX and 3DNow! vector support.
2499 include "X86InstrSSE.td"
2500 include "X86InstrAVX512.td"
2501 include "X86InstrMMX.td"
2502 include "X86Instr3DNow.td"
2505 include "X86InstrMPX.td"
2507 include "X86InstrVMX.td"
2508 include "X86InstrSVM.td"
2510 include "X86InstrTSX.td"
2511 include "X86InstrSGX.td"
2513 // System instructions.
2514 include "X86InstrSystem.td"
2516 // Compiler Pseudo Instructions and Pat Patterns
2517 include "X86InstrCompiler.td"
2519 //===----------------------------------------------------------------------===//
2520 // Assembler Mnemonic Aliases
2521 //===----------------------------------------------------------------------===//
2523 def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>;
2524 def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>;
2525 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;
2527 def : MnemonicAlias<"cbw", "cbtw", "att">;
2528 def : MnemonicAlias<"cwde", "cwtl", "att">;
2529 def : MnemonicAlias<"cwd", "cwtd", "att">;
2530 def : MnemonicAlias<"cdq", "cltd", "att">;
2531 def : MnemonicAlias<"cdqe", "cltq", "att">;
2532 def : MnemonicAlias<"cqo", "cqto", "att">;
2534 // In 64-bit mode lret maps to lretl; it is not ambiguous with lretq.
2535 def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>;
2536 def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>;
2538 def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>;
2539 def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>;
2541 def : MnemonicAlias<"loopz", "loope", "att">;
2542 def : MnemonicAlias<"loopnz", "loopne", "att">;
2544 def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>;
2545 def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>;
2546 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>;
2547 def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>;
2548 def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>;
2549 def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>;
2550 def : MnemonicAlias<"popfd", "popfl", "att">;
2552 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
2553 // all modes. However: "push (addr)" and "push $42" should default to
2554 // pushl/pushq depending on the current mode. Similar for "pop %bx"
2555 def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>;
2556 def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>;
2557 def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>;
2558 def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>;
2559 def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>;
2560 def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
2561 def : MnemonicAlias<"pushfd", "pushfl", "att">;
2563 def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>;
2564 def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>;
2565 def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>;
2566 def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>;
2567 def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>;
2568 def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>;
2570 def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>;
2571 def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>;
2572 def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>;
2573 def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>;
2575 def : MnemonicAlias<"repe", "rep">;
2576 def : MnemonicAlias<"repz", "rep">;
2577 def : MnemonicAlias<"repnz", "repne">;
2579 def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>;
2580 def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>;
2581 def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>;
2583 def : MnemonicAlias<"sal", "shl", "intel">;
2584 def : MnemonicAlias<"salb", "shlb", "att">;
2585 def : MnemonicAlias<"salw", "shlw", "att">;
2586 def : MnemonicAlias<"sall", "shll", "att">;
2587 def : MnemonicAlias<"salq", "shlq", "att">;
2589 def : MnemonicAlias<"smovb", "movsb", "att">;
2590 def : MnemonicAlias<"smovw", "movsw", "att">;
2591 def : MnemonicAlias<"smovl", "movsl", "att">;
2592 def : MnemonicAlias<"smovq", "movsq", "att">;
2594 def : MnemonicAlias<"ud2a", "ud2", "att">;
2595 def : MnemonicAlias<"verrw", "verr", "att">;
2597 // System instruction aliases.
2598 def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>;
2599 def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>;
2600 def : MnemonicAlias<"sysret", "sysretl", "att">;
2601 def : MnemonicAlias<"sysexit", "sysexitl", "att">;
2603 def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>;
2604 def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>;
2605 def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>;
2606 def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>;
2607 def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>;
2608 def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>;
2609 def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>;
2610 def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>;
2611 def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>;
2612 def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>;
2613 def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>;
2614 def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>;
2617 // Floating point stack aliases.
2618 def : MnemonicAlias<"fcmovz", "fcmove", "att">;
2619 def : MnemonicAlias<"fcmova", "fcmovnbe", "att">;
2620 def : MnemonicAlias<"fcmovnae", "fcmovb", "att">;
2621 def : MnemonicAlias<"fcmovna", "fcmovbe", "att">;
2622 def : MnemonicAlias<"fcmovae", "fcmovnb", "att">;
2623 def : MnemonicAlias<"fcomip", "fcompi", "att">;
2624 def : MnemonicAlias<"fildq", "fildll", "att">;
2625 def : MnemonicAlias<"fistpq", "fistpll", "att">;
2626 def : MnemonicAlias<"fisttpq", "fisttpll", "att">;
2627 def : MnemonicAlias<"fldcww", "fldcw", "att">;
2628 def : MnemonicAlias<"fnstcww", "fnstcw", "att">;
2629 def : MnemonicAlias<"fnstsww", "fnstsw", "att">;
2630 def : MnemonicAlias<"fucomip", "fucompi", "att">;
2631 def : MnemonicAlias<"fwait", "wait">;
2633 def : MnemonicAlias<"fxsaveq", "fxsave64", "att">;
2634 def : MnemonicAlias<"fxrstorq", "fxrstor64", "att">;
2635 def : MnemonicAlias<"xsaveq", "xsave64", "att">;
2636 def : MnemonicAlias<"xrstorq", "xrstor64", "att">;
2637 def : MnemonicAlias<"xsaveoptq", "xsaveopt64", "att">;
2640 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond,
2642 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
2643 !strconcat(Prefix, NewCond, Suffix), VariantName>;
2645 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
2646 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
2647 /// example "setz" -> "sete".
2648 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix,
2650 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb
2651 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete
2652 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe
2653 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae
2654 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae
2655 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle
2656 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge
2657 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne
2658 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp
2659 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp
2661 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb
2662 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta
2663 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl
2664 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg
2667 // Aliases for set<CC>
2668 defm : IntegerCondCodeMnemonicAlias<"set", "">;
2669 // Aliases for j<CC>
2670 defm : IntegerCondCodeMnemonicAlias<"j", "">;
2671 // Aliases for cmov<CC>{w,l,q}
2672 defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">;
2673 defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">;
2674 defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">;
2675 // No size suffix for intel-style asm.
2676 defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">;
2679 //===----------------------------------------------------------------------===//
2680 // Assembler Instruction Aliases
2681 //===----------------------------------------------------------------------===//
2683 // aad/aam default to base 10 if no operand is specified.
2684 def : InstAlias<"aad", (AAD8i8 10)>;
2685 def : InstAlias<"aam", (AAM8i8 10)>;
2687 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
2688 // Likewise for btc/btr/bts.
2689 def : InstAlias<"bt {$imm, $mem|$mem, $imm}",
2690 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2691 def : InstAlias<"btc {$imm, $mem|$mem, $imm}",
2692 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2693 def : InstAlias<"btr {$imm, $mem|$mem, $imm}",
2694 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2695 def : InstAlias<"bts {$imm, $mem|$mem, $imm}",
2696 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2699 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>;
2700 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>;
2701 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>;
2702 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;
2704 // lods aliases. Accept the destination being omitted because it's implicit
2705 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2706 // in the destination.
2707 def : InstAlias<"lodsb $src", (LODSB srcidx8:$src), 0>;
2708 def : InstAlias<"lodsw $src", (LODSW srcidx16:$src), 0>;
2709 def : InstAlias<"lods{l|d} $src", (LODSL srcidx32:$src), 0>;
2710 def : InstAlias<"lodsq $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2711 def : InstAlias<"lods {$src, %al|al, $src}", (LODSB srcidx8:$src), 0>;
2712 def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>;
2713 def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>;
2714 def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2716 // stos aliases. Accept the source being omitted because it's implicit in
2717 // the mnemonic, or the mnemonic suffix being omitted because it's implicit
2719 def : InstAlias<"stosb $dst", (STOSB dstidx8:$dst), 0>;
2720 def : InstAlias<"stosw $dst", (STOSW dstidx16:$dst), 0>;
2721 def : InstAlias<"stos{l|d} $dst", (STOSL dstidx32:$dst), 0>;
2722 def : InstAlias<"stosq $dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2723 def : InstAlias<"stos {%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>;
2724 def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>;
2725 def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>;
2726 def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2728 // scas aliases. Accept the destination being omitted because it's implicit
2729 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2730 // in the destination.
2731 def : InstAlias<"scasb $dst", (SCASB dstidx8:$dst), 0>;
2732 def : InstAlias<"scasw $dst", (SCASW dstidx16:$dst), 0>;
2733 def : InstAlias<"scas{l|d} $dst", (SCASL dstidx32:$dst), 0>;
2734 def : InstAlias<"scasq $dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2735 def : InstAlias<"scas {$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>;
2736 def : InstAlias<"scas {$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>;
2737 def : InstAlias<"scas {$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>;
2738 def : InstAlias<"scas {$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2740 // div and idiv aliases for explicit A register.
2741 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
2742 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
2743 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>;
2744 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>;
2745 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>;
2746 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>;
2747 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>;
2748 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>;
2749 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>;
2750 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>;
2751 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>;
2752 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>;
2753 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>;
2754 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>;
2755 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;
2756 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;
2760 // Various unary fpstack operations default to operating on on ST1.
2761 // For example, "fxch" -> "fxch %st(1)"
2762 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
2763 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
2764 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
2765 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
2766 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
2767 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
2768 def : InstAlias<"fxch", (XCH_F ST1), 0>;
2769 def : InstAlias<"fcom", (COM_FST0r ST1), 0>;
2770 def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>;
2771 def : InstAlias<"fcomi", (COM_FIr ST1), 0>;
2772 def : InstAlias<"fcompi", (COM_FIPr ST1), 0>;
2773 def : InstAlias<"fucom", (UCOM_Fr ST1), 0>;
2774 def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>;
2775 def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>;
2776 def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>;
2778 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
2779 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
2780 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
2782 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
2783 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"),
2784 (Inst RST:$op), EmitAlias>;
2785 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"),
2786 (Inst ST0), EmitAlias>;
2789 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
2790 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
2791 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
2792 defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>;
2793 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
2794 defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>;
2795 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
2796 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
2797 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
2798 defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>;
2799 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
2800 defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>;
2801 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
2802 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
2803 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
2804 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
2807 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
2808 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
2809 // solely because gas supports it.
2810 def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>;
2811 def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>;
2812 def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>;
2813 def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>;
2814 def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>;
2815 def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>;
2817 // We accept "fnstsw %eax" even though it only writes %ax.
2818 def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>;
2819 def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>;
2820 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
2822 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
2823 // this is compatible with what GAS does.
2824 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2825 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2826 def : InstAlias<"lcall {*}$dst", (FARCALL32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2827 def : InstAlias<"ljmp {*}$dst", (FARJMP32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2828 def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2829 def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2830 def : InstAlias<"lcall {*}$dst", (FARCALL16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2831 def : InstAlias<"ljmp {*}$dst", (FARJMP16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2833 def : InstAlias<"call {*}$dst", (CALL64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
2834 def : InstAlias<"jmp {*}$dst", (JMP64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
2835 def : InstAlias<"call {*}$dst", (CALL32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
2836 def : InstAlias<"jmp {*}$dst", (JMP32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
2837 def : InstAlias<"call {*}$dst", (CALL16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2838 def : InstAlias<"jmp {*}$dst", (JMP16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2841 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
2842 def : InstAlias<"imul{w} {$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>;
2843 def : InstAlias<"imul{w} {$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>;
2844 def : InstAlias<"imul{l} {$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>;
2845 def : InstAlias<"imul{l} {$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>;
2846 def : InstAlias<"imul{q} {$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>;
2847 def : InstAlias<"imul{q} {$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>;
2849 // inb %dx -> inb %al, %dx
2850 def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;
2851 def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;
2852 def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>;
2853 def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>;
2854 def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>;
2855 def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>;
2858 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
2859 def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2860 def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2861 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2862 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2863 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
2864 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
2865 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2866 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2868 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
2869 // the move. All segment/mem forms are equivalent, this has the shortest
2871 def : InstAlias<"mov {$mem, $seg|$seg, $mem}", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem), 0>;
2872 def : InstAlias<"mov {$seg, $mem|$mem, $seg}", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg), 0>;
2874 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
2875 def : InstAlias<"movq {$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>;
2877 // Match 'movq GR64, MMX' as an alias for movd.
2878 def : InstAlias<"movq {$src, $dst|$dst, $src}",
2879 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
2880 def : InstAlias<"movq {$src, $dst|$dst, $src}",
2881 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
2884 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
2885 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
2886 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
2887 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
2888 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
2889 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
2890 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
2893 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
2894 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
2895 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
2896 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
2897 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
2898 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
2899 // Note: No GR32->GR64 movzx form.
2901 // outb %dx -> outb %al, %dx
2902 def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>;
2903 def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>;
2904 def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>;
2905 def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>;
2906 def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>;
2907 def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>;
2909 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
2910 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
2911 // errors, since its encoding is the most compact.
2912 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>;
2914 // shld/shrd op,op -> shld op, op, CL
2915 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;
2916 def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>;
2917 def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>;
2918 def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>;
2919 def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>;
2920 def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>;
2922 def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>;
2923 def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>;
2924 def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>;
2925 def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>;
2926 def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>;
2927 def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>;
2929 /* FIXME: This is disabled because the asm matcher is currently incapable of
2930 * matching a fixed immediate like $1.
2931 // "shl X, $1" is an alias for "shl X".
2932 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
2933 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2934 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
2935 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2936 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
2937 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2938 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
2939 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2940 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
2941 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2942 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
2943 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2944 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
2945 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2946 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
2947 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2948 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2951 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2952 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
2953 defm : ShiftRotateByOneAlias<"rol", "ROL">;
2954 defm : ShiftRotateByOneAlias<"ror", "ROR">;
2957 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
2958 def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}",
2959 (TEST8rm GR8 :$val, i8mem :$mem), 0>;
2960 def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}",
2961 (TEST16rm GR16:$val, i16mem:$mem), 0>;
2962 def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}",
2963 (TEST32rm GR32:$val, i32mem:$mem), 0>;
2964 def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}",
2965 (TEST64rm GR64:$val, i64mem:$mem), 0>;
2967 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
2968 def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}",
2969 (XCHG8rm GR8 :$val, i8mem :$mem), 0>;
2970 def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}",
2971 (XCHG16rm GR16:$val, i16mem:$mem), 0>;
2972 def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}",
2973 (XCHG32rm GR32:$val, i32mem:$mem), 0>;
2974 def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}",
2975 (XCHG64rm GR64:$val, i64mem:$mem), 0>;
2977 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
2978 def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>;
2979 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
2980 (XCHG32ar GR32:$src), 0>, Requires<[Not64BitMode]>;
2981 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
2982 (XCHG32ar64 GR32_NOAX:$src), 0>, Requires<[In64BitMode]>;
2983 def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>;