1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 def SDTX86BrCond : SDTypeProfile<0, 3,
31 [SDTCisVT<0, OtherVT>,
32 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
34 def SDTX86SetCC : SDTypeProfile<1, 2,
36 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
38 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
40 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
42 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
43 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
44 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
46 def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
47 def SDT_X86CallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
50 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
52 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
54 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
56 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
58 def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
60 def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
62 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
64 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
66 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
67 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
68 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
69 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
71 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
73 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
74 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
76 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
78 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
79 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
81 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
82 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
84 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
85 [SDNPHasChain, SDNPMayStore,
86 SDNPMayLoad, SDNPMemOperand]>;
87 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
88 [SDNPHasChain, SDNPMayStore,
89 SDNPMayLoad, SDNPMemOperand]>;
90 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
91 [SDNPHasChain, SDNPMayStore,
92 SDNPMayLoad, SDNPMemOperand]>;
93 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
94 [SDNPHasChain, SDNPMayStore,
95 SDNPMayLoad, SDNPMemOperand]>;
96 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
97 [SDNPHasChain, SDNPMayStore,
98 SDNPMayLoad, SDNPMemOperand]>;
99 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
100 [SDNPHasChain, SDNPMayStore,
101 SDNPMayLoad, SDNPMemOperand]>;
102 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
103 [SDNPHasChain, SDNPMayStore,
104 SDNPMayLoad, SDNPMemOperand]>;
105 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
106 [SDNPHasChain, SDNPOptInFlag]>;
108 def X86callseq_start :
109 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
110 [SDNPHasChain, SDNPOutFlag]>;
112 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
113 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
115 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
116 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
118 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
119 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
121 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
122 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
123 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
124 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
127 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
128 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
130 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
131 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
133 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
134 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
135 def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
137 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
140 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
141 [SDNPHasChain, SDNPOptInFlag]>;
143 //===----------------------------------------------------------------------===//
144 // X86 Operand Definitions.
147 // *mem - Operand definitions for the funky X86 addressing mode operands.
149 class X86MemOperand<string printMethod> : Operand<iPTR> {
150 let PrintMethod = printMethod;
151 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
154 def i8mem : X86MemOperand<"printi8mem">;
155 def i16mem : X86MemOperand<"printi16mem">;
156 def i32mem : X86MemOperand<"printi32mem">;
157 def i64mem : X86MemOperand<"printi64mem">;
158 def i128mem : X86MemOperand<"printi128mem">;
159 def f32mem : X86MemOperand<"printf32mem">;
160 def f64mem : X86MemOperand<"printf64mem">;
161 def f80mem : X86MemOperand<"printf80mem">;
162 def f128mem : X86MemOperand<"printf128mem">;
164 def lea32mem : Operand<i32> {
165 let PrintMethod = "printi32mem";
166 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
169 def SSECC : Operand<i8> {
170 let PrintMethod = "printSSECC";
173 def piclabel: Operand<i32> {
174 let PrintMethod = "printPICLabel";
177 // A couple of more descriptive operand definitions.
178 // 16-bits but only 8 bits are significant.
179 def i16i8imm : Operand<i16>;
180 // 32-bits but only 8 bits are significant.
181 def i32i8imm : Operand<i32>;
183 // Branch targets have OtherVT type.
184 def brtarget : Operand<OtherVT>;
186 //===----------------------------------------------------------------------===//
187 // X86 Complex Pattern Definitions.
190 // Define X86 specific addressing mode.
191 def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
192 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
193 [add, mul, shl, or, frameindex], []>;
195 //===----------------------------------------------------------------------===//
196 // X86 Instruction Predicate Definitions.
197 def HasMMX : Predicate<"Subtarget->hasMMX()">;
198 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
199 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
200 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
201 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
202 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
203 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
204 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
205 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
206 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
207 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
208 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
209 def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
210 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
211 def OptForSpeed : Predicate<"!OptForSize">;
213 //===----------------------------------------------------------------------===//
214 // X86 Instruction Format Definitions.
217 include "X86InstrFormats.td"
219 //===----------------------------------------------------------------------===//
220 // Pattern fragments...
223 // X86 specific condition code. These correspond to CondCode in
224 // X86InstrInfo.h. They must be kept in synch.
225 def X86_COND_A : PatLeaf<(i8 0)>;
226 def X86_COND_AE : PatLeaf<(i8 1)>;
227 def X86_COND_B : PatLeaf<(i8 2)>;
228 def X86_COND_BE : PatLeaf<(i8 3)>;
229 def X86_COND_E : PatLeaf<(i8 4)>;
230 def X86_COND_G : PatLeaf<(i8 5)>;
231 def X86_COND_GE : PatLeaf<(i8 6)>;
232 def X86_COND_L : PatLeaf<(i8 7)>;
233 def X86_COND_LE : PatLeaf<(i8 8)>;
234 def X86_COND_NE : PatLeaf<(i8 9)>;
235 def X86_COND_NO : PatLeaf<(i8 10)>;
236 def X86_COND_NP : PatLeaf<(i8 11)>;
237 def X86_COND_NS : PatLeaf<(i8 12)>;
238 def X86_COND_O : PatLeaf<(i8 13)>;
239 def X86_COND_P : PatLeaf<(i8 14)>;
240 def X86_COND_S : PatLeaf<(i8 15)>;
242 def i16immSExt8 : PatLeaf<(i16 imm), [{
243 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
244 // sign extended field.
245 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
248 def i32immSExt8 : PatLeaf<(i32 imm), [{
249 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
250 // sign extended field.
251 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
254 // Helper fragments for loads.
255 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
256 // known to be 32-bit aligned or better. Ditto for i8 to i16.
257 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
258 LoadSDNode *LD = cast<LoadSDNode>(N);
259 ISD::LoadExtType ExtType = LD->getExtensionType();
260 if (ExtType == ISD::NON_EXTLOAD)
262 if (ExtType == ISD::EXTLOAD)
263 return LD->getAlignment() >= 2 && !LD->isVolatile();
267 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
268 LoadSDNode *LD = cast<LoadSDNode>(N);
269 ISD::LoadExtType ExtType = LD->getExtensionType();
270 if (ExtType == ISD::EXTLOAD)
271 return LD->getAlignment() >= 2 && !LD->isVolatile();
275 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
276 LoadSDNode *LD = cast<LoadSDNode>(N);
277 ISD::LoadExtType ExtType = LD->getExtensionType();
278 if (ExtType == ISD::NON_EXTLOAD)
280 if (ExtType == ISD::EXTLOAD)
281 return LD->getAlignment() >= 4 && !LD->isVolatile();
285 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
286 LoadSDNode *LD = cast<LoadSDNode>(N);
287 if (LD->isVolatile())
289 ISD::LoadExtType ExtType = LD->getExtensionType();
290 if (ExtType == ISD::NON_EXTLOAD)
292 if (ExtType == ISD::EXTLOAD)
293 return LD->getAlignment() >= 4;
297 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
298 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
300 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
301 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
302 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
304 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
305 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
306 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
308 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
309 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
310 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
311 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
312 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
313 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
315 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
316 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
317 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
318 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
319 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
320 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
323 // An 'and' node with a single use.
324 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
325 return N->hasOneUse();
328 // 'shld' and 'shrd' instruction patterns. Note that even though these have
329 // the srl and shl in their patterns, the C++ code must still check for them,
330 // because predicates are tested before children nodes are explored.
332 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
333 (or (srl node:$src1, node:$amt1),
334 (shl node:$src2, node:$amt2)), [{
335 assert(N->getOpcode() == ISD::OR);
336 return N->getOperand(0).getOpcode() == ISD::SRL &&
337 N->getOperand(1).getOpcode() == ISD::SHL &&
338 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
339 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
340 N->getOperand(0).getConstantOperandVal(1) ==
341 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
344 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
345 (or (shl node:$src1, node:$amt1),
346 (srl node:$src2, node:$amt2)), [{
347 assert(N->getOpcode() == ISD::OR);
348 return N->getOperand(0).getOpcode() == ISD::SHL &&
349 N->getOperand(1).getOpcode() == ISD::SRL &&
350 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
351 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
352 N->getOperand(0).getConstantOperandVal(1) ==
353 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
356 //===----------------------------------------------------------------------===//
357 // Instruction list...
360 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
361 // a stack adjustment and the codegen must know that they may modify the stack
362 // pointer before prolog-epilog rewriting occurs.
363 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
364 // sub / add which can clobber EFLAGS.
365 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
366 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
368 [(X86callseq_start timm:$amt)]>,
369 Requires<[In32BitMode]>;
370 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
372 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
373 Requires<[In32BitMode]>;
377 let neverHasSideEffects = 1 in
378 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
381 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
382 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
383 "call\t$label\n\tpop{l}\t$reg", []>;
385 //===----------------------------------------------------------------------===//
386 // Control Flow Instructions...
389 // Return instructions.
390 let isTerminator = 1, isReturn = 1, isBarrier = 1,
391 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
392 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
395 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
397 [(X86retflag imm:$amt)]>;
400 // All branches are RawFrm, Void, Branch, and Terminators
401 let isBranch = 1, isTerminator = 1 in
402 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
403 I<opcode, RawFrm, (outs), ins, asm, pattern>;
405 let isBranch = 1, isBarrier = 1 in
406 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
409 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
410 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
411 [(brind GR32:$dst)]>;
412 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
413 [(brind (loadi32 addr:$dst))]>;
416 // Conditional branches
417 let Uses = [EFLAGS] in {
418 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
419 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
420 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
421 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
422 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
423 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
424 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
425 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
426 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
427 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
428 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
429 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
431 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
432 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
433 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
434 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
435 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
436 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
437 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
438 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
440 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
441 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
442 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
443 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
444 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
445 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
446 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
447 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
448 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
449 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
450 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
451 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
454 //===----------------------------------------------------------------------===//
455 // Call Instructions...
458 // All calls clobber the non-callee saved registers. ESP is marked as
459 // a use to prevent stack-pointer assignments that appear immediately
460 // before calls from potentially appearing dead. Uses for argument
461 // registers are added manually.
462 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
463 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
464 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
465 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
467 def CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:$dst,variable_ops),
468 "call\t${dst:call}", []>;
469 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
470 "call\t{*}$dst", [(X86call GR32:$dst)]>;
471 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
472 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
477 def TAILCALL : I<0, Pseudo, (outs), (ins),
481 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
482 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops),
483 "#TC_RETURN $dst $offset",
486 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
487 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops),
488 "#TC_RETURN $dst $offset",
491 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
493 def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAILCALL",
495 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
496 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
498 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
499 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
500 "jmp\t{*}$dst # TAILCALL", []>;
502 //===----------------------------------------------------------------------===//
503 // Miscellaneous Instructions...
505 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
506 def LEAVE : I<0xC9, RawFrm,
507 (outs), (ins), "leave", []>;
509 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
511 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
514 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
517 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
518 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
519 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
520 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
522 let isTwoAddress = 1 in // GR32 = bswap GR32
523 def BSWAP32r : I<0xC8, AddRegFrm,
524 (outs GR32:$dst), (ins GR32:$src),
526 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
529 // Bit scan instructions.
530 let Defs = [EFLAGS] in {
531 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
532 "bsf{w}\t{$src, $dst|$dst, $src}",
533 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
534 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
535 "bsf{w}\t{$src, $dst|$dst, $src}",
536 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
537 (implicit EFLAGS)]>, TB;
538 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
539 "bsf{l}\t{$src, $dst|$dst, $src}",
540 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
541 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
542 "bsf{l}\t{$src, $dst|$dst, $src}",
543 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
544 (implicit EFLAGS)]>, TB;
546 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
547 "bsr{w}\t{$src, $dst|$dst, $src}",
548 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
549 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
550 "bsr{w}\t{$src, $dst|$dst, $src}",
551 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
552 (implicit EFLAGS)]>, TB;
553 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
554 "bsr{l}\t{$src, $dst|$dst, $src}",
555 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
556 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
557 "bsr{l}\t{$src, $dst|$dst, $src}",
558 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
559 (implicit EFLAGS)]>, TB;
562 let neverHasSideEffects = 1 in
563 def LEA16r : I<0x8D, MRMSrcMem,
564 (outs GR16:$dst), (ins i32mem:$src),
565 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
566 let isReMaterializable = 1 in
567 def LEA32r : I<0x8D, MRMSrcMem,
568 (outs GR32:$dst), (ins lea32mem:$src),
569 "lea{l}\t{$src|$dst}, {$dst|$src}",
570 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
572 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
573 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
574 [(X86rep_movs i8)]>, REP;
575 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
576 [(X86rep_movs i16)]>, REP, OpSize;
577 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
578 [(X86rep_movs i32)]>, REP;
581 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
582 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
583 [(X86rep_stos i8)]>, REP;
584 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
585 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
586 [(X86rep_stos i16)]>, REP, OpSize;
587 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
588 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
589 [(X86rep_stos i32)]>, REP;
591 let Defs = [RAX, RDX] in
592 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
595 let isBarrier = 1, hasCtrlDep = 1 in {
596 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
599 //===----------------------------------------------------------------------===//
600 // Input/Output Instructions...
602 let Defs = [AL], Uses = [DX] in
603 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
604 "in{b}\t{%dx, %al|%AL, %DX}", []>;
605 let Defs = [AX], Uses = [DX] in
606 def IN16rr : I<0xED, RawFrm, (outs), (ins),
607 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
608 let Defs = [EAX], Uses = [DX] in
609 def IN32rr : I<0xED, RawFrm, (outs), (ins),
610 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
613 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
614 "in{b}\t{$port, %al|%AL, $port}", []>;
616 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
617 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
619 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
620 "in{l}\t{$port, %eax|%EAX, $port}", []>;
622 let Uses = [DX, AL] in
623 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
624 "out{b}\t{%al, %dx|%DX, %AL}", []>;
625 let Uses = [DX, AX] in
626 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
627 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
628 let Uses = [DX, EAX] in
629 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
630 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
633 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
634 "out{b}\t{%al, $port|$port, %AL}", []>;
636 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
637 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
639 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
640 "out{l}\t{%eax, $port|$port, %EAX}", []>;
642 //===----------------------------------------------------------------------===//
643 // Move Instructions...
645 let neverHasSideEffects = 1 in {
646 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
647 "mov{b}\t{$src, $dst|$dst, $src}", []>;
648 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
649 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
650 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
651 "mov{l}\t{$src, $dst|$dst, $src}", []>;
653 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
654 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
655 "mov{b}\t{$src, $dst|$dst, $src}",
656 [(set GR8:$dst, imm:$src)]>;
657 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
658 "mov{w}\t{$src, $dst|$dst, $src}",
659 [(set GR16:$dst, imm:$src)]>, OpSize;
660 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
661 "mov{l}\t{$src, $dst|$dst, $src}",
662 [(set GR32:$dst, imm:$src)]>;
664 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
665 "mov{b}\t{$src, $dst|$dst, $src}",
666 [(store (i8 imm:$src), addr:$dst)]>;
667 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
668 "mov{w}\t{$src, $dst|$dst, $src}",
669 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
670 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
671 "mov{l}\t{$src, $dst|$dst, $src}",
672 [(store (i32 imm:$src), addr:$dst)]>;
674 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
675 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
676 "mov{b}\t{$src, $dst|$dst, $src}",
677 [(set GR8:$dst, (load addr:$src))]>;
678 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
679 "mov{w}\t{$src, $dst|$dst, $src}",
680 [(set GR16:$dst, (load addr:$src))]>, OpSize;
681 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
682 "mov{l}\t{$src, $dst|$dst, $src}",
683 [(set GR32:$dst, (load addr:$src))]>;
686 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
687 "mov{b}\t{$src, $dst|$dst, $src}",
688 [(store GR8:$src, addr:$dst)]>;
689 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
690 "mov{w}\t{$src, $dst|$dst, $src}",
691 [(store GR16:$src, addr:$dst)]>, OpSize;
692 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
693 "mov{l}\t{$src, $dst|$dst, $src}",
694 [(store GR32:$src, addr:$dst)]>;
696 //===----------------------------------------------------------------------===//
697 // Fixed-Register Multiplication and Division Instructions...
700 // Extra precision multiplication
701 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
702 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
703 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
704 // This probably ought to be moved to a def : Pat<> if the
705 // syntax can be accepted.
706 [(set AL, (mul AL, GR8:$src))]>; // AL,AH = AL*GR8
707 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
708 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>,
709 OpSize; // AX,DX = AX*GR16
710 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
711 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l}\t$src", []>;
712 // EAX,EDX = EAX*GR32
713 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
714 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
716 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
717 // This probably ought to be moved to a def : Pat<> if the
718 // syntax can be accepted.
719 [(set AL, (mul AL, (loadi8 addr:$src)))]>; // AL,AH = AL*[mem8]
720 let mayLoad = 1, neverHasSideEffects = 1 in {
721 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
722 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
723 "mul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
724 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
725 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
726 "mul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
729 let neverHasSideEffects = 1 in {
730 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
731 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
733 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
734 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
735 OpSize; // AX,DX = AX*GR16
736 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
737 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
738 // EAX,EDX = EAX*GR32
740 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
741 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
742 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
743 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
744 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
745 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
746 let Defs = [EAX,EDX], Uses = [EAX] in
747 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
748 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
751 // unsigned division/remainder
752 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
753 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
755 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
756 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
757 "div{w}\t$src", []>, OpSize;
758 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
759 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
762 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
763 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
765 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
766 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
767 "div{w}\t$src", []>, OpSize;
768 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
769 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
773 // Signed division/remainder.
774 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
775 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
776 "idiv{b}\t$src", []>;
777 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
778 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
779 "idiv{w}\t$src", []>, OpSize;
780 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
781 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
782 "idiv{l}\t$src", []>;
783 let mayLoad = 1, mayLoad = 1 in {
784 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
785 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
786 "idiv{b}\t$src", []>;
787 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
788 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
789 "idiv{w}\t$src", []>, OpSize;
790 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
791 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
792 "idiv{l}\t$src", []>;
794 } // neverHasSideEffects
796 //===----------------------------------------------------------------------===//
797 // Two address Instructions.
799 let isTwoAddress = 1 in {
802 let Uses = [EFLAGS] in {
803 let isCommutable = 1 in {
804 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
805 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
806 "cmovb\t{$src2, $dst|$dst, $src2}",
807 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
808 X86_COND_B, EFLAGS))]>,
810 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
811 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
812 "cmovb\t{$src2, $dst|$dst, $src2}",
813 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
814 X86_COND_B, EFLAGS))]>,
817 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
818 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
819 "cmovae\t{$src2, $dst|$dst, $src2}",
820 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
821 X86_COND_AE, EFLAGS))]>,
823 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
824 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
825 "cmovae\t{$src2, $dst|$dst, $src2}",
826 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
827 X86_COND_AE, EFLAGS))]>,
829 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
830 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
831 "cmove\t{$src2, $dst|$dst, $src2}",
832 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
833 X86_COND_E, EFLAGS))]>,
835 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
836 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
837 "cmove\t{$src2, $dst|$dst, $src2}",
838 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
839 X86_COND_E, EFLAGS))]>,
841 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
842 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
843 "cmovne\t{$src2, $dst|$dst, $src2}",
844 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
845 X86_COND_NE, EFLAGS))]>,
847 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
848 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
849 "cmovne\t{$src2, $dst|$dst, $src2}",
850 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
851 X86_COND_NE, EFLAGS))]>,
853 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
854 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
855 "cmovbe\t{$src2, $dst|$dst, $src2}",
856 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
857 X86_COND_BE, EFLAGS))]>,
859 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
860 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
861 "cmovbe\t{$src2, $dst|$dst, $src2}",
862 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
863 X86_COND_BE, EFLAGS))]>,
865 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
866 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
867 "cmova\t{$src2, $dst|$dst, $src2}",
868 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
869 X86_COND_A, EFLAGS))]>,
871 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
872 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
873 "cmova\t{$src2, $dst|$dst, $src2}",
874 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
875 X86_COND_A, EFLAGS))]>,
877 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
878 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
879 "cmovl\t{$src2, $dst|$dst, $src2}",
880 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
881 X86_COND_L, EFLAGS))]>,
883 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
884 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
885 "cmovl\t{$src2, $dst|$dst, $src2}",
886 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
887 X86_COND_L, EFLAGS))]>,
889 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
890 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
891 "cmovge\t{$src2, $dst|$dst, $src2}",
892 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
893 X86_COND_GE, EFLAGS))]>,
895 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
896 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
897 "cmovge\t{$src2, $dst|$dst, $src2}",
898 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
899 X86_COND_GE, EFLAGS))]>,
901 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
902 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
903 "cmovle\t{$src2, $dst|$dst, $src2}",
904 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
905 X86_COND_LE, EFLAGS))]>,
907 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
908 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
909 "cmovle\t{$src2, $dst|$dst, $src2}",
910 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
911 X86_COND_LE, EFLAGS))]>,
913 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
914 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
915 "cmovg\t{$src2, $dst|$dst, $src2}",
916 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
917 X86_COND_G, EFLAGS))]>,
919 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
920 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
921 "cmovg\t{$src2, $dst|$dst, $src2}",
922 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
923 X86_COND_G, EFLAGS))]>,
925 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
926 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
927 "cmovs\t{$src2, $dst|$dst, $src2}",
928 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
929 X86_COND_S, EFLAGS))]>,
931 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
932 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
933 "cmovs\t{$src2, $dst|$dst, $src2}",
934 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
935 X86_COND_S, EFLAGS))]>,
937 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
938 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
939 "cmovns\t{$src2, $dst|$dst, $src2}",
940 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
941 X86_COND_NS, EFLAGS))]>,
943 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
944 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
945 "cmovns\t{$src2, $dst|$dst, $src2}",
946 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
947 X86_COND_NS, EFLAGS))]>,
949 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
950 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
951 "cmovp\t{$src2, $dst|$dst, $src2}",
952 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
953 X86_COND_P, EFLAGS))]>,
955 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
956 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
957 "cmovp\t{$src2, $dst|$dst, $src2}",
958 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
959 X86_COND_P, EFLAGS))]>,
961 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
962 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
963 "cmovnp\t{$src2, $dst|$dst, $src2}",
964 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
965 X86_COND_NP, EFLAGS))]>,
967 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
968 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
969 "cmovnp\t{$src2, $dst|$dst, $src2}",
970 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
971 X86_COND_NP, EFLAGS))]>,
973 } // isCommutable = 1
975 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
976 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
977 "cmovnp\t{$src2, $dst|$dst, $src2}",
978 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
979 X86_COND_NP, EFLAGS))]>,
982 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
983 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
984 "cmovb\t{$src2, $dst|$dst, $src2}",
985 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
986 X86_COND_B, EFLAGS))]>,
988 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
989 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
990 "cmovb\t{$src2, $dst|$dst, $src2}",
991 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
992 X86_COND_B, EFLAGS))]>,
994 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
995 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
996 "cmovae\t{$src2, $dst|$dst, $src2}",
997 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
998 X86_COND_AE, EFLAGS))]>,
1000 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1001 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1002 "cmovae\t{$src2, $dst|$dst, $src2}",
1003 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1004 X86_COND_AE, EFLAGS))]>,
1006 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1007 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1008 "cmove\t{$src2, $dst|$dst, $src2}",
1009 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1010 X86_COND_E, EFLAGS))]>,
1012 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1013 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1014 "cmove\t{$src2, $dst|$dst, $src2}",
1015 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1016 X86_COND_E, EFLAGS))]>,
1018 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1019 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1020 "cmovne\t{$src2, $dst|$dst, $src2}",
1021 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1022 X86_COND_NE, EFLAGS))]>,
1024 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1025 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1026 "cmovne\t{$src2, $dst|$dst, $src2}",
1027 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1028 X86_COND_NE, EFLAGS))]>,
1030 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1031 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1032 "cmovbe\t{$src2, $dst|$dst, $src2}",
1033 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1034 X86_COND_BE, EFLAGS))]>,
1036 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1037 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1038 "cmovbe\t{$src2, $dst|$dst, $src2}",
1039 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1040 X86_COND_BE, EFLAGS))]>,
1042 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1043 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1044 "cmova\t{$src2, $dst|$dst, $src2}",
1045 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1046 X86_COND_A, EFLAGS))]>,
1048 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1049 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1050 "cmova\t{$src2, $dst|$dst, $src2}",
1051 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1052 X86_COND_A, EFLAGS))]>,
1054 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1055 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1056 "cmovl\t{$src2, $dst|$dst, $src2}",
1057 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1058 X86_COND_L, EFLAGS))]>,
1060 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1061 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1062 "cmovl\t{$src2, $dst|$dst, $src2}",
1063 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1064 X86_COND_L, EFLAGS))]>,
1066 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1067 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1068 "cmovge\t{$src2, $dst|$dst, $src2}",
1069 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1070 X86_COND_GE, EFLAGS))]>,
1072 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1073 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1074 "cmovge\t{$src2, $dst|$dst, $src2}",
1075 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1076 X86_COND_GE, EFLAGS))]>,
1078 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1079 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1080 "cmovle\t{$src2, $dst|$dst, $src2}",
1081 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1082 X86_COND_LE, EFLAGS))]>,
1084 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1085 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1086 "cmovle\t{$src2, $dst|$dst, $src2}",
1087 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1088 X86_COND_LE, EFLAGS))]>,
1090 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1091 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1092 "cmovg\t{$src2, $dst|$dst, $src2}",
1093 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1094 X86_COND_G, EFLAGS))]>,
1096 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1097 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1098 "cmovg\t{$src2, $dst|$dst, $src2}",
1099 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1100 X86_COND_G, EFLAGS))]>,
1102 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1103 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1104 "cmovs\t{$src2, $dst|$dst, $src2}",
1105 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1106 X86_COND_S, EFLAGS))]>,
1108 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1109 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1110 "cmovs\t{$src2, $dst|$dst, $src2}",
1111 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1112 X86_COND_S, EFLAGS))]>,
1114 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1115 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1116 "cmovns\t{$src2, $dst|$dst, $src2}",
1117 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1118 X86_COND_NS, EFLAGS))]>,
1120 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1121 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1122 "cmovns\t{$src2, $dst|$dst, $src2}",
1123 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1124 X86_COND_NS, EFLAGS))]>,
1126 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1127 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1128 "cmovp\t{$src2, $dst|$dst, $src2}",
1129 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1130 X86_COND_P, EFLAGS))]>,
1132 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1133 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1134 "cmovp\t{$src2, $dst|$dst, $src2}",
1135 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1136 X86_COND_P, EFLAGS))]>,
1138 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1139 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1140 "cmovnp\t{$src2, $dst|$dst, $src2}",
1141 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1142 X86_COND_NP, EFLAGS))]>,
1144 } // Uses = [EFLAGS]
1147 // unary instructions
1148 let CodeSize = 2 in {
1149 let Defs = [EFLAGS] in {
1150 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1151 [(set GR8:$dst, (ineg GR8:$src))]>;
1152 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1153 [(set GR16:$dst, (ineg GR16:$src))]>, OpSize;
1154 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1155 [(set GR32:$dst, (ineg GR32:$src))]>;
1156 let isTwoAddress = 0 in {
1157 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1158 [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
1159 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1160 [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1161 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1162 [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
1165 } // Defs = [EFLAGS]
1167 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1168 [(set GR8:$dst, (not GR8:$src))]>;
1169 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1170 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1171 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1172 [(set GR32:$dst, (not GR32:$src))]>;
1173 let isTwoAddress = 0 in {
1174 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1175 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1176 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1177 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1178 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1179 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1183 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1184 let Defs = [EFLAGS] in {
1186 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1187 [(set GR8:$dst, (add GR8:$src, 1))]>;
1188 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1189 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1190 [(set GR16:$dst, (add GR16:$src, 1))]>,
1191 OpSize, Requires<[In32BitMode]>;
1192 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1193 [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>;
1195 let isTwoAddress = 0, CodeSize = 2 in {
1196 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1197 [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
1198 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1199 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>,
1200 OpSize, Requires<[In32BitMode]>;
1201 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1202 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>,
1203 Requires<[In32BitMode]>;
1207 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1208 [(set GR8:$dst, (add GR8:$src, -1))]>;
1209 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1210 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1211 [(set GR16:$dst, (add GR16:$src, -1))]>,
1212 OpSize, Requires<[In32BitMode]>;
1213 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1214 [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>;
1217 let isTwoAddress = 0, CodeSize = 2 in {
1218 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1219 [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
1220 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1221 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>,
1222 OpSize, Requires<[In32BitMode]>;
1223 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1224 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>,
1225 Requires<[In32BitMode]>;
1227 } // Defs = [EFLAGS]
1229 // Logical operators...
1230 let Defs = [EFLAGS] in {
1231 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1232 def AND8rr : I<0x20, MRMDestReg,
1233 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1234 "and{b}\t{$src2, $dst|$dst, $src2}",
1235 [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>;
1236 def AND16rr : I<0x21, MRMDestReg,
1237 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1238 "and{w}\t{$src2, $dst|$dst, $src2}",
1239 [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize;
1240 def AND32rr : I<0x21, MRMDestReg,
1241 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1242 "and{l}\t{$src2, $dst|$dst, $src2}",
1243 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
1246 def AND8rm : I<0x22, MRMSrcMem,
1247 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1248 "and{b}\t{$src2, $dst|$dst, $src2}",
1249 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>;
1250 def AND16rm : I<0x23, MRMSrcMem,
1251 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1252 "and{w}\t{$src2, $dst|$dst, $src2}",
1253 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize;
1254 def AND32rm : I<0x23, MRMSrcMem,
1255 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1256 "and{l}\t{$src2, $dst|$dst, $src2}",
1257 [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>;
1259 def AND8ri : Ii8<0x80, MRM4r,
1260 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1261 "and{b}\t{$src2, $dst|$dst, $src2}",
1262 [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>;
1263 def AND16ri : Ii16<0x81, MRM4r,
1264 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1265 "and{w}\t{$src2, $dst|$dst, $src2}",
1266 [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize;
1267 def AND32ri : Ii32<0x81, MRM4r,
1268 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1269 "and{l}\t{$src2, $dst|$dst, $src2}",
1270 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
1271 def AND16ri8 : Ii8<0x83, MRM4r,
1272 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1273 "and{w}\t{$src2, $dst|$dst, $src2}",
1274 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>,
1276 def AND32ri8 : Ii8<0x83, MRM4r,
1277 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1278 "and{l}\t{$src2, $dst|$dst, $src2}",
1279 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>;
1281 let isTwoAddress = 0 in {
1282 def AND8mr : I<0x20, MRMDestMem,
1283 (outs), (ins i8mem :$dst, GR8 :$src),
1284 "and{b}\t{$src, $dst|$dst, $src}",
1285 [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>;
1286 def AND16mr : I<0x21, MRMDestMem,
1287 (outs), (ins i16mem:$dst, GR16:$src),
1288 "and{w}\t{$src, $dst|$dst, $src}",
1289 [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>,
1291 def AND32mr : I<0x21, MRMDestMem,
1292 (outs), (ins i32mem:$dst, GR32:$src),
1293 "and{l}\t{$src, $dst|$dst, $src}",
1294 [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>;
1295 def AND8mi : Ii8<0x80, MRM4m,
1296 (outs), (ins i8mem :$dst, i8imm :$src),
1297 "and{b}\t{$src, $dst|$dst, $src}",
1298 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1299 def AND16mi : Ii16<0x81, MRM4m,
1300 (outs), (ins i16mem:$dst, i16imm:$src),
1301 "and{w}\t{$src, $dst|$dst, $src}",
1302 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1304 def AND32mi : Ii32<0x81, MRM4m,
1305 (outs), (ins i32mem:$dst, i32imm:$src),
1306 "and{l}\t{$src, $dst|$dst, $src}",
1307 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1308 def AND16mi8 : Ii8<0x83, MRM4m,
1309 (outs), (ins i16mem:$dst, i16i8imm :$src),
1310 "and{w}\t{$src, $dst|$dst, $src}",
1311 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1313 def AND32mi8 : Ii8<0x83, MRM4m,
1314 (outs), (ins i32mem:$dst, i32i8imm :$src),
1315 "and{l}\t{$src, $dst|$dst, $src}",
1316 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1320 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1321 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1322 "or{b}\t{$src2, $dst|$dst, $src2}",
1323 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
1324 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1325 "or{w}\t{$src2, $dst|$dst, $src2}",
1326 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize;
1327 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1328 "or{l}\t{$src2, $dst|$dst, $src2}",
1329 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
1331 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1332 "or{b}\t{$src2, $dst|$dst, $src2}",
1333 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
1334 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1335 "or{w}\t{$src2, $dst|$dst, $src2}",
1336 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize;
1337 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1338 "or{l}\t{$src2, $dst|$dst, $src2}",
1339 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>;
1341 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1342 "or{b}\t{$src2, $dst|$dst, $src2}",
1343 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
1344 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1345 "or{w}\t{$src2, $dst|$dst, $src2}",
1346 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize;
1347 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1348 "or{l}\t{$src2, $dst|$dst, $src2}",
1349 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
1351 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1352 "or{w}\t{$src2, $dst|$dst, $src2}",
1353 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1354 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1355 "or{l}\t{$src2, $dst|$dst, $src2}",
1356 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>;
1357 let isTwoAddress = 0 in {
1358 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1359 "or{b}\t{$src, $dst|$dst, $src}",
1360 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
1361 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1362 "or{w}\t{$src, $dst|$dst, $src}",
1363 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize;
1364 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1365 "or{l}\t{$src, $dst|$dst, $src}",
1366 [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>;
1367 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1368 "or{b}\t{$src, $dst|$dst, $src}",
1369 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1370 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1371 "or{w}\t{$src, $dst|$dst, $src}",
1372 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1374 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1375 "or{l}\t{$src, $dst|$dst, $src}",
1376 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1377 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1378 "or{w}\t{$src, $dst|$dst, $src}",
1379 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1381 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1382 "or{l}\t{$src, $dst|$dst, $src}",
1383 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1384 } // isTwoAddress = 0
1387 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1388 def XOR8rr : I<0x30, MRMDestReg,
1389 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1390 "xor{b}\t{$src2, $dst|$dst, $src2}",
1391 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>;
1392 def XOR16rr : I<0x31, MRMDestReg,
1393 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1394 "xor{w}\t{$src2, $dst|$dst, $src2}",
1395 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize;
1396 def XOR32rr : I<0x31, MRMDestReg,
1397 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1398 "xor{l}\t{$src2, $dst|$dst, $src2}",
1399 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
1400 } // isCommutable = 1
1402 def XOR8rm : I<0x32, MRMSrcMem ,
1403 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1404 "xor{b}\t{$src2, $dst|$dst, $src2}",
1405 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>;
1406 def XOR16rm : I<0x33, MRMSrcMem ,
1407 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1408 "xor{w}\t{$src2, $dst|$dst, $src2}",
1409 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>,
1411 def XOR32rm : I<0x33, MRMSrcMem ,
1412 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1413 "xor{l}\t{$src2, $dst|$dst, $src2}",
1414 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>;
1416 def XOR8ri : Ii8<0x80, MRM6r,
1417 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1418 "xor{b}\t{$src2, $dst|$dst, $src2}",
1419 [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>;
1420 def XOR16ri : Ii16<0x81, MRM6r,
1421 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1422 "xor{w}\t{$src2, $dst|$dst, $src2}",
1423 [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize;
1424 def XOR32ri : Ii32<0x81, MRM6r,
1425 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1426 "xor{l}\t{$src2, $dst|$dst, $src2}",
1427 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
1428 def XOR16ri8 : Ii8<0x83, MRM6r,
1429 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1430 "xor{w}\t{$src2, $dst|$dst, $src2}",
1431 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>,
1433 def XOR32ri8 : Ii8<0x83, MRM6r,
1434 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1435 "xor{l}\t{$src2, $dst|$dst, $src2}",
1436 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>;
1438 let isTwoAddress = 0 in {
1439 def XOR8mr : I<0x30, MRMDestMem,
1440 (outs), (ins i8mem :$dst, GR8 :$src),
1441 "xor{b}\t{$src, $dst|$dst, $src}",
1442 [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>;
1443 def XOR16mr : I<0x31, MRMDestMem,
1444 (outs), (ins i16mem:$dst, GR16:$src),
1445 "xor{w}\t{$src, $dst|$dst, $src}",
1446 [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>,
1448 def XOR32mr : I<0x31, MRMDestMem,
1449 (outs), (ins i32mem:$dst, GR32:$src),
1450 "xor{l}\t{$src, $dst|$dst, $src}",
1451 [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>;
1452 def XOR8mi : Ii8<0x80, MRM6m,
1453 (outs), (ins i8mem :$dst, i8imm :$src),
1454 "xor{b}\t{$src, $dst|$dst, $src}",
1455 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1456 def XOR16mi : Ii16<0x81, MRM6m,
1457 (outs), (ins i16mem:$dst, i16imm:$src),
1458 "xor{w}\t{$src, $dst|$dst, $src}",
1459 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1461 def XOR32mi : Ii32<0x81, MRM6m,
1462 (outs), (ins i32mem:$dst, i32imm:$src),
1463 "xor{l}\t{$src, $dst|$dst, $src}",
1464 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1465 def XOR16mi8 : Ii8<0x83, MRM6m,
1466 (outs), (ins i16mem:$dst, i16i8imm :$src),
1467 "xor{w}\t{$src, $dst|$dst, $src}",
1468 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1470 def XOR32mi8 : Ii8<0x83, MRM6m,
1471 (outs), (ins i32mem:$dst, i32i8imm :$src),
1472 "xor{l}\t{$src, $dst|$dst, $src}",
1473 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1474 } // isTwoAddress = 0
1475 } // Defs = [EFLAGS]
1477 // Shift instructions
1478 let Defs = [EFLAGS] in {
1479 let Uses = [CL] in {
1480 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1481 "shl{b}\t{%cl, $dst|$dst, %CL}",
1482 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1483 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1484 "shl{w}\t{%cl, $dst|$dst, %CL}",
1485 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1486 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1487 "shl{l}\t{%cl, $dst|$dst, %CL}",
1488 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1491 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1492 "shl{b}\t{$src2, $dst|$dst, $src2}",
1493 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1494 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1495 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1496 "shl{w}\t{$src2, $dst|$dst, $src2}",
1497 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1498 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1499 "shl{l}\t{$src2, $dst|$dst, $src2}",
1500 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1501 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1503 } // isConvertibleToThreeAddress = 1
1505 let isTwoAddress = 0 in {
1506 let Uses = [CL] in {
1507 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1508 "shl{b}\t{%cl, $dst|$dst, %CL}",
1509 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1510 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1511 "shl{w}\t{%cl, $dst|$dst, %CL}",
1512 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1513 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1514 "shl{l}\t{%cl, $dst|$dst, %CL}",
1515 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1517 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1518 "shl{b}\t{$src, $dst|$dst, $src}",
1519 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1520 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1521 "shl{w}\t{$src, $dst|$dst, $src}",
1522 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1524 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1525 "shl{l}\t{$src, $dst|$dst, $src}",
1526 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1529 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1531 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1532 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1534 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1536 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1538 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1541 let Uses = [CL] in {
1542 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1543 "shr{b}\t{%cl, $dst|$dst, %CL}",
1544 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1545 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1546 "shr{w}\t{%cl, $dst|$dst, %CL}",
1547 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1548 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1549 "shr{l}\t{%cl, $dst|$dst, %CL}",
1550 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1553 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1554 "shr{b}\t{$src2, $dst|$dst, $src2}",
1555 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1556 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1557 "shr{w}\t{$src2, $dst|$dst, $src2}",
1558 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1559 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1560 "shr{l}\t{$src2, $dst|$dst, $src2}",
1561 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1564 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1566 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1567 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1569 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1570 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1572 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1574 let isTwoAddress = 0 in {
1575 let Uses = [CL] in {
1576 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1577 "shr{b}\t{%cl, $dst|$dst, %CL}",
1578 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1579 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1580 "shr{w}\t{%cl, $dst|$dst, %CL}",
1581 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1583 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1584 "shr{l}\t{%cl, $dst|$dst, %CL}",
1585 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1587 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1588 "shr{b}\t{$src, $dst|$dst, $src}",
1589 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1590 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1591 "shr{w}\t{$src, $dst|$dst, $src}",
1592 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1594 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1595 "shr{l}\t{$src, $dst|$dst, $src}",
1596 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1599 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1601 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1602 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1604 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1605 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1607 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1610 let Uses = [CL] in {
1611 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1612 "sar{b}\t{%cl, $dst|$dst, %CL}",
1613 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1614 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1615 "sar{w}\t{%cl, $dst|$dst, %CL}",
1616 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1617 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1618 "sar{l}\t{%cl, $dst|$dst, %CL}",
1619 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1622 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1623 "sar{b}\t{$src2, $dst|$dst, $src2}",
1624 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1625 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1626 "sar{w}\t{$src2, $dst|$dst, $src2}",
1627 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1629 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1630 "sar{l}\t{$src2, $dst|$dst, $src2}",
1631 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1634 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1636 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1637 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1639 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1640 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1642 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1644 let isTwoAddress = 0 in {
1645 let Uses = [CL] in {
1646 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1647 "sar{b}\t{%cl, $dst|$dst, %CL}",
1648 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
1649 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1650 "sar{w}\t{%cl, $dst|$dst, %CL}",
1651 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1652 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1653 "sar{l}\t{%cl, $dst|$dst, %CL}",
1654 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1656 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1657 "sar{b}\t{$src, $dst|$dst, $src}",
1658 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1659 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1660 "sar{w}\t{$src, $dst|$dst, $src}",
1661 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1663 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1664 "sar{l}\t{$src, $dst|$dst, $src}",
1665 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1668 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1670 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1671 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1673 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1675 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
1677 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1680 // Rotate instructions
1681 // FIXME: provide shorter instructions when imm8 == 1
1682 let Uses = [CL] in {
1683 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
1684 "rol{b}\t{%cl, $dst|$dst, %CL}",
1685 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
1686 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
1687 "rol{w}\t{%cl, $dst|$dst, %CL}",
1688 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
1689 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
1690 "rol{l}\t{%cl, $dst|$dst, %CL}",
1691 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
1694 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1695 "rol{b}\t{$src2, $dst|$dst, $src2}",
1696 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1697 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1698 "rol{w}\t{$src2, $dst|$dst, $src2}",
1699 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1700 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1701 "rol{l}\t{$src2, $dst|$dst, $src2}",
1702 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1705 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1707 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1708 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
1710 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1711 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1713 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1715 let isTwoAddress = 0 in {
1716 let Uses = [CL] in {
1717 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
1718 "rol{b}\t{%cl, $dst|$dst, %CL}",
1719 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
1720 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
1721 "rol{w}\t{%cl, $dst|$dst, %CL}",
1722 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1723 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
1724 "rol{l}\t{%cl, $dst|$dst, %CL}",
1725 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
1727 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
1728 "rol{b}\t{$src, $dst|$dst, $src}",
1729 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1730 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
1731 "rol{w}\t{$src, $dst|$dst, $src}",
1732 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1734 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
1735 "rol{l}\t{$src, $dst|$dst, $src}",
1736 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1739 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
1741 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1742 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
1744 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1746 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
1748 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1751 let Uses = [CL] in {
1752 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
1753 "ror{b}\t{%cl, $dst|$dst, %CL}",
1754 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
1755 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
1756 "ror{w}\t{%cl, $dst|$dst, %CL}",
1757 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
1758 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
1759 "ror{l}\t{%cl, $dst|$dst, %CL}",
1760 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
1763 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1764 "ror{b}\t{$src2, $dst|$dst, $src2}",
1765 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
1766 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1767 "ror{w}\t{$src2, $dst|$dst, $src2}",
1768 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1769 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1770 "ror{l}\t{$src2, $dst|$dst, $src2}",
1771 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
1774 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1776 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
1777 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
1779 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
1780 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
1782 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
1784 let isTwoAddress = 0 in {
1785 let Uses = [CL] in {
1786 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
1787 "ror{b}\t{%cl, $dst|$dst, %CL}",
1788 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
1789 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
1790 "ror{w}\t{%cl, $dst|$dst, %CL}",
1791 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1792 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
1793 "ror{l}\t{%cl, $dst|$dst, %CL}",
1794 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
1796 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1797 "ror{b}\t{$src, $dst|$dst, $src}",
1798 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1799 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
1800 "ror{w}\t{$src, $dst|$dst, $src}",
1801 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1803 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
1804 "ror{l}\t{$src, $dst|$dst, $src}",
1805 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1808 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
1810 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1811 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
1813 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1815 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
1817 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1822 // Double shift instructions (generalizations of rotate)
1823 let Uses = [CL] in {
1824 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1825 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1826 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
1827 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1828 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1829 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
1830 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1831 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1832 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
1834 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1835 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1836 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
1840 let isCommutable = 1 in { // These instructions commute to each other.
1841 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
1842 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1843 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1844 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
1847 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
1848 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1849 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1850 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
1853 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
1854 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1855 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1856 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
1859 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
1860 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1861 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1862 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
1867 let isTwoAddress = 0 in {
1868 let Uses = [CL] in {
1869 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1870 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1871 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
1873 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1874 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1875 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
1878 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
1879 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1880 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1881 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
1882 (i8 imm:$src3)), addr:$dst)]>,
1884 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
1885 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1886 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1887 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
1888 (i8 imm:$src3)), addr:$dst)]>,
1891 let Uses = [CL] in {
1892 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1893 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1894 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
1895 addr:$dst)]>, TB, OpSize;
1896 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1897 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1898 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
1899 addr:$dst)]>, TB, OpSize;
1901 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
1902 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1903 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1904 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
1905 (i8 imm:$src3)), addr:$dst)]>,
1907 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
1908 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1909 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1910 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
1911 (i8 imm:$src3)), addr:$dst)]>,
1914 } // Defs = [EFLAGS]
1918 let Defs = [EFLAGS] in {
1919 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1920 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
1921 (ins GR8 :$src1, GR8 :$src2),
1922 "add{b}\t{$src2, $dst|$dst, $src2}",
1923 [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>;
1924 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1925 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
1926 (ins GR16:$src1, GR16:$src2),
1927 "add{w}\t{$src2, $dst|$dst, $src2}",
1928 [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize;
1929 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
1930 (ins GR32:$src1, GR32:$src2),
1931 "add{l}\t{$src2, $dst|$dst, $src2}",
1932 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
1933 } // end isConvertibleToThreeAddress
1934 } // end isCommutable
1935 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
1936 (ins GR8 :$src1, i8mem :$src2),
1937 "add{b}\t{$src2, $dst|$dst, $src2}",
1938 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>;
1939 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
1940 (ins GR16:$src1, i16mem:$src2),
1941 "add{w}\t{$src2, $dst|$dst, $src2}",
1942 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>,OpSize;
1943 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
1944 (ins GR32:$src1, i32mem:$src2),
1945 "add{l}\t{$src2, $dst|$dst, $src2}",
1946 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>;
1948 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1949 "add{b}\t{$src2, $dst|$dst, $src2}",
1950 [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>;
1952 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1953 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
1954 (ins GR16:$src1, i16imm:$src2),
1955 "add{w}\t{$src2, $dst|$dst, $src2}",
1956 [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize;
1957 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
1958 (ins GR32:$src1, i32imm:$src2),
1959 "add{l}\t{$src2, $dst|$dst, $src2}",
1960 [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>;
1961 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
1962 (ins GR16:$src1, i16i8imm:$src2),
1963 "add{w}\t{$src2, $dst|$dst, $src2}",
1964 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1965 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
1966 (ins GR32:$src1, i32i8imm:$src2),
1967 "add{l}\t{$src2, $dst|$dst, $src2}",
1968 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>;
1971 let isTwoAddress = 0 in {
1972 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1973 "add{b}\t{$src2, $dst|$dst, $src2}",
1974 [(store (add (load addr:$dst), GR8:$src2), addr:$dst)]>;
1975 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1976 "add{w}\t{$src2, $dst|$dst, $src2}",
1977 [(store (add (load addr:$dst), GR16:$src2), addr:$dst)]>,
1979 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1980 "add{l}\t{$src2, $dst|$dst, $src2}",
1981 [(store (add (load addr:$dst), GR32:$src2), addr:$dst)]>;
1982 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
1983 "add{b}\t{$src2, $dst|$dst, $src2}",
1984 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1985 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
1986 "add{w}\t{$src2, $dst|$dst, $src2}",
1987 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1989 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
1990 "add{l}\t{$src2, $dst|$dst, $src2}",
1991 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1992 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1993 "add{w}\t{$src2, $dst|$dst, $src2}",
1994 [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1996 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1997 "add{l}\t{$src2, $dst|$dst, $src2}",
1998 [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2001 let Uses = [EFLAGS] in {
2002 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2003 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2004 "adc{l}\t{$src2, $dst|$dst, $src2}",
2005 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2007 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2008 "adc{l}\t{$src2, $dst|$dst, $src2}",
2009 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2010 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2011 "adc{l}\t{$src2, $dst|$dst, $src2}",
2012 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2013 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2014 "adc{l}\t{$src2, $dst|$dst, $src2}",
2015 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2017 let isTwoAddress = 0 in {
2018 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2019 "adc{l}\t{$src2, $dst|$dst, $src2}",
2020 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2021 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2022 "adc{l}\t{$src2, $dst|$dst, $src2}",
2023 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2024 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2025 "adc{l}\t{$src2, $dst|$dst, $src2}",
2026 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2028 } // Uses = [EFLAGS]
2030 def SUB8rr : I<0x28, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
2031 "sub{b}\t{$src2, $dst|$dst, $src2}",
2032 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2))]>;
2033 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2034 "sub{w}\t{$src2, $dst|$dst, $src2}",
2035 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2))]>, OpSize;
2036 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2037 "sub{l}\t{$src2, $dst|$dst, $src2}",
2038 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
2039 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
2040 "sub{b}\t{$src2, $dst|$dst, $src2}",
2041 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2)))]>;
2042 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2043 "sub{w}\t{$src2, $dst|$dst, $src2}",
2044 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2)))]>, OpSize;
2045 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2046 "sub{l}\t{$src2, $dst|$dst, $src2}",
2047 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2)))]>;
2049 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2050 "sub{b}\t{$src2, $dst|$dst, $src2}",
2051 [(set GR8:$dst, (sub GR8:$src1, imm:$src2))]>;
2052 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2053 "sub{w}\t{$src2, $dst|$dst, $src2}",
2054 [(set GR16:$dst, (sub GR16:$src1, imm:$src2))]>, OpSize;
2055 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2056 "sub{l}\t{$src2, $dst|$dst, $src2}",
2057 [(set GR32:$dst, (sub GR32:$src1, imm:$src2))]>;
2058 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2059 "sub{w}\t{$src2, $dst|$dst, $src2}",
2060 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2))]>,
2062 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2063 "sub{l}\t{$src2, $dst|$dst, $src2}",
2064 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2))]>;
2065 let isTwoAddress = 0 in {
2066 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2067 "sub{b}\t{$src2, $dst|$dst, $src2}",
2068 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst)]>;
2069 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2070 "sub{w}\t{$src2, $dst|$dst, $src2}",
2071 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst)]>,
2073 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2074 "sub{l}\t{$src2, $dst|$dst, $src2}",
2075 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst)]>;
2076 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2077 "sub{b}\t{$src2, $dst|$dst, $src2}",
2078 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2079 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2080 "sub{w}\t{$src2, $dst|$dst, $src2}",
2081 [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2083 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2084 "sub{l}\t{$src2, $dst|$dst, $src2}",
2085 [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2086 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2087 "sub{w}\t{$src2, $dst|$dst, $src2}",
2088 [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2090 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2091 "sub{l}\t{$src2, $dst|$dst, $src2}",
2092 [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2095 let Uses = [EFLAGS] in {
2096 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2097 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2098 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2100 let isTwoAddress = 0 in {
2101 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2102 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2103 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2104 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2105 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2106 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2107 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2108 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2109 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2110 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2111 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2112 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2114 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2115 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2116 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2117 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2118 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2119 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2120 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2121 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2122 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2123 } // Uses = [EFLAGS]
2124 } // Defs = [EFLAGS]
2126 let Defs = [EFLAGS] in {
2127 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2128 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2129 "imul{w}\t{$src2, $dst|$dst, $src2}",
2130 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2))]>, TB, OpSize;
2131 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2132 "imul{l}\t{$src2, $dst|$dst, $src2}",
2133 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>, TB;
2135 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2136 "imul{w}\t{$src2, $dst|$dst, $src2}",
2137 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2)))]>,
2139 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2140 "imul{l}\t{$src2, $dst|$dst, $src2}",
2141 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2)))]>, TB;
2142 } // Defs = [EFLAGS]
2143 } // end Two Address instructions
2145 // Suprisingly enough, these are not two address instructions!
2146 let Defs = [EFLAGS] in {
2147 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2148 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2149 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2150 [(set GR16:$dst, (mul GR16:$src1, imm:$src2))]>, OpSize;
2151 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2152 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2153 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2154 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
2155 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2156 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2157 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2158 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2))]>,
2160 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2161 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2162 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2163 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2))]>;
2165 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2166 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2167 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2168 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2))]>,
2170 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2171 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2172 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2173 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2))]>;
2174 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2175 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2176 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2177 [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>,
2179 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2180 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2181 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2182 [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>;
2183 } // Defs = [EFLAGS]
2185 //===----------------------------------------------------------------------===//
2186 // Test instructions are just like AND, except they don't generate a result.
2188 let Defs = [EFLAGS] in {
2189 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2190 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2191 "test{b}\t{$src2, $src1|$src1, $src2}",
2192 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
2193 (implicit EFLAGS)]>;
2194 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2195 "test{w}\t{$src2, $src1|$src1, $src2}",
2196 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
2197 (implicit EFLAGS)]>,
2199 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2200 "test{l}\t{$src2, $src1|$src1, $src2}",
2201 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
2202 (implicit EFLAGS)]>;
2205 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2206 "test{b}\t{$src2, $src1|$src1, $src2}",
2207 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2208 (implicit EFLAGS)]>;
2209 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2210 "test{w}\t{$src2, $src1|$src1, $src2}",
2211 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2212 (implicit EFLAGS)]>, OpSize;
2213 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2214 "test{l}\t{$src2, $src1|$src1, $src2}",
2215 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2216 (implicit EFLAGS)]>;
2218 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2219 (outs), (ins GR8:$src1, i8imm:$src2),
2220 "test{b}\t{$src2, $src1|$src1, $src2}",
2221 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
2222 (implicit EFLAGS)]>;
2223 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2224 (outs), (ins GR16:$src1, i16imm:$src2),
2225 "test{w}\t{$src2, $src1|$src1, $src2}",
2226 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
2227 (implicit EFLAGS)]>, OpSize;
2228 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2229 (outs), (ins GR32:$src1, i32imm:$src2),
2230 "test{l}\t{$src2, $src1|$src1, $src2}",
2231 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
2232 (implicit EFLAGS)]>;
2234 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2235 (outs), (ins i8mem:$src1, i8imm:$src2),
2236 "test{b}\t{$src2, $src1|$src1, $src2}",
2237 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2238 (implicit EFLAGS)]>;
2239 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2240 (outs), (ins i16mem:$src1, i16imm:$src2),
2241 "test{w}\t{$src2, $src1|$src1, $src2}",
2242 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2243 (implicit EFLAGS)]>, OpSize;
2244 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2245 (outs), (ins i32mem:$src1, i32imm:$src2),
2246 "test{l}\t{$src2, $src1|$src1, $src2}",
2247 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2248 (implicit EFLAGS)]>;
2249 } // Defs = [EFLAGS]
2252 // Condition code ops, incl. set if equal/not equal/...
2253 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2254 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2255 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2256 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2258 let Uses = [EFLAGS] in {
2259 def SETEr : I<0x94, MRM0r,
2260 (outs GR8 :$dst), (ins),
2262 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2264 def SETEm : I<0x94, MRM0m,
2265 (outs), (ins i8mem:$dst),
2267 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2269 def SETNEr : I<0x95, MRM0r,
2270 (outs GR8 :$dst), (ins),
2272 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2274 def SETNEm : I<0x95, MRM0m,
2275 (outs), (ins i8mem:$dst),
2277 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2279 def SETLr : I<0x9C, MRM0r,
2280 (outs GR8 :$dst), (ins),
2282 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2283 TB; // GR8 = < signed
2284 def SETLm : I<0x9C, MRM0m,
2285 (outs), (ins i8mem:$dst),
2287 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2288 TB; // [mem8] = < signed
2289 def SETGEr : I<0x9D, MRM0r,
2290 (outs GR8 :$dst), (ins),
2292 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2293 TB; // GR8 = >= signed
2294 def SETGEm : I<0x9D, MRM0m,
2295 (outs), (ins i8mem:$dst),
2297 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2298 TB; // [mem8] = >= signed
2299 def SETLEr : I<0x9E, MRM0r,
2300 (outs GR8 :$dst), (ins),
2302 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2303 TB; // GR8 = <= signed
2304 def SETLEm : I<0x9E, MRM0m,
2305 (outs), (ins i8mem:$dst),
2307 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2308 TB; // [mem8] = <= signed
2309 def SETGr : I<0x9F, MRM0r,
2310 (outs GR8 :$dst), (ins),
2312 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2313 TB; // GR8 = > signed
2314 def SETGm : I<0x9F, MRM0m,
2315 (outs), (ins i8mem:$dst),
2317 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2318 TB; // [mem8] = > signed
2320 def SETBr : I<0x92, MRM0r,
2321 (outs GR8 :$dst), (ins),
2323 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2324 TB; // GR8 = < unsign
2325 def SETBm : I<0x92, MRM0m,
2326 (outs), (ins i8mem:$dst),
2328 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
2329 TB; // [mem8] = < unsign
2330 def SETAEr : I<0x93, MRM0r,
2331 (outs GR8 :$dst), (ins),
2333 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
2334 TB; // GR8 = >= unsign
2335 def SETAEm : I<0x93, MRM0m,
2336 (outs), (ins i8mem:$dst),
2338 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
2339 TB; // [mem8] = >= unsign
2340 def SETBEr : I<0x96, MRM0r,
2341 (outs GR8 :$dst), (ins),
2343 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
2344 TB; // GR8 = <= unsign
2345 def SETBEm : I<0x96, MRM0m,
2346 (outs), (ins i8mem:$dst),
2348 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
2349 TB; // [mem8] = <= unsign
2350 def SETAr : I<0x97, MRM0r,
2351 (outs GR8 :$dst), (ins),
2353 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
2354 TB; // GR8 = > signed
2355 def SETAm : I<0x97, MRM0m,
2356 (outs), (ins i8mem:$dst),
2358 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
2359 TB; // [mem8] = > signed
2361 def SETSr : I<0x98, MRM0r,
2362 (outs GR8 :$dst), (ins),
2364 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
2365 TB; // GR8 = <sign bit>
2366 def SETSm : I<0x98, MRM0m,
2367 (outs), (ins i8mem:$dst),
2369 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
2370 TB; // [mem8] = <sign bit>
2371 def SETNSr : I<0x99, MRM0r,
2372 (outs GR8 :$dst), (ins),
2374 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
2375 TB; // GR8 = !<sign bit>
2376 def SETNSm : I<0x99, MRM0m,
2377 (outs), (ins i8mem:$dst),
2379 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
2380 TB; // [mem8] = !<sign bit>
2381 def SETPr : I<0x9A, MRM0r,
2382 (outs GR8 :$dst), (ins),
2384 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
2386 def SETPm : I<0x9A, MRM0m,
2387 (outs), (ins i8mem:$dst),
2389 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
2390 TB; // [mem8] = parity
2391 def SETNPr : I<0x9B, MRM0r,
2392 (outs GR8 :$dst), (ins),
2394 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
2395 TB; // GR8 = not parity
2396 def SETNPm : I<0x9B, MRM0m,
2397 (outs), (ins i8mem:$dst),
2399 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
2400 TB; // [mem8] = not parity
2401 } // Uses = [EFLAGS]
2404 // Integer comparisons
2405 let Defs = [EFLAGS] in {
2406 def CMP8rr : I<0x38, MRMDestReg,
2407 (outs), (ins GR8 :$src1, GR8 :$src2),
2408 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2409 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2410 def CMP16rr : I<0x39, MRMDestReg,
2411 (outs), (ins GR16:$src1, GR16:$src2),
2412 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2413 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
2414 def CMP32rr : I<0x39, MRMDestReg,
2415 (outs), (ins GR32:$src1, GR32:$src2),
2416 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2417 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
2418 def CMP8mr : I<0x38, MRMDestMem,
2419 (outs), (ins i8mem :$src1, GR8 :$src2),
2420 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2421 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
2422 (implicit EFLAGS)]>;
2423 def CMP16mr : I<0x39, MRMDestMem,
2424 (outs), (ins i16mem:$src1, GR16:$src2),
2425 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2426 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
2427 (implicit EFLAGS)]>, OpSize;
2428 def CMP32mr : I<0x39, MRMDestMem,
2429 (outs), (ins i32mem:$src1, GR32:$src2),
2430 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2431 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
2432 (implicit EFLAGS)]>;
2433 def CMP8rm : I<0x3A, MRMSrcMem,
2434 (outs), (ins GR8 :$src1, i8mem :$src2),
2435 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2436 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
2437 (implicit EFLAGS)]>;
2438 def CMP16rm : I<0x3B, MRMSrcMem,
2439 (outs), (ins GR16:$src1, i16mem:$src2),
2440 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2441 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
2442 (implicit EFLAGS)]>, OpSize;
2443 def CMP32rm : I<0x3B, MRMSrcMem,
2444 (outs), (ins GR32:$src1, i32mem:$src2),
2445 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2446 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
2447 (implicit EFLAGS)]>;
2448 def CMP8ri : Ii8<0x80, MRM7r,
2449 (outs), (ins GR8:$src1, i8imm:$src2),
2450 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2451 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
2452 def CMP16ri : Ii16<0x81, MRM7r,
2453 (outs), (ins GR16:$src1, i16imm:$src2),
2454 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2455 [(X86cmp GR16:$src1, imm:$src2),
2456 (implicit EFLAGS)]>, OpSize;
2457 def CMP32ri : Ii32<0x81, MRM7r,
2458 (outs), (ins GR32:$src1, i32imm:$src2),
2459 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2460 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
2461 def CMP8mi : Ii8 <0x80, MRM7m,
2462 (outs), (ins i8mem :$src1, i8imm :$src2),
2463 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2464 [(X86cmp (loadi8 addr:$src1), imm:$src2),
2465 (implicit EFLAGS)]>;
2466 def CMP16mi : Ii16<0x81, MRM7m,
2467 (outs), (ins i16mem:$src1, i16imm:$src2),
2468 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2469 [(X86cmp (loadi16 addr:$src1), imm:$src2),
2470 (implicit EFLAGS)]>, OpSize;
2471 def CMP32mi : Ii32<0x81, MRM7m,
2472 (outs), (ins i32mem:$src1, i32imm:$src2),
2473 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2474 [(X86cmp (loadi32 addr:$src1), imm:$src2),
2475 (implicit EFLAGS)]>;
2476 def CMP16ri8 : Ii8<0x83, MRM7r,
2477 (outs), (ins GR16:$src1, i16i8imm:$src2),
2478 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2479 [(X86cmp GR16:$src1, i16immSExt8:$src2),
2480 (implicit EFLAGS)]>, OpSize;
2481 def CMP16mi8 : Ii8<0x83, MRM7m,
2482 (outs), (ins i16mem:$src1, i16i8imm:$src2),
2483 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2484 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
2485 (implicit EFLAGS)]>, OpSize;
2486 def CMP32mi8 : Ii8<0x83, MRM7m,
2487 (outs), (ins i32mem:$src1, i32i8imm:$src2),
2488 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2489 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
2490 (implicit EFLAGS)]>;
2491 def CMP32ri8 : Ii8<0x83, MRM7r,
2492 (outs), (ins GR32:$src1, i32i8imm:$src2),
2493 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2494 [(X86cmp GR32:$src1, i32immSExt8:$src2),
2495 (implicit EFLAGS)]>;
2496 } // Defs = [EFLAGS]
2498 // Sign/Zero extenders
2499 // Use movsbl intead of movsbw; we don't care about the high 16 bits
2500 // of the register here. This has a smaller encoding and avoids a
2501 // partial-register update.
2502 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2503 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2504 [(set GR16:$dst, (sext GR8:$src))]>, TB;
2505 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2506 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2507 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
2508 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2509 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2510 [(set GR32:$dst, (sext GR8:$src))]>, TB;
2511 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2512 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2513 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
2514 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2515 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2516 [(set GR32:$dst, (sext GR16:$src))]>, TB;
2517 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2518 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2519 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
2521 // Use movzbl intead of movzbw; we don't care about the high 16 bits
2522 // of the register here. This has a smaller encoding and avoids a
2523 // partial-register update.
2524 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2525 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2526 [(set GR16:$dst, (zext GR8:$src))]>, TB;
2527 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2528 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2529 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
2530 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2531 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2532 [(set GR32:$dst, (zext GR8:$src))]>, TB;
2533 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2534 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2535 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
2536 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2537 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2538 [(set GR32:$dst, (zext GR16:$src))]>, TB;
2539 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2540 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2541 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
2543 let neverHasSideEffects = 1 in {
2544 let Defs = [AX], Uses = [AL] in
2545 def CBW : I<0x98, RawFrm, (outs), (ins),
2546 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
2547 let Defs = [EAX], Uses = [AX] in
2548 def CWDE : I<0x98, RawFrm, (outs), (ins),
2549 "{cwtl|cwde}", []>; // EAX = signext(AX)
2551 let Defs = [AX,DX], Uses = [AX] in
2552 def CWD : I<0x99, RawFrm, (outs), (ins),
2553 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
2554 let Defs = [EAX,EDX], Uses = [EAX] in
2555 def CDQ : I<0x99, RawFrm, (outs), (ins),
2556 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
2559 //===----------------------------------------------------------------------===//
2560 // Alias Instructions
2561 //===----------------------------------------------------------------------===//
2563 // Alias instructions that map movr0 to xor.
2564 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2565 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1 in {
2566 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
2567 "xor{b}\t$dst, $dst",
2568 [(set GR8:$dst, 0)]>;
2569 // Use xorl instead of xorw since we don't care about the high 16 bits,
2570 // it's smaller, and it avoids a partial-register update.
2571 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
2572 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
2573 [(set GR16:$dst, 0)]>;
2574 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
2575 "xor{l}\t$dst, $dst",
2576 [(set GR32:$dst, 0)]>;
2579 // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
2580 // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
2581 let neverHasSideEffects = 1 in {
2582 def MOV16to16_ : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16:$src),
2583 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2584 def MOV32to32_ : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32:$src),
2585 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2587 def MOV16_rr : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16_:$src),
2588 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2589 def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src),
2590 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2591 } // neverHasSideEffects
2593 let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
2594 def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src),
2595 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2596 def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src),
2597 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2599 let mayStore = 1, neverHasSideEffects = 1 in {
2600 def MOV16_mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16_:$src),
2601 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2602 def MOV32_mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32_:$src),
2603 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2606 //===----------------------------------------------------------------------===//
2607 // Thread Local Storage Instructions
2611 def TLS_addr32 : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
2612 "leal\t${sym:mem}(,%ebx,1), $dst",
2613 [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
2615 let AddedComplexity = 10 in
2616 def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
2617 "movl\t%gs:($src), $dst",
2618 [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
2620 let AddedComplexity = 15 in
2621 def TLS_gs_ri : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
2622 "movl\t%gs:${src:mem}, $dst",
2624 (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>;
2626 def TLS_tp : I<0, Pseudo, (outs GR32:$dst), (ins),
2627 "movl\t%gs:0, $dst",
2628 [(set GR32:$dst, X86TLStp)]>;
2630 //===----------------------------------------------------------------------===//
2631 // DWARF Pseudo Instructions
2634 def DWARF_LOC : I<0, Pseudo, (outs),
2635 (ins i32imm:$line, i32imm:$col, i32imm:$file),
2636 ".loc\t${file:debug} ${line:debug} ${col:debug}",
2637 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
2640 //===----------------------------------------------------------------------===//
2641 // EH Pseudo Instructions
2643 let isTerminator = 1, isReturn = 1, isBarrier = 1,
2645 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
2646 "ret\t#eh_return, addr: $addr",
2647 [(X86ehret GR32:$addr)]>;
2651 //===----------------------------------------------------------------------===//
2655 // Atomic swap. These are just normal xchg instructions. But since a memory
2656 // operand is referenced, the atomicity is ensured.
2657 let Constraints = "$val = $dst" in {
2658 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2659 "xchg{l}\t{$val, $ptr|$ptr, $val}",
2660 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
2661 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2662 "xchg{w}\t{$val, $ptr|$ptr, $val}",
2663 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
2665 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2666 "xchg{b}\t{$val, $ptr|$ptr, $val}",
2667 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
2670 // Atomic compare and swap.
2671 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
2672 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
2673 "lock\n\tcmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
2674 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
2676 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
2677 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
2678 "lock\n\tcmpxchg8b\t$ptr",
2679 [(X86cas8 addr:$ptr)]>, TB, LOCK;
2682 let Defs = [AX, EFLAGS], Uses = [AX] in {
2683 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
2684 "lock\n\tcmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
2685 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
2687 let Defs = [AL, EFLAGS], Uses = [AL] in {
2688 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
2689 "lock\n\tcmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
2690 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
2693 // Atomic exchange and add
2694 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
2695 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2696 "lock\n\txadd{l}\t{$val, $ptr|$ptr, $val}",
2697 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
2699 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2700 "lock\n\txadd{w}\t{$val, $ptr|$ptr, $val}",
2701 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
2703 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2704 "lock\n\txadd{b}\t{$val, $ptr|$ptr, $val}",
2705 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
2709 // Atomic exchange, and, or, xor
2710 let Constraints = "$val = $dst", Defs = [EFLAGS],
2711 usesCustomDAGSchedInserter = 1 in {
2712 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2713 "#ATOMAND32 PSUEDO!",
2714 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
2715 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2716 "#ATOMOR32 PSUEDO!",
2717 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
2718 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2719 "#ATOMXOR32 PSUEDO!",
2720 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
2721 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2722 "#ATOMNAND32 PSUEDO!",
2723 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
2724 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2725 "#ATOMMIN32 PSUEDO!",
2726 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
2727 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2728 "#ATOMMAX32 PSUEDO!",
2729 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
2730 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2731 "#ATOMUMIN32 PSUEDO!",
2732 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
2733 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2734 "#ATOMUMAX32 PSUEDO!",
2735 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
2737 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2738 "#ATOMAND16 PSUEDO!",
2739 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
2740 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2741 "#ATOMOR16 PSUEDO!",
2742 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
2743 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2744 "#ATOMXOR16 PSUEDO!",
2745 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
2746 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2747 "#ATOMNAND16 PSUEDO!",
2748 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
2749 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2750 "#ATOMMIN16 PSUEDO!",
2751 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
2752 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2753 "#ATOMMAX16 PSUEDO!",
2754 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
2755 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2756 "#ATOMUMIN16 PSUEDO!",
2757 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
2758 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2759 "#ATOMUMAX16 PSUEDO!",
2760 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
2762 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
2763 "#ATOMAND8 PSUEDO!",
2764 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
2765 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
2767 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
2768 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
2769 "#ATOMXOR8 PSUEDO!",
2770 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
2771 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
2772 "#ATOMNAND8 PSUEDO!",
2773 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
2776 let Constraints = "$val1 = $dst1, $val2 = $dst2",
2777 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
2778 Uses = [EAX, EBX, ECX, EDX],
2779 mayLoad = 1, mayStore = 1,
2780 usesCustomDAGSchedInserter = 1 in {
2781 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2782 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2783 "#ATOMAND6432 PSUEDO!", []>;
2784 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2785 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2786 "#ATOMOR6432 PSUEDO!", []>;
2787 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2788 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2789 "#ATOMXOR6432 PSUEDO!", []>;
2790 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2791 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2792 "#ATOMNAND6432 PSUEDO!", []>;
2793 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2794 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2795 "#ATOMADD6432 PSUEDO!", []>;
2796 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2797 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2798 "#ATOMSUB6432 PSUEDO!", []>;
2799 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2800 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2801 "#ATOMSWAP6432 PSUEDO!", []>;
2804 //===----------------------------------------------------------------------===//
2805 // Non-Instruction Patterns
2806 //===----------------------------------------------------------------------===//
2808 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
2809 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
2810 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
2811 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
2812 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
2813 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
2815 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
2816 (ADD32ri GR32:$src1, tconstpool:$src2)>;
2817 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
2818 (ADD32ri GR32:$src1, tjumptable:$src2)>;
2819 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
2820 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
2821 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
2822 (ADD32ri GR32:$src1, texternalsym:$src2)>;
2824 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
2825 (MOV32mi addr:$dst, tglobaladdr:$src)>;
2826 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
2827 (MOV32mi addr:$dst, texternalsym:$src)>;
2831 def : Pat<(X86tailcall GR32:$dst),
2834 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
2836 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
2839 def : Pat<(X86tcret GR32:$dst, imm:$off),
2840 (TCRETURNri GR32:$dst, imm:$off)>;
2842 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
2843 (TCRETURNdi texternalsym:$dst, imm:$off)>;
2845 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
2846 (TCRETURNdi texternalsym:$dst, imm:$off)>;
2848 def : Pat<(X86call (i32 tglobaladdr:$dst)),
2849 (CALLpcrel32 tglobaladdr:$dst)>;
2850 def : Pat<(X86call (i32 texternalsym:$dst)),
2851 (CALLpcrel32 texternalsym:$dst)>;
2853 // X86 specific add which produces a flag.
2854 def : Pat<(addc GR32:$src1, GR32:$src2),
2855 (ADD32rr GR32:$src1, GR32:$src2)>;
2856 def : Pat<(addc GR32:$src1, (load addr:$src2)),
2857 (ADD32rm GR32:$src1, addr:$src2)>;
2858 def : Pat<(addc GR32:$src1, imm:$src2),
2859 (ADD32ri GR32:$src1, imm:$src2)>;
2860 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
2861 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
2863 def : Pat<(subc GR32:$src1, GR32:$src2),
2864 (SUB32rr GR32:$src1, GR32:$src2)>;
2865 def : Pat<(subc GR32:$src1, (load addr:$src2)),
2866 (SUB32rm GR32:$src1, addr:$src2)>;
2867 def : Pat<(subc GR32:$src1, imm:$src2),
2868 (SUB32ri GR32:$src1, imm:$src2)>;
2869 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
2870 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
2874 // TEST R,R is smaller than CMP R,0
2875 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
2876 (TEST8rr GR8:$src1, GR8:$src1)>;
2877 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
2878 (TEST16rr GR16:$src1, GR16:$src1)>;
2879 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
2880 (TEST32rr GR32:$src1, GR32:$src1)>;
2882 // zextload bool -> zextload byte
2883 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2884 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2885 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2887 // extload bool -> extload byte
2888 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2889 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>,
2890 Requires<[In32BitMode]>;
2891 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2892 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>,
2893 Requires<[In32BitMode]>;
2894 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
2895 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
2898 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>,
2899 Requires<[In32BitMode]>;
2900 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>,
2901 Requires<[In32BitMode]>;
2902 def : Pat<(i32 (anyext GR16:$src)),
2903 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
2905 // (and (i32 load), 255) -> (zextload i8)
2906 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
2907 (MOVZX32rm8 addr:$src)>;
2908 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
2909 (MOVZX32rm16 addr:$src)>;
2911 //===----------------------------------------------------------------------===//
2913 //===----------------------------------------------------------------------===//
2915 // Odd encoding trick: -128 fits into an 8-bit immediate field while
2916 // +128 doesn't, so in this special case use a sub instead of an add.
2917 def : Pat<(add GR16:$src1, 128),
2918 (SUB16ri8 GR16:$src1, -128)>;
2919 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
2920 (SUB16mi8 addr:$dst, -128)>;
2921 def : Pat<(add GR32:$src1, 128),
2922 (SUB32ri8 GR32:$src1, -128)>;
2923 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
2924 (SUB32mi8 addr:$dst, -128)>;
2926 // r & (2^16-1) ==> movz
2927 def : Pat<(and GR32:$src1, 0xffff),
2928 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit)))>;
2929 // r & (2^8-1) ==> movz
2930 def : Pat<(and GR32:$src1, 0xff),
2931 (MOVZX32rr8 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src1),
2932 x86_subreg_8bit)))>,
2933 Requires<[In32BitMode]>;
2934 // r & (2^8-1) ==> movz
2935 def : Pat<(and GR16:$src1, 0xff),
2936 (MOVZX16rr8 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src1),
2937 x86_subreg_8bit)))>,
2938 Requires<[In32BitMode]>;
2940 // sext_inreg patterns
2941 def : Pat<(sext_inreg GR32:$src, i16),
2942 (MOVSX32rr16 (i16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)))>;
2943 def : Pat<(sext_inreg GR32:$src, i8),
2944 (MOVSX32rr8 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src),
2945 x86_subreg_8bit)))>,
2946 Requires<[In32BitMode]>;
2947 def : Pat<(sext_inreg GR16:$src, i8),
2948 (MOVSX16rr8 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src),
2949 x86_subreg_8bit)))>,
2950 Requires<[In32BitMode]>;
2953 def : Pat<(i16 (trunc GR32:$src)),
2954 (i16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
2955 def : Pat<(i8 (trunc GR32:$src)),
2956 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src), x86_subreg_8bit))>,
2957 Requires<[In32BitMode]>;
2958 def : Pat<(i8 (trunc GR16:$src)),
2959 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src), x86_subreg_8bit))>,
2960 Requires<[In32BitMode]>;
2962 // (shl x, 1) ==> (add x, x)
2963 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
2964 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
2965 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
2967 // (shl x (and y, 31)) ==> (shl x, y)
2968 def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
2969 (SHL8rCL GR8:$src1)>;
2970 def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
2971 (SHL16rCL GR16:$src1)>;
2972 def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
2973 (SHL32rCL GR32:$src1)>;
2974 def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
2975 (SHL8mCL addr:$dst)>;
2976 def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
2977 (SHL16mCL addr:$dst)>;
2978 def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
2979 (SHL32mCL addr:$dst)>;
2981 def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
2982 (SHR8rCL GR8:$src1)>;
2983 def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
2984 (SHR16rCL GR16:$src1)>;
2985 def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
2986 (SHR32rCL GR32:$src1)>;
2987 def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
2988 (SHR8mCL addr:$dst)>;
2989 def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
2990 (SHR16mCL addr:$dst)>;
2991 def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
2992 (SHR32mCL addr:$dst)>;
2994 def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
2995 (SAR8rCL GR8:$src1)>;
2996 def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
2997 (SAR16rCL GR16:$src1)>;
2998 def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
2999 (SAR32rCL GR32:$src1)>;
3000 def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3001 (SAR8mCL addr:$dst)>;
3002 def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3003 (SAR16mCL addr:$dst)>;
3004 def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3005 (SAR32mCL addr:$dst)>;
3007 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
3008 def : Pat<(or (srl GR32:$src1, CL:$amt),
3009 (shl GR32:$src2, (sub 32, CL:$amt))),
3010 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3012 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
3013 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3014 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3016 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
3017 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3018 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3020 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3021 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3023 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3025 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3026 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3028 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
3029 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3030 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3032 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
3033 def : Pat<(or (shl GR32:$src1, CL:$amt),
3034 (srl GR32:$src2, (sub 32, CL:$amt))),
3035 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3037 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
3038 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3039 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3041 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
3042 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3043 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3045 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3046 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3048 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3050 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3051 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3053 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
3054 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3055 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3057 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
3058 def : Pat<(or (srl GR16:$src1, CL:$amt),
3059 (shl GR16:$src2, (sub 16, CL:$amt))),
3060 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3062 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
3063 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3064 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3066 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
3067 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3068 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3070 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3071 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3073 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3075 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3076 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3078 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
3079 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3080 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3082 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
3083 def : Pat<(or (shl GR16:$src1, CL:$amt),
3084 (srl GR16:$src2, (sub 16, CL:$amt))),
3085 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3087 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
3088 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3089 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3091 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
3092 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3093 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3095 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3096 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3098 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3100 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3101 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3103 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
3104 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3105 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3107 //===----------------------------------------------------------------------===//
3108 // Floating Point Stack Support
3109 //===----------------------------------------------------------------------===//
3111 include "X86InstrFPStack.td"
3113 //===----------------------------------------------------------------------===//
3115 //===----------------------------------------------------------------------===//
3117 include "X86Instr64bit.td"
3119 //===----------------------------------------------------------------------===//
3120 // XMM Floating point support (requires SSE / SSE2)
3121 //===----------------------------------------------------------------------===//
3123 include "X86InstrSSE.td"
3125 //===----------------------------------------------------------------------===//
3126 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
3127 //===----------------------------------------------------------------------===//
3129 include "X86InstrMMX.td"