1 //===----------------------------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
32 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
34 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTX86BrCond : SDTypeProfile<0, 3,
39 [SDTCisVT<0, OtherVT>,
40 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
42 def SDTX86SetCC : SDTypeProfile<1, 2,
44 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86SetCC_C : SDTypeProfile<1, 2,
47 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
49 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
51 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
53 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
54 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
55 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
57 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
58 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
61 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
63 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
67 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
69 def SDTX86Void : SDTypeProfile<0, 0, []>;
71 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
73 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
75 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
77 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
79 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
81 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
82 def SDT_X86MEMBARRIERNoSSE : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
84 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
86 def X86MemBarrierNoSSE : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIERNoSSE,
88 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
90 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
92 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
96 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
97 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
98 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
99 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
101 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
102 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
104 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
105 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
107 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
108 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
110 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
111 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
112 SDNPMayLoad, SDNPMemOperand]>;
113 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
114 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
115 SDNPMayLoad, SDNPMemOperand]>;
116 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
117 [SDNPHasChain, SDNPMayStore,
118 SDNPMayLoad, SDNPMemOperand]>;
119 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
120 [SDNPHasChain, SDNPMayStore,
121 SDNPMayLoad, SDNPMemOperand]>;
122 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
123 [SDNPHasChain, SDNPMayStore,
124 SDNPMayLoad, SDNPMemOperand]>;
125 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
126 [SDNPHasChain, SDNPMayStore,
127 SDNPMayLoad, SDNPMemOperand]>;
128 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
129 [SDNPHasChain, SDNPMayStore,
130 SDNPMayLoad, SDNPMemOperand]>;
131 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
132 [SDNPHasChain, SDNPMayStore,
133 SDNPMayLoad, SDNPMemOperand]>;
134 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
135 [SDNPHasChain, SDNPMayStore,
136 SDNPMayLoad, SDNPMemOperand]>;
137 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
138 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
140 def X86vastart_save_xmm_regs :
141 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
142 SDT_X86VASTART_SAVE_XMM_REGS,
143 [SDNPHasChain, SDNPVariadic]>;
145 def X86callseq_start :
146 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
147 [SDNPHasChain, SDNPOutFlag]>;
149 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
150 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
152 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
153 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
156 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
157 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
158 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
159 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
162 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
163 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
165 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
166 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
168 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
169 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
171 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
174 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
175 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
177 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
179 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
180 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
182 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
185 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
186 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
187 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
189 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
191 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
194 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
196 def X86MingwAlloca : SDNode<"X86ISD::MINGW_ALLOCA", SDTX86Void,
197 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
199 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
202 //===----------------------------------------------------------------------===//
203 // X86 Operand Definitions.
206 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
207 // the index operand of an address, to conform to x86 encoding restrictions.
208 def ptr_rc_nosp : PointerLikeRegClass<1>;
210 // *mem - Operand definitions for the funky X86 addressing mode operands.
212 def X86MemAsmOperand : AsmOperandClass {
214 let SuperClasses = [];
216 def X86AbsMemAsmOperand : AsmOperandClass {
218 let SuperClasses = [X86MemAsmOperand];
220 class X86MemOperand<string printMethod> : Operand<iPTR> {
221 let PrintMethod = printMethod;
222 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
223 let ParserMatchClass = X86MemAsmOperand;
226 def opaque32mem : X86MemOperand<"printopaquemem">;
227 def opaque48mem : X86MemOperand<"printopaquemem">;
228 def opaque80mem : X86MemOperand<"printopaquemem">;
229 def opaque512mem : X86MemOperand<"printopaquemem">;
231 def i8mem : X86MemOperand<"printi8mem">;
232 def i16mem : X86MemOperand<"printi16mem">;
233 def i32mem : X86MemOperand<"printi32mem">;
234 def i64mem : X86MemOperand<"printi64mem">;
235 def i128mem : X86MemOperand<"printi128mem">;
236 def i256mem : X86MemOperand<"printi256mem">;
237 def f32mem : X86MemOperand<"printf32mem">;
238 def f64mem : X86MemOperand<"printf64mem">;
239 def f80mem : X86MemOperand<"printf80mem">;
240 def f128mem : X86MemOperand<"printf128mem">;
241 def f256mem : X86MemOperand<"printf256mem">;
243 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
244 // plain GR64, so that it doesn't potentially require a REX prefix.
245 def i8mem_NOREX : Operand<i64> {
246 let PrintMethod = "printi8mem";
247 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
248 let ParserMatchClass = X86MemAsmOperand;
251 // Special i32mem for addresses of load folding tail calls. These are not
252 // allowed to use callee-saved registers since they must be scheduled
253 // after callee-saved register are popped.
254 def i32mem_TC : Operand<i32> {
255 let PrintMethod = "printi32mem";
256 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
257 let ParserMatchClass = X86MemAsmOperand;
261 let ParserMatchClass = X86AbsMemAsmOperand,
262 PrintMethod = "print_pcrel_imm" in {
263 def i32imm_pcrel : Operand<i32>;
264 def i16imm_pcrel : Operand<i16>;
266 def offset8 : Operand<i64>;
267 def offset16 : Operand<i64>;
268 def offset32 : Operand<i64>;
269 def offset64 : Operand<i64>;
271 // Branch targets have OtherVT type and print as pc-relative values.
272 def brtarget : Operand<OtherVT>;
273 def brtarget8 : Operand<OtherVT>;
277 def SSECC : Operand<i8> {
278 let PrintMethod = "printSSECC";
281 class ImmSExtAsmOperandClass : AsmOperandClass {
282 let SuperClasses = [ImmAsmOperand];
283 let RenderMethod = "addImmOperands";
286 // Sign-extended immediate classes. We don't need to define the full lattice
287 // here because there is no instruction with an ambiguity between ImmSExti64i32
290 // The strange ranges come from the fact that the assembler always works with
291 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
292 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
295 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
296 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
297 let Name = "ImmSExti64i32";
300 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
301 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
302 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
303 let Name = "ImmSExti16i8";
304 let SuperClasses = [ImmSExti64i32AsmOperand];
307 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
308 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
309 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
310 let Name = "ImmSExti32i8";
314 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
315 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
316 let Name = "ImmSExti64i8";
317 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
318 ImmSExti64i32AsmOperand];
321 // A couple of more descriptive operand definitions.
322 // 16-bits but only 8 bits are significant.
323 def i16i8imm : Operand<i16> {
324 let ParserMatchClass = ImmSExti16i8AsmOperand;
326 // 32-bits but only 8 bits are significant.
327 def i32i8imm : Operand<i32> {
328 let ParserMatchClass = ImmSExti32i8AsmOperand;
331 //===----------------------------------------------------------------------===//
332 // X86 Complex Pattern Definitions.
335 // Define X86 specific addressing mode.
336 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
337 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
338 [add, sub, mul, X86mul_imm, shl, or, frameindex],
340 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
341 [tglobaltlsaddr], []>;
343 //===----------------------------------------------------------------------===//
344 // X86 Instruction Predicate Definitions.
345 def HasCMov : Predicate<"Subtarget->hasCMov()">;
346 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
348 // FIXME: temporary hack to let codegen assert or generate poor code in case
349 // no AVX version of the desired intructions is present, this is better for
350 // incremental dev (without fallbacks it's easier to spot what's missing)
351 def HasMMX : Predicate<"Subtarget->hasMMX() && !Subtarget->hasAVX()">;
352 def HasSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
353 def HasSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
354 def HasSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
355 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
356 def HasSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
357 def HasSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
358 def HasSSE4A : Predicate<"Subtarget->hasSSE4A() && !Subtarget->hasAVX()">;
360 def HasAVX : Predicate<"Subtarget->hasAVX()">;
361 def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">;
362 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
363 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
364 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
365 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
366 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
367 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
368 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
369 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
370 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
371 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
372 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
373 "TM.getCodeModel() != CodeModel::Kernel">;
374 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
375 "TM.getCodeModel() == CodeModel::Kernel">;
376 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
377 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
378 def OptForSize : Predicate<"OptForSize">;
379 def OptForSpeed : Predicate<"!OptForSize">;
380 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
381 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
382 def HasAES : Predicate<"Subtarget->hasAES()">;
384 //===----------------------------------------------------------------------===//
385 // X86 Instruction Format Definitions.
388 include "X86InstrFormats.td"
390 //===----------------------------------------------------------------------===//
391 // Pattern fragments...
394 // X86 specific condition code. These correspond to CondCode in
395 // X86InstrInfo.h. They must be kept in synch.
396 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
397 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
398 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
399 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
400 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
401 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
402 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
403 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
404 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
405 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
406 def X86_COND_NO : PatLeaf<(i8 10)>;
407 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
408 def X86_COND_NS : PatLeaf<(i8 12)>;
409 def X86_COND_O : PatLeaf<(i8 13)>;
410 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
411 def X86_COND_S : PatLeaf<(i8 15)>;
413 def immSext8 : PatLeaf<(imm), [{ return immSext8(N); }]>;
415 def i16immSExt8 : PatLeaf<(i16 immSext8)>;
416 def i32immSExt8 : PatLeaf<(i32 immSext8)>;
418 // Helper fragments for loads.
419 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
420 // known to be 32-bit aligned or better. Ditto for i8 to i16.
421 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
422 LoadSDNode *LD = cast<LoadSDNode>(N);
423 ISD::LoadExtType ExtType = LD->getExtensionType();
424 if (ExtType == ISD::NON_EXTLOAD)
426 if (ExtType == ISD::EXTLOAD)
427 return LD->getAlignment() >= 2 && !LD->isVolatile();
431 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
432 LoadSDNode *LD = cast<LoadSDNode>(N);
433 ISD::LoadExtType ExtType = LD->getExtensionType();
434 if (ExtType == ISD::EXTLOAD)
435 return LD->getAlignment() >= 2 && !LD->isVolatile();
439 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
440 LoadSDNode *LD = cast<LoadSDNode>(N);
441 ISD::LoadExtType ExtType = LD->getExtensionType();
442 if (ExtType == ISD::NON_EXTLOAD)
444 if (ExtType == ISD::EXTLOAD)
445 return LD->getAlignment() >= 4 && !LD->isVolatile();
449 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
450 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
451 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
452 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
453 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
455 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
456 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
457 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
459 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
460 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
461 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
462 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
463 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
464 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
466 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
467 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
468 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
469 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
470 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
471 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
474 // An 'and' node with a single use.
475 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
476 return N->hasOneUse();
478 // An 'srl' node with a single use.
479 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
480 return N->hasOneUse();
482 // An 'trunc' node with a single use.
483 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
484 return N->hasOneUse();
487 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
488 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
489 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
490 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
492 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
493 APInt Mask = APInt::getAllOnesValue(BitWidth);
494 APInt KnownZero0, KnownOne0;
495 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
496 APInt KnownZero1, KnownOne1;
497 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
498 return (~KnownZero0 & ~KnownZero1) == 0;
501 //===----------------------------------------------------------------------===//
502 // Instruction list...
505 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
506 // a stack adjustment and the codegen must know that they may modify the stack
507 // pointer before prolog-epilog rewriting occurs.
508 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
509 // sub / add which can clobber EFLAGS.
510 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
511 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
513 [(X86callseq_start timm:$amt)]>,
514 Requires<[In32BitMode]>;
515 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
517 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
518 Requires<[In32BitMode]>;
521 // x86-64 va_start lowering magic.
522 let usesCustomInserter = 1 in {
523 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
526 i64imm:$regsavefi, i64imm:$offset,
528 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
529 [(X86vastart_save_xmm_regs GR8:$al,
533 // Dynamic stack allocation yields _alloca call for Cygwin/Mingw targets. Calls
534 // to _alloca is needed to probe the stack when allocating more than 4k bytes in
535 // one go. Touching the stack at 4K increments is necessary to ensure that the
536 // guard pages used by the OS virtual memory manager are allocated in correct
538 // The main point of having separate instruction are extra unmodelled effects
539 // (compared to ordinary calls) like stack pointer change.
541 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
542 def MINGW_ALLOCA : I<0, Pseudo, (outs), (ins),
543 "# dynamic stack allocation",
548 let neverHasSideEffects = 1 in {
549 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
550 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
551 "nop{w}\t$zero", []>, TB, OpSize;
552 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
553 "nop{l}\t$zero", []>, TB;
557 let Uses = [EFLAGS] in {
558 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
560 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
561 [(int_x86_int (i8 3))]>;
562 def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
563 [(int_x86_int imm:$trap)]>;
564 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iretw", []>, OpSize;
565 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>;
567 // PIC base construction. This expands to code that looks like this:
570 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
571 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
574 //===----------------------------------------------------------------------===//
575 // Control Flow Instructions.
578 // Return instructions.
579 let isTerminator = 1, isReturn = 1, isBarrier = 1,
580 hasCtrlDep = 1, FPForm = SpecialFP in {
581 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
584 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
586 [(X86retflag timm:$amt)]>;
587 def LRET : I <0xCB, RawFrm, (outs), (ins),
589 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
593 // Unconditional branches.
594 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
595 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
596 "jmp\t$dst", [(br bb:$dst)]>;
597 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
601 // Conditional Branches.
602 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
603 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
604 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
605 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
606 [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
610 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
611 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
612 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
613 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
614 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
615 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
616 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
617 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
618 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
619 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
620 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
621 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
622 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
623 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
624 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
625 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
627 // jcx/jecx/jrcx instructions.
628 let isAsmParserOnly = 1, isBranch = 1, isTerminator = 1 in {
629 // These are the 32-bit versions of this instruction for the asmparser. In
630 // 32-bit mode, the address size prefix is jcxz and the unprefixed version is
633 def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
634 "jcxz\t$dst", []>, AdSize, Requires<[In32BitMode]>;
636 def JECXZ_32 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
637 "jecxz\t$dst", []>, Requires<[In32BitMode]>;
639 // J*CXZ instruction: 64-bit versions of this instruction for the asmparser.
640 // In 64-bit mode, the address size prefix is jecxz and the unprefixed version
643 def JECXZ_64 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
644 "jecxz\t$dst", []>, AdSize, Requires<[In64BitMode]>;
646 def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
647 "jrcxz\t$dst", []>, Requires<[In64BitMode]>;
652 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
653 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
654 [(brind GR32:$dst)]>, Requires<[In32BitMode]>;
655 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
656 [(brind (loadi32 addr:$dst))]>, Requires<[In32BitMode]>;
658 def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
659 (ins i16imm:$off, i16imm:$seg),
660 "ljmp{w}\t{$seg, $off|$off, $seg}", []>, OpSize;
661 def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
662 (ins i32imm:$off, i16imm:$seg),
663 "ljmp{l}\t{$seg, $off|$off, $seg}", []>;
665 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
666 "ljmp{w}\t{*}$dst", []>, OpSize;
667 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
668 "ljmp{l}\t{*}$dst", []>;
674 def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>;
675 def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>;
676 def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>;
678 //===----------------------------------------------------------------------===//
679 // Call Instructions...
682 // All calls clobber the non-callee saved registers. ESP is marked as
683 // a use to prevent stack-pointer assignments that appear immediately
684 // before calls from potentially appearing dead. Uses for argument
685 // registers are added manually.
686 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
687 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
688 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
689 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
691 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
692 (outs), (ins i32imm_pcrel:$dst,variable_ops),
693 "call{l}\t$dst", []>, Requires<[In32BitMode]>;
694 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
695 "call{l}\t{*}$dst", [(X86call GR32:$dst)]>,
696 Requires<[In32BitMode]>;
697 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
698 "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))]>,
699 Requires<[In32BitMode]>;
701 def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
702 (ins i16imm:$off, i16imm:$seg),
703 "lcall{w}\t{$seg, $off|$off, $seg}", []>, OpSize;
704 def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
705 (ins i32imm:$off, i16imm:$seg),
706 "lcall{l}\t{$seg, $off|$off, $seg}", []>;
708 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
709 "lcall{w}\t{*}$dst", []>, OpSize;
710 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
711 "lcall{l}\t{*}$dst", []>;
713 // callw for 16 bit code for the assembler.
714 let isAsmParserOnly = 1 in
715 def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
716 (outs), (ins i16imm_pcrel:$dst, variable_ops),
717 "callw\t$dst", []>, OpSize;
720 // Constructing a stack frame.
722 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
723 "enter\t$len, $lvl", []>;
727 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
729 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
730 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
731 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
732 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
734 def TCRETURNdi : I<0, Pseudo, (outs),
735 (ins i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
736 "#TC_RETURN $dst $offset", []>;
737 def TCRETURNri : I<0, Pseudo, (outs),
738 (ins GR32_TC:$dst, i32imm:$offset, variable_ops),
739 "#TC_RETURN $dst $offset", []>;
741 def TCRETURNmi : I<0, Pseudo, (outs),
742 (ins i32mem_TC:$dst, i32imm:$offset, variable_ops),
743 "#TC_RETURN $dst $offset", []>;
745 // FIXME: The should be pseudo instructions that are lowered when going to
747 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
748 (ins i32imm_pcrel:$dst, variable_ops),
749 "jmp\t$dst # TAILCALL",
751 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops),
752 "", []>; // FIXME: Remove encoding when JIT is dead.
754 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops),
755 "jmp{l}\t{*}$dst # TAILCALL", []>;
758 //===----------------------------------------------------------------------===//
759 // Miscellaneous Instructions...
761 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
762 def LEAVE : I<0xC9, RawFrm,
763 (outs), (ins), "leave", []>, Requires<[In32BitMode]>;
765 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
766 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
768 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
769 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
770 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
771 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
773 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
774 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
776 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
778 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
780 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
781 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
783 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
785 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
786 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
789 let mayStore = 1 in {
790 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
792 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
793 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
795 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
797 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
798 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
802 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
803 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
804 "push{l}\t$imm", []>;
805 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
806 "push{w}\t$imm", []>, OpSize;
807 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
808 "push{l}\t$imm", []>;
811 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
812 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
813 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
814 Requires<[In32BitMode]>;
816 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
817 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
818 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
819 Requires<[In32BitMode]>;
822 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
823 mayLoad=1, neverHasSideEffects=1 in {
824 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>,
825 Requires<[In32BitMode]>;
827 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
828 mayStore=1, neverHasSideEffects=1 in {
829 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>,
830 Requires<[In32BitMode]>;
833 let Uses = [EFLAGS], Constraints = "$src = $dst" in // GR32 = bswap GR32
834 def BSWAP32r : I<0xC8, AddRegFrm,
835 (outs GR32:$dst), (ins GR32:$src),
837 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
840 // Bit scan instructions.
841 let Defs = [EFLAGS] in {
842 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
843 "bsf{w}\t{$src, $dst|$dst, $src}",
844 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
845 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
846 "bsf{w}\t{$src, $dst|$dst, $src}",
847 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
849 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
850 "bsf{l}\t{$src, $dst|$dst, $src}",
851 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
852 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
853 "bsf{l}\t{$src, $dst|$dst, $src}",
854 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
856 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
857 "bsr{w}\t{$src, $dst|$dst, $src}",
858 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
859 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
860 "bsr{w}\t{$src, $dst|$dst, $src}",
861 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
863 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
864 "bsr{l}\t{$src, $dst|$dst, $src}",
865 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
866 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
867 "bsr{l}\t{$src, $dst|$dst, $src}",
868 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
871 let neverHasSideEffects = 1 in
872 def LEA16r : I<0x8D, MRMSrcMem,
873 (outs GR16:$dst), (ins i32mem:$src),
874 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
875 let isReMaterializable = 1 in
876 def LEA32r : I<0x8D, MRMSrcMem,
877 (outs GR32:$dst), (ins i32mem:$src),
878 "lea{l}\t{$src|$dst}, {$dst|$src}",
879 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
881 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
882 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
883 [(X86rep_movs i8)]>, REP;
884 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
885 [(X86rep_movs i16)]>, REP, OpSize;
886 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
887 [(X86rep_movs i32)]>, REP;
890 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
891 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
892 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
893 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
894 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
897 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
898 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
899 [(X86rep_stos i8)]>, REP;
900 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
901 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
902 [(X86rep_stos i16)]>, REP, OpSize;
903 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
904 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
905 [(X86rep_stos i32)]>, REP;
907 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
908 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
909 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
910 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
911 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
912 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
913 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
915 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
916 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
917 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
919 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
920 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
921 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
923 let Defs = [RAX, RDX] in
924 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
927 let Defs = [RAX, RCX, RDX] in
928 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
930 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
931 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
934 def SYSCALL : I<0x05, RawFrm,
935 (outs), (ins), "syscall", []>, TB;
936 def SYSRETL : I<0x07, RawFrm,
937 (outs), (ins), "sysretl", []>, TB;
938 def SYSENTER : I<0x34, RawFrm,
939 (outs), (ins), "sysenter", []>, TB;
940 def SYSEXIT : I<0x35, RawFrm,
941 (outs), (ins), "sysexit", []>, TB, Requires<[In32BitMode]>;
943 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
946 //===----------------------------------------------------------------------===//
947 // Input/Output Instructions...
949 let Defs = [AL], Uses = [DX] in
950 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
951 "in{b}\t{%dx, %al|%AL, %DX}", []>;
952 let Defs = [AX], Uses = [DX] in
953 def IN16rr : I<0xED, RawFrm, (outs), (ins),
954 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
955 let Defs = [EAX], Uses = [DX] in
956 def IN32rr : I<0xED, RawFrm, (outs), (ins),
957 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
960 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
961 "in{b}\t{$port, %al|%AL, $port}", []>;
963 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
964 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
966 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
967 "in{l}\t{$port, %eax|%EAX, $port}", []>;
969 let Uses = [DX, AL] in
970 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
971 "out{b}\t{%al, %dx|%DX, %AL}", []>;
972 let Uses = [DX, AX] in
973 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
974 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
975 let Uses = [DX, EAX] in
976 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
977 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
980 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
981 "out{b}\t{%al, $port|$port, %AL}", []>;
983 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
984 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
986 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
987 "out{l}\t{%eax, $port|$port, %EAX}", []>;
989 def IN8 : I<0x6C, RawFrm, (outs), (ins),
991 def IN16 : I<0x6D, RawFrm, (outs), (ins),
992 "ins{w}", []>, OpSize;
993 def IN32 : I<0x6D, RawFrm, (outs), (ins),
996 //===----------------------------------------------------------------------===//
997 // Move Instructions...
999 let neverHasSideEffects = 1 in {
1000 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1001 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1002 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1003 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1004 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1005 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1007 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1008 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1009 "mov{b}\t{$src, $dst|$dst, $src}",
1010 [(set GR8:$dst, imm:$src)]>;
1011 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1012 "mov{w}\t{$src, $dst|$dst, $src}",
1013 [(set GR16:$dst, imm:$src)]>, OpSize;
1014 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1015 "mov{l}\t{$src, $dst|$dst, $src}",
1016 [(set GR32:$dst, imm:$src)]>;
1019 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1020 "mov{b}\t{$src, $dst|$dst, $src}",
1021 [(store (i8 imm:$src), addr:$dst)]>;
1022 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1023 "mov{w}\t{$src, $dst|$dst, $src}",
1024 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
1025 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1026 "mov{l}\t{$src, $dst|$dst, $src}",
1027 [(store (i32 imm:$src), addr:$dst)]>;
1029 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
1030 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
1031 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
1032 "mov{b}\t{$src, %al|%al, $src}", []>,
1033 Requires<[In32BitMode]>;
1034 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
1035 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize,
1036 Requires<[In32BitMode]>;
1037 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1038 "mov{l}\t{$src, %eax|%eax, $src}", []>,
1039 Requires<[In32BitMode]>;
1040 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1041 "mov{b}\t{%al, $dst|$dst, %al}", []>,
1042 Requires<[In32BitMode]>;
1043 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1044 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize,
1045 Requires<[In32BitMode]>;
1046 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1047 "mov{l}\t{%eax, $dst|$dst, %eax}", []>,
1048 Requires<[In32BitMode]>;
1050 // Moves to and from segment registers
1051 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
1052 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1053 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
1054 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1055 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
1056 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1057 def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
1058 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1059 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
1060 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1061 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
1062 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1063 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
1064 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1065 def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
1066 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1068 let isCodeGenOnly = 1 in {
1069 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1070 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1071 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1072 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1073 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1074 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1077 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1078 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1079 "mov{b}\t{$src, $dst|$dst, $src}",
1080 [(set GR8:$dst, (loadi8 addr:$src))]>;
1081 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1082 "mov{w}\t{$src, $dst|$dst, $src}",
1083 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
1084 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1085 "mov{l}\t{$src, $dst|$dst, $src}",
1086 [(set GR32:$dst, (loadi32 addr:$src))]>;
1089 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1090 "mov{b}\t{$src, $dst|$dst, $src}",
1091 [(store GR8:$src, addr:$dst)]>;
1092 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1093 "mov{w}\t{$src, $dst|$dst, $src}",
1094 [(store GR16:$src, addr:$dst)]>, OpSize;
1095 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1096 "mov{l}\t{$src, $dst|$dst, $src}",
1097 [(store GR32:$src, addr:$dst)]>;
1099 /// Versions of MOV32rr, MOV32rm, and MOV32mr for i32mem_TC and GR32_TC.
1100 let isCodeGenOnly = 1 in {
1101 let neverHasSideEffects = 1 in
1102 def MOV32rr_TC : I<0x89, MRMDestReg, (outs GR32_TC:$dst), (ins GR32_TC:$src),
1103 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1106 canFoldAsLoad = 1, isReMaterializable = 1 in
1107 def MOV32rm_TC : I<0x8B, MRMSrcMem, (outs GR32_TC:$dst), (ins i32mem_TC:$src),
1108 "mov{l}\t{$src, $dst|$dst, $src}",
1112 def MOV32mr_TC : I<0x89, MRMDestMem, (outs), (ins i32mem_TC:$dst, GR32_TC:$src),
1113 "mov{l}\t{$src, $dst|$dst, $src}",
1117 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1118 // that they can be used for copying and storing h registers, which can't be
1119 // encoded when a REX prefix is present.
1120 let isCodeGenOnly = 1 in {
1121 let neverHasSideEffects = 1 in
1122 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1123 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1124 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1126 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1127 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1128 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1130 canFoldAsLoad = 1, isReMaterializable = 1 in
1131 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1132 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1133 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1136 // Moves to and from debug registers
1137 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
1138 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1139 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
1140 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1142 // Moves to and from control registers
1143 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
1144 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1145 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
1146 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1148 //===----------------------------------------------------------------------===//
1149 // Fixed-Register Multiplication and Division Instructions...
1152 // Extra precision multiplication
1154 // AL is really implied by AX, but the registers in Defs must match the
1155 // SDNode results (i8, i32).
1156 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1157 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
1158 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1159 // This probably ought to be moved to a def : Pat<> if the
1160 // syntax can be accepted.
1161 [(set AL, (mul AL, GR8:$src)),
1162 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1164 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1165 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1167 []>, OpSize; // AX,DX = AX*GR16
1169 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1170 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1172 []>; // EAX,EDX = EAX*GR32
1174 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1175 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1177 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1178 // This probably ought to be moved to a def : Pat<> if the
1179 // syntax can be accepted.
1180 [(set AL, (mul AL, (loadi8 addr:$src))),
1181 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1183 let mayLoad = 1, neverHasSideEffects = 1 in {
1184 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1185 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1187 []>, OpSize; // AX,DX = AX*[mem16]
1189 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1190 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1192 []>; // EAX,EDX = EAX*[mem32]
1195 let neverHasSideEffects = 1 in {
1196 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1197 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1199 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1200 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1201 OpSize; // AX,DX = AX*GR16
1202 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1203 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1204 // EAX,EDX = EAX*GR32
1205 let mayLoad = 1 in {
1206 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1207 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1208 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1209 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1210 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1211 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1212 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1213 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1214 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1216 } // neverHasSideEffects
1218 // unsigned division/remainder
1219 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1220 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1221 "div{b}\t$src", []>;
1222 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1223 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1224 "div{w}\t$src", []>, OpSize;
1225 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1226 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1227 "div{l}\t$src", []>;
1228 let mayLoad = 1 in {
1229 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1230 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1231 "div{b}\t$src", []>;
1232 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1233 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1234 "div{w}\t$src", []>, OpSize;
1235 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1236 // EDX:EAX/[mem32] = EAX,EDX
1237 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
1238 "div{l}\t$src", []>;
1241 // Signed division/remainder.
1242 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1243 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1244 "idiv{b}\t$src", []>;
1245 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1246 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1247 "idiv{w}\t$src", []>, OpSize;
1248 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1249 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1250 "idiv{l}\t$src", []>;
1251 let mayLoad = 1, mayLoad = 1 in {
1252 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1253 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1254 "idiv{b}\t$src", []>;
1255 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1256 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1257 "idiv{w}\t$src", []>, OpSize;
1258 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1259 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1260 // EDX:EAX/[mem32] = EAX,EDX
1261 "idiv{l}\t$src", []>;
1264 //===----------------------------------------------------------------------===//
1265 // Two address Instructions.
1267 let Constraints = "$src1 = $dst" in {
1269 // Conditional moves
1270 let Uses = [EFLAGS] in {
1272 let Predicates = [HasCMov] in {
1273 let isCommutable = 1 in {
1274 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1275 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1276 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1277 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1278 X86_COND_B, EFLAGS))]>,
1280 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1281 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1282 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1283 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1284 X86_COND_B, EFLAGS))]>,
1286 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1287 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1288 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1289 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1290 X86_COND_AE, EFLAGS))]>,
1292 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1293 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1294 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1295 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1296 X86_COND_AE, EFLAGS))]>,
1298 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1299 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1300 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1301 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1302 X86_COND_E, EFLAGS))]>,
1304 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1305 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1306 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1307 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1308 X86_COND_E, EFLAGS))]>,
1310 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1311 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1312 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1313 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1314 X86_COND_NE, EFLAGS))]>,
1316 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1317 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1318 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1319 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1320 X86_COND_NE, EFLAGS))]>,
1322 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1323 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1324 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1325 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1326 X86_COND_BE, EFLAGS))]>,
1328 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1329 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1330 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1331 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1332 X86_COND_BE, EFLAGS))]>,
1334 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1335 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1336 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1337 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1338 X86_COND_A, EFLAGS))]>,
1340 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1341 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1342 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1343 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1344 X86_COND_A, EFLAGS))]>,
1346 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1347 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1348 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1349 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1350 X86_COND_L, EFLAGS))]>,
1352 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1353 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1354 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1355 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1356 X86_COND_L, EFLAGS))]>,
1358 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1359 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1360 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1361 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1362 X86_COND_GE, EFLAGS))]>,
1364 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1365 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1366 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1367 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1368 X86_COND_GE, EFLAGS))]>,
1370 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1371 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1372 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1373 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1374 X86_COND_LE, EFLAGS))]>,
1376 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1377 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1378 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1379 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1380 X86_COND_LE, EFLAGS))]>,
1382 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1383 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1384 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1385 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1386 X86_COND_G, EFLAGS))]>,
1388 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1389 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1390 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1391 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1392 X86_COND_G, EFLAGS))]>,
1394 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1395 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1396 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1397 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1398 X86_COND_S, EFLAGS))]>,
1400 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1401 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1402 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1403 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1404 X86_COND_S, EFLAGS))]>,
1406 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1407 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1408 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1409 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1410 X86_COND_NS, EFLAGS))]>,
1412 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1413 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1414 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1415 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1416 X86_COND_NS, EFLAGS))]>,
1418 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1419 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1420 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1421 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1422 X86_COND_P, EFLAGS))]>,
1424 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1425 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1426 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1427 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1428 X86_COND_P, EFLAGS))]>,
1430 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1431 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1432 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1433 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1434 X86_COND_NP, EFLAGS))]>,
1436 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1437 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1438 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1439 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1440 X86_COND_NP, EFLAGS))]>,
1442 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1443 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1444 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1445 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1446 X86_COND_O, EFLAGS))]>,
1448 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1449 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1450 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1451 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1452 X86_COND_O, EFLAGS))]>,
1454 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1455 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1456 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1457 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1458 X86_COND_NO, EFLAGS))]>,
1460 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1461 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1462 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1463 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1464 X86_COND_NO, EFLAGS))]>,
1466 } // isCommutable = 1
1468 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1469 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1470 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1471 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1472 X86_COND_B, EFLAGS))]>,
1474 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1475 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1476 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1477 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1478 X86_COND_B, EFLAGS))]>,
1480 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1481 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1482 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1483 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1484 X86_COND_AE, EFLAGS))]>,
1486 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1487 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1488 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1489 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1490 X86_COND_AE, EFLAGS))]>,
1492 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1493 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1494 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1495 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1496 X86_COND_E, EFLAGS))]>,
1498 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1499 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1500 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1501 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1502 X86_COND_E, EFLAGS))]>,
1504 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1505 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1506 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1507 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1508 X86_COND_NE, EFLAGS))]>,
1510 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1511 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1512 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1513 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1514 X86_COND_NE, EFLAGS))]>,
1516 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1517 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1518 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1519 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1520 X86_COND_BE, EFLAGS))]>,
1522 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1523 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1524 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1525 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1526 X86_COND_BE, EFLAGS))]>,
1528 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1529 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1530 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1531 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1532 X86_COND_A, EFLAGS))]>,
1534 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1535 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1536 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1537 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1538 X86_COND_A, EFLAGS))]>,
1540 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1541 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1542 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1543 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1544 X86_COND_L, EFLAGS))]>,
1546 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1547 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1548 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1549 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1550 X86_COND_L, EFLAGS))]>,
1552 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1553 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1554 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1555 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1556 X86_COND_GE, EFLAGS))]>,
1558 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1559 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1560 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1561 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1562 X86_COND_GE, EFLAGS))]>,
1564 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1565 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1566 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1567 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1568 X86_COND_LE, EFLAGS))]>,
1570 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1571 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1572 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1573 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1574 X86_COND_LE, EFLAGS))]>,
1576 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1577 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1578 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1579 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1580 X86_COND_G, EFLAGS))]>,
1582 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1583 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1584 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1585 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1586 X86_COND_G, EFLAGS))]>,
1588 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1589 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1590 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1591 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1592 X86_COND_S, EFLAGS))]>,
1594 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1595 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1596 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1597 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1598 X86_COND_S, EFLAGS))]>,
1600 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1601 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1602 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1603 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1604 X86_COND_NS, EFLAGS))]>,
1606 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1607 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1608 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1609 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1610 X86_COND_NS, EFLAGS))]>,
1612 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1613 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1614 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1615 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1616 X86_COND_P, EFLAGS))]>,
1618 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1619 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1620 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1621 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1622 X86_COND_P, EFLAGS))]>,
1624 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1625 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1626 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1627 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1628 X86_COND_NP, EFLAGS))]>,
1630 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1631 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1632 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1633 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1634 X86_COND_NP, EFLAGS))]>,
1636 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1637 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1638 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1639 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1640 X86_COND_O, EFLAGS))]>,
1642 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1643 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1644 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1645 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1646 X86_COND_O, EFLAGS))]>,
1648 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1649 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1650 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1651 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1652 X86_COND_NO, EFLAGS))]>,
1654 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1655 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1656 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1657 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1658 X86_COND_NO, EFLAGS))]>,
1660 } // Predicates = [HasCMov]
1662 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1663 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1664 // however that requires promoting the operands, and can induce additional
1665 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1666 // clobber EFLAGS, because if one of the operands is zero, the expansion
1667 // could involve an xor.
1668 let usesCustomInserter = 1, Constraints = "", Defs = [EFLAGS] in {
1669 def CMOV_GR8 : I<0, Pseudo,
1670 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1671 "#CMOV_GR8 PSEUDO!",
1672 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1673 imm:$cond, EFLAGS))]>;
1675 let Predicates = [NoCMov] in {
1676 def CMOV_GR32 : I<0, Pseudo,
1677 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
1678 "#CMOV_GR32* PSEUDO!",
1680 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
1681 def CMOV_GR16 : I<0, Pseudo,
1682 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
1683 "#CMOV_GR16* PSEUDO!",
1685 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
1686 def CMOV_RFP32 : I<0, Pseudo,
1688 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
1689 "#CMOV_RFP32 PSEUDO!",
1691 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
1693 def CMOV_RFP64 : I<0, Pseudo,
1695 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
1696 "#CMOV_RFP64 PSEUDO!",
1698 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
1700 def CMOV_RFP80 : I<0, Pseudo,
1702 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
1703 "#CMOV_RFP80 PSEUDO!",
1705 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
1707 } // Predicates = [NoCMov]
1708 } // UsesCustomInserter = 1, Constraints = "", Defs = [EFLAGS]
1709 } // Uses = [EFLAGS]
1712 // unary instructions
1713 let CodeSize = 2 in {
1714 let Defs = [EFLAGS] in {
1715 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
1717 [(set GR8:$dst, (ineg GR8:$src1)),
1718 (implicit EFLAGS)]>;
1719 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
1721 [(set GR16:$dst, (ineg GR16:$src1)),
1722 (implicit EFLAGS)]>, OpSize;
1723 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
1725 [(set GR32:$dst, (ineg GR32:$src1)),
1726 (implicit EFLAGS)]>;
1728 let Constraints = "" in {
1729 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
1731 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1732 (implicit EFLAGS)]>;
1733 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
1735 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1736 (implicit EFLAGS)]>, OpSize;
1737 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
1739 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1740 (implicit EFLAGS)]>;
1741 } // Constraints = ""
1742 } // Defs = [EFLAGS]
1744 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1745 let AddedComplexity = 15 in {
1746 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
1748 [(set GR8:$dst, (not GR8:$src1))]>;
1749 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
1751 [(set GR16:$dst, (not GR16:$src1))]>, OpSize;
1752 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
1754 [(set GR32:$dst, (not GR32:$src1))]>;
1756 let Constraints = "" in {
1757 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
1759 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1760 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
1762 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1763 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
1765 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1766 } // Constraints = ""
1769 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1770 let Defs = [EFLAGS] in {
1772 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1774 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>;
1776 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1777 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
1779 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
1780 OpSize, Requires<[In32BitMode]>;
1781 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
1783 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
1784 Requires<[In32BitMode]>;
1786 let Constraints = "", CodeSize = 2 in {
1787 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1788 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1789 (implicit EFLAGS)]>;
1790 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1791 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1792 (implicit EFLAGS)]>,
1793 OpSize, Requires<[In32BitMode]>;
1794 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1795 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1796 (implicit EFLAGS)]>,
1797 Requires<[In32BitMode]>;
1798 } // Constraints = "", CodeSize = 2
1801 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1803 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>;
1804 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1805 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
1807 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
1808 OpSize, Requires<[In32BitMode]>;
1809 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
1811 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
1812 Requires<[In32BitMode]>;
1815 let Constraints = "", CodeSize = 2 in {
1816 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1817 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1818 (implicit EFLAGS)]>;
1819 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1820 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1821 (implicit EFLAGS)]>,
1822 OpSize, Requires<[In32BitMode]>;
1823 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1824 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1825 (implicit EFLAGS)]>,
1826 Requires<[In32BitMode]>;
1827 } // Constraints = "", CodeSize = 2
1828 } // Defs = [EFLAGS]
1830 // Logical operators...
1831 let Defs = [EFLAGS] in {
1832 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1833 def AND8rr : I<0x20, MRMDestReg,
1834 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1835 "and{b}\t{$src2, $dst|$dst, $src2}",
1836 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, GR8:$src2))]>;
1837 def AND16rr : I<0x21, MRMDestReg,
1838 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1839 "and{w}\t{$src2, $dst|$dst, $src2}",
1840 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1841 GR16:$src2))]>, OpSize;
1842 def AND32rr : I<0x21, MRMDestReg,
1843 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1844 "and{l}\t{$src2, $dst|$dst, $src2}",
1845 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1849 // AND instructions with the destination register in REG and the source register
1850 // in R/M. Included for the disassembler.
1851 let isCodeGenOnly = 1 in {
1852 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1853 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1854 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1855 (ins GR16:$src1, GR16:$src2),
1856 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1857 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1858 (ins GR32:$src1, GR32:$src2),
1859 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1862 def AND8rm : I<0x22, MRMSrcMem,
1863 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1864 "and{b}\t{$src2, $dst|$dst, $src2}",
1865 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1866 (loadi8 addr:$src2)))]>;
1867 def AND16rm : I<0x23, MRMSrcMem,
1868 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1869 "and{w}\t{$src2, $dst|$dst, $src2}",
1870 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1871 (loadi16 addr:$src2)))]>,
1873 def AND32rm : I<0x23, MRMSrcMem,
1874 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1875 "and{l}\t{$src2, $dst|$dst, $src2}",
1876 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1877 (loadi32 addr:$src2)))]>;
1879 def AND8ri : Ii8<0x80, MRM4r,
1880 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1881 "and{b}\t{$src2, $dst|$dst, $src2}",
1882 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1884 def AND16ri : Ii16<0x81, MRM4r,
1885 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1886 "and{w}\t{$src2, $dst|$dst, $src2}",
1887 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1888 imm:$src2))]>, OpSize;
1889 def AND32ri : Ii32<0x81, MRM4r,
1890 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1891 "and{l}\t{$src2, $dst|$dst, $src2}",
1892 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1894 def AND16ri8 : Ii8<0x83, MRM4r,
1895 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1896 "and{w}\t{$src2, $dst|$dst, $src2}",
1897 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1898 i16immSExt8:$src2))]>,
1900 def AND32ri8 : Ii8<0x83, MRM4r,
1901 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1902 "and{l}\t{$src2, $dst|$dst, $src2}",
1903 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1904 i32immSExt8:$src2))]>;
1906 let Constraints = "" in {
1907 def AND8mr : I<0x20, MRMDestMem,
1908 (outs), (ins i8mem :$dst, GR8 :$src),
1909 "and{b}\t{$src, $dst|$dst, $src}",
1910 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1911 (implicit EFLAGS)]>;
1912 def AND16mr : I<0x21, MRMDestMem,
1913 (outs), (ins i16mem:$dst, GR16:$src),
1914 "and{w}\t{$src, $dst|$dst, $src}",
1915 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1916 (implicit EFLAGS)]>,
1918 def AND32mr : I<0x21, MRMDestMem,
1919 (outs), (ins i32mem:$dst, GR32:$src),
1920 "and{l}\t{$src, $dst|$dst, $src}",
1921 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1922 (implicit EFLAGS)]>;
1923 def AND8mi : Ii8<0x80, MRM4m,
1924 (outs), (ins i8mem :$dst, i8imm :$src),
1925 "and{b}\t{$src, $dst|$dst, $src}",
1926 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1927 (implicit EFLAGS)]>;
1928 def AND16mi : Ii16<0x81, MRM4m,
1929 (outs), (ins i16mem:$dst, i16imm:$src),
1930 "and{w}\t{$src, $dst|$dst, $src}",
1931 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1932 (implicit EFLAGS)]>,
1934 def AND32mi : Ii32<0x81, MRM4m,
1935 (outs), (ins i32mem:$dst, i32imm:$src),
1936 "and{l}\t{$src, $dst|$dst, $src}",
1937 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1938 (implicit EFLAGS)]>;
1939 def AND16mi8 : Ii8<0x83, MRM4m,
1940 (outs), (ins i16mem:$dst, i16i8imm :$src),
1941 "and{w}\t{$src, $dst|$dst, $src}",
1942 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1943 (implicit EFLAGS)]>,
1945 def AND32mi8 : Ii8<0x83, MRM4m,
1946 (outs), (ins i32mem:$dst, i32i8imm :$src),
1947 "and{l}\t{$src, $dst|$dst, $src}",
1948 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1949 (implicit EFLAGS)]>;
1951 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1952 "and{b}\t{$src, %al|%al, $src}", []>;
1953 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1954 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1955 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1956 "and{l}\t{$src, %eax|%eax, $src}", []>;
1958 } // Constraints = ""
1961 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1962 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1963 (ins GR8 :$src1, GR8 :$src2),
1964 "or{b}\t{$src2, $dst|$dst, $src2}",
1965 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
1966 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1967 (ins GR16:$src1, GR16:$src2),
1968 "or{w}\t{$src2, $dst|$dst, $src2}",
1969 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
1971 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1972 (ins GR32:$src1, GR32:$src2),
1973 "or{l}\t{$src2, $dst|$dst, $src2}",
1974 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
1977 // OR instructions with the destination register in REG and the source register
1978 // in R/M. Included for the disassembler.
1979 let isCodeGenOnly = 1 in {
1980 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1981 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1982 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1983 (ins GR16:$src1, GR16:$src2),
1984 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1985 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1986 (ins GR32:$src1, GR32:$src2),
1987 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
1990 def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst),
1991 (ins GR8 :$src1, i8mem :$src2),
1992 "or{b}\t{$src2, $dst|$dst, $src2}",
1993 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
1994 (load addr:$src2)))]>;
1995 def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst),
1996 (ins GR16:$src1, i16mem:$src2),
1997 "or{w}\t{$src2, $dst|$dst, $src2}",
1998 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1999 (load addr:$src2)))]>,
2001 def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst),
2002 (ins GR32:$src1, i32mem:$src2),
2003 "or{l}\t{$src2, $dst|$dst, $src2}",
2004 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
2005 (load addr:$src2)))]>;
2007 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
2008 (ins GR8 :$src1, i8imm:$src2),
2009 "or{b}\t{$src2, $dst|$dst, $src2}",
2010 [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
2011 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
2012 (ins GR16:$src1, i16imm:$src2),
2013 "or{w}\t{$src2, $dst|$dst, $src2}",
2014 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
2015 imm:$src2))]>, OpSize;
2016 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
2017 (ins GR32:$src1, i32imm:$src2),
2018 "or{l}\t{$src2, $dst|$dst, $src2}",
2019 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
2022 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
2023 (ins GR16:$src1, i16i8imm:$src2),
2024 "or{w}\t{$src2, $dst|$dst, $src2}",
2025 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
2026 i16immSExt8:$src2))]>, OpSize;
2027 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
2028 (ins GR32:$src1, i32i8imm:$src2),
2029 "or{l}\t{$src2, $dst|$dst, $src2}",
2030 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
2031 i32immSExt8:$src2))]>;
2032 let Constraints = "" in {
2033 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
2034 "or{b}\t{$src, $dst|$dst, $src}",
2035 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
2036 (implicit EFLAGS)]>;
2037 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
2038 "or{w}\t{$src, $dst|$dst, $src}",
2039 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
2040 (implicit EFLAGS)]>, OpSize;
2041 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2042 "or{l}\t{$src, $dst|$dst, $src}",
2043 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
2044 (implicit EFLAGS)]>;
2045 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2046 "or{b}\t{$src, $dst|$dst, $src}",
2047 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
2048 (implicit EFLAGS)]>;
2049 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
2050 "or{w}\t{$src, $dst|$dst, $src}",
2051 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
2052 (implicit EFLAGS)]>,
2054 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
2055 "or{l}\t{$src, $dst|$dst, $src}",
2056 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
2057 (implicit EFLAGS)]>;
2058 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
2059 "or{w}\t{$src, $dst|$dst, $src}",
2060 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
2061 (implicit EFLAGS)]>,
2063 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
2064 "or{l}\t{$src, $dst|$dst, $src}",
2065 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
2066 (implicit EFLAGS)]>;
2068 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
2069 "or{b}\t{$src, %al|%al, $src}", []>;
2070 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
2071 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2072 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
2073 "or{l}\t{$src, %eax|%eax, $src}", []>;
2074 } // Constraints = ""
2077 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
2078 def XOR8rr : I<0x30, MRMDestReg,
2079 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
2080 "xor{b}\t{$src2, $dst|$dst, $src2}",
2081 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2083 def XOR16rr : I<0x31, MRMDestReg,
2084 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2085 "xor{w}\t{$src2, $dst|$dst, $src2}",
2086 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2087 GR16:$src2))]>, OpSize;
2088 def XOR32rr : I<0x31, MRMDestReg,
2089 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2090 "xor{l}\t{$src2, $dst|$dst, $src2}",
2091 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2093 } // isCommutable = 1
2095 // XOR instructions with the destination register in REG and the source register
2096 // in R/M. Included for the disassembler.
2097 let isCodeGenOnly = 1 in {
2098 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2099 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
2100 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
2101 (ins GR16:$src1, GR16:$src2),
2102 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2103 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
2104 (ins GR32:$src1, GR32:$src2),
2105 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
2108 def XOR8rm : I<0x32, MRMSrcMem,
2109 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
2110 "xor{b}\t{$src2, $dst|$dst, $src2}",
2111 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2112 (load addr:$src2)))]>;
2113 def XOR16rm : I<0x33, MRMSrcMem,
2114 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2115 "xor{w}\t{$src2, $dst|$dst, $src2}",
2116 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2117 (load addr:$src2)))]>,
2119 def XOR32rm : I<0x33, MRMSrcMem,
2120 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2121 "xor{l}\t{$src2, $dst|$dst, $src2}",
2122 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2123 (load addr:$src2)))]>;
2125 def XOR8ri : Ii8<0x80, MRM6r,
2126 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2127 "xor{b}\t{$src2, $dst|$dst, $src2}",
2128 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
2129 def XOR16ri : Ii16<0x81, MRM6r,
2130 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2131 "xor{w}\t{$src2, $dst|$dst, $src2}",
2132 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2133 imm:$src2))]>, OpSize;
2134 def XOR32ri : Ii32<0x81, MRM6r,
2135 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2136 "xor{l}\t{$src2, $dst|$dst, $src2}",
2137 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2139 def XOR16ri8 : Ii8<0x83, MRM6r,
2140 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2141 "xor{w}\t{$src2, $dst|$dst, $src2}",
2142 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2143 i16immSExt8:$src2))]>,
2145 def XOR32ri8 : Ii8<0x83, MRM6r,
2146 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2147 "xor{l}\t{$src2, $dst|$dst, $src2}",
2148 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2149 i32immSExt8:$src2))]>;
2151 let Constraints = "" in {
2152 def XOR8mr : I<0x30, MRMDestMem,
2153 (outs), (ins i8mem :$dst, GR8 :$src),
2154 "xor{b}\t{$src, $dst|$dst, $src}",
2155 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
2156 (implicit EFLAGS)]>;
2157 def XOR16mr : I<0x31, MRMDestMem,
2158 (outs), (ins i16mem:$dst, GR16:$src),
2159 "xor{w}\t{$src, $dst|$dst, $src}",
2160 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
2161 (implicit EFLAGS)]>,
2163 def XOR32mr : I<0x31, MRMDestMem,
2164 (outs), (ins i32mem:$dst, GR32:$src),
2165 "xor{l}\t{$src, $dst|$dst, $src}",
2166 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
2167 (implicit EFLAGS)]>;
2168 def XOR8mi : Ii8<0x80, MRM6m,
2169 (outs), (ins i8mem :$dst, i8imm :$src),
2170 "xor{b}\t{$src, $dst|$dst, $src}",
2171 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
2172 (implicit EFLAGS)]>;
2173 def XOR16mi : Ii16<0x81, MRM6m,
2174 (outs), (ins i16mem:$dst, i16imm:$src),
2175 "xor{w}\t{$src, $dst|$dst, $src}",
2176 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
2177 (implicit EFLAGS)]>,
2179 def XOR32mi : Ii32<0x81, MRM6m,
2180 (outs), (ins i32mem:$dst, i32imm:$src),
2181 "xor{l}\t{$src, $dst|$dst, $src}",
2182 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
2183 (implicit EFLAGS)]>;
2184 def XOR16mi8 : Ii8<0x83, MRM6m,
2185 (outs), (ins i16mem:$dst, i16i8imm :$src),
2186 "xor{w}\t{$src, $dst|$dst, $src}",
2187 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
2188 (implicit EFLAGS)]>,
2190 def XOR32mi8 : Ii8<0x83, MRM6m,
2191 (outs), (ins i32mem:$dst, i32i8imm :$src),
2192 "xor{l}\t{$src, $dst|$dst, $src}",
2193 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
2194 (implicit EFLAGS)]>;
2196 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
2197 "xor{b}\t{$src, %al|%al, $src}", []>;
2198 def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
2199 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2200 def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
2201 "xor{l}\t{$src, %eax|%eax, $src}", []>;
2202 } // Constraints = ""
2203 } // Defs = [EFLAGS]
2205 // Shift instructions
2206 let Defs = [EFLAGS] in {
2207 let Uses = [CL] in {
2208 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
2209 "shl{b}\t{%cl, $dst|$dst, CL}",
2210 [(set GR8:$dst, (shl GR8:$src1, CL))]>;
2211 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2212 "shl{w}\t{%cl, $dst|$dst, CL}",
2213 [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize;
2214 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2215 "shl{l}\t{%cl, $dst|$dst, CL}",
2216 [(set GR32:$dst, (shl GR32:$src1, CL))]>;
2219 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2220 "shl{b}\t{$src2, $dst|$dst, $src2}",
2221 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
2223 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2224 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2225 "shl{w}\t{$src2, $dst|$dst, $src2}",
2226 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2227 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2228 "shl{l}\t{$src2, $dst|$dst, $src2}",
2229 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
2231 // NOTE: We don't include patterns for shifts of a register by one, because
2232 // 'add reg,reg' is cheaper.
2234 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
2235 "shl{b}\t$dst", []>;
2236 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2237 "shl{w}\t$dst", []>, OpSize;
2238 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2239 "shl{l}\t$dst", []>;
2241 } // isConvertibleToThreeAddress = 1
2243 let Constraints = "" in {
2244 let Uses = [CL] in {
2245 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
2246 "shl{b}\t{%cl, $dst|$dst, CL}",
2247 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
2248 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
2249 "shl{w}\t{%cl, $dst|$dst, CL}",
2250 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2251 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
2252 "shl{l}\t{%cl, $dst|$dst, CL}",
2253 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
2255 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
2256 "shl{b}\t{$src, $dst|$dst, $src}",
2257 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2258 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
2259 "shl{w}\t{$src, $dst|$dst, $src}",
2260 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2262 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
2263 "shl{l}\t{$src, $dst|$dst, $src}",
2264 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2267 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
2269 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2270 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
2272 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2274 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2276 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2277 } // Constraints = ""
2279 let Uses = [CL] in {
2280 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
2281 "shr{b}\t{%cl, $dst|$dst, CL}",
2282 [(set GR8:$dst, (srl GR8:$src1, CL))]>;
2283 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2284 "shr{w}\t{%cl, $dst|$dst, CL}",
2285 [(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize;
2286 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2287 "shr{l}\t{%cl, $dst|$dst, CL}",
2288 [(set GR32:$dst, (srl GR32:$src1, CL))]>;
2291 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2292 "shr{b}\t{$src2, $dst|$dst, $src2}",
2293 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2294 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2295 "shr{w}\t{$src2, $dst|$dst, $src2}",
2296 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2297 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2298 "shr{l}\t{$src2, $dst|$dst, $src2}",
2299 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2302 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2304 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2305 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2307 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2308 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2310 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2312 let Constraints = "" in {
2313 let Uses = [CL] in {
2314 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2315 "shr{b}\t{%cl, $dst|$dst, CL}",
2316 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2317 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2318 "shr{w}\t{%cl, $dst|$dst, CL}",
2319 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2321 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2322 "shr{l}\t{%cl, $dst|$dst, CL}",
2323 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2325 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2326 "shr{b}\t{$src, $dst|$dst, $src}",
2327 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2328 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2329 "shr{w}\t{$src, $dst|$dst, $src}",
2330 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2332 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2333 "shr{l}\t{$src, $dst|$dst, $src}",
2334 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2337 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2339 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2340 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2342 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2343 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2345 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2346 } // Constraints = ""
2348 let Uses = [CL] in {
2349 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2350 "sar{b}\t{%cl, $dst|$dst, CL}",
2351 [(set GR8:$dst, (sra GR8:$src1, CL))]>;
2352 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2353 "sar{w}\t{%cl, $dst|$dst, CL}",
2354 [(set GR16:$dst, (sra GR16:$src1, CL))]>, OpSize;
2355 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2356 "sar{l}\t{%cl, $dst|$dst, CL}",
2357 [(set GR32:$dst, (sra GR32:$src1, CL))]>;
2360 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2361 "sar{b}\t{$src2, $dst|$dst, $src2}",
2362 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2363 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2364 "sar{w}\t{$src2, $dst|$dst, $src2}",
2365 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2367 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2368 "sar{l}\t{$src2, $dst|$dst, $src2}",
2369 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2372 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2374 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2375 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2377 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2378 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2380 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2382 let Constraints = "" in {
2383 let Uses = [CL] in {
2384 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2385 "sar{b}\t{%cl, $dst|$dst, CL}",
2386 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2387 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2388 "sar{w}\t{%cl, $dst|$dst, CL}",
2389 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2390 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2391 "sar{l}\t{%cl, $dst|$dst, CL}",
2392 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2394 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2395 "sar{b}\t{$src, $dst|$dst, $src}",
2396 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2397 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2398 "sar{w}\t{$src, $dst|$dst, $src}",
2399 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2401 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2402 "sar{l}\t{$src, $dst|$dst, $src}",
2403 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2406 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2408 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2409 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2411 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2413 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2415 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2416 } // Constraints = ""
2418 // Rotate instructions
2420 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
2421 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2422 let Uses = [CL] in {
2423 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
2424 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2426 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
2427 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2429 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
2430 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2431 let Uses = [CL] in {
2432 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
2433 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2435 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
2436 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2438 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
2439 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2440 let Uses = [CL] in {
2441 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
2442 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2444 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
2445 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2447 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
2448 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2449 let Uses = [CL] in {
2450 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
2451 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2453 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
2454 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2456 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
2457 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2458 let Uses = [CL] in {
2459 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
2460 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2462 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
2463 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2465 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
2466 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2467 let Uses = [CL] in {
2468 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
2469 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2471 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
2472 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2474 let Constraints = "" in {
2475 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
2476 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2477 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2478 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2479 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
2480 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2481 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2482 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2483 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
2484 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2485 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2486 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2487 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
2488 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2489 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2490 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2491 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
2492 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2493 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2494 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2495 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
2496 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2497 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2498 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2500 let Uses = [CL] in {
2501 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
2502 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2503 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
2504 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2505 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
2506 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2507 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
2508 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2509 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
2510 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2511 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
2512 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2514 } // Constraints = ""
2516 // FIXME: provide shorter instructions when imm8 == 1
2517 let Uses = [CL] in {
2518 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2519 "rol{b}\t{%cl, $dst|$dst, CL}",
2520 [(set GR8:$dst, (rotl GR8:$src1, CL))]>;
2521 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2522 "rol{w}\t{%cl, $dst|$dst, CL}",
2523 [(set GR16:$dst, (rotl GR16:$src1, CL))]>, OpSize;
2524 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2525 "rol{l}\t{%cl, $dst|$dst, CL}",
2526 [(set GR32:$dst, (rotl GR32:$src1, CL))]>;
2529 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2530 "rol{b}\t{$src2, $dst|$dst, $src2}",
2531 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2532 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2533 "rol{w}\t{$src2, $dst|$dst, $src2}",
2534 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2536 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2537 "rol{l}\t{$src2, $dst|$dst, $src2}",
2538 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2541 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2543 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2544 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2546 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2547 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2549 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2551 let Constraints = "" in {
2552 let Uses = [CL] in {
2553 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2554 "rol{b}\t{%cl, $dst|$dst, CL}",
2555 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2556 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2557 "rol{w}\t{%cl, $dst|$dst, CL}",
2558 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2559 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2560 "rol{l}\t{%cl, $dst|$dst, CL}",
2561 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2563 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2564 "rol{b}\t{$src, $dst|$dst, $src}",
2565 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2566 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2567 "rol{w}\t{$src, $dst|$dst, $src}",
2568 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2570 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2571 "rol{l}\t{$src, $dst|$dst, $src}",
2572 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2575 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2577 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2578 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2580 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2582 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2584 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2585 } // Constraints = ""
2587 let Uses = [CL] in {
2588 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2589 "ror{b}\t{%cl, $dst|$dst, CL}",
2590 [(set GR8:$dst, (rotr GR8:$src1, CL))]>;
2591 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2592 "ror{w}\t{%cl, $dst|$dst, CL}",
2593 [(set GR16:$dst, (rotr GR16:$src1, CL))]>, OpSize;
2594 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2595 "ror{l}\t{%cl, $dst|$dst, CL}",
2596 [(set GR32:$dst, (rotr GR32:$src1, CL))]>;
2599 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2600 "ror{b}\t{$src2, $dst|$dst, $src2}",
2601 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2602 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2603 "ror{w}\t{$src2, $dst|$dst, $src2}",
2604 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2606 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2607 "ror{l}\t{$src2, $dst|$dst, $src2}",
2608 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2611 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2613 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2614 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2616 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2617 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2619 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2621 let Constraints = "" in {
2622 let Uses = [CL] in {
2623 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2624 "ror{b}\t{%cl, $dst|$dst, CL}",
2625 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2626 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2627 "ror{w}\t{%cl, $dst|$dst, CL}",
2628 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2629 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2630 "ror{l}\t{%cl, $dst|$dst, CL}",
2631 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2633 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2634 "ror{b}\t{$src, $dst|$dst, $src}",
2635 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2636 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2637 "ror{w}\t{$src, $dst|$dst, $src}",
2638 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2640 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2641 "ror{l}\t{$src, $dst|$dst, $src}",
2642 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2645 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2647 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2648 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2650 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2652 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2654 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2655 } // Constraints = ""
2658 // Double shift instructions (generalizations of rotate)
2659 let Uses = [CL] in {
2660 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2661 (ins GR32:$src1, GR32:$src2),
2662 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2663 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2664 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2665 (ins GR32:$src1, GR32:$src2),
2666 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2667 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2668 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2669 (ins GR16:$src1, GR16:$src2),
2670 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2671 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2673 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2674 (ins GR16:$src1, GR16:$src2),
2675 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2676 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2680 let isCommutable = 1 in { // These instructions commute to each other.
2681 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2683 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2684 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2685 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2688 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2690 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2691 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2692 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2695 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2697 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2698 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2699 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2702 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2704 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2705 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2706 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2711 let Constraints = "" in {
2712 let Uses = [CL] in {
2713 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2714 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2715 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2717 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2718 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2719 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2722 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2723 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2724 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2725 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2726 (i8 imm:$src3)), addr:$dst)]>,
2728 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2729 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2730 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2731 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2732 (i8 imm:$src3)), addr:$dst)]>,
2735 let Uses = [CL] in {
2736 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2737 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2738 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2739 addr:$dst)]>, TB, OpSize;
2740 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2741 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2742 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2743 addr:$dst)]>, TB, OpSize;
2745 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2746 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2747 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2748 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2749 (i8 imm:$src3)), addr:$dst)]>,
2751 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2752 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2753 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2754 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2755 (i8 imm:$src3)), addr:$dst)]>,
2757 } // Constraints = ""
2758 } // Defs = [EFLAGS]
2762 let Defs = [EFLAGS] in {
2763 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2764 // Register-Register Addition
2765 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2766 (ins GR8 :$src1, GR8 :$src2),
2767 "add{b}\t{$src2, $dst|$dst, $src2}",
2768 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
2770 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2771 // Register-Register Addition
2772 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2773 (ins GR16:$src1, GR16:$src2),
2774 "add{w}\t{$src2, $dst|$dst, $src2}",
2775 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2776 GR16:$src2))]>, OpSize;
2777 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2778 (ins GR32:$src1, GR32:$src2),
2779 "add{l}\t{$src2, $dst|$dst, $src2}",
2780 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2782 } // end isConvertibleToThreeAddress
2783 } // end isCommutable
2785 // These are alternate spellings for use by the disassembler, we mark them as
2786 // code gen only to ensure they aren't matched by the assembler.
2787 let isCodeGenOnly = 1 in {
2788 def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2789 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2790 def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2791 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2792 def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR32:$dst),(ins GR32:$src1, GR32:$src2),
2793 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2796 // Register-Memory Addition
2797 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2798 (ins GR8 :$src1, i8mem :$src2),
2799 "add{b}\t{$src2, $dst|$dst, $src2}",
2800 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
2801 (load addr:$src2)))]>;
2802 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2803 (ins GR16:$src1, i16mem:$src2),
2804 "add{w}\t{$src2, $dst|$dst, $src2}",
2805 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2806 (load addr:$src2)))]>, OpSize;
2807 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2808 (ins GR32:$src1, i32mem:$src2),
2809 "add{l}\t{$src2, $dst|$dst, $src2}",
2810 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2811 (load addr:$src2)))]>;
2813 // Register-Integer Addition
2814 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2815 "add{b}\t{$src2, $dst|$dst, $src2}",
2816 [(set GR8:$dst, EFLAGS,
2817 (X86add_flag GR8:$src1, imm:$src2))]>;
2819 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2820 // Register-Integer Addition
2821 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2822 (ins GR16:$src1, i16imm:$src2),
2823 "add{w}\t{$src2, $dst|$dst, $src2}",
2824 [(set GR16:$dst, EFLAGS,
2825 (X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
2826 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2827 (ins GR32:$src1, i32imm:$src2),
2828 "add{l}\t{$src2, $dst|$dst, $src2}",
2829 [(set GR32:$dst, EFLAGS,
2830 (X86add_flag GR32:$src1, imm:$src2))]>;
2831 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2832 (ins GR16:$src1, i16i8imm:$src2),
2833 "add{w}\t{$src2, $dst|$dst, $src2}",
2834 [(set GR16:$dst, EFLAGS,
2835 (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2836 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2837 (ins GR32:$src1, i32i8imm:$src2),
2838 "add{l}\t{$src2, $dst|$dst, $src2}",
2839 [(set GR32:$dst, EFLAGS,
2840 (X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
2843 let Constraints = "" in {
2844 // Memory-Register Addition
2845 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2846 "add{b}\t{$src2, $dst|$dst, $src2}",
2847 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2848 (implicit EFLAGS)]>;
2849 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2850 "add{w}\t{$src2, $dst|$dst, $src2}",
2851 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2852 (implicit EFLAGS)]>, OpSize;
2853 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2854 "add{l}\t{$src2, $dst|$dst, $src2}",
2855 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2856 (implicit EFLAGS)]>;
2857 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2858 "add{b}\t{$src2, $dst|$dst, $src2}",
2859 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2860 (implicit EFLAGS)]>;
2861 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2862 "add{w}\t{$src2, $dst|$dst, $src2}",
2863 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2864 (implicit EFLAGS)]>, OpSize;
2865 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2866 "add{l}\t{$src2, $dst|$dst, $src2}",
2867 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2868 (implicit EFLAGS)]>;
2869 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2870 "add{w}\t{$src2, $dst|$dst, $src2}",
2871 [(store (add (load addr:$dst), i16immSExt8:$src2),
2873 (implicit EFLAGS)]>, OpSize;
2874 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2875 "add{l}\t{$src2, $dst|$dst, $src2}",
2876 [(store (add (load addr:$dst), i32immSExt8:$src2),
2878 (implicit EFLAGS)]>;
2881 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2882 "add{b}\t{$src, %al|%al, $src}", []>;
2883 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2884 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2885 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2886 "add{l}\t{$src, %eax|%eax, $src}", []>;
2887 } // Constraints = ""
2889 let Uses = [EFLAGS] in {
2890 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2891 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2892 "adc{b}\t{$src2, $dst|$dst, $src2}",
2893 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2894 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2895 (ins GR16:$src1, GR16:$src2),
2896 "adc{w}\t{$src2, $dst|$dst, $src2}",
2897 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2898 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2899 (ins GR32:$src1, GR32:$src2),
2900 "adc{l}\t{$src2, $dst|$dst, $src2}",
2901 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2904 let isCodeGenOnly = 1 in {
2905 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2906 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2907 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2908 (ins GR16:$src1, GR16:$src2),
2909 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2910 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2911 (ins GR32:$src1, GR32:$src2),
2912 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2915 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2916 (ins GR8:$src1, i8mem:$src2),
2917 "adc{b}\t{$src2, $dst|$dst, $src2}",
2918 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2919 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2920 (ins GR16:$src1, i16mem:$src2),
2921 "adc{w}\t{$src2, $dst|$dst, $src2}",
2922 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2924 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2925 (ins GR32:$src1, i32mem:$src2),
2926 "adc{l}\t{$src2, $dst|$dst, $src2}",
2927 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2928 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2929 "adc{b}\t{$src2, $dst|$dst, $src2}",
2930 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2931 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2932 (ins GR16:$src1, i16imm:$src2),
2933 "adc{w}\t{$src2, $dst|$dst, $src2}",
2934 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2935 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2936 (ins GR16:$src1, i16i8imm:$src2),
2937 "adc{w}\t{$src2, $dst|$dst, $src2}",
2938 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2940 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2941 (ins GR32:$src1, i32imm:$src2),
2942 "adc{l}\t{$src2, $dst|$dst, $src2}",
2943 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2944 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2945 (ins GR32:$src1, i32i8imm:$src2),
2946 "adc{l}\t{$src2, $dst|$dst, $src2}",
2947 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2949 let Constraints = "" in {
2950 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2951 "adc{b}\t{$src2, $dst|$dst, $src2}",
2952 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2953 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2954 "adc{w}\t{$src2, $dst|$dst, $src2}",
2955 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2957 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2958 "adc{l}\t{$src2, $dst|$dst, $src2}",
2959 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2960 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2961 "adc{b}\t{$src2, $dst|$dst, $src2}",
2962 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2963 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2964 "adc{w}\t{$src2, $dst|$dst, $src2}",
2965 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2967 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2968 "adc{w}\t{$src2, $dst|$dst, $src2}",
2969 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2971 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2972 "adc{l}\t{$src2, $dst|$dst, $src2}",
2973 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2974 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2975 "adc{l}\t{$src2, $dst|$dst, $src2}",
2976 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2978 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2979 "adc{b}\t{$src, %al|%al, $src}", []>;
2980 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2981 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2982 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2983 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2984 } // Constraints = ""
2985 } // Uses = [EFLAGS]
2987 // Register-Register Subtraction
2988 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2989 "sub{b}\t{$src2, $dst|$dst, $src2}",
2990 [(set GR8:$dst, EFLAGS,
2991 (X86sub_flag GR8:$src1, GR8:$src2))]>;
2992 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2993 "sub{w}\t{$src2, $dst|$dst, $src2}",
2994 [(set GR16:$dst, EFLAGS,
2995 (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
2996 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2997 "sub{l}\t{$src2, $dst|$dst, $src2}",
2998 [(set GR32:$dst, EFLAGS,
2999 (X86sub_flag GR32:$src1, GR32:$src2))]>;
3001 let isCodeGenOnly = 1 in {
3002 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3003 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
3004 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
3005 (ins GR16:$src1, GR16:$src2),
3006 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3007 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
3008 (ins GR32:$src1, GR32:$src2),
3009 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
3012 // Register-Memory Subtraction
3013 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
3014 (ins GR8 :$src1, i8mem :$src2),
3015 "sub{b}\t{$src2, $dst|$dst, $src2}",
3016 [(set GR8:$dst, EFLAGS,
3017 (X86sub_flag GR8:$src1, (load addr:$src2)))]>;
3018 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
3019 (ins GR16:$src1, i16mem:$src2),
3020 "sub{w}\t{$src2, $dst|$dst, $src2}",
3021 [(set GR16:$dst, EFLAGS,
3022 (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
3023 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
3024 (ins GR32:$src1, i32mem:$src2),
3025 "sub{l}\t{$src2, $dst|$dst, $src2}",
3026 [(set GR32:$dst, EFLAGS,
3027 (X86sub_flag GR32:$src1, (load addr:$src2)))]>;
3029 // Register-Integer Subtraction
3030 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
3031 (ins GR8:$src1, i8imm:$src2),
3032 "sub{b}\t{$src2, $dst|$dst, $src2}",
3033 [(set GR8:$dst, EFLAGS,
3034 (X86sub_flag GR8:$src1, imm:$src2))]>;
3035 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
3036 (ins GR16:$src1, i16imm:$src2),
3037 "sub{w}\t{$src2, $dst|$dst, $src2}",
3038 [(set GR16:$dst, EFLAGS,
3039 (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
3040 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
3041 (ins GR32:$src1, i32imm:$src2),
3042 "sub{l}\t{$src2, $dst|$dst, $src2}",
3043 [(set GR32:$dst, EFLAGS,
3044 (X86sub_flag GR32:$src1, imm:$src2))]>;
3045 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
3046 (ins GR16:$src1, i16i8imm:$src2),
3047 "sub{w}\t{$src2, $dst|$dst, $src2}",
3048 [(set GR16:$dst, EFLAGS,
3049 (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
3050 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
3051 (ins GR32:$src1, i32i8imm:$src2),
3052 "sub{l}\t{$src2, $dst|$dst, $src2}",
3053 [(set GR32:$dst, EFLAGS,
3054 (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
3056 let Constraints = "" in {
3057 // Memory-Register Subtraction
3058 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3059 "sub{b}\t{$src2, $dst|$dst, $src2}",
3060 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
3061 (implicit EFLAGS)]>;
3062 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3063 "sub{w}\t{$src2, $dst|$dst, $src2}",
3064 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
3065 (implicit EFLAGS)]>, OpSize;
3066 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3067 "sub{l}\t{$src2, $dst|$dst, $src2}",
3068 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
3069 (implicit EFLAGS)]>;
3071 // Memory-Integer Subtraction
3072 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3073 "sub{b}\t{$src2, $dst|$dst, $src2}",
3074 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
3075 (implicit EFLAGS)]>;
3076 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3077 "sub{w}\t{$src2, $dst|$dst, $src2}",
3078 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
3079 (implicit EFLAGS)]>, OpSize;
3080 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3081 "sub{l}\t{$src2, $dst|$dst, $src2}",
3082 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
3083 (implicit EFLAGS)]>;
3084 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3085 "sub{w}\t{$src2, $dst|$dst, $src2}",
3086 [(store (sub (load addr:$dst), i16immSExt8:$src2),
3088 (implicit EFLAGS)]>, OpSize;
3089 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3090 "sub{l}\t{$src2, $dst|$dst, $src2}",
3091 [(store (sub (load addr:$dst), i32immSExt8:$src2),
3093 (implicit EFLAGS)]>;
3095 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
3096 "sub{b}\t{$src, %al|%al, $src}", []>;
3097 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
3098 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3099 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
3100 "sub{l}\t{$src, %eax|%eax, $src}", []>;
3101 } // Constraints = ""
3103 let Uses = [EFLAGS] in {
3104 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
3105 (ins GR8:$src1, GR8:$src2),
3106 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3107 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
3108 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
3109 (ins GR16:$src1, GR16:$src2),
3110 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3111 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
3112 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
3113 (ins GR32:$src1, GR32:$src2),
3114 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3115 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
3117 let Constraints = "" in {
3118 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3119 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3120 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
3121 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3122 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3123 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
3125 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3126 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3127 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
3128 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
3129 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3130 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
3131 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
3132 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3133 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
3135 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3136 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3137 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
3139 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
3140 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3141 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
3142 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3143 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3144 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
3146 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
3147 "sbb{b}\t{$src, %al|%al, $src}", []>;
3148 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
3149 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3150 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
3151 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
3152 } // Constraints = ""
3154 let isCodeGenOnly = 1 in {
3155 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3156 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
3157 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
3158 (ins GR16:$src1, GR16:$src2),
3159 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3160 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
3161 (ins GR32:$src1, GR32:$src2),
3162 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
3165 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
3166 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3167 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
3168 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
3169 (ins GR16:$src1, i16mem:$src2),
3170 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3171 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
3173 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
3174 (ins GR32:$src1, i32mem:$src2),
3175 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3176 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
3177 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
3178 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3179 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
3180 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
3181 (ins GR16:$src1, i16imm:$src2),
3182 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3183 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
3184 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
3185 (ins GR16:$src1, i16i8imm:$src2),
3186 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3187 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
3189 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
3190 (ins GR32:$src1, i32imm:$src2),
3191 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3192 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
3193 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
3194 (ins GR32:$src1, i32i8imm:$src2),
3195 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3196 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
3197 } // Uses = [EFLAGS]
3198 } // Defs = [EFLAGS]
3200 let Defs = [EFLAGS] in {
3201 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
3202 // Register-Register Signed Integer Multiply
3203 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3204 "imul{w}\t{$src2, $dst|$dst, $src2}",
3205 [(set GR16:$dst, EFLAGS,
3206 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
3207 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3208 "imul{l}\t{$src2, $dst|$dst, $src2}",
3209 [(set GR32:$dst, EFLAGS,
3210 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
3213 // Register-Memory Signed Integer Multiply
3214 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
3215 (ins GR16:$src1, i16mem:$src2),
3216 "imul{w}\t{$src2, $dst|$dst, $src2}",
3217 [(set GR16:$dst, EFLAGS,
3218 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
3220 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
3221 (ins GR32:$src1, i32mem:$src2),
3222 "imul{l}\t{$src2, $dst|$dst, $src2}",
3223 [(set GR32:$dst, EFLAGS,
3224 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
3225 } // Defs = [EFLAGS]
3226 } // end Two Address instructions
3228 // Suprisingly enough, these are not two address instructions!
3229 let Defs = [EFLAGS] in {
3230 // Register-Integer Signed Integer Multiply
3231 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
3232 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
3233 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3234 [(set GR16:$dst, EFLAGS,
3235 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
3236 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
3237 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
3238 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3239 [(set GR32:$dst, EFLAGS,
3240 (X86smul_flag GR32:$src1, imm:$src2))]>;
3241 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
3242 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
3243 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3244 [(set GR16:$dst, EFLAGS,
3245 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
3247 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
3248 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
3249 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3250 [(set GR32:$dst, EFLAGS,
3251 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
3253 // Memory-Integer Signed Integer Multiply
3254 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
3255 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
3256 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3257 [(set GR16:$dst, EFLAGS,
3258 (X86smul_flag (load addr:$src1), imm:$src2))]>,
3260 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
3261 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
3262 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3263 [(set GR32:$dst, EFLAGS,
3264 (X86smul_flag (load addr:$src1), imm:$src2))]>;
3265 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
3266 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
3267 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3268 [(set GR16:$dst, EFLAGS,
3269 (X86smul_flag (load addr:$src1),
3270 i16immSExt8:$src2))]>, OpSize;
3271 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
3272 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
3273 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3274 [(set GR32:$dst, EFLAGS,
3275 (X86smul_flag (load addr:$src1),
3276 i32immSExt8:$src2))]>;
3277 } // Defs = [EFLAGS]
3279 //===----------------------------------------------------------------------===//
3280 // Test instructions are just like AND, except they don't generate a result.
3282 let Defs = [EFLAGS] in {
3283 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
3284 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3285 "test{b}\t{$src2, $src1|$src1, $src2}",
3286 [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
3287 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3288 "test{w}\t{$src2, $src1|$src1, $src2}",
3289 [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
3292 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3293 "test{l}\t{$src2, $src1|$src1, $src2}",
3294 [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
3298 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
3299 "test{b}\t{$src, %al|%al, $src}", []>;
3300 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
3301 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3302 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
3303 "test{l}\t{$src, %eax|%eax, $src}", []>;
3305 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
3306 "test{b}\t{$src2, $src1|$src1, $src2}",
3307 [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
3309 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
3310 "test{w}\t{$src2, $src1|$src1, $src2}",
3311 [(set EFLAGS, (X86cmp (and GR16:$src1,
3312 (loadi16 addr:$src2)), 0))]>, OpSize;
3313 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
3314 "test{l}\t{$src2, $src1|$src1, $src2}",
3315 [(set EFLAGS, (X86cmp (and GR32:$src1,
3316 (loadi32 addr:$src2)), 0))]>;
3318 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
3319 (outs), (ins GR8:$src1, i8imm:$src2),
3320 "test{b}\t{$src2, $src1|$src1, $src2}",
3321 [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
3322 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
3323 (outs), (ins GR16:$src1, i16imm:$src2),
3324 "test{w}\t{$src2, $src1|$src1, $src2}",
3325 [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
3327 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
3328 (outs), (ins GR32:$src1, i32imm:$src2),
3329 "test{l}\t{$src2, $src1|$src1, $src2}",
3330 [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
3332 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
3333 (outs), (ins i8mem:$src1, i8imm:$src2),
3334 "test{b}\t{$src2, $src1|$src1, $src2}",
3335 [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
3337 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3338 (outs), (ins i16mem:$src1, i16imm:$src2),
3339 "test{w}\t{$src2, $src1|$src1, $src2}",
3340 [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
3342 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3343 (outs), (ins i32mem:$src1, i32imm:$src2),
3344 "test{l}\t{$src2, $src1|$src1, $src2}",
3345 [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
3347 } // Defs = [EFLAGS]
3350 // Condition code ops, incl. set if equal/not equal/...
3351 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3352 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3353 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3354 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3356 let Uses = [EFLAGS] in {
3357 // Use sbb to materialize carry bit.
3358 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
3359 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
3360 // However, Pat<> can't replicate the destination reg into the inputs of the
3362 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
3364 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
3365 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3366 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
3367 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
3369 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
3370 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3373 def SETEr : I<0x94, MRM0r,
3374 (outs GR8 :$dst), (ins),
3376 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3378 def SETEm : I<0x94, MRM0m,
3379 (outs), (ins i8mem:$dst),
3381 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3384 def SETNEr : I<0x95, MRM0r,
3385 (outs GR8 :$dst), (ins),
3387 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3389 def SETNEm : I<0x95, MRM0m,
3390 (outs), (ins i8mem:$dst),
3392 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3395 def SETLr : I<0x9C, MRM0r,
3396 (outs GR8 :$dst), (ins),
3398 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3399 TB; // GR8 = < signed
3400 def SETLm : I<0x9C, MRM0m,
3401 (outs), (ins i8mem:$dst),
3403 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3404 TB; // [mem8] = < signed
3406 def SETGEr : I<0x9D, MRM0r,
3407 (outs GR8 :$dst), (ins),
3409 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3410 TB; // GR8 = >= signed
3411 def SETGEm : I<0x9D, MRM0m,
3412 (outs), (ins i8mem:$dst),
3414 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3415 TB; // [mem8] = >= signed
3417 def SETLEr : I<0x9E, MRM0r,
3418 (outs GR8 :$dst), (ins),
3420 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3421 TB; // GR8 = <= signed
3422 def SETLEm : I<0x9E, MRM0m,
3423 (outs), (ins i8mem:$dst),
3425 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3426 TB; // [mem8] = <= signed
3428 def SETGr : I<0x9F, MRM0r,
3429 (outs GR8 :$dst), (ins),
3431 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3432 TB; // GR8 = > signed
3433 def SETGm : I<0x9F, MRM0m,
3434 (outs), (ins i8mem:$dst),
3436 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3437 TB; // [mem8] = > signed
3439 def SETBr : I<0x92, MRM0r,
3440 (outs GR8 :$dst), (ins),
3442 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3443 TB; // GR8 = < unsign
3444 def SETBm : I<0x92, MRM0m,
3445 (outs), (ins i8mem:$dst),
3447 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3448 TB; // [mem8] = < unsign
3450 def SETAEr : I<0x93, MRM0r,
3451 (outs GR8 :$dst), (ins),
3453 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3454 TB; // GR8 = >= unsign
3455 def SETAEm : I<0x93, MRM0m,
3456 (outs), (ins i8mem:$dst),
3458 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3459 TB; // [mem8] = >= unsign
3461 def SETBEr : I<0x96, MRM0r,
3462 (outs GR8 :$dst), (ins),
3464 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3465 TB; // GR8 = <= unsign
3466 def SETBEm : I<0x96, MRM0m,
3467 (outs), (ins i8mem:$dst),
3469 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3470 TB; // [mem8] = <= unsign
3472 def SETAr : I<0x97, MRM0r,
3473 (outs GR8 :$dst), (ins),
3475 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3476 TB; // GR8 = > signed
3477 def SETAm : I<0x97, MRM0m,
3478 (outs), (ins i8mem:$dst),
3480 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3481 TB; // [mem8] = > signed
3483 def SETSr : I<0x98, MRM0r,
3484 (outs GR8 :$dst), (ins),
3486 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3487 TB; // GR8 = <sign bit>
3488 def SETSm : I<0x98, MRM0m,
3489 (outs), (ins i8mem:$dst),
3491 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3492 TB; // [mem8] = <sign bit>
3493 def SETNSr : I<0x99, MRM0r,
3494 (outs GR8 :$dst), (ins),
3496 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3497 TB; // GR8 = !<sign bit>
3498 def SETNSm : I<0x99, MRM0m,
3499 (outs), (ins i8mem:$dst),
3501 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3502 TB; // [mem8] = !<sign bit>
3504 def SETPr : I<0x9A, MRM0r,
3505 (outs GR8 :$dst), (ins),
3507 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3509 def SETPm : I<0x9A, MRM0m,
3510 (outs), (ins i8mem:$dst),
3512 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3513 TB; // [mem8] = parity
3514 def SETNPr : I<0x9B, MRM0r,
3515 (outs GR8 :$dst), (ins),
3517 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3518 TB; // GR8 = not parity
3519 def SETNPm : I<0x9B, MRM0m,
3520 (outs), (ins i8mem:$dst),
3522 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3523 TB; // [mem8] = not parity
3525 def SETOr : I<0x90, MRM0r,
3526 (outs GR8 :$dst), (ins),
3528 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3529 TB; // GR8 = overflow
3530 def SETOm : I<0x90, MRM0m,
3531 (outs), (ins i8mem:$dst),
3533 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3534 TB; // [mem8] = overflow
3535 def SETNOr : I<0x91, MRM0r,
3536 (outs GR8 :$dst), (ins),
3538 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3539 TB; // GR8 = not overflow
3540 def SETNOm : I<0x91, MRM0m,
3541 (outs), (ins i8mem:$dst),
3543 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3544 TB; // [mem8] = not overflow
3545 } // Uses = [EFLAGS]
3548 // Integer comparisons
3549 let Defs = [EFLAGS] in {
3550 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3551 "cmp{b}\t{$src, %al|%al, $src}", []>;
3552 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3553 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3554 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3555 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3557 def CMP8rr : I<0x38, MRMDestReg,
3558 (outs), (ins GR8 :$src1, GR8 :$src2),
3559 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3560 [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
3561 def CMP16rr : I<0x39, MRMDestReg,
3562 (outs), (ins GR16:$src1, GR16:$src2),
3563 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3564 [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
3565 def CMP32rr : I<0x39, MRMDestReg,
3566 (outs), (ins GR32:$src1, GR32:$src2),
3567 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3568 [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
3569 def CMP8mr : I<0x38, MRMDestMem,
3570 (outs), (ins i8mem :$src1, GR8 :$src2),
3571 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3572 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
3573 def CMP16mr : I<0x39, MRMDestMem,
3574 (outs), (ins i16mem:$src1, GR16:$src2),
3575 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3576 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
3578 def CMP32mr : I<0x39, MRMDestMem,
3579 (outs), (ins i32mem:$src1, GR32:$src2),
3580 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3581 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
3582 def CMP8rm : I<0x3A, MRMSrcMem,
3583 (outs), (ins GR8 :$src1, i8mem :$src2),
3584 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3585 [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
3586 def CMP16rm : I<0x3B, MRMSrcMem,
3587 (outs), (ins GR16:$src1, i16mem:$src2),
3588 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3589 [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
3591 def CMP32rm : I<0x3B, MRMSrcMem,
3592 (outs), (ins GR32:$src1, i32mem:$src2),
3593 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3594 [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
3596 // These are alternate spellings for use by the disassembler, we mark them as
3597 // code gen only to ensure they aren't matched by the assembler.
3598 let isCodeGenOnly = 1 in {
3599 def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3600 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3601 def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3602 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3603 def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3604 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3607 def CMP8ri : Ii8<0x80, MRM7r,
3608 (outs), (ins GR8:$src1, i8imm:$src2),
3609 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3610 [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
3611 def CMP16ri : Ii16<0x81, MRM7r,
3612 (outs), (ins GR16:$src1, i16imm:$src2),
3613 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3614 [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
3615 def CMP32ri : Ii32<0x81, MRM7r,
3616 (outs), (ins GR32:$src1, i32imm:$src2),
3617 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3618 [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
3619 def CMP8mi : Ii8 <0x80, MRM7m,
3620 (outs), (ins i8mem :$src1, i8imm :$src2),
3621 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3622 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
3623 def CMP16mi : Ii16<0x81, MRM7m,
3624 (outs), (ins i16mem:$src1, i16imm:$src2),
3625 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3626 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
3628 def CMP32mi : Ii32<0x81, MRM7m,
3629 (outs), (ins i32mem:$src1, i32imm:$src2),
3630 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3631 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
3632 def CMP16ri8 : Ii8<0x83, MRM7r,
3633 (outs), (ins GR16:$src1, i16i8imm:$src2),
3634 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3635 [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
3637 def CMP16mi8 : Ii8<0x83, MRM7m,
3638 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3639 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3640 [(set EFLAGS, (X86cmp (loadi16 addr:$src1),
3641 i16immSExt8:$src2))]>, OpSize;
3642 def CMP32mi8 : Ii8<0x83, MRM7m,
3643 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3644 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3645 [(set EFLAGS, (X86cmp (loadi32 addr:$src1),
3646 i32immSExt8:$src2))]>;
3647 def CMP32ri8 : Ii8<0x83, MRM7r,
3648 (outs), (ins GR32:$src1, i32i8imm:$src2),
3649 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3650 [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
3651 } // Defs = [EFLAGS]
3654 // TODO: BTC, BTR, and BTS
3655 let Defs = [EFLAGS] in {
3656 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3657 "bt{w}\t{$src2, $src1|$src1, $src2}",
3658 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
3659 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3660 "bt{l}\t{$src2, $src1|$src1, $src2}",
3661 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
3663 // Unlike with the register+register form, the memory+register form of the
3664 // bt instruction does not ignore the high bits of the index. From ISel's
3665 // perspective, this is pretty bizarre. Make these instructions disassembly
3668 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3669 "bt{w}\t{$src2, $src1|$src1, $src2}",
3670 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3671 // (implicit EFLAGS)]
3673 >, OpSize, TB, Requires<[FastBTMem]>;
3674 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3675 "bt{l}\t{$src2, $src1|$src1, $src2}",
3676 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3677 // (implicit EFLAGS)]
3679 >, TB, Requires<[FastBTMem]>;
3681 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3682 "bt{w}\t{$src2, $src1|$src1, $src2}",
3683 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
3685 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3686 "bt{l}\t{$src2, $src1|$src1, $src2}",
3687 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
3688 // Note that these instructions don't need FastBTMem because that
3689 // only applies when the other operand is in a register. When it's
3690 // an immediate, bt is still fast.
3691 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3692 "bt{w}\t{$src2, $src1|$src1, $src2}",
3693 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
3695 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3696 "bt{l}\t{$src2, $src1|$src1, $src2}",
3697 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
3700 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3701 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3702 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3703 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3704 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3705 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3706 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3707 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3708 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3709 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3710 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3711 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3712 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3713 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3714 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3715 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3717 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3718 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3719 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3720 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3721 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3722 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3723 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3724 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3725 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3726 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3727 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3728 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3729 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3730 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3731 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3732 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3734 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3735 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3736 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3737 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3738 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3739 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3740 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3741 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3742 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3743 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3744 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3745 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3746 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3747 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3748 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3749 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3750 } // Defs = [EFLAGS]
3752 // Sign/Zero extenders
3753 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3754 // of the register here. This has a smaller encoding and avoids a
3755 // partial-register update. Actual movsbw included for the disassembler.
3756 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3757 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3758 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3759 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3760 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3761 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3762 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3763 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3764 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3765 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3766 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3767 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3768 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3769 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3770 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3771 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3772 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3773 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3774 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3775 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3777 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3778 // of the register here. This has a smaller encoding and avoids a
3779 // partial-register update. Actual movzbw included for the disassembler.
3780 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3781 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3782 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3783 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3784 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3785 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3786 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3787 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3788 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3789 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3790 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3791 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3792 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3793 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3794 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3795 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3796 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3797 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3798 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3799 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3801 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
3802 // except that they use GR32_NOREX for the output operand register class
3803 // instead of GR32. This allows them to operate on h registers on x86-64.
3804 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3805 (outs GR32_NOREX:$dst), (ins GR8:$src),
3806 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3809 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3810 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3811 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3814 let neverHasSideEffects = 1 in {
3815 let Defs = [AX], Uses = [AL] in
3816 def CBW : I<0x98, RawFrm, (outs), (ins),
3817 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3818 let Defs = [EAX], Uses = [AX] in
3819 def CWDE : I<0x98, RawFrm, (outs), (ins),
3820 "{cwtl|cwde}", []>; // EAX = signext(AX)
3822 let Defs = [AX,DX], Uses = [AX] in
3823 def CWD : I<0x99, RawFrm, (outs), (ins),
3824 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3825 let Defs = [EAX,EDX], Uses = [EAX] in
3826 def CDQ : I<0x99, RawFrm, (outs), (ins),
3827 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3830 //===----------------------------------------------------------------------===//
3831 // Alias Instructions
3832 //===----------------------------------------------------------------------===//
3834 // Alias instructions that map movr0 to xor.
3835 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3836 // FIXME: Set encoding to pseudo.
3837 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3838 isCodeGenOnly = 1 in {
3839 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
3840 [(set GR8:$dst, 0)]>;
3842 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
3843 // encoding and avoids a partial-register update sometimes, but doing so
3844 // at isel time interferes with rematerialization in the current register
3845 // allocator. For now, this is rewritten when the instruction is lowered
3847 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3849 [(set GR16:$dst, 0)]>, OpSize;
3851 // FIXME: Set encoding to pseudo.
3852 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
3853 [(set GR32:$dst, 0)]>;
3856 //===----------------------------------------------------------------------===//
3857 // Thread Local Storage Instructions
3861 // All calls clobber the non-callee saved registers. ESP is marked as
3862 // a use to prevent stack-pointer assignments that appear immediately
3863 // before calls from potentially appearing dead.
3864 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3865 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3866 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3867 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3869 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
3870 "leal\t$sym, %eax; "
3871 "call\t___tls_get_addr@PLT",
3872 [(X86tlsaddr tls32addr:$sym)]>,
3873 Requires<[In32BitMode]>;
3875 // Darwin TLS Support
3876 // For i386, the address of the thunk is passed on the stack, on return the
3877 // address of the variable is in %eax. %ecx is trashed during the function
3878 // call. All other registers are preserved.
3879 let Defs = [EAX, ECX],
3881 usesCustomInserter = 1 in
3882 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
3884 [(X86TLSCall addr:$sym)]>,
3885 Requires<[In32BitMode]>;
3887 //===----------------------------------------------------------------------===//
3888 // EH Pseudo Instructions
3890 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3891 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3892 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3893 "ret\t#eh_return, addr: $addr",
3894 [(X86ehret GR32:$addr)]>;
3898 //===----------------------------------------------------------------------===//
3904 // TODO: Get this to fold the constant into the instruction.
3905 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
3907 "or{l}\t{$zero, $dst|$dst, $zero}",
3908 []>, Requires<[In32BitMode]>, LOCK;
3910 let hasSideEffects = 1 in {
3911 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
3913 [(X86MemBarrier)]>, Requires<[HasSSE2]>;
3916 // Atomic swap. These are just normal xchg instructions. But since a memory
3917 // operand is referenced, the atomicity is ensured.
3918 let Constraints = "$val = $dst" in {
3919 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3920 (ins GR32:$val, i32mem:$ptr),
3921 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3922 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3923 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3924 (ins GR16:$val, i16mem:$ptr),
3925 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3926 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3928 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3929 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3930 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3932 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3933 "xchg{l}\t{$val, $src|$src, $val}", []>;
3934 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3935 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3936 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3937 "xchg{b}\t{$val, $src|$src, $val}", []>;
3940 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3941 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3942 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3943 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
3945 // Atomic compare and swap.
3946 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3947 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3949 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3950 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3952 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3953 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
3956 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3959 let Defs = [AX, EFLAGS], Uses = [AX] in {
3960 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3962 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3963 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3965 let Defs = [AL, EFLAGS], Uses = [AL] in {
3966 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3968 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3969 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3972 // Atomic exchange and add
3973 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3974 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
3976 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3977 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3979 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
3981 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3982 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3984 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3986 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3987 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3991 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3992 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3993 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3994 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3995 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3996 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3998 let mayLoad = 1, mayStore = 1 in {
3999 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
4000 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
4001 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
4002 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4003 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
4004 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
4007 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
4008 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
4009 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
4010 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4011 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4012 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
4014 let mayLoad = 1, mayStore = 1 in {
4015 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
4016 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
4017 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
4018 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4019 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
4020 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
4023 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
4024 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
4025 "cmpxchg8b\t$dst", []>, TB;
4027 // Optimized codegen when the non-memory output is not used.
4028 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
4029 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1 in {
4030 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
4032 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4033 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
4035 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4036 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
4038 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4039 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
4041 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4042 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
4044 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4045 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
4047 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4048 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
4050 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4051 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
4053 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4055 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
4057 "inc{b}\t$dst", []>, LOCK;
4058 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
4060 "inc{w}\t$dst", []>, OpSize, LOCK;
4061 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
4063 "inc{l}\t$dst", []>, LOCK;
4065 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
4067 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4068 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
4070 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4071 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
4073 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4074 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
4076 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4077 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
4079 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4080 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
4082 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4083 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
4085 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4086 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
4088 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4090 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
4092 "dec{b}\t$dst", []>, LOCK;
4093 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
4095 "dec{w}\t$dst", []>, OpSize, LOCK;
4096 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
4098 "dec{l}\t$dst", []>, LOCK;
4101 // Atomic exchange, and, or, xor
4102 let Constraints = "$val = $dst", Defs = [EFLAGS],
4103 usesCustomInserter = 1 in {
4104 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4105 "#ATOMAND32 PSEUDO!",
4106 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
4107 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4108 "#ATOMOR32 PSEUDO!",
4109 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
4110 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4111 "#ATOMXOR32 PSEUDO!",
4112 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
4113 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4114 "#ATOMNAND32 PSEUDO!",
4115 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
4116 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
4117 "#ATOMMIN32 PSEUDO!",
4118 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
4119 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4120 "#ATOMMAX32 PSEUDO!",
4121 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
4122 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4123 "#ATOMUMIN32 PSEUDO!",
4124 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
4125 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4126 "#ATOMUMAX32 PSEUDO!",
4127 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
4129 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4130 "#ATOMAND16 PSEUDO!",
4131 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
4132 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4133 "#ATOMOR16 PSEUDO!",
4134 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
4135 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4136 "#ATOMXOR16 PSEUDO!",
4137 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
4138 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4139 "#ATOMNAND16 PSEUDO!",
4140 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
4141 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
4142 "#ATOMMIN16 PSEUDO!",
4143 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
4144 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4145 "#ATOMMAX16 PSEUDO!",
4146 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
4147 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4148 "#ATOMUMIN16 PSEUDO!",
4149 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
4150 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4151 "#ATOMUMAX16 PSEUDO!",
4152 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
4154 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4155 "#ATOMAND8 PSEUDO!",
4156 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
4157 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4159 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
4160 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4161 "#ATOMXOR8 PSEUDO!",
4162 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
4163 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4164 "#ATOMNAND8 PSEUDO!",
4165 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
4168 let Constraints = "$val1 = $dst1, $val2 = $dst2",
4169 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
4170 Uses = [EAX, EBX, ECX, EDX],
4171 mayLoad = 1, mayStore = 1,
4172 usesCustomInserter = 1 in {
4173 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4174 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4175 "#ATOMAND6432 PSEUDO!", []>;
4176 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4177 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4178 "#ATOMOR6432 PSEUDO!", []>;
4179 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4180 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4181 "#ATOMXOR6432 PSEUDO!", []>;
4182 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4183 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4184 "#ATOMNAND6432 PSEUDO!", []>;
4185 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4186 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4187 "#ATOMADD6432 PSEUDO!", []>;
4188 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4189 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4190 "#ATOMSUB6432 PSEUDO!", []>;
4191 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4192 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4193 "#ATOMSWAP6432 PSEUDO!", []>;
4196 // Segmentation support instructions.
4198 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4199 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4200 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4201 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4203 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
4204 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
4205 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4206 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4207 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4209 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4210 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4211 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4212 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4213 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4214 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4215 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4216 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4218 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
4220 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
4221 "str{w}\t{$dst}", []>, TB;
4222 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
4223 "str{w}\t{$dst}", []>, TB;
4224 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
4225 "ltr{w}\t{$src}", []>, TB;
4226 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
4227 "ltr{w}\t{$src}", []>, TB;
4229 def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
4230 "push{w}\t%cs", []>, Requires<[In32BitMode]>, OpSize;
4231 def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
4232 "push{l}\t%cs", []>, Requires<[In32BitMode]>;
4233 def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
4234 "push{w}\t%ss", []>, Requires<[In32BitMode]>, OpSize;
4235 def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
4236 "push{l}\t%ss", []>, Requires<[In32BitMode]>;
4237 def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
4238 "push{w}\t%ds", []>, Requires<[In32BitMode]>, OpSize;
4239 def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
4240 "push{l}\t%ds", []>, Requires<[In32BitMode]>;
4241 def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
4242 "push{w}\t%es", []>, Requires<[In32BitMode]>, OpSize;
4243 def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
4244 "push{l}\t%es", []>, Requires<[In32BitMode]>;
4246 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
4247 "push{w}\t%fs", []>, OpSize, TB;
4248 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
4249 "push{l}\t%fs", []>, TB, Requires<[In32BitMode]>;
4250 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
4251 "push{w}\t%gs", []>, OpSize, TB;
4252 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
4253 "push{l}\t%gs", []>, TB, Requires<[In32BitMode]>;
4255 // No "pop cs" instruction.
4256 def POPSS16 : I<0x17, RawFrm, (outs), (ins),
4257 "pop{w}\t%ss", []>, OpSize, Requires<[In32BitMode]>;
4258 def POPSS32 : I<0x17, RawFrm, (outs), (ins),
4259 "pop{l}\t%ss", []> , Requires<[In32BitMode]>;
4260 def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
4261 "pop{w}\t%ds", []>, OpSize, Requires<[In32BitMode]>;
4262 def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
4263 "pop{l}\t%ds", []> , Requires<[In32BitMode]>;
4264 def POPES16 : I<0x07, RawFrm, (outs), (ins),
4265 "pop{w}\t%es", []>, OpSize, Requires<[In32BitMode]>;
4266 def POPES32 : I<0x07, RawFrm, (outs), (ins),
4267 "pop{l}\t%es", []> , Requires<[In32BitMode]>;
4268 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
4269 "pop{w}\t%fs", []>, OpSize, TB;
4270 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
4271 "pop{l}\t%fs", []>, TB , Requires<[In32BitMode]>;
4272 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
4273 "pop{w}\t%gs", []>, OpSize, TB;
4274 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
4275 "pop{l}\t%gs", []>, TB , Requires<[In32BitMode]>;
4277 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4278 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4279 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4280 "lds{l}\t{$src, $dst|$dst, $src}", []>;
4281 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4282 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4283 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4284 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
4285 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4286 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4287 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4288 "les{l}\t{$src, $dst|$dst, $src}", []>;
4289 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4290 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4291 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4292 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4293 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4294 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4295 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4296 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4298 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
4299 "verr\t$seg", []>, TB;
4300 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
4301 "verr\t$seg", []>, TB;
4302 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
4303 "verw\t$seg", []>, TB;
4304 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
4305 "verw\t$seg", []>, TB;
4307 // Descriptor-table support instructions
4309 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
4310 "sgdt\t$dst", []>, TB;
4311 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
4312 "sidt\t$dst", []>, TB;
4313 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
4314 "sldt{w}\t$dst", []>, TB, OpSize;
4315 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
4316 "sldt{w}\t$dst", []>, TB;
4317 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
4318 "sldt{l}\t$dst", []>, TB;
4319 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
4320 "lgdt\t$src", []>, TB;
4321 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
4322 "lidt\t$src", []>, TB;
4323 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
4324 "lldt{w}\t$src", []>, TB;
4325 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
4326 "lldt{w}\t$src", []>, TB;
4328 // Lock instruction prefix
4329 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
4331 // Repeat string operation instruction prefixes
4332 // These uses the DF flag in the EFLAGS register to inc or dec ECX
4333 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
4334 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
4335 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
4336 // Repeat while not equal (used with CMPS and SCAS)
4337 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
4340 // Segment override instruction prefixes
4341 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
4342 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
4343 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
4344 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
4345 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
4346 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
4348 // String manipulation instructions
4350 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
4351 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
4352 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
4354 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
4355 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
4356 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
4358 // CPU flow control instructions
4360 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
4361 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
4363 // FPU control instructions
4365 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
4367 // Flag instructions
4369 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
4370 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
4371 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
4372 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
4373 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
4374 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
4375 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
4377 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
4379 // Table lookup instructions
4381 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
4383 // Specialized register support
4385 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
4386 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
4387 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
4389 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
4390 "smsw{w}\t$dst", []>, OpSize, TB;
4391 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
4392 "smsw{l}\t$dst", []>, TB;
4393 // For memory operands, there is only a 16-bit form
4394 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
4395 "smsw{w}\t$dst", []>, TB;
4397 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
4398 "lmsw{w}\t$src", []>, TB;
4399 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
4400 "lmsw{w}\t$src", []>, TB;
4402 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
4404 // Cache instructions
4406 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
4407 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
4412 def INVEPT : I<0x80, RawFrm, (outs), (ins), "invept", []>, OpSize, T8;
4414 def INVVPID : I<0x81, RawFrm, (outs), (ins), "invvpid", []>, OpSize, T8;
4416 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
4417 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4418 "vmclear\t$vmcs", []>, OpSize, TB;
4420 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
4422 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
4423 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4424 "vmptrld\t$vmcs", []>, TB;
4425 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4426 "vmptrst\t$vmcs", []>, TB;
4427 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
4428 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4429 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
4430 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4431 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
4432 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4433 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4434 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4435 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4436 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4437 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4438 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4439 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4440 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4441 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4442 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4444 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
4445 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
4446 "vmxon\t{$vmxon}", []>, XS;
4448 //===----------------------------------------------------------------------===//
4449 // Non-Instruction Patterns
4450 //===----------------------------------------------------------------------===//
4452 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
4453 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
4454 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
4455 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
4456 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
4457 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
4458 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
4460 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
4461 (ADD32ri GR32:$src1, tconstpool:$src2)>;
4462 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
4463 (ADD32ri GR32:$src1, tjumptable:$src2)>;
4464 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
4465 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
4466 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
4467 (ADD32ri GR32:$src1, texternalsym:$src2)>;
4468 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
4469 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
4471 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
4472 (MOV32mi addr:$dst, tglobaladdr:$src)>;
4473 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
4474 (MOV32mi addr:$dst, texternalsym:$src)>;
4475 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
4476 (MOV32mi addr:$dst, tblockaddress:$src)>;
4480 def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
4481 (TCRETURNri GR32_TC:$dst, imm:$off)>,
4482 Requires<[In32BitMode]>;
4484 // FIXME: This is disabled for 32-bit PIC mode because the global base
4485 // register which is part of the address mode may be assigned a
4486 // callee-saved register.
4487 def : Pat<(X86tcret (load addr:$dst), imm:$off),
4488 (TCRETURNmi addr:$dst, imm:$off)>,
4489 Requires<[In32BitMode, IsNotPIC]>;
4491 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
4492 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4493 Requires<[In32BitMode]>;
4495 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
4496 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4497 Requires<[In32BitMode]>;
4499 // Normal calls, with various flavors of addresses.
4500 def : Pat<(X86call (i32 tglobaladdr:$dst)),
4501 (CALLpcrel32 tglobaladdr:$dst)>;
4502 def : Pat<(X86call (i32 texternalsym:$dst)),
4503 (CALLpcrel32 texternalsym:$dst)>;
4504 def : Pat<(X86call (i32 imm:$dst)),
4505 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
4507 // X86 specific add which produces a flag.
4508 def : Pat<(addc GR32:$src1, GR32:$src2),
4509 (ADD32rr GR32:$src1, GR32:$src2)>;
4510 def : Pat<(addc GR32:$src1, (load addr:$src2)),
4511 (ADD32rm GR32:$src1, addr:$src2)>;
4512 def : Pat<(addc GR32:$src1, imm:$src2),
4513 (ADD32ri GR32:$src1, imm:$src2)>;
4514 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
4515 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4517 def : Pat<(subc GR32:$src1, GR32:$src2),
4518 (SUB32rr GR32:$src1, GR32:$src2)>;
4519 def : Pat<(subc GR32:$src1, (load addr:$src2)),
4520 (SUB32rm GR32:$src1, addr:$src2)>;
4521 def : Pat<(subc GR32:$src1, imm:$src2),
4522 (SUB32ri GR32:$src1, imm:$src2)>;
4523 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
4524 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4528 // TEST R,R is smaller than CMP R,0
4529 def : Pat<(X86cmp GR8:$src1, 0),
4530 (TEST8rr GR8:$src1, GR8:$src1)>;
4531 def : Pat<(X86cmp GR16:$src1, 0),
4532 (TEST16rr GR16:$src1, GR16:$src1)>;
4533 def : Pat<(X86cmp GR32:$src1, 0),
4534 (TEST32rr GR32:$src1, GR32:$src1)>;
4536 // Conditional moves with folded loads with operands swapped and conditions
4538 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
4539 (CMOVAE16rm GR16:$src2, addr:$src1)>;
4540 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
4541 (CMOVAE32rm GR32:$src2, addr:$src1)>;
4542 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
4543 (CMOVB16rm GR16:$src2, addr:$src1)>;
4544 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
4545 (CMOVB32rm GR32:$src2, addr:$src1)>;
4546 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
4547 (CMOVNE16rm GR16:$src2, addr:$src1)>;
4548 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
4549 (CMOVNE32rm GR32:$src2, addr:$src1)>;
4550 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
4551 (CMOVE16rm GR16:$src2, addr:$src1)>;
4552 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
4553 (CMOVE32rm GR32:$src2, addr:$src1)>;
4554 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
4555 (CMOVA16rm GR16:$src2, addr:$src1)>;
4556 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
4557 (CMOVA32rm GR32:$src2, addr:$src1)>;
4558 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
4559 (CMOVBE16rm GR16:$src2, addr:$src1)>;
4560 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
4561 (CMOVBE32rm GR32:$src2, addr:$src1)>;
4562 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
4563 (CMOVGE16rm GR16:$src2, addr:$src1)>;
4564 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
4565 (CMOVGE32rm GR32:$src2, addr:$src1)>;
4566 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
4567 (CMOVL16rm GR16:$src2, addr:$src1)>;
4568 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
4569 (CMOVL32rm GR32:$src2, addr:$src1)>;
4570 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
4571 (CMOVG16rm GR16:$src2, addr:$src1)>;
4572 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
4573 (CMOVG32rm GR32:$src2, addr:$src1)>;
4574 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
4575 (CMOVLE16rm GR16:$src2, addr:$src1)>;
4576 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
4577 (CMOVLE32rm GR32:$src2, addr:$src1)>;
4578 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
4579 (CMOVNP16rm GR16:$src2, addr:$src1)>;
4580 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
4581 (CMOVNP32rm GR32:$src2, addr:$src1)>;
4582 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
4583 (CMOVP16rm GR16:$src2, addr:$src1)>;
4584 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
4585 (CMOVP32rm GR32:$src2, addr:$src1)>;
4586 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
4587 (CMOVNS16rm GR16:$src2, addr:$src1)>;
4588 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
4589 (CMOVNS32rm GR32:$src2, addr:$src1)>;
4590 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
4591 (CMOVS16rm GR16:$src2, addr:$src1)>;
4592 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
4593 (CMOVS32rm GR32:$src2, addr:$src1)>;
4594 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
4595 (CMOVNO16rm GR16:$src2, addr:$src1)>;
4596 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
4597 (CMOVNO32rm GR32:$src2, addr:$src1)>;
4598 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
4599 (CMOVO16rm GR16:$src2, addr:$src1)>;
4600 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
4601 (CMOVO32rm GR32:$src2, addr:$src1)>;
4603 // zextload bool -> zextload byte
4604 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4605 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4606 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4608 // extload bool -> extload byte
4609 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4610 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4611 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4612 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
4613 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
4614 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
4616 // anyext. Define these to do an explicit zero-extend to
4617 // avoid partial-register updates.
4618 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
4619 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
4621 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
4622 def : Pat<(i32 (anyext GR16:$src)),
4623 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
4626 //===----------------------------------------------------------------------===//
4628 //===----------------------------------------------------------------------===//
4630 // Odd encoding trick: -128 fits into an 8-bit immediate field while
4631 // +128 doesn't, so in this special case use a sub instead of an add.
4632 def : Pat<(add GR16:$src1, 128),
4633 (SUB16ri8 GR16:$src1, -128)>;
4634 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
4635 (SUB16mi8 addr:$dst, -128)>;
4636 def : Pat<(add GR32:$src1, 128),
4637 (SUB32ri8 GR32:$src1, -128)>;
4638 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
4639 (SUB32mi8 addr:$dst, -128)>;
4641 // r & (2^16-1) ==> movz
4642 def : Pat<(and GR32:$src1, 0xffff),
4643 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
4644 // r & (2^8-1) ==> movz
4645 def : Pat<(and GR32:$src1, 0xff),
4646 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
4649 Requires<[In32BitMode]>;
4650 // r & (2^8-1) ==> movz
4651 def : Pat<(and GR16:$src1, 0xff),
4652 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
4655 Requires<[In32BitMode]>;
4657 // sext_inreg patterns
4658 def : Pat<(sext_inreg GR32:$src, i16),
4659 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
4660 def : Pat<(sext_inreg GR32:$src, i8),
4661 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4664 Requires<[In32BitMode]>;
4665 def : Pat<(sext_inreg GR16:$src, i8),
4666 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4669 Requires<[In32BitMode]>;
4672 def : Pat<(i16 (trunc GR32:$src)),
4673 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
4674 def : Pat<(i8 (trunc GR32:$src)),
4675 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4677 Requires<[In32BitMode]>;
4678 def : Pat<(i8 (trunc GR16:$src)),
4679 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4681 Requires<[In32BitMode]>;
4683 // h-register tricks
4684 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
4685 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4687 Requires<[In32BitMode]>;
4688 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
4689 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4691 Requires<[In32BitMode]>;
4692 def : Pat<(srl GR16:$src, (i8 8)),
4695 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4698 Requires<[In32BitMode]>;
4699 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4700 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4703 Requires<[In32BitMode]>;
4704 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4705 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4708 Requires<[In32BitMode]>;
4709 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4710 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4713 Requires<[In32BitMode]>;
4714 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
4715 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4718 Requires<[In32BitMode]>;
4720 // (shl x, 1) ==> (add x, x)
4721 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
4722 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
4723 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
4725 // (shl x (and y, 31)) ==> (shl x, y)
4726 def : Pat<(shl GR8:$src1, (and CL, 31)),
4727 (SHL8rCL GR8:$src1)>;
4728 def : Pat<(shl GR16:$src1, (and CL, 31)),
4729 (SHL16rCL GR16:$src1)>;
4730 def : Pat<(shl GR32:$src1, (and CL, 31)),
4731 (SHL32rCL GR32:$src1)>;
4732 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4733 (SHL8mCL addr:$dst)>;
4734 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4735 (SHL16mCL addr:$dst)>;
4736 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4737 (SHL32mCL addr:$dst)>;
4739 def : Pat<(srl GR8:$src1, (and CL, 31)),
4740 (SHR8rCL GR8:$src1)>;
4741 def : Pat<(srl GR16:$src1, (and CL, 31)),
4742 (SHR16rCL GR16:$src1)>;
4743 def : Pat<(srl GR32:$src1, (and CL, 31)),
4744 (SHR32rCL GR32:$src1)>;
4745 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4746 (SHR8mCL addr:$dst)>;
4747 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4748 (SHR16mCL addr:$dst)>;
4749 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4750 (SHR32mCL addr:$dst)>;
4752 def : Pat<(sra GR8:$src1, (and CL, 31)),
4753 (SAR8rCL GR8:$src1)>;
4754 def : Pat<(sra GR16:$src1, (and CL, 31)),
4755 (SAR16rCL GR16:$src1)>;
4756 def : Pat<(sra GR32:$src1, (and CL, 31)),
4757 (SAR32rCL GR32:$src1)>;
4758 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4759 (SAR8mCL addr:$dst)>;
4760 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4761 (SAR16mCL addr:$dst)>;
4762 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4763 (SAR32mCL addr:$dst)>;
4765 // (anyext (setcc_carry)) -> (setcc_carry)
4766 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4768 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4770 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
4773 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
4774 let AddedComplexity = 5 in { // Try this before the selecting to OR
4775 def : Pat<(or_is_add GR16:$src1, imm:$src2),
4776 (ADD16ri GR16:$src1, imm:$src2)>;
4777 def : Pat<(or_is_add GR32:$src1, imm:$src2),
4778 (ADD32ri GR32:$src1, imm:$src2)>;
4779 def : Pat<(or_is_add GR16:$src1, i16immSExt8:$src2),
4780 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4781 def : Pat<(or_is_add GR32:$src1, i32immSExt8:$src2),
4782 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4783 def : Pat<(or_is_add GR16:$src1, GR16:$src2),
4784 (ADD16rr GR16:$src1, GR16:$src2)>;
4785 def : Pat<(or_is_add GR32:$src1, GR32:$src2),
4786 (ADD32rr GR32:$src1, GR32:$src2)>;
4787 } // AddedComplexity
4789 //===----------------------------------------------------------------------===//
4790 // EFLAGS-defining Patterns
4791 //===----------------------------------------------------------------------===//
4794 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
4795 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
4796 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
4799 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
4800 (ADD8rm GR8:$src1, addr:$src2)>;
4801 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
4802 (ADD16rm GR16:$src1, addr:$src2)>;
4803 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
4804 (ADD32rm GR32:$src1, addr:$src2)>;
4807 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
4808 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
4809 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
4810 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
4811 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4812 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
4813 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4816 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
4817 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
4818 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
4821 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
4822 (SUB8rm GR8:$src1, addr:$src2)>;
4823 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
4824 (SUB16rm GR16:$src1, addr:$src2)>;
4825 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
4826 (SUB32rm GR32:$src1, addr:$src2)>;
4829 def : Pat<(sub GR8:$src1, imm:$src2),
4830 (SUB8ri GR8:$src1, imm:$src2)>;
4831 def : Pat<(sub GR16:$src1, imm:$src2),
4832 (SUB16ri GR16:$src1, imm:$src2)>;
4833 def : Pat<(sub GR32:$src1, imm:$src2),
4834 (SUB32ri GR32:$src1, imm:$src2)>;
4835 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
4836 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4837 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
4838 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4841 def : Pat<(mul GR16:$src1, GR16:$src2),
4842 (IMUL16rr GR16:$src1, GR16:$src2)>;
4843 def : Pat<(mul GR32:$src1, GR32:$src2),
4844 (IMUL32rr GR32:$src1, GR32:$src2)>;
4847 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
4848 (IMUL16rm GR16:$src1, addr:$src2)>;
4849 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
4850 (IMUL32rm GR32:$src1, addr:$src2)>;
4853 def : Pat<(mul GR16:$src1, imm:$src2),
4854 (IMUL16rri GR16:$src1, imm:$src2)>;
4855 def : Pat<(mul GR32:$src1, imm:$src2),
4856 (IMUL32rri GR32:$src1, imm:$src2)>;
4857 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
4858 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4859 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
4860 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4862 // reg = mul mem, imm
4863 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
4864 (IMUL16rmi addr:$src1, imm:$src2)>;
4865 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
4866 (IMUL32rmi addr:$src1, imm:$src2)>;
4867 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
4868 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4869 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
4870 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4872 // Optimize multiply by 2 with EFLAGS result.
4873 let AddedComplexity = 2 in {
4874 def : Pat<(X86smul_flag GR16:$src1, 2), (ADD16rr GR16:$src1, GR16:$src1)>;
4875 def : Pat<(X86smul_flag GR32:$src1, 2), (ADD32rr GR32:$src1, GR32:$src1)>;
4878 // Patterns for nodes that do not produce flags, for instructions that do.
4881 def : Pat<(add GR8:$src1 , 1), (INC8r GR8:$src1)>;
4882 def : Pat<(add GR16:$src1, 1), (INC16r GR16:$src1)>, Requires<[In32BitMode]>;
4883 def : Pat<(add GR32:$src1, 1), (INC32r GR32:$src1)>, Requires<[In32BitMode]>;
4886 def : Pat<(add GR8:$src1 , -1), (DEC8r GR8:$src1)>;
4887 def : Pat<(add GR16:$src1, -1), (DEC16r GR16:$src1)>, Requires<[In32BitMode]>;
4888 def : Pat<(add GR32:$src1, -1), (DEC32r GR32:$src1)>, Requires<[In32BitMode]>;
4891 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
4892 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
4893 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
4896 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
4897 (OR8rm GR8:$src1, addr:$src2)>;
4898 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
4899 (OR16rm GR16:$src1, addr:$src2)>;
4900 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
4901 (OR32rm GR32:$src1, addr:$src2)>;
4904 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
4905 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
4906 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
4907 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
4908 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4909 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
4910 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4913 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
4914 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
4915 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
4918 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
4919 (XOR8rm GR8:$src1, addr:$src2)>;
4920 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
4921 (XOR16rm GR16:$src1, addr:$src2)>;
4922 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
4923 (XOR32rm GR32:$src1, addr:$src2)>;
4926 def : Pat<(xor GR8:$src1, imm:$src2),
4927 (XOR8ri GR8:$src1, imm:$src2)>;
4928 def : Pat<(xor GR16:$src1, imm:$src2),
4929 (XOR16ri GR16:$src1, imm:$src2)>;
4930 def : Pat<(xor GR32:$src1, imm:$src2),
4931 (XOR32ri GR32:$src1, imm:$src2)>;
4932 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
4933 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4934 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
4935 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4938 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
4939 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
4940 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
4943 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
4944 (AND8rm GR8:$src1, addr:$src2)>;
4945 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
4946 (AND16rm GR16:$src1, addr:$src2)>;
4947 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
4948 (AND32rm GR32:$src1, addr:$src2)>;
4951 def : Pat<(and GR8:$src1, imm:$src2),
4952 (AND8ri GR8:$src1, imm:$src2)>;
4953 def : Pat<(and GR16:$src1, imm:$src2),
4954 (AND16ri GR16:$src1, imm:$src2)>;
4955 def : Pat<(and GR32:$src1, imm:$src2),
4956 (AND32ri GR32:$src1, imm:$src2)>;
4957 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
4958 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
4959 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
4960 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
4962 //===----------------------------------------------------------------------===//
4963 // Floating Point Stack Support
4964 //===----------------------------------------------------------------------===//
4966 include "X86InstrFPStack.td"
4968 //===----------------------------------------------------------------------===//
4970 //===----------------------------------------------------------------------===//
4972 include "X86Instr64bit.td"
4974 //===----------------------------------------------------------------------===//
4975 // SIMD support (SSE, MMX and AVX)
4976 //===----------------------------------------------------------------------===//
4978 include "X86InstrFragmentsSIMD.td"
4980 //===----------------------------------------------------------------------===//
4981 // FMA - Fused Multiply-Add support (requires FMA)
4982 //===----------------------------------------------------------------------===//
4984 include "X86InstrFMA.td"
4986 //===----------------------------------------------------------------------===//
4987 // XMM Floating point support (requires SSE / SSE2)
4988 //===----------------------------------------------------------------------===//
4990 include "X86InstrSSE.td"
4992 //===----------------------------------------------------------------------===//
4993 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
4994 //===----------------------------------------------------------------------===//
4996 include "X86InstrMMX.td"