1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
35 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
49 // RES1, RES2, FLAGS = op LHS, RHS
50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
54 SDTCisInt<0>, SDTCisVT<1, i32>]>;
55 def SDTX86BrCond : SDTypeProfile<0, 3,
56 [SDTCisVT<0, OtherVT>,
57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 def SDTX86SetCC : SDTypeProfile<1, 2,
61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
62 def SDTX86SetCC_C : SDTypeProfile<1, 2,
64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
66 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
68 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
70 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
72 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
74 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
75 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
76 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
78 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
79 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
82 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
84 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
88 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
94 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
96 def SDTX86Void : SDTypeProfile<0, 0, []>;
98 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
100 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
102 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
104 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
106 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
108 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
110 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
112 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
114 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
116 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
117 [SDNPHasChain,SDNPSideEffect]>;
118 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
120 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
122 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
126 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
127 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
128 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
129 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
131 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
132 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
134 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
135 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
137 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
138 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
140 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
142 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
143 [SDNPHasChain, SDNPSideEffect]>;
145 def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand,
146 [SDNPHasChain, SDNPSideEffect]>;
148 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
149 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
150 SDNPMayLoad, SDNPMemOperand]>;
151 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
152 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
153 SDNPMayLoad, SDNPMemOperand]>;
154 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
155 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
156 SDNPMayLoad, SDNPMemOperand]>;
158 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
159 [SDNPHasChain, SDNPMayStore,
160 SDNPMayLoad, SDNPMemOperand]>;
161 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
162 [SDNPHasChain, SDNPMayStore,
163 SDNPMayLoad, SDNPMemOperand]>;
164 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
165 [SDNPHasChain, SDNPMayStore,
166 SDNPMayLoad, SDNPMemOperand]>;
167 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
168 [SDNPHasChain, SDNPMayStore,
169 SDNPMayLoad, SDNPMemOperand]>;
170 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
171 [SDNPHasChain, SDNPMayStore,
172 SDNPMayLoad, SDNPMemOperand]>;
173 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
174 [SDNPHasChain, SDNPMayStore,
175 SDNPMayLoad, SDNPMemOperand]>;
176 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
177 [SDNPHasChain, SDNPMayStore,
178 SDNPMayLoad, SDNPMemOperand]>;
179 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
180 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
182 def X86vastart_save_xmm_regs :
183 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
184 SDT_X86VASTART_SAVE_XMM_REGS,
185 [SDNPHasChain, SDNPVariadic]>;
187 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
188 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
190 def X86callseq_start :
191 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
192 [SDNPHasChain, SDNPOutGlue]>;
194 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
195 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
197 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
198 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
201 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
202 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
203 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
204 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
207 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
208 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
210 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
211 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
213 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
214 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
216 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
217 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
219 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
222 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
223 SDTypeProfile<1, 1, [SDTCisInt<0>,
225 [SDNPHasChain, SDNPSideEffect]>;
226 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
227 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
228 [SDNPHasChain, SDNPSideEffect]>;
230 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
231 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
233 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
235 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
236 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
238 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
240 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
241 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
243 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
244 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
245 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
247 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
249 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
251 def X86andn_flag : SDNode<"X86ISD::ANDN", SDTBinaryArithWithFlags>;
253 def X86blsi : SDNode<"X86ISD::BLSI", SDTIntUnaryOp>;
254 def X86blsmsk : SDNode<"X86ISD::BLSMSK", SDTIntUnaryOp>;
255 def X86blsr : SDNode<"X86ISD::BLSR", SDTIntUnaryOp>;
257 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
259 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
260 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
262 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
265 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
266 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
268 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL,
269 [SDNPHasChain, SDNPOutGlue]>;
271 //===----------------------------------------------------------------------===//
272 // X86 Operand Definitions.
275 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
276 // the index operand of an address, to conform to x86 encoding restrictions.
277 def ptr_rc_nosp : PointerLikeRegClass<1>;
279 // *mem - Operand definitions for the funky X86 addressing mode operands.
281 def X86MemAsmOperand : AsmOperandClass {
282 let Name = "Mem"; let PredicateMethod = "isMem";
284 def X86Mem8AsmOperand : AsmOperandClass {
285 let Name = "Mem8"; let PredicateMethod = "isMem8";
287 def X86Mem16AsmOperand : AsmOperandClass {
288 let Name = "Mem16"; let PredicateMethod = "isMem16";
290 def X86Mem32AsmOperand : AsmOperandClass {
291 let Name = "Mem32"; let PredicateMethod = "isMem32";
293 def X86Mem64AsmOperand : AsmOperandClass {
294 let Name = "Mem64"; let PredicateMethod = "isMem64";
296 def X86Mem80AsmOperand : AsmOperandClass {
297 let Name = "Mem80"; let PredicateMethod = "isMem80";
299 def X86Mem128AsmOperand : AsmOperandClass {
300 let Name = "Mem128"; let PredicateMethod = "isMem128";
302 def X86Mem256AsmOperand : AsmOperandClass {
303 let Name = "Mem256"; let PredicateMethod = "isMem256";
306 // Gather mem operands
307 def X86MemVX32Operand : AsmOperandClass {
308 let Name = "MemVX32"; let PredicateMethod = "isMemVX32";
310 def X86MemVY32Operand : AsmOperandClass {
311 let Name = "MemVY32"; let PredicateMethod = "isMemVY32";
313 def X86MemVX64Operand : AsmOperandClass {
314 let Name = "MemVX64"; let PredicateMethod = "isMemVX64";
316 def X86MemVY64Operand : AsmOperandClass {
317 let Name = "MemVY64"; let PredicateMethod = "isMemVY64";
320 def X86AbsMemAsmOperand : AsmOperandClass {
322 let SuperClasses = [X86MemAsmOperand];
324 class X86MemOperand<string printMethod> : Operand<iPTR> {
325 let PrintMethod = printMethod;
326 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
327 let ParserMatchClass = X86MemAsmOperand;
330 let OperandType = "OPERAND_MEMORY" in {
331 def opaque32mem : X86MemOperand<"printopaquemem">;
332 def opaque48mem : X86MemOperand<"printopaquemem">;
333 def opaque80mem : X86MemOperand<"printopaquemem">;
334 def opaque512mem : X86MemOperand<"printopaquemem">;
336 def i8mem : X86MemOperand<"printi8mem"> {
337 let ParserMatchClass = X86Mem8AsmOperand; }
338 def i16mem : X86MemOperand<"printi16mem"> {
339 let ParserMatchClass = X86Mem16AsmOperand; }
340 def i32mem : X86MemOperand<"printi32mem"> {
341 let ParserMatchClass = X86Mem32AsmOperand; }
342 def i64mem : X86MemOperand<"printi64mem"> {
343 let ParserMatchClass = X86Mem64AsmOperand; }
344 def i128mem : X86MemOperand<"printi128mem"> {
345 let ParserMatchClass = X86Mem128AsmOperand; }
346 def i256mem : X86MemOperand<"printi256mem"> {
347 let ParserMatchClass = X86Mem256AsmOperand; }
348 def f32mem : X86MemOperand<"printf32mem"> {
349 let ParserMatchClass = X86Mem32AsmOperand; }
350 def f64mem : X86MemOperand<"printf64mem"> {
351 let ParserMatchClass = X86Mem64AsmOperand; }
352 def f80mem : X86MemOperand<"printf80mem"> {
353 let ParserMatchClass = X86Mem80AsmOperand; }
354 def f128mem : X86MemOperand<"printf128mem"> {
355 let ParserMatchClass = X86Mem128AsmOperand; }
356 def f256mem : X86MemOperand<"printf256mem">{
357 let ParserMatchClass = X86Mem256AsmOperand; }
359 // Gather mem operands
360 def vx32mem : X86MemOperand<"printi32mem">{
361 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
362 let ParserMatchClass = X86MemVX32Operand; }
363 def vy32mem : X86MemOperand<"printi32mem">{
364 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
365 let ParserMatchClass = X86MemVY32Operand; }
366 def vx64mem : X86MemOperand<"printi64mem">{
367 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
368 let ParserMatchClass = X86MemVX64Operand; }
369 def vy64mem : X86MemOperand<"printi64mem">{
370 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
371 let ParserMatchClass = X86MemVY64Operand; }
374 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
375 // plain GR64, so that it doesn't potentially require a REX prefix.
376 def i8mem_NOREX : Operand<i64> {
377 let PrintMethod = "printi8mem";
378 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
379 let ParserMatchClass = X86Mem8AsmOperand;
380 let OperandType = "OPERAND_MEMORY";
383 // GPRs available for tailcall.
384 // It represents GR32_TC, GR64_TC or GR64_TCW64.
385 def ptr_rc_tailcall : PointerLikeRegClass<2>;
387 // Special i32mem for addresses of load folding tail calls. These are not
388 // allowed to use callee-saved registers since they must be scheduled
389 // after callee-saved register are popped.
390 def i32mem_TC : Operand<i32> {
391 let PrintMethod = "printi32mem";
392 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
394 let ParserMatchClass = X86Mem32AsmOperand;
395 let OperandType = "OPERAND_MEMORY";
398 // Special i64mem for addresses of load folding tail calls. These are not
399 // allowed to use callee-saved registers since they must be scheduled
400 // after callee-saved register are popped.
401 def i64mem_TC : Operand<i64> {
402 let PrintMethod = "printi64mem";
403 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
404 ptr_rc_tailcall, i32imm, i8imm);
405 let ParserMatchClass = X86Mem64AsmOperand;
406 let OperandType = "OPERAND_MEMORY";
409 let OperandType = "OPERAND_PCREL",
410 ParserMatchClass = X86AbsMemAsmOperand,
411 PrintMethod = "printPCRelImm" in {
412 def i32imm_pcrel : Operand<i32>;
413 def i16imm_pcrel : Operand<i16>;
415 def offset8 : Operand<i64>;
416 def offset16 : Operand<i64>;
417 def offset32 : Operand<i64>;
418 def offset64 : Operand<i64>;
420 // Branch targets have OtherVT type and print as pc-relative values.
421 def brtarget : Operand<OtherVT>;
422 def brtarget8 : Operand<OtherVT>;
426 def SSECC : Operand<i8> {
427 let PrintMethod = "printSSECC";
428 let OperandType = "OPERAND_IMMEDIATE";
431 def AVXCC : Operand<i8> {
432 let PrintMethod = "printAVXCC";
433 let OperandType = "OPERAND_IMMEDIATE";
436 class ImmSExtAsmOperandClass : AsmOperandClass {
437 let SuperClasses = [ImmAsmOperand];
438 let RenderMethod = "addImmOperands";
441 class ImmZExtAsmOperandClass : AsmOperandClass {
442 let SuperClasses = [ImmAsmOperand];
443 let RenderMethod = "addImmOperands";
446 // Sign-extended immediate classes. We don't need to define the full lattice
447 // here because there is no instruction with an ambiguity between ImmSExti64i32
450 // The strange ranges come from the fact that the assembler always works with
451 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
452 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
455 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
456 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
457 let Name = "ImmSExti64i32";
460 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
461 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
462 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
463 let Name = "ImmSExti16i8";
464 let SuperClasses = [ImmSExti64i32AsmOperand];
467 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
468 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
469 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
470 let Name = "ImmSExti32i8";
474 def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass {
475 let Name = "ImmZExtu32u8";
480 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
481 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
482 let Name = "ImmSExti64i8";
483 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
484 ImmSExti64i32AsmOperand];
487 // A couple of more descriptive operand definitions.
488 // 16-bits but only 8 bits are significant.
489 def i16i8imm : Operand<i16> {
490 let ParserMatchClass = ImmSExti16i8AsmOperand;
491 let OperandType = "OPERAND_IMMEDIATE";
493 // 32-bits but only 8 bits are significant.
494 def i32i8imm : Operand<i32> {
495 let ParserMatchClass = ImmSExti32i8AsmOperand;
496 let OperandType = "OPERAND_IMMEDIATE";
498 // 32-bits but only 8 bits are significant, and those 8 bits are unsigned.
499 def u32u8imm : Operand<i32> {
500 let ParserMatchClass = ImmZExtu32u8AsmOperand;
501 let OperandType = "OPERAND_IMMEDIATE";
504 // 64-bits but only 32 bits are significant.
505 def i64i32imm : Operand<i64> {
506 let ParserMatchClass = ImmSExti64i32AsmOperand;
507 let OperandType = "OPERAND_IMMEDIATE";
510 // 64-bits but only 32 bits are significant, and those bits are treated as being
512 def i64i32imm_pcrel : Operand<i64> {
513 let PrintMethod = "printPCRelImm";
514 let ParserMatchClass = X86AbsMemAsmOperand;
515 let OperandType = "OPERAND_PCREL";
518 // 64-bits but only 8 bits are significant.
519 def i64i8imm : Operand<i64> {
520 let ParserMatchClass = ImmSExti64i8AsmOperand;
521 let OperandType = "OPERAND_IMMEDIATE";
524 def lea64_32mem : Operand<i32> {
525 let PrintMethod = "printi32mem";
526 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
527 let ParserMatchClass = X86MemAsmOperand;
530 // Memory operands that use 64-bit pointers in both ILP32 and LP64.
531 def lea64mem : Operand<i64> {
532 let PrintMethod = "printi64mem";
533 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
534 let ParserMatchClass = X86MemAsmOperand;
538 //===----------------------------------------------------------------------===//
539 // X86 Complex Pattern Definitions.
542 // Define X86 specific addressing mode.
543 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
544 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
545 [add, sub, mul, X86mul_imm, shl, or, frameindex],
547 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
548 def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr",
549 [add, sub, mul, X86mul_imm, shl, or,
550 frameindex, X86WrapperRIP],
553 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
554 [tglobaltlsaddr], []>;
556 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
557 [tglobaltlsaddr], []>;
559 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
560 [add, sub, mul, X86mul_imm, shl, or, frameindex,
563 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
564 [tglobaltlsaddr], []>;
566 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
567 [tglobaltlsaddr], []>;
569 //===----------------------------------------------------------------------===//
570 // X86 Instruction Predicate Definitions.
571 def HasCMov : Predicate<"Subtarget->hasCMov()">;
572 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
574 def HasMMX : Predicate<"Subtarget->hasMMX()">;
575 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
576 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
577 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
578 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
579 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
580 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
581 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
582 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
583 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
584 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
585 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
586 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
587 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
588 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
589 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
590 def HasAVX : Predicate<"Subtarget->hasAVX()">;
591 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
592 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
594 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
595 def HasAES : Predicate<"Subtarget->hasAES()">;
596 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
597 def HasFMA : Predicate<"Subtarget->hasFMA()">;
598 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
599 def HasXOP : Predicate<"Subtarget->hasXOP()">;
600 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
601 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
602 def HasF16C : Predicate<"Subtarget->hasF16C()">;
603 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
604 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
605 def HasBMI : Predicate<"Subtarget->hasBMI()">;
606 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
607 def HasRTM : Predicate<"Subtarget->hasRTM()">;
608 def HasHLE : Predicate<"Subtarget->hasHLE()">;
609 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
610 def HasADX : Predicate<"Subtarget->hasADX()">;
611 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
612 def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
613 def HasPrefetchW : Predicate<"Subtarget->has3DNow() || Subtarget->hasPRFCHW()">;
614 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
615 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
616 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
617 def In32BitMode : Predicate<"!Subtarget->is64Bit()">,
618 AssemblerPredicate<"!Mode64Bit", "32-bit mode">;
619 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
620 AssemblerPredicate<"Mode64Bit", "64-bit mode">;
621 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
622 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
623 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
624 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
625 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
626 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
627 "TM.getCodeModel() != CodeModel::Kernel">;
628 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
629 "TM.getCodeModel() == CodeModel::Kernel">;
630 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
631 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
632 def OptForSize : Predicate<"OptForSize">;
633 def OptForSpeed : Predicate<"!OptForSize">;
634 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
635 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
636 def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">;
638 //===----------------------------------------------------------------------===//
639 // X86 Instruction Format Definitions.
642 include "X86InstrFormats.td"
644 //===----------------------------------------------------------------------===//
645 // Pattern fragments.
648 // X86 specific condition code. These correspond to CondCode in
649 // X86InstrInfo.h. They must be kept in synch.
650 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
651 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
652 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
653 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
654 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
655 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
656 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
657 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
658 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
659 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
660 def X86_COND_NO : PatLeaf<(i8 10)>;
661 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
662 def X86_COND_NS : PatLeaf<(i8 12)>;
663 def X86_COND_O : PatLeaf<(i8 13)>;
664 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
665 def X86_COND_S : PatLeaf<(i8 15)>;
667 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
668 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
669 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
670 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
673 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
676 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
678 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
680 def i64immZExt32SExt8 : ImmLeaf<i64, [{
681 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
684 // Helper fragments for loads.
685 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
686 // known to be 32-bit aligned or better. Ditto for i8 to i16.
687 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
688 LoadSDNode *LD = cast<LoadSDNode>(N);
689 ISD::LoadExtType ExtType = LD->getExtensionType();
690 if (ExtType == ISD::NON_EXTLOAD)
692 if (ExtType == ISD::EXTLOAD)
693 return LD->getAlignment() >= 2 && !LD->isVolatile();
697 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
698 LoadSDNode *LD = cast<LoadSDNode>(N);
699 ISD::LoadExtType ExtType = LD->getExtensionType();
700 if (ExtType == ISD::EXTLOAD)
701 return LD->getAlignment() >= 2 && !LD->isVolatile();
705 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
706 LoadSDNode *LD = cast<LoadSDNode>(N);
707 ISD::LoadExtType ExtType = LD->getExtensionType();
708 if (ExtType == ISD::NON_EXTLOAD)
710 if (ExtType == ISD::EXTLOAD)
711 return LD->getAlignment() >= 4 && !LD->isVolatile();
715 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
716 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
717 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
718 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
719 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
721 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
722 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
723 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
724 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
725 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
726 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
728 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
729 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
730 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
731 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
732 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
733 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
734 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
735 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
736 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
737 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
739 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
740 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
741 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
742 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
743 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
744 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
745 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
746 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
747 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
748 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
751 // An 'and' node with a single use.
752 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
753 return N->hasOneUse();
755 // An 'srl' node with a single use.
756 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
757 return N->hasOneUse();
759 // An 'trunc' node with a single use.
760 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
761 return N->hasOneUse();
764 //===----------------------------------------------------------------------===//
769 let neverHasSideEffects = 1, SchedRW = [WriteZero] in {
770 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
771 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
772 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize;
773 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
774 "nop{l}\t$zero", [], IIC_NOP>, TB;
778 // Constructing a stack frame.
779 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
780 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
782 let SchedRW = [WriteALU] in {
783 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
784 def LEAVE : I<0xC9, RawFrm,
785 (outs), (ins), "leave", [], IIC_LEAVE>,
786 Requires<[In32BitMode]>;
788 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
789 def LEAVE64 : I<0xC9, RawFrm,
790 (outs), (ins), "leave", [], IIC_LEAVE>,
791 Requires<[In64BitMode]>;
794 //===----------------------------------------------------------------------===//
795 // Miscellaneous Instructions.
798 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
799 let mayLoad = 1, SchedRW = [WriteLoad] in {
800 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
801 IIC_POP_REG16>, OpSize;
802 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
804 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
805 IIC_POP_REG>, OpSize;
806 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
807 IIC_POP_MEM>, OpSize;
808 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
810 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
813 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, OpSize;
814 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
815 Requires<[In32BitMode]>;
816 } // mayLoad, SchedRW
818 let mayStore = 1, SchedRW = [WriteStore] in {
819 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
820 IIC_PUSH_REG>, OpSize;
821 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
823 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
824 IIC_PUSH_REG>, OpSize;
825 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
828 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
830 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
833 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
834 "push{l}\t$imm", [], IIC_PUSH_IMM>;
835 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
836 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize;
837 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
838 "push{l}\t$imm", [], IIC_PUSH_IMM>;
840 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
842 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
843 Requires<[In32BitMode]>;
845 } // mayStore, SchedRW
848 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
849 let mayLoad = 1, SchedRW = [WriteLoad] in {
850 def POP64r : I<0x58, AddRegFrm,
851 (outs GR64:$reg), (ins), "pop{q}\t$reg", [], IIC_POP_REG>;
852 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
854 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [],
856 } // mayLoad, SchedRW
857 let mayStore = 1, SchedRW = [WriteStore] in {
858 def PUSH64r : I<0x50, AddRegFrm,
859 (outs), (ins GR64:$reg), "push{q}\t$reg", [], IIC_PUSH_REG>;
860 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
862 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
864 } // mayStore, SchedRW
867 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1,
868 SchedRW = [WriteStore] in {
869 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
870 "push{q}\t$imm", [], IIC_PUSH_IMM>;
871 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
872 "push{q}\t$imm", [], IIC_PUSH_IMM>;
873 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
874 "push{q}\t$imm", [], IIC_PUSH_IMM>;
877 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
878 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
879 Requires<[In64BitMode]>, Sched<[WriteLoad]>;
880 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
881 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
882 Requires<[In64BitMode]>, Sched<[WriteStore]>;
884 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
885 mayLoad = 1, neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
886 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", [], IIC_POP_A>,
887 Requires<[In32BitMode]>;
889 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
890 mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
891 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", [], IIC_PUSH_A>,
892 Requires<[In32BitMode]>;
895 let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
897 def BSWAP32r : I<0xC8, AddRegFrm,
898 (outs GR32:$dst), (ins GR32:$src),
900 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, TB;
902 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
904 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
905 } // Constraints = "$src = $dst", SchedRW
907 // Bit scan instructions.
908 let Defs = [EFLAGS] in {
909 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
910 "bsf{w}\t{$src, $dst|$dst, $src}",
911 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
912 IIC_BSF>, TB, OpSize, Sched<[WriteShift]>;
913 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
914 "bsf{w}\t{$src, $dst|$dst, $src}",
915 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
916 IIC_BSF>, TB, OpSize, Sched<[WriteShiftLd]>;
917 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
918 "bsf{l}\t{$src, $dst|$dst, $src}",
919 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))], IIC_BSF>, TB,
921 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
922 "bsf{l}\t{$src, $dst|$dst, $src}",
923 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
924 IIC_BSF>, TB, Sched<[WriteShiftLd]>;
925 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
926 "bsf{q}\t{$src, $dst|$dst, $src}",
927 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
928 IIC_BSF>, TB, Sched<[WriteShift]>;
929 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
930 "bsf{q}\t{$src, $dst|$dst, $src}",
931 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
932 IIC_BSF>, TB, Sched<[WriteShiftLd]>;
934 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
935 "bsr{w}\t{$src, $dst|$dst, $src}",
936 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))], IIC_BSR>,
937 TB, OpSize, Sched<[WriteShift]>;
938 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
939 "bsr{w}\t{$src, $dst|$dst, $src}",
940 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
942 OpSize, Sched<[WriteShiftLd]>;
943 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
944 "bsr{l}\t{$src, $dst|$dst, $src}",
945 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))], IIC_BSR>, TB,
947 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
948 "bsr{l}\t{$src, $dst|$dst, $src}",
949 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
950 IIC_BSR>, TB, Sched<[WriteShiftLd]>;
951 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
952 "bsr{q}\t{$src, $dst|$dst, $src}",
953 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], IIC_BSR>, TB,
955 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
956 "bsr{q}\t{$src, $dst|$dst, $src}",
957 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
958 IIC_BSR>, TB, Sched<[WriteShiftLd]>;
961 let SchedRW = [WriteMicrocoded] in {
962 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
963 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
964 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", [], IIC_MOVS>;
965 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", [], IIC_MOVS>, OpSize;
966 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", [], IIC_MOVS>;
967 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", [], IIC_MOVS>;
970 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
971 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
972 def STOSB : I<0xAA, RawFrm, (outs), (ins), "stosb", [], IIC_STOS>;
973 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
974 def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", [], IIC_STOS>, OpSize;
975 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
976 def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", [], IIC_STOS>;
977 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
978 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", [], IIC_STOS>;
980 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", [], IIC_SCAS>;
981 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", [], IIC_SCAS>, OpSize;
982 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", [], IIC_SCAS>;
983 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", [], IIC_SCAS>;
985 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", [], IIC_CMPS>;
986 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", [], IIC_CMPS>, OpSize;
987 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", [], IIC_CMPS>;
988 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", [], IIC_CMPS>;
991 //===----------------------------------------------------------------------===//
992 // Move Instructions.
994 let SchedRW = [WriteMove] in {
995 let neverHasSideEffects = 1 in {
996 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
997 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
998 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
999 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
1000 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1001 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1002 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1003 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1006 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1007 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1008 "mov{b}\t{$src, $dst|$dst, $src}",
1009 [(set GR8:$dst, imm:$src)], IIC_MOV>;
1010 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1011 "mov{w}\t{$src, $dst|$dst, $src}",
1012 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize;
1013 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1014 "mov{l}\t{$src, $dst|$dst, $src}",
1015 [(set GR32:$dst, imm:$src)], IIC_MOV>;
1016 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
1017 "movabs{q}\t{$src, $dst|$dst, $src}",
1018 [(set GR64:$dst, imm:$src)], IIC_MOV>;
1019 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1020 "mov{q}\t{$src, $dst|$dst, $src}",
1021 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
1025 let SchedRW = [WriteStore] in {
1026 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1027 "mov{b}\t{$src, $dst|$dst, $src}",
1028 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
1029 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1030 "mov{w}\t{$src, $dst|$dst, $src}",
1031 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize;
1032 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1033 "mov{l}\t{$src, $dst|$dst, $src}",
1034 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>;
1035 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1036 "mov{q}\t{$src, $dst|$dst, $src}",
1037 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
1040 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
1041 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
1042 let SchedRW = [WriteALU] in {
1043 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
1044 "mov{b}\t{$src, %al|AL, $src}", [], IIC_MOV_MEM>,
1045 Requires<[In32BitMode]>;
1046 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
1047 "mov{w}\t{$src, %ax|AL, $src}", [], IIC_MOV_MEM>, OpSize,
1048 Requires<[In32BitMode]>;
1049 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1050 "mov{l}\t{$src, %eax|EAX, $src}", [], IIC_MOV_MEM>,
1051 Requires<[In32BitMode]>;
1052 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1053 "mov{b}\t{%al, $dst|$dst, AL}", [], IIC_MOV_MEM>,
1054 Requires<[In32BitMode]>;
1055 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1056 "mov{w}\t{%ax, $dst|$dst, AL}", [], IIC_MOV_MEM>, OpSize,
1057 Requires<[In32BitMode]>;
1058 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1059 "mov{l}\t{%eax, $dst|$dst, EAX}", [], IIC_MOV_MEM>,
1060 Requires<[In32BitMode]>;
1063 // FIXME: These definitions are utterly broken
1064 // Just leave them commented out for now because they're useless outside
1065 // of the large code model, and most compilers won't generate the instructions
1068 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
1069 "mov{q}\t{$src, %rax|RAX, $src}", []>;
1070 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
1071 "mov{q}\t{$src, %rax|RAX, $src}", []>;
1072 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
1073 "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
1074 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
1075 "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
1079 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
1080 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1081 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1082 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1083 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
1084 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1085 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1086 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1087 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1090 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1091 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1092 "mov{b}\t{$src, $dst|$dst, $src}",
1093 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1094 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1095 "mov{w}\t{$src, $dst|$dst, $src}",
1096 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize;
1097 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1098 "mov{l}\t{$src, $dst|$dst, $src}",
1099 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>;
1100 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1101 "mov{q}\t{$src, $dst|$dst, $src}",
1102 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1105 let SchedRW = [WriteStore] in {
1106 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1107 "mov{b}\t{$src, $dst|$dst, $src}",
1108 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1109 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1110 "mov{w}\t{$src, $dst|$dst, $src}",
1111 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize;
1112 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1113 "mov{l}\t{$src, $dst|$dst, $src}",
1114 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>;
1115 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1116 "mov{q}\t{$src, $dst|$dst, $src}",
1117 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1120 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1121 // that they can be used for copying and storing h registers, which can't be
1122 // encoded when a REX prefix is present.
1123 let isCodeGenOnly = 1 in {
1124 let neverHasSideEffects = 1 in
1125 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1126 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1127 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
1130 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1131 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1132 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1133 IIC_MOV_MEM>, Sched<[WriteStore]>;
1134 let mayLoad = 1, neverHasSideEffects = 1,
1135 canFoldAsLoad = 1, isReMaterializable = 1 in
1136 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1137 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1138 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1139 IIC_MOV_MEM>, Sched<[WriteLoad]>;
1143 // Condition code ops, incl. set if equal/not equal/...
1144 let SchedRW = [WriteALU] in {
1145 let Defs = [EFLAGS], Uses = [AH] in
1146 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1147 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
1148 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
1149 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1150 IIC_AHF>; // AH = flags
1153 //===----------------------------------------------------------------------===//
1154 // Bit tests instructions: BT, BTS, BTR, BTC.
1156 let Defs = [EFLAGS] in {
1157 let SchedRW = [WriteALU] in {
1158 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1159 "bt{w}\t{$src2, $src1|$src1, $src2}",
1160 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1162 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1163 "bt{l}\t{$src2, $src1|$src1, $src2}",
1164 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>, TB;
1165 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1166 "bt{q}\t{$src2, $src1|$src1, $src2}",
1167 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1170 // Unlike with the register+register form, the memory+register form of the
1171 // bt instruction does not ignore the high bits of the index. From ISel's
1172 // perspective, this is pretty bizarre. Make these instructions disassembly
1175 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
1176 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1177 "bt{w}\t{$src2, $src1|$src1, $src2}",
1178 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1179 // (implicit EFLAGS)]
1181 >, OpSize, TB, Requires<[FastBTMem]>;
1182 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1183 "bt{l}\t{$src2, $src1|$src1, $src2}",
1184 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1185 // (implicit EFLAGS)]
1187 >, TB, Requires<[FastBTMem]>;
1188 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1189 "bt{q}\t{$src2, $src1|$src1, $src2}",
1190 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1191 // (implicit EFLAGS)]
1196 let SchedRW = [WriteALU] in {
1197 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1198 "bt{w}\t{$src2, $src1|$src1, $src2}",
1199 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1200 IIC_BT_RI>, OpSize, TB;
1201 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1202 "bt{l}\t{$src2, $src1|$src1, $src2}",
1203 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1205 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1206 "bt{q}\t{$src2, $src1|$src1, $src2}",
1207 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1211 // Note that these instructions don't need FastBTMem because that
1212 // only applies when the other operand is in a register. When it's
1213 // an immediate, bt is still fast.
1214 let SchedRW = [WriteALU] in {
1215 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1216 "bt{w}\t{$src2, $src1|$src1, $src2}",
1217 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1218 ], IIC_BT_MI>, OpSize, TB;
1219 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1220 "bt{l}\t{$src2, $src1|$src1, $src2}",
1221 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1223 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1224 "bt{q}\t{$src2, $src1|$src1, $src2}",
1225 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1226 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1229 let hasSideEffects = 0 in {
1230 let SchedRW = [WriteALU] in {
1231 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1232 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1234 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1235 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1236 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1237 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1240 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1241 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1242 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1244 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1245 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1246 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1247 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1250 let SchedRW = [WriteALU] in {
1251 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1252 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1254 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1255 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1256 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1257 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1260 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1261 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1262 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1264 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1265 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1266 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1267 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1270 let SchedRW = [WriteALU] in {
1271 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1272 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1274 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1275 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1276 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1277 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1280 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1281 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1282 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1284 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1285 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1286 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1287 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1290 let SchedRW = [WriteALU] in {
1291 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1292 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1294 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1295 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1296 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1297 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1300 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1301 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1302 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1304 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1305 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1306 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1307 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1310 let SchedRW = [WriteALU] in {
1311 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1312 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1314 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1315 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1316 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1317 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1320 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1321 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1322 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1324 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1325 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1326 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1327 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1330 let SchedRW = [WriteALU] in {
1331 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1332 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1334 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1335 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1336 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1337 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1340 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1341 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1342 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1344 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1345 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1346 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1347 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1349 } // hasSideEffects = 0
1350 } // Defs = [EFLAGS]
1353 //===----------------------------------------------------------------------===//
1357 // Atomic swap. These are just normal xchg instructions. But since a memory
1358 // operand is referenced, the atomicity is ensured.
1359 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
1360 InstrItinClass itin> {
1361 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
1362 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
1363 (ins GR8:$val, i8mem:$ptr),
1364 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
1367 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
1369 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
1370 (ins GR16:$val, i16mem:$ptr),
1371 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
1374 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
1376 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
1377 (ins GR32:$val, i32mem:$ptr),
1378 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
1381 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
1383 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
1384 (ins GR64:$val, i64mem:$ptr),
1385 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
1388 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
1393 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
1395 // Swap between registers.
1396 let SchedRW = [WriteALU] in {
1397 let Constraints = "$val = $dst" in {
1398 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1399 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1400 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1401 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, OpSize;
1402 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1403 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1404 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1405 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1408 // Swap between EAX and other registers.
1409 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1410 "xchg{w}\t{$src, %ax|AX, $src}", [], IIC_XCHG_REG>, OpSize;
1411 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1412 "xchg{l}\t{$src, %eax|EAX, $src}", [], IIC_XCHG_REG>,
1413 Requires<[In32BitMode]>;
1414 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1415 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1416 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1417 "xchg{l}\t{$src, %eax|EAX, $src}", [], IIC_XCHG_REG>,
1418 Requires<[In64BitMode]>;
1419 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1420 "xchg{q}\t{$src, %rax|RAX, $src}", [], IIC_XCHG_REG>;
1423 let SchedRW = [WriteALU] in {
1424 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1425 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1426 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1427 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1429 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1430 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1431 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1432 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1435 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1436 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1437 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1438 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1439 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1441 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1442 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1443 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1444 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1448 let SchedRW = [WriteALU] in {
1449 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1450 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1451 IIC_CMPXCHG_REG8>, TB;
1452 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1453 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1454 IIC_CMPXCHG_REG>, TB, OpSize;
1455 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1456 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1457 IIC_CMPXCHG_REG>, TB;
1458 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1459 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1460 IIC_CMPXCHG_REG>, TB;
1463 let SchedRW = [WriteALULd, WriteRMW] in {
1464 let mayLoad = 1, mayStore = 1 in {
1465 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1466 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1467 IIC_CMPXCHG_MEM8>, TB;
1468 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1469 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1470 IIC_CMPXCHG_MEM>, TB, OpSize;
1471 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1472 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1473 IIC_CMPXCHG_MEM>, TB;
1474 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1475 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1476 IIC_CMPXCHG_MEM>, TB;
1479 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1480 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1481 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1483 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1484 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1485 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1486 TB, Requires<[HasCmpxchg16b]>;
1490 // Lock instruction prefix
1491 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1493 // Rex64 instruction prefix
1494 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>;
1496 // Data16 instruction prefix
1497 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1499 // Repeat string operation instruction prefixes
1500 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1501 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1502 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1503 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1504 // Repeat while not equal (used with CMPS and SCAS)
1505 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1509 // String manipulation instructions
1510 let SchedRW = [WriteMicrocoded] in {
1511 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", [], IIC_LODS>;
1512 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", [], IIC_LODS>, OpSize;
1513 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", [], IIC_LODS>;
1514 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", [], IIC_LODS>;
1517 let SchedRW = [WriteSystem] in {
1518 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", [], IIC_OUTS>;
1519 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", [], IIC_OUTS>, OpSize;
1520 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", [], IIC_OUTS>;
1523 // Flag instructions
1524 let SchedRW = [WriteALU] in {
1525 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1526 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1527 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1528 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1529 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1530 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1531 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1533 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1536 // Table lookup instructions
1537 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,
1540 let SchedRW = [WriteMicrocoded] in {
1541 // ASCII Adjust After Addition
1542 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1543 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1544 Requires<[In32BitMode]>;
1546 // ASCII Adjust AX Before Division
1547 // sets AL, AH and EFLAGS and uses AL and AH
1548 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1549 "aad\t$src", [], IIC_AAD>, Requires<[In32BitMode]>;
1551 // ASCII Adjust AX After Multiply
1552 // sets AL, AH and EFLAGS and uses AL
1553 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1554 "aam\t$src", [], IIC_AAM>, Requires<[In32BitMode]>;
1556 // ASCII Adjust AL After Subtraction - sets
1557 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1558 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1559 Requires<[In32BitMode]>;
1561 // Decimal Adjust AL after Addition
1562 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1563 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1564 Requires<[In32BitMode]>;
1566 // Decimal Adjust AL after Subtraction
1567 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1568 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1569 Requires<[In32BitMode]>;
1572 let SchedRW = [WriteSystem] in {
1573 // Check Array Index Against Bounds
1574 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1575 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize,
1576 Requires<[In32BitMode]>;
1577 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1578 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>,
1579 Requires<[In32BitMode]>;
1581 // Adjust RPL Field of Segment Selector
1582 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1583 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1584 Requires<[In32BitMode]>;
1585 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1586 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1587 Requires<[In32BitMode]>;
1590 //===----------------------------------------------------------------------===//
1591 // MOVBE Instructions
1593 let Predicates = [HasMOVBE] in {
1594 let SchedRW = [WriteALULd] in {
1595 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1596 "movbe{w}\t{$src, $dst|$dst, $src}",
1597 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1599 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1600 "movbe{l}\t{$src, $dst|$dst, $src}",
1601 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1603 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1604 "movbe{q}\t{$src, $dst|$dst, $src}",
1605 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
1608 let SchedRW = [WriteStore] in {
1609 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1610 "movbe{w}\t{$src, $dst|$dst, $src}",
1611 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1613 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1614 "movbe{l}\t{$src, $dst|$dst, $src}",
1615 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1617 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1618 "movbe{q}\t{$src, $dst|$dst, $src}",
1619 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
1624 //===----------------------------------------------------------------------===//
1625 // RDRAND Instruction
1627 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1628 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1630 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize, TB;
1631 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1633 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, TB;
1634 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1636 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
1639 //===----------------------------------------------------------------------===//
1640 // RDSEED Instruction
1642 let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
1643 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
1645 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize, TB;
1646 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
1648 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, TB;
1649 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
1651 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
1654 //===----------------------------------------------------------------------===//
1655 // LZCNT Instruction
1657 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
1658 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1659 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1660 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
1662 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1663 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1664 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
1665 (implicit EFLAGS)]>, XS, OpSize;
1667 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1668 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1669 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS;
1670 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1671 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1672 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
1673 (implicit EFLAGS)]>, XS;
1675 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1676 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1677 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
1679 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1680 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1681 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
1682 (implicit EFLAGS)]>, XS;
1685 //===----------------------------------------------------------------------===//
1688 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1689 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1690 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1691 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
1693 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1694 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1695 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
1696 (implicit EFLAGS)]>, XS, OpSize;
1698 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1699 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1700 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS;
1701 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1702 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1703 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
1704 (implicit EFLAGS)]>, XS;
1706 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1707 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1708 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
1710 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1711 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1712 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
1713 (implicit EFLAGS)]>, XS;
1716 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
1717 RegisterClass RC, X86MemOperand x86memop, SDNode OpNode,
1719 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
1720 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1721 [(set RC:$dst, (OpNode RC:$src)), (implicit EFLAGS)]>, T8, VEX_4V;
1722 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
1723 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1724 [(set RC:$dst, (OpNode (ld_frag addr:$src))), (implicit EFLAGS)]>,
1728 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1729 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem,
1731 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem,
1732 X86blsr, loadi64>, VEX_W;
1733 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem,
1734 X86blsmsk, loadi32>;
1735 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem,
1736 X86blsmsk, loadi64>, VEX_W;
1737 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem,
1739 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem,
1740 X86blsi, loadi64>, VEX_W;
1743 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
1744 X86MemOperand x86memop, Intrinsic Int,
1746 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1747 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1748 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
1750 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
1751 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1752 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
1753 (implicit EFLAGS)]>, T8, VEX_4VOp3;
1756 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1757 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
1758 int_x86_bmi_bextr_32, loadi32>;
1759 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
1760 int_x86_bmi_bextr_64, loadi64>, VEX_W;
1763 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
1764 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
1765 int_x86_bmi_bzhi_32, loadi32>;
1766 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
1767 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
1770 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
1771 X86MemOperand x86memop, Intrinsic Int,
1773 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1774 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1775 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
1777 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1778 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1779 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
1782 let Predicates = [HasBMI2] in {
1783 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
1784 int_x86_bmi_pdep_32, loadi32>, T8XD;
1785 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
1786 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
1787 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
1788 int_x86_bmi_pext_32, loadi32>, T8XS;
1789 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
1790 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
1793 //===----------------------------------------------------------------------===//
1795 //===----------------------------------------------------------------------===//
1797 include "X86InstrArithmetic.td"
1798 include "X86InstrCMovSetCC.td"
1799 include "X86InstrExtension.td"
1800 include "X86InstrControl.td"
1801 include "X86InstrShiftRotate.td"
1803 // X87 Floating Point Stack.
1804 include "X86InstrFPStack.td"
1806 // SIMD support (SSE, MMX and AVX)
1807 include "X86InstrFragmentsSIMD.td"
1809 // FMA - Fused Multiply-Add support (requires FMA)
1810 include "X86InstrFMA.td"
1813 include "X86InstrXOP.td"
1815 // SSE, MMX and 3DNow! vector support.
1816 include "X86InstrSSE.td"
1817 include "X86InstrMMX.td"
1818 include "X86Instr3DNow.td"
1820 include "X86InstrVMX.td"
1821 include "X86InstrSVM.td"
1823 include "X86InstrTSX.td"
1825 // System instructions.
1826 include "X86InstrSystem.td"
1828 // Compiler Pseudo Instructions and Pat Patterns
1829 include "X86InstrCompiler.td"
1831 //===----------------------------------------------------------------------===//
1832 // Assembler Mnemonic Aliases
1833 //===----------------------------------------------------------------------===//
1835 def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>;
1836 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;
1838 def : MnemonicAlias<"cbw", "cbtw", "att">;
1839 def : MnemonicAlias<"cwde", "cwtl", "att">;
1840 def : MnemonicAlias<"cwd", "cwtd", "att">;
1841 def : MnemonicAlias<"cdq", "cltd", "att">;
1842 def : MnemonicAlias<"cdqe", "cltq", "att">;
1843 def : MnemonicAlias<"cqo", "cqto", "att">;
1845 // lret maps to lretl, it is not ambiguous with lretq.
1846 def : MnemonicAlias<"lret", "lretl", "att">;
1848 def : MnemonicAlias<"leavel", "leave", "att">, Requires<[In32BitMode]>;
1849 def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>;
1851 def : MnemonicAlias<"loopz", "loope", "att">;
1852 def : MnemonicAlias<"loopnz", "loopne", "att">;
1854 def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>;
1855 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>;
1856 def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>;
1857 def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>;
1858 def : MnemonicAlias<"popfd", "popfl", "att">;
1860 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
1861 // all modes. However: "push (addr)" and "push $42" should default to
1862 // pushl/pushq depending on the current mode. Similar for "pop %bx"
1863 def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>;
1864 def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>;
1865 def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>;
1866 def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
1867 def : MnemonicAlias<"pushfd", "pushfl", "att">;
1869 def : MnemonicAlias<"popad", "popa", "intel">, Requires<[In32BitMode]>;
1870 def : MnemonicAlias<"pushad", "pusha", "intel">, Requires<[In32BitMode]>;
1872 def : MnemonicAlias<"repe", "rep", "att">;
1873 def : MnemonicAlias<"repz", "rep", "att">;
1874 def : MnemonicAlias<"repnz", "repne", "att">;
1876 def : MnemonicAlias<"retl", "ret", "att">, Requires<[In32BitMode]>;
1877 def : MnemonicAlias<"retq", "ret", "att">, Requires<[In64BitMode]>;
1879 def : MnemonicAlias<"salb", "shlb", "att">;
1880 def : MnemonicAlias<"salw", "shlw", "att">;
1881 def : MnemonicAlias<"sall", "shll", "att">;
1882 def : MnemonicAlias<"salq", "shlq", "att">;
1884 def : MnemonicAlias<"smovb", "movsb", "att">;
1885 def : MnemonicAlias<"smovw", "movsw", "att">;
1886 def : MnemonicAlias<"smovl", "movsl", "att">;
1887 def : MnemonicAlias<"smovq", "movsq", "att">;
1889 def : MnemonicAlias<"ud2a", "ud2", "att">;
1890 def : MnemonicAlias<"verrw", "verr", "att">;
1892 // System instruction aliases.
1893 def : MnemonicAlias<"iret", "iretl", "att">;
1894 def : MnemonicAlias<"sysret", "sysretl", "att">;
1895 def : MnemonicAlias<"sysexit", "sysexitl", "att">;
1897 def : MnemonicAlias<"lgdtl", "lgdt", "att">, Requires<[In32BitMode]>;
1898 def : MnemonicAlias<"lgdtq", "lgdt", "att">, Requires<[In64BitMode]>;
1899 def : MnemonicAlias<"lidtl", "lidt", "att">, Requires<[In32BitMode]>;
1900 def : MnemonicAlias<"lidtq", "lidt", "att">, Requires<[In64BitMode]>;
1901 def : MnemonicAlias<"sgdtl", "sgdt", "att">, Requires<[In32BitMode]>;
1902 def : MnemonicAlias<"sgdtq", "sgdt", "att">, Requires<[In64BitMode]>;
1903 def : MnemonicAlias<"sidtl", "sidt", "att">, Requires<[In32BitMode]>;
1904 def : MnemonicAlias<"sidtq", "sidt", "att">, Requires<[In64BitMode]>;
1907 // Floating point stack aliases.
1908 def : MnemonicAlias<"fcmovz", "fcmove", "att">;
1909 def : MnemonicAlias<"fcmova", "fcmovnbe", "att">;
1910 def : MnemonicAlias<"fcmovnae", "fcmovb", "att">;
1911 def : MnemonicAlias<"fcmovna", "fcmovbe", "att">;
1912 def : MnemonicAlias<"fcmovae", "fcmovnb", "att">;
1913 def : MnemonicAlias<"fcomip", "fcompi", "att">;
1914 def : MnemonicAlias<"fildq", "fildll", "att">;
1915 def : MnemonicAlias<"fistpq", "fistpll", "att">;
1916 def : MnemonicAlias<"fisttpq", "fisttpll", "att">;
1917 def : MnemonicAlias<"fldcww", "fldcw", "att">;
1918 def : MnemonicAlias<"fnstcww", "fnstcw", "att">;
1919 def : MnemonicAlias<"fnstsww", "fnstsw", "att">;
1920 def : MnemonicAlias<"fucomip", "fucompi", "att">;
1921 def : MnemonicAlias<"fwait", "wait", "att">;
1924 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond,
1926 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
1927 !strconcat(Prefix, NewCond, Suffix), VariantName>;
1929 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
1930 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
1931 /// example "setz" -> "sete".
1932 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix,
1934 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb
1935 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete
1936 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe
1937 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae
1938 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae
1939 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle
1940 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge
1941 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne
1942 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp
1943 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp
1945 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb
1946 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta
1947 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl
1948 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg
1951 // Aliases for set<CC>
1952 defm : IntegerCondCodeMnemonicAlias<"set", "">;
1953 // Aliases for j<CC>
1954 defm : IntegerCondCodeMnemonicAlias<"j", "">;
1955 // Aliases for cmov<CC>{w,l,q}
1956 defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">;
1957 defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">;
1958 defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">;
1959 // No size suffix for intel-style asm.
1960 defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">;
1963 //===----------------------------------------------------------------------===//
1964 // Assembler Instruction Aliases
1965 //===----------------------------------------------------------------------===//
1967 // aad/aam default to base 10 if no operand is specified.
1968 def : InstAlias<"aad", (AAD8i8 10)>;
1969 def : InstAlias<"aam", (AAM8i8 10)>;
1971 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
1972 def : InstAlias<"bt $imm, $mem", (BT32mi8 i32mem:$mem, i32i8imm:$imm)>;
1975 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>;
1976 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>;
1977 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
1978 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
1980 // div and idiv aliases for explicit A register.
1981 def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>;
1982 def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>;
1983 def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>;
1984 def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>;
1985 def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>;
1986 def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>;
1987 def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>;
1988 def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>;
1989 def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>;
1990 def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>;
1991 def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>;
1992 def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>;
1993 def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>;
1994 def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>;
1995 def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>;
1996 def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>;
2000 // Various unary fpstack operations default to operating on on ST1.
2001 // For example, "fxch" -> "fxch %st(1)"
2002 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
2003 def : InstAlias<"fsubp", (SUBR_FPrST0 ST1)>;
2004 def : InstAlias<"fsubrp", (SUB_FPrST0 ST1)>;
2005 def : InstAlias<"fmulp", (MUL_FPrST0 ST1)>;
2006 def : InstAlias<"fdivp", (DIVR_FPrST0 ST1)>;
2007 def : InstAlias<"fdivrp", (DIV_FPrST0 ST1)>;
2008 def : InstAlias<"fxch", (XCH_F ST1)>;
2009 def : InstAlias<"fcom", (COM_FST0r ST1)>;
2010 def : InstAlias<"fcomp", (COMP_FST0r ST1)>;
2011 def : InstAlias<"fcomi", (COM_FIr ST1)>;
2012 def : InstAlias<"fcompi", (COM_FIPr ST1)>;
2013 def : InstAlias<"fucom", (UCOM_Fr ST1)>;
2014 def : InstAlias<"fucomp", (UCOM_FPr ST1)>;
2015 def : InstAlias<"fucomi", (UCOM_FIr ST1)>;
2016 def : InstAlias<"fucompi", (UCOM_FIPr ST1)>;
2018 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
2019 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
2020 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
2022 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
2023 def : InstAlias<!strconcat(Mnemonic, " $op, %st(0)"),
2024 (Inst RST:$op), EmitAlias>;
2025 def : InstAlias<!strconcat(Mnemonic, " %st(0), %st(0)"),
2026 (Inst ST0), EmitAlias>;
2029 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
2030 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
2031 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
2032 defm : FpUnaryAlias<"fsubp", SUBR_FPrST0>;
2033 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
2034 defm : FpUnaryAlias<"fsubrp", SUB_FPrST0>;
2035 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
2036 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
2037 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
2038 defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>;
2039 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
2040 defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>;
2041 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
2042 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
2043 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
2044 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
2047 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
2048 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
2049 // solely because gas supports it.
2050 def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op), 0>;
2051 def : InstAlias<"fmulp %st(0), $op", (MUL_FPrST0 RST:$op)>;
2052 def : InstAlias<"fsubp %st(0), $op", (SUBR_FPrST0 RST:$op)>;
2053 def : InstAlias<"fsubrp %st(0), $op", (SUB_FPrST0 RST:$op)>;
2054 def : InstAlias<"fdivp %st(0), $op", (DIVR_FPrST0 RST:$op)>;
2055 def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>;
2057 // We accept "fnstsw %eax" even though it only writes %ax.
2058 def : InstAlias<"fnstsw %eax", (FNSTSW16r)>;
2059 def : InstAlias<"fnstsw %al" , (FNSTSW16r)>;
2060 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
2062 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
2063 // this is compatible with what GAS does.
2064 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2065 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2066 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>;
2067 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>;
2069 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
2070 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
2071 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
2072 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
2073 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
2074 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
2075 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
2077 // inb %dx -> inb %al, %dx
2078 def : InstAlias<"inb %dx", (IN8rr)>;
2079 def : InstAlias<"inw %dx", (IN16rr)>;
2080 def : InstAlias<"inl %dx", (IN32rr)>;
2081 def : InstAlias<"inb $port", (IN8ri i8imm:$port)>;
2082 def : InstAlias<"inw $port", (IN16ri i8imm:$port)>;
2083 def : InstAlias<"inl $port", (IN32ri i8imm:$port)>;
2086 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
2087 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2088 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2089 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
2090 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
2091 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2092 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2094 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
2095 // the move. All segment/mem forms are equivalent, this has the shortest
2097 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
2098 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
2100 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
2101 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
2103 // Match 'movq GR64, MMX' as an alias for movd.
2104 def : InstAlias<"movq $src, $dst",
2105 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
2106 def : InstAlias<"movq $src, $dst",
2107 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
2109 // movsd with no operands (as opposed to the SSE scalar move of a double) is an
2110 // alias for movsl. (as in rep; movsd)
2111 def : InstAlias<"movsd", (MOVSD)>;
2114 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
2115 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
2116 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
2117 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
2118 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
2119 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
2120 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
2123 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
2124 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
2125 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
2126 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
2127 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
2128 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
2129 // Note: No GR32->GR64 movzx form.
2131 // outb %dx -> outb %al, %dx
2132 def : InstAlias<"outb %dx", (OUT8rr)>;
2133 def : InstAlias<"outw %dx", (OUT16rr)>;
2134 def : InstAlias<"outl %dx", (OUT32rr)>;
2135 def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>;
2136 def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>;
2137 def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>;
2139 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
2140 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
2141 // errors, since its encoding is the most compact.
2142 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
2144 // shld/shrd op,op -> shld op, op, CL
2145 def : InstAlias<"shldw $r2, $r1", (SHLD16rrCL GR16:$r1, GR16:$r2)>;
2146 def : InstAlias<"shldl $r2, $r1", (SHLD32rrCL GR32:$r1, GR32:$r2)>;
2147 def : InstAlias<"shldq $r2, $r1", (SHLD64rrCL GR64:$r1, GR64:$r2)>;
2148 def : InstAlias<"shrdw $r2, $r1", (SHRD16rrCL GR16:$r1, GR16:$r2)>;
2149 def : InstAlias<"shrdl $r2, $r1", (SHRD32rrCL GR32:$r1, GR32:$r2)>;
2150 def : InstAlias<"shrdq $r2, $r1", (SHRD64rrCL GR64:$r1, GR64:$r2)>;
2152 def : InstAlias<"shldw $reg, $mem", (SHLD16mrCL i16mem:$mem, GR16:$reg)>;
2153 def : InstAlias<"shldl $reg, $mem", (SHLD32mrCL i32mem:$mem, GR32:$reg)>;
2154 def : InstAlias<"shldq $reg, $mem", (SHLD64mrCL i64mem:$mem, GR64:$reg)>;
2155 def : InstAlias<"shrdw $reg, $mem", (SHRD16mrCL i16mem:$mem, GR16:$reg)>;
2156 def : InstAlias<"shrdl $reg, $mem", (SHRD32mrCL i32mem:$mem, GR32:$reg)>;
2157 def : InstAlias<"shrdq $reg, $mem", (SHRD64mrCL i64mem:$mem, GR64:$reg)>;
2159 /* FIXME: This is disabled because the asm matcher is currently incapable of
2160 * matching a fixed immediate like $1.
2161 // "shl X, $1" is an alias for "shl X".
2162 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
2163 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2164 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
2165 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2166 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
2167 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2168 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
2169 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2170 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
2171 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2172 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
2173 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2174 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
2175 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2176 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
2177 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2178 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2181 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2182 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
2183 defm : ShiftRotateByOneAlias<"rol", "ROL">;
2184 defm : ShiftRotateByOneAlias<"ror", "ROR">;
2187 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
2188 def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>;
2189 def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>;
2190 def : InstAlias<"testl $val, $mem", (TEST32rm GR32:$val, i32mem:$mem)>;
2191 def : InstAlias<"testq $val, $mem", (TEST64rm GR64:$val, i64mem:$mem)>;
2193 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
2194 def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>;
2195 def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>;
2196 def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>;
2197 def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>;
2199 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
2200 def : InstAlias<"xchgw %ax, $src", (XCHG16ar GR16:$src)>;
2201 def : InstAlias<"xchgl %eax, $src", (XCHG32ar GR32:$src)>, Requires<[In32BitMode]>;
2202 def : InstAlias<"xchgl %eax, $src", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
2203 def : InstAlias<"xchgq %rax, $src", (XCHG64ar GR64:$src)>;