1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 def SDTX86BrCond : SDTypeProfile<0, 3,
31 [SDTCisVT<0, OtherVT>,
32 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
34 def SDTX86SetCC : SDTypeProfile<1, 2,
36 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
38 def SDTX86Ret : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>;
40 def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
41 def SDT_X86CallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
44 def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
46 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
48 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
50 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
52 def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
54 def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
56 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
58 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
60 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
61 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
62 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
63 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
65 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
67 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
68 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
70 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
72 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
73 [SDNPHasChain, SDNPOptInFlag]>;
75 def X86callseq_start :
76 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
77 [SDNPHasChain, SDNPOutFlag]>;
79 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
82 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
83 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
85 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
86 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
88 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
89 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
90 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
91 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
94 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
95 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
97 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
98 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
100 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
101 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
102 def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
104 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
107 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
108 [SDNPHasChain, SDNPOptInFlag]>;
110 //===----------------------------------------------------------------------===//
111 // X86 Operand Definitions.
114 // *mem - Operand definitions for the funky X86 addressing mode operands.
116 class X86MemOperand<string printMethod> : Operand<iPTR> {
117 let PrintMethod = printMethod;
118 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
121 def i8mem : X86MemOperand<"printi8mem">;
122 def i16mem : X86MemOperand<"printi16mem">;
123 def i32mem : X86MemOperand<"printi32mem">;
124 def i64mem : X86MemOperand<"printi64mem">;
125 def i128mem : X86MemOperand<"printi128mem">;
126 def f32mem : X86MemOperand<"printf32mem">;
127 def f64mem : X86MemOperand<"printf64mem">;
128 def f80mem : X86MemOperand<"printf80mem">;
129 def f128mem : X86MemOperand<"printf128mem">;
131 def lea32mem : Operand<i32> {
132 let PrintMethod = "printi32mem";
133 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
136 def SSECC : Operand<i8> {
137 let PrintMethod = "printSSECC";
140 def piclabel: Operand<i32> {
141 let PrintMethod = "printPICLabel";
144 // A couple of more descriptive operand definitions.
145 // 16-bits but only 8 bits are significant.
146 def i16i8imm : Operand<i16>;
147 // 32-bits but only 8 bits are significant.
148 def i32i8imm : Operand<i32>;
150 // Branch targets have OtherVT type.
151 def brtarget : Operand<OtherVT>;
153 //===----------------------------------------------------------------------===//
154 // X86 Complex Pattern Definitions.
157 // Define X86 specific addressing mode.
158 def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
159 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
160 [add, mul, shl, or, frameindex], []>;
162 //===----------------------------------------------------------------------===//
163 // X86 Instruction Predicate Definitions.
164 def HasMMX : Predicate<"Subtarget->hasMMX()">;
165 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
166 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
167 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
168 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
169 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
170 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
171 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
172 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
173 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
174 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
175 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
176 def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
177 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
179 //===----------------------------------------------------------------------===//
180 // X86 Instruction Format Definitions.
183 include "X86InstrFormats.td"
185 //===----------------------------------------------------------------------===//
186 // Pattern fragments...
189 // X86 specific condition code. These correspond to CondCode in
190 // X86InstrInfo.h. They must be kept in synch.
191 def X86_COND_A : PatLeaf<(i8 0)>;
192 def X86_COND_AE : PatLeaf<(i8 1)>;
193 def X86_COND_B : PatLeaf<(i8 2)>;
194 def X86_COND_BE : PatLeaf<(i8 3)>;
195 def X86_COND_E : PatLeaf<(i8 4)>;
196 def X86_COND_G : PatLeaf<(i8 5)>;
197 def X86_COND_GE : PatLeaf<(i8 6)>;
198 def X86_COND_L : PatLeaf<(i8 7)>;
199 def X86_COND_LE : PatLeaf<(i8 8)>;
200 def X86_COND_NE : PatLeaf<(i8 9)>;
201 def X86_COND_NO : PatLeaf<(i8 10)>;
202 def X86_COND_NP : PatLeaf<(i8 11)>;
203 def X86_COND_NS : PatLeaf<(i8 12)>;
204 def X86_COND_O : PatLeaf<(i8 13)>;
205 def X86_COND_P : PatLeaf<(i8 14)>;
206 def X86_COND_S : PatLeaf<(i8 15)>;
208 def i16immSExt8 : PatLeaf<(i16 imm), [{
209 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
210 // sign extended field.
211 return (int16_t)N->getValue() == (int8_t)N->getValue();
214 def i32immSExt8 : PatLeaf<(i32 imm), [{
215 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
216 // sign extended field.
217 return (int32_t)N->getValue() == (int8_t)N->getValue();
220 // Helper fragments for loads.
221 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
222 def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>;
223 def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>;
224 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
226 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
227 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
228 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
230 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
231 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
232 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
234 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
235 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
236 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
237 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
238 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
239 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
241 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
242 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
243 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
244 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
245 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
246 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
248 //===----------------------------------------------------------------------===//
249 // Instruction list...
252 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
253 // a stack adjustment and the codegen must know that they may modify the stack
254 // pointer before prolog-epilog rewriting occurs.
255 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become sub / add
256 // which can clobber EFLAGS.
257 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
258 def ADJCALLSTACKDOWN : I<0, Pseudo, (outs), (ins i32imm:$amt),
260 [(X86callseq_start imm:$amt)]>;
261 def ADJCALLSTACKUP : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
263 [(X86callseq_end imm:$amt1, imm:$amt2)]>;
265 let isImplicitDef = 1 in {
266 def IMPLICIT_DEF_GR8 : I<0, Pseudo, (outs GR8:$dst), (ins),
267 "#IMPLICIT_DEF $dst",
268 [(set GR8:$dst, (undef))]>;
269 def IMPLICIT_DEF_GR16 : I<0, Pseudo, (outs GR16:$dst), (ins),
270 "#IMPLICIT_DEF $dst",
271 [(set GR16:$dst, (undef))]>;
272 def IMPLICIT_DEF_GR32 : I<0, Pseudo, (outs GR32:$dst), (ins),
273 "#IMPLICIT_DEF $dst",
274 [(set GR32:$dst, (undef))]>;
278 let neverHasSideEffects = 1 in
279 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
282 let neverHasSideEffects = 1, isNotDuplicable = 1 in
283 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
284 "call\t$label\n\tpop{l}\t$reg", []>;
286 //===----------------------------------------------------------------------===//
287 // Control Flow Instructions...
290 // Return instructions.
291 let isTerminator = 1, isReturn = 1, isBarrier = 1,
293 def RET : I<0xC3, RawFrm, (outs), (ins), "ret", [(X86retflag 0)]>;
294 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), "ret\t$amt",
295 [(X86retflag imm:$amt)]>;
298 // All branches are RawFrm, Void, Branch, and Terminators
299 let isBranch = 1, isTerminator = 1 in
300 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
301 I<opcode, RawFrm, (outs), ins, asm, pattern>;
303 let isBranch = 1, isBarrier = 1 in
304 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
307 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
308 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
309 [(brind GR32:$dst)]>;
310 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
311 [(brind (loadi32 addr:$dst))]>;
314 // Conditional branches
315 let Uses = [EFLAGS] in {
316 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
317 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
318 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
319 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
320 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
321 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
322 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
323 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
324 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
325 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
326 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
327 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
329 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
330 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
331 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
332 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
333 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
334 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
335 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
336 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
338 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
339 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
340 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
341 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
342 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
343 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
344 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
345 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
346 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
347 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
348 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
349 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
352 //===----------------------------------------------------------------------===//
353 // Call Instructions...
356 // All calls clobber the non-callee saved registers...
357 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
358 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
359 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, EFLAGS] in {
360 def CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:$dst,variable_ops),
361 "call\t${dst:call}", []>;
362 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
363 "call\t{*}$dst", [(X86call GR32:$dst)]>;
364 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
365 "call\t{*}$dst", []>;
370 def TAILCALL : I<0, Pseudo, (outs), (ins ),
374 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
375 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset),
376 "#TC_RETURN $dst $offset",
379 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
380 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset),
381 "#TC_RETURN $dst $offset",
384 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
385 def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAILCALL",
387 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
388 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
390 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
391 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
392 "jmp\t{*}$dst # TAILCALL", []>;
394 //===----------------------------------------------------------------------===//
395 // Miscellaneous Instructions...
397 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
398 def LEAVE : I<0xC9, RawFrm,
399 (outs), (ins), "leave", []>;
401 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
403 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
406 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
409 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
410 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
411 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
412 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
414 let isTwoAddress = 1 in // GR32 = bswap GR32
415 def BSWAP32r : I<0xC8, AddRegFrm,
416 (outs GR32:$dst), (ins GR32:$src),
418 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
421 // Bit scan instructions.
422 let Defs = [EFLAGS] in {
423 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
424 "bsf{w}\t{$src, $dst|$dst, $src}",
425 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
426 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
427 "bsf{w}\t{$src, $dst|$dst, $src}",
428 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
429 (implicit EFLAGS)]>, TB;
430 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
431 "bsf{l}\t{$src, $dst|$dst, $src}",
432 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
433 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
434 "bsf{l}\t{$src, $dst|$dst, $src}",
435 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
436 (implicit EFLAGS)]>, TB;
438 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
439 "bsr{w}\t{$src, $dst|$dst, $src}",
440 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
441 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
442 "bsr{w}\t{$src, $dst|$dst, $src}",
443 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
444 (implicit EFLAGS)]>, TB;
445 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
446 "bsr{l}\t{$src, $dst|$dst, $src}",
447 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
448 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
449 "bsr{l}\t{$src, $dst|$dst, $src}",
450 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
451 (implicit EFLAGS)]>, TB;
454 let neverHasSideEffects = 1 in
455 def LEA16r : I<0x8D, MRMSrcMem,
456 (outs GR16:$dst), (ins i32mem:$src),
457 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
458 def LEA32r : I<0x8D, MRMSrcMem,
459 (outs GR32:$dst), (ins lea32mem:$src),
460 "lea{l}\t{$src|$dst}, {$dst|$src}",
461 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
463 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
464 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
465 [(X86rep_movs i8)]>, REP;
466 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
467 [(X86rep_movs i16)]>, REP, OpSize;
468 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
469 [(X86rep_movs i32)]>, REP;
472 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
473 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
474 [(X86rep_stos i8)]>, REP;
475 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
476 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
477 [(X86rep_stos i16)]>, REP, OpSize;
478 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
479 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
480 [(X86rep_stos i32)]>, REP;
482 let Defs = [RAX, RDX] in
483 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
486 let isBarrier = 1, hasCtrlDep = 1 in {
487 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
490 //===----------------------------------------------------------------------===//
491 // Input/Output Instructions...
493 let Defs = [AL], Uses = [DX] in
494 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
495 "in{b}\t{%dx, %al|%AL, %DX}", []>;
496 let Defs = [AX], Uses = [DX] in
497 def IN16rr : I<0xED, RawFrm, (outs), (ins),
498 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
499 let Defs = [EAX], Uses = [DX] in
500 def IN32rr : I<0xED, RawFrm, (outs), (ins),
501 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
504 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
505 "in{b}\t{$port, %al|%AL, $port}", []>;
507 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
508 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
510 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
511 "in{l}\t{$port, %eax|%EAX, $port}", []>;
513 let Uses = [DX, AL] in
514 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
515 "out{b}\t{%al, %dx|%DX, %AL}", []>;
516 let Uses = [DX, AX] in
517 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
518 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
519 let Uses = [DX, EAX] in
520 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
521 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
524 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
525 "out{b}\t{%al, $port|$port, %AL}", []>;
527 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
528 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
530 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
531 "out{l}\t{%eax, $port|$port, %EAX}", []>;
533 //===----------------------------------------------------------------------===//
534 // Move Instructions...
536 let neverHasSideEffects = 1 in {
537 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
538 "mov{b}\t{$src, $dst|$dst, $src}", []>;
539 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
540 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
541 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
542 "mov{l}\t{$src, $dst|$dst, $src}", []>;
544 let isReMaterializable = 1 in {
545 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
546 "mov{b}\t{$src, $dst|$dst, $src}",
547 [(set GR8:$dst, imm:$src)]>;
548 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
549 "mov{w}\t{$src, $dst|$dst, $src}",
550 [(set GR16:$dst, imm:$src)]>, OpSize;
551 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
552 "mov{l}\t{$src, $dst|$dst, $src}",
553 [(set GR32:$dst, imm:$src)]>;
555 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
556 "mov{b}\t{$src, $dst|$dst, $src}",
557 [(store (i8 imm:$src), addr:$dst)]>;
558 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
559 "mov{w}\t{$src, $dst|$dst, $src}",
560 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
561 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
562 "mov{l}\t{$src, $dst|$dst, $src}",
563 [(store (i32 imm:$src), addr:$dst)]>;
565 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
566 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
567 "mov{b}\t{$src, $dst|$dst, $src}",
568 [(set GR8:$dst, (load addr:$src))]>;
569 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
570 "mov{w}\t{$src, $dst|$dst, $src}",
571 [(set GR16:$dst, (load addr:$src))]>, OpSize;
572 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
573 "mov{l}\t{$src, $dst|$dst, $src}",
574 [(set GR32:$dst, (load addr:$src))]>;
577 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
578 "mov{b}\t{$src, $dst|$dst, $src}",
579 [(store GR8:$src, addr:$dst)]>;
580 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
581 "mov{w}\t{$src, $dst|$dst, $src}",
582 [(store GR16:$src, addr:$dst)]>, OpSize;
583 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
584 "mov{l}\t{$src, $dst|$dst, $src}",
585 [(store GR32:$src, addr:$dst)]>;
587 //===----------------------------------------------------------------------===//
588 // Fixed-Register Multiplication and Division Instructions...
591 // Extra precision multiplication
592 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
593 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
594 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
595 // This probably ought to be moved to a def : Pat<> if the
596 // syntax can be accepted.
597 [(set AL, (mul AL, GR8:$src))]>; // AL,AH = AL*GR8
598 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
599 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>,
600 OpSize; // AX,DX = AX*GR16
601 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
602 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l}\t$src", []>;
603 // EAX,EDX = EAX*GR32
604 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
605 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
607 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
608 // This probably ought to be moved to a def : Pat<> if the
609 // syntax can be accepted.
610 [(set AL, (mul AL, (loadi8 addr:$src)))]>; // AL,AH = AL*[mem8]
611 let mayLoad = 1, neverHasSideEffects = 1 in {
612 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
613 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
614 "mul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
615 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
616 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
617 "mul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
620 let neverHasSideEffects = 1 in {
621 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
622 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
624 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
625 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
626 OpSize; // AX,DX = AX*GR16
627 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
628 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
629 // EAX,EDX = EAX*GR32
631 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
632 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
633 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
634 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
635 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
636 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
637 let Defs = [EAX,EDX], Uses = [EAX] in
638 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
639 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
642 // unsigned division/remainder
643 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
644 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
646 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
647 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
648 "div{w}\t$src", []>, OpSize;
649 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
650 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
653 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
654 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
656 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
657 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
658 "div{w}\t$src", []>, OpSize;
659 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
660 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
664 // Signed division/remainder.
665 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
666 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
667 "idiv{b}\t$src", []>;
668 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
669 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
670 "idiv{w}\t$src", []>, OpSize;
671 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
672 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
673 "idiv{l}\t$src", []>;
674 let mayLoad = 1, mayLoad = 1 in {
675 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
676 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
677 "idiv{b}\t$src", []>;
678 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
679 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
680 "idiv{w}\t$src", []>, OpSize;
681 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
682 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
683 "idiv{l}\t$src", []>;
685 } // neverHasSideEffects
687 //===----------------------------------------------------------------------===//
688 // Two address Instructions.
690 let isTwoAddress = 1 in {
693 let Uses = [EFLAGS] in {
694 let isCommutable = 1 in {
695 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
696 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
697 "cmovb\t{$src2, $dst|$dst, $src2}",
698 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
699 X86_COND_B, EFLAGS))]>,
701 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
702 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
703 "cmovb\t{$src2, $dst|$dst, $src2}",
704 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
705 X86_COND_B, EFLAGS))]>,
708 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
709 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
710 "cmovae\t{$src2, $dst|$dst, $src2}",
711 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
712 X86_COND_AE, EFLAGS))]>,
714 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
715 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
716 "cmovae\t{$src2, $dst|$dst, $src2}",
717 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
718 X86_COND_AE, EFLAGS))]>,
720 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
721 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
722 "cmove\t{$src2, $dst|$dst, $src2}",
723 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
724 X86_COND_E, EFLAGS))]>,
726 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
727 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
728 "cmove\t{$src2, $dst|$dst, $src2}",
729 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
730 X86_COND_E, EFLAGS))]>,
732 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
733 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
734 "cmovne\t{$src2, $dst|$dst, $src2}",
735 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
736 X86_COND_NE, EFLAGS))]>,
738 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
739 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
740 "cmovne\t{$src2, $dst|$dst, $src2}",
741 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
742 X86_COND_NE, EFLAGS))]>,
744 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
745 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
746 "cmovbe\t{$src2, $dst|$dst, $src2}",
747 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
748 X86_COND_BE, EFLAGS))]>,
750 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
751 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
752 "cmovbe\t{$src2, $dst|$dst, $src2}",
753 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
754 X86_COND_BE, EFLAGS))]>,
756 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
757 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
758 "cmova\t{$src2, $dst|$dst, $src2}",
759 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
760 X86_COND_A, EFLAGS))]>,
762 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
763 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
764 "cmova\t{$src2, $dst|$dst, $src2}",
765 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
766 X86_COND_A, EFLAGS))]>,
768 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
769 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
770 "cmovl\t{$src2, $dst|$dst, $src2}",
771 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
772 X86_COND_L, EFLAGS))]>,
774 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
775 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
776 "cmovl\t{$src2, $dst|$dst, $src2}",
777 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
778 X86_COND_L, EFLAGS))]>,
780 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
781 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
782 "cmovge\t{$src2, $dst|$dst, $src2}",
783 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
784 X86_COND_GE, EFLAGS))]>,
786 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
787 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
788 "cmovge\t{$src2, $dst|$dst, $src2}",
789 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
790 X86_COND_GE, EFLAGS))]>,
792 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
793 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
794 "cmovle\t{$src2, $dst|$dst, $src2}",
795 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
796 X86_COND_LE, EFLAGS))]>,
798 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
799 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
800 "cmovle\t{$src2, $dst|$dst, $src2}",
801 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
802 X86_COND_LE, EFLAGS))]>,
804 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
805 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
806 "cmovg\t{$src2, $dst|$dst, $src2}",
807 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
808 X86_COND_G, EFLAGS))]>,
810 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
811 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
812 "cmovg\t{$src2, $dst|$dst, $src2}",
813 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
814 X86_COND_G, EFLAGS))]>,
816 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
817 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
818 "cmovs\t{$src2, $dst|$dst, $src2}",
819 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
820 X86_COND_S, EFLAGS))]>,
822 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
823 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
824 "cmovs\t{$src2, $dst|$dst, $src2}",
825 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
826 X86_COND_S, EFLAGS))]>,
828 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
829 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
830 "cmovns\t{$src2, $dst|$dst, $src2}",
831 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
832 X86_COND_NS, EFLAGS))]>,
834 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
835 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
836 "cmovns\t{$src2, $dst|$dst, $src2}",
837 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
838 X86_COND_NS, EFLAGS))]>,
840 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
841 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
842 "cmovp\t{$src2, $dst|$dst, $src2}",
843 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
844 X86_COND_P, EFLAGS))]>,
846 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
847 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
848 "cmovp\t{$src2, $dst|$dst, $src2}",
849 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
850 X86_COND_P, EFLAGS))]>,
852 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
853 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
854 "cmovnp\t{$src2, $dst|$dst, $src2}",
855 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
856 X86_COND_NP, EFLAGS))]>,
858 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
859 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
860 "cmovnp\t{$src2, $dst|$dst, $src2}",
861 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
862 X86_COND_NP, EFLAGS))]>,
864 } // isCommutable = 1
866 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
867 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
868 "cmovnp\t{$src2, $dst|$dst, $src2}",
869 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
870 X86_COND_NP, EFLAGS))]>,
873 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
874 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
875 "cmovb\t{$src2, $dst|$dst, $src2}",
876 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
877 X86_COND_B, EFLAGS))]>,
879 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
880 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
881 "cmovb\t{$src2, $dst|$dst, $src2}",
882 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
883 X86_COND_B, EFLAGS))]>,
885 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
886 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
887 "cmovae\t{$src2, $dst|$dst, $src2}",
888 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
889 X86_COND_AE, EFLAGS))]>,
891 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
892 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
893 "cmovae\t{$src2, $dst|$dst, $src2}",
894 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
895 X86_COND_AE, EFLAGS))]>,
897 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
898 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
899 "cmove\t{$src2, $dst|$dst, $src2}",
900 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
901 X86_COND_E, EFLAGS))]>,
903 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
904 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
905 "cmove\t{$src2, $dst|$dst, $src2}",
906 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
907 X86_COND_E, EFLAGS))]>,
909 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
910 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
911 "cmovne\t{$src2, $dst|$dst, $src2}",
912 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
913 X86_COND_NE, EFLAGS))]>,
915 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
916 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
917 "cmovne\t{$src2, $dst|$dst, $src2}",
918 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
919 X86_COND_NE, EFLAGS))]>,
921 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
922 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
923 "cmovbe\t{$src2, $dst|$dst, $src2}",
924 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
925 X86_COND_BE, EFLAGS))]>,
927 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
928 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
929 "cmovbe\t{$src2, $dst|$dst, $src2}",
930 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
931 X86_COND_BE, EFLAGS))]>,
933 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
934 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
935 "cmova\t{$src2, $dst|$dst, $src2}",
936 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
937 X86_COND_A, EFLAGS))]>,
939 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
940 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
941 "cmova\t{$src2, $dst|$dst, $src2}",
942 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
943 X86_COND_A, EFLAGS))]>,
945 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
946 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
947 "cmovl\t{$src2, $dst|$dst, $src2}",
948 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
949 X86_COND_L, EFLAGS))]>,
951 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
952 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
953 "cmovl\t{$src2, $dst|$dst, $src2}",
954 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
955 X86_COND_L, EFLAGS))]>,
957 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
958 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
959 "cmovge\t{$src2, $dst|$dst, $src2}",
960 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
961 X86_COND_GE, EFLAGS))]>,
963 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
964 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
965 "cmovge\t{$src2, $dst|$dst, $src2}",
966 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
967 X86_COND_GE, EFLAGS))]>,
969 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
970 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
971 "cmovle\t{$src2, $dst|$dst, $src2}",
972 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
973 X86_COND_LE, EFLAGS))]>,
975 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
976 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
977 "cmovle\t{$src2, $dst|$dst, $src2}",
978 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
979 X86_COND_LE, EFLAGS))]>,
981 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
982 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
983 "cmovg\t{$src2, $dst|$dst, $src2}",
984 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
985 X86_COND_G, EFLAGS))]>,
987 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
988 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
989 "cmovg\t{$src2, $dst|$dst, $src2}",
990 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
991 X86_COND_G, EFLAGS))]>,
993 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
994 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
995 "cmovs\t{$src2, $dst|$dst, $src2}",
996 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
997 X86_COND_S, EFLAGS))]>,
999 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1000 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1001 "cmovs\t{$src2, $dst|$dst, $src2}",
1002 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1003 X86_COND_S, EFLAGS))]>,
1005 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1006 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1007 "cmovns\t{$src2, $dst|$dst, $src2}",
1008 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1009 X86_COND_NS, EFLAGS))]>,
1011 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1012 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1013 "cmovns\t{$src2, $dst|$dst, $src2}",
1014 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1015 X86_COND_NS, EFLAGS))]>,
1017 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1018 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1019 "cmovp\t{$src2, $dst|$dst, $src2}",
1020 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1021 X86_COND_P, EFLAGS))]>,
1023 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1024 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1025 "cmovp\t{$src2, $dst|$dst, $src2}",
1026 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1027 X86_COND_P, EFLAGS))]>,
1029 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1030 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1031 "cmovnp\t{$src2, $dst|$dst, $src2}",
1032 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1033 X86_COND_NP, EFLAGS))]>,
1035 } // Uses = [EFLAGS]
1038 // unary instructions
1039 let CodeSize = 2 in {
1040 let Defs = [EFLAGS] in {
1041 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1042 [(set GR8:$dst, (ineg GR8:$src))]>;
1043 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1044 [(set GR16:$dst, (ineg GR16:$src))]>, OpSize;
1045 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1046 [(set GR32:$dst, (ineg GR32:$src))]>;
1047 let isTwoAddress = 0 in {
1048 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1049 [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
1050 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1051 [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1052 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1053 [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
1056 } // Defs = [EFLAGS]
1058 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1059 [(set GR8:$dst, (not GR8:$src))]>;
1060 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1061 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1062 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1063 [(set GR32:$dst, (not GR32:$src))]>;
1064 let isTwoAddress = 0 in {
1065 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1066 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1067 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1068 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1069 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1070 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1074 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1075 let Defs = [EFLAGS] in {
1077 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1078 [(set GR8:$dst, (add GR8:$src, 1))]>;
1079 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1080 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1081 [(set GR16:$dst, (add GR16:$src, 1))]>,
1082 OpSize, Requires<[In32BitMode]>;
1083 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1084 [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>;
1086 let isTwoAddress = 0, CodeSize = 2 in {
1087 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1088 [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
1089 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1090 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>,
1091 OpSize, Requires<[In32BitMode]>;
1092 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1093 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>,
1094 Requires<[In32BitMode]>;
1098 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1099 [(set GR8:$dst, (add GR8:$src, -1))]>;
1100 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1101 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1102 [(set GR16:$dst, (add GR16:$src, -1))]>,
1103 OpSize, Requires<[In32BitMode]>;
1104 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1105 [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>;
1108 let isTwoAddress = 0, CodeSize = 2 in {
1109 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1110 [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
1111 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1112 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>,
1113 OpSize, Requires<[In32BitMode]>;
1114 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1115 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>,
1116 Requires<[In32BitMode]>;
1118 } // Defs = [EFLAGS]
1120 // Logical operators...
1121 let Defs = [EFLAGS] in {
1122 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1123 def AND8rr : I<0x20, MRMDestReg,
1124 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1125 "and{b}\t{$src2, $dst|$dst, $src2}",
1126 [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>;
1127 def AND16rr : I<0x21, MRMDestReg,
1128 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1129 "and{w}\t{$src2, $dst|$dst, $src2}",
1130 [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize;
1131 def AND32rr : I<0x21, MRMDestReg,
1132 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1133 "and{l}\t{$src2, $dst|$dst, $src2}",
1134 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
1137 def AND8rm : I<0x22, MRMSrcMem,
1138 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1139 "and{b}\t{$src2, $dst|$dst, $src2}",
1140 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>;
1141 def AND16rm : I<0x23, MRMSrcMem,
1142 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1143 "and{w}\t{$src2, $dst|$dst, $src2}",
1144 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize;
1145 def AND32rm : I<0x23, MRMSrcMem,
1146 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1147 "and{l}\t{$src2, $dst|$dst, $src2}",
1148 [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>;
1150 def AND8ri : Ii8<0x80, MRM4r,
1151 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1152 "and{b}\t{$src2, $dst|$dst, $src2}",
1153 [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>;
1154 def AND16ri : Ii16<0x81, MRM4r,
1155 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1156 "and{w}\t{$src2, $dst|$dst, $src2}",
1157 [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize;
1158 def AND32ri : Ii32<0x81, MRM4r,
1159 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1160 "and{l}\t{$src2, $dst|$dst, $src2}",
1161 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
1162 def AND16ri8 : Ii8<0x83, MRM4r,
1163 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1164 "and{w}\t{$src2, $dst|$dst, $src2}",
1165 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>,
1167 def AND32ri8 : Ii8<0x83, MRM4r,
1168 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1169 "and{l}\t{$src2, $dst|$dst, $src2}",
1170 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>;
1172 let isTwoAddress = 0 in {
1173 def AND8mr : I<0x20, MRMDestMem,
1174 (outs), (ins i8mem :$dst, GR8 :$src),
1175 "and{b}\t{$src, $dst|$dst, $src}",
1176 [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>;
1177 def AND16mr : I<0x21, MRMDestMem,
1178 (outs), (ins i16mem:$dst, GR16:$src),
1179 "and{w}\t{$src, $dst|$dst, $src}",
1180 [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>,
1182 def AND32mr : I<0x21, MRMDestMem,
1183 (outs), (ins i32mem:$dst, GR32:$src),
1184 "and{l}\t{$src, $dst|$dst, $src}",
1185 [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>;
1186 def AND8mi : Ii8<0x80, MRM4m,
1187 (outs), (ins i8mem :$dst, i8imm :$src),
1188 "and{b}\t{$src, $dst|$dst, $src}",
1189 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1190 def AND16mi : Ii16<0x81, MRM4m,
1191 (outs), (ins i16mem:$dst, i16imm:$src),
1192 "and{w}\t{$src, $dst|$dst, $src}",
1193 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1195 def AND32mi : Ii32<0x81, MRM4m,
1196 (outs), (ins i32mem:$dst, i32imm:$src),
1197 "and{l}\t{$src, $dst|$dst, $src}",
1198 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1199 def AND16mi8 : Ii8<0x83, MRM4m,
1200 (outs), (ins i16mem:$dst, i16i8imm :$src),
1201 "and{w}\t{$src, $dst|$dst, $src}",
1202 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1204 def AND32mi8 : Ii8<0x83, MRM4m,
1205 (outs), (ins i32mem:$dst, i32i8imm :$src),
1206 "and{l}\t{$src, $dst|$dst, $src}",
1207 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1211 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1212 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1213 "or{b}\t{$src2, $dst|$dst, $src2}",
1214 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
1215 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1216 "or{w}\t{$src2, $dst|$dst, $src2}",
1217 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize;
1218 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1219 "or{l}\t{$src2, $dst|$dst, $src2}",
1220 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
1222 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1223 "or{b}\t{$src2, $dst|$dst, $src2}",
1224 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
1225 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1226 "or{w}\t{$src2, $dst|$dst, $src2}",
1227 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize;
1228 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1229 "or{l}\t{$src2, $dst|$dst, $src2}",
1230 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>;
1232 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1233 "or{b}\t{$src2, $dst|$dst, $src2}",
1234 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
1235 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1236 "or{w}\t{$src2, $dst|$dst, $src2}",
1237 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize;
1238 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1239 "or{l}\t{$src2, $dst|$dst, $src2}",
1240 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
1242 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1243 "or{w}\t{$src2, $dst|$dst, $src2}",
1244 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1245 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1246 "or{l}\t{$src2, $dst|$dst, $src2}",
1247 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>;
1248 let isTwoAddress = 0 in {
1249 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1250 "or{b}\t{$src, $dst|$dst, $src}",
1251 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
1252 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1253 "or{w}\t{$src, $dst|$dst, $src}",
1254 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize;
1255 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1256 "or{l}\t{$src, $dst|$dst, $src}",
1257 [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>;
1258 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1259 "or{b}\t{$src, $dst|$dst, $src}",
1260 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1261 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1262 "or{w}\t{$src, $dst|$dst, $src}",
1263 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1265 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1266 "or{l}\t{$src, $dst|$dst, $src}",
1267 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1268 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1269 "or{w}\t{$src, $dst|$dst, $src}",
1270 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1272 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1273 "or{l}\t{$src, $dst|$dst, $src}",
1274 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1278 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1279 def XOR8rr : I<0x30, MRMDestReg,
1280 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1281 "xor{b}\t{$src2, $dst|$dst, $src2}",
1282 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>;
1283 def XOR16rr : I<0x31, MRMDestReg,
1284 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1285 "xor{w}\t{$src2, $dst|$dst, $src2}",
1286 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize;
1287 def XOR32rr : I<0x31, MRMDestReg,
1288 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1289 "xor{l}\t{$src2, $dst|$dst, $src2}",
1290 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
1293 def XOR8rm : I<0x32, MRMSrcMem ,
1294 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1295 "xor{b}\t{$src2, $dst|$dst, $src2}",
1296 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>;
1297 def XOR16rm : I<0x33, MRMSrcMem ,
1298 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1299 "xor{w}\t{$src2, $dst|$dst, $src2}",
1300 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>, OpSize;
1301 def XOR32rm : I<0x33, MRMSrcMem ,
1302 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1303 "xor{l}\t{$src2, $dst|$dst, $src2}",
1304 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>;
1306 def XOR8ri : Ii8<0x80, MRM6r,
1307 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1308 "xor{b}\t{$src2, $dst|$dst, $src2}",
1309 [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>;
1310 def XOR16ri : Ii16<0x81, MRM6r,
1311 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1312 "xor{w}\t{$src2, $dst|$dst, $src2}",
1313 [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize;
1314 def XOR32ri : Ii32<0x81, MRM6r,
1315 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1316 "xor{l}\t{$src2, $dst|$dst, $src2}",
1317 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
1318 def XOR16ri8 : Ii8<0x83, MRM6r,
1319 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1320 "xor{w}\t{$src2, $dst|$dst, $src2}",
1321 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>,
1323 def XOR32ri8 : Ii8<0x83, MRM6r,
1324 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1325 "xor{l}\t{$src2, $dst|$dst, $src2}",
1326 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>;
1327 let isTwoAddress = 0 in {
1328 def XOR8mr : I<0x30, MRMDestMem,
1329 (outs), (ins i8mem :$dst, GR8 :$src),
1330 "xor{b}\t{$src, $dst|$dst, $src}",
1331 [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>;
1332 def XOR16mr : I<0x31, MRMDestMem,
1333 (outs), (ins i16mem:$dst, GR16:$src),
1334 "xor{w}\t{$src, $dst|$dst, $src}",
1335 [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>,
1337 def XOR32mr : I<0x31, MRMDestMem,
1338 (outs), (ins i32mem:$dst, GR32:$src),
1339 "xor{l}\t{$src, $dst|$dst, $src}",
1340 [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>;
1341 def XOR8mi : Ii8<0x80, MRM6m,
1342 (outs), (ins i8mem :$dst, i8imm :$src),
1343 "xor{b}\t{$src, $dst|$dst, $src}",
1344 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1345 def XOR16mi : Ii16<0x81, MRM6m,
1346 (outs), (ins i16mem:$dst, i16imm:$src),
1347 "xor{w}\t{$src, $dst|$dst, $src}",
1348 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1350 def XOR32mi : Ii32<0x81, MRM6m,
1351 (outs), (ins i32mem:$dst, i32imm:$src),
1352 "xor{l}\t{$src, $dst|$dst, $src}",
1353 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1354 def XOR16mi8 : Ii8<0x83, MRM6m,
1355 (outs), (ins i16mem:$dst, i16i8imm :$src),
1356 "xor{w}\t{$src, $dst|$dst, $src}",
1357 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1359 def XOR32mi8 : Ii8<0x83, MRM6m,
1360 (outs), (ins i32mem:$dst, i32i8imm :$src),
1361 "xor{l}\t{$src, $dst|$dst, $src}",
1362 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1364 } // Defs = [EFLAGS]
1366 // Shift instructions
1367 let Defs = [EFLAGS] in {
1368 let Uses = [CL] in {
1369 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1370 "shl{b}\t{%cl, $dst|$dst, %CL}",
1371 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1372 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1373 "shl{w}\t{%cl, $dst|$dst, %CL}",
1374 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1375 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1376 "shl{l}\t{%cl, $dst|$dst, %CL}",
1377 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1380 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1381 "shl{b}\t{$src2, $dst|$dst, $src2}",
1382 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1383 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1384 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1385 "shl{w}\t{$src2, $dst|$dst, $src2}",
1386 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1387 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1388 "shl{l}\t{$src2, $dst|$dst, $src2}",
1389 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1390 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1394 let isTwoAddress = 0 in {
1395 let Uses = [CL] in {
1396 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1397 "shl{b}\t{%cl, $dst|$dst, %CL}",
1398 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1399 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1400 "shl{w}\t{%cl, $dst|$dst, %CL}",
1401 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1402 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1403 "shl{l}\t{%cl, $dst|$dst, %CL}",
1404 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1406 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1407 "shl{b}\t{$src, $dst|$dst, $src}",
1408 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1409 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1410 "shl{w}\t{$src, $dst|$dst, $src}",
1411 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1413 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1414 "shl{l}\t{$src, $dst|$dst, $src}",
1415 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1418 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1420 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1421 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1423 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1425 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1427 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1430 let Uses = [CL] in {
1431 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1432 "shr{b}\t{%cl, $dst|$dst, %CL}",
1433 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1434 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1435 "shr{w}\t{%cl, $dst|$dst, %CL}",
1436 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1437 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1438 "shr{l}\t{%cl, $dst|$dst, %CL}",
1439 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1442 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1443 "shr{b}\t{$src2, $dst|$dst, $src2}",
1444 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1445 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1446 "shr{w}\t{$src2, $dst|$dst, $src2}",
1447 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1448 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1449 "shr{l}\t{$src2, $dst|$dst, $src2}",
1450 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1453 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1455 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1456 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1458 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1459 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1461 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1463 let isTwoAddress = 0 in {
1464 let Uses = [CL] in {
1465 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1466 "shr{b}\t{%cl, $dst|$dst, %CL}",
1467 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1468 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1469 "shr{w}\t{%cl, $dst|$dst, %CL}",
1470 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1472 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1473 "shr{l}\t{%cl, $dst|$dst, %CL}",
1474 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1476 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1477 "shr{b}\t{$src, $dst|$dst, $src}",
1478 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1479 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1480 "shr{w}\t{$src, $dst|$dst, $src}",
1481 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1483 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1484 "shr{l}\t{$src, $dst|$dst, $src}",
1485 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1488 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1490 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1491 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1493 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1494 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1496 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1499 let Uses = [CL] in {
1500 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1501 "sar{b}\t{%cl, $dst|$dst, %CL}",
1502 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1503 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1504 "sar{w}\t{%cl, $dst|$dst, %CL}",
1505 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1506 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1507 "sar{l}\t{%cl, $dst|$dst, %CL}",
1508 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1511 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1512 "sar{b}\t{$src2, $dst|$dst, $src2}",
1513 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1514 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1515 "sar{w}\t{$src2, $dst|$dst, $src2}",
1516 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1518 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1519 "sar{l}\t{$src2, $dst|$dst, $src2}",
1520 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1523 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1525 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1526 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1528 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1529 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1531 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1533 let isTwoAddress = 0 in {
1534 let Uses = [CL] in {
1535 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1536 "sar{b}\t{%cl, $dst|$dst, %CL}",
1537 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
1538 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1539 "sar{w}\t{%cl, $dst|$dst, %CL}",
1540 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1541 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1542 "sar{l}\t{%cl, $dst|$dst, %CL}",
1543 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1545 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1546 "sar{b}\t{$src, $dst|$dst, $src}",
1547 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1548 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1549 "sar{w}\t{$src, $dst|$dst, $src}",
1550 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1552 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1553 "sar{l}\t{$src, $dst|$dst, $src}",
1554 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1557 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1559 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1560 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1562 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1564 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
1566 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1569 // Rotate instructions
1570 // FIXME: provide shorter instructions when imm8 == 1
1571 let Uses = [CL] in {
1572 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
1573 "rol{b}\t{%cl, $dst|$dst, %CL}",
1574 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
1575 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
1576 "rol{w}\t{%cl, $dst|$dst, %CL}",
1577 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
1578 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
1579 "rol{l}\t{%cl, $dst|$dst, %CL}",
1580 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
1583 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1584 "rol{b}\t{$src2, $dst|$dst, $src2}",
1585 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1586 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1587 "rol{w}\t{$src2, $dst|$dst, $src2}",
1588 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1589 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1590 "rol{l}\t{$src2, $dst|$dst, $src2}",
1591 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1594 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1596 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1597 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
1599 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1600 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1602 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1604 let isTwoAddress = 0 in {
1605 let Uses = [CL] in {
1606 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
1607 "rol{b}\t{%cl, $dst|$dst, %CL}",
1608 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
1609 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
1610 "rol{w}\t{%cl, $dst|$dst, %CL}",
1611 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1612 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
1613 "rol{l}\t{%cl, $dst|$dst, %CL}",
1614 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
1616 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
1617 "rol{b}\t{$src, $dst|$dst, $src}",
1618 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1619 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
1620 "rol{w}\t{$src, $dst|$dst, $src}",
1621 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1623 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
1624 "rol{l}\t{$src, $dst|$dst, $src}",
1625 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1628 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
1630 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1631 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
1633 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1635 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
1637 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1640 let Uses = [CL] in {
1641 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
1642 "ror{b}\t{%cl, $dst|$dst, %CL}",
1643 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
1644 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
1645 "ror{w}\t{%cl, $dst|$dst, %CL}",
1646 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
1647 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
1648 "ror{l}\t{%cl, $dst|$dst, %CL}",
1649 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
1652 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1653 "ror{b}\t{$src2, $dst|$dst, $src2}",
1654 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
1655 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1656 "ror{w}\t{$src2, $dst|$dst, $src2}",
1657 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1658 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1659 "ror{l}\t{$src2, $dst|$dst, $src2}",
1660 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
1663 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1665 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
1666 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
1668 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
1669 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
1671 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
1673 let isTwoAddress = 0 in {
1674 let Uses = [CL] in {
1675 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
1676 "ror{b}\t{%cl, $dst|$dst, %CL}",
1677 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
1678 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
1679 "ror{w}\t{%cl, $dst|$dst, %CL}",
1680 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1681 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
1682 "ror{l}\t{%cl, $dst|$dst, %CL}",
1683 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
1685 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1686 "ror{b}\t{$src, $dst|$dst, $src}",
1687 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1688 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
1689 "ror{w}\t{$src, $dst|$dst, $src}",
1690 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1692 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
1693 "ror{l}\t{$src, $dst|$dst, $src}",
1694 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1697 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
1699 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1700 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
1702 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1704 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
1706 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1711 // Double shift instructions (generalizations of rotate)
1712 let Uses = [CL] in {
1713 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1714 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1715 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
1716 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1717 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1718 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
1719 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1720 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1721 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
1723 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1724 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1725 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
1729 let isCommutable = 1 in { // These instructions commute to each other.
1730 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
1731 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1732 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1733 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
1736 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
1737 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1738 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1739 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
1742 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
1743 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1744 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1745 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
1748 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
1749 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1750 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1751 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
1756 let isTwoAddress = 0 in {
1757 let Uses = [CL] in {
1758 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1759 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1760 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
1762 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1763 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1764 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
1767 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
1768 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1769 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1770 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
1771 (i8 imm:$src3)), addr:$dst)]>,
1773 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
1774 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1775 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1776 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
1777 (i8 imm:$src3)), addr:$dst)]>,
1780 let Uses = [CL] in {
1781 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1782 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1783 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
1784 addr:$dst)]>, TB, OpSize;
1785 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1786 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1787 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
1788 addr:$dst)]>, TB, OpSize;
1790 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
1791 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1792 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1793 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
1794 (i8 imm:$src3)), addr:$dst)]>,
1796 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
1797 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1798 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1799 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
1800 (i8 imm:$src3)), addr:$dst)]>,
1803 } // Defs = [EFLAGS]
1807 let Defs = [EFLAGS] in {
1808 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1809 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
1810 (ins GR8 :$src1, GR8 :$src2),
1811 "add{b}\t{$src2, $dst|$dst, $src2}",
1812 [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>;
1813 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1814 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
1815 (ins GR16:$src1, GR16:$src2),
1816 "add{w}\t{$src2, $dst|$dst, $src2}",
1817 [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize;
1818 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
1819 (ins GR32:$src1, GR32:$src2),
1820 "add{l}\t{$src2, $dst|$dst, $src2}",
1821 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
1822 } // end isConvertibleToThreeAddress
1823 } // end isCommutable
1824 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
1825 (ins GR8 :$src1, i8mem :$src2),
1826 "add{b}\t{$src2, $dst|$dst, $src2}",
1827 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>;
1828 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
1829 (ins GR16:$src1, i16mem:$src2),
1830 "add{w}\t{$src2, $dst|$dst, $src2}",
1831 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>,OpSize;
1832 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
1833 (ins GR32:$src1, i32mem:$src2),
1834 "add{l}\t{$src2, $dst|$dst, $src2}",
1835 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>;
1837 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1838 "add{b}\t{$src2, $dst|$dst, $src2}",
1839 [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>;
1841 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1842 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
1843 (ins GR16:$src1, i16imm:$src2),
1844 "add{w}\t{$src2, $dst|$dst, $src2}",
1845 [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize;
1846 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
1847 (ins GR32:$src1, i32imm:$src2),
1848 "add{l}\t{$src2, $dst|$dst, $src2}",
1849 [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>;
1850 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
1851 (ins GR16:$src1, i16i8imm:$src2),
1852 "add{w}\t{$src2, $dst|$dst, $src2}",
1853 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1854 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
1855 (ins GR32:$src1, i32i8imm:$src2),
1856 "add{l}\t{$src2, $dst|$dst, $src2}",
1857 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>;
1860 let isTwoAddress = 0 in {
1861 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1862 "add{b}\t{$src2, $dst|$dst, $src2}",
1863 [(store (add (load addr:$dst), GR8:$src2), addr:$dst)]>;
1864 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1865 "add{w}\t{$src2, $dst|$dst, $src2}",
1866 [(store (add (load addr:$dst), GR16:$src2), addr:$dst)]>,
1868 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1869 "add{l}\t{$src2, $dst|$dst, $src2}",
1870 [(store (add (load addr:$dst), GR32:$src2), addr:$dst)]>;
1871 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
1872 "add{b}\t{$src2, $dst|$dst, $src2}",
1873 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1874 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
1875 "add{w}\t{$src2, $dst|$dst, $src2}",
1876 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1878 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
1879 "add{l}\t{$src2, $dst|$dst, $src2}",
1880 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1881 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1882 "add{w}\t{$src2, $dst|$dst, $src2}",
1883 [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1885 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1886 "add{l}\t{$src2, $dst|$dst, $src2}",
1887 [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1890 let Uses = [EFLAGS] in {
1891 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1892 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1893 "adc{l}\t{$src2, $dst|$dst, $src2}",
1894 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
1896 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1897 "adc{l}\t{$src2, $dst|$dst, $src2}",
1898 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
1899 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1900 "adc{l}\t{$src2, $dst|$dst, $src2}",
1901 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
1902 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1903 "adc{l}\t{$src2, $dst|$dst, $src2}",
1904 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
1906 let isTwoAddress = 0 in {
1907 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1908 "adc{l}\t{$src2, $dst|$dst, $src2}",
1909 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
1910 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
1911 "adc{l}\t{$src2, $dst|$dst, $src2}",
1912 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1913 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1914 "adc{l}\t{$src2, $dst|$dst, $src2}",
1915 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1917 } // Uses = [EFLAGS]
1919 def SUB8rr : I<0x28, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1920 "sub{b}\t{$src2, $dst|$dst, $src2}",
1921 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2))]>;
1922 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1923 "sub{w}\t{$src2, $dst|$dst, $src2}",
1924 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2))]>, OpSize;
1925 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1926 "sub{l}\t{$src2, $dst|$dst, $src2}",
1927 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
1928 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1929 "sub{b}\t{$src2, $dst|$dst, $src2}",
1930 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2)))]>;
1931 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1932 "sub{w}\t{$src2, $dst|$dst, $src2}",
1933 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2)))]>, OpSize;
1934 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1935 "sub{l}\t{$src2, $dst|$dst, $src2}",
1936 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2)))]>;
1938 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1939 "sub{b}\t{$src2, $dst|$dst, $src2}",
1940 [(set GR8:$dst, (sub GR8:$src1, imm:$src2))]>;
1941 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1942 "sub{w}\t{$src2, $dst|$dst, $src2}",
1943 [(set GR16:$dst, (sub GR16:$src1, imm:$src2))]>, OpSize;
1944 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1945 "sub{l}\t{$src2, $dst|$dst, $src2}",
1946 [(set GR32:$dst, (sub GR32:$src1, imm:$src2))]>;
1947 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1948 "sub{w}\t{$src2, $dst|$dst, $src2}",
1949 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2))]>,
1951 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1952 "sub{l}\t{$src2, $dst|$dst, $src2}",
1953 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2))]>;
1954 let isTwoAddress = 0 in {
1955 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1956 "sub{b}\t{$src2, $dst|$dst, $src2}",
1957 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst)]>;
1958 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1959 "sub{w}\t{$src2, $dst|$dst, $src2}",
1960 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst)]>,
1962 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1963 "sub{l}\t{$src2, $dst|$dst, $src2}",
1964 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst)]>;
1965 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
1966 "sub{b}\t{$src2, $dst|$dst, $src2}",
1967 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1968 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
1969 "sub{w}\t{$src2, $dst|$dst, $src2}",
1970 [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1972 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
1973 "sub{l}\t{$src2, $dst|$dst, $src2}",
1974 [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1975 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1976 "sub{w}\t{$src2, $dst|$dst, $src2}",
1977 [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1979 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1980 "sub{l}\t{$src2, $dst|$dst, $src2}",
1981 [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1984 let Uses = [EFLAGS] in {
1985 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1986 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1987 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
1989 let isTwoAddress = 0 in {
1990 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1991 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1992 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
1993 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
1994 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1995 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1996 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
1997 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1998 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1999 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2000 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2001 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2003 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2004 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2005 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2006 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2007 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2008 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2009 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2010 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2011 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2012 } // Uses = [EFLAGS]
2013 } // Defs = [EFLAGS]
2015 let Defs = [EFLAGS] in {
2016 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2017 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2018 "imul{w}\t{$src2, $dst|$dst, $src2}",
2019 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2))]>, TB, OpSize;
2020 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2021 "imul{l}\t{$src2, $dst|$dst, $src2}",
2022 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>, TB;
2024 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2025 "imul{w}\t{$src2, $dst|$dst, $src2}",
2026 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2)))]>,
2028 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2029 "imul{l}\t{$src2, $dst|$dst, $src2}",
2030 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2)))]>, TB;
2031 } // Defs = [EFLAGS]
2032 } // end Two Address instructions
2034 // Suprisingly enough, these are not two address instructions!
2035 let Defs = [EFLAGS] in {
2036 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2037 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2038 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2039 [(set GR16:$dst, (mul GR16:$src1, imm:$src2))]>, OpSize;
2040 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2041 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2042 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2043 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
2044 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2045 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2046 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2047 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2))]>,
2049 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2050 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2051 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2052 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2))]>;
2054 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2055 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2056 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2057 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2))]>,
2059 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2060 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2061 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2062 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2))]>;
2063 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2064 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2065 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2066 [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>,
2068 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2069 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2070 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2071 [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>;
2072 } // Defs = [EFLAGS]
2074 //===----------------------------------------------------------------------===//
2075 // Test instructions are just like AND, except they don't generate a result.
2077 let Defs = [EFLAGS] in {
2078 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2079 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2080 "test{b}\t{$src2, $src1|$src1, $src2}",
2081 [(X86cmp (and GR8:$src1, GR8:$src2), 0),
2082 (implicit EFLAGS)]>;
2083 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2084 "test{w}\t{$src2, $src1|$src1, $src2}",
2085 [(X86cmp (and GR16:$src1, GR16:$src2), 0),
2086 (implicit EFLAGS)]>,
2088 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2089 "test{l}\t{$src2, $src1|$src1, $src2}",
2090 [(X86cmp (and GR32:$src1, GR32:$src2), 0),
2091 (implicit EFLAGS)]>;
2094 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2095 "test{b}\t{$src2, $src1|$src1, $src2}",
2096 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2097 (implicit EFLAGS)]>;
2098 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2099 "test{w}\t{$src2, $src1|$src1, $src2}",
2100 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2101 (implicit EFLAGS)]>, OpSize;
2102 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2103 "test{l}\t{$src2, $src1|$src1, $src2}",
2104 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2105 (implicit EFLAGS)]>;
2107 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2108 (outs), (ins GR8:$src1, i8imm:$src2),
2109 "test{b}\t{$src2, $src1|$src1, $src2}",
2110 [(X86cmp (and GR8:$src1, imm:$src2), 0),
2111 (implicit EFLAGS)]>;
2112 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2113 (outs), (ins GR16:$src1, i16imm:$src2),
2114 "test{w}\t{$src2, $src1|$src1, $src2}",
2115 [(X86cmp (and GR16:$src1, imm:$src2), 0),
2116 (implicit EFLAGS)]>, OpSize;
2117 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2118 (outs), (ins GR32:$src1, i32imm:$src2),
2119 "test{l}\t{$src2, $src1|$src1, $src2}",
2120 [(X86cmp (and GR32:$src1, imm:$src2), 0),
2121 (implicit EFLAGS)]>;
2123 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2124 (outs), (ins i8mem:$src1, i8imm:$src2),
2125 "test{b}\t{$src2, $src1|$src1, $src2}",
2126 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2127 (implicit EFLAGS)]>;
2128 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2129 (outs), (ins i16mem:$src1, i16imm:$src2),
2130 "test{w}\t{$src2, $src1|$src1, $src2}",
2131 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2132 (implicit EFLAGS)]>, OpSize;
2133 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2134 (outs), (ins i32mem:$src1, i32imm:$src2),
2135 "test{l}\t{$src2, $src1|$src1, $src2}",
2136 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2137 (implicit EFLAGS)]>;
2138 } // Defs = [EFLAGS]
2141 // Condition code ops, incl. set if equal/not equal/...
2142 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2143 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2144 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2145 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2147 let Uses = [EFLAGS] in {
2148 def SETEr : I<0x94, MRM0r,
2149 (outs GR8 :$dst), (ins),
2151 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2153 def SETEm : I<0x94, MRM0m,
2154 (outs), (ins i8mem:$dst),
2156 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2158 def SETNEr : I<0x95, MRM0r,
2159 (outs GR8 :$dst), (ins),
2161 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2163 def SETNEm : I<0x95, MRM0m,
2164 (outs), (ins i8mem:$dst),
2166 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2168 def SETLr : I<0x9C, MRM0r,
2169 (outs GR8 :$dst), (ins),
2171 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2172 TB; // GR8 = < signed
2173 def SETLm : I<0x9C, MRM0m,
2174 (outs), (ins i8mem:$dst),
2176 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2177 TB; // [mem8] = < signed
2178 def SETGEr : I<0x9D, MRM0r,
2179 (outs GR8 :$dst), (ins),
2181 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2182 TB; // GR8 = >= signed
2183 def SETGEm : I<0x9D, MRM0m,
2184 (outs), (ins i8mem:$dst),
2186 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2187 TB; // [mem8] = >= signed
2188 def SETLEr : I<0x9E, MRM0r,
2189 (outs GR8 :$dst), (ins),
2191 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2192 TB; // GR8 = <= signed
2193 def SETLEm : I<0x9E, MRM0m,
2194 (outs), (ins i8mem:$dst),
2196 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2197 TB; // [mem8] = <= signed
2198 def SETGr : I<0x9F, MRM0r,
2199 (outs GR8 :$dst), (ins),
2201 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2202 TB; // GR8 = > signed
2203 def SETGm : I<0x9F, MRM0m,
2204 (outs), (ins i8mem:$dst),
2206 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2207 TB; // [mem8] = > signed
2209 def SETBr : I<0x92, MRM0r,
2210 (outs GR8 :$dst), (ins),
2212 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2213 TB; // GR8 = < unsign
2214 def SETBm : I<0x92, MRM0m,
2215 (outs), (ins i8mem:$dst),
2217 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
2218 TB; // [mem8] = < unsign
2219 def SETAEr : I<0x93, MRM0r,
2220 (outs GR8 :$dst), (ins),
2222 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
2223 TB; // GR8 = >= unsign
2224 def SETAEm : I<0x93, MRM0m,
2225 (outs), (ins i8mem:$dst),
2227 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
2228 TB; // [mem8] = >= unsign
2229 def SETBEr : I<0x96, MRM0r,
2230 (outs GR8 :$dst), (ins),
2232 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
2233 TB; // GR8 = <= unsign
2234 def SETBEm : I<0x96, MRM0m,
2235 (outs), (ins i8mem:$dst),
2237 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
2238 TB; // [mem8] = <= unsign
2239 def SETAr : I<0x97, MRM0r,
2240 (outs GR8 :$dst), (ins),
2242 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
2243 TB; // GR8 = > signed
2244 def SETAm : I<0x97, MRM0m,
2245 (outs), (ins i8mem:$dst),
2247 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
2248 TB; // [mem8] = > signed
2250 def SETSr : I<0x98, MRM0r,
2251 (outs GR8 :$dst), (ins),
2253 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
2254 TB; // GR8 = <sign bit>
2255 def SETSm : I<0x98, MRM0m,
2256 (outs), (ins i8mem:$dst),
2258 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
2259 TB; // [mem8] = <sign bit>
2260 def SETNSr : I<0x99, MRM0r,
2261 (outs GR8 :$dst), (ins),
2263 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
2264 TB; // GR8 = !<sign bit>
2265 def SETNSm : I<0x99, MRM0m,
2266 (outs), (ins i8mem:$dst),
2268 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
2269 TB; // [mem8] = !<sign bit>
2270 def SETPr : I<0x9A, MRM0r,
2271 (outs GR8 :$dst), (ins),
2273 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
2275 def SETPm : I<0x9A, MRM0m,
2276 (outs), (ins i8mem:$dst),
2278 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
2279 TB; // [mem8] = parity
2280 def SETNPr : I<0x9B, MRM0r,
2281 (outs GR8 :$dst), (ins),
2283 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
2284 TB; // GR8 = not parity
2285 def SETNPm : I<0x9B, MRM0m,
2286 (outs), (ins i8mem:$dst),
2288 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
2289 TB; // [mem8] = not parity
2290 } // Uses = [EFLAGS]
2293 // Integer comparisons
2294 let Defs = [EFLAGS] in {
2295 def CMP8rr : I<0x38, MRMDestReg,
2296 (outs), (ins GR8 :$src1, GR8 :$src2),
2297 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2298 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2299 def CMP16rr : I<0x39, MRMDestReg,
2300 (outs), (ins GR16:$src1, GR16:$src2),
2301 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2302 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
2303 def CMP32rr : I<0x39, MRMDestReg,
2304 (outs), (ins GR32:$src1, GR32:$src2),
2305 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2306 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
2307 def CMP8mr : I<0x38, MRMDestMem,
2308 (outs), (ins i8mem :$src1, GR8 :$src2),
2309 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2310 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
2311 (implicit EFLAGS)]>;
2312 def CMP16mr : I<0x39, MRMDestMem,
2313 (outs), (ins i16mem:$src1, GR16:$src2),
2314 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2315 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
2316 (implicit EFLAGS)]>, OpSize;
2317 def CMP32mr : I<0x39, MRMDestMem,
2318 (outs), (ins i32mem:$src1, GR32:$src2),
2319 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2320 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
2321 (implicit EFLAGS)]>;
2322 def CMP8rm : I<0x3A, MRMSrcMem,
2323 (outs), (ins GR8 :$src1, i8mem :$src2),
2324 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2325 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
2326 (implicit EFLAGS)]>;
2327 def CMP16rm : I<0x3B, MRMSrcMem,
2328 (outs), (ins GR16:$src1, i16mem:$src2),
2329 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2330 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
2331 (implicit EFLAGS)]>, OpSize;
2332 def CMP32rm : I<0x3B, MRMSrcMem,
2333 (outs), (ins GR32:$src1, i32mem:$src2),
2334 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2335 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
2336 (implicit EFLAGS)]>;
2337 def CMP8ri : Ii8<0x80, MRM7r,
2338 (outs), (ins GR8:$src1, i8imm:$src2),
2339 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2340 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
2341 def CMP16ri : Ii16<0x81, MRM7r,
2342 (outs), (ins GR16:$src1, i16imm:$src2),
2343 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2344 [(X86cmp GR16:$src1, imm:$src2),
2345 (implicit EFLAGS)]>, OpSize;
2346 def CMP32ri : Ii32<0x81, MRM7r,
2347 (outs), (ins GR32:$src1, i32imm:$src2),
2348 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2349 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
2350 def CMP8mi : Ii8 <0x80, MRM7m,
2351 (outs), (ins i8mem :$src1, i8imm :$src2),
2352 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2353 [(X86cmp (loadi8 addr:$src1), imm:$src2),
2354 (implicit EFLAGS)]>;
2355 def CMP16mi : Ii16<0x81, MRM7m,
2356 (outs), (ins i16mem:$src1, i16imm:$src2),
2357 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2358 [(X86cmp (loadi16 addr:$src1), imm:$src2),
2359 (implicit EFLAGS)]>, OpSize;
2360 def CMP32mi : Ii32<0x81, MRM7m,
2361 (outs), (ins i32mem:$src1, i32imm:$src2),
2362 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2363 [(X86cmp (loadi32 addr:$src1), imm:$src2),
2364 (implicit EFLAGS)]>;
2365 def CMP16ri8 : Ii8<0x83, MRM7r,
2366 (outs), (ins GR16:$src1, i16i8imm:$src2),
2367 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2368 [(X86cmp GR16:$src1, i16immSExt8:$src2),
2369 (implicit EFLAGS)]>, OpSize;
2370 def CMP16mi8 : Ii8<0x83, MRM7m,
2371 (outs), (ins i16mem:$src1, i16i8imm:$src2),
2372 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2373 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
2374 (implicit EFLAGS)]>, OpSize;
2375 def CMP32mi8 : Ii8<0x83, MRM7m,
2376 (outs), (ins i32mem:$src1, i32i8imm:$src2),
2377 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2378 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
2379 (implicit EFLAGS)]>;
2380 def CMP32ri8 : Ii8<0x83, MRM7r,
2381 (outs), (ins GR32:$src1, i32i8imm:$src2),
2382 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2383 [(X86cmp GR32:$src1, i32immSExt8:$src2),
2384 (implicit EFLAGS)]>;
2385 } // Defs = [EFLAGS]
2387 // Sign/Zero extenders
2388 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2389 "movs{bw|x}\t{$src, $dst|$dst, $src}",
2390 [(set GR16:$dst, (sext GR8:$src))]>, TB, OpSize;
2391 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2392 "movs{bw|x}\t{$src, $dst|$dst, $src}",
2393 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize;
2394 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2395 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2396 [(set GR32:$dst, (sext GR8:$src))]>, TB;
2397 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2398 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2399 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
2400 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2401 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2402 [(set GR32:$dst, (sext GR16:$src))]>, TB;
2403 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2404 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2405 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
2407 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2408 "movz{bw|x}\t{$src, $dst|$dst, $src}",
2409 [(set GR16:$dst, (zext GR8:$src))]>, TB, OpSize;
2410 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2411 "movz{bw|x}\t{$src, $dst|$dst, $src}",
2412 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize;
2413 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2414 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2415 [(set GR32:$dst, (zext GR8:$src))]>, TB;
2416 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2417 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2418 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
2419 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2420 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2421 [(set GR32:$dst, (zext GR16:$src))]>, TB;
2422 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2423 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2424 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
2426 let neverHasSideEffects = 1 in {
2427 let Defs = [AX], Uses = [AL] in
2428 def CBW : I<0x98, RawFrm, (outs), (ins),
2429 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
2430 let Defs = [EAX], Uses = [AX] in
2431 def CWDE : I<0x98, RawFrm, (outs), (ins),
2432 "{cwtl|cwde}", []>; // EAX = signext(AX)
2434 let Defs = [AX,DX], Uses = [AX] in
2435 def CWD : I<0x99, RawFrm, (outs), (ins),
2436 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
2437 let Defs = [EAX,EDX], Uses = [EAX] in
2438 def CDQ : I<0x99, RawFrm, (outs), (ins),
2439 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
2442 //===----------------------------------------------------------------------===//
2443 // Alias Instructions
2444 //===----------------------------------------------------------------------===//
2446 // Alias instructions that map movr0 to xor.
2447 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2448 let Defs = [EFLAGS], isReMaterializable = 1 in {
2449 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
2450 "xor{b}\t$dst, $dst",
2451 [(set GR8:$dst, 0)]>;
2452 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
2453 "xor{w}\t$dst, $dst",
2454 [(set GR16:$dst, 0)]>, OpSize;
2455 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
2456 "xor{l}\t$dst, $dst",
2457 [(set GR32:$dst, 0)]>;
2460 // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
2461 // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
2462 let neverHasSideEffects = 1 in {
2463 def MOV16to16_ : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16:$src),
2464 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2465 def MOV32to32_ : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32:$src),
2466 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2468 def MOV16_rr : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16_:$src),
2469 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2470 def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src),
2471 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2472 } // neverHasSideEffects
2474 let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
2475 def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src),
2476 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2477 def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src),
2478 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2480 let mayStore = 1, neverHasSideEffects = 1 in {
2481 def MOV16_mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16_:$src),
2482 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2483 def MOV32_mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32_:$src),
2484 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2487 //===----------------------------------------------------------------------===//
2488 // Thread Local Storage Instructions
2492 def TLS_addr : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
2493 "leal\t${sym:mem}(,%ebx,1), $dst",
2494 [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
2496 let AddedComplexity = 10 in
2497 def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
2498 "movl\t%gs:($src), $dst",
2499 [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
2501 let AddedComplexity = 15 in
2502 def TLS_gs_ri : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
2503 "movl\t%gs:${src:mem}, $dst",
2505 (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>;
2507 def TLS_tp : I<0, Pseudo, (outs GR32:$dst), (ins),
2508 "movl\t%gs:0, $dst",
2509 [(set GR32:$dst, X86TLStp)]>;
2511 //===----------------------------------------------------------------------===//
2512 // DWARF Pseudo Instructions
2515 def DWARF_LOC : I<0, Pseudo, (outs),
2516 (ins i32imm:$line, i32imm:$col, i32imm:$file),
2517 ".loc\t${file:debug} ${line:debug} ${col:debug}",
2518 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
2521 //===----------------------------------------------------------------------===//
2522 // EH Pseudo Instructions
2524 let isTerminator = 1, isReturn = 1, isBarrier = 1,
2526 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
2527 "ret\t#eh_return, addr: $addr",
2528 [(X86ehret GR32:$addr)]>;
2532 //===----------------------------------------------------------------------===//
2533 // Non-Instruction Patterns
2534 //===----------------------------------------------------------------------===//
2536 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
2537 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
2538 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
2539 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)), (MOV32ri tglobaltlsaddr:$dst)>;
2540 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
2541 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
2543 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
2544 (ADD32ri GR32:$src1, tconstpool:$src2)>;
2545 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
2546 (ADD32ri GR32:$src1, tjumptable:$src2)>;
2547 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
2548 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
2549 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
2550 (ADD32ri GR32:$src1, texternalsym:$src2)>;
2552 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
2553 (MOV32mi addr:$dst, tglobaladdr:$src)>;
2554 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
2555 (MOV32mi addr:$dst, texternalsym:$src)>;
2559 def : Pat<(X86tailcall GR32:$dst),
2562 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
2564 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
2567 def : Pat<(X86tcret GR32:$dst, imm:$off),
2568 (TCRETURNri GR32:$dst, imm:$off)>;
2570 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
2571 (TCRETURNdi texternalsym:$dst, imm:$off)>;
2573 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
2574 (TCRETURNdi texternalsym:$dst, imm:$off)>;
2576 def : Pat<(X86call (i32 tglobaladdr:$dst)),
2577 (CALLpcrel32 tglobaladdr:$dst)>;
2578 def : Pat<(X86call (i32 texternalsym:$dst)),
2579 (CALLpcrel32 texternalsym:$dst)>;
2581 // X86 specific add which produces a flag.
2582 def : Pat<(addc GR32:$src1, GR32:$src2),
2583 (ADD32rr GR32:$src1, GR32:$src2)>;
2584 def : Pat<(addc GR32:$src1, (load addr:$src2)),
2585 (ADD32rm GR32:$src1, addr:$src2)>;
2586 def : Pat<(addc GR32:$src1, imm:$src2),
2587 (ADD32ri GR32:$src1, imm:$src2)>;
2588 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
2589 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
2591 def : Pat<(subc GR32:$src1, GR32:$src2),
2592 (SUB32rr GR32:$src1, GR32:$src2)>;
2593 def : Pat<(subc GR32:$src1, (load addr:$src2)),
2594 (SUB32rm GR32:$src1, addr:$src2)>;
2595 def : Pat<(subc GR32:$src1, imm:$src2),
2596 (SUB32ri GR32:$src1, imm:$src2)>;
2597 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
2598 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
2602 // TEST R,R is smaller than CMP R,0
2603 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
2604 (TEST8rr GR8:$src1, GR8:$src1)>;
2605 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
2606 (TEST16rr GR16:$src1, GR16:$src1)>;
2607 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
2608 (TEST32rr GR32:$src1, GR32:$src1)>;
2610 // zextload bool -> zextload byte
2611 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2612 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2613 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2615 // extload bool -> extload byte
2616 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2617 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2618 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2619 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
2620 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
2621 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
2624 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
2625 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
2626 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
2627 def : Pat<(i16 (anyext (loadi8 addr:$src))), (MOVZX16rm8 addr:$src)>;
2628 def : Pat<(i32 (anyext (loadi8 addr:$src))), (MOVZX32rm8 addr:$src)>;
2629 def : Pat<(i32 (anyext (loadi16 addr:$src))), (MOVZX32rm16 addr:$src)>;
2631 // (and (i32 load), 255) -> (zextload i8)
2632 def : Pat<(i32 (and (loadi32 addr:$src), (i32 255))), (MOVZX32rm8 addr:$src)>;
2633 def : Pat<(i32 (and (loadi32 addr:$src), (i32 65535))),(MOVZX32rm16 addr:$src)>;
2635 //===----------------------------------------------------------------------===//
2637 //===----------------------------------------------------------------------===//
2639 // (shl x, 1) ==> (add x, x)
2640 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
2641 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
2642 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
2644 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
2645 def : Pat<(or (srl GR32:$src1, CL:$amt),
2646 (shl GR32:$src2, (sub 32, CL:$amt))),
2647 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
2649 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
2650 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2651 (SHRD32mrCL addr:$dst, GR32:$src2)>;
2653 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
2654 def : Pat<(or (shl GR32:$src1, CL:$amt),
2655 (srl GR32:$src2, (sub 32, CL:$amt))),
2656 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
2658 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
2659 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2660 (SHLD32mrCL addr:$dst, GR32:$src2)>;
2662 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
2663 def : Pat<(or (srl GR16:$src1, CL:$amt),
2664 (shl GR16:$src2, (sub 16, CL:$amt))),
2665 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
2667 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
2668 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2669 (SHRD16mrCL addr:$dst, GR16:$src2)>;
2671 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
2672 def : Pat<(or (shl GR16:$src1, CL:$amt),
2673 (srl GR16:$src2, (sub 16, CL:$amt))),
2674 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
2676 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
2677 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2678 (SHLD16mrCL addr:$dst, GR16:$src2)>;
2681 //===----------------------------------------------------------------------===//
2682 // Floating Point Stack Support
2683 //===----------------------------------------------------------------------===//
2685 include "X86InstrFPStack.td"
2687 //===----------------------------------------------------------------------===//
2689 //===----------------------------------------------------------------------===//
2691 include "X86Instr64bit.td"
2693 //===----------------------------------------------------------------------===//
2694 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
2695 //===----------------------------------------------------------------------===//
2697 include "X86InstrMMX.td"
2699 //===----------------------------------------------------------------------===//
2700 // XMM Floating point support (requires SSE / SSE2)
2701 //===----------------------------------------------------------------------===//
2703 include "X86InstrSSE.td"