1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 def SDTUnaryArithOvf : SDTypeProfile<1, 1,
32 def SDTBinaryArithOvf : SDTypeProfile<1, 2,
33 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
36 def SDTX86BrCond : SDTypeProfile<0, 3,
37 [SDTCisVT<0, OtherVT>,
38 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
40 def SDTX86SetCC : SDTypeProfile<1, 2,
42 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
44 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
46 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
48 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
49 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
50 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
52 def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
53 def SDT_X86CallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
56 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
58 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
60 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
62 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
64 def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
66 def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
68 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
70 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
72 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
73 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
74 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
75 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
77 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
79 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
81 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
82 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
84 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
86 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
87 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
89 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
90 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
92 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
93 [SDNPHasChain, SDNPMayStore,
94 SDNPMayLoad, SDNPMemOperand]>;
95 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
96 [SDNPHasChain, SDNPMayStore,
97 SDNPMayLoad, SDNPMemOperand]>;
98 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
99 [SDNPHasChain, SDNPMayStore,
100 SDNPMayLoad, SDNPMemOperand]>;
101 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
102 [SDNPHasChain, SDNPMayStore,
103 SDNPMayLoad, SDNPMemOperand]>;
104 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
105 [SDNPHasChain, SDNPMayStore,
106 SDNPMayLoad, SDNPMemOperand]>;
107 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
108 [SDNPHasChain, SDNPMayStore,
109 SDNPMayLoad, SDNPMemOperand]>;
110 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
111 [SDNPHasChain, SDNPMayStore,
112 SDNPMayLoad, SDNPMemOperand]>;
113 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
114 [SDNPHasChain, SDNPOptInFlag]>;
116 def X86callseq_start :
117 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
118 [SDNPHasChain, SDNPOutFlag]>;
120 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
121 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
123 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
124 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
126 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
127 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
129 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
130 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
131 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
132 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
135 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
136 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
138 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
139 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
141 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
142 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
143 def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
145 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
148 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
149 [SDNPHasChain, SDNPOptInFlag]>;
151 def X86add_ovf : SDNode<"X86ISD::ADD", SDTBinaryArithOvf>;
152 def X86sub_ovf : SDNode<"X86ISD::SUB", SDTBinaryArithOvf>;
153 def X86smul_ovf : SDNode<"X86ISD::SMUL", SDTBinaryArithOvf>;
154 def X86umul_ovf : SDNode<"X86ISD::UMUL", SDTUnaryArithOvf>;
156 //===----------------------------------------------------------------------===//
157 // X86 Operand Definitions.
160 // *mem - Operand definitions for the funky X86 addressing mode operands.
162 class X86MemOperand<string printMethod> : Operand<iPTR> {
163 let PrintMethod = printMethod;
164 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
167 def i8mem : X86MemOperand<"printi8mem">;
168 def i16mem : X86MemOperand<"printi16mem">;
169 def i32mem : X86MemOperand<"printi32mem">;
170 def i64mem : X86MemOperand<"printi64mem">;
171 def i128mem : X86MemOperand<"printi128mem">;
172 def f32mem : X86MemOperand<"printf32mem">;
173 def f64mem : X86MemOperand<"printf64mem">;
174 def f80mem : X86MemOperand<"printf80mem">;
175 def f128mem : X86MemOperand<"printf128mem">;
177 def lea32mem : Operand<i32> {
178 let PrintMethod = "printi32mem";
179 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
182 def SSECC : Operand<i8> {
183 let PrintMethod = "printSSECC";
186 def piclabel: Operand<i32> {
187 let PrintMethod = "printPICLabel";
190 // A couple of more descriptive operand definitions.
191 // 16-bits but only 8 bits are significant.
192 def i16i8imm : Operand<i16>;
193 // 32-bits but only 8 bits are significant.
194 def i32i8imm : Operand<i32>;
196 // Branch targets have OtherVT type.
197 def brtarget : Operand<OtherVT>;
199 //===----------------------------------------------------------------------===//
200 // X86 Complex Pattern Definitions.
203 // Define X86 specific addressing mode.
204 def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
205 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
206 [add, mul, shl, or, frameindex], []>;
208 //===----------------------------------------------------------------------===//
209 // X86 Instruction Predicate Definitions.
210 def HasMMX : Predicate<"Subtarget->hasMMX()">;
211 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
212 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
213 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
214 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
215 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
216 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
217 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
218 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
219 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
220 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
221 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
222 def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
223 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
224 def OptForSpeed : Predicate<"!OptForSize">;
225 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
227 //===----------------------------------------------------------------------===//
228 // X86 Instruction Format Definitions.
231 include "X86InstrFormats.td"
233 //===----------------------------------------------------------------------===//
234 // Pattern fragments...
237 // X86 specific condition code. These correspond to CondCode in
238 // X86InstrInfo.h. They must be kept in synch.
239 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
240 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
241 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
242 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
243 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
244 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
245 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
246 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
247 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
248 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
249 def X86_COND_NO : PatLeaf<(i8 10)>;
250 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
251 def X86_COND_NS : PatLeaf<(i8 12)>;
252 def X86_COND_O : PatLeaf<(i8 13)>;
253 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
254 def X86_COND_S : PatLeaf<(i8 15)>;
256 def i16immSExt8 : PatLeaf<(i16 imm), [{
257 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
258 // sign extended field.
259 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
262 def i32immSExt8 : PatLeaf<(i32 imm), [{
263 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
264 // sign extended field.
265 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
268 // Helper fragments for loads.
269 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
270 // known to be 32-bit aligned or better. Ditto for i8 to i16.
271 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
272 LoadSDNode *LD = cast<LoadSDNode>(N);
273 ISD::LoadExtType ExtType = LD->getExtensionType();
274 if (ExtType == ISD::NON_EXTLOAD)
276 if (ExtType == ISD::EXTLOAD)
277 return LD->getAlignment() >= 2 && !LD->isVolatile();
281 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
282 LoadSDNode *LD = cast<LoadSDNode>(N);
283 ISD::LoadExtType ExtType = LD->getExtensionType();
284 if (ExtType == ISD::EXTLOAD)
285 return LD->getAlignment() >= 2 && !LD->isVolatile();
289 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
290 LoadSDNode *LD = cast<LoadSDNode>(N);
291 ISD::LoadExtType ExtType = LD->getExtensionType();
292 if (ExtType == ISD::NON_EXTLOAD)
294 if (ExtType == ISD::EXTLOAD)
295 return LD->getAlignment() >= 4 && !LD->isVolatile();
299 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
300 LoadSDNode *LD = cast<LoadSDNode>(N);
301 if (LD->isVolatile())
303 ISD::LoadExtType ExtType = LD->getExtensionType();
304 if (ExtType == ISD::NON_EXTLOAD)
306 if (ExtType == ISD::EXTLOAD)
307 return LD->getAlignment() >= 4;
311 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
312 LoadSDNode *LD = cast<LoadSDNode>(N);
313 const Value *Src = LD->getSrcValue();
316 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
317 return PT->getAddressSpace() == 256;
321 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
322 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
324 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
325 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
326 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
328 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
329 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
330 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
332 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
333 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
334 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
335 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
336 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
337 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
339 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
340 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
341 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
342 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
343 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
344 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
347 // An 'and' node with a single use.
348 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
349 return N->hasOneUse();
352 // 'shld' and 'shrd' instruction patterns. Note that even though these have
353 // the srl and shl in their patterns, the C++ code must still check for them,
354 // because predicates are tested before children nodes are explored.
356 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
357 (or (srl node:$src1, node:$amt1),
358 (shl node:$src2, node:$amt2)), [{
359 assert(N->getOpcode() == ISD::OR);
360 return N->getOperand(0).getOpcode() == ISD::SRL &&
361 N->getOperand(1).getOpcode() == ISD::SHL &&
362 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
363 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
364 N->getOperand(0).getConstantOperandVal(1) ==
365 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
368 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
369 (or (shl node:$src1, node:$amt1),
370 (srl node:$src2, node:$amt2)), [{
371 assert(N->getOpcode() == ISD::OR);
372 return N->getOperand(0).getOpcode() == ISD::SHL &&
373 N->getOperand(1).getOpcode() == ISD::SRL &&
374 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
375 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
376 N->getOperand(0).getConstantOperandVal(1) ==
377 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
380 //===----------------------------------------------------------------------===//
381 // Instruction list...
384 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
385 // a stack adjustment and the codegen must know that they may modify the stack
386 // pointer before prolog-epilog rewriting occurs.
387 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
388 // sub / add which can clobber EFLAGS.
389 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
390 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
392 [(X86callseq_start timm:$amt)]>,
393 Requires<[In32BitMode]>;
394 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
396 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
397 Requires<[In32BitMode]>;
401 let neverHasSideEffects = 1 in
402 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
405 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
406 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
407 "call\t$label\n\tpop{l}\t$reg", []>;
409 //===----------------------------------------------------------------------===//
410 // Control Flow Instructions...
413 // Return instructions.
414 let isTerminator = 1, isReturn = 1, isBarrier = 1,
415 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
416 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
419 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
421 [(X86retflag imm:$amt)]>;
424 // All branches are RawFrm, Void, Branch, and Terminators
425 let isBranch = 1, isTerminator = 1 in
426 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
427 I<opcode, RawFrm, (outs), ins, asm, pattern>;
429 let isBranch = 1, isBarrier = 1 in
430 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
433 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
434 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
435 [(brind GR32:$dst)]>;
436 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
437 [(brind (loadi32 addr:$dst))]>;
440 // Conditional branches
441 let Uses = [EFLAGS] in {
442 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
443 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
444 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
445 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
446 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
447 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
448 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
449 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
450 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
451 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
452 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
453 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
455 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
456 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
457 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
458 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
459 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
460 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
461 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
462 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
464 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
465 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
466 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
467 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
468 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
469 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
470 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
471 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
472 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
473 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
474 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
475 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
478 //===----------------------------------------------------------------------===//
479 // Call Instructions...
482 // All calls clobber the non-callee saved registers. ESP is marked as
483 // a use to prevent stack-pointer assignments that appear immediately
484 // before calls from potentially appearing dead. Uses for argument
485 // registers are added manually.
486 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
487 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
488 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
489 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
491 def CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:$dst,variable_ops),
492 "call\t${dst:call}", []>;
493 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
494 "call\t{*}$dst", [(X86call GR32:$dst)]>;
495 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
496 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
501 def TAILCALL : I<0, Pseudo, (outs), (ins),
505 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
506 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops),
507 "#TC_RETURN $dst $offset",
510 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
511 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops),
512 "#TC_RETURN $dst $offset",
515 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
517 def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAILCALL",
519 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
520 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
522 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
523 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
524 "jmp\t{*}$dst # TAILCALL", []>;
526 //===----------------------------------------------------------------------===//
527 // Miscellaneous Instructions...
529 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
530 def LEAVE : I<0xC9, RawFrm,
531 (outs), (ins), "leave", []>;
533 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
535 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
538 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
541 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
542 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
543 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
544 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
546 let isTwoAddress = 1 in // GR32 = bswap GR32
547 def BSWAP32r : I<0xC8, AddRegFrm,
548 (outs GR32:$dst), (ins GR32:$src),
550 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
553 // Bit scan instructions.
554 let Defs = [EFLAGS] in {
555 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
556 "bsf{w}\t{$src, $dst|$dst, $src}",
557 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
558 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
559 "bsf{w}\t{$src, $dst|$dst, $src}",
560 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
561 (implicit EFLAGS)]>, TB;
562 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
563 "bsf{l}\t{$src, $dst|$dst, $src}",
564 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
565 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
566 "bsf{l}\t{$src, $dst|$dst, $src}",
567 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
568 (implicit EFLAGS)]>, TB;
570 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
571 "bsr{w}\t{$src, $dst|$dst, $src}",
572 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
573 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
574 "bsr{w}\t{$src, $dst|$dst, $src}",
575 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
576 (implicit EFLAGS)]>, TB;
577 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
578 "bsr{l}\t{$src, $dst|$dst, $src}",
579 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
580 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
581 "bsr{l}\t{$src, $dst|$dst, $src}",
582 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
583 (implicit EFLAGS)]>, TB;
586 let neverHasSideEffects = 1 in
587 def LEA16r : I<0x8D, MRMSrcMem,
588 (outs GR16:$dst), (ins i32mem:$src),
589 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
590 let isReMaterializable = 1 in
591 def LEA32r : I<0x8D, MRMSrcMem,
592 (outs GR32:$dst), (ins lea32mem:$src),
593 "lea{l}\t{$src|$dst}, {$dst|$src}",
594 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
596 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
597 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
598 [(X86rep_movs i8)]>, REP;
599 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
600 [(X86rep_movs i16)]>, REP, OpSize;
601 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
602 [(X86rep_movs i32)]>, REP;
605 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
606 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
607 [(X86rep_stos i8)]>, REP;
608 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
609 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
610 [(X86rep_stos i16)]>, REP, OpSize;
611 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
612 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
613 [(X86rep_stos i32)]>, REP;
615 let Defs = [RAX, RDX] in
616 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
619 let isBarrier = 1, hasCtrlDep = 1 in {
620 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
623 //===----------------------------------------------------------------------===//
624 // Input/Output Instructions...
626 let Defs = [AL], Uses = [DX] in
627 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
628 "in{b}\t{%dx, %al|%AL, %DX}", []>;
629 let Defs = [AX], Uses = [DX] in
630 def IN16rr : I<0xED, RawFrm, (outs), (ins),
631 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
632 let Defs = [EAX], Uses = [DX] in
633 def IN32rr : I<0xED, RawFrm, (outs), (ins),
634 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
637 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
638 "in{b}\t{$port, %al|%AL, $port}", []>;
640 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
641 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
643 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
644 "in{l}\t{$port, %eax|%EAX, $port}", []>;
646 let Uses = [DX, AL] in
647 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
648 "out{b}\t{%al, %dx|%DX, %AL}", []>;
649 let Uses = [DX, AX] in
650 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
651 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
652 let Uses = [DX, EAX] in
653 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
654 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
657 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
658 "out{b}\t{%al, $port|$port, %AL}", []>;
660 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
661 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
663 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
664 "out{l}\t{%eax, $port|$port, %EAX}", []>;
666 //===----------------------------------------------------------------------===//
667 // Move Instructions...
669 let neverHasSideEffects = 1 in {
670 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
671 "mov{b}\t{$src, $dst|$dst, $src}", []>;
672 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
673 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
674 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
675 "mov{l}\t{$src, $dst|$dst, $src}", []>;
677 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
678 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
679 "mov{b}\t{$src, $dst|$dst, $src}",
680 [(set GR8:$dst, imm:$src)]>;
681 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
682 "mov{w}\t{$src, $dst|$dst, $src}",
683 [(set GR16:$dst, imm:$src)]>, OpSize;
684 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
685 "mov{l}\t{$src, $dst|$dst, $src}",
686 [(set GR32:$dst, imm:$src)]>;
688 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
689 "mov{b}\t{$src, $dst|$dst, $src}",
690 [(store (i8 imm:$src), addr:$dst)]>;
691 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
692 "mov{w}\t{$src, $dst|$dst, $src}",
693 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
694 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
695 "mov{l}\t{$src, $dst|$dst, $src}",
696 [(store (i32 imm:$src), addr:$dst)]>;
698 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
699 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
700 "mov{b}\t{$src, $dst|$dst, $src}",
701 [(set GR8:$dst, (load addr:$src))]>;
702 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
703 "mov{w}\t{$src, $dst|$dst, $src}",
704 [(set GR16:$dst, (load addr:$src))]>, OpSize;
705 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
706 "mov{l}\t{$src, $dst|$dst, $src}",
707 [(set GR32:$dst, (load addr:$src))]>;
710 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
711 "mov{b}\t{$src, $dst|$dst, $src}",
712 [(store GR8:$src, addr:$dst)]>;
713 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
714 "mov{w}\t{$src, $dst|$dst, $src}",
715 [(store GR16:$src, addr:$dst)]>, OpSize;
716 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
717 "mov{l}\t{$src, $dst|$dst, $src}",
718 [(store GR32:$src, addr:$dst)]>;
720 //===----------------------------------------------------------------------===//
721 // Fixed-Register Multiplication and Division Instructions...
724 // Extra precision multiplication
725 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
726 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
727 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
728 // This probably ought to be moved to a def : Pat<> if the
729 // syntax can be accepted.
730 [(set AL, (mul AL, GR8:$src)),
731 (implicit EFLAGS)]>; // AL,AH = AL*GR8
733 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
734 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
736 []>, OpSize; // AX,DX = AX*GR16
738 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
739 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
741 []>; // EAX,EDX = EAX*GR32
743 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
744 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
746 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
747 // This probably ought to be moved to a def : Pat<> if the
748 // syntax can be accepted.
749 [(set AL, (mul AL, (loadi8 addr:$src))),
750 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
752 let mayLoad = 1, neverHasSideEffects = 1 in {
753 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
754 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
756 []>, OpSize; // AX,DX = AX*[mem16]
758 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
759 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
761 []>; // EAX,EDX = EAX*[mem32]
764 let neverHasSideEffects = 1 in {
765 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
766 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
768 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
769 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
770 OpSize; // AX,DX = AX*GR16
771 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
772 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
773 // EAX,EDX = EAX*GR32
775 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
776 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
777 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
778 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
779 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
780 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
781 let Defs = [EAX,EDX], Uses = [EAX] in
782 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
783 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
785 } // neverHasSideEffects
787 // unsigned division/remainder
788 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
789 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
791 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
792 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
793 "div{w}\t$src", []>, OpSize;
794 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
795 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
798 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
799 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
801 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
802 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
803 "div{w}\t$src", []>, OpSize;
804 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
805 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
809 // Signed division/remainder.
810 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
811 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
812 "idiv{b}\t$src", []>;
813 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
814 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
815 "idiv{w}\t$src", []>, OpSize;
816 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
817 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
818 "idiv{l}\t$src", []>;
819 let mayLoad = 1, mayLoad = 1 in {
820 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
821 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
822 "idiv{b}\t$src", []>;
823 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
824 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
825 "idiv{w}\t$src", []>, OpSize;
826 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
827 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
828 "idiv{l}\t$src", []>;
831 //===----------------------------------------------------------------------===//
832 // Two address Instructions.
834 let isTwoAddress = 1 in {
837 let Uses = [EFLAGS] in {
838 let isCommutable = 1 in {
839 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
840 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
841 "cmovb\t{$src2, $dst|$dst, $src2}",
842 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
843 X86_COND_B, EFLAGS))]>,
845 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
846 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
847 "cmovb\t{$src2, $dst|$dst, $src2}",
848 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
849 X86_COND_B, EFLAGS))]>,
851 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
852 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
853 "cmovae\t{$src2, $dst|$dst, $src2}",
854 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
855 X86_COND_AE, EFLAGS))]>,
857 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
858 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
859 "cmovae\t{$src2, $dst|$dst, $src2}",
860 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
861 X86_COND_AE, EFLAGS))]>,
863 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
864 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
865 "cmove\t{$src2, $dst|$dst, $src2}",
866 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
867 X86_COND_E, EFLAGS))]>,
869 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
870 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
871 "cmove\t{$src2, $dst|$dst, $src2}",
872 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
873 X86_COND_E, EFLAGS))]>,
875 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
876 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
877 "cmovne\t{$src2, $dst|$dst, $src2}",
878 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
879 X86_COND_NE, EFLAGS))]>,
881 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
882 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
883 "cmovne\t{$src2, $dst|$dst, $src2}",
884 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
885 X86_COND_NE, EFLAGS))]>,
887 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
888 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
889 "cmovbe\t{$src2, $dst|$dst, $src2}",
890 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
891 X86_COND_BE, EFLAGS))]>,
893 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
894 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
895 "cmovbe\t{$src2, $dst|$dst, $src2}",
896 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
897 X86_COND_BE, EFLAGS))]>,
899 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
900 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
901 "cmova\t{$src2, $dst|$dst, $src2}",
902 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
903 X86_COND_A, EFLAGS))]>,
905 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
906 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
907 "cmova\t{$src2, $dst|$dst, $src2}",
908 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
909 X86_COND_A, EFLAGS))]>,
911 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
912 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
913 "cmovl\t{$src2, $dst|$dst, $src2}",
914 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
915 X86_COND_L, EFLAGS))]>,
917 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
918 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
919 "cmovl\t{$src2, $dst|$dst, $src2}",
920 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
921 X86_COND_L, EFLAGS))]>,
923 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
924 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
925 "cmovge\t{$src2, $dst|$dst, $src2}",
926 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
927 X86_COND_GE, EFLAGS))]>,
929 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
930 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
931 "cmovge\t{$src2, $dst|$dst, $src2}",
932 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
933 X86_COND_GE, EFLAGS))]>,
935 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
936 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
937 "cmovle\t{$src2, $dst|$dst, $src2}",
938 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
939 X86_COND_LE, EFLAGS))]>,
941 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
942 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
943 "cmovle\t{$src2, $dst|$dst, $src2}",
944 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
945 X86_COND_LE, EFLAGS))]>,
947 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
948 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
949 "cmovg\t{$src2, $dst|$dst, $src2}",
950 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
951 X86_COND_G, EFLAGS))]>,
953 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
954 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
955 "cmovg\t{$src2, $dst|$dst, $src2}",
956 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
957 X86_COND_G, EFLAGS))]>,
959 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
960 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
961 "cmovs\t{$src2, $dst|$dst, $src2}",
962 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
963 X86_COND_S, EFLAGS))]>,
965 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
966 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
967 "cmovs\t{$src2, $dst|$dst, $src2}",
968 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
969 X86_COND_S, EFLAGS))]>,
971 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
972 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
973 "cmovns\t{$src2, $dst|$dst, $src2}",
974 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
975 X86_COND_NS, EFLAGS))]>,
977 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
978 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
979 "cmovns\t{$src2, $dst|$dst, $src2}",
980 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
981 X86_COND_NS, EFLAGS))]>,
983 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
984 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
985 "cmovp\t{$src2, $dst|$dst, $src2}",
986 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
987 X86_COND_P, EFLAGS))]>,
989 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
990 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
991 "cmovp\t{$src2, $dst|$dst, $src2}",
992 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
993 X86_COND_P, EFLAGS))]>,
995 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
996 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
997 "cmovnp\t{$src2, $dst|$dst, $src2}",
998 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
999 X86_COND_NP, EFLAGS))]>,
1001 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1002 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1003 "cmovnp\t{$src2, $dst|$dst, $src2}",
1004 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1005 X86_COND_NP, EFLAGS))]>,
1007 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1008 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1009 "cmovo\t{$src2, $dst|$dst, $src2}",
1010 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1011 X86_COND_O, EFLAGS))]>,
1013 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1014 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1015 "cmovo\t{$src2, $dst|$dst, $src2}",
1016 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1017 X86_COND_O, EFLAGS))]>,
1019 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1020 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1021 "cmovno\t{$src2, $dst|$dst, $src2}",
1022 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1023 X86_COND_NO, EFLAGS))]>,
1025 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1026 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1027 "cmovno\t{$src2, $dst|$dst, $src2}",
1028 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1029 X86_COND_NO, EFLAGS))]>,
1031 } // isCommutable = 1
1033 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1034 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1035 "cmovb\t{$src2, $dst|$dst, $src2}",
1036 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1037 X86_COND_B, EFLAGS))]>,
1039 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1040 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1041 "cmovb\t{$src2, $dst|$dst, $src2}",
1042 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1043 X86_COND_B, EFLAGS))]>,
1045 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1046 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1047 "cmovae\t{$src2, $dst|$dst, $src2}",
1048 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1049 X86_COND_AE, EFLAGS))]>,
1051 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1052 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1053 "cmovae\t{$src2, $dst|$dst, $src2}",
1054 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1055 X86_COND_AE, EFLAGS))]>,
1057 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1058 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1059 "cmove\t{$src2, $dst|$dst, $src2}",
1060 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1061 X86_COND_E, EFLAGS))]>,
1063 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1064 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1065 "cmove\t{$src2, $dst|$dst, $src2}",
1066 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1067 X86_COND_E, EFLAGS))]>,
1069 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1070 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1071 "cmovne\t{$src2, $dst|$dst, $src2}",
1072 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1073 X86_COND_NE, EFLAGS))]>,
1075 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1076 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1077 "cmovne\t{$src2, $dst|$dst, $src2}",
1078 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1079 X86_COND_NE, EFLAGS))]>,
1081 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1082 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1083 "cmovbe\t{$src2, $dst|$dst, $src2}",
1084 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1085 X86_COND_BE, EFLAGS))]>,
1087 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1088 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1089 "cmovbe\t{$src2, $dst|$dst, $src2}",
1090 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1091 X86_COND_BE, EFLAGS))]>,
1093 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1094 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1095 "cmova\t{$src2, $dst|$dst, $src2}",
1096 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1097 X86_COND_A, EFLAGS))]>,
1099 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1100 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1101 "cmova\t{$src2, $dst|$dst, $src2}",
1102 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1103 X86_COND_A, EFLAGS))]>,
1105 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1106 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1107 "cmovl\t{$src2, $dst|$dst, $src2}",
1108 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1109 X86_COND_L, EFLAGS))]>,
1111 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1112 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1113 "cmovl\t{$src2, $dst|$dst, $src2}",
1114 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1115 X86_COND_L, EFLAGS))]>,
1117 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1118 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1119 "cmovge\t{$src2, $dst|$dst, $src2}",
1120 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1121 X86_COND_GE, EFLAGS))]>,
1123 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1124 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1125 "cmovge\t{$src2, $dst|$dst, $src2}",
1126 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1127 X86_COND_GE, EFLAGS))]>,
1129 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1130 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1131 "cmovle\t{$src2, $dst|$dst, $src2}",
1132 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1133 X86_COND_LE, EFLAGS))]>,
1135 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1136 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1137 "cmovle\t{$src2, $dst|$dst, $src2}",
1138 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1139 X86_COND_LE, EFLAGS))]>,
1141 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1142 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1143 "cmovg\t{$src2, $dst|$dst, $src2}",
1144 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1145 X86_COND_G, EFLAGS))]>,
1147 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1148 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1149 "cmovg\t{$src2, $dst|$dst, $src2}",
1150 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1151 X86_COND_G, EFLAGS))]>,
1153 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1154 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1155 "cmovs\t{$src2, $dst|$dst, $src2}",
1156 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1157 X86_COND_S, EFLAGS))]>,
1159 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1160 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1161 "cmovs\t{$src2, $dst|$dst, $src2}",
1162 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1163 X86_COND_S, EFLAGS))]>,
1165 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1166 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1167 "cmovns\t{$src2, $dst|$dst, $src2}",
1168 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1169 X86_COND_NS, EFLAGS))]>,
1171 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1172 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1173 "cmovns\t{$src2, $dst|$dst, $src2}",
1174 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1175 X86_COND_NS, EFLAGS))]>,
1177 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1178 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1179 "cmovp\t{$src2, $dst|$dst, $src2}",
1180 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1181 X86_COND_P, EFLAGS))]>,
1183 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1184 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1185 "cmovp\t{$src2, $dst|$dst, $src2}",
1186 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1187 X86_COND_P, EFLAGS))]>,
1189 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1190 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1191 "cmovnp\t{$src2, $dst|$dst, $src2}",
1192 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1193 X86_COND_NP, EFLAGS))]>,
1195 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1196 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1197 "cmovnp\t{$src2, $dst|$dst, $src2}",
1198 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1199 X86_COND_NP, EFLAGS))]>,
1201 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1202 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1203 "cmovo\t{$src2, $dst|$dst, $src2}",
1204 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1205 X86_COND_O, EFLAGS))]>,
1207 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1208 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1209 "cmovo\t{$src2, $dst|$dst, $src2}",
1210 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1211 X86_COND_O, EFLAGS))]>,
1213 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1214 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1215 "cmovno\t{$src2, $dst|$dst, $src2}",
1216 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1217 X86_COND_NO, EFLAGS))]>,
1219 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1220 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1221 "cmovno\t{$src2, $dst|$dst, $src2}",
1222 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1223 X86_COND_NO, EFLAGS))]>,
1225 } // Uses = [EFLAGS]
1228 // unary instructions
1229 let CodeSize = 2 in {
1230 let Defs = [EFLAGS] in {
1231 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1232 [(set GR8:$dst, (ineg GR8:$src))]>;
1233 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1234 [(set GR16:$dst, (ineg GR16:$src))]>, OpSize;
1235 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1236 [(set GR32:$dst, (ineg GR32:$src))]>;
1237 let isTwoAddress = 0 in {
1238 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1239 [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
1240 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1241 [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1242 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1243 [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
1246 } // Defs = [EFLAGS]
1248 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1249 let AddedComplexity = 15 in {
1250 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1251 [(set GR8:$dst, (not GR8:$src))]>;
1252 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1253 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1254 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1255 [(set GR32:$dst, (not GR32:$src))]>;
1257 let isTwoAddress = 0 in {
1258 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1259 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1260 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1261 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1262 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1263 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1267 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1268 let Defs = [EFLAGS] in {
1270 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1271 [(set GR8:$dst, (add GR8:$src, 1))]>;
1272 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1273 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1274 [(set GR16:$dst, (add GR16:$src, 1))]>,
1275 OpSize, Requires<[In32BitMode]>;
1276 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1277 [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>;
1279 let isTwoAddress = 0, CodeSize = 2 in {
1280 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1281 [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
1282 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1283 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>,
1284 OpSize, Requires<[In32BitMode]>;
1285 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1286 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>,
1287 Requires<[In32BitMode]>;
1291 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1292 [(set GR8:$dst, (add GR8:$src, -1))]>;
1293 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1294 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1295 [(set GR16:$dst, (add GR16:$src, -1))]>,
1296 OpSize, Requires<[In32BitMode]>;
1297 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1298 [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>;
1301 let isTwoAddress = 0, CodeSize = 2 in {
1302 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1303 [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
1304 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1305 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>,
1306 OpSize, Requires<[In32BitMode]>;
1307 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1308 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>,
1309 Requires<[In32BitMode]>;
1311 } // Defs = [EFLAGS]
1313 // Logical operators...
1314 let Defs = [EFLAGS] in {
1315 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1316 def AND8rr : I<0x20, MRMDestReg,
1317 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1318 "and{b}\t{$src2, $dst|$dst, $src2}",
1319 [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>;
1320 def AND16rr : I<0x21, MRMDestReg,
1321 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1322 "and{w}\t{$src2, $dst|$dst, $src2}",
1323 [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize;
1324 def AND32rr : I<0x21, MRMDestReg,
1325 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1326 "and{l}\t{$src2, $dst|$dst, $src2}",
1327 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
1330 def AND8rm : I<0x22, MRMSrcMem,
1331 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1332 "and{b}\t{$src2, $dst|$dst, $src2}",
1333 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>;
1334 def AND16rm : I<0x23, MRMSrcMem,
1335 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1336 "and{w}\t{$src2, $dst|$dst, $src2}",
1337 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize;
1338 def AND32rm : I<0x23, MRMSrcMem,
1339 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1340 "and{l}\t{$src2, $dst|$dst, $src2}",
1341 [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>;
1343 def AND8ri : Ii8<0x80, MRM4r,
1344 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1345 "and{b}\t{$src2, $dst|$dst, $src2}",
1346 [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>;
1347 def AND16ri : Ii16<0x81, MRM4r,
1348 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1349 "and{w}\t{$src2, $dst|$dst, $src2}",
1350 [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize;
1351 def AND32ri : Ii32<0x81, MRM4r,
1352 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1353 "and{l}\t{$src2, $dst|$dst, $src2}",
1354 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
1355 def AND16ri8 : Ii8<0x83, MRM4r,
1356 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1357 "and{w}\t{$src2, $dst|$dst, $src2}",
1358 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>,
1360 def AND32ri8 : Ii8<0x83, MRM4r,
1361 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1362 "and{l}\t{$src2, $dst|$dst, $src2}",
1363 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>;
1365 let isTwoAddress = 0 in {
1366 def AND8mr : I<0x20, MRMDestMem,
1367 (outs), (ins i8mem :$dst, GR8 :$src),
1368 "and{b}\t{$src, $dst|$dst, $src}",
1369 [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>;
1370 def AND16mr : I<0x21, MRMDestMem,
1371 (outs), (ins i16mem:$dst, GR16:$src),
1372 "and{w}\t{$src, $dst|$dst, $src}",
1373 [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>,
1375 def AND32mr : I<0x21, MRMDestMem,
1376 (outs), (ins i32mem:$dst, GR32:$src),
1377 "and{l}\t{$src, $dst|$dst, $src}",
1378 [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>;
1379 def AND8mi : Ii8<0x80, MRM4m,
1380 (outs), (ins i8mem :$dst, i8imm :$src),
1381 "and{b}\t{$src, $dst|$dst, $src}",
1382 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1383 def AND16mi : Ii16<0x81, MRM4m,
1384 (outs), (ins i16mem:$dst, i16imm:$src),
1385 "and{w}\t{$src, $dst|$dst, $src}",
1386 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1388 def AND32mi : Ii32<0x81, MRM4m,
1389 (outs), (ins i32mem:$dst, i32imm:$src),
1390 "and{l}\t{$src, $dst|$dst, $src}",
1391 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1392 def AND16mi8 : Ii8<0x83, MRM4m,
1393 (outs), (ins i16mem:$dst, i16i8imm :$src),
1394 "and{w}\t{$src, $dst|$dst, $src}",
1395 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1397 def AND32mi8 : Ii8<0x83, MRM4m,
1398 (outs), (ins i32mem:$dst, i32i8imm :$src),
1399 "and{l}\t{$src, $dst|$dst, $src}",
1400 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1404 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1405 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1406 "or{b}\t{$src2, $dst|$dst, $src2}",
1407 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
1408 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1409 "or{w}\t{$src2, $dst|$dst, $src2}",
1410 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize;
1411 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1412 "or{l}\t{$src2, $dst|$dst, $src2}",
1413 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
1415 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1416 "or{b}\t{$src2, $dst|$dst, $src2}",
1417 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
1418 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1419 "or{w}\t{$src2, $dst|$dst, $src2}",
1420 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize;
1421 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1422 "or{l}\t{$src2, $dst|$dst, $src2}",
1423 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>;
1425 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1426 "or{b}\t{$src2, $dst|$dst, $src2}",
1427 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
1428 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1429 "or{w}\t{$src2, $dst|$dst, $src2}",
1430 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize;
1431 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1432 "or{l}\t{$src2, $dst|$dst, $src2}",
1433 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
1435 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1436 "or{w}\t{$src2, $dst|$dst, $src2}",
1437 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1438 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1439 "or{l}\t{$src2, $dst|$dst, $src2}",
1440 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>;
1441 let isTwoAddress = 0 in {
1442 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1443 "or{b}\t{$src, $dst|$dst, $src}",
1444 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
1445 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1446 "or{w}\t{$src, $dst|$dst, $src}",
1447 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize;
1448 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1449 "or{l}\t{$src, $dst|$dst, $src}",
1450 [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>;
1451 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1452 "or{b}\t{$src, $dst|$dst, $src}",
1453 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1454 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1455 "or{w}\t{$src, $dst|$dst, $src}",
1456 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1458 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1459 "or{l}\t{$src, $dst|$dst, $src}",
1460 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1461 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1462 "or{w}\t{$src, $dst|$dst, $src}",
1463 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1465 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1466 "or{l}\t{$src, $dst|$dst, $src}",
1467 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1468 } // isTwoAddress = 0
1471 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1472 def XOR8rr : I<0x30, MRMDestReg,
1473 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1474 "xor{b}\t{$src2, $dst|$dst, $src2}",
1475 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>;
1476 def XOR16rr : I<0x31, MRMDestReg,
1477 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1478 "xor{w}\t{$src2, $dst|$dst, $src2}",
1479 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize;
1480 def XOR32rr : I<0x31, MRMDestReg,
1481 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1482 "xor{l}\t{$src2, $dst|$dst, $src2}",
1483 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
1484 } // isCommutable = 1
1486 def XOR8rm : I<0x32, MRMSrcMem ,
1487 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1488 "xor{b}\t{$src2, $dst|$dst, $src2}",
1489 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>;
1490 def XOR16rm : I<0x33, MRMSrcMem ,
1491 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1492 "xor{w}\t{$src2, $dst|$dst, $src2}",
1493 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>,
1495 def XOR32rm : I<0x33, MRMSrcMem ,
1496 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1497 "xor{l}\t{$src2, $dst|$dst, $src2}",
1498 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>;
1500 def XOR8ri : Ii8<0x80, MRM6r,
1501 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1502 "xor{b}\t{$src2, $dst|$dst, $src2}",
1503 [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>;
1504 def XOR16ri : Ii16<0x81, MRM6r,
1505 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1506 "xor{w}\t{$src2, $dst|$dst, $src2}",
1507 [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize;
1508 def XOR32ri : Ii32<0x81, MRM6r,
1509 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1510 "xor{l}\t{$src2, $dst|$dst, $src2}",
1511 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
1512 def XOR16ri8 : Ii8<0x83, MRM6r,
1513 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1514 "xor{w}\t{$src2, $dst|$dst, $src2}",
1515 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>,
1517 def XOR32ri8 : Ii8<0x83, MRM6r,
1518 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1519 "xor{l}\t{$src2, $dst|$dst, $src2}",
1520 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>;
1522 let isTwoAddress = 0 in {
1523 def XOR8mr : I<0x30, MRMDestMem,
1524 (outs), (ins i8mem :$dst, GR8 :$src),
1525 "xor{b}\t{$src, $dst|$dst, $src}",
1526 [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>;
1527 def XOR16mr : I<0x31, MRMDestMem,
1528 (outs), (ins i16mem:$dst, GR16:$src),
1529 "xor{w}\t{$src, $dst|$dst, $src}",
1530 [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>,
1532 def XOR32mr : I<0x31, MRMDestMem,
1533 (outs), (ins i32mem:$dst, GR32:$src),
1534 "xor{l}\t{$src, $dst|$dst, $src}",
1535 [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>;
1536 def XOR8mi : Ii8<0x80, MRM6m,
1537 (outs), (ins i8mem :$dst, i8imm :$src),
1538 "xor{b}\t{$src, $dst|$dst, $src}",
1539 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1540 def XOR16mi : Ii16<0x81, MRM6m,
1541 (outs), (ins i16mem:$dst, i16imm:$src),
1542 "xor{w}\t{$src, $dst|$dst, $src}",
1543 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1545 def XOR32mi : Ii32<0x81, MRM6m,
1546 (outs), (ins i32mem:$dst, i32imm:$src),
1547 "xor{l}\t{$src, $dst|$dst, $src}",
1548 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1549 def XOR16mi8 : Ii8<0x83, MRM6m,
1550 (outs), (ins i16mem:$dst, i16i8imm :$src),
1551 "xor{w}\t{$src, $dst|$dst, $src}",
1552 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1554 def XOR32mi8 : Ii8<0x83, MRM6m,
1555 (outs), (ins i32mem:$dst, i32i8imm :$src),
1556 "xor{l}\t{$src, $dst|$dst, $src}",
1557 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1558 } // isTwoAddress = 0
1559 } // Defs = [EFLAGS]
1561 // Shift instructions
1562 let Defs = [EFLAGS] in {
1563 let Uses = [CL] in {
1564 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1565 "shl{b}\t{%cl, $dst|$dst, %CL}",
1566 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1567 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1568 "shl{w}\t{%cl, $dst|$dst, %CL}",
1569 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1570 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1571 "shl{l}\t{%cl, $dst|$dst, %CL}",
1572 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1575 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1576 "shl{b}\t{$src2, $dst|$dst, $src2}",
1577 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1578 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1579 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1580 "shl{w}\t{$src2, $dst|$dst, $src2}",
1581 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1582 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1583 "shl{l}\t{$src2, $dst|$dst, $src2}",
1584 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1585 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1587 } // isConvertibleToThreeAddress = 1
1589 let isTwoAddress = 0 in {
1590 let Uses = [CL] in {
1591 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1592 "shl{b}\t{%cl, $dst|$dst, %CL}",
1593 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1594 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1595 "shl{w}\t{%cl, $dst|$dst, %CL}",
1596 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1597 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1598 "shl{l}\t{%cl, $dst|$dst, %CL}",
1599 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1601 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1602 "shl{b}\t{$src, $dst|$dst, $src}",
1603 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1604 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1605 "shl{w}\t{$src, $dst|$dst, $src}",
1606 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1608 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1609 "shl{l}\t{$src, $dst|$dst, $src}",
1610 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1613 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1615 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1616 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1618 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1620 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1622 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1625 let Uses = [CL] in {
1626 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1627 "shr{b}\t{%cl, $dst|$dst, %CL}",
1628 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1629 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1630 "shr{w}\t{%cl, $dst|$dst, %CL}",
1631 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1632 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1633 "shr{l}\t{%cl, $dst|$dst, %CL}",
1634 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1637 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1638 "shr{b}\t{$src2, $dst|$dst, $src2}",
1639 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1640 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1641 "shr{w}\t{$src2, $dst|$dst, $src2}",
1642 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1643 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1644 "shr{l}\t{$src2, $dst|$dst, $src2}",
1645 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1648 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1650 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1651 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1653 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1654 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1656 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1658 let isTwoAddress = 0 in {
1659 let Uses = [CL] in {
1660 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1661 "shr{b}\t{%cl, $dst|$dst, %CL}",
1662 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1663 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1664 "shr{w}\t{%cl, $dst|$dst, %CL}",
1665 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1667 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1668 "shr{l}\t{%cl, $dst|$dst, %CL}",
1669 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1671 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1672 "shr{b}\t{$src, $dst|$dst, $src}",
1673 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1674 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1675 "shr{w}\t{$src, $dst|$dst, $src}",
1676 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1678 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1679 "shr{l}\t{$src, $dst|$dst, $src}",
1680 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1683 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1685 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1686 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1688 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1689 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1691 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1694 let Uses = [CL] in {
1695 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1696 "sar{b}\t{%cl, $dst|$dst, %CL}",
1697 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1698 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1699 "sar{w}\t{%cl, $dst|$dst, %CL}",
1700 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1701 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1702 "sar{l}\t{%cl, $dst|$dst, %CL}",
1703 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1706 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1707 "sar{b}\t{$src2, $dst|$dst, $src2}",
1708 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1709 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1710 "sar{w}\t{$src2, $dst|$dst, $src2}",
1711 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1713 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1714 "sar{l}\t{$src2, $dst|$dst, $src2}",
1715 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1718 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1720 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1721 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1723 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1724 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1726 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1728 let isTwoAddress = 0 in {
1729 let Uses = [CL] in {
1730 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1731 "sar{b}\t{%cl, $dst|$dst, %CL}",
1732 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
1733 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1734 "sar{w}\t{%cl, $dst|$dst, %CL}",
1735 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1736 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1737 "sar{l}\t{%cl, $dst|$dst, %CL}",
1738 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1740 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1741 "sar{b}\t{$src, $dst|$dst, $src}",
1742 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1743 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1744 "sar{w}\t{$src, $dst|$dst, $src}",
1745 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1747 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1748 "sar{l}\t{$src, $dst|$dst, $src}",
1749 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1752 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1754 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1755 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1757 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1759 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
1761 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1764 // Rotate instructions
1765 // FIXME: provide shorter instructions when imm8 == 1
1766 let Uses = [CL] in {
1767 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
1768 "rol{b}\t{%cl, $dst|$dst, %CL}",
1769 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
1770 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
1771 "rol{w}\t{%cl, $dst|$dst, %CL}",
1772 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
1773 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
1774 "rol{l}\t{%cl, $dst|$dst, %CL}",
1775 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
1778 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1779 "rol{b}\t{$src2, $dst|$dst, $src2}",
1780 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1781 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1782 "rol{w}\t{$src2, $dst|$dst, $src2}",
1783 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1784 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1785 "rol{l}\t{$src2, $dst|$dst, $src2}",
1786 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1789 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1791 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1792 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
1794 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1795 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1797 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1799 let isTwoAddress = 0 in {
1800 let Uses = [CL] in {
1801 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
1802 "rol{b}\t{%cl, $dst|$dst, %CL}",
1803 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
1804 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
1805 "rol{w}\t{%cl, $dst|$dst, %CL}",
1806 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1807 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
1808 "rol{l}\t{%cl, $dst|$dst, %CL}",
1809 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
1811 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
1812 "rol{b}\t{$src, $dst|$dst, $src}",
1813 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1814 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
1815 "rol{w}\t{$src, $dst|$dst, $src}",
1816 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1818 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
1819 "rol{l}\t{$src, $dst|$dst, $src}",
1820 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1823 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
1825 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1826 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
1828 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1830 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
1832 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1835 let Uses = [CL] in {
1836 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
1837 "ror{b}\t{%cl, $dst|$dst, %CL}",
1838 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
1839 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
1840 "ror{w}\t{%cl, $dst|$dst, %CL}",
1841 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
1842 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
1843 "ror{l}\t{%cl, $dst|$dst, %CL}",
1844 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
1847 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1848 "ror{b}\t{$src2, $dst|$dst, $src2}",
1849 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
1850 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1851 "ror{w}\t{$src2, $dst|$dst, $src2}",
1852 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1853 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1854 "ror{l}\t{$src2, $dst|$dst, $src2}",
1855 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
1858 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1860 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
1861 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
1863 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
1864 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
1866 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
1868 let isTwoAddress = 0 in {
1869 let Uses = [CL] in {
1870 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
1871 "ror{b}\t{%cl, $dst|$dst, %CL}",
1872 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
1873 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
1874 "ror{w}\t{%cl, $dst|$dst, %CL}",
1875 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1876 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
1877 "ror{l}\t{%cl, $dst|$dst, %CL}",
1878 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
1880 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1881 "ror{b}\t{$src, $dst|$dst, $src}",
1882 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1883 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
1884 "ror{w}\t{$src, $dst|$dst, $src}",
1885 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1887 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
1888 "ror{l}\t{$src, $dst|$dst, $src}",
1889 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1892 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
1894 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1895 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
1897 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1899 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
1901 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1906 // Double shift instructions (generalizations of rotate)
1907 let Uses = [CL] in {
1908 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1909 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1910 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
1911 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1912 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1913 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
1914 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1915 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1916 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
1918 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1919 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1920 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
1924 let isCommutable = 1 in { // These instructions commute to each other.
1925 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
1926 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1927 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1928 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
1931 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
1932 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1933 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1934 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
1937 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
1938 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1939 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1940 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
1943 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
1944 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1945 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1946 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
1951 let isTwoAddress = 0 in {
1952 let Uses = [CL] in {
1953 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1954 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1955 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
1957 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1958 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1959 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
1962 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
1963 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1964 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1965 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
1966 (i8 imm:$src3)), addr:$dst)]>,
1968 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
1969 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1970 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1971 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
1972 (i8 imm:$src3)), addr:$dst)]>,
1975 let Uses = [CL] in {
1976 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1977 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1978 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
1979 addr:$dst)]>, TB, OpSize;
1980 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1981 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1982 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
1983 addr:$dst)]>, TB, OpSize;
1985 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
1986 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1987 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1988 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
1989 (i8 imm:$src3)), addr:$dst)]>,
1991 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
1992 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1993 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1994 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
1995 (i8 imm:$src3)), addr:$dst)]>,
1998 } // Defs = [EFLAGS]
2002 let Defs = [EFLAGS] in {
2003 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2004 // Register-Register Addition
2005 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2006 (ins GR8 :$src1, GR8 :$src2),
2007 "add{b}\t{$src2, $dst|$dst, $src2}",
2008 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
2009 (implicit EFLAGS)]>;
2011 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2012 // Register-Register Addition
2013 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2014 (ins GR16:$src1, GR16:$src2),
2015 "add{w}\t{$src2, $dst|$dst, $src2}",
2016 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2017 (implicit EFLAGS)]>, OpSize;
2018 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2019 (ins GR32:$src1, GR32:$src2),
2020 "add{l}\t{$src2, $dst|$dst, $src2}",
2021 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2022 (implicit EFLAGS)]>;
2023 } // end isConvertibleToThreeAddress
2024 } // end isCommutable
2026 // Register-Memory Addition
2027 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2028 (ins GR8 :$src1, i8mem :$src2),
2029 "add{b}\t{$src2, $dst|$dst, $src2}",
2030 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2031 (implicit EFLAGS)]>;
2032 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2033 (ins GR16:$src1, i16mem:$src2),
2034 "add{w}\t{$src2, $dst|$dst, $src2}",
2035 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2036 (implicit EFLAGS)]>, OpSize;
2037 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2038 (ins GR32:$src1, i32mem:$src2),
2039 "add{l}\t{$src2, $dst|$dst, $src2}",
2040 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2041 (implicit EFLAGS)]>;
2043 // Register-Integer Addition
2044 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2045 "add{b}\t{$src2, $dst|$dst, $src2}",
2046 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2047 (implicit EFLAGS)]>;
2049 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2050 // Register-Integer Addition
2051 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2052 (ins GR16:$src1, i16imm:$src2),
2053 "add{w}\t{$src2, $dst|$dst, $src2}",
2054 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2055 (implicit EFLAGS)]>, OpSize;
2056 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2057 (ins GR32:$src1, i32imm:$src2),
2058 "add{l}\t{$src2, $dst|$dst, $src2}",
2059 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2060 (implicit EFLAGS)]>;
2061 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2062 (ins GR16:$src1, i16i8imm:$src2),
2063 "add{w}\t{$src2, $dst|$dst, $src2}",
2064 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2065 (implicit EFLAGS)]>, OpSize;
2066 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2067 (ins GR32:$src1, i32i8imm:$src2),
2068 "add{l}\t{$src2, $dst|$dst, $src2}",
2069 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2070 (implicit EFLAGS)]>;
2073 let isTwoAddress = 0 in {
2074 // Memory-Register Addition
2075 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2076 "add{b}\t{$src2, $dst|$dst, $src2}",
2077 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2078 (implicit EFLAGS)]>;
2079 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2080 "add{w}\t{$src2, $dst|$dst, $src2}",
2081 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2082 (implicit EFLAGS)]>, OpSize;
2083 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2084 "add{l}\t{$src2, $dst|$dst, $src2}",
2085 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2086 (implicit EFLAGS)]>;
2087 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2088 "add{b}\t{$src2, $dst|$dst, $src2}",
2089 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2090 (implicit EFLAGS)]>;
2091 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2092 "add{w}\t{$src2, $dst|$dst, $src2}",
2093 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2094 (implicit EFLAGS)]>, OpSize;
2095 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2096 "add{l}\t{$src2, $dst|$dst, $src2}",
2097 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2098 (implicit EFLAGS)]>;
2099 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2100 "add{w}\t{$src2, $dst|$dst, $src2}",
2101 [(store (add (load addr:$dst), i16immSExt8:$src2),
2103 (implicit EFLAGS)]>, OpSize;
2104 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2105 "add{l}\t{$src2, $dst|$dst, $src2}",
2106 [(store (add (load addr:$dst), i32immSExt8:$src2),
2108 (implicit EFLAGS)]>;
2111 let Uses = [EFLAGS] in {
2112 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2113 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2114 "adc{l}\t{$src2, $dst|$dst, $src2}",
2115 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2117 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2118 "adc{l}\t{$src2, $dst|$dst, $src2}",
2119 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2120 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2121 "adc{l}\t{$src2, $dst|$dst, $src2}",
2122 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2123 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2124 "adc{l}\t{$src2, $dst|$dst, $src2}",
2125 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2127 let isTwoAddress = 0 in {
2128 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2129 "adc{l}\t{$src2, $dst|$dst, $src2}",
2130 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2131 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2132 "adc{l}\t{$src2, $dst|$dst, $src2}",
2133 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2134 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2135 "adc{l}\t{$src2, $dst|$dst, $src2}",
2136 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2138 } // Uses = [EFLAGS]
2140 // Register-Register Subtraction
2141 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2142 "sub{b}\t{$src2, $dst|$dst, $src2}",
2143 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2144 (implicit EFLAGS)]>;
2145 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2146 "sub{w}\t{$src2, $dst|$dst, $src2}",
2147 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2148 (implicit EFLAGS)]>, OpSize;
2149 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2150 "sub{l}\t{$src2, $dst|$dst, $src2}",
2151 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2152 (implicit EFLAGS)]>;
2154 // Register-Memory Subtraction
2155 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2156 (ins GR8 :$src1, i8mem :$src2),
2157 "sub{b}\t{$src2, $dst|$dst, $src2}",
2158 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2159 (implicit EFLAGS)]>;
2160 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2161 (ins GR16:$src1, i16mem:$src2),
2162 "sub{w}\t{$src2, $dst|$dst, $src2}",
2163 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2164 (implicit EFLAGS)]>, OpSize;
2165 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2166 (ins GR32:$src1, i32mem:$src2),
2167 "sub{l}\t{$src2, $dst|$dst, $src2}",
2168 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2169 (implicit EFLAGS)]>;
2171 // Register-Integer Subtraction
2172 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2173 (ins GR8:$src1, i8imm:$src2),
2174 "sub{b}\t{$src2, $dst|$dst, $src2}",
2175 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2176 (implicit EFLAGS)]>;
2177 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2178 (ins GR16:$src1, i16imm:$src2),
2179 "sub{w}\t{$src2, $dst|$dst, $src2}",
2180 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2181 (implicit EFLAGS)]>, OpSize;
2182 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2183 (ins GR32:$src1, i32imm:$src2),
2184 "sub{l}\t{$src2, $dst|$dst, $src2}",
2185 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2186 (implicit EFLAGS)]>;
2187 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2188 (ins GR16:$src1, i16i8imm:$src2),
2189 "sub{w}\t{$src2, $dst|$dst, $src2}",
2190 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2191 (implicit EFLAGS)]>, OpSize;
2192 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2193 (ins GR32:$src1, i32i8imm:$src2),
2194 "sub{l}\t{$src2, $dst|$dst, $src2}",
2195 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2196 (implicit EFLAGS)]>;
2198 let isTwoAddress = 0 in {
2199 // Memory-Register Subtraction
2200 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2201 "sub{b}\t{$src2, $dst|$dst, $src2}",
2202 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2203 (implicit EFLAGS)]>;
2204 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2205 "sub{w}\t{$src2, $dst|$dst, $src2}",
2206 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2207 (implicit EFLAGS)]>, OpSize;
2208 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2209 "sub{l}\t{$src2, $dst|$dst, $src2}",
2210 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2211 (implicit EFLAGS)]>;
2213 // Memory-Integer Subtraction
2214 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2215 "sub{b}\t{$src2, $dst|$dst, $src2}",
2216 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2217 (implicit EFLAGS)]>;
2218 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2219 "sub{w}\t{$src2, $dst|$dst, $src2}",
2220 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2221 (implicit EFLAGS)]>, OpSize;
2222 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2223 "sub{l}\t{$src2, $dst|$dst, $src2}",
2224 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2225 (implicit EFLAGS)]>;
2226 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2227 "sub{w}\t{$src2, $dst|$dst, $src2}",
2228 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2230 (implicit EFLAGS)]>, OpSize;
2231 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2232 "sub{l}\t{$src2, $dst|$dst, $src2}",
2233 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2235 (implicit EFLAGS)]>;
2238 let Uses = [EFLAGS] in {
2239 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2240 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2241 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2243 let isTwoAddress = 0 in {
2244 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2245 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2246 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2247 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2248 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2249 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2250 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2251 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2252 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2253 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2254 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2255 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2257 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2258 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2259 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2260 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2261 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2262 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2263 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2264 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2265 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2266 } // Uses = [EFLAGS]
2267 } // Defs = [EFLAGS]
2269 let Defs = [EFLAGS] in {
2270 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2271 // Register-Register Signed Integer Multiply
2272 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2273 "imul{w}\t{$src2, $dst|$dst, $src2}",
2274 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
2275 (implicit EFLAGS)]>, TB, OpSize;
2276 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2277 "imul{l}\t{$src2, $dst|$dst, $src2}",
2278 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
2279 (implicit EFLAGS)]>, TB;
2282 // Register-Memory Signed Integer Multiply
2283 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
2284 (ins GR16:$src1, i16mem:$src2),
2285 "imul{w}\t{$src2, $dst|$dst, $src2}",
2286 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
2287 (implicit EFLAGS)]>, TB, OpSize;
2288 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2289 "imul{l}\t{$src2, $dst|$dst, $src2}",
2290 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
2291 (implicit EFLAGS)]>, TB;
2292 } // Defs = [EFLAGS]
2293 } // end Two Address instructions
2295 // Suprisingly enough, these are not two address instructions!
2296 let Defs = [EFLAGS] in {
2297 // Register-Integer Signed Integer Multiply
2298 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2299 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2300 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2301 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
2302 (implicit EFLAGS)]>, OpSize;
2303 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2304 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2305 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2306 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
2307 (implicit EFLAGS)]>;
2308 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2309 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2310 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2311 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
2312 (implicit EFLAGS)]>, OpSize;
2313 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2314 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2315 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2316 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
2317 (implicit EFLAGS)]>;
2319 // Memory-Integer Signed Integer Multiply
2320 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2321 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2322 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2323 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
2324 (implicit EFLAGS)]>, OpSize;
2325 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2326 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2327 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2328 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
2329 (implicit EFLAGS)]>;
2330 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2331 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2332 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2333 [(set GR16:$dst, (mul (load addr:$src1),
2334 i16immSExt8:$src2)),
2335 (implicit EFLAGS)]>, OpSize;
2336 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2337 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2338 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2339 [(set GR32:$dst, (mul (load addr:$src1),
2340 i32immSExt8:$src2)),
2341 (implicit EFLAGS)]>;
2342 } // Defs = [EFLAGS]
2344 //===----------------------------------------------------------------------===//
2345 // Test instructions are just like AND, except they don't generate a result.
2347 let Defs = [EFLAGS] in {
2348 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2349 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2350 "test{b}\t{$src2, $src1|$src1, $src2}",
2351 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
2352 (implicit EFLAGS)]>;
2353 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2354 "test{w}\t{$src2, $src1|$src1, $src2}",
2355 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
2356 (implicit EFLAGS)]>,
2358 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2359 "test{l}\t{$src2, $src1|$src1, $src2}",
2360 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
2361 (implicit EFLAGS)]>;
2364 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2365 "test{b}\t{$src2, $src1|$src1, $src2}",
2366 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2367 (implicit EFLAGS)]>;
2368 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2369 "test{w}\t{$src2, $src1|$src1, $src2}",
2370 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2371 (implicit EFLAGS)]>, OpSize;
2372 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2373 "test{l}\t{$src2, $src1|$src1, $src2}",
2374 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2375 (implicit EFLAGS)]>;
2377 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2378 (outs), (ins GR8:$src1, i8imm:$src2),
2379 "test{b}\t{$src2, $src1|$src1, $src2}",
2380 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
2381 (implicit EFLAGS)]>;
2382 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2383 (outs), (ins GR16:$src1, i16imm:$src2),
2384 "test{w}\t{$src2, $src1|$src1, $src2}",
2385 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
2386 (implicit EFLAGS)]>, OpSize;
2387 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2388 (outs), (ins GR32:$src1, i32imm:$src2),
2389 "test{l}\t{$src2, $src1|$src1, $src2}",
2390 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
2391 (implicit EFLAGS)]>;
2393 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2394 (outs), (ins i8mem:$src1, i8imm:$src2),
2395 "test{b}\t{$src2, $src1|$src1, $src2}",
2396 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2397 (implicit EFLAGS)]>;
2398 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2399 (outs), (ins i16mem:$src1, i16imm:$src2),
2400 "test{w}\t{$src2, $src1|$src1, $src2}",
2401 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2402 (implicit EFLAGS)]>, OpSize;
2403 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2404 (outs), (ins i32mem:$src1, i32imm:$src2),
2405 "test{l}\t{$src2, $src1|$src1, $src2}",
2406 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2407 (implicit EFLAGS)]>;
2408 } // Defs = [EFLAGS]
2411 // Condition code ops, incl. set if equal/not equal/...
2412 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2413 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2414 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2415 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2417 let Uses = [EFLAGS] in {
2418 def SETEr : I<0x94, MRM0r,
2419 (outs GR8 :$dst), (ins),
2421 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2423 def SETEm : I<0x94, MRM0m,
2424 (outs), (ins i8mem:$dst),
2426 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2429 def SETNEr : I<0x95, MRM0r,
2430 (outs GR8 :$dst), (ins),
2432 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2434 def SETNEm : I<0x95, MRM0m,
2435 (outs), (ins i8mem:$dst),
2437 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2440 def SETLr : I<0x9C, MRM0r,
2441 (outs GR8 :$dst), (ins),
2443 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2444 TB; // GR8 = < signed
2445 def SETLm : I<0x9C, MRM0m,
2446 (outs), (ins i8mem:$dst),
2448 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2449 TB; // [mem8] = < signed
2451 def SETGEr : I<0x9D, MRM0r,
2452 (outs GR8 :$dst), (ins),
2454 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2455 TB; // GR8 = >= signed
2456 def SETGEm : I<0x9D, MRM0m,
2457 (outs), (ins i8mem:$dst),
2459 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2460 TB; // [mem8] = >= signed
2462 def SETLEr : I<0x9E, MRM0r,
2463 (outs GR8 :$dst), (ins),
2465 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2466 TB; // GR8 = <= signed
2467 def SETLEm : I<0x9E, MRM0m,
2468 (outs), (ins i8mem:$dst),
2470 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2471 TB; // [mem8] = <= signed
2473 def SETGr : I<0x9F, MRM0r,
2474 (outs GR8 :$dst), (ins),
2476 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2477 TB; // GR8 = > signed
2478 def SETGm : I<0x9F, MRM0m,
2479 (outs), (ins i8mem:$dst),
2481 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2482 TB; // [mem8] = > signed
2484 def SETBr : I<0x92, MRM0r,
2485 (outs GR8 :$dst), (ins),
2487 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2488 TB; // GR8 = < unsign
2489 def SETBm : I<0x92, MRM0m,
2490 (outs), (ins i8mem:$dst),
2492 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
2493 TB; // [mem8] = < unsign
2495 def SETAEr : I<0x93, MRM0r,
2496 (outs GR8 :$dst), (ins),
2498 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
2499 TB; // GR8 = >= unsign
2500 def SETAEm : I<0x93, MRM0m,
2501 (outs), (ins i8mem:$dst),
2503 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
2504 TB; // [mem8] = >= unsign
2506 def SETBEr : I<0x96, MRM0r,
2507 (outs GR8 :$dst), (ins),
2509 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
2510 TB; // GR8 = <= unsign
2511 def SETBEm : I<0x96, MRM0m,
2512 (outs), (ins i8mem:$dst),
2514 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
2515 TB; // [mem8] = <= unsign
2517 def SETAr : I<0x97, MRM0r,
2518 (outs GR8 :$dst), (ins),
2520 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
2521 TB; // GR8 = > signed
2522 def SETAm : I<0x97, MRM0m,
2523 (outs), (ins i8mem:$dst),
2525 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
2526 TB; // [mem8] = > signed
2528 def SETSr : I<0x98, MRM0r,
2529 (outs GR8 :$dst), (ins),
2531 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
2532 TB; // GR8 = <sign bit>
2533 def SETSm : I<0x98, MRM0m,
2534 (outs), (ins i8mem:$dst),
2536 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
2537 TB; // [mem8] = <sign bit>
2538 def SETNSr : I<0x99, MRM0r,
2539 (outs GR8 :$dst), (ins),
2541 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
2542 TB; // GR8 = !<sign bit>
2543 def SETNSm : I<0x99, MRM0m,
2544 (outs), (ins i8mem:$dst),
2546 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
2547 TB; // [mem8] = !<sign bit>
2549 def SETPr : I<0x9A, MRM0r,
2550 (outs GR8 :$dst), (ins),
2552 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
2554 def SETPm : I<0x9A, MRM0m,
2555 (outs), (ins i8mem:$dst),
2557 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
2558 TB; // [mem8] = parity
2559 def SETNPr : I<0x9B, MRM0r,
2560 (outs GR8 :$dst), (ins),
2562 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
2563 TB; // GR8 = not parity
2564 def SETNPm : I<0x9B, MRM0m,
2565 (outs), (ins i8mem:$dst),
2567 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
2568 TB; // [mem8] = not parity
2570 def SETOr : I<0x90, MRM0r,
2571 (outs GR8 :$dst), (ins),
2573 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
2574 TB; // GR8 = overflow
2575 def SETOm : I<0x90, MRM0m,
2576 (outs), (ins i8mem:$dst),
2578 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
2579 TB; // [mem8] = overflow
2580 def SETNOr : I<0x91, MRM0r,
2581 (outs GR8 :$dst), (ins),
2583 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
2584 TB; // GR8 = not overflow
2585 def SETNOm : I<0x91, MRM0m,
2586 (outs), (ins i8mem:$dst),
2588 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
2589 TB; // [mem8] = not overflow
2590 } // Uses = [EFLAGS]
2593 // Integer comparisons
2594 let Defs = [EFLAGS] in {
2595 def CMP8rr : I<0x38, MRMDestReg,
2596 (outs), (ins GR8 :$src1, GR8 :$src2),
2597 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2598 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2599 def CMP16rr : I<0x39, MRMDestReg,
2600 (outs), (ins GR16:$src1, GR16:$src2),
2601 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2602 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
2603 def CMP32rr : I<0x39, MRMDestReg,
2604 (outs), (ins GR32:$src1, GR32:$src2),
2605 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2606 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
2607 def CMP8mr : I<0x38, MRMDestMem,
2608 (outs), (ins i8mem :$src1, GR8 :$src2),
2609 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2610 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
2611 (implicit EFLAGS)]>;
2612 def CMP16mr : I<0x39, MRMDestMem,
2613 (outs), (ins i16mem:$src1, GR16:$src2),
2614 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2615 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
2616 (implicit EFLAGS)]>, OpSize;
2617 def CMP32mr : I<0x39, MRMDestMem,
2618 (outs), (ins i32mem:$src1, GR32:$src2),
2619 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2620 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
2621 (implicit EFLAGS)]>;
2622 def CMP8rm : I<0x3A, MRMSrcMem,
2623 (outs), (ins GR8 :$src1, i8mem :$src2),
2624 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2625 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
2626 (implicit EFLAGS)]>;
2627 def CMP16rm : I<0x3B, MRMSrcMem,
2628 (outs), (ins GR16:$src1, i16mem:$src2),
2629 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2630 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
2631 (implicit EFLAGS)]>, OpSize;
2632 def CMP32rm : I<0x3B, MRMSrcMem,
2633 (outs), (ins GR32:$src1, i32mem:$src2),
2634 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2635 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
2636 (implicit EFLAGS)]>;
2637 def CMP8ri : Ii8<0x80, MRM7r,
2638 (outs), (ins GR8:$src1, i8imm:$src2),
2639 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2640 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
2641 def CMP16ri : Ii16<0x81, MRM7r,
2642 (outs), (ins GR16:$src1, i16imm:$src2),
2643 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2644 [(X86cmp GR16:$src1, imm:$src2),
2645 (implicit EFLAGS)]>, OpSize;
2646 def CMP32ri : Ii32<0x81, MRM7r,
2647 (outs), (ins GR32:$src1, i32imm:$src2),
2648 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2649 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
2650 def CMP8mi : Ii8 <0x80, MRM7m,
2651 (outs), (ins i8mem :$src1, i8imm :$src2),
2652 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2653 [(X86cmp (loadi8 addr:$src1), imm:$src2),
2654 (implicit EFLAGS)]>;
2655 def CMP16mi : Ii16<0x81, MRM7m,
2656 (outs), (ins i16mem:$src1, i16imm:$src2),
2657 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2658 [(X86cmp (loadi16 addr:$src1), imm:$src2),
2659 (implicit EFLAGS)]>, OpSize;
2660 def CMP32mi : Ii32<0x81, MRM7m,
2661 (outs), (ins i32mem:$src1, i32imm:$src2),
2662 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2663 [(X86cmp (loadi32 addr:$src1), imm:$src2),
2664 (implicit EFLAGS)]>;
2665 def CMP16ri8 : Ii8<0x83, MRM7r,
2666 (outs), (ins GR16:$src1, i16i8imm:$src2),
2667 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2668 [(X86cmp GR16:$src1, i16immSExt8:$src2),
2669 (implicit EFLAGS)]>, OpSize;
2670 def CMP16mi8 : Ii8<0x83, MRM7m,
2671 (outs), (ins i16mem:$src1, i16i8imm:$src2),
2672 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2673 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
2674 (implicit EFLAGS)]>, OpSize;
2675 def CMP32mi8 : Ii8<0x83, MRM7m,
2676 (outs), (ins i32mem:$src1, i32i8imm:$src2),
2677 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2678 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
2679 (implicit EFLAGS)]>;
2680 def CMP32ri8 : Ii8<0x83, MRM7r,
2681 (outs), (ins GR32:$src1, i32i8imm:$src2),
2682 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2683 [(X86cmp GR32:$src1, i32immSExt8:$src2),
2684 (implicit EFLAGS)]>;
2685 } // Defs = [EFLAGS]
2688 // TODO: BTC, BTR, and BTS
2689 let Defs = [EFLAGS] in {
2690 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2691 "bt{w}\t{$src2, $src1|$src1, $src2}",
2692 [(X86bt GR16:$src1, GR16:$src2),
2693 (implicit EFLAGS)]>, OpSize, TB;
2694 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2695 "bt{l}\t{$src2, $src1|$src1, $src2}",
2696 [(X86bt GR32:$src1, GR32:$src2),
2697 (implicit EFLAGS)]>, TB;
2699 // Unlike with the register+register form, the memory+register form of the
2700 // bt instruction does not ignore the high bits of the index. From ISel's
2701 // perspective, this is pretty bizarre. Disable these instructions for now.
2702 //def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
2703 // "bt{w}\t{$src2, $src1|$src1, $src2}",
2704 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
2705 // (implicit EFLAGS)]>, OpSize, TB, Requires<[FastBTMem]>;
2706 //def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
2707 // "bt{l}\t{$src2, $src1|$src1, $src2}",
2708 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
2709 // (implicit EFLAGS)]>, TB, Requires<[FastBTMem]>;
2711 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
2712 "bt{w}\t{$src2, $src1|$src1, $src2}",
2713 [(X86bt GR16:$src1, i16immSExt8:$src2),
2714 (implicit EFLAGS)]>, OpSize, TB;
2715 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
2716 "bt{l}\t{$src2, $src1|$src1, $src2}",
2717 [(X86bt GR32:$src1, i32immSExt8:$src2),
2718 (implicit EFLAGS)]>, TB;
2719 // Note that these instructions don't need FastBTMem because that
2720 // only applies when the other operand is in a register. When it's
2721 // an immediate, bt is still fast.
2722 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
2723 "bt{w}\t{$src2, $src1|$src1, $src2}",
2724 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
2725 (implicit EFLAGS)]>, OpSize, TB;
2726 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
2727 "bt{l}\t{$src2, $src1|$src1, $src2}",
2728 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
2729 (implicit EFLAGS)]>, TB;
2730 } // Defs = [EFLAGS]
2732 // Sign/Zero extenders
2733 // Use movsbl intead of movsbw; we don't care about the high 16 bits
2734 // of the register here. This has a smaller encoding and avoids a
2735 // partial-register update.
2736 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2737 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2738 [(set GR16:$dst, (sext GR8:$src))]>, TB;
2739 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2740 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2741 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
2742 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2743 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2744 [(set GR32:$dst, (sext GR8:$src))]>, TB;
2745 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2746 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2747 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
2748 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2749 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2750 [(set GR32:$dst, (sext GR16:$src))]>, TB;
2751 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2752 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2753 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
2755 // Use movzbl intead of movzbw; we don't care about the high 16 bits
2756 // of the register here. This has a smaller encoding and avoids a
2757 // partial-register update.
2758 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2759 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2760 [(set GR16:$dst, (zext GR8:$src))]>, TB;
2761 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2762 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2763 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
2764 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2765 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2766 [(set GR32:$dst, (zext GR8:$src))]>, TB;
2767 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2768 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2769 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
2770 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2771 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2772 [(set GR32:$dst, (zext GR16:$src))]>, TB;
2773 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2774 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2775 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
2777 let neverHasSideEffects = 1 in {
2778 let Defs = [AX], Uses = [AL] in
2779 def CBW : I<0x98, RawFrm, (outs), (ins),
2780 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
2781 let Defs = [EAX], Uses = [AX] in
2782 def CWDE : I<0x98, RawFrm, (outs), (ins),
2783 "{cwtl|cwde}", []>; // EAX = signext(AX)
2785 let Defs = [AX,DX], Uses = [AX] in
2786 def CWD : I<0x99, RawFrm, (outs), (ins),
2787 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
2788 let Defs = [EAX,EDX], Uses = [EAX] in
2789 def CDQ : I<0x99, RawFrm, (outs), (ins),
2790 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
2793 //===----------------------------------------------------------------------===//
2794 // Alias Instructions
2795 //===----------------------------------------------------------------------===//
2797 // Alias instructions that map movr0 to xor.
2798 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2799 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1 in {
2800 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
2801 "xor{b}\t$dst, $dst",
2802 [(set GR8:$dst, 0)]>;
2803 // Use xorl instead of xorw since we don't care about the high 16 bits,
2804 // it's smaller, and it avoids a partial-register update.
2805 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
2806 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
2807 [(set GR16:$dst, 0)]>;
2808 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
2809 "xor{l}\t$dst, $dst",
2810 [(set GR32:$dst, 0)]>;
2813 // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
2814 // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
2815 let neverHasSideEffects = 1 in {
2816 def MOV16to16_ : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16:$src),
2817 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2818 def MOV32to32_ : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32:$src),
2819 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2821 def MOV16_rr : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16_:$src),
2822 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2823 def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src),
2824 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2825 } // neverHasSideEffects
2827 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
2828 def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src),
2829 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2830 def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src),
2831 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2833 let mayStore = 1, neverHasSideEffects = 1 in {
2834 def MOV16_mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16_:$src),
2835 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2836 def MOV32_mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32_:$src),
2837 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2840 //===----------------------------------------------------------------------===//
2841 // Thread Local Storage Instructions
2845 def TLS_addr32 : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
2846 "leal\t${sym:mem}(,%ebx,1), $dst",
2847 [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
2849 let AddedComplexity = 10 in
2850 def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
2851 "movl\t%gs:($src), $dst",
2852 [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
2854 let AddedComplexity = 15 in
2855 def TLS_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
2856 "movl\t%gs:${src:mem}, $dst",
2858 (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>,
2861 def TLS_tp : I<0x8B, Pseudo, (outs GR32:$dst), (ins),
2862 "movl\t%gs:0, $dst",
2863 [(set GR32:$dst, X86TLStp)]>, SegGS;
2865 let AddedComplexity = 5 in
2866 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2867 "movl\t%gs:$src, $dst",
2868 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
2870 //===----------------------------------------------------------------------===//
2871 // DWARF Pseudo Instructions
2874 def DWARF_LOC : I<0, Pseudo, (outs),
2875 (ins i32imm:$line, i32imm:$col, i32imm:$file),
2876 ".loc\t${file:debug} ${line:debug} ${col:debug}",
2877 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
2880 //===----------------------------------------------------------------------===//
2881 // EH Pseudo Instructions
2883 let isTerminator = 1, isReturn = 1, isBarrier = 1,
2885 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
2886 "ret\t#eh_return, addr: $addr",
2887 [(X86ehret GR32:$addr)]>;
2891 //===----------------------------------------------------------------------===//
2895 // Atomic swap. These are just normal xchg instructions. But since a memory
2896 // operand is referenced, the atomicity is ensured.
2897 let Constraints = "$val = $dst" in {
2898 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2899 "xchg{l}\t{$val, $ptr|$ptr, $val}",
2900 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
2901 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2902 "xchg{w}\t{$val, $ptr|$ptr, $val}",
2903 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
2905 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2906 "xchg{b}\t{$val, $ptr|$ptr, $val}",
2907 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
2910 // Atomic compare and swap.
2911 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
2912 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
2913 "lock\n\tcmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
2914 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
2916 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
2917 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
2918 "lock\n\tcmpxchg8b\t$ptr",
2919 [(X86cas8 addr:$ptr)]>, TB, LOCK;
2922 let Defs = [AX, EFLAGS], Uses = [AX] in {
2923 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
2924 "lock\n\tcmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
2925 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
2927 let Defs = [AL, EFLAGS], Uses = [AL] in {
2928 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
2929 "lock\n\tcmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
2930 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
2933 // Atomic exchange and add
2934 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
2935 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2936 "lock\n\txadd{l}\t{$val, $ptr|$ptr, $val}",
2937 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
2939 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2940 "lock\n\txadd{w}\t{$val, $ptr|$ptr, $val}",
2941 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
2943 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2944 "lock\n\txadd{b}\t{$val, $ptr|$ptr, $val}",
2945 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
2949 // Atomic exchange, and, or, xor
2950 let Constraints = "$val = $dst", Defs = [EFLAGS],
2951 usesCustomDAGSchedInserter = 1 in {
2952 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2953 "#ATOMAND32 PSEUDO!",
2954 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
2955 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2956 "#ATOMOR32 PSEUDO!",
2957 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
2958 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2959 "#ATOMXOR32 PSEUDO!",
2960 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
2961 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2962 "#ATOMNAND32 PSEUDO!",
2963 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
2964 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2965 "#ATOMMIN32 PSEUDO!",
2966 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
2967 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2968 "#ATOMMAX32 PSEUDO!",
2969 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
2970 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2971 "#ATOMUMIN32 PSEUDO!",
2972 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
2973 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2974 "#ATOMUMAX32 PSEUDO!",
2975 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
2977 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2978 "#ATOMAND16 PSEUDO!",
2979 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
2980 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2981 "#ATOMOR16 PSEUDO!",
2982 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
2983 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2984 "#ATOMXOR16 PSEUDO!",
2985 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
2986 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2987 "#ATOMNAND16 PSEUDO!",
2988 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
2989 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2990 "#ATOMMIN16 PSEUDO!",
2991 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
2992 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2993 "#ATOMMAX16 PSEUDO!",
2994 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
2995 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2996 "#ATOMUMIN16 PSEUDO!",
2997 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
2998 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2999 "#ATOMUMAX16 PSEUDO!",
3000 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
3002 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3003 "#ATOMAND8 PSEUDO!",
3004 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
3005 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3007 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
3008 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3009 "#ATOMXOR8 PSEUDO!",
3010 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
3011 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3012 "#ATOMNAND8 PSEUDO!",
3013 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
3016 let Constraints = "$val1 = $dst1, $val2 = $dst2",
3017 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
3018 Uses = [EAX, EBX, ECX, EDX],
3019 mayLoad = 1, mayStore = 1,
3020 usesCustomDAGSchedInserter = 1 in {
3021 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3022 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3023 "#ATOMAND6432 PSEUDO!", []>;
3024 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3025 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3026 "#ATOMOR6432 PSEUDO!", []>;
3027 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3028 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3029 "#ATOMXOR6432 PSEUDO!", []>;
3030 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3031 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3032 "#ATOMNAND6432 PSEUDO!", []>;
3033 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3034 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3035 "#ATOMADD6432 PSEUDO!", []>;
3036 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3037 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3038 "#ATOMSUB6432 PSEUDO!", []>;
3039 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3040 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3041 "#ATOMSWAP6432 PSEUDO!", []>;
3044 //===----------------------------------------------------------------------===//
3045 // Non-Instruction Patterns
3046 //===----------------------------------------------------------------------===//
3048 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
3049 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
3050 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
3051 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
3052 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
3053 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
3055 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
3056 (ADD32ri GR32:$src1, tconstpool:$src2)>;
3057 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
3058 (ADD32ri GR32:$src1, tjumptable:$src2)>;
3059 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
3060 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
3061 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
3062 (ADD32ri GR32:$src1, texternalsym:$src2)>;
3064 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
3065 (MOV32mi addr:$dst, tglobaladdr:$src)>;
3066 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
3067 (MOV32mi addr:$dst, texternalsym:$src)>;
3071 def : Pat<(X86tailcall GR32:$dst),
3074 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
3076 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
3079 def : Pat<(X86tcret GR32:$dst, imm:$off),
3080 (TCRETURNri GR32:$dst, imm:$off)>;
3082 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
3083 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3085 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
3086 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3088 def : Pat<(X86call (i32 tglobaladdr:$dst)),
3089 (CALLpcrel32 tglobaladdr:$dst)>;
3090 def : Pat<(X86call (i32 texternalsym:$dst)),
3091 (CALLpcrel32 texternalsym:$dst)>;
3093 // X86 specific add which produces a flag.
3094 def : Pat<(addc GR32:$src1, GR32:$src2),
3095 (ADD32rr GR32:$src1, GR32:$src2)>;
3096 def : Pat<(addc GR32:$src1, (load addr:$src2)),
3097 (ADD32rm GR32:$src1, addr:$src2)>;
3098 def : Pat<(addc GR32:$src1, imm:$src2),
3099 (ADD32ri GR32:$src1, imm:$src2)>;
3100 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
3101 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3103 def : Pat<(subc GR32:$src1, GR32:$src2),
3104 (SUB32rr GR32:$src1, GR32:$src2)>;
3105 def : Pat<(subc GR32:$src1, (load addr:$src2)),
3106 (SUB32rm GR32:$src1, addr:$src2)>;
3107 def : Pat<(subc GR32:$src1, imm:$src2),
3108 (SUB32ri GR32:$src1, imm:$src2)>;
3109 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
3110 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3114 // TEST R,R is smaller than CMP R,0
3115 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
3116 (TEST8rr GR8:$src1, GR8:$src1)>;
3117 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
3118 (TEST16rr GR16:$src1, GR16:$src1)>;
3119 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
3120 (TEST32rr GR32:$src1, GR32:$src1)>;
3122 // Conditional moves with folded loads with operands swapped and conditions
3124 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
3125 (CMOVAE16rm GR16:$src2, addr:$src1)>;
3126 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
3127 (CMOVAE32rm GR32:$src2, addr:$src1)>;
3128 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
3129 (CMOVB16rm GR16:$src2, addr:$src1)>;
3130 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
3131 (CMOVB32rm GR32:$src2, addr:$src1)>;
3132 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
3133 (CMOVNE16rm GR16:$src2, addr:$src1)>;
3134 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
3135 (CMOVNE32rm GR32:$src2, addr:$src1)>;
3136 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
3137 (CMOVE16rm GR16:$src2, addr:$src1)>;
3138 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
3139 (CMOVE32rm GR32:$src2, addr:$src1)>;
3140 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
3141 (CMOVA16rm GR16:$src2, addr:$src1)>;
3142 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
3143 (CMOVA32rm GR32:$src2, addr:$src1)>;
3144 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
3145 (CMOVBE16rm GR16:$src2, addr:$src1)>;
3146 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
3147 (CMOVBE32rm GR32:$src2, addr:$src1)>;
3148 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
3149 (CMOVGE16rm GR16:$src2, addr:$src1)>;
3150 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
3151 (CMOVGE32rm GR32:$src2, addr:$src1)>;
3152 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
3153 (CMOVL16rm GR16:$src2, addr:$src1)>;
3154 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
3155 (CMOVL32rm GR32:$src2, addr:$src1)>;
3156 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
3157 (CMOVG16rm GR16:$src2, addr:$src1)>;
3158 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
3159 (CMOVG32rm GR32:$src2, addr:$src1)>;
3160 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
3161 (CMOVLE16rm GR16:$src2, addr:$src1)>;
3162 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
3163 (CMOVLE32rm GR32:$src2, addr:$src1)>;
3164 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
3165 (CMOVNP16rm GR16:$src2, addr:$src1)>;
3166 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
3167 (CMOVNP32rm GR32:$src2, addr:$src1)>;
3168 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
3169 (CMOVP16rm GR16:$src2, addr:$src1)>;
3170 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
3171 (CMOVP32rm GR32:$src2, addr:$src1)>;
3172 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
3173 (CMOVNS16rm GR16:$src2, addr:$src1)>;
3174 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
3175 (CMOVNS32rm GR32:$src2, addr:$src1)>;
3176 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
3177 (CMOVS16rm GR16:$src2, addr:$src1)>;
3178 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
3179 (CMOVS32rm GR32:$src2, addr:$src1)>;
3180 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
3181 (CMOVNO16rm GR16:$src2, addr:$src1)>;
3182 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
3183 (CMOVNO32rm GR32:$src2, addr:$src1)>;
3184 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
3185 (CMOVO16rm GR16:$src2, addr:$src1)>;
3186 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
3187 (CMOVO32rm GR32:$src2, addr:$src1)>;
3189 // zextload bool -> zextload byte
3190 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3191 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3192 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3194 // extload bool -> extload byte
3195 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3196 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>,
3197 Requires<[In32BitMode]>;
3198 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3199 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>,
3200 Requires<[In32BitMode]>;
3201 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
3202 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
3205 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>,
3206 Requires<[In32BitMode]>;
3207 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>,
3208 Requires<[In32BitMode]>;
3209 def : Pat<(i32 (anyext GR16:$src)),
3210 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
3212 // (and (i32 load), 255) -> (zextload i8)
3213 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
3214 (MOVZX32rm8 addr:$src)>;
3215 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
3216 (MOVZX32rm16 addr:$src)>;
3218 //===----------------------------------------------------------------------===//
3220 //===----------------------------------------------------------------------===//
3222 // Odd encoding trick: -128 fits into an 8-bit immediate field while
3223 // +128 doesn't, so in this special case use a sub instead of an add.
3224 def : Pat<(add GR16:$src1, 128),
3225 (SUB16ri8 GR16:$src1, -128)>;
3226 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
3227 (SUB16mi8 addr:$dst, -128)>;
3228 def : Pat<(add GR32:$src1, 128),
3229 (SUB32ri8 GR32:$src1, -128)>;
3230 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
3231 (SUB32mi8 addr:$dst, -128)>;
3233 // r & (2^16-1) ==> movz
3234 def : Pat<(and GR32:$src1, 0xffff),
3235 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit)))>;
3236 // r & (2^8-1) ==> movz
3237 def : Pat<(and GR32:$src1, 0xff),
3238 (MOVZX32rr8 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src1),
3239 x86_subreg_8bit)))>,
3240 Requires<[In32BitMode]>;
3241 // r & (2^8-1) ==> movz
3242 def : Pat<(and GR16:$src1, 0xff),
3243 (MOVZX16rr8 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src1),
3244 x86_subreg_8bit)))>,
3245 Requires<[In32BitMode]>;
3247 // sext_inreg patterns
3248 def : Pat<(sext_inreg GR32:$src, i16),
3249 (MOVSX32rr16 (i16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)))>;
3250 def : Pat<(sext_inreg GR32:$src, i8),
3251 (MOVSX32rr8 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src),
3252 x86_subreg_8bit)))>,
3253 Requires<[In32BitMode]>;
3254 def : Pat<(sext_inreg GR16:$src, i8),
3255 (MOVSX16rr8 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src),
3256 x86_subreg_8bit)))>,
3257 Requires<[In32BitMode]>;
3260 def : Pat<(i16 (trunc GR32:$src)),
3261 (i16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
3262 def : Pat<(i8 (trunc GR32:$src)),
3263 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src), x86_subreg_8bit))>,
3264 Requires<[In32BitMode]>;
3265 def : Pat<(i8 (trunc GR16:$src)),
3266 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src), x86_subreg_8bit))>,
3267 Requires<[In32BitMode]>;
3269 // (shl x, 1) ==> (add x, x)
3270 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
3271 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
3272 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
3274 // (shl x (and y, 31)) ==> (shl x, y)
3275 def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
3276 (SHL8rCL GR8:$src1)>;
3277 def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
3278 (SHL16rCL GR16:$src1)>;
3279 def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
3280 (SHL32rCL GR32:$src1)>;
3281 def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3282 (SHL8mCL addr:$dst)>;
3283 def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3284 (SHL16mCL addr:$dst)>;
3285 def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3286 (SHL32mCL addr:$dst)>;
3288 def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
3289 (SHR8rCL GR8:$src1)>;
3290 def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
3291 (SHR16rCL GR16:$src1)>;
3292 def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
3293 (SHR32rCL GR32:$src1)>;
3294 def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3295 (SHR8mCL addr:$dst)>;
3296 def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3297 (SHR16mCL addr:$dst)>;
3298 def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3299 (SHR32mCL addr:$dst)>;
3301 def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
3302 (SAR8rCL GR8:$src1)>;
3303 def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
3304 (SAR16rCL GR16:$src1)>;
3305 def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
3306 (SAR32rCL GR32:$src1)>;
3307 def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3308 (SAR8mCL addr:$dst)>;
3309 def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3310 (SAR16mCL addr:$dst)>;
3311 def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3312 (SAR32mCL addr:$dst)>;
3314 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
3315 def : Pat<(or (srl GR32:$src1, CL:$amt),
3316 (shl GR32:$src2, (sub 32, CL:$amt))),
3317 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3319 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
3320 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3321 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3323 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
3324 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3325 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3327 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3328 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3330 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3332 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3333 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3335 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
3336 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3337 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3339 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
3340 def : Pat<(or (shl GR32:$src1, CL:$amt),
3341 (srl GR32:$src2, (sub 32, CL:$amt))),
3342 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3344 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
3345 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3346 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3348 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
3349 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3350 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3352 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3353 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3355 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3357 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3358 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3360 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
3361 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3362 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3364 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
3365 def : Pat<(or (srl GR16:$src1, CL:$amt),
3366 (shl GR16:$src2, (sub 16, CL:$amt))),
3367 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3369 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
3370 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3371 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3373 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
3374 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3375 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3377 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3378 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3380 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3382 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3383 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3385 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
3386 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3387 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3389 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
3390 def : Pat<(or (shl GR16:$src1, CL:$amt),
3391 (srl GR16:$src2, (sub 16, CL:$amt))),
3392 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3394 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
3395 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3396 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3398 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
3399 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3400 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3402 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3403 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3405 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3407 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3408 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3410 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
3411 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3412 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3414 //===----------------------------------------------------------------------===//
3415 // Overflow Patterns
3416 //===----------------------------------------------------------------------===//
3418 // Register-Register Addition with Overflow
3419 def : Pat<(parallel (X86add_ovf GR8:$src1, GR8:$src2),
3421 (ADD8rr GR8:$src1, GR8:$src2)>;
3423 // Register-Register Addition with Overflow
3424 def : Pat<(parallel (X86add_ovf GR16:$src1, GR16:$src2),
3426 (ADD16rr GR16:$src1, GR16:$src2)>;
3427 def : Pat<(parallel (X86add_ovf GR32:$src1, GR32:$src2),
3429 (ADD32rr GR32:$src1, GR32:$src2)>;
3431 // Register-Memory Addition with Overflow
3432 def : Pat<(parallel (X86add_ovf GR8:$src1, (load addr:$src2)),
3434 (ADD8rm GR8:$src1, addr:$src2)>;
3435 def : Pat<(parallel (X86add_ovf GR16:$src1, (load addr:$src2)),
3437 (ADD16rm GR16:$src1, addr:$src2)>;
3438 def : Pat<(parallel (X86add_ovf GR32:$src1, (load addr:$src2)),
3440 (ADD32rm GR32:$src1, addr:$src2)>;
3442 // Register-Integer Addition with Overflow
3443 def : Pat<(parallel (X86add_ovf GR8:$src1, imm:$src2),
3445 (ADD8ri GR8:$src1, imm:$src2)>;
3447 // Register-Integer Addition with Overflow
3448 def : Pat<(parallel (X86add_ovf GR16:$src1, imm:$src2),
3450 (ADD16ri GR16:$src1, imm:$src2)>;
3451 def : Pat<(parallel (X86add_ovf GR32:$src1, imm:$src2),
3453 (ADD32ri GR32:$src1, imm:$src2)>;
3454 def : Pat<(parallel (X86add_ovf GR16:$src1, i16immSExt8:$src2),
3456 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
3457 def : Pat<(parallel (X86add_ovf GR32:$src1, i32immSExt8:$src2),
3459 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3461 // Memory-Register Addition with Overflow
3462 def : Pat<(parallel (store (X86add_ovf (load addr:$dst), GR8:$src2),
3465 (ADD8mr addr:$dst, GR8:$src2)>;
3466 def : Pat<(parallel (store (X86add_ovf (load addr:$dst), GR16:$src2),
3469 (ADD16mr addr:$dst, GR16:$src2)>;
3470 def : Pat<(parallel (store (X86add_ovf (load addr:$dst), GR32:$src2),
3473 (ADD32mr addr:$dst, GR32:$src2)>;
3474 def : Pat<(parallel (store (X86add_ovf (loadi8 addr:$dst), imm:$src2),
3477 (ADD8mi addr:$dst, imm:$src2)>;
3478 def : Pat<(parallel (store (X86add_ovf (loadi16 addr:$dst), imm:$src2),
3481 (ADD16mi addr:$dst, imm:$src2)>;
3482 def : Pat<(parallel (store (X86add_ovf (loadi32 addr:$dst), imm:$src2),
3485 (ADD32mi addr:$dst, imm:$src2)>;
3486 def : Pat<(parallel (store (X86add_ovf (load addr:$dst), i16immSExt8:$src2),
3489 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
3490 def : Pat<(parallel (store (X86add_ovf (load addr:$dst), i32immSExt8:$src2),
3493 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
3495 // Register-Register Subtraction with Overflow
3496 def : Pat<(parallel (X86sub_ovf GR8:$src1, GR8:$src2),
3498 (SUB8rr GR8:$src1, GR8:$src2)>;
3499 def : Pat<(parallel (X86sub_ovf GR16:$src1, GR16:$src2),
3501 (SUB16rr GR16:$src1, GR16:$src2)>;
3502 def : Pat<(parallel (X86sub_ovf GR32:$src1, GR32:$src2),
3504 (SUB32rr GR32:$src1, GR32:$src2)>;
3506 // Register-Memory Subtraction with Overflow
3507 def : Pat<(parallel (X86sub_ovf GR8:$src1, (load addr:$src2)),
3509 (SUB8rm GR8:$src1, addr:$src2)>;
3510 def : Pat<(parallel (X86sub_ovf GR16:$src1, (load addr:$src2)),
3512 (SUB16rm GR16:$src1, addr:$src2)>;
3513 def : Pat<(parallel (X86sub_ovf GR32:$src1, (load addr:$src2)),
3515 (SUB32rm GR32:$src1, addr:$src2)>;
3517 // Register-Integer Subtraction with Overflow
3518 def : Pat<(parallel (X86sub_ovf GR8:$src1, imm:$src2),
3520 (SUB8ri GR8:$src1, imm:$src2)>;
3521 def : Pat<(parallel (X86sub_ovf GR16:$src1, imm:$src2),
3523 (SUB16ri GR16:$src1, imm:$src2)>;
3524 def : Pat<(parallel (X86sub_ovf GR32:$src1, imm:$src2),
3526 (SUB32ri GR32:$src1, imm:$src2)>;
3527 def : Pat<(parallel (X86sub_ovf GR16:$src1, i16immSExt8:$src2),
3529 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
3530 def : Pat<(parallel (X86sub_ovf GR32:$src1, i32immSExt8:$src2),
3532 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3534 // Memory-Register Subtraction with Overflow
3535 def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), GR8:$src2),
3538 (SUB8mr addr:$dst, GR8:$src2)>;
3539 def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), GR16:$src2),
3542 (SUB16mr addr:$dst, GR16:$src2)>;
3543 def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), GR32:$src2),
3546 (SUB32mr addr:$dst, GR32:$src2)>;
3548 // Memory-Integer Subtraction with Overflow
3549 def : Pat<(parallel (store (X86sub_ovf (loadi8 addr:$dst), imm:$src2),
3552 (SUB8mi addr:$dst, imm:$src2)>;
3553 def : Pat<(parallel (store (X86sub_ovf (loadi16 addr:$dst), imm:$src2),
3556 (SUB16mi addr:$dst, imm:$src2)>;
3557 def : Pat<(parallel (store (X86sub_ovf (loadi32 addr:$dst), imm:$src2),
3560 (SUB32mi addr:$dst, imm:$src2)>;
3561 def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), i16immSExt8:$src2),
3564 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
3565 def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), i32immSExt8:$src2),
3568 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
3571 // Register-Register Signed Integer Multiply with Overflow
3572 def : Pat<(parallel (X86smul_ovf GR16:$src1, GR16:$src2),
3574 (IMUL16rr GR16:$src1, GR16:$src2)>;
3575 def : Pat<(parallel (X86smul_ovf GR32:$src1, GR32:$src2),
3577 (IMUL32rr GR32:$src1, GR32:$src2)>;
3579 // Register-Memory Signed Integer Multiply with Overflow
3580 def : Pat<(parallel (X86smul_ovf GR16:$src1, (load addr:$src2)),
3582 (IMUL16rm GR16:$src1, addr:$src2)>;
3583 def : Pat<(parallel (X86smul_ovf GR32:$src1, (load addr:$src2)),
3585 (IMUL32rm GR32:$src1, addr:$src2)>;
3587 // Register-Integer Signed Integer Multiply with Overflow
3588 def : Pat<(parallel (X86smul_ovf GR16:$src1, imm:$src2),
3590 (IMUL16rri GR16:$src1, imm:$src2)>;
3591 def : Pat<(parallel (X86smul_ovf GR32:$src1, imm:$src2),
3593 (IMUL32rri GR32:$src1, imm:$src2)>;
3594 def : Pat<(parallel (X86smul_ovf GR16:$src1, i16immSExt8:$src2),
3596 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
3597 def : Pat<(parallel (X86smul_ovf GR32:$src1, i32immSExt8:$src2),
3599 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
3601 // Memory-Integer Signed Integer Multiply with Overflow
3602 def : Pat<(parallel (X86smul_ovf (load addr:$src1), imm:$src2),
3604 (IMUL16rmi addr:$src1, imm:$src2)>;
3605 def : Pat<(parallel (X86smul_ovf (load addr:$src1), imm:$src2),
3607 (IMUL32rmi addr:$src1, imm:$src2)>;
3608 def : Pat<(parallel (X86smul_ovf (load addr:$src1), i16immSExt8:$src2),
3610 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
3611 def : Pat<(parallel (X86smul_ovf (load addr:$src1), i32immSExt8:$src2),
3613 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
3615 // Optimize multiple with overflow by 2.
3616 let AddedComplexity = 2 in {
3617 def : Pat<(parallel (X86smul_ovf GR16:$src1, 2),
3619 (ADD16rr GR16:$src1, GR16:$src1)>;
3621 def : Pat<(parallel (X86smul_ovf GR32:$src1, 2),
3623 (ADD32rr GR32:$src1, GR32:$src1)>;
3626 //===----------------------------------------------------------------------===//
3627 // Floating Point Stack Support
3628 //===----------------------------------------------------------------------===//
3630 include "X86InstrFPStack.td"
3632 //===----------------------------------------------------------------------===//
3634 //===----------------------------------------------------------------------===//
3636 include "X86Instr64bit.td"
3638 //===----------------------------------------------------------------------===//
3639 // XMM Floating point support (requires SSE / SSE2)
3640 //===----------------------------------------------------------------------===//
3642 include "X86InstrSSE.td"
3644 //===----------------------------------------------------------------------===//
3645 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
3646 //===----------------------------------------------------------------------===//
3648 include "X86InstrMMX.td"