1 //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
30 def SDTX86BrCond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>;
33 def SDTX86SetCC : SDTypeProfile<1, 1,
34 [SDTCisVT<0, i8>, SDTCisVT<1, i8>]>;
36 def SDTX86Ret : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>;
38 def SDT_X86CallSeqStart : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
39 def SDT_X86CallSeqEnd : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>,
42 def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
44 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
46 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
48 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
50 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
51 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
53 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest,
54 [SDNPHasChain, SDNPOutFlag]>;
56 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov,
57 [SDNPInFlag, SDNPOutFlag]>;
58 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
59 [SDNPHasChain, SDNPInFlag]>;
60 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC,
61 [SDNPInFlag, SDNPOutFlag]>;
63 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
64 [SDNPHasChain, SDNPOptInFlag]>;
66 def X86callseq_start :
67 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
68 [SDNPHasChain, SDNPOutFlag]>;
70 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
71 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
73 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
74 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
76 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
77 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
79 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
80 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
81 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
82 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
84 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
85 [SDNPHasChain, SDNPOutFlag]>;
87 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
89 //===----------------------------------------------------------------------===//
90 // X86 Operand Definitions.
93 // *mem - Operand definitions for the funky X86 addressing mode operands.
95 class X86MemOperand<string printMethod> : Operand<iPTR> {
96 let PrintMethod = printMethod;
97 let NumMIOperands = 4;
98 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
101 def i8mem : X86MemOperand<"printi8mem">;
102 def i16mem : X86MemOperand<"printi16mem">;
103 def i32mem : X86MemOperand<"printi32mem">;
104 def i64mem : X86MemOperand<"printi64mem">;
105 def i128mem : X86MemOperand<"printi128mem">;
106 def f32mem : X86MemOperand<"printf32mem">;
107 def f64mem : X86MemOperand<"printf64mem">;
108 def f128mem : X86MemOperand<"printf128mem">;
110 def lea32mem : Operand<i32> {
111 let PrintMethod = "printi32mem";
112 let NumMIOperands = 4;
113 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
116 def SSECC : Operand<i8> {
117 let PrintMethod = "printSSECC";
120 def piclabel: Operand<i32> {
121 let PrintMethod = "printPICLabel";
124 // A couple of more descriptive operand definitions.
125 // 16-bits but only 8 bits are significant.
126 def i16i8imm : Operand<i16>;
127 // 32-bits but only 8 bits are significant.
128 def i32i8imm : Operand<i32>;
130 // Branch targets have OtherVT type.
131 def brtarget : Operand<OtherVT>;
133 //===----------------------------------------------------------------------===//
134 // X86 Complex Pattern Definitions.
137 // Define X86 specific addressing mode.
138 def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
139 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
140 [add, mul, shl, or, frameindex], []>;
142 //===----------------------------------------------------------------------===//
143 // X86 Instruction Format Definitions.
146 // Format specifies the encoding used by the instruction. This is part of the
147 // ad-hoc solution used to emit machine instruction encodings by our machine
149 class Format<bits<6> val> {
153 def Pseudo : Format<0>; def RawFrm : Format<1>;
154 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
155 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
156 def MRMSrcMem : Format<6>;
157 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
158 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
159 def MRM6r : Format<22>; def MRM7r : Format<23>;
160 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
161 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
162 def MRM6m : Format<30>; def MRM7m : Format<31>;
163 def MRMInitReg : Format<32>;
165 //===----------------------------------------------------------------------===//
166 // X86 Instruction Predicate Definitions.
167 def HasMMX : Predicate<"Subtarget->hasMMX()">;
168 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
169 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
170 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
171 def FPStack : Predicate<"!Subtarget->hasSSE2()">;
172 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
173 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
175 //===----------------------------------------------------------------------===//
176 // X86 specific pattern fragments.
179 // ImmType - This specifies the immediate type used by an instruction. This is
180 // part of the ad-hoc solution used to emit machine instruction encodings by our
181 // machine code emitter.
182 class ImmType<bits<3> val> {
185 def NoImm : ImmType<0>;
186 def Imm8 : ImmType<1>;
187 def Imm16 : ImmType<2>;
188 def Imm32 : ImmType<3>;
189 def Imm64 : ImmType<4>;
191 // FPFormat - This specifies what form this FP instruction has. This is used by
192 // the Floating-Point stackifier pass.
193 class FPFormat<bits<3> val> {
196 def NotFP : FPFormat<0>;
197 def ZeroArgFP : FPFormat<1>;
198 def OneArgFP : FPFormat<2>;
199 def OneArgFPRW : FPFormat<3>;
200 def TwoArgFP : FPFormat<4>;
201 def CompareFP : FPFormat<5>;
202 def CondMovFP : FPFormat<6>;
203 def SpecialFP : FPFormat<7>;
206 class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr>
208 let Namespace = "X86";
210 bits<8> Opcode = opcod;
212 bits<6> FormBits = Form.Value;
214 bits<3> ImmTypeBits = ImmT.Value;
216 dag OperandList = ops;
217 string AsmString = AsmStr;
220 // Attributes specific to X86 instructions...
222 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
223 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
225 bits<4> Prefix = 0; // Which prefix byte does this inst have?
226 bit hasREX_WPrefix = 0; // Does this inst requires the REX.W prefix?
227 FPFormat FPForm; // What flavor of FP instruction is this?
228 bits<3> FPFormBits = 0;
232 // Prefix byte classes which are used to indicate to the ad-hoc machine code
233 // emitter that various prefix bytes are required.
234 class OpSize { bit hasOpSizePrefix = 1; }
235 class AdSize { bit hasAdSizePrefix = 1; }
236 class REX_W { bit hasREX_WPrefix = 1; }
237 class TB { bits<4> Prefix = 1; }
238 class REP { bits<4> Prefix = 2; }
239 class D8 { bits<4> Prefix = 3; }
240 class D9 { bits<4> Prefix = 4; }
241 class DA { bits<4> Prefix = 5; }
242 class DB { bits<4> Prefix = 6; }
243 class DC { bits<4> Prefix = 7; }
244 class DD { bits<4> Prefix = 8; }
245 class DE { bits<4> Prefix = 9; }
246 class DF { bits<4> Prefix = 10; }
247 class XD { bits<4> Prefix = 11; }
248 class XS { bits<4> Prefix = 12; }
251 //===----------------------------------------------------------------------===//
252 // Pattern fragments...
255 // X86 specific condition code. These correspond to CondCode in
256 // X86ISelLowering.h. They must be kept in synch.
257 def X86_COND_A : PatLeaf<(i8 0)>;
258 def X86_COND_AE : PatLeaf<(i8 1)>;
259 def X86_COND_B : PatLeaf<(i8 2)>;
260 def X86_COND_BE : PatLeaf<(i8 3)>;
261 def X86_COND_E : PatLeaf<(i8 4)>;
262 def X86_COND_G : PatLeaf<(i8 5)>;
263 def X86_COND_GE : PatLeaf<(i8 6)>;
264 def X86_COND_L : PatLeaf<(i8 7)>;
265 def X86_COND_LE : PatLeaf<(i8 8)>;
266 def X86_COND_NE : PatLeaf<(i8 9)>;
267 def X86_COND_NO : PatLeaf<(i8 10)>;
268 def X86_COND_NP : PatLeaf<(i8 11)>;
269 def X86_COND_NS : PatLeaf<(i8 12)>;
270 def X86_COND_O : PatLeaf<(i8 13)>;
271 def X86_COND_P : PatLeaf<(i8 14)>;
272 def X86_COND_S : PatLeaf<(i8 15)>;
274 def i16immSExt8 : PatLeaf<(i16 imm), [{
275 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
276 // sign extended field.
277 return (int16_t)N->getValue() == (int8_t)N->getValue();
280 def i32immSExt8 : PatLeaf<(i32 imm), [{
281 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
282 // sign extended field.
283 return (int32_t)N->getValue() == (int8_t)N->getValue();
286 // Helper fragments for loads.
287 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
288 def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>;
289 def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>;
290 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
292 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
293 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
295 def sextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (sextloadi1 node:$ptr))>;
296 def sextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (sextloadi1 node:$ptr))>;
297 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
298 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
299 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
301 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
302 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
303 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
304 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
305 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
306 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
308 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
309 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
310 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
311 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
312 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
313 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
315 //===----------------------------------------------------------------------===//
316 // Instruction templates...
319 class I<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
320 : X86Inst<o, f, NoImm, ops, asm> {
321 let Pattern = pattern;
324 class Ii8 <bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
325 : X86Inst<o, f, Imm8 , ops, asm> {
326 let Pattern = pattern;
329 class Ii16<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
330 : X86Inst<o, f, Imm16, ops, asm> {
331 let Pattern = pattern;
334 class Ii32<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
335 : X86Inst<o, f, Imm32, ops, asm> {
336 let Pattern = pattern;
340 //===----------------------------------------------------------------------===//
341 // Instruction list...
344 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
345 // a stack adjustment and the codegen must know that they may modify the stack
346 // pointer before prolog-epilog rewriting occurs.
347 def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN",
348 [(X86callseq_start imm:$amt)]>, Imp<[ESP],[ESP]>;
349 def ADJCALLSTACKUP : I<0, Pseudo, (ops i32imm:$amt1, i32imm:$amt2),
351 [(X86callseq_end imm:$amt1, imm:$amt2)]>,
353 def IMPLICIT_USE : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE", []>;
354 def IMPLICIT_DEF : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF", []>;
355 def IMPLICIT_DEF_GR8 : I<0, Pseudo, (ops GR8:$dst),
356 "#IMPLICIT_DEF $dst",
357 [(set GR8:$dst, (undef))]>;
358 def IMPLICIT_DEF_GR16 : I<0, Pseudo, (ops GR16:$dst),
359 "#IMPLICIT_DEF $dst",
360 [(set GR16:$dst, (undef))]>;
361 def IMPLICIT_DEF_GR32 : I<0, Pseudo, (ops GR32:$dst),
362 "#IMPLICIT_DEF $dst",
363 [(set GR32:$dst, (undef))]>;
366 def NOOP : I<0x90, RawFrm, (ops), "nop", []>;
369 def TRUNC_32_to8 : I<0x88, MRMDestReg, (ops GR8:$dst, GR32_:$src),
370 "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}", []>;
371 def TRUNC_16_to8 : I<0x88, MRMDestReg, (ops GR8:$dst, GR16_:$src),
372 "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}}", []>;
373 def TRUNC_32to16 : I<0x89, MRMDestReg, (ops GR16:$dst, GR32:$src),
374 "mov{w} {${src:subreg16}, $dst|$dst, ${src:subreg16}}",
375 [(set GR16:$dst, (trunc GR32:$src))]>;
377 //===----------------------------------------------------------------------===//
378 // Control Flow Instructions...
381 // Return instructions.
382 let isTerminator = 1, isReturn = 1, isBarrier = 1,
383 hasCtrlDep = 1, noResults = 1 in {
384 def RET : I<0xC3, RawFrm, (ops), "ret", [(X86retflag 0)]>;
385 def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt",
386 [(X86retflag imm:$amt)]>;
389 // All branches are RawFrm, Void, Branch, and Terminators
390 let isBranch = 1, isTerminator = 1, noResults = 1 in
391 class IBr<bits<8> opcode, dag ops, string asm, list<dag> pattern> :
392 I<opcode, RawFrm, ops, asm, pattern>;
395 let isBranch = 1, isBarrier = 1 in
396 def JMP : IBr<0xE9, (ops brtarget:$dst), "jmp $dst", [(br bb:$dst)]>;
398 let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in {
399 def JMP32r : I<0xFF, MRM4r, (ops GR32:$dst), "jmp{l} {*}$dst",
400 [(brind GR32:$dst)]>;
401 def JMP32m : I<0xFF, MRM4m, (ops i32mem:$dst), "jmp{l} {*}$dst",
402 [(brind (loadi32 addr:$dst))]>;
405 // Conditional branches
406 def JE : IBr<0x84, (ops brtarget:$dst), "je $dst",
407 [(X86brcond bb:$dst, X86_COND_E)]>, TB;
408 def JNE : IBr<0x85, (ops brtarget:$dst), "jne $dst",
409 [(X86brcond bb:$dst, X86_COND_NE)]>, TB;
410 def JL : IBr<0x8C, (ops brtarget:$dst), "jl $dst",
411 [(X86brcond bb:$dst, X86_COND_L)]>, TB;
412 def JLE : IBr<0x8E, (ops brtarget:$dst), "jle $dst",
413 [(X86brcond bb:$dst, X86_COND_LE)]>, TB;
414 def JG : IBr<0x8F, (ops brtarget:$dst), "jg $dst",
415 [(X86brcond bb:$dst, X86_COND_G)]>, TB;
416 def JGE : IBr<0x8D, (ops brtarget:$dst), "jge $dst",
417 [(X86brcond bb:$dst, X86_COND_GE)]>, TB;
419 def JB : IBr<0x82, (ops brtarget:$dst), "jb $dst",
420 [(X86brcond bb:$dst, X86_COND_B)]>, TB;
421 def JBE : IBr<0x86, (ops brtarget:$dst), "jbe $dst",
422 [(X86brcond bb:$dst, X86_COND_BE)]>, TB;
423 def JA : IBr<0x87, (ops brtarget:$dst), "ja $dst",
424 [(X86brcond bb:$dst, X86_COND_A)]>, TB;
425 def JAE : IBr<0x83, (ops brtarget:$dst), "jae $dst",
426 [(X86brcond bb:$dst, X86_COND_AE)]>, TB;
428 def JS : IBr<0x88, (ops brtarget:$dst), "js $dst",
429 [(X86brcond bb:$dst, X86_COND_S)]>, TB;
430 def JNS : IBr<0x89, (ops brtarget:$dst), "jns $dst",
431 [(X86brcond bb:$dst, X86_COND_NS)]>, TB;
432 def JP : IBr<0x8A, (ops brtarget:$dst), "jp $dst",
433 [(X86brcond bb:$dst, X86_COND_P)]>, TB;
434 def JNP : IBr<0x8B, (ops brtarget:$dst), "jnp $dst",
435 [(X86brcond bb:$dst, X86_COND_NP)]>, TB;
436 def JO : IBr<0x80, (ops brtarget:$dst), "jo $dst",
437 [(X86brcond bb:$dst, X86_COND_O)]>, TB;
438 def JNO : IBr<0x81, (ops brtarget:$dst), "jno $dst",
439 [(X86brcond bb:$dst, X86_COND_NO)]>, TB;
441 //===----------------------------------------------------------------------===//
442 // Call Instructions...
444 let isCall = 1, noResults = 1 in
445 // All calls clobber the non-callee saved registers...
446 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
447 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in {
448 def CALLpcrel32 : I<0xE8, RawFrm, (ops i32imm:$dst, variable_ops),
449 "call ${dst:call}", []>;
450 def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
451 "call {*}$dst", [(X86call GR32:$dst)]>;
452 def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst, variable_ops),
457 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
458 def TAILJMPd : IBr<0xE9, (ops i32imm:$dst), "jmp ${dst:call} # TAIL CALL",
460 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
461 def TAILJMPr : I<0xFF, MRM4r, (ops GR32:$dst), "jmp {*}$dst # TAIL CALL",
463 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
464 def TAILJMPm : I<0xFF, MRM4m, (ops i32mem:$dst),
465 "jmp {*}$dst # TAIL CALL", []>;
467 //===----------------------------------------------------------------------===//
468 // Miscellaneous Instructions...
470 def LEAVE : I<0xC9, RawFrm,
471 (ops), "leave", []>, Imp<[EBP,ESP],[EBP,ESP]>;
472 def POP32r : I<0x58, AddRegFrm,
473 (ops GR32:$reg), "pop{l} $reg", []>, Imp<[ESP],[ESP]>;
475 def MovePCtoStack : I<0, Pseudo, (ops piclabel:$label),
478 let isTwoAddress = 1 in // GR32 = bswap GR32
479 def BSWAP32r : I<0xC8, AddRegFrm,
480 (ops GR32:$dst, GR32:$src),
482 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
484 def XCHG8rr : I<0x86, MRMDestReg, // xchg GR8, GR8
485 (ops GR8:$src1, GR8:$src2),
486 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
487 def XCHG16rr : I<0x87, MRMDestReg, // xchg GR16, GR16
488 (ops GR16:$src1, GR16:$src2),
489 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
490 def XCHG32rr : I<0x87, MRMDestReg, // xchg GR32, GR32
491 (ops GR32:$src1, GR32:$src2),
492 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
494 def XCHG8mr : I<0x86, MRMDestMem,
495 (ops i8mem:$src1, GR8:$src2),
496 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
497 def XCHG16mr : I<0x87, MRMDestMem,
498 (ops i16mem:$src1, GR16:$src2),
499 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
500 def XCHG32mr : I<0x87, MRMDestMem,
501 (ops i32mem:$src1, GR32:$src2),
502 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
503 def XCHG8rm : I<0x86, MRMSrcMem,
504 (ops GR8:$src1, i8mem:$src2),
505 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
506 def XCHG16rm : I<0x87, MRMSrcMem,
507 (ops GR16:$src1, i16mem:$src2),
508 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
509 def XCHG32rm : I<0x87, MRMSrcMem,
510 (ops GR32:$src1, i32mem:$src2),
511 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
513 def LEA16r : I<0x8D, MRMSrcMem,
514 (ops GR16:$dst, i32mem:$src),
515 "lea{w} {$src|$dst}, {$dst|$src}", []>, OpSize;
516 def LEA32r : I<0x8D, MRMSrcMem,
517 (ops GR32:$dst, lea32mem:$src),
518 "lea{l} {$src|$dst}, {$dst|$src}",
519 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
521 def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}",
523 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
524 def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}",
525 [(X86rep_movs i16)]>,
526 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize;
527 def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsl|rep movsd}",
528 [(X86rep_movs i32)]>,
529 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
531 def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}",
533 Imp<[AL,ECX,EDI], [ECX,EDI]>, REP;
534 def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}",
535 [(X86rep_stos i16)]>,
536 Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize;
537 def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}",
538 [(X86rep_stos i32)]>,
539 Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP;
542 //===----------------------------------------------------------------------===//
543 // Input/Output Instructions...
545 def IN8rr : I<0xEC, RawFrm, (ops),
546 "in{b} {%dx, %al|%AL, %DX}",
547 []>, Imp<[DX], [AL]>;
548 def IN16rr : I<0xED, RawFrm, (ops),
549 "in{w} {%dx, %ax|%AX, %DX}",
550 []>, Imp<[DX], [AX]>, OpSize;
551 def IN32rr : I<0xED, RawFrm, (ops),
552 "in{l} {%dx, %eax|%EAX, %DX}",
553 []>, Imp<[DX],[EAX]>;
555 def IN8ri : Ii8<0xE4, RawFrm, (ops i16i8imm:$port),
556 "in{b} {$port, %al|%AL, $port}",
559 def IN16ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port),
560 "in{w} {$port, %ax|%AX, $port}",
562 Imp<[], [AX]>, OpSize;
563 def IN32ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port),
564 "in{l} {$port, %eax|%EAX, $port}",
568 def OUT8rr : I<0xEE, RawFrm, (ops),
569 "out{b} {%al, %dx|%DX, %AL}",
570 []>, Imp<[DX, AL], []>;
571 def OUT16rr : I<0xEF, RawFrm, (ops),
572 "out{w} {%ax, %dx|%DX, %AX}",
573 []>, Imp<[DX, AX], []>, OpSize;
574 def OUT32rr : I<0xEF, RawFrm, (ops),
575 "out{l} {%eax, %dx|%DX, %EAX}",
576 []>, Imp<[DX, EAX], []>;
578 def OUT8ir : Ii8<0xE6, RawFrm, (ops i16i8imm:$port),
579 "out{b} {%al, $port|$port, %AL}",
582 def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
583 "out{w} {%ax, $port|$port, %AX}",
585 Imp<[AX], []>, OpSize;
586 def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
587 "out{l} {%eax, $port|$port, %EAX}",
591 //===----------------------------------------------------------------------===//
592 // Move Instructions...
594 def MOV8rr : I<0x88, MRMDestReg, (ops GR8 :$dst, GR8 :$src),
595 "mov{b} {$src, $dst|$dst, $src}", []>;
596 def MOV16rr : I<0x89, MRMDestReg, (ops GR16:$dst, GR16:$src),
597 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
598 def MOV32rr : I<0x89, MRMDestReg, (ops GR32:$dst, GR32:$src),
599 "mov{l} {$src, $dst|$dst, $src}", []>;
600 def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops GR8 :$dst, i8imm :$src),
601 "mov{b} {$src, $dst|$dst, $src}",
602 [(set GR8:$dst, imm:$src)]>;
603 def MOV16ri : Ii16<0xB8, AddRegFrm, (ops GR16:$dst, i16imm:$src),
604 "mov{w} {$src, $dst|$dst, $src}",
605 [(set GR16:$dst, imm:$src)]>, OpSize;
606 def MOV32ri : Ii32<0xB8, AddRegFrm, (ops GR32:$dst, i32imm:$src),
607 "mov{l} {$src, $dst|$dst, $src}",
608 [(set GR32:$dst, imm:$src)]>;
609 def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src),
610 "mov{b} {$src, $dst|$dst, $src}",
611 [(store (i8 imm:$src), addr:$dst)]>;
612 def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src),
613 "mov{w} {$src, $dst|$dst, $src}",
614 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
615 def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src),
616 "mov{l} {$src, $dst|$dst, $src}",
617 [(store (i32 imm:$src), addr:$dst)]>;
619 def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src),
620 "mov{b} {$src, $dst|$dst, $src}",
621 [(set GR8:$dst, (load addr:$src))]>;
622 def MOV16rm : I<0x8B, MRMSrcMem, (ops GR16:$dst, i16mem:$src),
623 "mov{w} {$src, $dst|$dst, $src}",
624 [(set GR16:$dst, (load addr:$src))]>, OpSize;
625 def MOV32rm : I<0x8B, MRMSrcMem, (ops GR32:$dst, i32mem:$src),
626 "mov{l} {$src, $dst|$dst, $src}",
627 [(set GR32:$dst, (load addr:$src))]>;
629 def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, GR8 :$src),
630 "mov{b} {$src, $dst|$dst, $src}",
631 [(store GR8:$src, addr:$dst)]>;
632 def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, GR16:$src),
633 "mov{w} {$src, $dst|$dst, $src}",
634 [(store GR16:$src, addr:$dst)]>, OpSize;
635 def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, GR32:$src),
636 "mov{l} {$src, $dst|$dst, $src}",
637 [(store GR32:$src, addr:$dst)]>;
639 //===----------------------------------------------------------------------===//
640 // Fixed-Register Multiplication and Division Instructions...
643 // Extra precision multiplication
644 def MUL8r : I<0xF6, MRM4r, (ops GR8:$src), "mul{b} $src",
645 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
646 // This probably ought to be moved to a def : Pat<> if the
647 // syntax can be accepted.
648 [(set AL, (mul AL, GR8:$src))]>,
649 Imp<[AL],[AX]>; // AL,AH = AL*GR8
650 def MUL16r : I<0xF7, MRM4r, (ops GR16:$src), "mul{w} $src", []>,
651 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16
652 def MUL32r : I<0xF7, MRM4r, (ops GR32:$src), "mul{l} $src", []>,
653 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*GR32
654 def MUL8m : I<0xF6, MRM4m, (ops i8mem :$src),
656 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
657 // This probably ought to be moved to a def : Pat<> if the
658 // syntax can be accepted.
659 [(set AL, (mul AL, (loadi8 addr:$src)))]>,
660 Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
661 def MUL16m : I<0xF7, MRM4m, (ops i16mem:$src),
662 "mul{w} $src", []>, Imp<[AX],[AX,DX]>,
663 OpSize; // AX,DX = AX*[mem16]
664 def MUL32m : I<0xF7, MRM4m, (ops i32mem:$src),
665 "mul{l} $src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32]
667 def IMUL8r : I<0xF6, MRM5r, (ops GR8:$src), "imul{b} $src", []>,
668 Imp<[AL],[AX]>; // AL,AH = AL*GR8
669 def IMUL16r : I<0xF7, MRM5r, (ops GR16:$src), "imul{w} $src", []>,
670 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16
671 def IMUL32r : I<0xF7, MRM5r, (ops GR32:$src), "imul{l} $src", []>,
672 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*GR32
673 def IMUL8m : I<0xF6, MRM5m, (ops i8mem :$src),
674 "imul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
675 def IMUL16m : I<0xF7, MRM5m, (ops i16mem:$src),
676 "imul{w} $src", []>, Imp<[AX],[AX,DX]>,
677 OpSize; // AX,DX = AX*[mem16]
678 def IMUL32m : I<0xF7, MRM5m, (ops i32mem:$src),
680 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
682 // unsigned division/remainder
683 def DIV8r : I<0xF6, MRM6r, (ops GR8:$src), // AX/r8 = AL,AH
684 "div{b} $src", []>, Imp<[AX],[AX]>;
685 def DIV16r : I<0xF7, MRM6r, (ops GR16:$src), // DX:AX/r16 = AX,DX
686 "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
687 def DIV32r : I<0xF7, MRM6r, (ops GR32:$src), // EDX:EAX/r32 = EAX,EDX
688 "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
689 def DIV8m : I<0xF6, MRM6m, (ops i8mem:$src), // AX/[mem8] = AL,AH
690 "div{b} $src", []>, Imp<[AX],[AX]>;
691 def DIV16m : I<0xF7, MRM6m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX
692 "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
693 def DIV32m : I<0xF7, MRM6m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
694 "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
696 // Signed division/remainder.
697 def IDIV8r : I<0xF6, MRM7r, (ops GR8:$src), // AX/r8 = AL,AH
698 "idiv{b} $src", []>, Imp<[AX],[AX]>;
699 def IDIV16r: I<0xF7, MRM7r, (ops GR16:$src), // DX:AX/r16 = AX,DX
700 "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
701 def IDIV32r: I<0xF7, MRM7r, (ops GR32:$src), // EDX:EAX/r32 = EAX,EDX
702 "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
703 def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src), // AX/[mem8] = AL,AH
704 "idiv{b} $src", []>, Imp<[AX],[AX]>;
705 def IDIV16m: I<0xF7, MRM7m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX
706 "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
707 def IDIV32m: I<0xF7, MRM7m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
708 "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
711 //===----------------------------------------------------------------------===//
712 // Two address Instructions...
714 let isTwoAddress = 1 in {
717 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
718 (ops GR16:$dst, GR16:$src1, GR16:$src2),
719 "cmovb {$src2, $dst|$dst, $src2}",
720 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
723 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
724 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
725 "cmovb {$src2, $dst|$dst, $src2}",
726 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
729 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
730 (ops GR32:$dst, GR32:$src1, GR32:$src2),
731 "cmovb {$src2, $dst|$dst, $src2}",
732 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
735 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
736 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
737 "cmovb {$src2, $dst|$dst, $src2}",
738 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
742 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
743 (ops GR16:$dst, GR16:$src1, GR16:$src2),
744 "cmovae {$src2, $dst|$dst, $src2}",
745 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
748 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
749 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
750 "cmovae {$src2, $dst|$dst, $src2}",
751 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
754 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
755 (ops GR32:$dst, GR32:$src1, GR32:$src2),
756 "cmovae {$src2, $dst|$dst, $src2}",
757 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
760 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
761 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
762 "cmovae {$src2, $dst|$dst, $src2}",
763 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
767 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
768 (ops GR16:$dst, GR16:$src1, GR16:$src2),
769 "cmove {$src2, $dst|$dst, $src2}",
770 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
773 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
774 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
775 "cmove {$src2, $dst|$dst, $src2}",
776 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
779 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
780 (ops GR32:$dst, GR32:$src1, GR32:$src2),
781 "cmove {$src2, $dst|$dst, $src2}",
782 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
785 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
786 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
787 "cmove {$src2, $dst|$dst, $src2}",
788 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
792 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
793 (ops GR16:$dst, GR16:$src1, GR16:$src2),
794 "cmovne {$src2, $dst|$dst, $src2}",
795 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
798 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
799 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
800 "cmovne {$src2, $dst|$dst, $src2}",
801 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
804 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
805 (ops GR32:$dst, GR32:$src1, GR32:$src2),
806 "cmovne {$src2, $dst|$dst, $src2}",
807 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
810 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
811 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
812 "cmovne {$src2, $dst|$dst, $src2}",
813 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
817 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
818 (ops GR16:$dst, GR16:$src1, GR16:$src2),
819 "cmovbe {$src2, $dst|$dst, $src2}",
820 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
823 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
824 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
825 "cmovbe {$src2, $dst|$dst, $src2}",
826 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
829 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
830 (ops GR32:$dst, GR32:$src1, GR32:$src2),
831 "cmovbe {$src2, $dst|$dst, $src2}",
832 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
835 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
836 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
837 "cmovbe {$src2, $dst|$dst, $src2}",
838 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
842 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
843 (ops GR16:$dst, GR16:$src1, GR16:$src2),
844 "cmova {$src2, $dst|$dst, $src2}",
845 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
848 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
849 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
850 "cmova {$src2, $dst|$dst, $src2}",
851 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
854 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
855 (ops GR32:$dst, GR32:$src1, GR32:$src2),
856 "cmova {$src2, $dst|$dst, $src2}",
857 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
860 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
861 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
862 "cmova {$src2, $dst|$dst, $src2}",
863 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
867 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
868 (ops GR16:$dst, GR16:$src1, GR16:$src2),
869 "cmovl {$src2, $dst|$dst, $src2}",
870 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
873 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
874 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
875 "cmovl {$src2, $dst|$dst, $src2}",
876 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
879 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
880 (ops GR32:$dst, GR32:$src1, GR32:$src2),
881 "cmovl {$src2, $dst|$dst, $src2}",
882 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
885 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
886 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
887 "cmovl {$src2, $dst|$dst, $src2}",
888 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
892 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
893 (ops GR16:$dst, GR16:$src1, GR16:$src2),
894 "cmovge {$src2, $dst|$dst, $src2}",
895 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
898 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
899 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
900 "cmovge {$src2, $dst|$dst, $src2}",
901 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
904 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
905 (ops GR32:$dst, GR32:$src1, GR32:$src2),
906 "cmovge {$src2, $dst|$dst, $src2}",
907 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
910 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
911 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
912 "cmovge {$src2, $dst|$dst, $src2}",
913 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
917 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
918 (ops GR16:$dst, GR16:$src1, GR16:$src2),
919 "cmovle {$src2, $dst|$dst, $src2}",
920 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
923 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
924 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
925 "cmovle {$src2, $dst|$dst, $src2}",
926 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
929 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
930 (ops GR32:$dst, GR32:$src1, GR32:$src2),
931 "cmovle {$src2, $dst|$dst, $src2}",
932 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
935 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
936 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
937 "cmovle {$src2, $dst|$dst, $src2}",
938 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
942 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
943 (ops GR16:$dst, GR16:$src1, GR16:$src2),
944 "cmovg {$src2, $dst|$dst, $src2}",
945 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
948 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
949 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
950 "cmovg {$src2, $dst|$dst, $src2}",
951 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
954 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
955 (ops GR32:$dst, GR32:$src1, GR32:$src2),
956 "cmovg {$src2, $dst|$dst, $src2}",
957 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
960 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
961 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
962 "cmovg {$src2, $dst|$dst, $src2}",
963 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
967 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
968 (ops GR16:$dst, GR16:$src1, GR16:$src2),
969 "cmovs {$src2, $dst|$dst, $src2}",
970 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
973 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
974 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
975 "cmovs {$src2, $dst|$dst, $src2}",
976 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
979 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
980 (ops GR32:$dst, GR32:$src1, GR32:$src2),
981 "cmovs {$src2, $dst|$dst, $src2}",
982 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
985 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
986 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
987 "cmovs {$src2, $dst|$dst, $src2}",
988 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
992 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
993 (ops GR16:$dst, GR16:$src1, GR16:$src2),
994 "cmovns {$src2, $dst|$dst, $src2}",
995 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
998 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
999 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1000 "cmovns {$src2, $dst|$dst, $src2}",
1001 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1004 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1005 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1006 "cmovns {$src2, $dst|$dst, $src2}",
1007 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1010 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1011 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1012 "cmovns {$src2, $dst|$dst, $src2}",
1013 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1017 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1018 (ops GR16:$dst, GR16:$src1, GR16:$src2),
1019 "cmovp {$src2, $dst|$dst, $src2}",
1020 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1023 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1024 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1025 "cmovp {$src2, $dst|$dst, $src2}",
1026 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1029 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1030 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1031 "cmovp {$src2, $dst|$dst, $src2}",
1032 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1035 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1036 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1037 "cmovp {$src2, $dst|$dst, $src2}",
1038 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1042 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1043 (ops GR16:$dst, GR16:$src1, GR16:$src2),
1044 "cmovnp {$src2, $dst|$dst, $src2}",
1045 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1048 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1049 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1050 "cmovnp {$src2, $dst|$dst, $src2}",
1051 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1054 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1055 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1056 "cmovnp {$src2, $dst|$dst, $src2}",
1057 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1060 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1061 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1062 "cmovnp {$src2, $dst|$dst, $src2}",
1063 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1068 // unary instructions
1069 let CodeSize = 2 in {
1070 def NEG8r : I<0xF6, MRM3r, (ops GR8 :$dst, GR8 :$src), "neg{b} $dst",
1071 [(set GR8:$dst, (ineg GR8:$src))]>;
1072 def NEG16r : I<0xF7, MRM3r, (ops GR16:$dst, GR16:$src), "neg{w} $dst",
1073 [(set GR16:$dst, (ineg GR16:$src))]>, OpSize;
1074 def NEG32r : I<0xF7, MRM3r, (ops GR32:$dst, GR32:$src), "neg{l} $dst",
1075 [(set GR32:$dst, (ineg GR32:$src))]>;
1076 let isTwoAddress = 0 in {
1077 def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst",
1078 [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
1079 def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg{w} $dst",
1080 [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1081 def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg{l} $dst",
1082 [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
1086 def NOT8r : I<0xF6, MRM2r, (ops GR8 :$dst, GR8 :$src), "not{b} $dst",
1087 [(set GR8:$dst, (not GR8:$src))]>;
1088 def NOT16r : I<0xF7, MRM2r, (ops GR16:$dst, GR16:$src), "not{w} $dst",
1089 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1090 def NOT32r : I<0xF7, MRM2r, (ops GR32:$dst, GR32:$src), "not{l} $dst",
1091 [(set GR32:$dst, (not GR32:$src))]>;
1092 let isTwoAddress = 0 in {
1093 def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst",
1094 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1095 def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not{w} $dst",
1096 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1097 def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst",
1098 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1102 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1104 def INC8r : I<0xFE, MRM0r, (ops GR8 :$dst, GR8 :$src), "inc{b} $dst",
1105 [(set GR8:$dst, (add GR8:$src, 1))]>;
1106 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1107 def INC16r : I<0x40, AddRegFrm, (ops GR16:$dst, GR16:$src), "inc{w} $dst",
1108 [(set GR16:$dst, (add GR16:$src, 1))]>,
1109 OpSize, Requires<[In32BitMode]>;
1110 def INC32r : I<0x40, AddRegFrm, (ops GR32:$dst, GR32:$src), "inc{l} $dst",
1111 [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>;
1113 let isTwoAddress = 0, CodeSize = 2 in {
1114 def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst",
1115 [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
1116 def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst",
1117 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>, OpSize;
1118 def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst",
1119 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>;
1123 def DEC8r : I<0xFE, MRM1r, (ops GR8 :$dst, GR8 :$src), "dec{b} $dst",
1124 [(set GR8:$dst, (add GR8:$src, -1))]>;
1125 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1126 def DEC16r : I<0x48, AddRegFrm, (ops GR16:$dst, GR16:$src), "dec{w} $dst",
1127 [(set GR16:$dst, (add GR16:$src, -1))]>,
1128 OpSize, Requires<[In32BitMode]>;
1129 def DEC32r : I<0x48, AddRegFrm, (ops GR32:$dst, GR32:$src), "dec{l} $dst",
1130 [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>;
1133 let isTwoAddress = 0, CodeSize = 2 in {
1134 def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst",
1135 [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
1136 def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst",
1137 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>, OpSize;
1138 def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst",
1139 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>;
1142 // Logical operators...
1143 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1144 def AND8rr : I<0x20, MRMDestReg,
1145 (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1146 "and{b} {$src2, $dst|$dst, $src2}",
1147 [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>;
1148 def AND16rr : I<0x21, MRMDestReg,
1149 (ops GR16:$dst, GR16:$src1, GR16:$src2),
1150 "and{w} {$src2, $dst|$dst, $src2}",
1151 [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize;
1152 def AND32rr : I<0x21, MRMDestReg,
1153 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1154 "and{l} {$src2, $dst|$dst, $src2}",
1155 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
1158 def AND8rm : I<0x22, MRMSrcMem,
1159 (ops GR8 :$dst, GR8 :$src1, i8mem :$src2),
1160 "and{b} {$src2, $dst|$dst, $src2}",
1161 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>;
1162 def AND16rm : I<0x23, MRMSrcMem,
1163 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1164 "and{w} {$src2, $dst|$dst, $src2}",
1165 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize;
1166 def AND32rm : I<0x23, MRMSrcMem,
1167 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1168 "and{l} {$src2, $dst|$dst, $src2}",
1169 [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>;
1171 def AND8ri : Ii8<0x80, MRM4r,
1172 (ops GR8 :$dst, GR8 :$src1, i8imm :$src2),
1173 "and{b} {$src2, $dst|$dst, $src2}",
1174 [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>;
1175 def AND16ri : Ii16<0x81, MRM4r,
1176 (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1177 "and{w} {$src2, $dst|$dst, $src2}",
1178 [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize;
1179 def AND32ri : Ii32<0x81, MRM4r,
1180 (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1181 "and{l} {$src2, $dst|$dst, $src2}",
1182 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
1183 def AND16ri8 : Ii8<0x83, MRM4r,
1184 (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1185 "and{w} {$src2, $dst|$dst, $src2}",
1186 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>,
1188 def AND32ri8 : Ii8<0x83, MRM4r,
1189 (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1190 "and{l} {$src2, $dst|$dst, $src2}",
1191 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>;
1193 let isTwoAddress = 0 in {
1194 def AND8mr : I<0x20, MRMDestMem,
1195 (ops i8mem :$dst, GR8 :$src),
1196 "and{b} {$src, $dst|$dst, $src}",
1197 [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>;
1198 def AND16mr : I<0x21, MRMDestMem,
1199 (ops i16mem:$dst, GR16:$src),
1200 "and{w} {$src, $dst|$dst, $src}",
1201 [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>,
1203 def AND32mr : I<0x21, MRMDestMem,
1204 (ops i32mem:$dst, GR32:$src),
1205 "and{l} {$src, $dst|$dst, $src}",
1206 [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>;
1207 def AND8mi : Ii8<0x80, MRM4m,
1208 (ops i8mem :$dst, i8imm :$src),
1209 "and{b} {$src, $dst|$dst, $src}",
1210 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1211 def AND16mi : Ii16<0x81, MRM4m,
1212 (ops i16mem:$dst, i16imm:$src),
1213 "and{w} {$src, $dst|$dst, $src}",
1214 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1216 def AND32mi : Ii32<0x81, MRM4m,
1217 (ops i32mem:$dst, i32imm:$src),
1218 "and{l} {$src, $dst|$dst, $src}",
1219 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1220 def AND16mi8 : Ii8<0x83, MRM4m,
1221 (ops i16mem:$dst, i16i8imm :$src),
1222 "and{w} {$src, $dst|$dst, $src}",
1223 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1225 def AND32mi8 : Ii8<0x83, MRM4m,
1226 (ops i32mem:$dst, i32i8imm :$src),
1227 "and{l} {$src, $dst|$dst, $src}",
1228 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1232 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1233 def OR8rr : I<0x08, MRMDestReg, (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1234 "or{b} {$src2, $dst|$dst, $src2}",
1235 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
1236 def OR16rr : I<0x09, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1237 "or{w} {$src2, $dst|$dst, $src2}",
1238 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize;
1239 def OR32rr : I<0x09, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1240 "or{l} {$src2, $dst|$dst, $src2}",
1241 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
1243 def OR8rm : I<0x0A, MRMSrcMem , (ops GR8 :$dst, GR8 :$src1, i8mem :$src2),
1244 "or{b} {$src2, $dst|$dst, $src2}",
1245 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
1246 def OR16rm : I<0x0B, MRMSrcMem , (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1247 "or{w} {$src2, $dst|$dst, $src2}",
1248 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize;
1249 def OR32rm : I<0x0B, MRMSrcMem , (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1250 "or{l} {$src2, $dst|$dst, $src2}",
1251 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>;
1253 def OR8ri : Ii8 <0x80, MRM1r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1254 "or{b} {$src2, $dst|$dst, $src2}",
1255 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
1256 def OR16ri : Ii16<0x81, MRM1r, (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1257 "or{w} {$src2, $dst|$dst, $src2}",
1258 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize;
1259 def OR32ri : Ii32<0x81, MRM1r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1260 "or{l} {$src2, $dst|$dst, $src2}",
1261 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
1263 def OR16ri8 : Ii8<0x83, MRM1r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1264 "or{w} {$src2, $dst|$dst, $src2}",
1265 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1266 def OR32ri8 : Ii8<0x83, MRM1r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1267 "or{l} {$src2, $dst|$dst, $src2}",
1268 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>;
1269 let isTwoAddress = 0 in {
1270 def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, GR8:$src),
1271 "or{b} {$src, $dst|$dst, $src}",
1272 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
1273 def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, GR16:$src),
1274 "or{w} {$src, $dst|$dst, $src}",
1275 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize;
1276 def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, GR32:$src),
1277 "or{l} {$src, $dst|$dst, $src}",
1278 [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>;
1279 def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src),
1280 "or{b} {$src, $dst|$dst, $src}",
1281 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1282 def OR16mi : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src),
1283 "or{w} {$src, $dst|$dst, $src}",
1284 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1286 def OR32mi : Ii32<0x81, MRM1m, (ops i32mem:$dst, i32imm:$src),
1287 "or{l} {$src, $dst|$dst, $src}",
1288 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1289 def OR16mi8 : Ii8<0x83, MRM1m, (ops i16mem:$dst, i16i8imm:$src),
1290 "or{w} {$src, $dst|$dst, $src}",
1291 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1293 def OR32mi8 : Ii8<0x83, MRM1m, (ops i32mem:$dst, i32i8imm:$src),
1294 "or{l} {$src, $dst|$dst, $src}",
1295 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1299 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1300 def XOR8rr : I<0x30, MRMDestReg,
1301 (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1302 "xor{b} {$src2, $dst|$dst, $src2}",
1303 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>;
1304 def XOR16rr : I<0x31, MRMDestReg,
1305 (ops GR16:$dst, GR16:$src1, GR16:$src2),
1306 "xor{w} {$src2, $dst|$dst, $src2}",
1307 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize;
1308 def XOR32rr : I<0x31, MRMDestReg,
1309 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1310 "xor{l} {$src2, $dst|$dst, $src2}",
1311 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
1314 def XOR8rm : I<0x32, MRMSrcMem ,
1315 (ops GR8 :$dst, GR8:$src1, i8mem :$src2),
1316 "xor{b} {$src2, $dst|$dst, $src2}",
1317 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>;
1318 def XOR16rm : I<0x33, MRMSrcMem ,
1319 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1320 "xor{w} {$src2, $dst|$dst, $src2}",
1321 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>, OpSize;
1322 def XOR32rm : I<0x33, MRMSrcMem ,
1323 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1324 "xor{l} {$src2, $dst|$dst, $src2}",
1325 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>;
1327 def XOR8ri : Ii8<0x80, MRM6r,
1328 (ops GR8:$dst, GR8:$src1, i8imm:$src2),
1329 "xor{b} {$src2, $dst|$dst, $src2}",
1330 [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>;
1331 def XOR16ri : Ii16<0x81, MRM6r,
1332 (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1333 "xor{w} {$src2, $dst|$dst, $src2}",
1334 [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize;
1335 def XOR32ri : Ii32<0x81, MRM6r,
1336 (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1337 "xor{l} {$src2, $dst|$dst, $src2}",
1338 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
1339 def XOR16ri8 : Ii8<0x83, MRM6r,
1340 (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1341 "xor{w} {$src2, $dst|$dst, $src2}",
1342 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>,
1344 def XOR32ri8 : Ii8<0x83, MRM6r,
1345 (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1346 "xor{l} {$src2, $dst|$dst, $src2}",
1347 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>;
1348 let isTwoAddress = 0 in {
1349 def XOR8mr : I<0x30, MRMDestMem,
1350 (ops i8mem :$dst, GR8 :$src),
1351 "xor{b} {$src, $dst|$dst, $src}",
1352 [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>;
1353 def XOR16mr : I<0x31, MRMDestMem,
1354 (ops i16mem:$dst, GR16:$src),
1355 "xor{w} {$src, $dst|$dst, $src}",
1356 [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>,
1358 def XOR32mr : I<0x31, MRMDestMem,
1359 (ops i32mem:$dst, GR32:$src),
1360 "xor{l} {$src, $dst|$dst, $src}",
1361 [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>;
1362 def XOR8mi : Ii8<0x80, MRM6m,
1363 (ops i8mem :$dst, i8imm :$src),
1364 "xor{b} {$src, $dst|$dst, $src}",
1365 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1366 def XOR16mi : Ii16<0x81, MRM6m,
1367 (ops i16mem:$dst, i16imm:$src),
1368 "xor{w} {$src, $dst|$dst, $src}",
1369 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1371 def XOR32mi : Ii32<0x81, MRM6m,
1372 (ops i32mem:$dst, i32imm:$src),
1373 "xor{l} {$src, $dst|$dst, $src}",
1374 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1375 def XOR16mi8 : Ii8<0x83, MRM6m,
1376 (ops i16mem:$dst, i16i8imm :$src),
1377 "xor{w} {$src, $dst|$dst, $src}",
1378 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1380 def XOR32mi8 : Ii8<0x83, MRM6m,
1381 (ops i32mem:$dst, i32i8imm :$src),
1382 "xor{l} {$src, $dst|$dst, $src}",
1383 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1386 // Shift instructions
1387 def SHL8rCL : I<0xD2, MRM4r, (ops GR8 :$dst, GR8 :$src),
1388 "shl{b} {%cl, $dst|$dst, %CL}",
1389 [(set GR8:$dst, (shl GR8:$src, CL))]>, Imp<[CL],[]>;
1390 def SHL16rCL : I<0xD3, MRM4r, (ops GR16:$dst, GR16:$src),
1391 "shl{w} {%cl, $dst|$dst, %CL}",
1392 [(set GR16:$dst, (shl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1393 def SHL32rCL : I<0xD3, MRM4r, (ops GR32:$dst, GR32:$src),
1394 "shl{l} {%cl, $dst|$dst, %CL}",
1395 [(set GR32:$dst, (shl GR32:$src, CL))]>, Imp<[CL],[]>;
1397 def SHL8ri : Ii8<0xC0, MRM4r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1398 "shl{b} {$src2, $dst|$dst, $src2}",
1399 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1400 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1401 def SHL16ri : Ii8<0xC1, MRM4r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1402 "shl{w} {$src2, $dst|$dst, $src2}",
1403 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1404 def SHL32ri : Ii8<0xC1, MRM4r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1405 "shl{l} {$src2, $dst|$dst, $src2}",
1406 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1409 // Shift left by one. Not used because (add x, x) is slightly cheaper.
1410 def SHL8r1 : I<0xD0, MRM4r, (ops GR8 :$dst, GR8 :$src1),
1412 def SHL16r1 : I<0xD1, MRM4r, (ops GR16:$dst, GR16:$src1),
1413 "shl{w} $dst", []>, OpSize;
1414 def SHL32r1 : I<0xD1, MRM4r, (ops GR32:$dst, GR32:$src1),
1417 let isTwoAddress = 0 in {
1418 def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst),
1419 "shl{b} {%cl, $dst|$dst, %CL}",
1420 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>,
1422 def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst),
1423 "shl{w} {%cl, $dst|$dst, %CL}",
1424 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>,
1425 Imp<[CL],[]>, OpSize;
1426 def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst),
1427 "shl{l} {%cl, $dst|$dst, %CL}",
1428 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>,
1430 def SHL8mi : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src),
1431 "shl{b} {$src, $dst|$dst, $src}",
1432 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1433 def SHL16mi : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src),
1434 "shl{w} {$src, $dst|$dst, $src}",
1435 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1437 def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src),
1438 "shl{l} {$src, $dst|$dst, $src}",
1439 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1442 def SHL8m1 : I<0xD0, MRM4m, (ops i8mem :$dst),
1444 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1445 def SHL16m1 : I<0xD1, MRM4m, (ops i16mem:$dst),
1447 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1449 def SHL32m1 : I<0xD1, MRM4m, (ops i32mem:$dst),
1451 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1454 def SHR8rCL : I<0xD2, MRM5r, (ops GR8 :$dst, GR8 :$src),
1455 "shr{b} {%cl, $dst|$dst, %CL}",
1456 [(set GR8:$dst, (srl GR8:$src, CL))]>, Imp<[CL],[]>;
1457 def SHR16rCL : I<0xD3, MRM5r, (ops GR16:$dst, GR16:$src),
1458 "shr{w} {%cl, $dst|$dst, %CL}",
1459 [(set GR16:$dst, (srl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1460 def SHR32rCL : I<0xD3, MRM5r, (ops GR32:$dst, GR32:$src),
1461 "shr{l} {%cl, $dst|$dst, %CL}",
1462 [(set GR32:$dst, (srl GR32:$src, CL))]>, Imp<[CL],[]>;
1464 def SHR8ri : Ii8<0xC0, MRM5r, (ops GR8:$dst, GR8:$src1, i8imm:$src2),
1465 "shr{b} {$src2, $dst|$dst, $src2}",
1466 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1467 def SHR16ri : Ii8<0xC1, MRM5r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1468 "shr{w} {$src2, $dst|$dst, $src2}",
1469 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1470 def SHR32ri : Ii8<0xC1, MRM5r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1471 "shr{l} {$src2, $dst|$dst, $src2}",
1472 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1475 def SHR8r1 : I<0xD0, MRM5r, (ops GR8:$dst, GR8:$src1),
1477 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1478 def SHR16r1 : I<0xD1, MRM5r, (ops GR16:$dst, GR16:$src1),
1480 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1481 def SHR32r1 : I<0xD1, MRM5r, (ops GR32:$dst, GR32:$src1),
1483 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1485 let isTwoAddress = 0 in {
1486 def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst),
1487 "shr{b} {%cl, $dst|$dst, %CL}",
1488 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>,
1490 def SHR16mCL : I<0xD3, MRM5m, (ops i16mem:$dst),
1491 "shr{w} {%cl, $dst|$dst, %CL}",
1492 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1493 Imp<[CL],[]>, OpSize;
1494 def SHR32mCL : I<0xD3, MRM5m, (ops i32mem:$dst),
1495 "shr{l} {%cl, $dst|$dst, %CL}",
1496 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>,
1498 def SHR8mi : Ii8<0xC0, MRM5m, (ops i8mem :$dst, i8imm:$src),
1499 "shr{b} {$src, $dst|$dst, $src}",
1500 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1501 def SHR16mi : Ii8<0xC1, MRM5m, (ops i16mem:$dst, i8imm:$src),
1502 "shr{w} {$src, $dst|$dst, $src}",
1503 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1505 def SHR32mi : Ii8<0xC1, MRM5m, (ops i32mem:$dst, i8imm:$src),
1506 "shr{l} {$src, $dst|$dst, $src}",
1507 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1510 def SHR8m1 : I<0xD0, MRM5m, (ops i8mem :$dst),
1512 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1513 def SHR16m1 : I<0xD1, MRM5m, (ops i16mem:$dst),
1515 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1516 def SHR32m1 : I<0xD1, MRM5m, (ops i32mem:$dst),
1518 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1521 def SAR8rCL : I<0xD2, MRM7r, (ops GR8 :$dst, GR8 :$src),
1522 "sar{b} {%cl, $dst|$dst, %CL}",
1523 [(set GR8:$dst, (sra GR8:$src, CL))]>, Imp<[CL],[]>;
1524 def SAR16rCL : I<0xD3, MRM7r, (ops GR16:$dst, GR16:$src),
1525 "sar{w} {%cl, $dst|$dst, %CL}",
1526 [(set GR16:$dst, (sra GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1527 def SAR32rCL : I<0xD3, MRM7r, (ops GR32:$dst, GR32:$src),
1528 "sar{l} {%cl, $dst|$dst, %CL}",
1529 [(set GR32:$dst, (sra GR32:$src, CL))]>, Imp<[CL],[]>;
1531 def SAR8ri : Ii8<0xC0, MRM7r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1532 "sar{b} {$src2, $dst|$dst, $src2}",
1533 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1534 def SAR16ri : Ii8<0xC1, MRM7r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1535 "sar{w} {$src2, $dst|$dst, $src2}",
1536 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1538 def SAR32ri : Ii8<0xC1, MRM7r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1539 "sar{l} {$src2, $dst|$dst, $src2}",
1540 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1543 def SAR8r1 : I<0xD0, MRM7r, (ops GR8 :$dst, GR8 :$src1),
1545 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1546 def SAR16r1 : I<0xD1, MRM7r, (ops GR16:$dst, GR16:$src1),
1548 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1549 def SAR32r1 : I<0xD1, MRM7r, (ops GR32:$dst, GR32:$src1),
1551 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1553 let isTwoAddress = 0 in {
1554 def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst),
1555 "sar{b} {%cl, $dst|$dst, %CL}",
1556 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>,
1558 def SAR16mCL : I<0xD3, MRM7m, (ops i16mem:$dst),
1559 "sar{w} {%cl, $dst|$dst, %CL}",
1560 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>,
1561 Imp<[CL],[]>, OpSize;
1562 def SAR32mCL : I<0xD3, MRM7m, (ops i32mem:$dst),
1563 "sar{l} {%cl, $dst|$dst, %CL}",
1564 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>,
1566 def SAR8mi : Ii8<0xC0, MRM7m, (ops i8mem :$dst, i8imm:$src),
1567 "sar{b} {$src, $dst|$dst, $src}",
1568 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1569 def SAR16mi : Ii8<0xC1, MRM7m, (ops i16mem:$dst, i8imm:$src),
1570 "sar{w} {$src, $dst|$dst, $src}",
1571 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1573 def SAR32mi : Ii8<0xC1, MRM7m, (ops i32mem:$dst, i8imm:$src),
1574 "sar{l} {$src, $dst|$dst, $src}",
1575 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1578 def SAR8m1 : I<0xD0, MRM7m, (ops i8mem :$dst),
1580 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1581 def SAR16m1 : I<0xD1, MRM7m, (ops i16mem:$dst),
1583 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1585 def SAR32m1 : I<0xD1, MRM7m, (ops i32mem:$dst),
1587 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1590 // Rotate instructions
1591 // FIXME: provide shorter instructions when imm8 == 1
1592 def ROL8rCL : I<0xD2, MRM0r, (ops GR8 :$dst, GR8 :$src),
1593 "rol{b} {%cl, $dst|$dst, %CL}",
1594 [(set GR8:$dst, (rotl GR8:$src, CL))]>, Imp<[CL],[]>;
1595 def ROL16rCL : I<0xD3, MRM0r, (ops GR16:$dst, GR16:$src),
1596 "rol{w} {%cl, $dst|$dst, %CL}",
1597 [(set GR16:$dst, (rotl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1598 def ROL32rCL : I<0xD3, MRM0r, (ops GR32:$dst, GR32:$src),
1599 "rol{l} {%cl, $dst|$dst, %CL}",
1600 [(set GR32:$dst, (rotl GR32:$src, CL))]>, Imp<[CL],[]>;
1602 def ROL8ri : Ii8<0xC0, MRM0r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1603 "rol{b} {$src2, $dst|$dst, $src2}",
1604 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1605 def ROL16ri : Ii8<0xC1, MRM0r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1606 "rol{w} {$src2, $dst|$dst, $src2}",
1607 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1608 def ROL32ri : Ii8<0xC1, MRM0r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1609 "rol{l} {$src2, $dst|$dst, $src2}",
1610 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1613 def ROL8r1 : I<0xD0, MRM0r, (ops GR8 :$dst, GR8 :$src1),
1615 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1616 def ROL16r1 : I<0xD1, MRM0r, (ops GR16:$dst, GR16:$src1),
1618 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1619 def ROL32r1 : I<0xD1, MRM0r, (ops GR32:$dst, GR32:$src1),
1621 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1623 let isTwoAddress = 0 in {
1624 def ROL8mCL : I<0xD2, MRM0m, (ops i8mem :$dst),
1625 "rol{b} {%cl, $dst|$dst, %CL}",
1626 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>,
1628 def ROL16mCL : I<0xD3, MRM0m, (ops i16mem:$dst),
1629 "rol{w} {%cl, $dst|$dst, %CL}",
1630 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>,
1631 Imp<[CL],[]>, OpSize;
1632 def ROL32mCL : I<0xD3, MRM0m, (ops i32mem:$dst),
1633 "rol{l} {%cl, $dst|$dst, %CL}",
1634 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>,
1636 def ROL8mi : Ii8<0xC0, MRM0m, (ops i8mem :$dst, i8imm:$src),
1637 "rol{b} {$src, $dst|$dst, $src}",
1638 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1639 def ROL16mi : Ii8<0xC1, MRM0m, (ops i16mem:$dst, i8imm:$src),
1640 "rol{w} {$src, $dst|$dst, $src}",
1641 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1643 def ROL32mi : Ii8<0xC1, MRM0m, (ops i32mem:$dst, i8imm:$src),
1644 "rol{l} {$src, $dst|$dst, $src}",
1645 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1648 def ROL8m1 : I<0xD0, MRM0m, (ops i8mem :$dst),
1650 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1651 def ROL16m1 : I<0xD1, MRM0m, (ops i16mem:$dst),
1653 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1655 def ROL32m1 : I<0xD1, MRM0m, (ops i32mem:$dst),
1657 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1660 def ROR8rCL : I<0xD2, MRM1r, (ops GR8 :$dst, GR8 :$src),
1661 "ror{b} {%cl, $dst|$dst, %CL}",
1662 [(set GR8:$dst, (rotr GR8:$src, CL))]>, Imp<[CL],[]>;
1663 def ROR16rCL : I<0xD3, MRM1r, (ops GR16:$dst, GR16:$src),
1664 "ror{w} {%cl, $dst|$dst, %CL}",
1665 [(set GR16:$dst, (rotr GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1666 def ROR32rCL : I<0xD3, MRM1r, (ops GR32:$dst, GR32:$src),
1667 "ror{l} {%cl, $dst|$dst, %CL}",
1668 [(set GR32:$dst, (rotr GR32:$src, CL))]>, Imp<[CL],[]>;
1670 def ROR8ri : Ii8<0xC0, MRM1r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1671 "ror{b} {$src2, $dst|$dst, $src2}",
1672 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
1673 def ROR16ri : Ii8<0xC1, MRM1r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1674 "ror{w} {$src2, $dst|$dst, $src2}",
1675 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1676 def ROR32ri : Ii8<0xC1, MRM1r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1677 "ror{l} {$src2, $dst|$dst, $src2}",
1678 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
1681 def ROR8r1 : I<0xD0, MRM1r, (ops GR8 :$dst, GR8 :$src1),
1683 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
1684 def ROR16r1 : I<0xD1, MRM1r, (ops GR16:$dst, GR16:$src1),
1686 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
1687 def ROR32r1 : I<0xD1, MRM1r, (ops GR32:$dst, GR32:$src1),
1689 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
1691 let isTwoAddress = 0 in {
1692 def ROR8mCL : I<0xD2, MRM1m, (ops i8mem :$dst),
1693 "ror{b} {%cl, $dst|$dst, %CL}",
1694 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>,
1696 def ROR16mCL : I<0xD3, MRM1m, (ops i16mem:$dst),
1697 "ror{w} {%cl, $dst|$dst, %CL}",
1698 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>,
1699 Imp<[CL],[]>, OpSize;
1700 def ROR32mCL : I<0xD3, MRM1m, (ops i32mem:$dst),
1701 "ror{l} {%cl, $dst|$dst, %CL}",
1702 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>,
1704 def ROR8mi : Ii8<0xC0, MRM1m, (ops i8mem :$dst, i8imm:$src),
1705 "ror{b} {$src, $dst|$dst, $src}",
1706 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1707 def ROR16mi : Ii8<0xC1, MRM1m, (ops i16mem:$dst, i8imm:$src),
1708 "ror{w} {$src, $dst|$dst, $src}",
1709 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1711 def ROR32mi : Ii8<0xC1, MRM1m, (ops i32mem:$dst, i8imm:$src),
1712 "ror{l} {$src, $dst|$dst, $src}",
1713 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1716 def ROR8m1 : I<0xD0, MRM1m, (ops i8mem :$dst),
1718 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1719 def ROR16m1 : I<0xD1, MRM1m, (ops i16mem:$dst),
1721 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1723 def ROR32m1 : I<0xD1, MRM1m, (ops i32mem:$dst),
1725 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1730 // Double shift instructions (generalizations of rotate)
1731 def SHLD32rrCL : I<0xA5, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1732 "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1733 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>,
1735 def SHRD32rrCL : I<0xAD, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1736 "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1737 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>,
1739 def SHLD16rrCL : I<0xA5, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1740 "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1741 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
1742 Imp<[CL],[]>, TB, OpSize;
1743 def SHRD16rrCL : I<0xAD, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1744 "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1745 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
1746 Imp<[CL],[]>, TB, OpSize;
1748 let isCommutable = 1 in { // These instructions commute to each other.
1749 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
1750 (ops GR32:$dst, GR32:$src1, GR32:$src2, i8imm:$src3),
1751 "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1752 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
1755 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
1756 (ops GR32:$dst, GR32:$src1, GR32:$src2, i8imm:$src3),
1757 "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1758 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
1761 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
1762 (ops GR16:$dst, GR16:$src1, GR16:$src2, i8imm:$src3),
1763 "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1764 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
1767 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
1768 (ops GR16:$dst, GR16:$src1, GR16:$src2, i8imm:$src3),
1769 "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1770 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
1775 let isTwoAddress = 0 in {
1776 def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1777 "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1778 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
1781 def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1782 "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1783 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
1786 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
1787 (ops i32mem:$dst, GR32:$src2, i8imm:$src3),
1788 "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1789 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
1790 (i8 imm:$src3)), addr:$dst)]>,
1792 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
1793 (ops i32mem:$dst, GR32:$src2, i8imm:$src3),
1794 "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1795 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
1796 (i8 imm:$src3)), addr:$dst)]>,
1799 def SHLD16mrCL : I<0xA5, MRMDestMem, (ops i16mem:$dst, GR16:$src2),
1800 "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1801 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
1803 Imp<[CL],[]>, TB, OpSize;
1804 def SHRD16mrCL : I<0xAD, MRMDestMem, (ops i16mem:$dst, GR16:$src2),
1805 "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1806 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
1808 Imp<[CL],[]>, TB, OpSize;
1809 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
1810 (ops i16mem:$dst, GR16:$src2, i8imm:$src3),
1811 "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1812 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
1813 (i8 imm:$src3)), addr:$dst)]>,
1815 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
1816 (ops i16mem:$dst, GR16:$src2, i8imm:$src3),
1817 "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1818 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
1819 (i8 imm:$src3)), addr:$dst)]>,
1825 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1826 def ADD8rr : I<0x00, MRMDestReg, (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1827 "add{b} {$src2, $dst|$dst, $src2}",
1828 [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>;
1829 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1830 def ADD16rr : I<0x01, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1831 "add{w} {$src2, $dst|$dst, $src2}",
1832 [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize;
1833 def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1834 "add{l} {$src2, $dst|$dst, $src2}",
1835 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
1836 } // end isConvertibleToThreeAddress
1837 } // end isCommutable
1838 def ADD8rm : I<0x02, MRMSrcMem, (ops GR8 :$dst, GR8 :$src1, i8mem :$src2),
1839 "add{b} {$src2, $dst|$dst, $src2}",
1840 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>;
1841 def ADD16rm : I<0x03, MRMSrcMem, (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1842 "add{w} {$src2, $dst|$dst, $src2}",
1843 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>, OpSize;
1844 def ADD32rm : I<0x03, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1845 "add{l} {$src2, $dst|$dst, $src2}",
1846 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>;
1848 def ADD8ri : Ii8<0x80, MRM0r, (ops GR8:$dst, GR8:$src1, i8imm:$src2),
1849 "add{b} {$src2, $dst|$dst, $src2}",
1850 [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>;
1852 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1853 def ADD16ri : Ii16<0x81, MRM0r, (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1854 "add{w} {$src2, $dst|$dst, $src2}",
1855 [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize;
1856 def ADD32ri : Ii32<0x81, MRM0r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1857 "add{l} {$src2, $dst|$dst, $src2}",
1858 [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>;
1859 def ADD16ri8 : Ii8<0x83, MRM0r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1860 "add{w} {$src2, $dst|$dst, $src2}",
1861 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>,
1863 def ADD32ri8 : Ii8<0x83, MRM0r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1864 "add{l} {$src2, $dst|$dst, $src2}",
1865 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>;
1868 let isTwoAddress = 0 in {
1869 def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, GR8 :$src2),
1870 "add{b} {$src2, $dst|$dst, $src2}",
1871 [(store (add (load addr:$dst), GR8:$src2), addr:$dst)]>;
1872 def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, GR16:$src2),
1873 "add{w} {$src2, $dst|$dst, $src2}",
1874 [(store (add (load addr:$dst), GR16:$src2), addr:$dst)]>,
1876 def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1877 "add{l} {$src2, $dst|$dst, $src2}",
1878 [(store (add (load addr:$dst), GR32:$src2), addr:$dst)]>;
1879 def ADD8mi : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2),
1880 "add{b} {$src2, $dst|$dst, $src2}",
1881 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1882 def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2),
1883 "add{w} {$src2, $dst|$dst, $src2}",
1884 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1886 def ADD32mi : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2),
1887 "add{l} {$src2, $dst|$dst, $src2}",
1888 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1889 def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i16i8imm :$src2),
1890 "add{w} {$src2, $dst|$dst, $src2}",
1891 [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1893 def ADD32mi8 : Ii8<0x83, MRM0m, (ops i32mem:$dst, i32i8imm :$src2),
1894 "add{l} {$src2, $dst|$dst, $src2}",
1895 [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1898 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1899 def ADC32rr : I<0x11, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1900 "adc{l} {$src2, $dst|$dst, $src2}",
1901 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
1903 def ADC32rm : I<0x13, MRMSrcMem , (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1904 "adc{l} {$src2, $dst|$dst, $src2}",
1905 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
1906 def ADC32ri : Ii32<0x81, MRM2r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1907 "adc{l} {$src2, $dst|$dst, $src2}",
1908 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
1909 def ADC32ri8 : Ii8<0x83, MRM2r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1910 "adc{l} {$src2, $dst|$dst, $src2}",
1911 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
1913 let isTwoAddress = 0 in {
1914 def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1915 "adc{l} {$src2, $dst|$dst, $src2}",
1916 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
1917 def ADC32mi : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2),
1918 "adc{l} {$src2, $dst|$dst, $src2}",
1919 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1920 def ADC32mi8 : Ii8<0x83, MRM2m, (ops i32mem:$dst, i32i8imm :$src2),
1921 "adc{l} {$src2, $dst|$dst, $src2}",
1922 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1925 def SUB8rr : I<0x28, MRMDestReg, (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1926 "sub{b} {$src2, $dst|$dst, $src2}",
1927 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2))]>;
1928 def SUB16rr : I<0x29, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1929 "sub{w} {$src2, $dst|$dst, $src2}",
1930 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2))]>, OpSize;
1931 def SUB32rr : I<0x29, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1932 "sub{l} {$src2, $dst|$dst, $src2}",
1933 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
1934 def SUB8rm : I<0x2A, MRMSrcMem, (ops GR8 :$dst, GR8 :$src1, i8mem :$src2),
1935 "sub{b} {$src2, $dst|$dst, $src2}",
1936 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2)))]>;
1937 def SUB16rm : I<0x2B, MRMSrcMem, (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1938 "sub{w} {$src2, $dst|$dst, $src2}",
1939 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2)))]>, OpSize;
1940 def SUB32rm : I<0x2B, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1941 "sub{l} {$src2, $dst|$dst, $src2}",
1942 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2)))]>;
1944 def SUB8ri : Ii8 <0x80, MRM5r, (ops GR8:$dst, GR8:$src1, i8imm:$src2),
1945 "sub{b} {$src2, $dst|$dst, $src2}",
1946 [(set GR8:$dst, (sub GR8:$src1, imm:$src2))]>;
1947 def SUB16ri : Ii16<0x81, MRM5r, (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1948 "sub{w} {$src2, $dst|$dst, $src2}",
1949 [(set GR16:$dst, (sub GR16:$src1, imm:$src2))]>, OpSize;
1950 def SUB32ri : Ii32<0x81, MRM5r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1951 "sub{l} {$src2, $dst|$dst, $src2}",
1952 [(set GR32:$dst, (sub GR32:$src1, imm:$src2))]>;
1953 def SUB16ri8 : Ii8<0x83, MRM5r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1954 "sub{w} {$src2, $dst|$dst, $src2}",
1955 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2))]>,
1957 def SUB32ri8 : Ii8<0x83, MRM5r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1958 "sub{l} {$src2, $dst|$dst, $src2}",
1959 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2))]>;
1960 let isTwoAddress = 0 in {
1961 def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, GR8 :$src2),
1962 "sub{b} {$src2, $dst|$dst, $src2}",
1963 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst)]>;
1964 def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, GR16:$src2),
1965 "sub{w} {$src2, $dst|$dst, $src2}",
1966 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst)]>,
1968 def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1969 "sub{l} {$src2, $dst|$dst, $src2}",
1970 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst)]>;
1971 def SUB8mi : Ii8<0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2),
1972 "sub{b} {$src2, $dst|$dst, $src2}",
1973 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1974 def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2),
1975 "sub{w} {$src2, $dst|$dst, $src2}",
1976 [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1978 def SUB32mi : Ii32<0x81, MRM5m, (ops i32mem:$dst, i32imm:$src2),
1979 "sub{l} {$src2, $dst|$dst, $src2}",
1980 [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1981 def SUB16mi8 : Ii8<0x83, MRM5m, (ops i16mem:$dst, i16i8imm :$src2),
1982 "sub{w} {$src2, $dst|$dst, $src2}",
1983 [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1985 def SUB32mi8 : Ii8<0x83, MRM5m, (ops i32mem:$dst, i32i8imm :$src2),
1986 "sub{l} {$src2, $dst|$dst, $src2}",
1987 [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1990 def SBB32rr : I<0x19, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1991 "sbb{l} {$src2, $dst|$dst, $src2}",
1992 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
1994 let isTwoAddress = 0 in {
1995 def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1996 "sbb{l} {$src2, $dst|$dst, $src2}",
1997 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
1998 def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2),
1999 "sbb{b} {$src2, $dst|$dst, $src2}",
2000 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2001 def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2),
2002 "sbb{l} {$src2, $dst|$dst, $src2}",
2003 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2004 def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i32i8imm :$src2),
2005 "sbb{l} {$src2, $dst|$dst, $src2}",
2006 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2008 def SBB32rm : I<0x1B, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2),
2009 "sbb{l} {$src2, $dst|$dst, $src2}",
2010 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2011 def SBB32ri : Ii32<0x81, MRM3r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
2012 "sbb{l} {$src2, $dst|$dst, $src2}",
2013 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2014 def SBB32ri8 : Ii8<0x83, MRM3r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
2015 "sbb{l} {$src2, $dst|$dst, $src2}",
2016 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2018 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2019 def IMUL16rr : I<0xAF, MRMSrcReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
2020 "imul{w} {$src2, $dst|$dst, $src2}",
2021 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2))]>, TB, OpSize;
2022 def IMUL32rr : I<0xAF, MRMSrcReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
2023 "imul{l} {$src2, $dst|$dst, $src2}",
2024 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>, TB;
2026 def IMUL16rm : I<0xAF, MRMSrcMem, (ops GR16:$dst, GR16:$src1, i16mem:$src2),
2027 "imul{w} {$src2, $dst|$dst, $src2}",
2028 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2)))]>,
2030 def IMUL32rm : I<0xAF, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2),
2031 "imul{l} {$src2, $dst|$dst, $src2}",
2032 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2)))]>, TB;
2034 } // end Two Address instructions
2036 // Suprisingly enough, these are not two address instructions!
2037 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2038 (ops GR16:$dst, GR16:$src1, i16imm:$src2),
2039 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
2040 [(set GR16:$dst, (mul GR16:$src1, imm:$src2))]>, OpSize;
2041 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2042 (ops GR32:$dst, GR32:$src1, i32imm:$src2),
2043 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
2044 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
2045 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2046 (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
2047 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
2048 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2))]>,
2050 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2051 (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
2052 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
2053 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2))]>;
2055 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2056 (ops GR16:$dst, i16mem:$src1, i16imm:$src2),
2057 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
2058 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2))]>,
2060 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2061 (ops GR32:$dst, i32mem:$src1, i32imm:$src2),
2062 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
2063 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2))]>;
2064 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2065 (ops GR16:$dst, i16mem:$src1, i16i8imm :$src2),
2066 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
2067 [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>,
2069 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2070 (ops GR32:$dst, i32mem:$src1, i32i8imm: $src2),
2071 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
2072 [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>;
2074 //===----------------------------------------------------------------------===//
2075 // Test instructions are just like AND, except they don't generate a result.
2077 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2078 def TEST8rr : I<0x84, MRMDestReg, (ops GR8:$src1, GR8:$src2),
2079 "test{b} {$src2, $src1|$src1, $src2}",
2080 [(X86cmp (and GR8:$src1, GR8:$src2), 0)]>;
2081 def TEST16rr : I<0x85, MRMDestReg, (ops GR16:$src1, GR16:$src2),
2082 "test{w} {$src2, $src1|$src1, $src2}",
2083 [(X86cmp (and GR16:$src1, GR16:$src2), 0)]>, OpSize;
2084 def TEST32rr : I<0x85, MRMDestReg, (ops GR32:$src1, GR32:$src2),
2085 "test{l} {$src2, $src1|$src1, $src2}",
2086 [(X86cmp (and GR32:$src1, GR32:$src2), 0)]>;
2089 def TEST8rm : I<0x84, MRMSrcMem, (ops GR8 :$src1, i8mem :$src2),
2090 "test{b} {$src2, $src1|$src1, $src2}",
2091 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0)]>;
2092 def TEST16rm : I<0x85, MRMSrcMem, (ops GR16:$src1, i16mem:$src2),
2093 "test{w} {$src2, $src1|$src1, $src2}",
2094 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0)]>,
2096 def TEST32rm : I<0x85, MRMSrcMem, (ops GR32:$src1, i32mem:$src2),
2097 "test{l} {$src2, $src1|$src1, $src2}",
2098 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0)]>;
2100 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2101 (ops GR8:$src1, i8imm:$src2),
2102 "test{b} {$src2, $src1|$src1, $src2}",
2103 [(X86cmp (and GR8:$src1, imm:$src2), 0)]>;
2104 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2105 (ops GR16:$src1, i16imm:$src2),
2106 "test{w} {$src2, $src1|$src1, $src2}",
2107 [(X86cmp (and GR16:$src1, imm:$src2), 0)]>, OpSize;
2108 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2109 (ops GR32:$src1, i32imm:$src2),
2110 "test{l} {$src2, $src1|$src1, $src2}",
2111 [(X86cmp (and GR32:$src1, imm:$src2), 0)]>;
2113 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2114 (ops i8mem:$src1, i8imm:$src2),
2115 "test{b} {$src2, $src1|$src1, $src2}",
2116 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0)]>;
2117 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2118 (ops i16mem:$src1, i16imm:$src2),
2119 "test{w} {$src2, $src1|$src1, $src2}",
2120 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0)]>,
2122 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2123 (ops i32mem:$src1, i32imm:$src2),
2124 "test{l} {$src2, $src1|$src1, $src2}",
2125 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0)]>;
2128 // Condition code ops, incl. set if equal/not equal/...
2129 def SAHF : I<0x9E, RawFrm, (ops), "sahf", []>, Imp<[AH],[]>; // flags = AH
2130 def LAHF : I<0x9F, RawFrm, (ops), "lahf", []>, Imp<[],[AH]>; // AH = flags
2132 def SETEr : I<0x94, MRM0r,
2135 [(set GR8:$dst, (X86setcc X86_COND_E))]>,
2137 def SETEm : I<0x94, MRM0m,
2140 [(store (X86setcc X86_COND_E), addr:$dst)]>,
2142 def SETNEr : I<0x95, MRM0r,
2145 [(set GR8:$dst, (X86setcc X86_COND_NE))]>,
2147 def SETNEm : I<0x95, MRM0m,
2150 [(store (X86setcc X86_COND_NE), addr:$dst)]>,
2152 def SETLr : I<0x9C, MRM0r,
2155 [(set GR8:$dst, (X86setcc X86_COND_L))]>,
2156 TB; // GR8 = < signed
2157 def SETLm : I<0x9C, MRM0m,
2160 [(store (X86setcc X86_COND_L), addr:$dst)]>,
2161 TB; // [mem8] = < signed
2162 def SETGEr : I<0x9D, MRM0r,
2165 [(set GR8:$dst, (X86setcc X86_COND_GE))]>,
2166 TB; // GR8 = >= signed
2167 def SETGEm : I<0x9D, MRM0m,
2170 [(store (X86setcc X86_COND_GE), addr:$dst)]>,
2171 TB; // [mem8] = >= signed
2172 def SETLEr : I<0x9E, MRM0r,
2175 [(set GR8:$dst, (X86setcc X86_COND_LE))]>,
2176 TB; // GR8 = <= signed
2177 def SETLEm : I<0x9E, MRM0m,
2180 [(store (X86setcc X86_COND_LE), addr:$dst)]>,
2181 TB; // [mem8] = <= signed
2182 def SETGr : I<0x9F, MRM0r,
2185 [(set GR8:$dst, (X86setcc X86_COND_G))]>,
2186 TB; // GR8 = > signed
2187 def SETGm : I<0x9F, MRM0m,
2190 [(store (X86setcc X86_COND_G), addr:$dst)]>,
2191 TB; // [mem8] = > signed
2193 def SETBr : I<0x92, MRM0r,
2196 [(set GR8:$dst, (X86setcc X86_COND_B))]>,
2197 TB; // GR8 = < unsign
2198 def SETBm : I<0x92, MRM0m,
2201 [(store (X86setcc X86_COND_B), addr:$dst)]>,
2202 TB; // [mem8] = < unsign
2203 def SETAEr : I<0x93, MRM0r,
2206 [(set GR8:$dst, (X86setcc X86_COND_AE))]>,
2207 TB; // GR8 = >= unsign
2208 def SETAEm : I<0x93, MRM0m,
2211 [(store (X86setcc X86_COND_AE), addr:$dst)]>,
2212 TB; // [mem8] = >= unsign
2213 def SETBEr : I<0x96, MRM0r,
2216 [(set GR8:$dst, (X86setcc X86_COND_BE))]>,
2217 TB; // GR8 = <= unsign
2218 def SETBEm : I<0x96, MRM0m,
2221 [(store (X86setcc X86_COND_BE), addr:$dst)]>,
2222 TB; // [mem8] = <= unsign
2223 def SETAr : I<0x97, MRM0r,
2226 [(set GR8:$dst, (X86setcc X86_COND_A))]>,
2227 TB; // GR8 = > signed
2228 def SETAm : I<0x97, MRM0m,
2231 [(store (X86setcc X86_COND_A), addr:$dst)]>,
2232 TB; // [mem8] = > signed
2234 def SETSr : I<0x98, MRM0r,
2237 [(set GR8:$dst, (X86setcc X86_COND_S))]>,
2238 TB; // GR8 = <sign bit>
2239 def SETSm : I<0x98, MRM0m,
2242 [(store (X86setcc X86_COND_S), addr:$dst)]>,
2243 TB; // [mem8] = <sign bit>
2244 def SETNSr : I<0x99, MRM0r,
2247 [(set GR8:$dst, (X86setcc X86_COND_NS))]>,
2248 TB; // GR8 = !<sign bit>
2249 def SETNSm : I<0x99, MRM0m,
2252 [(store (X86setcc X86_COND_NS), addr:$dst)]>,
2253 TB; // [mem8] = !<sign bit>
2254 def SETPr : I<0x9A, MRM0r,
2257 [(set GR8:$dst, (X86setcc X86_COND_P))]>,
2259 def SETPm : I<0x9A, MRM0m,
2262 [(store (X86setcc X86_COND_P), addr:$dst)]>,
2263 TB; // [mem8] = parity
2264 def SETNPr : I<0x9B, MRM0r,
2267 [(set GR8:$dst, (X86setcc X86_COND_NP))]>,
2268 TB; // GR8 = not parity
2269 def SETNPm : I<0x9B, MRM0m,
2272 [(store (X86setcc X86_COND_NP), addr:$dst)]>,
2273 TB; // [mem8] = not parity
2275 // Integer comparisons
2276 def CMP8rr : I<0x38, MRMDestReg,
2277 (ops GR8 :$src1, GR8 :$src2),
2278 "cmp{b} {$src2, $src1|$src1, $src2}",
2279 [(X86cmp GR8:$src1, GR8:$src2)]>;
2280 def CMP16rr : I<0x39, MRMDestReg,
2281 (ops GR16:$src1, GR16:$src2),
2282 "cmp{w} {$src2, $src1|$src1, $src2}",
2283 [(X86cmp GR16:$src1, GR16:$src2)]>, OpSize;
2284 def CMP32rr : I<0x39, MRMDestReg,
2285 (ops GR32:$src1, GR32:$src2),
2286 "cmp{l} {$src2, $src1|$src1, $src2}",
2287 [(X86cmp GR32:$src1, GR32:$src2)]>;
2288 def CMP8mr : I<0x38, MRMDestMem,
2289 (ops i8mem :$src1, GR8 :$src2),
2290 "cmp{b} {$src2, $src1|$src1, $src2}",
2291 [(X86cmp (loadi8 addr:$src1), GR8:$src2)]>;
2292 def CMP16mr : I<0x39, MRMDestMem,
2293 (ops i16mem:$src1, GR16:$src2),
2294 "cmp{w} {$src2, $src1|$src1, $src2}",
2295 [(X86cmp (loadi16 addr:$src1), GR16:$src2)]>, OpSize;
2296 def CMP32mr : I<0x39, MRMDestMem,
2297 (ops i32mem:$src1, GR32:$src2),
2298 "cmp{l} {$src2, $src1|$src1, $src2}",
2299 [(X86cmp (loadi32 addr:$src1), GR32:$src2)]>;
2300 def CMP8rm : I<0x3A, MRMSrcMem,
2301 (ops GR8 :$src1, i8mem :$src2),
2302 "cmp{b} {$src2, $src1|$src1, $src2}",
2303 [(X86cmp GR8:$src1, (loadi8 addr:$src2))]>;
2304 def CMP16rm : I<0x3B, MRMSrcMem,
2305 (ops GR16:$src1, i16mem:$src2),
2306 "cmp{w} {$src2, $src1|$src1, $src2}",
2307 [(X86cmp GR16:$src1, (loadi16 addr:$src2))]>, OpSize;
2308 def CMP32rm : I<0x3B, MRMSrcMem,
2309 (ops GR32:$src1, i32mem:$src2),
2310 "cmp{l} {$src2, $src1|$src1, $src2}",
2311 [(X86cmp GR32:$src1, (loadi32 addr:$src2))]>;
2312 def CMP8ri : Ii8<0x80, MRM7r,
2313 (ops GR8:$src1, i8imm:$src2),
2314 "cmp{b} {$src2, $src1|$src1, $src2}",
2315 [(X86cmp GR8:$src1, imm:$src2)]>;
2316 def CMP16ri : Ii16<0x81, MRM7r,
2317 (ops GR16:$src1, i16imm:$src2),
2318 "cmp{w} {$src2, $src1|$src1, $src2}",
2319 [(X86cmp GR16:$src1, imm:$src2)]>, OpSize;
2320 def CMP32ri : Ii32<0x81, MRM7r,
2321 (ops GR32:$src1, i32imm:$src2),
2322 "cmp{l} {$src2, $src1|$src1, $src2}",
2323 [(X86cmp GR32:$src1, imm:$src2)]>;
2324 def CMP8mi : Ii8 <0x80, MRM7m,
2325 (ops i8mem :$src1, i8imm :$src2),
2326 "cmp{b} {$src2, $src1|$src1, $src2}",
2327 [(X86cmp (loadi8 addr:$src1), imm:$src2)]>;
2328 def CMP16mi : Ii16<0x81, MRM7m,
2329 (ops i16mem:$src1, i16imm:$src2),
2330 "cmp{w} {$src2, $src1|$src1, $src2}",
2331 [(X86cmp (loadi16 addr:$src1), imm:$src2)]>, OpSize;
2332 def CMP32mi : Ii32<0x81, MRM7m,
2333 (ops i32mem:$src1, i32imm:$src2),
2334 "cmp{l} {$src2, $src1|$src1, $src2}",
2335 [(X86cmp (loadi32 addr:$src1), imm:$src2)]>;
2336 def CMP16ri8 : Ii8<0x83, MRM7r,
2337 (ops GR16:$src1, i16i8imm:$src2),
2338 "cmp{w} {$src2, $src1|$src1, $src2}",
2339 [(X86cmp GR16:$src1, i16immSExt8:$src2)]>, OpSize;
2340 def CMP16mi8 : Ii8<0x83, MRM7m,
2341 (ops i16mem:$src1, i16i8imm:$src2),
2342 "cmp{w} {$src2, $src1|$src1, $src2}",
2343 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2)]>, OpSize;
2344 def CMP32mi8 : Ii8<0x83, MRM7m,
2345 (ops i32mem:$src1, i32i8imm:$src2),
2346 "cmp{l} {$src2, $src1|$src1, $src2}",
2347 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2)]>;
2348 def CMP32ri8 : Ii8<0x83, MRM7r,
2349 (ops GR32:$src1, i32i8imm:$src2),
2350 "cmp{l} {$src2, $src1|$src1, $src2}",
2351 [(X86cmp GR32:$src1, i32immSExt8:$src2)]>;
2353 // Sign/Zero extenders
2354 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops GR16:$dst, GR8 :$src),
2355 "movs{bw|x} {$src, $dst|$dst, $src}",
2356 [(set GR16:$dst, (sext GR8:$src))]>, TB, OpSize;
2357 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (ops GR16:$dst, i8mem :$src),
2358 "movs{bw|x} {$src, $dst|$dst, $src}",
2359 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize;
2360 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops GR32:$dst, GR8 :$src),
2361 "movs{bl|x} {$src, $dst|$dst, $src}",
2362 [(set GR32:$dst, (sext GR8:$src))]>, TB;
2363 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (ops GR32:$dst, i8mem :$src),
2364 "movs{bl|x} {$src, $dst|$dst, $src}",
2365 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
2366 def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops GR32:$dst, GR16:$src),
2367 "movs{wl|x} {$src, $dst|$dst, $src}",
2368 [(set GR32:$dst, (sext GR16:$src))]>, TB;
2369 def MOVSX32rm16: I<0xBF, MRMSrcMem, (ops GR32:$dst, i16mem:$src),
2370 "movs{wl|x} {$src, $dst|$dst, $src}",
2371 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
2373 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops GR16:$dst, GR8 :$src),
2374 "movz{bw|x} {$src, $dst|$dst, $src}",
2375 [(set GR16:$dst, (zext GR8:$src))]>, TB, OpSize;
2376 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (ops GR16:$dst, i8mem :$src),
2377 "movz{bw|x} {$src, $dst|$dst, $src}",
2378 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize;
2379 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops GR32:$dst, GR8 :$src),
2380 "movz{bl|x} {$src, $dst|$dst, $src}",
2381 [(set GR32:$dst, (zext GR8:$src))]>, TB;
2382 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (ops GR32:$dst, i8mem :$src),
2383 "movz{bl|x} {$src, $dst|$dst, $src}",
2384 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
2385 def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops GR32:$dst, GR16:$src),
2386 "movz{wl|x} {$src, $dst|$dst, $src}",
2387 [(set GR32:$dst, (zext GR16:$src))]>, TB;
2388 def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops GR32:$dst, i16mem:$src),
2389 "movz{wl|x} {$src, $dst|$dst, $src}",
2390 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
2392 def CBW : I<0x98, RawFrm, (ops),
2393 "{cbtw|cbw}", []>, Imp<[AL],[AX]>; // AX = signext(AL)
2394 def CWDE : I<0x98, RawFrm, (ops),
2395 "{cwtl|cwde}", []>, Imp<[AX],[EAX]>; // EAX = signext(AX)
2397 def CWD : I<0x99, RawFrm, (ops),
2398 "{cwtd|cwd}", []>, Imp<[AX],[AX,DX]>; // DX:AX = signext(AX)
2399 def CDQ : I<0x99, RawFrm, (ops),
2400 "{cltd|cdq}", []>, Imp<[EAX],[EAX,EDX]>; // EDX:EAX = signext(EAX)
2402 //===----------------------------------------------------------------------===//
2403 // Miscellaneous Instructions
2404 //===----------------------------------------------------------------------===//
2406 def RDTSC : I<0x31, RawFrm, (ops), "rdtsc", [(X86rdtsc)]>,
2407 TB, Imp<[],[EAX,EDX]>;
2409 //===----------------------------------------------------------------------===//
2410 // Alias Instructions
2411 //===----------------------------------------------------------------------===//
2413 // Alias instructions that map movr0 to xor.
2414 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2415 def MOV8r0 : I<0x30, MRMInitReg, (ops GR8 :$dst),
2416 "xor{b} $dst, $dst",
2417 [(set GR8:$dst, 0)]>;
2418 def MOV16r0 : I<0x31, MRMInitReg, (ops GR16:$dst),
2419 "xor{w} $dst, $dst",
2420 [(set GR16:$dst, 0)]>, OpSize;
2421 def MOV32r0 : I<0x31, MRMInitReg, (ops GR32:$dst),
2422 "xor{l} $dst, $dst",
2423 [(set GR32:$dst, 0)]>;
2425 // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
2426 // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
2427 def MOV16to16_ : I<0x89, MRMDestReg, (ops GR16_:$dst, GR16:$src),
2428 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
2429 def MOV32to32_ : I<0x89, MRMDestReg, (ops GR32_:$dst, GR32:$src),
2430 "mov{l} {$src, $dst|$dst, $src}", []>;
2432 def MOV16_rr : I<0x89, MRMDestReg, (ops GR16_:$dst, GR16_:$src),
2433 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
2434 def MOV32_rr : I<0x89, MRMDestReg, (ops GR32_:$dst, GR32_:$src),
2435 "mov{l} {$src, $dst|$dst, $src}", []>;
2436 def MOV16_rm : I<0x8B, MRMSrcMem, (ops GR16_:$dst, i16mem:$src),
2437 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
2438 def MOV32_rm : I<0x8B, MRMSrcMem, (ops GR32_:$dst, i32mem:$src),
2439 "mov{l} {$src, $dst|$dst, $src}", []>;
2440 def MOV16_mr : I<0x89, MRMDestMem, (ops i16mem:$dst, GR16_:$src),
2441 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
2442 def MOV32_mr : I<0x89, MRMDestMem, (ops i32mem:$dst, GR32_:$src),
2443 "mov{l} {$src, $dst|$dst, $src}", []>;
2445 //===----------------------------------------------------------------------===//
2446 // DWARF Pseudo Instructions
2449 def DWARF_LOC : I<0, Pseudo, (ops i32imm:$line, i32imm:$col, i32imm:$file),
2450 "; .loc $file, $line, $col",
2451 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
2454 def DWARF_LABEL : I<0, Pseudo, (ops i32imm:$id),
2455 "\n${:private}debug_loc${id:debug}:",
2456 [(dwarf_label (i32 imm:$id))]>;
2458 //===----------------------------------------------------------------------===//
2459 // Non-Instruction Patterns
2460 //===----------------------------------------------------------------------===//
2462 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
2463 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
2464 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
2465 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
2466 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
2468 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
2469 (ADD32ri GR32:$src1, tconstpool:$src2)>;
2470 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
2471 (ADD32ri GR32:$src1, tjumptable:$src2)>;
2472 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
2473 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
2474 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
2475 (ADD32ri GR32:$src1, texternalsym:$src2)>;
2477 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
2478 (MOV32mi addr:$dst, tglobaladdr:$src)>;
2479 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
2480 (MOV32mi addr:$dst, texternalsym:$src)>;
2483 def : Pat<(X86tailcall GR32:$dst),
2484 (CALL32r GR32:$dst)>;
2486 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
2487 (CALLpcrel32 tglobaladdr:$dst)>;
2488 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
2489 (CALLpcrel32 texternalsym:$dst)>;
2491 def : Pat<(X86call (i32 tglobaladdr:$dst)),
2492 (CALLpcrel32 tglobaladdr:$dst)>;
2493 def : Pat<(X86call (i32 texternalsym:$dst)),
2494 (CALLpcrel32 texternalsym:$dst)>;
2496 // X86 specific add which produces a flag.
2497 def : Pat<(addc GR32:$src1, GR32:$src2),
2498 (ADD32rr GR32:$src1, GR32:$src2)>;
2499 def : Pat<(addc GR32:$src1, (load addr:$src2)),
2500 (ADD32rm GR32:$src1, addr:$src2)>;
2501 def : Pat<(addc GR32:$src1, imm:$src2),
2502 (ADD32ri GR32:$src1, imm:$src2)>;
2503 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
2504 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
2506 def : Pat<(subc GR32:$src1, GR32:$src2),
2507 (SUB32rr GR32:$src1, GR32:$src2)>;
2508 def : Pat<(subc GR32:$src1, (load addr:$src2)),
2509 (SUB32rm GR32:$src1, addr:$src2)>;
2510 def : Pat<(subc GR32:$src1, imm:$src2),
2511 (SUB32ri GR32:$src1, imm:$src2)>;
2512 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
2513 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
2515 def : Pat<(truncstorei1 (i8 imm:$src), addr:$dst),
2516 (MOV8mi addr:$dst, imm:$src)>;
2517 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
2518 (MOV8mr addr:$dst, GR8:$src)>;
2522 // TEST R,R is smaller than CMP R,0
2523 def : Pat<(X86cmp GR8:$src1, 0),
2524 (TEST8rr GR8:$src1, GR8:$src1)>;
2525 def : Pat<(X86cmp GR16:$src1, 0),
2526 (TEST16rr GR16:$src1, GR16:$src1)>;
2527 def : Pat<(X86cmp GR32:$src1, 0),
2528 (TEST32rr GR32:$src1, GR32:$src1)>;
2530 // {s|z}extload bool -> {s|z}extload byte
2531 def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>;
2532 def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>;
2533 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2534 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2535 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2537 // extload bool -> extload byte
2538 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2539 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2540 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2541 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
2542 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
2543 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
2546 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
2547 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
2548 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
2549 def : Pat<(i16 (anyext (loadi8 addr:$src))), (MOVZX16rm8 addr:$src)>;
2550 def : Pat<(i32 (anyext (loadi8 addr:$src))), (MOVZX32rm8 addr:$src)>;
2551 def : Pat<(i32 (anyext (loadi16 addr:$src))), (MOVZX32rm16 addr:$src)>;
2553 //===----------------------------------------------------------------------===//
2555 //===----------------------------------------------------------------------===//
2557 // (shl x, 1) ==> (add x, x)
2558 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
2559 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
2560 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
2562 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
2563 def : Pat<(or (srl GR32:$src1, CL:$amt),
2564 (shl GR32:$src2, (sub 32, CL:$amt))),
2565 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
2567 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
2568 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2569 (SHRD32mrCL addr:$dst, GR32:$src2)>;
2571 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
2572 def : Pat<(or (shl GR32:$src1, CL:$amt),
2573 (srl GR32:$src2, (sub 32, CL:$amt))),
2574 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
2576 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
2577 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2578 (SHLD32mrCL addr:$dst, GR32:$src2)>;
2580 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
2581 def : Pat<(or (srl GR16:$src1, CL:$amt),
2582 (shl GR16:$src2, (sub 16, CL:$amt))),
2583 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
2585 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
2586 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2587 (SHRD16mrCL addr:$dst, GR16:$src2)>;
2589 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
2590 def : Pat<(or (shl GR16:$src1, CL:$amt),
2591 (srl GR16:$src2, (sub 16, CL:$amt))),
2592 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
2594 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
2595 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2596 (SHLD16mrCL addr:$dst, GR16:$src2)>;
2599 //===----------------------------------------------------------------------===//
2600 // Floating Point Stack Support
2601 //===----------------------------------------------------------------------===//
2603 include "X86InstrFPStack.td"
2605 //===----------------------------------------------------------------------===//
2606 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
2607 //===----------------------------------------------------------------------===//
2609 include "X86InstrMMX.td"
2611 //===----------------------------------------------------------------------===//
2612 // XMM Floating point support (requires SSE / SSE2)
2613 //===----------------------------------------------------------------------===//
2615 include "X86InstrSSE.td"
2617 //===----------------------------------------------------------------------===//
2619 //===----------------------------------------------------------------------===//
2621 include "X86InstrX86-64.td"