1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 def SDTX86BrCond : SDTypeProfile<0, 3,
31 [SDTCisVT<0, OtherVT>,
32 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
34 def SDTX86SetCC : SDTypeProfile<1, 2,
36 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
38 def SDTX86Ret : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>;
40 def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
41 def SDT_X86CallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
44 def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
46 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
48 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
50 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
52 def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
54 def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
56 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
58 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
60 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
61 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
62 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
63 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
65 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
67 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
68 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
70 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
72 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
73 [SDNPHasChain, SDNPOptInFlag]>;
75 def X86callseq_start :
76 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
77 [SDNPHasChain, SDNPOutFlag]>;
79 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
82 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
83 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
85 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
86 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
88 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
89 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
90 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
91 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
93 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
94 [SDNPHasChain, SDNPOutFlag]>;
96 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
97 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
99 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
100 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
101 def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
103 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
106 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
107 [SDNPHasChain, SDNPOptInFlag]>;
109 //===----------------------------------------------------------------------===//
110 // X86 Operand Definitions.
113 // *mem - Operand definitions for the funky X86 addressing mode operands.
115 class X86MemOperand<string printMethod> : Operand<iPTR> {
116 let PrintMethod = printMethod;
117 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
120 def i8mem : X86MemOperand<"printi8mem">;
121 def i16mem : X86MemOperand<"printi16mem">;
122 def i32mem : X86MemOperand<"printi32mem">;
123 def i64mem : X86MemOperand<"printi64mem">;
124 def i128mem : X86MemOperand<"printi128mem">;
125 def f32mem : X86MemOperand<"printf32mem">;
126 def f64mem : X86MemOperand<"printf64mem">;
127 def f80mem : X86MemOperand<"printf80mem">;
128 def f128mem : X86MemOperand<"printf128mem">;
130 def lea32mem : Operand<i32> {
131 let PrintMethod = "printi32mem";
132 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
135 def SSECC : Operand<i8> {
136 let PrintMethod = "printSSECC";
139 def piclabel: Operand<i32> {
140 let PrintMethod = "printPICLabel";
143 // A couple of more descriptive operand definitions.
144 // 16-bits but only 8 bits are significant.
145 def i16i8imm : Operand<i16>;
146 // 32-bits but only 8 bits are significant.
147 def i32i8imm : Operand<i32>;
149 // Branch targets have OtherVT type.
150 def brtarget : Operand<OtherVT>;
152 //===----------------------------------------------------------------------===//
153 // X86 Complex Pattern Definitions.
156 // Define X86 specific addressing mode.
157 def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
158 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
159 [add, mul, shl, or, frameindex], []>;
161 //===----------------------------------------------------------------------===//
162 // X86 Instruction Predicate Definitions.
163 def HasMMX : Predicate<"Subtarget->hasMMX()">;
164 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
165 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
166 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
167 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
168 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
169 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
170 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
171 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
172 def HasLow4G : Predicate<"Subtarget->hasLow4GUserSpaceAddress()">;
173 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
174 def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
175 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
177 //===----------------------------------------------------------------------===//
178 // X86 Instruction Format Definitions.
181 include "X86InstrFormats.td"
183 //===----------------------------------------------------------------------===//
184 // Pattern fragments...
187 // X86 specific condition code. These correspond to CondCode in
188 // X86InstrInfo.h. They must be kept in synch.
189 def X86_COND_A : PatLeaf<(i8 0)>;
190 def X86_COND_AE : PatLeaf<(i8 1)>;
191 def X86_COND_B : PatLeaf<(i8 2)>;
192 def X86_COND_BE : PatLeaf<(i8 3)>;
193 def X86_COND_E : PatLeaf<(i8 4)>;
194 def X86_COND_G : PatLeaf<(i8 5)>;
195 def X86_COND_GE : PatLeaf<(i8 6)>;
196 def X86_COND_L : PatLeaf<(i8 7)>;
197 def X86_COND_LE : PatLeaf<(i8 8)>;
198 def X86_COND_NE : PatLeaf<(i8 9)>;
199 def X86_COND_NO : PatLeaf<(i8 10)>;
200 def X86_COND_NP : PatLeaf<(i8 11)>;
201 def X86_COND_NS : PatLeaf<(i8 12)>;
202 def X86_COND_O : PatLeaf<(i8 13)>;
203 def X86_COND_P : PatLeaf<(i8 14)>;
204 def X86_COND_S : PatLeaf<(i8 15)>;
206 def i16immSExt8 : PatLeaf<(i16 imm), [{
207 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
208 // sign extended field.
209 return (int16_t)N->getValue() == (int8_t)N->getValue();
212 def i32immSExt8 : PatLeaf<(i32 imm), [{
213 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
214 // sign extended field.
215 return (int32_t)N->getValue() == (int8_t)N->getValue();
218 // Helper fragments for loads.
219 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
220 def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>;
221 def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>;
222 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
224 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
225 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
226 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
228 def sextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (sextloadi1 node:$ptr))>;
229 def sextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (sextloadi1 node:$ptr))>;
230 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
231 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
232 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
234 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
235 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
236 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
237 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
238 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
239 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
241 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
242 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
243 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
244 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
245 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
246 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
248 //===----------------------------------------------------------------------===//
249 // Instruction list...
252 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
253 // a stack adjustment and the codegen must know that they may modify the stack
254 // pointer before prolog-epilog rewriting occurs.
255 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become sub / add
256 // which can clobber EFLAGS.
257 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
258 def ADJCALLSTACKDOWN : I<0, Pseudo, (outs), (ins i32imm:$amt),
260 [(X86callseq_start imm:$amt)]>;
261 def ADJCALLSTACKUP : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
263 [(X86callseq_end imm:$amt1, imm:$amt2)]>;
265 def IMPLICIT_USE : I<0, Pseudo, (outs), (ins variable_ops),
266 "#IMPLICIT_USE", []>;
267 let isImplicitDef = 1 in {
268 def IMPLICIT_DEF : I<0, Pseudo, (outs variable_ops), (ins),
269 "#IMPLICIT_DEF", []>;
270 def IMPLICIT_DEF_GR8 : I<0, Pseudo, (outs GR8:$dst), (ins),
271 "#IMPLICIT_DEF $dst",
272 [(set GR8:$dst, (undef))]>;
273 def IMPLICIT_DEF_GR16 : I<0, Pseudo, (outs GR16:$dst), (ins),
274 "#IMPLICIT_DEF $dst",
275 [(set GR16:$dst, (undef))]>;
276 def IMPLICIT_DEF_GR32 : I<0, Pseudo, (outs GR32:$dst), (ins),
277 "#IMPLICIT_DEF $dst",
278 [(set GR32:$dst, (undef))]>;
282 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
285 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
286 "call\t$label\n\tpop{l}\t$reg", []>;
288 //===----------------------------------------------------------------------===//
289 // Control Flow Instructions...
292 // Return instructions.
293 let isTerminator = 1, isReturn = 1, isBarrier = 1,
295 def RET : I<0xC3, RawFrm, (outs), (ins), "ret", [(X86retflag 0)]>;
296 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), "ret\t$amt",
297 [(X86retflag imm:$amt)]>;
300 // All branches are RawFrm, Void, Branch, and Terminators
301 let isBranch = 1, isTerminator = 1 in
302 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
303 I<opcode, RawFrm, (outs), ins, asm, pattern>;
305 let isBranch = 1, isBarrier = 1 in
306 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
309 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
310 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
311 [(brind GR32:$dst)]>;
312 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
313 [(brind (loadi32 addr:$dst))]>;
316 // Conditional branches
317 let Uses = [EFLAGS] in {
318 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
319 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
320 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
321 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
322 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
323 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
324 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
325 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
326 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
327 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
328 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
329 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
331 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
332 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
333 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
334 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
335 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
336 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
337 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
338 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
340 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
341 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
342 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
343 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
344 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
345 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
346 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
347 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
348 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
349 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
350 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
351 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
354 //===----------------------------------------------------------------------===//
355 // Call Instructions...
358 // All calls clobber the non-callee saved registers...
359 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
360 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
361 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, EFLAGS] in {
362 def CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:$dst,variable_ops),
363 "call\t${dst:call}", []>;
364 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
365 "call\t{*}$dst", [(X86call GR32:$dst)]>;
366 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
367 "call\t{*}$dst", []>;
372 def TAILCALL : I<0, Pseudo, (outs), (ins ),
376 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
377 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset),
378 "#TC_RETURN $dst $offset",
381 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
382 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset),
383 "#TC_RETURN $dst $offset",
386 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
387 def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAILCALL",
389 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
390 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
392 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
393 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
394 "jmp\t{*}$dst # TAILCALL", []>;
396 //===----------------------------------------------------------------------===//
397 // Miscellaneous Instructions...
399 let Defs = [EBP, ESP], Uses = [EBP, ESP] in
400 def LEAVE : I<0xC9, RawFrm,
401 (outs), (ins), "leave", []>;
403 let Defs = [ESP], Uses = [ESP] in {
404 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
406 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
409 let Defs = [ESP, EFLAGS], Uses = [ESP] in
410 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
411 let Defs = [ESP], Uses = [ESP, EFLAGS] in
412 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
414 let isTwoAddress = 1 in // GR32 = bswap GR32
415 def BSWAP32r : I<0xC8, AddRegFrm,
416 (outs GR32:$dst), (ins GR32:$src),
418 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
420 // FIXME: Model xchg* as two address instructions?
421 def XCHG8rr : I<0x86, MRMDestReg, // xchg GR8, GR8
422 (outs), (ins GR8:$src1, GR8:$src2),
423 "xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
424 def XCHG16rr : I<0x87, MRMDestReg, // xchg GR16, GR16
425 (outs), (ins GR16:$src1, GR16:$src2),
426 "xchg{w}\t{$src2|$src1}, {$src1|$src2}", []>, OpSize;
427 def XCHG32rr : I<0x87, MRMDestReg, // xchg GR32, GR32
428 (outs), (ins GR32:$src1, GR32:$src2),
429 "xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
431 def XCHG8mr : I<0x86, MRMDestMem,
432 (outs), (ins i8mem:$src1, GR8:$src2),
433 "xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
434 def XCHG16mr : I<0x87, MRMDestMem,
435 (outs), (ins i16mem:$src1, GR16:$src2),
436 "xchg{w}\t{$src2|$src1}, {$src1|$src2}", []>, OpSize;
437 def XCHG32mr : I<0x87, MRMDestMem,
438 (outs), (ins i32mem:$src1, GR32:$src2),
439 "xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
440 def XCHG8rm : I<0x86, MRMSrcMem,
441 (outs), (ins GR8:$src1, i8mem:$src2),
442 "xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
443 def XCHG16rm : I<0x87, MRMSrcMem,
444 (outs), (ins GR16:$src1, i16mem:$src2),
445 "xchg{w}\t{$src2|$src1}, {$src1|$src2}", []>, OpSize;
446 def XCHG32rm : I<0x87, MRMSrcMem,
447 (outs), (ins GR32:$src1, i32mem:$src2),
448 "xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
450 // Bit scan instructions.
451 let Defs = [EFLAGS] in {
452 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
453 "bsf{w}\t{$src, $dst|$dst, $src}",
454 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
455 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
456 "bsf{w}\t{$src, $dst|$dst, $src}",
457 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
458 (implicit EFLAGS)]>, TB;
459 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
460 "bsf{l}\t{$src, $dst|$dst, $src}",
461 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
462 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
463 "bsf{l}\t{$src, $dst|$dst, $src}",
464 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
465 (implicit EFLAGS)]>, TB;
467 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
468 "bsr{w}\t{$src, $dst|$dst, $src}",
469 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
470 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
471 "bsr{w}\t{$src, $dst|$dst, $src}",
472 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
473 (implicit EFLAGS)]>, TB;
474 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
475 "bsr{l}\t{$src, $dst|$dst, $src}",
476 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
477 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
478 "bsr{l}\t{$src, $dst|$dst, $src}",
479 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
480 (implicit EFLAGS)]>, TB;
483 def LEA16r : I<0x8D, MRMSrcMem,
484 (outs GR16:$dst), (ins i32mem:$src),
485 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
486 def LEA32r : I<0x8D, MRMSrcMem,
487 (outs GR32:$dst), (ins lea32mem:$src),
488 "lea{l}\t{$src|$dst}, {$dst|$src}",
489 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
491 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
492 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
493 [(X86rep_movs i8)]>, REP;
494 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
495 [(X86rep_movs i16)]>, REP, OpSize;
496 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
497 [(X86rep_movs i32)]>, REP;
500 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
501 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
502 [(X86rep_stos i8)]>, REP;
503 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
504 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
505 [(X86rep_stos i16)]>, REP, OpSize;
506 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
507 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
508 [(X86rep_stos i32)]>, REP;
510 let Defs = [RAX, RDX] in
511 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
514 //===----------------------------------------------------------------------===//
515 // Input/Output Instructions...
517 let Defs = [AL], Uses = [DX] in
518 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
519 "in{b}\t{%dx, %al|%AL, %DX}", []>;
520 let Defs = [AX], Uses = [DX] in
521 def IN16rr : I<0xED, RawFrm, (outs), (ins),
522 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
523 let Defs = [EAX], Uses = [DX] in
524 def IN32rr : I<0xED, RawFrm, (outs), (ins),
525 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
528 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
529 "in{b}\t{$port, %al|%AL, $port}", []>;
531 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
532 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
534 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
535 "in{l}\t{$port, %eax|%EAX, $port}", []>;
537 let Uses = [DX, AL] in
538 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
539 "out{b}\t{%al, %dx|%DX, %AL}", []>;
540 let Uses = [DX, AX] in
541 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
542 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
543 let Uses = [DX, EAX] in
544 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
545 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
548 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
549 "out{b}\t{%al, $port|$port, %AL}", []>;
551 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
552 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
554 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
555 "out{l}\t{%eax, $port|$port, %EAX}", []>;
557 //===----------------------------------------------------------------------===//
558 // Move Instructions...
560 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
561 "mov{b}\t{$src, $dst|$dst, $src}", []>;
562 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
563 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
564 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
565 "mov{l}\t{$src, $dst|$dst, $src}", []>;
566 let isReMaterializable = 1, neverHasSideEffects = 1 in {
567 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
568 "mov{b}\t{$src, $dst|$dst, $src}",
569 [(set GR8:$dst, imm:$src)]>;
570 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
571 "mov{w}\t{$src, $dst|$dst, $src}",
572 [(set GR16:$dst, imm:$src)]>, OpSize;
573 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
574 "mov{l}\t{$src, $dst|$dst, $src}",
575 [(set GR32:$dst, imm:$src)]>;
577 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
578 "mov{b}\t{$src, $dst|$dst, $src}",
579 [(store (i8 imm:$src), addr:$dst)]>;
580 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
581 "mov{w}\t{$src, $dst|$dst, $src}",
582 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
583 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
584 "mov{l}\t{$src, $dst|$dst, $src}",
585 [(store (i32 imm:$src), addr:$dst)]>;
587 let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
588 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
589 "mov{b}\t{$src, $dst|$dst, $src}",
590 [(set GR8:$dst, (load addr:$src))]>;
591 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
592 "mov{w}\t{$src, $dst|$dst, $src}",
593 [(set GR16:$dst, (load addr:$src))]>, OpSize;
594 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
595 "mov{l}\t{$src, $dst|$dst, $src}",
596 [(set GR32:$dst, (load addr:$src))]>;
599 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
600 "mov{b}\t{$src, $dst|$dst, $src}",
601 [(store GR8:$src, addr:$dst)]>;
602 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
603 "mov{w}\t{$src, $dst|$dst, $src}",
604 [(store GR16:$src, addr:$dst)]>, OpSize;
605 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
606 "mov{l}\t{$src, $dst|$dst, $src}",
607 [(store GR32:$src, addr:$dst)]>;
609 //===----------------------------------------------------------------------===//
610 // Fixed-Register Multiplication and Division Instructions...
613 // Extra precision multiplication
614 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
615 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
616 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
617 // This probably ought to be moved to a def : Pat<> if the
618 // syntax can be accepted.
619 [(set AL, (mul AL, GR8:$src))]>; // AL,AH = AL*GR8
620 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
621 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>,
622 OpSize; // AX,DX = AX*GR16
623 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
624 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l}\t$src", []>;
625 // EAX,EDX = EAX*GR32
626 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
627 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
629 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
630 // This probably ought to be moved to a def : Pat<> if the
631 // syntax can be accepted.
632 [(set AL, (mul AL, (loadi8 addr:$src)))]>; // AL,AH = AL*[mem8]
633 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
634 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
635 "mul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
636 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
637 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
638 "mul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
640 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
641 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
643 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
644 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
645 OpSize; // AX,DX = AX*GR16
646 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
647 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
648 // EAX,EDX = EAX*GR32
649 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
650 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
651 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
652 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
653 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
654 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
655 let Defs = [EAX,EDX], Uses = [EAX] in
656 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
657 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
659 // unsigned division/remainder
660 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
661 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
663 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
664 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
665 "div{w}\t$src", []>, OpSize;
666 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
667 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
669 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
670 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
672 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
673 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
674 "div{w}\t$src", []>, OpSize;
675 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
676 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
679 // Signed division/remainder.
680 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
681 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
682 "idiv{b}\t$src", []>;
683 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
684 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
685 "idiv{w}\t$src", []>, OpSize;
686 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
687 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
688 "idiv{l}\t$src", []>;
689 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
690 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
691 "idiv{b}\t$src", []>;
692 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
693 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
694 "idiv{w}\t$src", []>, OpSize;
695 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
696 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
697 "idiv{l}\t$src", []>;
700 //===----------------------------------------------------------------------===//
701 // Two address Instructions...
703 let isTwoAddress = 1 in {
706 let Uses = [EFLAGS] in {
707 let isCommutable = 1 in {
708 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
709 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
710 "cmovb\t{$src2, $dst|$dst, $src2}",
711 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
712 X86_COND_B, EFLAGS))]>,
714 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
715 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
716 "cmovb\t{$src2, $dst|$dst, $src2}",
717 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
718 X86_COND_B, EFLAGS))]>,
721 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
722 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
723 "cmovae\t{$src2, $dst|$dst, $src2}",
724 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
725 X86_COND_AE, EFLAGS))]>,
727 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
728 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
729 "cmovae\t{$src2, $dst|$dst, $src2}",
730 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
731 X86_COND_AE, EFLAGS))]>,
733 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
734 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
735 "cmove\t{$src2, $dst|$dst, $src2}",
736 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
737 X86_COND_E, EFLAGS))]>,
739 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
740 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
741 "cmove\t{$src2, $dst|$dst, $src2}",
742 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
743 X86_COND_E, EFLAGS))]>,
745 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
746 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
747 "cmovne\t{$src2, $dst|$dst, $src2}",
748 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
749 X86_COND_NE, EFLAGS))]>,
751 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
752 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
753 "cmovne\t{$src2, $dst|$dst, $src2}",
754 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
755 X86_COND_NE, EFLAGS))]>,
757 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
758 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
759 "cmovbe\t{$src2, $dst|$dst, $src2}",
760 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
761 X86_COND_BE, EFLAGS))]>,
763 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
764 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
765 "cmovbe\t{$src2, $dst|$dst, $src2}",
766 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
767 X86_COND_BE, EFLAGS))]>,
769 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
770 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
771 "cmova\t{$src2, $dst|$dst, $src2}",
772 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
773 X86_COND_A, EFLAGS))]>,
775 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
776 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
777 "cmova\t{$src2, $dst|$dst, $src2}",
778 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
779 X86_COND_A, EFLAGS))]>,
781 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
782 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
783 "cmovl\t{$src2, $dst|$dst, $src2}",
784 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
785 X86_COND_L, EFLAGS))]>,
787 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
788 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
789 "cmovl\t{$src2, $dst|$dst, $src2}",
790 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
791 X86_COND_L, EFLAGS))]>,
793 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
794 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
795 "cmovge\t{$src2, $dst|$dst, $src2}",
796 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
797 X86_COND_GE, EFLAGS))]>,
799 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
800 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
801 "cmovge\t{$src2, $dst|$dst, $src2}",
802 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
803 X86_COND_GE, EFLAGS))]>,
805 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
806 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
807 "cmovle\t{$src2, $dst|$dst, $src2}",
808 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
809 X86_COND_LE, EFLAGS))]>,
811 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
812 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
813 "cmovle\t{$src2, $dst|$dst, $src2}",
814 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
815 X86_COND_LE, EFLAGS))]>,
817 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
818 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
819 "cmovg\t{$src2, $dst|$dst, $src2}",
820 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
821 X86_COND_G, EFLAGS))]>,
823 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
824 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
825 "cmovg\t{$src2, $dst|$dst, $src2}",
826 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
827 X86_COND_G, EFLAGS))]>,
829 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
830 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
831 "cmovs\t{$src2, $dst|$dst, $src2}",
832 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
833 X86_COND_S, EFLAGS))]>,
835 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
836 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
837 "cmovs\t{$src2, $dst|$dst, $src2}",
838 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
839 X86_COND_S, EFLAGS))]>,
841 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
842 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
843 "cmovns\t{$src2, $dst|$dst, $src2}",
844 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
845 X86_COND_NS, EFLAGS))]>,
847 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
848 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
849 "cmovns\t{$src2, $dst|$dst, $src2}",
850 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
851 X86_COND_NS, EFLAGS))]>,
853 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
854 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
855 "cmovp\t{$src2, $dst|$dst, $src2}",
856 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
857 X86_COND_P, EFLAGS))]>,
859 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
860 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
861 "cmovp\t{$src2, $dst|$dst, $src2}",
862 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
863 X86_COND_P, EFLAGS))]>,
865 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
866 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
867 "cmovnp\t{$src2, $dst|$dst, $src2}",
868 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
869 X86_COND_NP, EFLAGS))]>,
871 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
872 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
873 "cmovnp\t{$src2, $dst|$dst, $src2}",
874 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
875 X86_COND_NP, EFLAGS))]>,
877 } // isCommutable = 1
879 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
880 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
881 "cmovnp\t{$src2, $dst|$dst, $src2}",
882 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
883 X86_COND_NP, EFLAGS))]>,
886 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
887 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
888 "cmovb\t{$src2, $dst|$dst, $src2}",
889 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
890 X86_COND_B, EFLAGS))]>,
892 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
893 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
894 "cmovb\t{$src2, $dst|$dst, $src2}",
895 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
896 X86_COND_B, EFLAGS))]>,
898 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
899 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
900 "cmovae\t{$src2, $dst|$dst, $src2}",
901 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
902 X86_COND_AE, EFLAGS))]>,
904 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
905 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
906 "cmovae\t{$src2, $dst|$dst, $src2}",
907 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
908 X86_COND_AE, EFLAGS))]>,
910 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
911 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
912 "cmove\t{$src2, $dst|$dst, $src2}",
913 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
914 X86_COND_E, EFLAGS))]>,
916 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
917 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
918 "cmove\t{$src2, $dst|$dst, $src2}",
919 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
920 X86_COND_E, EFLAGS))]>,
922 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
923 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
924 "cmovne\t{$src2, $dst|$dst, $src2}",
925 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
926 X86_COND_NE, EFLAGS))]>,
928 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
929 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
930 "cmovne\t{$src2, $dst|$dst, $src2}",
931 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
932 X86_COND_NE, EFLAGS))]>,
934 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
935 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
936 "cmovbe\t{$src2, $dst|$dst, $src2}",
937 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
938 X86_COND_BE, EFLAGS))]>,
940 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
941 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
942 "cmovbe\t{$src2, $dst|$dst, $src2}",
943 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
944 X86_COND_BE, EFLAGS))]>,
946 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
947 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
948 "cmova\t{$src2, $dst|$dst, $src2}",
949 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
950 X86_COND_A, EFLAGS))]>,
952 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
953 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
954 "cmova\t{$src2, $dst|$dst, $src2}",
955 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
956 X86_COND_A, EFLAGS))]>,
958 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
959 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
960 "cmovl\t{$src2, $dst|$dst, $src2}",
961 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
962 X86_COND_L, EFLAGS))]>,
964 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
965 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
966 "cmovl\t{$src2, $dst|$dst, $src2}",
967 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
968 X86_COND_L, EFLAGS))]>,
970 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
971 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
972 "cmovge\t{$src2, $dst|$dst, $src2}",
973 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
974 X86_COND_GE, EFLAGS))]>,
976 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
977 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
978 "cmovge\t{$src2, $dst|$dst, $src2}",
979 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
980 X86_COND_GE, EFLAGS))]>,
982 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
983 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
984 "cmovle\t{$src2, $dst|$dst, $src2}",
985 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
986 X86_COND_LE, EFLAGS))]>,
988 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
989 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
990 "cmovle\t{$src2, $dst|$dst, $src2}",
991 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
992 X86_COND_LE, EFLAGS))]>,
994 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
995 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
996 "cmovg\t{$src2, $dst|$dst, $src2}",
997 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
998 X86_COND_G, EFLAGS))]>,
1000 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1001 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1002 "cmovg\t{$src2, $dst|$dst, $src2}",
1003 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1004 X86_COND_G, EFLAGS))]>,
1006 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1007 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1008 "cmovs\t{$src2, $dst|$dst, $src2}",
1009 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1010 X86_COND_S, EFLAGS))]>,
1012 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1013 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1014 "cmovs\t{$src2, $dst|$dst, $src2}",
1015 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1016 X86_COND_S, EFLAGS))]>,
1018 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1019 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1020 "cmovns\t{$src2, $dst|$dst, $src2}",
1021 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1022 X86_COND_NS, EFLAGS))]>,
1024 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1025 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1026 "cmovns\t{$src2, $dst|$dst, $src2}",
1027 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1028 X86_COND_NS, EFLAGS))]>,
1030 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1031 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1032 "cmovp\t{$src2, $dst|$dst, $src2}",
1033 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1034 X86_COND_P, EFLAGS))]>,
1036 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1037 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1038 "cmovp\t{$src2, $dst|$dst, $src2}",
1039 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1040 X86_COND_P, EFLAGS))]>,
1042 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1043 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1044 "cmovnp\t{$src2, $dst|$dst, $src2}",
1045 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1046 X86_COND_NP, EFLAGS))]>,
1048 } // Uses = [EFLAGS]
1051 // unary instructions
1052 let CodeSize = 2 in {
1053 let Defs = [EFLAGS] in {
1054 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1055 [(set GR8:$dst, (ineg GR8:$src))]>;
1056 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1057 [(set GR16:$dst, (ineg GR16:$src))]>, OpSize;
1058 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1059 [(set GR32:$dst, (ineg GR32:$src))]>;
1060 let isTwoAddress = 0 in {
1061 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1062 [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
1063 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1064 [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1065 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1066 [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
1069 } // Defs = [EFLAGS]
1071 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1072 [(set GR8:$dst, (not GR8:$src))]>;
1073 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1074 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1075 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1076 [(set GR32:$dst, (not GR32:$src))]>;
1077 let isTwoAddress = 0 in {
1078 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1079 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1080 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1081 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1082 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1083 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1087 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1088 let Defs = [EFLAGS] in {
1090 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1091 [(set GR8:$dst, (add GR8:$src, 1))]>;
1092 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1093 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1094 [(set GR16:$dst, (add GR16:$src, 1))]>,
1095 OpSize, Requires<[In32BitMode]>;
1096 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1097 [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>;
1099 let isTwoAddress = 0, CodeSize = 2 in {
1100 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1101 [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
1102 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1103 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>,
1104 OpSize, Requires<[In32BitMode]>;
1105 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1106 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>,
1107 Requires<[In32BitMode]>;
1111 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1112 [(set GR8:$dst, (add GR8:$src, -1))]>;
1113 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1114 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1115 [(set GR16:$dst, (add GR16:$src, -1))]>,
1116 OpSize, Requires<[In32BitMode]>;
1117 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1118 [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>;
1121 let isTwoAddress = 0, CodeSize = 2 in {
1122 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1123 [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
1124 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1125 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>,
1126 OpSize, Requires<[In32BitMode]>;
1127 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1128 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>,
1129 Requires<[In32BitMode]>;
1131 } // Defs = [EFLAGS]
1133 // Logical operators...
1134 let Defs = [EFLAGS] in {
1135 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1136 def AND8rr : I<0x20, MRMDestReg,
1137 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1138 "and{b}\t{$src2, $dst|$dst, $src2}",
1139 [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>;
1140 def AND16rr : I<0x21, MRMDestReg,
1141 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1142 "and{w}\t{$src2, $dst|$dst, $src2}",
1143 [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize;
1144 def AND32rr : I<0x21, MRMDestReg,
1145 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1146 "and{l}\t{$src2, $dst|$dst, $src2}",
1147 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
1150 def AND8rm : I<0x22, MRMSrcMem,
1151 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1152 "and{b}\t{$src2, $dst|$dst, $src2}",
1153 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>;
1154 def AND16rm : I<0x23, MRMSrcMem,
1155 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1156 "and{w}\t{$src2, $dst|$dst, $src2}",
1157 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize;
1158 def AND32rm : I<0x23, MRMSrcMem,
1159 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1160 "and{l}\t{$src2, $dst|$dst, $src2}",
1161 [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>;
1163 def AND8ri : Ii8<0x80, MRM4r,
1164 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1165 "and{b}\t{$src2, $dst|$dst, $src2}",
1166 [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>;
1167 def AND16ri : Ii16<0x81, MRM4r,
1168 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1169 "and{w}\t{$src2, $dst|$dst, $src2}",
1170 [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize;
1171 def AND32ri : Ii32<0x81, MRM4r,
1172 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1173 "and{l}\t{$src2, $dst|$dst, $src2}",
1174 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
1175 def AND16ri8 : Ii8<0x83, MRM4r,
1176 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1177 "and{w}\t{$src2, $dst|$dst, $src2}",
1178 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>,
1180 def AND32ri8 : Ii8<0x83, MRM4r,
1181 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1182 "and{l}\t{$src2, $dst|$dst, $src2}",
1183 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>;
1185 let isTwoAddress = 0 in {
1186 def AND8mr : I<0x20, MRMDestMem,
1187 (outs), (ins i8mem :$dst, GR8 :$src),
1188 "and{b}\t{$src, $dst|$dst, $src}",
1189 [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>;
1190 def AND16mr : I<0x21, MRMDestMem,
1191 (outs), (ins i16mem:$dst, GR16:$src),
1192 "and{w}\t{$src, $dst|$dst, $src}",
1193 [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>,
1195 def AND32mr : I<0x21, MRMDestMem,
1196 (outs), (ins i32mem:$dst, GR32:$src),
1197 "and{l}\t{$src, $dst|$dst, $src}",
1198 [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>;
1199 def AND8mi : Ii8<0x80, MRM4m,
1200 (outs), (ins i8mem :$dst, i8imm :$src),
1201 "and{b}\t{$src, $dst|$dst, $src}",
1202 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1203 def AND16mi : Ii16<0x81, MRM4m,
1204 (outs), (ins i16mem:$dst, i16imm:$src),
1205 "and{w}\t{$src, $dst|$dst, $src}",
1206 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1208 def AND32mi : Ii32<0x81, MRM4m,
1209 (outs), (ins i32mem:$dst, i32imm:$src),
1210 "and{l}\t{$src, $dst|$dst, $src}",
1211 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1212 def AND16mi8 : Ii8<0x83, MRM4m,
1213 (outs), (ins i16mem:$dst, i16i8imm :$src),
1214 "and{w}\t{$src, $dst|$dst, $src}",
1215 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1217 def AND32mi8 : Ii8<0x83, MRM4m,
1218 (outs), (ins i32mem:$dst, i32i8imm :$src),
1219 "and{l}\t{$src, $dst|$dst, $src}",
1220 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1224 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1225 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1226 "or{b}\t{$src2, $dst|$dst, $src2}",
1227 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
1228 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1229 "or{w}\t{$src2, $dst|$dst, $src2}",
1230 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize;
1231 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1232 "or{l}\t{$src2, $dst|$dst, $src2}",
1233 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
1235 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1236 "or{b}\t{$src2, $dst|$dst, $src2}",
1237 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
1238 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1239 "or{w}\t{$src2, $dst|$dst, $src2}",
1240 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize;
1241 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1242 "or{l}\t{$src2, $dst|$dst, $src2}",
1243 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>;
1245 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1246 "or{b}\t{$src2, $dst|$dst, $src2}",
1247 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
1248 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1249 "or{w}\t{$src2, $dst|$dst, $src2}",
1250 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize;
1251 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1252 "or{l}\t{$src2, $dst|$dst, $src2}",
1253 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
1255 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1256 "or{w}\t{$src2, $dst|$dst, $src2}",
1257 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1258 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1259 "or{l}\t{$src2, $dst|$dst, $src2}",
1260 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>;
1261 let isTwoAddress = 0 in {
1262 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1263 "or{b}\t{$src, $dst|$dst, $src}",
1264 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
1265 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1266 "or{w}\t{$src, $dst|$dst, $src}",
1267 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize;
1268 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1269 "or{l}\t{$src, $dst|$dst, $src}",
1270 [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>;
1271 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1272 "or{b}\t{$src, $dst|$dst, $src}",
1273 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1274 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1275 "or{w}\t{$src, $dst|$dst, $src}",
1276 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1278 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1279 "or{l}\t{$src, $dst|$dst, $src}",
1280 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1281 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1282 "or{w}\t{$src, $dst|$dst, $src}",
1283 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1285 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1286 "or{l}\t{$src, $dst|$dst, $src}",
1287 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1291 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1292 def XOR8rr : I<0x30, MRMDestReg,
1293 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1294 "xor{b}\t{$src2, $dst|$dst, $src2}",
1295 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>;
1296 def XOR16rr : I<0x31, MRMDestReg,
1297 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1298 "xor{w}\t{$src2, $dst|$dst, $src2}",
1299 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize;
1300 def XOR32rr : I<0x31, MRMDestReg,
1301 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1302 "xor{l}\t{$src2, $dst|$dst, $src2}",
1303 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
1306 def XOR8rm : I<0x32, MRMSrcMem ,
1307 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1308 "xor{b}\t{$src2, $dst|$dst, $src2}",
1309 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>;
1310 def XOR16rm : I<0x33, MRMSrcMem ,
1311 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1312 "xor{w}\t{$src2, $dst|$dst, $src2}",
1313 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>, OpSize;
1314 def XOR32rm : I<0x33, MRMSrcMem ,
1315 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1316 "xor{l}\t{$src2, $dst|$dst, $src2}",
1317 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>;
1319 def XOR8ri : Ii8<0x80, MRM6r,
1320 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1321 "xor{b}\t{$src2, $dst|$dst, $src2}",
1322 [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>;
1323 def XOR16ri : Ii16<0x81, MRM6r,
1324 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1325 "xor{w}\t{$src2, $dst|$dst, $src2}",
1326 [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize;
1327 def XOR32ri : Ii32<0x81, MRM6r,
1328 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1329 "xor{l}\t{$src2, $dst|$dst, $src2}",
1330 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
1331 def XOR16ri8 : Ii8<0x83, MRM6r,
1332 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1333 "xor{w}\t{$src2, $dst|$dst, $src2}",
1334 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>,
1336 def XOR32ri8 : Ii8<0x83, MRM6r,
1337 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1338 "xor{l}\t{$src2, $dst|$dst, $src2}",
1339 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>;
1340 let isTwoAddress = 0 in {
1341 def XOR8mr : I<0x30, MRMDestMem,
1342 (outs), (ins i8mem :$dst, GR8 :$src),
1343 "xor{b}\t{$src, $dst|$dst, $src}",
1344 [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>;
1345 def XOR16mr : I<0x31, MRMDestMem,
1346 (outs), (ins i16mem:$dst, GR16:$src),
1347 "xor{w}\t{$src, $dst|$dst, $src}",
1348 [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>,
1350 def XOR32mr : I<0x31, MRMDestMem,
1351 (outs), (ins i32mem:$dst, GR32:$src),
1352 "xor{l}\t{$src, $dst|$dst, $src}",
1353 [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>;
1354 def XOR8mi : Ii8<0x80, MRM6m,
1355 (outs), (ins i8mem :$dst, i8imm :$src),
1356 "xor{b}\t{$src, $dst|$dst, $src}",
1357 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1358 def XOR16mi : Ii16<0x81, MRM6m,
1359 (outs), (ins i16mem:$dst, i16imm:$src),
1360 "xor{w}\t{$src, $dst|$dst, $src}",
1361 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1363 def XOR32mi : Ii32<0x81, MRM6m,
1364 (outs), (ins i32mem:$dst, i32imm:$src),
1365 "xor{l}\t{$src, $dst|$dst, $src}",
1366 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1367 def XOR16mi8 : Ii8<0x83, MRM6m,
1368 (outs), (ins i16mem:$dst, i16i8imm :$src),
1369 "xor{w}\t{$src, $dst|$dst, $src}",
1370 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1372 def XOR32mi8 : Ii8<0x83, MRM6m,
1373 (outs), (ins i32mem:$dst, i32i8imm :$src),
1374 "xor{l}\t{$src, $dst|$dst, $src}",
1375 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1377 } // Defs = [EFLAGS]
1379 // Shift instructions
1380 let Defs = [EFLAGS] in {
1381 let Uses = [CL] in {
1382 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1383 "shl{b}\t{%cl, $dst|$dst, %CL}",
1384 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1385 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1386 "shl{w}\t{%cl, $dst|$dst, %CL}",
1387 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1388 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1389 "shl{l}\t{%cl, $dst|$dst, %CL}",
1390 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1393 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1394 "shl{b}\t{$src2, $dst|$dst, $src2}",
1395 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1396 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1397 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1398 "shl{w}\t{$src2, $dst|$dst, $src2}",
1399 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1400 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1401 "shl{l}\t{$src2, $dst|$dst, $src2}",
1402 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1405 // Shift left by one. Not used because (add x, x) is slightly cheaper.
1406 def SHL8r1 : I<0xD0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
1407 "shl{b}\t$dst", []>;
1408 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
1409 "shl{w}\t$dst", []>, OpSize;
1410 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
1411 "shl{l}\t$dst", []>;
1413 let isTwoAddress = 0 in {
1414 let Uses = [CL] in {
1415 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1416 "shl{b}\t{%cl, $dst|$dst, %CL}",
1417 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1418 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1419 "shl{w}\t{%cl, $dst|$dst, %CL}",
1420 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1421 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1422 "shl{l}\t{%cl, $dst|$dst, %CL}",
1423 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1425 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1426 "shl{b}\t{$src, $dst|$dst, $src}",
1427 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1428 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1429 "shl{w}\t{$src, $dst|$dst, $src}",
1430 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1432 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1433 "shl{l}\t{$src, $dst|$dst, $src}",
1434 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1437 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1439 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1440 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1442 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1444 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1446 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1449 let Uses = [CL] in {
1450 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1451 "shr{b}\t{%cl, $dst|$dst, %CL}",
1452 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1453 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1454 "shr{w}\t{%cl, $dst|$dst, %CL}",
1455 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1456 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1457 "shr{l}\t{%cl, $dst|$dst, %CL}",
1458 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1461 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1462 "shr{b}\t{$src2, $dst|$dst, $src2}",
1463 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1464 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1465 "shr{w}\t{$src2, $dst|$dst, $src2}",
1466 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1467 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1468 "shr{l}\t{$src2, $dst|$dst, $src2}",
1469 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1472 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1474 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1475 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1477 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1478 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1480 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1482 let isTwoAddress = 0 in {
1483 let Uses = [CL] in {
1484 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1485 "shr{b}\t{%cl, $dst|$dst, %CL}",
1486 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1487 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1488 "shr{w}\t{%cl, $dst|$dst, %CL}",
1489 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1491 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1492 "shr{l}\t{%cl, $dst|$dst, %CL}",
1493 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1495 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1496 "shr{b}\t{$src, $dst|$dst, $src}",
1497 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1498 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1499 "shr{w}\t{$src, $dst|$dst, $src}",
1500 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1502 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1503 "shr{l}\t{$src, $dst|$dst, $src}",
1504 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1507 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1509 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1510 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1512 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1513 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1515 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1518 let Uses = [CL] in {
1519 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1520 "sar{b}\t{%cl, $dst|$dst, %CL}",
1521 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1522 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1523 "sar{w}\t{%cl, $dst|$dst, %CL}",
1524 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1525 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1526 "sar{l}\t{%cl, $dst|$dst, %CL}",
1527 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1530 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1531 "sar{b}\t{$src2, $dst|$dst, $src2}",
1532 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1533 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1534 "sar{w}\t{$src2, $dst|$dst, $src2}",
1535 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1537 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1538 "sar{l}\t{$src2, $dst|$dst, $src2}",
1539 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1542 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1544 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1545 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1547 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1548 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1550 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1552 let isTwoAddress = 0 in {
1553 let Uses = [CL] in {
1554 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1555 "sar{b}\t{%cl, $dst|$dst, %CL}",
1556 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
1557 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1558 "sar{w}\t{%cl, $dst|$dst, %CL}",
1559 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1560 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1561 "sar{l}\t{%cl, $dst|$dst, %CL}",
1562 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1564 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1565 "sar{b}\t{$src, $dst|$dst, $src}",
1566 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1567 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1568 "sar{w}\t{$src, $dst|$dst, $src}",
1569 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1571 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1572 "sar{l}\t{$src, $dst|$dst, $src}",
1573 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1576 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1578 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1579 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1581 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1583 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
1585 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1588 // Rotate instructions
1589 // FIXME: provide shorter instructions when imm8 == 1
1590 let Uses = [CL] in {
1591 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
1592 "rol{b}\t{%cl, $dst|$dst, %CL}",
1593 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
1594 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
1595 "rol{w}\t{%cl, $dst|$dst, %CL}",
1596 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
1597 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
1598 "rol{l}\t{%cl, $dst|$dst, %CL}",
1599 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
1602 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1603 "rol{b}\t{$src2, $dst|$dst, $src2}",
1604 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1605 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1606 "rol{w}\t{$src2, $dst|$dst, $src2}",
1607 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1608 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1609 "rol{l}\t{$src2, $dst|$dst, $src2}",
1610 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1613 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1615 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1616 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
1618 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1619 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1621 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1623 let isTwoAddress = 0 in {
1624 let Uses = [CL] in {
1625 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
1626 "rol{b}\t{%cl, $dst|$dst, %CL}",
1627 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
1628 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
1629 "rol{w}\t{%cl, $dst|$dst, %CL}",
1630 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1631 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
1632 "rol{l}\t{%cl, $dst|$dst, %CL}",
1633 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
1635 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
1636 "rol{b}\t{$src, $dst|$dst, $src}",
1637 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1638 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
1639 "rol{w}\t{$src, $dst|$dst, $src}",
1640 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1642 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
1643 "rol{l}\t{$src, $dst|$dst, $src}",
1644 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1647 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
1649 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1650 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
1652 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1654 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
1656 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1659 let Uses = [CL] in {
1660 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
1661 "ror{b}\t{%cl, $dst|$dst, %CL}",
1662 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
1663 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
1664 "ror{w}\t{%cl, $dst|$dst, %CL}",
1665 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
1666 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
1667 "ror{l}\t{%cl, $dst|$dst, %CL}",
1668 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
1671 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1672 "ror{b}\t{$src2, $dst|$dst, $src2}",
1673 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
1674 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1675 "ror{w}\t{$src2, $dst|$dst, $src2}",
1676 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1677 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1678 "ror{l}\t{$src2, $dst|$dst, $src2}",
1679 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
1682 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1684 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
1685 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
1687 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
1688 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
1690 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
1692 let isTwoAddress = 0 in {
1693 let Uses = [CL] in {
1694 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
1695 "ror{b}\t{%cl, $dst|$dst, %CL}",
1696 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
1697 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
1698 "ror{w}\t{%cl, $dst|$dst, %CL}",
1699 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1700 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
1701 "ror{l}\t{%cl, $dst|$dst, %CL}",
1702 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
1704 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1705 "ror{b}\t{$src, $dst|$dst, $src}",
1706 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1707 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
1708 "ror{w}\t{$src, $dst|$dst, $src}",
1709 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1711 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
1712 "ror{l}\t{$src, $dst|$dst, $src}",
1713 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1716 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
1718 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1719 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
1721 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1723 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
1725 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1730 // Double shift instructions (generalizations of rotate)
1731 let Uses = [CL] in {
1732 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1733 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1734 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
1735 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1736 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1737 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
1738 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1739 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1740 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
1742 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1743 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1744 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
1748 let isCommutable = 1 in { // These instructions commute to each other.
1749 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
1750 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1751 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1752 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
1755 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
1756 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1757 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1758 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
1761 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
1762 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1763 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1764 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
1767 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
1768 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1769 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1770 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
1775 let isTwoAddress = 0 in {
1776 let Uses = [CL] in {
1777 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1778 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1779 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
1781 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1782 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1783 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
1786 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
1787 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1788 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1789 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
1790 (i8 imm:$src3)), addr:$dst)]>,
1792 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
1793 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1794 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1795 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
1796 (i8 imm:$src3)), addr:$dst)]>,
1799 let Uses = [CL] in {
1800 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1801 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1802 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
1803 addr:$dst)]>, TB, OpSize;
1804 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1805 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1806 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
1807 addr:$dst)]>, TB, OpSize;
1809 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
1810 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1811 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1812 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
1813 (i8 imm:$src3)), addr:$dst)]>,
1815 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
1816 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1817 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1818 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
1819 (i8 imm:$src3)), addr:$dst)]>,
1822 } // Defs = [EFLAGS]
1826 let Defs = [EFLAGS] in {
1827 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1828 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
1829 (ins GR8 :$src1, GR8 :$src2),
1830 "add{b}\t{$src2, $dst|$dst, $src2}",
1831 [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>;
1832 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1833 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
1834 (ins GR16:$src1, GR16:$src2),
1835 "add{w}\t{$src2, $dst|$dst, $src2}",
1836 [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize;
1837 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
1838 (ins GR32:$src1, GR32:$src2),
1839 "add{l}\t{$src2, $dst|$dst, $src2}",
1840 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
1841 } // end isConvertibleToThreeAddress
1842 } // end isCommutable
1843 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
1844 (ins GR8 :$src1, i8mem :$src2),
1845 "add{b}\t{$src2, $dst|$dst, $src2}",
1846 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>;
1847 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
1848 (ins GR16:$src1, i16mem:$src2),
1849 "add{w}\t{$src2, $dst|$dst, $src2}",
1850 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>,OpSize;
1851 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
1852 (ins GR32:$src1, i32mem:$src2),
1853 "add{l}\t{$src2, $dst|$dst, $src2}",
1854 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>;
1856 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1857 "add{b}\t{$src2, $dst|$dst, $src2}",
1858 [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>;
1860 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1861 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
1862 (ins GR16:$src1, i16imm:$src2),
1863 "add{w}\t{$src2, $dst|$dst, $src2}",
1864 [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize;
1865 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
1866 (ins GR32:$src1, i32imm:$src2),
1867 "add{l}\t{$src2, $dst|$dst, $src2}",
1868 [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>;
1869 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
1870 (ins GR16:$src1, i16i8imm:$src2),
1871 "add{w}\t{$src2, $dst|$dst, $src2}",
1872 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1873 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
1874 (ins GR32:$src1, i32i8imm:$src2),
1875 "add{l}\t{$src2, $dst|$dst, $src2}",
1876 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>;
1879 let isTwoAddress = 0 in {
1880 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1881 "add{b}\t{$src2, $dst|$dst, $src2}",
1882 [(store (add (load addr:$dst), GR8:$src2), addr:$dst)]>;
1883 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1884 "add{w}\t{$src2, $dst|$dst, $src2}",
1885 [(store (add (load addr:$dst), GR16:$src2), addr:$dst)]>,
1887 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1888 "add{l}\t{$src2, $dst|$dst, $src2}",
1889 [(store (add (load addr:$dst), GR32:$src2), addr:$dst)]>;
1890 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
1891 "add{b}\t{$src2, $dst|$dst, $src2}",
1892 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1893 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
1894 "add{w}\t{$src2, $dst|$dst, $src2}",
1895 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1897 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
1898 "add{l}\t{$src2, $dst|$dst, $src2}",
1899 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1900 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1901 "add{w}\t{$src2, $dst|$dst, $src2}",
1902 [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1904 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1905 "add{l}\t{$src2, $dst|$dst, $src2}",
1906 [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1909 let Uses = [EFLAGS] in {
1910 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1911 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1912 "adc{l}\t{$src2, $dst|$dst, $src2}",
1913 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
1915 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1916 "adc{l}\t{$src2, $dst|$dst, $src2}",
1917 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
1918 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1919 "adc{l}\t{$src2, $dst|$dst, $src2}",
1920 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
1921 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1922 "adc{l}\t{$src2, $dst|$dst, $src2}",
1923 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
1925 let isTwoAddress = 0 in {
1926 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1927 "adc{l}\t{$src2, $dst|$dst, $src2}",
1928 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
1929 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
1930 "adc{l}\t{$src2, $dst|$dst, $src2}",
1931 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1932 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1933 "adc{l}\t{$src2, $dst|$dst, $src2}",
1934 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1936 } // Uses = [EFLAGS]
1938 def SUB8rr : I<0x28, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1939 "sub{b}\t{$src2, $dst|$dst, $src2}",
1940 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2))]>;
1941 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1942 "sub{w}\t{$src2, $dst|$dst, $src2}",
1943 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2))]>, OpSize;
1944 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1945 "sub{l}\t{$src2, $dst|$dst, $src2}",
1946 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
1947 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1948 "sub{b}\t{$src2, $dst|$dst, $src2}",
1949 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2)))]>;
1950 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1951 "sub{w}\t{$src2, $dst|$dst, $src2}",
1952 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2)))]>, OpSize;
1953 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1954 "sub{l}\t{$src2, $dst|$dst, $src2}",
1955 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2)))]>;
1957 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1958 "sub{b}\t{$src2, $dst|$dst, $src2}",
1959 [(set GR8:$dst, (sub GR8:$src1, imm:$src2))]>;
1960 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1961 "sub{w}\t{$src2, $dst|$dst, $src2}",
1962 [(set GR16:$dst, (sub GR16:$src1, imm:$src2))]>, OpSize;
1963 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1964 "sub{l}\t{$src2, $dst|$dst, $src2}",
1965 [(set GR32:$dst, (sub GR32:$src1, imm:$src2))]>;
1966 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1967 "sub{w}\t{$src2, $dst|$dst, $src2}",
1968 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2))]>,
1970 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1971 "sub{l}\t{$src2, $dst|$dst, $src2}",
1972 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2))]>;
1973 let isTwoAddress = 0 in {
1974 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1975 "sub{b}\t{$src2, $dst|$dst, $src2}",
1976 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst)]>;
1977 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1978 "sub{w}\t{$src2, $dst|$dst, $src2}",
1979 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst)]>,
1981 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1982 "sub{l}\t{$src2, $dst|$dst, $src2}",
1983 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst)]>;
1984 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
1985 "sub{b}\t{$src2, $dst|$dst, $src2}",
1986 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1987 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
1988 "sub{w}\t{$src2, $dst|$dst, $src2}",
1989 [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1991 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
1992 "sub{l}\t{$src2, $dst|$dst, $src2}",
1993 [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1994 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1995 "sub{w}\t{$src2, $dst|$dst, $src2}",
1996 [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1998 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1999 "sub{l}\t{$src2, $dst|$dst, $src2}",
2000 [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2003 let Uses = [EFLAGS] in {
2004 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2005 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2006 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2008 let isTwoAddress = 0 in {
2009 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2010 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2011 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2012 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2013 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2014 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2015 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2016 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2017 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2018 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2019 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2020 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2022 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2023 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2024 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2025 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2026 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2027 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2028 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2029 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2030 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2031 } // Uses = [EFLAGS]
2032 } // Defs = [EFLAGS]
2034 let Defs = [EFLAGS] in {
2035 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2036 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2037 "imul{w}\t{$src2, $dst|$dst, $src2}",
2038 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2))]>, TB, OpSize;
2039 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2040 "imul{l}\t{$src2, $dst|$dst, $src2}",
2041 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>, TB;
2043 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2044 "imul{w}\t{$src2, $dst|$dst, $src2}",
2045 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2)))]>,
2047 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2048 "imul{l}\t{$src2, $dst|$dst, $src2}",
2049 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2)))]>, TB;
2050 } // Defs = [EFLAGS]
2051 } // end Two Address instructions
2053 // Suprisingly enough, these are not two address instructions!
2054 let Defs = [EFLAGS] in {
2055 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2056 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2057 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2058 [(set GR16:$dst, (mul GR16:$src1, imm:$src2))]>, OpSize;
2059 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2060 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2061 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2062 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
2063 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2064 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2065 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2066 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2))]>,
2068 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2069 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2070 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2071 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2))]>;
2073 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2074 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2075 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2076 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2))]>,
2078 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2079 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2080 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2081 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2))]>;
2082 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2083 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2084 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2085 [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>,
2087 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2088 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2089 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2090 [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>;
2091 } // Defs = [EFLAGS]
2093 //===----------------------------------------------------------------------===//
2094 // Test instructions are just like AND, except they don't generate a result.
2096 let Defs = [EFLAGS] in {
2097 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2098 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2099 "test{b}\t{$src2, $src1|$src1, $src2}",
2100 [(X86cmp (and GR8:$src1, GR8:$src2), 0),
2101 (implicit EFLAGS)]>;
2102 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2103 "test{w}\t{$src2, $src1|$src1, $src2}",
2104 [(X86cmp (and GR16:$src1, GR16:$src2), 0),
2105 (implicit EFLAGS)]>,
2107 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2108 "test{l}\t{$src2, $src1|$src1, $src2}",
2109 [(X86cmp (and GR32:$src1, GR32:$src2), 0),
2110 (implicit EFLAGS)]>;
2113 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2114 "test{b}\t{$src2, $src1|$src1, $src2}",
2115 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2116 (implicit EFLAGS)]>;
2117 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2118 "test{w}\t{$src2, $src1|$src1, $src2}",
2119 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2120 (implicit EFLAGS)]>, OpSize;
2121 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2122 "test{l}\t{$src2, $src1|$src1, $src2}",
2123 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2124 (implicit EFLAGS)]>;
2126 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2127 (outs), (ins GR8:$src1, i8imm:$src2),
2128 "test{b}\t{$src2, $src1|$src1, $src2}",
2129 [(X86cmp (and GR8:$src1, imm:$src2), 0),
2130 (implicit EFLAGS)]>;
2131 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2132 (outs), (ins GR16:$src1, i16imm:$src2),
2133 "test{w}\t{$src2, $src1|$src1, $src2}",
2134 [(X86cmp (and GR16:$src1, imm:$src2), 0),
2135 (implicit EFLAGS)]>, OpSize;
2136 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2137 (outs), (ins GR32:$src1, i32imm:$src2),
2138 "test{l}\t{$src2, $src1|$src1, $src2}",
2139 [(X86cmp (and GR32:$src1, imm:$src2), 0),
2140 (implicit EFLAGS)]>;
2142 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2143 (outs), (ins i8mem:$src1, i8imm:$src2),
2144 "test{b}\t{$src2, $src1|$src1, $src2}",
2145 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2146 (implicit EFLAGS)]>;
2147 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2148 (outs), (ins i16mem:$src1, i16imm:$src2),
2149 "test{w}\t{$src2, $src1|$src1, $src2}",
2150 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2151 (implicit EFLAGS)]>, OpSize;
2152 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2153 (outs), (ins i32mem:$src1, i32imm:$src2),
2154 "test{l}\t{$src2, $src1|$src1, $src2}",
2155 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2156 (implicit EFLAGS)]>;
2157 } // Defs = [EFLAGS]
2160 // Condition code ops, incl. set if equal/not equal/...
2161 let Defs = [EFLAGS], Uses = [AH] in
2162 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2163 let Defs = [AH], Uses = [EFLAGS] in
2164 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2166 let Uses = [EFLAGS] in {
2167 def SETEr : I<0x94, MRM0r,
2168 (outs GR8 :$dst), (ins),
2170 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2172 def SETEm : I<0x94, MRM0m,
2173 (outs), (ins i8mem:$dst),
2175 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2177 def SETNEr : I<0x95, MRM0r,
2178 (outs GR8 :$dst), (ins),
2180 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2182 def SETNEm : I<0x95, MRM0m,
2183 (outs), (ins i8mem:$dst),
2185 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2187 def SETLr : I<0x9C, MRM0r,
2188 (outs GR8 :$dst), (ins),
2190 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2191 TB; // GR8 = < signed
2192 def SETLm : I<0x9C, MRM0m,
2193 (outs), (ins i8mem:$dst),
2195 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2196 TB; // [mem8] = < signed
2197 def SETGEr : I<0x9D, MRM0r,
2198 (outs GR8 :$dst), (ins),
2200 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2201 TB; // GR8 = >= signed
2202 def SETGEm : I<0x9D, MRM0m,
2203 (outs), (ins i8mem:$dst),
2205 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2206 TB; // [mem8] = >= signed
2207 def SETLEr : I<0x9E, MRM0r,
2208 (outs GR8 :$dst), (ins),
2210 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2211 TB; // GR8 = <= signed
2212 def SETLEm : I<0x9E, MRM0m,
2213 (outs), (ins i8mem:$dst),
2215 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2216 TB; // [mem8] = <= signed
2217 def SETGr : I<0x9F, MRM0r,
2218 (outs GR8 :$dst), (ins),
2220 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2221 TB; // GR8 = > signed
2222 def SETGm : I<0x9F, MRM0m,
2223 (outs), (ins i8mem:$dst),
2225 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2226 TB; // [mem8] = > signed
2228 def SETBr : I<0x92, MRM0r,
2229 (outs GR8 :$dst), (ins),
2231 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2232 TB; // GR8 = < unsign
2233 def SETBm : I<0x92, MRM0m,
2234 (outs), (ins i8mem:$dst),
2236 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
2237 TB; // [mem8] = < unsign
2238 def SETAEr : I<0x93, MRM0r,
2239 (outs GR8 :$dst), (ins),
2241 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
2242 TB; // GR8 = >= unsign
2243 def SETAEm : I<0x93, MRM0m,
2244 (outs), (ins i8mem:$dst),
2246 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
2247 TB; // [mem8] = >= unsign
2248 def SETBEr : I<0x96, MRM0r,
2249 (outs GR8 :$dst), (ins),
2251 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
2252 TB; // GR8 = <= unsign
2253 def SETBEm : I<0x96, MRM0m,
2254 (outs), (ins i8mem:$dst),
2256 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
2257 TB; // [mem8] = <= unsign
2258 def SETAr : I<0x97, MRM0r,
2259 (outs GR8 :$dst), (ins),
2261 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
2262 TB; // GR8 = > signed
2263 def SETAm : I<0x97, MRM0m,
2264 (outs), (ins i8mem:$dst),
2266 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
2267 TB; // [mem8] = > signed
2269 def SETSr : I<0x98, MRM0r,
2270 (outs GR8 :$dst), (ins),
2272 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
2273 TB; // GR8 = <sign bit>
2274 def SETSm : I<0x98, MRM0m,
2275 (outs), (ins i8mem:$dst),
2277 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
2278 TB; // [mem8] = <sign bit>
2279 def SETNSr : I<0x99, MRM0r,
2280 (outs GR8 :$dst), (ins),
2282 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
2283 TB; // GR8 = !<sign bit>
2284 def SETNSm : I<0x99, MRM0m,
2285 (outs), (ins i8mem:$dst),
2287 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
2288 TB; // [mem8] = !<sign bit>
2289 def SETPr : I<0x9A, MRM0r,
2290 (outs GR8 :$dst), (ins),
2292 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
2294 def SETPm : I<0x9A, MRM0m,
2295 (outs), (ins i8mem:$dst),
2297 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
2298 TB; // [mem8] = parity
2299 def SETNPr : I<0x9B, MRM0r,
2300 (outs GR8 :$dst), (ins),
2302 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
2303 TB; // GR8 = not parity
2304 def SETNPm : I<0x9B, MRM0m,
2305 (outs), (ins i8mem:$dst),
2307 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
2308 TB; // [mem8] = not parity
2309 } // Uses = [EFLAGS]
2312 // Integer comparisons
2313 let Defs = [EFLAGS] in {
2314 def CMP8rr : I<0x38, MRMDestReg,
2315 (outs), (ins GR8 :$src1, GR8 :$src2),
2316 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2317 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2318 def CMP16rr : I<0x39, MRMDestReg,
2319 (outs), (ins GR16:$src1, GR16:$src2),
2320 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2321 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
2322 def CMP32rr : I<0x39, MRMDestReg,
2323 (outs), (ins GR32:$src1, GR32:$src2),
2324 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2325 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
2326 def CMP8mr : I<0x38, MRMDestMem,
2327 (outs), (ins i8mem :$src1, GR8 :$src2),
2328 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2329 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
2330 (implicit EFLAGS)]>;
2331 def CMP16mr : I<0x39, MRMDestMem,
2332 (outs), (ins i16mem:$src1, GR16:$src2),
2333 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2334 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
2335 (implicit EFLAGS)]>, OpSize;
2336 def CMP32mr : I<0x39, MRMDestMem,
2337 (outs), (ins i32mem:$src1, GR32:$src2),
2338 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2339 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
2340 (implicit EFLAGS)]>;
2341 def CMP8rm : I<0x3A, MRMSrcMem,
2342 (outs), (ins GR8 :$src1, i8mem :$src2),
2343 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2344 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
2345 (implicit EFLAGS)]>;
2346 def CMP16rm : I<0x3B, MRMSrcMem,
2347 (outs), (ins GR16:$src1, i16mem:$src2),
2348 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2349 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
2350 (implicit EFLAGS)]>, OpSize;
2351 def CMP32rm : I<0x3B, MRMSrcMem,
2352 (outs), (ins GR32:$src1, i32mem:$src2),
2353 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2354 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
2355 (implicit EFLAGS)]>;
2356 def CMP8ri : Ii8<0x80, MRM7r,
2357 (outs), (ins GR8:$src1, i8imm:$src2),
2358 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2359 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
2360 def CMP16ri : Ii16<0x81, MRM7r,
2361 (outs), (ins GR16:$src1, i16imm:$src2),
2362 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2363 [(X86cmp GR16:$src1, imm:$src2),
2364 (implicit EFLAGS)]>, OpSize;
2365 def CMP32ri : Ii32<0x81, MRM7r,
2366 (outs), (ins GR32:$src1, i32imm:$src2),
2367 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2368 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
2369 def CMP8mi : Ii8 <0x80, MRM7m,
2370 (outs), (ins i8mem :$src1, i8imm :$src2),
2371 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2372 [(X86cmp (loadi8 addr:$src1), imm:$src2),
2373 (implicit EFLAGS)]>;
2374 def CMP16mi : Ii16<0x81, MRM7m,
2375 (outs), (ins i16mem:$src1, i16imm:$src2),
2376 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2377 [(X86cmp (loadi16 addr:$src1), imm:$src2),
2378 (implicit EFLAGS)]>, OpSize;
2379 def CMP32mi : Ii32<0x81, MRM7m,
2380 (outs), (ins i32mem:$src1, i32imm:$src2),
2381 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2382 [(X86cmp (loadi32 addr:$src1), imm:$src2),
2383 (implicit EFLAGS)]>;
2384 def CMP16ri8 : Ii8<0x83, MRM7r,
2385 (outs), (ins GR16:$src1, i16i8imm:$src2),
2386 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2387 [(X86cmp GR16:$src1, i16immSExt8:$src2),
2388 (implicit EFLAGS)]>, OpSize;
2389 def CMP16mi8 : Ii8<0x83, MRM7m,
2390 (outs), (ins i16mem:$src1, i16i8imm:$src2),
2391 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2392 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
2393 (implicit EFLAGS)]>, OpSize;
2394 def CMP32mi8 : Ii8<0x83, MRM7m,
2395 (outs), (ins i32mem:$src1, i32i8imm:$src2),
2396 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2397 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
2398 (implicit EFLAGS)]>;
2399 def CMP32ri8 : Ii8<0x83, MRM7r,
2400 (outs), (ins GR32:$src1, i32i8imm:$src2),
2401 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2402 [(X86cmp GR32:$src1, i32immSExt8:$src2),
2403 (implicit EFLAGS)]>;
2404 } // Defs = [EFLAGS]
2406 // Sign/Zero extenders
2407 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2408 "movs{bw|x}\t{$src, $dst|$dst, $src}",
2409 [(set GR16:$dst, (sext GR8:$src))]>, TB, OpSize;
2410 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2411 "movs{bw|x}\t{$src, $dst|$dst, $src}",
2412 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize;
2413 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2414 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2415 [(set GR32:$dst, (sext GR8:$src))]>, TB;
2416 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2417 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2418 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
2419 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2420 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2421 [(set GR32:$dst, (sext GR16:$src))]>, TB;
2422 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2423 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2424 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
2426 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2427 "movz{bw|x}\t{$src, $dst|$dst, $src}",
2428 [(set GR16:$dst, (zext GR8:$src))]>, TB, OpSize;
2429 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2430 "movz{bw|x}\t{$src, $dst|$dst, $src}",
2431 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize;
2432 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2433 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2434 [(set GR32:$dst, (zext GR8:$src))]>, TB;
2435 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2436 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2437 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
2438 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2439 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2440 [(set GR32:$dst, (zext GR16:$src))]>, TB;
2441 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2442 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2443 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
2445 let Defs = [AX], Uses = [AL] in
2446 def CBW : I<0x98, RawFrm, (outs), (ins),
2447 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
2448 let Defs = [EAX], Uses = [AX] in
2449 def CWDE : I<0x98, RawFrm, (outs), (ins),
2450 "{cwtl|cwde}", []>; // EAX = signext(AX)
2452 let Defs = [AX,DX], Uses = [AX] in
2453 def CWD : I<0x99, RawFrm, (outs), (ins),
2454 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
2455 let Defs = [EAX,EDX], Uses = [EAX] in
2456 def CDQ : I<0x99, RawFrm, (outs), (ins),
2457 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
2460 //===----------------------------------------------------------------------===//
2461 // Alias Instructions
2462 //===----------------------------------------------------------------------===//
2464 // Alias instructions that map movr0 to xor.
2465 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2466 let Defs = [EFLAGS], isReMaterializable = 1, neverHasSideEffects = 1 in {
2467 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
2468 "xor{b}\t$dst, $dst",
2469 [(set GR8:$dst, 0)]>;
2470 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
2471 "xor{w}\t$dst, $dst",
2472 [(set GR16:$dst, 0)]>, OpSize;
2473 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
2474 "xor{l}\t$dst, $dst",
2475 [(set GR32:$dst, 0)]>;
2478 // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
2479 // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
2480 def MOV16to16_ : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16:$src),
2481 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2482 def MOV32to32_ : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32:$src),
2483 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2485 def MOV16_rr : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16_:$src),
2486 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2487 def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src),
2488 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2489 let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
2490 def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src),
2491 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2492 def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src),
2493 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2495 def MOV16_mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16_:$src),
2496 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2497 def MOV32_mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32_:$src),
2498 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2500 //===----------------------------------------------------------------------===//
2501 // Thread Local Storage Instructions
2505 def TLS_addr : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
2506 "leal\t${sym:mem}(,%ebx,1), $dst",
2507 [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
2509 let AddedComplexity = 10 in
2510 def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
2511 "movl\t%gs:($src), $dst",
2512 [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
2514 let AddedComplexity = 15 in
2515 def TLS_gs_ri : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
2516 "movl\t%gs:${src:mem}, $dst",
2518 (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>;
2520 def TLS_tp : I<0, Pseudo, (outs GR32:$dst), (ins),
2521 "movl\t%gs:0, $dst",
2522 [(set GR32:$dst, X86TLStp)]>;
2524 //===----------------------------------------------------------------------===//
2525 // DWARF Pseudo Instructions
2528 def DWARF_LOC : I<0, Pseudo, (outs),
2529 (ins i32imm:$line, i32imm:$col, i32imm:$file),
2530 ".loc\t${file:debug} ${line:debug} ${col:debug}",
2531 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
2534 //===----------------------------------------------------------------------===//
2535 // EH Pseudo Instructions
2537 let isTerminator = 1, isReturn = 1, isBarrier = 1,
2539 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
2540 "ret\t#eh_return, addr: $addr",
2541 [(X86ehret GR32:$addr)]>;
2545 //===----------------------------------------------------------------------===//
2546 // Non-Instruction Patterns
2547 //===----------------------------------------------------------------------===//
2549 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
2550 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
2551 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
2552 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)), (MOV32ri tglobaltlsaddr:$dst)>;
2553 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
2554 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
2556 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
2557 (ADD32ri GR32:$src1, tconstpool:$src2)>;
2558 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
2559 (ADD32ri GR32:$src1, tjumptable:$src2)>;
2560 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
2561 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
2562 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
2563 (ADD32ri GR32:$src1, texternalsym:$src2)>;
2565 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
2566 (MOV32mi addr:$dst, tglobaladdr:$src)>;
2567 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
2568 (MOV32mi addr:$dst, texternalsym:$src)>;
2572 def : Pat<(X86tailcall GR32:$dst),
2575 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
2577 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
2580 def : Pat<(X86tcret GR32:$dst, imm:$off),
2581 (TCRETURNri GR32:$dst, imm:$off)>;
2583 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
2584 (TCRETURNdi texternalsym:$dst, imm:$off)>;
2586 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
2587 (TCRETURNdi texternalsym:$dst, imm:$off)>;
2589 def : Pat<(X86call (i32 tglobaladdr:$dst)),
2590 (CALLpcrel32 tglobaladdr:$dst)>;
2591 def : Pat<(X86call (i32 texternalsym:$dst)),
2592 (CALLpcrel32 texternalsym:$dst)>;
2594 // X86 specific add which produces a flag.
2595 def : Pat<(addc GR32:$src1, GR32:$src2),
2596 (ADD32rr GR32:$src1, GR32:$src2)>;
2597 def : Pat<(addc GR32:$src1, (load addr:$src2)),
2598 (ADD32rm GR32:$src1, addr:$src2)>;
2599 def : Pat<(addc GR32:$src1, imm:$src2),
2600 (ADD32ri GR32:$src1, imm:$src2)>;
2601 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
2602 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
2604 def : Pat<(subc GR32:$src1, GR32:$src2),
2605 (SUB32rr GR32:$src1, GR32:$src2)>;
2606 def : Pat<(subc GR32:$src1, (load addr:$src2)),
2607 (SUB32rm GR32:$src1, addr:$src2)>;
2608 def : Pat<(subc GR32:$src1, imm:$src2),
2609 (SUB32ri GR32:$src1, imm:$src2)>;
2610 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
2611 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
2613 def : Pat<(truncstorei1 (i8 imm:$src), addr:$dst),
2614 (MOV8mi addr:$dst, imm:$src)>;
2615 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
2616 (MOV8mr addr:$dst, GR8:$src)>;
2620 // TEST R,R is smaller than CMP R,0
2621 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
2622 (TEST8rr GR8:$src1, GR8:$src1)>;
2623 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
2624 (TEST16rr GR16:$src1, GR16:$src1)>;
2625 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
2626 (TEST32rr GR32:$src1, GR32:$src1)>;
2628 // {s|z}extload bool -> {s|z}extload byte
2629 def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>;
2630 def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>;
2631 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2632 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2633 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2635 // extload bool -> extload byte
2636 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2637 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2638 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2639 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
2640 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
2641 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
2644 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
2645 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
2646 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
2647 def : Pat<(i16 (anyext (loadi8 addr:$src))), (MOVZX16rm8 addr:$src)>;
2648 def : Pat<(i32 (anyext (loadi8 addr:$src))), (MOVZX32rm8 addr:$src)>;
2649 def : Pat<(i32 (anyext (loadi16 addr:$src))), (MOVZX32rm16 addr:$src)>;
2651 // (and (i32 load), 255) -> (zextload i8)
2652 def : Pat<(i32 (and (loadi32 addr:$src), (i32 255))), (MOVZX32rm8 addr:$src)>;
2653 def : Pat<(i32 (and (loadi32 addr:$src), (i32 65535))),(MOVZX32rm16 addr:$src)>;
2655 //===----------------------------------------------------------------------===//
2657 //===----------------------------------------------------------------------===//
2659 // (shl x, 1) ==> (add x, x)
2660 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
2661 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
2662 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
2664 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
2665 def : Pat<(or (srl GR32:$src1, CL:$amt),
2666 (shl GR32:$src2, (sub 32, CL:$amt))),
2667 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
2669 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
2670 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2671 (SHRD32mrCL addr:$dst, GR32:$src2)>;
2673 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
2674 def : Pat<(or (shl GR32:$src1, CL:$amt),
2675 (srl GR32:$src2, (sub 32, CL:$amt))),
2676 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
2678 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
2679 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2680 (SHLD32mrCL addr:$dst, GR32:$src2)>;
2682 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
2683 def : Pat<(or (srl GR16:$src1, CL:$amt),
2684 (shl GR16:$src2, (sub 16, CL:$amt))),
2685 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
2687 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
2688 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2689 (SHRD16mrCL addr:$dst, GR16:$src2)>;
2691 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
2692 def : Pat<(or (shl GR16:$src1, CL:$amt),
2693 (srl GR16:$src2, (sub 16, CL:$amt))),
2694 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
2696 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
2697 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2698 (SHLD16mrCL addr:$dst, GR16:$src2)>;
2701 //===----------------------------------------------------------------------===//
2702 // Floating Point Stack Support
2703 //===----------------------------------------------------------------------===//
2705 include "X86InstrFPStack.td"
2707 //===----------------------------------------------------------------------===//
2709 //===----------------------------------------------------------------------===//
2711 include "X86InstrX86-64.td"
2713 //===----------------------------------------------------------------------===//
2714 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
2715 //===----------------------------------------------------------------------===//
2717 include "X86InstrMMX.td"
2719 //===----------------------------------------------------------------------===//
2720 // XMM Floating point support (requires SSE / SSE2)
2721 //===----------------------------------------------------------------------===//
2723 include "X86InstrSSE.td"