1 //===- X86InstrInfo.td - Main X86 Instruction Definition ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
35 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
49 // RES1, RES2, FLAGS = op LHS, RHS
50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
54 SDTCisInt<0>, SDTCisVT<1, i32>]>;
55 def SDTX86BrCond : SDTypeProfile<0, 3,
56 [SDTCisVT<0, OtherVT>,
57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 def SDTX86SetCC : SDTypeProfile<1, 2,
61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
62 def SDTX86SetCC_C : SDTypeProfile<1, 2,
64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
66 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
68 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
71 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
72 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
74 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
75 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
78 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
80 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
84 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
90 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
92 def SDTX86Void : SDTypeProfile<0, 0, []>;
94 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
96 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
98 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
100 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
102 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
104 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
106 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
107 def SDT_X86MEMBARRIERNoSSE : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
109 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
111 def X86MemBarrierNoSSE : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIERNoSSE,
113 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
115 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
117 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
121 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
122 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
123 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
124 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
126 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
127 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
129 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
130 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
132 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
133 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
135 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
136 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
137 SDNPMayLoad, SDNPMemOperand]>;
138 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
139 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
140 SDNPMayLoad, SDNPMemOperand]>;
141 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
142 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
143 SDNPMayLoad, SDNPMemOperand]>;
145 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
146 [SDNPHasChain, SDNPMayStore,
147 SDNPMayLoad, SDNPMemOperand]>;
148 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
149 [SDNPHasChain, SDNPMayStore,
150 SDNPMayLoad, SDNPMemOperand]>;
151 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
152 [SDNPHasChain, SDNPMayStore,
153 SDNPMayLoad, SDNPMemOperand]>;
154 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
155 [SDNPHasChain, SDNPMayStore,
156 SDNPMayLoad, SDNPMemOperand]>;
157 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
158 [SDNPHasChain, SDNPMayStore,
159 SDNPMayLoad, SDNPMemOperand]>;
160 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
161 [SDNPHasChain, SDNPMayStore,
162 SDNPMayLoad, SDNPMemOperand]>;
163 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
164 [SDNPHasChain, SDNPMayStore,
165 SDNPMayLoad, SDNPMemOperand]>;
166 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
167 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
169 def X86vastart_save_xmm_regs :
170 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
171 SDT_X86VASTART_SAVE_XMM_REGS,
172 [SDNPHasChain, SDNPVariadic]>;
174 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
175 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
177 def X86callseq_start :
178 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
179 [SDNPHasChain, SDNPOutGlue]>;
181 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
182 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
184 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
185 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
188 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
189 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
190 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
191 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
194 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
195 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
197 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
198 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
200 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
201 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
203 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
206 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
207 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
209 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
211 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
212 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
214 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
216 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
217 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
219 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
220 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
221 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
223 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
225 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
227 def X86andn_flag : SDNode<"X86ISD::ANDN", SDTBinaryArithWithFlags>;
229 def X86blsi_flag : SDNode<"X86ISD::BLSI", SDTUnaryArithWithFlags>;
230 def X86blsmsk_flag : SDNode<"X86ISD::BLSMSK", SDTUnaryArithWithFlags>;
231 def X86blsr_flag : SDNode<"X86ISD::BLSR", SDTUnaryArithWithFlags>;
233 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
235 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
236 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
238 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
241 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
242 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
244 //===----------------------------------------------------------------------===//
245 // X86 Operand Definitions.
248 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
249 // the index operand of an address, to conform to x86 encoding restrictions.
250 def ptr_rc_nosp : PointerLikeRegClass<1>;
252 // *mem - Operand definitions for the funky X86 addressing mode operands.
254 def X86MemAsmOperand : AsmOperandClass {
256 let SuperClasses = [];
258 def X86AbsMemAsmOperand : AsmOperandClass {
260 let SuperClasses = [X86MemAsmOperand];
262 class X86MemOperand<string printMethod> : Operand<iPTR> {
263 let PrintMethod = printMethod;
264 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
265 let ParserMatchClass = X86MemAsmOperand;
268 let OperandType = "OPERAND_MEMORY" in {
269 def opaque32mem : X86MemOperand<"printopaquemem">;
270 def opaque48mem : X86MemOperand<"printopaquemem">;
271 def opaque80mem : X86MemOperand<"printopaquemem">;
272 def opaque512mem : X86MemOperand<"printopaquemem">;
274 def i8mem : X86MemOperand<"printi8mem">;
275 def i16mem : X86MemOperand<"printi16mem">;
276 def i32mem : X86MemOperand<"printi32mem">;
277 def i64mem : X86MemOperand<"printi64mem">;
278 def i128mem : X86MemOperand<"printi128mem">;
279 def i256mem : X86MemOperand<"printi256mem">;
280 def f32mem : X86MemOperand<"printf32mem">;
281 def f64mem : X86MemOperand<"printf64mem">;
282 def f80mem : X86MemOperand<"printf80mem">;
283 def f128mem : X86MemOperand<"printf128mem">;
284 def f256mem : X86MemOperand<"printf256mem">;
287 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
288 // plain GR64, so that it doesn't potentially require a REX prefix.
289 def i8mem_NOREX : Operand<i64> {
290 let PrintMethod = "printi8mem";
291 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
292 let ParserMatchClass = X86MemAsmOperand;
293 let OperandType = "OPERAND_MEMORY";
296 // GPRs available for tailcall.
297 // It represents GR64_TC or GR64_TCW64.
298 def ptr_rc_tailcall : PointerLikeRegClass<2>;
300 // Special i32mem for addresses of load folding tail calls. These are not
301 // allowed to use callee-saved registers since they must be scheduled
302 // after callee-saved register are popped.
303 def i32mem_TC : Operand<i32> {
304 let PrintMethod = "printi32mem";
305 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
306 let ParserMatchClass = X86MemAsmOperand;
307 let OperandType = "OPERAND_MEMORY";
310 // Special i64mem for addresses of load folding tail calls. These are not
311 // allowed to use callee-saved registers since they must be scheduled
312 // after callee-saved register are popped.
313 def i64mem_TC : Operand<i64> {
314 let PrintMethod = "printi64mem";
315 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
316 ptr_rc_tailcall, i32imm, i8imm);
317 let ParserMatchClass = X86MemAsmOperand;
318 let OperandType = "OPERAND_MEMORY";
321 let OperandType = "OPERAND_PCREL",
322 ParserMatchClass = X86AbsMemAsmOperand,
323 PrintMethod = "print_pcrel_imm" in {
324 def i32imm_pcrel : Operand<i32>;
325 def i16imm_pcrel : Operand<i16>;
327 def offset8 : Operand<i64>;
328 def offset16 : Operand<i64>;
329 def offset32 : Operand<i64>;
330 def offset64 : Operand<i64>;
332 // Branch targets have OtherVT type and print as pc-relative values.
333 def brtarget : Operand<OtherVT>;
334 def brtarget8 : Operand<OtherVT>;
338 def SSECC : Operand<i8> {
339 let PrintMethod = "printSSECC";
340 let OperandType = "OPERAND_IMMEDIATE";
343 class ImmSExtAsmOperandClass : AsmOperandClass {
344 let SuperClasses = [ImmAsmOperand];
345 let RenderMethod = "addImmOperands";
348 class ImmZExtAsmOperandClass : AsmOperandClass {
349 let SuperClasses = [ImmAsmOperand];
350 let RenderMethod = "addImmOperands";
353 // Sign-extended immediate classes. We don't need to define the full lattice
354 // here because there is no instruction with an ambiguity between ImmSExti64i32
357 // The strange ranges come from the fact that the assembler always works with
358 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
359 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
362 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
363 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
364 let Name = "ImmSExti64i32";
367 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
368 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
369 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
370 let Name = "ImmSExti16i8";
371 let SuperClasses = [ImmSExti64i32AsmOperand];
374 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
375 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
376 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
377 let Name = "ImmSExti32i8";
381 def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass {
382 let Name = "ImmZExtu32u8";
387 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
388 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
389 let Name = "ImmSExti64i8";
390 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
391 ImmSExti64i32AsmOperand];
394 // A couple of more descriptive operand definitions.
395 // 16-bits but only 8 bits are significant.
396 def i16i8imm : Operand<i16> {
397 let ParserMatchClass = ImmSExti16i8AsmOperand;
398 let OperandType = "OPERAND_IMMEDIATE";
400 // 32-bits but only 8 bits are significant.
401 def i32i8imm : Operand<i32> {
402 let ParserMatchClass = ImmSExti32i8AsmOperand;
403 let OperandType = "OPERAND_IMMEDIATE";
405 // 32-bits but only 8 bits are significant, and those 8 bits are unsigned.
406 def u32u8imm : Operand<i32> {
407 let ParserMatchClass = ImmZExtu32u8AsmOperand;
408 let OperandType = "OPERAND_IMMEDIATE";
411 // 64-bits but only 32 bits are significant.
412 def i64i32imm : Operand<i64> {
413 let ParserMatchClass = ImmSExti64i32AsmOperand;
414 let OperandType = "OPERAND_IMMEDIATE";
417 // 64-bits but only 32 bits are significant, and those bits are treated as being
419 def i64i32imm_pcrel : Operand<i64> {
420 let PrintMethod = "print_pcrel_imm";
421 let ParserMatchClass = X86AbsMemAsmOperand;
422 let OperandType = "OPERAND_PCREL";
425 // 64-bits but only 8 bits are significant.
426 def i64i8imm : Operand<i64> {
427 let ParserMatchClass = ImmSExti64i8AsmOperand;
428 let OperandType = "OPERAND_IMMEDIATE";
431 def lea64_32mem : Operand<i32> {
432 let PrintMethod = "printi32mem";
433 let AsmOperandLowerMethod = "lower_lea64_32mem";
434 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm);
435 let ParserMatchClass = X86MemAsmOperand;
439 //===----------------------------------------------------------------------===//
440 // X86 Complex Pattern Definitions.
443 // Define X86 specific addressing mode.
444 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
445 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
446 [add, sub, mul, X86mul_imm, shl, or, frameindex],
448 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
449 [tglobaltlsaddr], []>;
451 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
452 [add, sub, mul, X86mul_imm, shl, or, frameindex,
455 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
456 [tglobaltlsaddr], []>;
458 //===----------------------------------------------------------------------===//
459 // X86 Instruction Predicate Definitions.
460 def HasCMov : Predicate<"Subtarget->hasCMov()">;
461 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
463 def HasMMX : Predicate<"Subtarget->hasMMX()">;
464 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
465 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
466 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
467 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
468 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
469 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
470 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
471 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
472 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
474 def HasAVX : Predicate<"Subtarget->hasAVX()">;
475 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
476 def HasXMM : Predicate<"Subtarget->hasXMM()">;
477 def HasXMMInt : Predicate<"Subtarget->hasXMMInt()">;
479 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
480 def HasAES : Predicate<"Subtarget->hasAES()">;
481 def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">;
482 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
483 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
484 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
485 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
486 def HasF16C : Predicate<"Subtarget->hasF16C()">;
487 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
488 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
489 def HasBMI : Predicate<"Subtarget->hasBMI()">;
490 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
491 def FPStackf32 : Predicate<"!Subtarget->hasXMM()">;
492 def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">;
493 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
494 def In32BitMode : Predicate<"!Subtarget->is64Bit()">,
495 AssemblerPredicate<"!Mode64Bit">;
496 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
497 AssemblerPredicate<"Mode64Bit">;
498 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
499 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
500 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
501 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
502 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
503 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
504 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
505 "TM.getCodeModel() != CodeModel::Kernel">;
506 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
507 "TM.getCodeModel() == CodeModel::Kernel">;
508 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
509 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
510 def OptForSize : Predicate<"OptForSize">;
511 def OptForSpeed : Predicate<"!OptForSize">;
512 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
513 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
515 //===----------------------------------------------------------------------===//
516 // X86 Instruction Format Definitions.
519 include "X86InstrFormats.td"
521 //===----------------------------------------------------------------------===//
522 // Pattern fragments.
525 // X86 specific condition code. These correspond to CondCode in
526 // X86InstrInfo.h. They must be kept in synch.
527 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
528 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
529 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
530 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
531 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
532 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
533 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
534 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
535 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
536 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
537 def X86_COND_NO : PatLeaf<(i8 10)>;
538 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
539 def X86_COND_NS : PatLeaf<(i8 12)>;
540 def X86_COND_O : PatLeaf<(i8 13)>;
541 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
542 def X86_COND_S : PatLeaf<(i8 15)>;
544 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
545 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
546 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
547 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
550 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
553 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
555 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
557 def i64immZExt32SExt8 : ImmLeaf<i64, [{
558 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
561 // Helper fragments for loads.
562 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
563 // known to be 32-bit aligned or better. Ditto for i8 to i16.
564 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
565 LoadSDNode *LD = cast<LoadSDNode>(N);
566 ISD::LoadExtType ExtType = LD->getExtensionType();
567 if (ExtType == ISD::NON_EXTLOAD)
569 if (ExtType == ISD::EXTLOAD)
570 return LD->getAlignment() >= 2 && !LD->isVolatile();
574 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
575 LoadSDNode *LD = cast<LoadSDNode>(N);
576 ISD::LoadExtType ExtType = LD->getExtensionType();
577 if (ExtType == ISD::EXTLOAD)
578 return LD->getAlignment() >= 2 && !LD->isVolatile();
582 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
583 LoadSDNode *LD = cast<LoadSDNode>(N);
584 ISD::LoadExtType ExtType = LD->getExtensionType();
585 if (ExtType == ISD::NON_EXTLOAD)
587 if (ExtType == ISD::EXTLOAD)
588 return LD->getAlignment() >= 4 && !LD->isVolatile();
592 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
593 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
594 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
595 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
596 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
598 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
599 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
600 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
601 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
602 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
603 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
605 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
606 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
607 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
608 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
609 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
610 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
611 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
612 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
613 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
614 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
616 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
617 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
618 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
619 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
620 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
621 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
622 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
623 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
624 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
625 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
628 // An 'and' node with a single use.
629 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
630 return N->hasOneUse();
632 // An 'srl' node with a single use.
633 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
634 return N->hasOneUse();
636 // An 'trunc' node with a single use.
637 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
638 return N->hasOneUse();
641 //===----------------------------------------------------------------------===//
646 let neverHasSideEffects = 1 in {
647 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
648 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
649 "nop{w}\t$zero", []>, TB, OpSize;
650 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
651 "nop{l}\t$zero", []>, TB;
655 // Constructing a stack frame.
656 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
657 "enter\t$len, $lvl", []>;
659 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
660 def LEAVE : I<0xC9, RawFrm,
661 (outs), (ins), "leave", []>, Requires<[In32BitMode]>;
663 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
664 def LEAVE64 : I<0xC9, RawFrm,
665 (outs), (ins), "leave", []>, Requires<[In64BitMode]>;
667 //===----------------------------------------------------------------------===//
668 // Miscellaneous Instructions.
671 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
673 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
675 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
676 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
678 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
680 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
681 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
683 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
684 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
685 Requires<[In32BitMode]>;
688 let mayStore = 1 in {
689 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
691 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
692 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
694 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
696 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
697 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
699 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
700 "push{l}\t$imm", []>;
701 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
702 "push{w}\t$imm", []>, OpSize;
703 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
704 "push{l}\t$imm", []>;
706 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
707 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
708 Requires<[In32BitMode]>;
713 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
715 def POP64r : I<0x58, AddRegFrm,
716 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
717 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
718 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
720 let mayStore = 1 in {
721 def PUSH64r : I<0x50, AddRegFrm,
722 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
723 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
724 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
728 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
729 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
730 "push{q}\t$imm", []>;
731 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
732 "push{q}\t$imm", []>;
733 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
734 "push{q}\t$imm", []>;
737 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
738 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>,
739 Requires<[In64BitMode]>;
740 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
741 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>,
742 Requires<[In64BitMode]>;
746 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
747 mayLoad=1, neverHasSideEffects=1 in {
748 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>,
749 Requires<[In32BitMode]>;
751 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
752 mayStore=1, neverHasSideEffects=1 in {
753 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>,
754 Requires<[In32BitMode]>;
757 let Constraints = "$src = $dst" in { // GR32 = bswap GR32
758 def BSWAP32r : I<0xC8, AddRegFrm,
759 (outs GR32:$dst), (ins GR32:$src),
761 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
763 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
765 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
766 } // Constraints = "$src = $dst"
768 // Bit scan instructions.
769 let Defs = [EFLAGS] in {
770 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
771 "bsf{w}\t{$src, $dst|$dst, $src}",
772 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
773 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
774 "bsf{w}\t{$src, $dst|$dst, $src}",
775 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
777 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
778 "bsf{l}\t{$src, $dst|$dst, $src}",
779 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
780 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
781 "bsf{l}\t{$src, $dst|$dst, $src}",
782 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
783 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
784 "bsf{q}\t{$src, $dst|$dst, $src}",
785 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, TB;
786 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
787 "bsf{q}\t{$src, $dst|$dst, $src}",
788 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, TB;
790 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
791 "bsr{w}\t{$src, $dst|$dst, $src}",
792 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
793 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
794 "bsr{w}\t{$src, $dst|$dst, $src}",
795 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
797 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
798 "bsr{l}\t{$src, $dst|$dst, $src}",
799 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
800 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
801 "bsr{l}\t{$src, $dst|$dst, $src}",
802 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
803 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
804 "bsr{q}\t{$src, $dst|$dst, $src}",
805 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, TB;
806 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
807 "bsr{q}\t{$src, $dst|$dst, $src}",
808 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, TB;
812 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
813 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
814 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", []>;
815 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", []>, OpSize;
816 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", []>;
817 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", []>;
820 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
821 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
822 def STOSB : I<0xAA, RawFrm, (outs), (ins), "stosb", []>;
823 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
824 def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", []>, OpSize;
825 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
826 def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", []>;
827 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
828 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", []>;
830 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", []>;
831 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", []>, OpSize;
832 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", []>;
833 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", []>;
835 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", []>;
836 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", []>, OpSize;
837 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", []>;
838 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", []>;
841 //===----------------------------------------------------------------------===//
842 // Move Instructions.
845 let neverHasSideEffects = 1 in {
846 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
847 "mov{b}\t{$src, $dst|$dst, $src}", []>;
848 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
849 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
850 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
851 "mov{l}\t{$src, $dst|$dst, $src}", []>;
852 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
853 "mov{q}\t{$src, $dst|$dst, $src}", []>;
855 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
856 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
857 "mov{b}\t{$src, $dst|$dst, $src}",
858 [(set GR8:$dst, imm:$src)]>;
859 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
860 "mov{w}\t{$src, $dst|$dst, $src}",
861 [(set GR16:$dst, imm:$src)]>, OpSize;
862 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
863 "mov{l}\t{$src, $dst|$dst, $src}",
864 [(set GR32:$dst, imm:$src)]>;
865 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
866 "movabs{q}\t{$src, $dst|$dst, $src}",
867 [(set GR64:$dst, imm:$src)]>;
868 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
869 "mov{q}\t{$src, $dst|$dst, $src}",
870 [(set GR64:$dst, i64immSExt32:$src)]>;
873 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
874 "mov{b}\t{$src, $dst|$dst, $src}",
875 [(store (i8 imm:$src), addr:$dst)]>;
876 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
877 "mov{w}\t{$src, $dst|$dst, $src}",
878 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
879 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
880 "mov{l}\t{$src, $dst|$dst, $src}",
881 [(store (i32 imm:$src), addr:$dst)]>;
882 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
883 "mov{q}\t{$src, $dst|$dst, $src}",
884 [(store i64immSExt32:$src, addr:$dst)]>;
886 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
887 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
888 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
889 "mov{b}\t{$src, %al|AL, $src}", []>,
890 Requires<[In32BitMode]>;
891 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
892 "mov{w}\t{$src, %ax|AL, $src}", []>, OpSize,
893 Requires<[In32BitMode]>;
894 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
895 "mov{l}\t{$src, %eax|EAX, $src}", []>,
896 Requires<[In32BitMode]>;
897 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
898 "mov{b}\t{%al, $dst|$dst, AL}", []>,
899 Requires<[In32BitMode]>;
900 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
901 "mov{w}\t{%ax, $dst|$dst, AL}", []>, OpSize,
902 Requires<[In32BitMode]>;
903 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
904 "mov{l}\t{%eax, $dst|$dst, EAX}", []>,
905 Requires<[In32BitMode]>;
907 // FIXME: These definitions are utterly broken
908 // Just leave them commented out for now because they're useless outside
909 // of the large code model, and most compilers won't generate the instructions
912 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
913 "mov{q}\t{$src, %rax|RAX, $src}", []>;
914 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
915 "mov{q}\t{$src, %rax|RAX, $src}", []>;
916 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
917 "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
918 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
919 "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
923 let isCodeGenOnly = 1 in {
924 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
925 "mov{b}\t{$src, $dst|$dst, $src}", []>;
926 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
927 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
928 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
929 "mov{l}\t{$src, $dst|$dst, $src}", []>;
930 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
931 "mov{q}\t{$src, $dst|$dst, $src}", []>;
934 let canFoldAsLoad = 1, isReMaterializable = 1 in {
935 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
936 "mov{b}\t{$src, $dst|$dst, $src}",
937 [(set GR8:$dst, (loadi8 addr:$src))]>;
938 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
939 "mov{w}\t{$src, $dst|$dst, $src}",
940 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
941 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
942 "mov{l}\t{$src, $dst|$dst, $src}",
943 [(set GR32:$dst, (loadi32 addr:$src))]>;
944 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
945 "mov{q}\t{$src, $dst|$dst, $src}",
946 [(set GR64:$dst, (load addr:$src))]>;
949 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
950 "mov{b}\t{$src, $dst|$dst, $src}",
951 [(store GR8:$src, addr:$dst)]>;
952 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
953 "mov{w}\t{$src, $dst|$dst, $src}",
954 [(store GR16:$src, addr:$dst)]>, OpSize;
955 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
956 "mov{l}\t{$src, $dst|$dst, $src}",
957 [(store GR32:$src, addr:$dst)]>;
958 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
959 "mov{q}\t{$src, $dst|$dst, $src}",
960 [(store GR64:$src, addr:$dst)]>;
962 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
963 // that they can be used for copying and storing h registers, which can't be
964 // encoded when a REX prefix is present.
965 let isCodeGenOnly = 1 in {
966 let neverHasSideEffects = 1 in
967 def MOV8rr_NOREX : I<0x88, MRMDestReg,
968 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
969 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
971 def MOV8mr_NOREX : I<0x88, MRMDestMem,
972 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
973 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
974 let mayLoad = 1, neverHasSideEffects = 1,
975 canFoldAsLoad = 1, isReMaterializable = 1 in
976 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
977 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
978 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
982 // Condition code ops, incl. set if equal/not equal/...
983 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
984 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
985 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
986 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
989 //===----------------------------------------------------------------------===//
990 // Bit tests instructions: BT, BTS, BTR, BTC.
992 let Defs = [EFLAGS] in {
993 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
994 "bt{w}\t{$src2, $src1|$src1, $src2}",
995 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
996 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
997 "bt{l}\t{$src2, $src1|$src1, $src2}",
998 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
999 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1000 "bt{q}\t{$src2, $src1|$src1, $src2}",
1001 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB;
1003 // Unlike with the register+register form, the memory+register form of the
1004 // bt instruction does not ignore the high bits of the index. From ISel's
1005 // perspective, this is pretty bizarre. Make these instructions disassembly
1008 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1009 "bt{w}\t{$src2, $src1|$src1, $src2}",
1010 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1011 // (implicit EFLAGS)]
1013 >, OpSize, TB, Requires<[FastBTMem]>;
1014 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1015 "bt{l}\t{$src2, $src1|$src1, $src2}",
1016 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1017 // (implicit EFLAGS)]
1019 >, TB, Requires<[FastBTMem]>;
1020 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1021 "bt{q}\t{$src2, $src1|$src1, $src2}",
1022 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1023 // (implicit EFLAGS)]
1027 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1028 "bt{w}\t{$src2, $src1|$src1, $src2}",
1029 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
1031 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1032 "bt{l}\t{$src2, $src1|$src1, $src2}",
1033 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
1034 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1035 "bt{q}\t{$src2, $src1|$src1, $src2}",
1036 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))]>, TB;
1038 // Note that these instructions don't need FastBTMem because that
1039 // only applies when the other operand is in a register. When it's
1040 // an immediate, bt is still fast.
1041 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1042 "bt{w}\t{$src2, $src1|$src1, $src2}",
1043 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1045 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1046 "bt{l}\t{$src2, $src1|$src1, $src2}",
1047 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1049 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1050 "bt{q}\t{$src2, $src1|$src1, $src2}",
1051 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1052 i64immSExt8:$src2))]>, TB;
1055 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1056 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1057 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1058 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1059 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1060 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1061 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1062 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1063 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1064 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1065 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1066 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1067 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1068 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1069 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1070 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1071 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1072 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1073 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1074 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1075 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1076 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1077 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1078 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1080 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1081 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1082 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1083 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1084 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1085 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1086 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1087 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1088 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1089 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1090 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1091 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1092 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1093 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1094 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1095 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1096 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1097 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1098 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1099 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1100 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1101 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1102 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1103 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1105 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1106 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1107 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1108 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1109 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1110 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1111 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1112 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1113 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1114 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1115 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1116 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1117 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1118 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1119 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1120 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1121 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1122 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1123 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1124 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1125 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1126 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1127 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1128 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1129 } // Defs = [EFLAGS]
1132 //===----------------------------------------------------------------------===//
1137 // Atomic swap. These are just normal xchg instructions. But since a memory
1138 // operand is referenced, the atomicity is ensured.
1139 let Constraints = "$val = $dst" in {
1140 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
1141 "xchg{b}\t{$val, $ptr|$ptr, $val}",
1142 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
1143 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),(ins GR16:$val, i16mem:$ptr),
1144 "xchg{w}\t{$val, $ptr|$ptr, $val}",
1145 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
1147 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),(ins GR32:$val, i32mem:$ptr),
1148 "xchg{l}\t{$val, $ptr|$ptr, $val}",
1149 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
1150 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),(ins GR64:$val,i64mem:$ptr),
1151 "xchg{q}\t{$val, $ptr|$ptr, $val}",
1152 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1154 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1155 "xchg{b}\t{$val, $src|$src, $val}", []>;
1156 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1157 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
1158 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1159 "xchg{l}\t{$val, $src|$src, $val}", []>;
1160 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1161 "xchg{q}\t{$val, $src|$src, $val}", []>;
1164 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1165 "xchg{w}\t{$src, %ax|AX, $src}", []>, OpSize;
1166 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1167 "xchg{l}\t{$src, %eax|EAX, $src}", []>, Requires<[In32BitMode]>;
1168 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1169 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1170 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1171 "xchg{l}\t{$src, %eax|EAX, $src}", []>, Requires<[In64BitMode]>;
1172 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1173 "xchg{q}\t{$src, %rax|RAX, $src}", []>;
1177 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1178 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
1179 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1180 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1181 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1182 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
1183 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1184 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1186 let mayLoad = 1, mayStore = 1 in {
1187 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1188 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
1189 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1190 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1191 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1192 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
1193 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1194 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1198 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1199 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
1200 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1201 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1202 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1203 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
1204 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1205 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1207 let mayLoad = 1, mayStore = 1 in {
1208 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1209 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
1210 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1211 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1212 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1213 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
1214 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1215 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1218 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1219 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1220 "cmpxchg8b\t$dst", []>, TB;
1222 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1223 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1224 "cmpxchg16b\t$dst", []>, TB, Requires<[HasCmpxchg16b]>;
1228 // Lock instruction prefix
1229 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1231 // Rex64 instruction prefix
1232 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>;
1234 // Data16 instruction prefix
1235 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1237 // Repeat string operation instruction prefixes
1238 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1239 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1240 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1241 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1242 // Repeat while not equal (used with CMPS and SCAS)
1243 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1247 // String manipulation instructions
1248 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
1249 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
1250 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
1251 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
1253 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
1254 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
1255 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
1258 // Flag instructions
1259 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
1260 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
1261 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
1262 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
1263 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
1264 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
1265 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
1267 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
1269 // Table lookup instructions
1270 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
1272 // ASCII Adjust After Addition
1273 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1274 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", []>, Requires<[In32BitMode]>;
1276 // ASCII Adjust AX Before Division
1277 // sets AL, AH and EFLAGS and uses AL and AH
1278 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1279 "aad\t$src", []>, Requires<[In32BitMode]>;
1281 // ASCII Adjust AX After Multiply
1282 // sets AL, AH and EFLAGS and uses AL
1283 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1284 "aam\t$src", []>, Requires<[In32BitMode]>;
1286 // ASCII Adjust AL After Subtraction - sets
1287 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1288 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>, Requires<[In32BitMode]>;
1290 // Decimal Adjust AL after Addition
1291 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1292 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", []>, Requires<[In32BitMode]>;
1294 // Decimal Adjust AL after Subtraction
1295 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1296 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>, Requires<[In32BitMode]>;
1298 // Check Array Index Against Bounds
1299 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1300 "bound\t{$src, $dst|$dst, $src}", []>, OpSize,
1301 Requires<[In32BitMode]>;
1302 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1303 "bound\t{$src, $dst|$dst, $src}", []>,
1304 Requires<[In32BitMode]>;
1306 // Adjust RPL Field of Segment Selector
1307 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$src), (ins GR16:$dst),
1308 "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
1309 def ARPL16mr : I<0x63, MRMSrcMem, (outs GR16:$src), (ins i16mem:$dst),
1310 "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
1312 //===----------------------------------------------------------------------===//
1313 // MOVBE Instructions
1315 let Predicates = [HasMOVBE] in {
1316 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1317 "movbe{w}\t{$src, $dst|$dst, $src}",
1318 [(set GR16:$dst, (bswap (loadi16 addr:$src)))]>, OpSize, T8;
1319 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1320 "movbe{l}\t{$src, $dst|$dst, $src}",
1321 [(set GR32:$dst, (bswap (loadi32 addr:$src)))]>, T8;
1322 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1323 "movbe{q}\t{$src, $dst|$dst, $src}",
1324 [(set GR64:$dst, (bswap (loadi64 addr:$src)))]>, T8;
1325 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1326 "movbe{w}\t{$src, $dst|$dst, $src}",
1327 [(store (bswap GR16:$src), addr:$dst)]>, OpSize, T8;
1328 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1329 "movbe{l}\t{$src, $dst|$dst, $src}",
1330 [(store (bswap GR32:$src), addr:$dst)]>, T8;
1331 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1332 "movbe{q}\t{$src, $dst|$dst, $src}",
1333 [(store (bswap GR64:$src), addr:$dst)]>, T8;
1336 //===----------------------------------------------------------------------===//
1337 // RDRAND Instruction
1339 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1340 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1341 "rdrand{w}\t$dst", []>, OpSize, TB;
1342 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1343 "rdrand{l}\t$dst", []>, TB;
1344 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1345 "rdrand{q}\t$dst", []>, TB;
1348 //===----------------------------------------------------------------------===//
1349 // LZCNT Instruction
1351 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
1352 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1353 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1354 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
1356 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1357 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1358 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
1359 (implicit EFLAGS)]>, XS, OpSize;
1361 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1362 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1363 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS;
1364 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1365 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1366 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
1367 (implicit EFLAGS)]>, XS;
1369 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1370 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1371 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
1373 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1374 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1375 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
1376 (implicit EFLAGS)]>, XS;
1379 //===----------------------------------------------------------------------===//
1382 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1383 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1384 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1385 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
1387 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1388 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1389 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
1390 (implicit EFLAGS)]>, XS, OpSize;
1392 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1393 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1394 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS;
1395 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1396 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1397 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
1398 (implicit EFLAGS)]>, XS;
1400 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1401 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1402 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
1404 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1405 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1406 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
1407 (implicit EFLAGS)]>, XS;
1410 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
1411 RegisterClass RC, X86MemOperand x86memop, SDNode OpNode,
1413 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
1414 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1415 [(set RC:$dst, EFLAGS, (OpNode RC:$src))]>, T8, VEX_4V;
1416 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
1417 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1418 [(set RC:$dst, EFLAGS, (OpNode (ld_frag addr:$src)))]>,
1422 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1423 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem,
1424 X86blsr_flag, loadi32>;
1425 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem,
1426 X86blsr_flag, loadi64>, VEX_W;
1427 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem,
1428 X86blsmsk_flag, loadi32>;
1429 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem,
1430 X86blsmsk_flag, loadi64>, VEX_W;
1431 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem,
1432 X86blsi_flag, loadi32>;
1433 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem,
1434 X86blsi_flag, loadi64>, VEX_W;
1437 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
1438 X86MemOperand x86memop, Intrinsic Int,
1440 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1441 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1442 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
1444 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
1445 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1446 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
1447 (implicit EFLAGS)]>, T8, VEX_4VOp3;
1450 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1451 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
1452 int_x86_bmi_bextr_32, loadi32>;
1453 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
1454 int_x86_bmi_bextr_64, loadi64>, VEX_W;
1457 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
1458 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
1459 int_x86_bmi_bzhi_32, loadi32>;
1460 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
1461 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
1464 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
1465 X86MemOperand x86memop, Intrinsic Int,
1467 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1468 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1469 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
1471 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1472 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1473 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
1476 let Predicates = [HasBMI2] in {
1477 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
1478 int_x86_bmi_pdep_32, loadi32>, T8XD;
1479 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
1480 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
1481 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
1482 int_x86_bmi_pext_32, loadi32>, T8XS;
1483 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
1484 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
1487 //===----------------------------------------------------------------------===//
1489 //===----------------------------------------------------------------------===//
1491 include "X86InstrArithmetic.td"
1492 include "X86InstrCMovSetCC.td"
1493 include "X86InstrExtension.td"
1494 include "X86InstrControl.td"
1495 include "X86InstrShiftRotate.td"
1497 // X87 Floating Point Stack.
1498 include "X86InstrFPStack.td"
1500 // SIMD support (SSE, MMX and AVX)
1501 include "X86InstrFragmentsSIMD.td"
1503 // FMA - Fused Multiply-Add support (requires FMA)
1504 include "X86InstrFMA.td"
1506 // SSE, MMX and 3DNow! vector support.
1507 include "X86InstrSSE.td"
1508 include "X86InstrMMX.td"
1509 include "X86Instr3DNow.td"
1511 include "X86InstrVMX.td"
1513 // System instructions.
1514 include "X86InstrSystem.td"
1516 // Compiler Pseudo Instructions and Pat Patterns
1517 include "X86InstrCompiler.td"
1519 //===----------------------------------------------------------------------===//
1520 // Assembler Mnemonic Aliases
1521 //===----------------------------------------------------------------------===//
1523 def : MnemonicAlias<"call", "calll">, Requires<[In32BitMode]>;
1524 def : MnemonicAlias<"call", "callq">, Requires<[In64BitMode]>;
1526 def : MnemonicAlias<"cbw", "cbtw">;
1527 def : MnemonicAlias<"cwde", "cwtl">;
1528 def : MnemonicAlias<"cwd", "cwtd">;
1529 def : MnemonicAlias<"cdq", "cltd">;
1530 def : MnemonicAlias<"cdqe", "cltq">;
1531 def : MnemonicAlias<"cqo", "cqto">;
1533 // lret maps to lretl, it is not ambiguous with lretq.
1534 def : MnemonicAlias<"lret", "lretl">;
1536 def : MnemonicAlias<"leavel", "leave">, Requires<[In32BitMode]>;
1537 def : MnemonicAlias<"leaveq", "leave">, Requires<[In64BitMode]>;
1539 def : MnemonicAlias<"loopz", "loope">;
1540 def : MnemonicAlias<"loopnz", "loopne">;
1542 def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
1543 def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
1544 def : MnemonicAlias<"popf", "popfl">, Requires<[In32BitMode]>;
1545 def : MnemonicAlias<"popf", "popfq">, Requires<[In64BitMode]>;
1546 def : MnemonicAlias<"popfd", "popfl">;
1548 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
1549 // all modes. However: "push (addr)" and "push $42" should default to
1550 // pushl/pushq depending on the current mode. Similar for "pop %bx"
1551 def : MnemonicAlias<"push", "pushl">, Requires<[In32BitMode]>;
1552 def : MnemonicAlias<"push", "pushq">, Requires<[In64BitMode]>;
1553 def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
1554 def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1555 def : MnemonicAlias<"pushfd", "pushfl">;
1557 def : MnemonicAlias<"repe", "rep">;
1558 def : MnemonicAlias<"repz", "rep">;
1559 def : MnemonicAlias<"repnz", "repne">;
1561 def : MnemonicAlias<"retl", "ret">, Requires<[In32BitMode]>;
1562 def : MnemonicAlias<"retq", "ret">, Requires<[In64BitMode]>;
1564 def : MnemonicAlias<"salb", "shlb">;
1565 def : MnemonicAlias<"salw", "shlw">;
1566 def : MnemonicAlias<"sall", "shll">;
1567 def : MnemonicAlias<"salq", "shlq">;
1569 def : MnemonicAlias<"smovb", "movsb">;
1570 def : MnemonicAlias<"smovw", "movsw">;
1571 def : MnemonicAlias<"smovl", "movsl">;
1572 def : MnemonicAlias<"smovq", "movsq">;
1574 def : MnemonicAlias<"ud2a", "ud2">;
1575 def : MnemonicAlias<"verrw", "verr">;
1577 // System instruction aliases.
1578 def : MnemonicAlias<"iret", "iretl">;
1579 def : MnemonicAlias<"sysret", "sysretl">;
1580 def : MnemonicAlias<"sysexit", "sysexitl">;
1582 def : MnemonicAlias<"lgdtl", "lgdt">, Requires<[In32BitMode]>;
1583 def : MnemonicAlias<"lgdtq", "lgdt">, Requires<[In64BitMode]>;
1584 def : MnemonicAlias<"lidtl", "lidt">, Requires<[In32BitMode]>;
1585 def : MnemonicAlias<"lidtq", "lidt">, Requires<[In64BitMode]>;
1586 def : MnemonicAlias<"sgdtl", "sgdt">, Requires<[In32BitMode]>;
1587 def : MnemonicAlias<"sgdtq", "sgdt">, Requires<[In64BitMode]>;
1588 def : MnemonicAlias<"sidtl", "sidt">, Requires<[In32BitMode]>;
1589 def : MnemonicAlias<"sidtq", "sidt">, Requires<[In64BitMode]>;
1592 // Floating point stack aliases.
1593 def : MnemonicAlias<"fcmovz", "fcmove">;
1594 def : MnemonicAlias<"fcmova", "fcmovnbe">;
1595 def : MnemonicAlias<"fcmovnae", "fcmovb">;
1596 def : MnemonicAlias<"fcmovna", "fcmovbe">;
1597 def : MnemonicAlias<"fcmovae", "fcmovnb">;
1598 def : MnemonicAlias<"fcomip", "fcompi">;
1599 def : MnemonicAlias<"fildq", "fildll">;
1600 def : MnemonicAlias<"fldcww", "fldcw">;
1601 def : MnemonicAlias<"fnstcww", "fnstcw">;
1602 def : MnemonicAlias<"fnstsww", "fnstsw">;
1603 def : MnemonicAlias<"fucomip", "fucompi">;
1604 def : MnemonicAlias<"fwait", "wait">;
1607 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond>
1608 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
1609 !strconcat(Prefix, NewCond, Suffix)>;
1611 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
1612 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
1613 /// example "setz" -> "sete".
1614 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix> {
1615 def C : CondCodeAlias<Prefix, Suffix, "c", "b">; // setc -> setb
1616 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e">; // setz -> sete
1617 def NA : CondCodeAlias<Prefix, Suffix, "na", "be">; // setna -> setbe
1618 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae">; // setnb -> setae
1619 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae">; // setnc -> setae
1620 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le">; // setng -> setle
1621 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge">; // setnl -> setge
1622 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne">; // setnz -> setne
1623 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p">; // setpe -> setp
1624 def PO : CondCodeAlias<Prefix, Suffix, "po", "np">; // setpo -> setnp
1626 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b">; // setnae -> setb
1627 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a">; // setnbe -> seta
1628 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l">; // setnge -> setl
1629 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g">; // setnle -> setg
1632 // Aliases for set<CC>
1633 defm : IntegerCondCodeMnemonicAlias<"set", "">;
1634 // Aliases for j<CC>
1635 defm : IntegerCondCodeMnemonicAlias<"j", "">;
1636 // Aliases for cmov<CC>{w,l,q}
1637 defm : IntegerCondCodeMnemonicAlias<"cmov", "w">;
1638 defm : IntegerCondCodeMnemonicAlias<"cmov", "l">;
1639 defm : IntegerCondCodeMnemonicAlias<"cmov", "q">;
1642 //===----------------------------------------------------------------------===//
1643 // Assembler Instruction Aliases
1644 //===----------------------------------------------------------------------===//
1646 // aad/aam default to base 10 if no operand is specified.
1647 def : InstAlias<"aad", (AAD8i8 10)>;
1648 def : InstAlias<"aam", (AAM8i8 10)>;
1650 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
1651 def : InstAlias<"bt $imm, $mem", (BT32mi8 i32mem:$mem, i32i8imm:$imm)>;
1654 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>;
1655 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>;
1656 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
1657 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
1659 // div and idiv aliases for explicit A register.
1660 def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>;
1661 def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>;
1662 def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>;
1663 def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>;
1664 def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>;
1665 def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>;
1666 def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>;
1667 def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>;
1668 def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>;
1669 def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>;
1670 def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>;
1671 def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>;
1672 def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>;
1673 def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>;
1674 def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>;
1675 def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>;
1679 // Various unary fpstack operations default to operating on on ST1.
1680 // For example, "fxch" -> "fxch %st(1)"
1681 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
1682 def : InstAlias<"fsubp", (SUBR_FPrST0 ST1)>;
1683 def : InstAlias<"fsubrp", (SUB_FPrST0 ST1)>;
1684 def : InstAlias<"fmulp", (MUL_FPrST0 ST1)>;
1685 def : InstAlias<"fdivp", (DIVR_FPrST0 ST1)>;
1686 def : InstAlias<"fdivrp", (DIV_FPrST0 ST1)>;
1687 def : InstAlias<"fxch", (XCH_F ST1)>;
1688 def : InstAlias<"fcomi", (COM_FIr ST1)>;
1689 def : InstAlias<"fcompi", (COM_FIPr ST1)>;
1690 def : InstAlias<"fucom", (UCOM_Fr ST1)>;
1691 def : InstAlias<"fucomp", (UCOM_FPr ST1)>;
1692 def : InstAlias<"fucomi", (UCOM_FIr ST1)>;
1693 def : InstAlias<"fucompi", (UCOM_FIPr ST1)>;
1695 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
1696 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
1697 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
1699 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
1700 def : InstAlias<!strconcat(Mnemonic, " $op, %st(0)"),
1701 (Inst RST:$op), EmitAlias>;
1702 def : InstAlias<!strconcat(Mnemonic, " %st(0), %st(0)"),
1703 (Inst ST0), EmitAlias>;
1706 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
1707 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
1708 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
1709 defm : FpUnaryAlias<"fsubp", SUBR_FPrST0>;
1710 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
1711 defm : FpUnaryAlias<"fsubrp", SUB_FPrST0>;
1712 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
1713 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
1714 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
1715 defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>;
1716 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
1717 defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>;
1718 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
1719 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
1720 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
1721 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
1724 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
1725 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
1726 // solely because gas supports it.
1727 def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op), 0>;
1728 def : InstAlias<"fmulp %st(0), $op", (MUL_FPrST0 RST:$op)>;
1729 def : InstAlias<"fsubp %st(0), $op", (SUBR_FPrST0 RST:$op)>;
1730 def : InstAlias<"fsubrp %st(0), $op", (SUB_FPrST0 RST:$op)>;
1731 def : InstAlias<"fdivp %st(0), $op", (DIVR_FPrST0 RST:$op)>;
1732 def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>;
1734 // We accept "fnstsw %eax" even though it only writes %ax.
1735 def : InstAlias<"fnstsw %eax", (FNSTSW8r)>;
1736 def : InstAlias<"fnstsw %al" , (FNSTSW8r)>;
1737 def : InstAlias<"fnstsw" , (FNSTSW8r)>;
1739 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
1740 // this is compatible with what GAS does.
1741 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1742 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1743 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>;
1744 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>;
1746 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
1747 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
1748 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
1749 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
1750 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
1751 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
1752 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
1754 // inb %dx -> inb %al, %dx
1755 def : InstAlias<"inb %dx", (IN8rr)>;
1756 def : InstAlias<"inw %dx", (IN16rr)>;
1757 def : InstAlias<"inl %dx", (IN32rr)>;
1758 def : InstAlias<"inb $port", (IN8ri i8imm:$port)>;
1759 def : InstAlias<"inw $port", (IN16ri i8imm:$port)>;
1760 def : InstAlias<"inl $port", (IN32ri i8imm:$port)>;
1763 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
1764 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1765 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1766 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
1767 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
1768 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1769 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
1771 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
1772 // the move. All segment/mem forms are equivalent, this has the shortest
1774 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
1775 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
1777 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
1778 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
1780 // Match 'movq GR64, MMX' as an alias for movd.
1781 def : InstAlias<"movq $src, $dst",
1782 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
1783 def : InstAlias<"movq $src, $dst",
1784 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
1786 // movsd with no operands (as opposed to the SSE scalar move of a double) is an
1787 // alias for movsl. (as in rep; movsd)
1788 def : InstAlias<"movsd", (MOVSD)>;
1791 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
1792 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
1793 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
1794 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
1795 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
1796 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
1797 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
1800 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
1801 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
1802 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
1803 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
1804 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
1805 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
1806 // Note: No GR32->GR64 movzx form.
1808 // outb %dx -> outb %al, %dx
1809 def : InstAlias<"outb %dx", (OUT8rr)>;
1810 def : InstAlias<"outw %dx", (OUT16rr)>;
1811 def : InstAlias<"outl %dx", (OUT32rr)>;
1812 def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>;
1813 def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>;
1814 def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>;
1816 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
1817 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
1818 // errors, since its encoding is the most compact.
1819 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
1821 // shld/shrd op,op -> shld op, op, 1
1822 def : InstAlias<"shldw $r1, $r2", (SHLD16rri8 GR16:$r1, GR16:$r2, 1)>;
1823 def : InstAlias<"shldl $r1, $r2", (SHLD32rri8 GR32:$r1, GR32:$r2, 1)>;
1824 def : InstAlias<"shldq $r1, $r2", (SHLD64rri8 GR64:$r1, GR64:$r2, 1)>;
1825 def : InstAlias<"shrdw $r1, $r2", (SHRD16rri8 GR16:$r1, GR16:$r2, 1)>;
1826 def : InstAlias<"shrdl $r1, $r2", (SHRD32rri8 GR32:$r1, GR32:$r2, 1)>;
1827 def : InstAlias<"shrdq $r1, $r2", (SHRD64rri8 GR64:$r1, GR64:$r2, 1)>;
1829 def : InstAlias<"shldw $mem, $reg", (SHLD16mri8 i16mem:$mem, GR16:$reg, 1)>;
1830 def : InstAlias<"shldl $mem, $reg", (SHLD32mri8 i32mem:$mem, GR32:$reg, 1)>;
1831 def : InstAlias<"shldq $mem, $reg", (SHLD64mri8 i64mem:$mem, GR64:$reg, 1)>;
1832 def : InstAlias<"shrdw $mem, $reg", (SHRD16mri8 i16mem:$mem, GR16:$reg, 1)>;
1833 def : InstAlias<"shrdl $mem, $reg", (SHRD32mri8 i32mem:$mem, GR32:$reg, 1)>;
1834 def : InstAlias<"shrdq $mem, $reg", (SHRD64mri8 i64mem:$mem, GR64:$reg, 1)>;
1836 /* FIXME: This is disabled because the asm matcher is currently incapable of
1837 * matching a fixed immediate like $1.
1838 // "shl X, $1" is an alias for "shl X".
1839 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
1840 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
1841 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
1842 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
1843 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
1844 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
1845 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
1846 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
1847 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
1848 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
1849 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
1850 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
1851 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
1852 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
1853 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
1854 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
1855 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
1858 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
1859 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
1860 defm : ShiftRotateByOneAlias<"rol", "ROL">;
1861 defm : ShiftRotateByOneAlias<"ror", "ROR">;
1864 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
1865 def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>;
1866 def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>;
1867 def : InstAlias<"testl $val, $mem", (TEST32rm GR32:$val, i32mem:$mem)>;
1868 def : InstAlias<"testq $val, $mem", (TEST64rm GR64:$val, i64mem:$mem)>;
1870 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
1871 def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>;
1872 def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>;
1873 def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>;
1874 def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>;
1876 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
1877 def : InstAlias<"xchgw %ax, $src", (XCHG16ar GR16:$src)>;
1878 def : InstAlias<"xchgl %eax, $src", (XCHG32ar GR32:$src)>, Requires<[In32BitMode]>;
1879 def : InstAlias<"xchgl %eax, $src", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
1880 def : InstAlias<"xchgq %rax, $src", (XCHG64ar GR64:$src)>;