1 //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Format specifies the encoding used by the instruction. This is part of the
17 // ad-hoc solution used to emit machine instruction encodings by our machine
19 class Format<bits<5> val> {
23 def Pseudo : Format<0>; def RawFrm : Format<1>;
24 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
25 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
26 def MRMSrcMem : Format<6>;
27 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
28 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
29 def MRM6r : Format<22>; def MRM7r : Format<23>;
30 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
31 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
32 def MRM6m : Format<30>; def MRM7m : Format<31>;
34 // ArgType - This specifies the argument type used by an instruction. This is
35 // part of the ad-hoc solution used to emit machine instruction encodings by our
36 // machine code emitter.
37 class ArgType<bits<3> val> {
40 def NoArg : ArgType<0>;
41 def Arg8 : ArgType<1>;
42 def Arg16 : ArgType<2>;
43 def Arg32 : ArgType<3>;
44 def Arg64 : ArgType<4>; // 64 bit int argument for FILD64
45 def ArgF32 : ArgType<5>;
46 def ArgF64 : ArgType<6>;
47 def ArgF80 : ArgType<6>;
49 // FPFormat - This specifies what form this FP instruction has. This is used by
50 // the Floating-Point stackifier pass.
51 class FPFormat<bits<3> val> {
54 def NotFP : FPFormat<0>;
55 def ZeroArgFP : FPFormat<1>;
56 def OneArgFP : FPFormat<2>;
57 def OneArgFPRW : FPFormat<3>;
58 def TwoArgFP : FPFormat<4>;
59 def SpecialFP : FPFormat<5>;
62 class X86Inst<string nam, bits<8> opcod, Format f, ArgType a> : Instruction {
63 let Namespace = "X86";
66 bits<8> Opcode = opcod;
68 bits<5> FormBits = Form.Value;
70 bits<3> TypeBits = Type.Value;
72 // Attributes specific to X86 instructions...
73 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
74 bit printImplicitUses = 0; // Should we print implicit uses of this inst?
76 bits<4> Prefix = 0; // Which prefix byte does this inst have?
77 FPFormat FPForm; // What flavor of FP instruction is this?
78 bits<3> FPFormBits = 0;
81 class Imp<list<Register> uses, list<Register> defs> {
82 list<Register> Uses = uses;
83 list<Register> Defs = defs;
86 class Pattern<dag P> {
91 // Prefix byte classes which are used to indicate to the ad-hoc machine code
92 // emitter that various prefix bytes are required.
93 class OpSize { bit hasOpSizePrefix = 1; }
94 class TB { bits<4> Prefix = 1; }
95 class REP { bits<4> Prefix = 2; }
96 class D8 { bits<4> Prefix = 3; }
97 class D9 { bits<4> Prefix = 4; }
98 class DA { bits<4> Prefix = 5; }
99 class DB { bits<4> Prefix = 6; }
100 class DC { bits<4> Prefix = 7; }
101 class DD { bits<4> Prefix = 8; }
102 class DE { bits<4> Prefix = 9; }
103 class DF { bits<4> Prefix = 10; }
107 //===----------------------------------------------------------------------===//
108 // Instruction list...
111 def PHI : X86Inst<"PHI", 0, Pseudo, NoArg>; // PHI node...
113 def NOOP : X86Inst<"nop", 0x90, RawFrm, NoArg>; // nop
115 def ADJCALLSTACKDOWN : X86Inst<"ADJCALLSTACKDOWN", 0, Pseudo, NoArg>;
116 def ADJCALLSTACKUP : X86Inst<"ADJCALLSTACKUP", 0, Pseudo, NoArg>;
117 def IMPLICIT_USE : X86Inst<"IMPLICIT_USE", 0, Pseudo, NoArg>;
118 def IMPLICIT_DEF : X86Inst<"IMPLICIT_DEF", 0, Pseudo, NoArg>;
119 let isTerminator = 1 in
120 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
121 def FP_REG_KILL : X86Inst<"FP_REG_KILL", 0, Pseudo, NoArg>;
122 //===----------------------------------------------------------------------===//
123 // Control Flow Instructions...
126 // Return instruction...
127 let isTerminator = 1, isReturn = 1 in
128 def RET : X86Inst<"ret", 0xC3, RawFrm, NoArg>, Pattern<(retvoid)>;
130 // All branches are RawFrm, Void, Branch, and Terminators
131 let isBranch = 1, isTerminator = 1 in
132 class IBr<string name, bits<8> opcode> : X86Inst<name, opcode, RawFrm, NoArg>;
134 def JMP : IBr<"jmp", 0xE9>, Pattern<(br basicblock)>;
135 def JB : IBr<"jb" , 0x82>, TB;
136 def JAE : IBr<"jae", 0x83>, TB;
137 def JE : IBr<"je" , 0x84>, TB, Pattern<(isVoid (unspec1 basicblock))>;
138 def JNE : IBr<"jne", 0x85>, TB;
139 def JBE : IBr<"jbe", 0x86>, TB;
140 def JA : IBr<"ja" , 0x87>, TB;
141 def JS : IBr<"js" , 0x88>, TB;
142 def JNS : IBr<"jns", 0x89>, TB;
143 def JL : IBr<"jl" , 0x8C>, TB;
144 def JGE : IBr<"jge", 0x8D>, TB;
145 def JLE : IBr<"jle", 0x8E>, TB;
146 def JG : IBr<"jg" , 0x8F>, TB;
149 //===----------------------------------------------------------------------===//
150 // Call Instructions...
153 // All calls clobber the non-callee saved registers...
154 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6] in {
155 def CALLpcrel32 : X86Inst<"call", 0xE8, RawFrm, NoArg>;
156 def CALLr32 : X86Inst<"call", 0xFF, MRM2r , Arg32>;
157 def CALLm32 : X86Inst<"call", 0xFF, MRM2m , Arg32>;
161 //===----------------------------------------------------------------------===//
162 // Miscellaneous Instructions...
164 def LEAVE : X86Inst<"leave", 0xC9, RawFrm, NoArg>, Imp<[EBP,ESP],[EBP,ESP]>;
165 def POPr32 : X86Inst<"pop", 0x58, AddRegFrm, Arg32>, Imp<[ESP],[ESP]>;
167 let isTwoAddress = 1 in // R32 = bswap R32
168 def BSWAPr32 : X86Inst<"bswap", 0xC8, AddRegFrm, Arg32>, TB;
170 def XCHGrr8 : X86Inst<"xchg", 0x86, MRMDestReg, Arg8>; // xchg R8, R8
171 def XCHGrr16 : X86Inst<"xchg", 0x87, MRMDestReg, Arg16>, OpSize;// xchg R16, R16
172 def XCHGrr32 : X86Inst<"xchg", 0x87, MRMDestReg, Arg32>; // xchg R32, R32
173 def XCHGmr8 : X86Inst<"xchg", 0x86, MRMDestMem, Arg8>; // xchg [mem8], R8
174 def XCHGmr16 : X86Inst<"xchg", 0x87, MRMDestMem, Arg16>, OpSize;// xchg [mem16], R16
175 def XCHGmr32 : X86Inst<"xchg", 0x87, MRMDestMem, Arg32>; // xchg [mem32], R32
176 def XCHGrm8 : X86Inst<"xchg", 0x86, MRMSrcMem , Arg8>; // xchg R8, [mem8]
177 def XCHGrm16 : X86Inst<"xchg", 0x87, MRMSrcMem , Arg16>, OpSize;// xchg R16, [mem16]
178 def XCHGrm32 : X86Inst<"xchg", 0x87, MRMSrcMem , Arg32>; // xchg R32, [mem32]
180 def LEAr16 : X86Inst<"lea", 0x8D, MRMSrcMem, Arg16>, OpSize; // R16 = lea [mem]
181 def LEAr32 : X86Inst<"lea", 0x8D, MRMSrcMem, Arg32>; // R32 = lea [mem]
184 def REP_MOVSB : X86Inst<"rep movsb", 0xA4, RawFrm, NoArg>, REP,
185 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>;
186 def REP_MOVSW : X86Inst<"rep movsw", 0xA5, RawFrm, NoArg>, REP, OpSize,
187 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>;
188 def REP_MOVSD : X86Inst<"rep movsd", 0xA5, RawFrm, NoArg>, REP,
189 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>;
191 def REP_STOSB : X86Inst<"rep stosb", 0xAA, RawFrm, NoArg>, REP,
192 Imp<[AL,ECX,EDI], [ECX,EDI]>;
193 def REP_STOSW : X86Inst<"rep stosw", 0xAB, RawFrm, NoArg>, REP, OpSize,
194 Imp<[AX,ECX,EDI], [ECX,EDI]>;
195 def REP_STOSD : X86Inst<"rep stosd", 0xAB, RawFrm, NoArg>, REP,
196 Imp<[EAX,ECX,EDI], [ECX,EDI]>;
198 //===----------------------------------------------------------------------===//
199 // Move Instructions...
201 def MOVrr8 : X86Inst<"mov", 0x88, MRMDestReg, Arg8>, Pattern<(set R8 , R8 )>;
202 def MOVrr16 : X86Inst<"mov", 0x89, MRMDestReg, Arg16>, OpSize, Pattern<(set R16, R16)>;
203 def MOVrr32 : X86Inst<"mov", 0x89, MRMDestReg, Arg32>, Pattern<(set R32, R32)>;
204 def MOVri8 : X86Inst<"mov", 0xB0, AddRegFrm , Arg8>, Pattern<(set R8 , imm )>;
205 def MOVri16 : X86Inst<"mov", 0xB8, AddRegFrm , Arg16>, OpSize, Pattern<(set R16, imm)>;
206 def MOVri32 : X86Inst<"mov", 0xB8, AddRegFrm , Arg32>, Pattern<(set R32, imm)>;
207 def MOVmi8 : X86Inst<"mov", 0xC6, MRM0m , Arg8>; // [mem] = imm8
208 def MOVmi16 : X86Inst<"mov", 0xC7, MRM0m , Arg16>, OpSize; // [mem] = imm16
209 def MOVmi32 : X86Inst<"mov", 0xC7, MRM0m , Arg32>; // [mem] = imm32
211 def MOVrm8 : X86Inst<"mov", 0x8A, MRMSrcMem , Arg8>; // R8 = [mem]
212 def MOVrm16 : X86Inst<"mov", 0x8B, MRMSrcMem , Arg16>, OpSize, // R16 = [mem]
213 Pattern<(set R16, (load (plus R32, (plus (times imm, R32), imm))))>;
214 def MOVrm32 : X86Inst<"mov", 0x8B, MRMSrcMem , Arg32>, // R32 = [mem]
215 Pattern<(set R32, (load (plus R32, (plus (times imm, R32), imm))))>;
217 def MOVmr8 : X86Inst<"mov", 0x88, MRMDestMem, Arg8>; // [mem] = R8
218 def MOVmr16 : X86Inst<"mov", 0x89, MRMDestMem, Arg16>, OpSize; // [mem] = R16
219 def MOVmr32 : X86Inst<"mov", 0x89, MRMDestMem, Arg32>; // [mem] = R32
221 //===----------------------------------------------------------------------===//
222 // Fixed-Register Multiplication and Division Instructions...
225 // Extra precision multiplication
226 def MULr8 : X86Inst<"mul", 0xF6, MRM4r , Arg8 >, Imp<[AL],[AX]>; // AL,AH = AL*R8
227 def MULr16 : X86Inst<"mul", 0xF7, MRM4r , Arg16>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
228 def MULr32 : X86Inst<"mul", 0xF7, MRM4r , Arg32>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
229 def MULm8 : X86Inst<"mul", 0xF6, MRM4m , Arg8 >, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
230 def MULm16 : X86Inst<"mul", 0xF7, MRM4m , Arg16>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*[mem16]
231 def MULm32 : X86Inst<"mul", 0xF7, MRM4m , Arg32>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
233 // unsigned division/remainder
234 def DIVr8 : X86Inst<"div", 0xF6, MRM6r , Arg8 >, Imp<[AX],[AX]>; // AX/r8 = AL,AH
235 def DIVr16 : X86Inst<"div", 0xF7, MRM6r , Arg16>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
236 def DIVr32 : X86Inst<"div", 0xF7, MRM6r , Arg32>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
237 def DIVm8 : X86Inst<"div", 0xF6, MRM6m , Arg8 >, Imp<[AX],[AX]>; // AX/[mem8] = AL,AH
238 def DIVm16 : X86Inst<"div", 0xF7, MRM6m , Arg16>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[mem16] = AX,DX
239 def DIVm32 : X86Inst<"div", 0xF7, MRM6m , Arg32>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX
241 // signed division/remainder
242 def IDIVr8 : X86Inst<"idiv",0xF6, MRM7r , Arg8 >, Imp<[AX],[AX]>; // AX/r8 = AL,AH
243 def IDIVr16: X86Inst<"idiv",0xF7, MRM7r , Arg16>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
244 def IDIVr32: X86Inst<"idiv",0xF7, MRM7r , Arg32>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
245 def IDIVm8 : X86Inst<"idiv",0xF6, MRM7m , Arg8 >, Imp<[AX],[AX]>; // AX/[mem8] = AL,AH
246 def IDIVm16: X86Inst<"idiv",0xF7, MRM7m , Arg16>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[mem16] = AX,DX
247 def IDIVm32: X86Inst<"idiv",0xF7, MRM7m , Arg32>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX
249 // Sign-extenders for division
250 def CBW : X86Inst<"cbw", 0x98, RawFrm, Arg8 >, Imp<[AL],[AH]>; // AX = signext(AL)
251 def CWD : X86Inst<"cwd", 0x99, RawFrm, Arg8 >, Imp<[AX],[DX]>; // DX:AX = signext(AX)
252 def CDQ : X86Inst<"cdq", 0x99, RawFrm, Arg8 >, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX)
254 //===----------------------------------------------------------------------===//
255 // Two address Instructions...
257 let isTwoAddress = 1 in { // Define some helper classes to make defs shorter.
258 class I2A8 <string n, bits<8> o, Format F> : X86Inst<n, o, F, Arg8>;
259 class I2A16<string n, bits<8> o, Format F> : X86Inst<n, o, F, Arg16>;
260 class I2A32<string n, bits<8> o, Format F> : X86Inst<n, o, F, Arg32>;
263 // unary instructions
264 def NEGr8 : I2A8 <"neg", 0xF6, MRM3r >; // R8 = -R8 = 0-R8
265 def NEGr16 : I2A16<"neg", 0xF7, MRM3r >, OpSize; // R16 = -R16 = 0-R16
266 def NEGr32 : I2A32<"neg", 0xF7, MRM3r >; // R32 = -R32 = 0-R32
267 def NEGm8 : I2A8 <"neg", 0xF6, MRM3m >; // [mem8] = -[mem8] = 0-[mem8]
268 def NEGm16 : I2A16<"neg", 0xF7, MRM3m >, OpSize; // [mem16] = -[mem16] = 0-[mem16]
269 def NEGm32 : I2A32<"neg", 0xF7, MRM3m >; // [mem32] = -[mem32] = 0-[mem32]
271 def NOTr8 : I2A8 <"not", 0xF6, MRM2r >; // R8 = ~R8 = R8^-1
272 def NOTr16 : I2A16<"not", 0xF7, MRM2r >, OpSize; // R16 = ~R16 = R16^-1
273 def NOTr32 : I2A32<"not", 0xF7, MRM2r >; // R32 = ~R32 = R32^-1
274 def NOTm8 : I2A8 <"not", 0xF6, MRM2m >; // [mem8] = ~[mem8] = [mem8^-1]
275 def NOTm16 : I2A16<"not", 0xF7, MRM2m >, OpSize; // [mem16] = ~[mem16] = [mem16^-1]
276 def NOTm32 : I2A32<"not", 0xF7, MRM2m >; // [mem32] = ~[mem32] = [mem32^-1]
278 def INCr8 : I2A8 <"inc", 0xFE, MRM0r >; // ++R8
279 def INCr16 : I2A16<"inc", 0xFF, MRM0r >, OpSize; // ++R16
280 def INCr32 : I2A32<"inc", 0xFF, MRM0r >; // ++R32
281 def INCm8 : I2A8 <"inc", 0xFE, MRM0m >; // ++R8
282 def INCm16 : I2A16<"inc", 0xFF, MRM0m >, OpSize; // ++R16
283 def INCm32 : I2A32<"inc", 0xFF, MRM0m >; // ++R32
285 def DECr8 : I2A8 <"dec", 0xFE, MRM1r >; // --R8
286 def DECr16 : I2A16<"dec", 0xFF, MRM1r >, OpSize; // --R16
287 def DECr32 : I2A32<"dec", 0xFF, MRM1r >; // --R32
288 def DECm8 : I2A8 <"dec", 0xFE, MRM1m >; // --[mem8]
289 def DECm16 : I2A16<"dec", 0xFF, MRM1m >, OpSize; // --[mem16]
290 def DECm32 : I2A32<"dec", 0xFF, MRM1m >; // --[mem32]
295 def ADDrr8 : I2A8 <"add", 0x00, MRMDestReg>, Pattern<(set R8 , (plus R8 , R8 ))>;
296 def ADDrr16 : I2A16<"add", 0x01, MRMDestReg>, OpSize, Pattern<(set R16, (plus R16, R16))>;
297 def ADDrr32 : I2A32<"add", 0x01, MRMDestReg>, Pattern<(set R32, (plus R32, R32))>;
298 def ADDri8 : I2A8 <"add", 0x80, MRM0r >, Pattern<(set R8 , (plus R8 , imm))>;
299 def ADDri16 : I2A16<"add", 0x81, MRM0r >, OpSize, Pattern<(set R16, (plus R16, imm))>;
300 def ADDri32 : I2A32<"add", 0x81, MRM0r >, Pattern<(set R32, (plus R32, imm))>;
301 def ADDri16b : I2A8 <"add", 0x83, MRM0r >, OpSize; // ADDri with sign extended 8 bit imm
302 def ADDri32b : I2A8 <"add", 0x83, MRM0r >;
304 def ADDmr8 : I2A8 <"add", 0x00, MRMDestMem>; // [mem8] += R8
305 def ADDmr16 : I2A16<"add", 0x01, MRMDestMem>, OpSize; // [mem16] += R16
306 def ADDmr32 : I2A32<"add", 0x01, MRMDestMem>; // [mem32] += R32
307 def ADDrm8 : I2A8 <"add", 0x02, MRMSrcMem >; // R8 += [mem8]
308 def ADDrm16 : I2A16<"add", 0x03, MRMSrcMem >, OpSize; // R16 += [mem16]
309 def ADDrm32 : I2A32<"add", 0x03, MRMSrcMem >; // R32 += [mem32]
310 def ADDmi8 : I2A8 <"add", 0x80, MRMDestMem>; // [mem8] += I8
311 def ADDmi16 : I2A16<"add", 0x81, MRMDestMem>, OpSize; // [mem16] += I16
312 def ADDmi32 : I2A32<"add", 0x81, MRMDestMem>; // [mem32] += I8
313 def ADDmi16b : I2A8 <"add", 0x83, MRMDestMem>, OpSize; // [mem16] += I8
314 def ADDmi32b : I2A8 <"add", 0x83, MRMDestMem>; // [mem32] += I32
316 def ADCrr32 : I2A32<"adc", 0x11, MRMDestReg>; // R32 += R32+Carry
317 def ADCrm32 : I2A32<"adc", 0x11, MRMSrcMem >; // R32 += [mem32]+Carry
318 def ADCmr32 : I2A32<"adc", 0x13, MRMDestMem>; // [mem32] += R32+Carry
320 def SUBrr8 : I2A8 <"sub", 0x28, MRMDestReg>, Pattern<(set R8 , (minus R8 , R8 ))>;
321 def SUBrr16 : I2A16<"sub", 0x29, MRMDestReg>, OpSize, Pattern<(set R16, (minus R16, R16))>;
322 def SUBrr32 : I2A32<"sub", 0x29, MRMDestReg>, Pattern<(set R32, (minus R32, R32))>;
323 def SUBri8 : I2A8 <"sub", 0x80, MRM5r >, Pattern<(set R8 , (minus R8 , imm))>;
324 def SUBri16 : I2A16<"sub", 0x81, MRM5r >, OpSize, Pattern<(set R16, (minus R16, imm))>;
325 def SUBri32 : I2A32<"sub", 0x81, MRM5r >, Pattern<(set R32, (minus R32, imm))>;
326 def SUBri16b : I2A8 <"sub", 0x83, MRM5r >, OpSize;
327 def SUBri32b : I2A8 <"sub", 0x83, MRM5r >;
329 def SUBmr8 : I2A8 <"sub", 0x28, MRMDestMem>; // [mem8] -= R8
330 def SUBmr16 : I2A16<"sub", 0x29, MRMDestMem>, OpSize; // [mem16] -= R16
331 def SUBmr32 : I2A32<"sub", 0x29, MRMDestMem>; // [mem32] -= R32
332 def SUBrm8 : I2A8 <"sub", 0x2A, MRMSrcMem >; // R8 -= [mem8]
333 def SUBrm16 : I2A16<"sub", 0x2B, MRMSrcMem >, OpSize; // R16 -= [mem16]
334 def SUBrm32 : I2A32<"sub", 0x2B, MRMSrcMem >; // R32 -= [mem32]
335 def SUBmi8 : I2A8 <"sub", 0x80, MRMDestMem>; // [mem8] -= I8
336 def SUBmi16 : I2A16<"sub", 0x81, MRMDestMem>, OpSize; // [mem16] -= I16
337 def SUBmi32 : I2A32<"sub", 0x81, MRMDestMem>; // [mem32] -= I8
338 def SUBmi16b : I2A8 <"sub", 0x83, MRMDestMem>, OpSize; // [mem16] -= I8
339 def SUBmi32b : I2A8 <"sub", 0x83, MRMDestMem>; // [mem32] -= I32
341 def SBBrr32 : I2A32<"sbb", 0x19, MRMDestReg>; // R32 -= R32+Borrow
342 def SBBrm32 : I2A32<"sbb", 0x19, MRMSrcMem >; // R32 -= [mem32]+Borrow
343 def SBBmr32 : I2A32<"sbb", 0x1B, MRMDestMem>; // [mem32] -= R32+Borrow
345 def IMULrr16 : I2A16<"imul", 0xAF, MRMSrcReg>, TB, OpSize, Pattern<(set R16, (times R16, R16))>;
346 def IMULrr32 : I2A32<"imul", 0xAF, MRMSrcReg>, TB , Pattern<(set R32, (times R32, R32))>;
347 def IMULrm16 : I2A16<"imul", 0xAF, MRMSrcMem>, TB, OpSize;
348 def IMULrm32 : I2A32<"imul", 0xAF, MRMSrcMem>, TB ;
351 // These are suprisingly enough not two address instructions!
352 def IMULrri16 : X86Inst<"imul", 0x69, MRMSrcReg, Arg16>, OpSize; // R16 = R16*I16
353 def IMULrri32 : X86Inst<"imul", 0x69, MRMSrcReg, Arg32>; // R32 = R32*I32
354 def IMULrri16b : X86Inst<"imul", 0x6B, MRMSrcReg, Arg8 >, OpSize; // R16 = R16*I8
355 def IMULrri32b : X86Inst<"imul", 0x6B, MRMSrcReg, Arg8 >; // R32 = R32*I8
356 def IMULrmi16 : X86Inst<"imul", 0x69, MRMSrcMem, Arg16>, OpSize; // R16 = [mem16]*I16
357 def IMULrmi32 : X86Inst<"imul", 0x69, MRMSrcMem, Arg32>; // R32 = [mem32]*I32
358 def IMULrmi16b : X86Inst<"imul", 0x6B, MRMSrcMem, Arg8 >, OpSize; // R16 = [mem16]*I8
359 def IMULrmi32b : X86Inst<"imul", 0x6B, MRMSrcMem, Arg8 >; // R32 = [mem32]*I8
363 // Logical operators...
364 def ANDrr8 : I2A8 <"and", 0x20, MRMDestReg>, Pattern<(set R8 , (and R8 , R8 ))>;
365 def ANDrr16 : I2A16<"and", 0x21, MRMDestReg>, OpSize, Pattern<(set R16, (and R16, R16))>;
366 def ANDrr32 : I2A32<"and", 0x21, MRMDestReg>, Pattern<(set R32, (and R32, R32))>;
367 def ANDmr8 : I2A8 <"and", 0x20, MRMDestMem>; // [mem8] &= R8
368 def ANDmr16 : I2A16<"and", 0x21, MRMDestMem>, OpSize; // [mem16] &= R16
369 def ANDmr32 : I2A32<"and", 0x21, MRMDestMem>; // [mem32] &= R32
370 def ANDrm8 : I2A8 <"and", 0x22, MRMSrcMem >; // R8 &= [mem8]
371 def ANDrm16 : I2A16<"and", 0x23, MRMSrcMem >, OpSize; // R16 &= [mem16]
372 def ANDrm32 : I2A32<"and", 0x23, MRMSrcMem >; // R32 &= [mem32]
374 def ANDri8 : I2A8 <"and", 0x80, MRM4r >, Pattern<(set R8 , (and R8 , imm))>;
375 def ANDri16 : I2A16<"and", 0x81, MRM4r >, OpSize, Pattern<(set R16, (and R16, imm))>;
376 def ANDri32 : I2A32<"and", 0x81, MRM4r >, Pattern<(set R32, (and R32, imm))>;
377 def ANDmi8 : I2A8 <"and", 0x80, MRM4m >; // [mem8] &= imm8
378 def ANDmi16 : I2A16<"and", 0x81, MRM4m >, OpSize; // [mem16] &= imm16
379 def ANDmi32 : I2A32<"and", 0x81, MRM4m >; // [mem32] &= imm32
381 def ANDri16b : I2A8 <"and", 0x83, MRM4r >, OpSize; // R16 &= imm8
382 def ANDri32b : I2A8 <"and", 0x83, MRM4r >; // R32 &= imm8
383 def ANDmi16b : I2A8 <"and", 0x83, MRM4m >, OpSize; // [mem16] &= imm8
384 def ANDmi32b : I2A8 <"and", 0x83, MRM4m >; // [mem32] &= imm8
389 def ORrr8 : I2A8 <"or" , 0x08, MRMDestReg>, Pattern<(set R8 , (or R8 , R8 ))>;
390 def ORrr16 : I2A16<"or" , 0x09, MRMDestReg>, OpSize, Pattern<(set R16, (or R16, R16))>;
391 def ORrr32 : I2A32<"or" , 0x09, MRMDestReg>, Pattern<(set R32, (or R32, R32))>;
392 def ORmr8 : I2A8 <"or" , 0x08, MRMDestMem>; // [mem8] |= R8
393 def ORmr16 : I2A16<"or" , 0x09, MRMDestMem>, OpSize; // [mem16] |= R16
394 def ORmr32 : I2A32<"or" , 0x09, MRMDestMem>; // [mem32] |= R32
395 def ORrm8 : I2A8 <"or" , 0x0A, MRMSrcMem >; // R8 |= [mem8]
396 def ORrm16 : I2A16<"or" , 0x0B, MRMSrcMem >, OpSize; // R16 |= [mem16]
397 def ORrm32 : I2A32<"or" , 0x0B, MRMSrcMem >; // R32 |= [mem32]
399 def ORri8 : I2A8 <"or" , 0x80, MRM1r >, Pattern<(set R8 , (or R8 , imm))>;
400 def ORri16 : I2A16<"or" , 0x81, MRM1r >, OpSize, Pattern<(set R16, (or R16, imm))>;
401 def ORri32 : I2A32<"or" , 0x81, MRM1r >, Pattern<(set R32, (or R32, imm))>;
402 def ORmi8 : I2A8 <"or" , 0x80, MRM1m >; // [mem8] |= imm8
403 def ORmi16 : I2A16<"or" , 0x81, MRM1m >, OpSize; // [mem16] |= imm16
404 def ORmi32 : I2A32<"or" , 0x81, MRM1m >; // [mem32] |= imm32
406 def ORri16b : I2A8 <"or" , 0x83, MRM1r >, OpSize; // R16 |= imm8
407 def ORri32b : I2A8 <"or" , 0x83, MRM1r >; // R32 |= imm8
408 def ORmi16b : I2A8 <"or" , 0x83, MRM1m >, OpSize; // [mem16] |= imm8
409 def ORmi32b : I2A8 <"or" , 0x83, MRM1m >; // [mem32] |= imm8
412 def XORrr8 : I2A8 <"xor", 0x30, MRMDestReg>, Pattern<(set R8 , (xor R8 , R8 ))>;
413 def XORrr16 : I2A16<"xor", 0x31, MRMDestReg>, OpSize, Pattern<(set R16, (xor R16, R16))>;
414 def XORrr32 : I2A32<"xor", 0x31, MRMDestReg>, Pattern<(set R32, (xor R32, R32))>;
415 def XORmr8 : I2A8 <"xor", 0x30, MRMDestMem>; // [mem8] ^= R8
416 def XORmr16 : I2A16<"xor", 0x31, MRMDestMem>, OpSize; // [mem16] ^= R16
417 def XORmr32 : I2A32<"xor", 0x31, MRMDestMem>; // [mem32] ^= R32
418 def XORrm8 : I2A8 <"xor", 0x32, MRMSrcMem >; // R8 ^= [mem8]
419 def XORrm16 : I2A16<"xor", 0x33, MRMSrcMem >, OpSize; // R16 ^= [mem16]
420 def XORrm32 : I2A32<"xor", 0x33, MRMSrcMem >; // R32 ^= [mem32]
422 def XORri8 : I2A8 <"xor", 0x80, MRM6r >, Pattern<(set R8 , (xor R8 , imm))>;
423 def XORri16 : I2A16<"xor", 0x81, MRM6r >, OpSize, Pattern<(set R16, (xor R16, imm))>;
424 def XORri32 : I2A32<"xor", 0x81, MRM6r >, Pattern<(set R32, (xor R32, imm))>;
425 def XORmi8 : I2A8 <"xor", 0x80, MRM6m >; // [mem8] ^= R8
426 def XORmi16 : I2A16<"xor", 0x81, MRM6m >, OpSize; // [mem16] ^= R16
427 def XORmi32 : I2A32<"xor", 0x81, MRM6m >; // [mem32] ^= R32
429 def XORri16b : I2A8 <"xor", 0x83, MRM6r >, OpSize; // R16 ^= imm8
430 def XORri32b : I2A8 <"xor", 0x83, MRM6r >; // R32 ^= imm8
431 def XORmi16b : I2A8 <"xor", 0x83, MRM6m >, OpSize; // [mem16] ^= imm8
432 def XORmi32b : I2A8 <"xor", 0x83, MRM6m >; // [mem32] ^= imm8
434 // Test instructions are just like AND, except they don't generate a result.
435 def TESTrr8 : X86Inst<"test", 0x84, MRMDestReg, Arg8 >; // flags = R8 & R8
436 def TESTrr16 : X86Inst<"test", 0x85, MRMDestReg, Arg16>, OpSize; // flags = R16 & R16
437 def TESTrr32 : X86Inst<"test", 0x85, MRMDestReg, Arg32>; // flags = R32 & R32
438 def TESTmr8 : X86Inst<"test", 0x84, MRMDestMem, Arg8 >; // flags = [mem8] & R8
439 def TESTmr16 : X86Inst<"test", 0x85, MRMDestMem, Arg16>, OpSize; // flags = [mem16] & R16
440 def TESTmr32 : X86Inst<"test", 0x85, MRMDestMem, Arg32>; // flags = [mem32] & R32
441 def TESTrm8 : X86Inst<"test", 0x84, MRMSrcMem , Arg8 >; // flags = R8 & [mem8]
442 def TESTrm16 : X86Inst<"test", 0x85, MRMSrcMem , Arg16>, OpSize; // flags = R16 & [mem16]
443 def TESTrm32 : X86Inst<"test", 0x85, MRMSrcMem , Arg32>; // flags = R32 & [mem32]
445 def TESTri8 : X86Inst<"test", 0xF6, MRM0r , Arg8 >; // flags = R8 & imm8
446 def TESTri16 : X86Inst<"test", 0xF7, MRM0r , Arg16>, OpSize; // flags = R16 & imm16
447 def TESTri32 : X86Inst<"test", 0xF7, MRM0r , Arg32>; // flags = R32 & imm32
448 def TESTmi8 : X86Inst<"test", 0xF6, MRM0m , Arg8 >; // flags = [mem8] & imm8
449 def TESTmi16 : X86Inst<"test", 0xF7, MRM0m , Arg16>, OpSize; // flags = [mem16] & imm16
450 def TESTmi32 : X86Inst<"test", 0xF7, MRM0m , Arg32>; // flags = [mem32] & imm32
452 // Shift instructions
453 class UsesCL { list<Register> Uses = [CL]; bit printImplicitUses = 1; }
455 def SHLrCL8 : I2A8 <"shl", 0xD2, MRM4r > , UsesCL; // R8 <<= cl
456 def SHLrCL16 : I2A8 <"shl", 0xD3, MRM4r >, OpSize, UsesCL; // R16 <<= cl
457 def SHLrCL32 : I2A8 <"shl", 0xD3, MRM4r > , UsesCL; // R32 <<= cl
458 def SHLmCL8 : I2A8 <"shl", 0xD2, MRM4m > , UsesCL; // [mem8] <<= cl
459 def SHLmCL16 : I2A8 <"shl", 0xD3, MRM4m >, OpSize, UsesCL; // [mem16] <<= cl
460 def SHLmCL32 : I2A8 <"shl", 0xD3, MRM4m > , UsesCL; // [mem32] <<= cl
462 def SHLri8 : I2A8 <"shl", 0xC0, MRM4r >; // R8 <<= imm8
463 def SHLri16 : I2A8 <"shl", 0xC1, MRM4r >, OpSize; // R16 <<= imm16
464 def SHLri32 : I2A8 <"shl", 0xC1, MRM4r >; // R32 <<= imm32
465 def SHLmi8 : I2A8 <"shl", 0xC0, MRM4m >; // [mem8] <<= imm8
466 def SHLmi16 : I2A8 <"shl", 0xC1, MRM4m >, OpSize; // [mem16] <<= imm16
467 def SHLmi32 : I2A8 <"shl", 0xC1, MRM4m >; // [mem32] <<= imm32
469 def SHRrCL8 : I2A8 <"shr", 0xD2, MRM5r > , UsesCL; // R8 >>= cl
470 def SHRrCL16 : I2A8 <"shr", 0xD3, MRM5r >, OpSize, UsesCL; // R16 >>= cl
471 def SHRrCL32 : I2A8 <"shr", 0xD3, MRM5r > , UsesCL; // R32 >>= cl
472 def SHRmCL8 : I2A8 <"shr", 0xD2, MRM5m > , UsesCL; // [mem8] >>= cl
473 def SHRmCL16 : I2A8 <"shr", 0xD3, MRM5m >, OpSize, UsesCL; // [mem16] >>= cl
474 def SHRmCL32 : I2A8 <"shr", 0xD3, MRM5m > , UsesCL; // [mem32] >>= cl
476 def SHRri8 : I2A8 <"shr", 0xC0, MRM5r >; // R8 >>= imm8
477 def SHRri16 : I2A8 <"shr", 0xC1, MRM5r >, OpSize; // R16 >>= imm16
478 def SHRri32 : I2A8 <"shr", 0xC1, MRM5r >; // R32 >>= imm32
479 def SHRmi8 : I2A8 <"shr", 0xC0, MRM5m >; // [mem8] >>= imm8
480 def SHRmi16 : I2A8 <"shr", 0xC1, MRM5m >, OpSize; // [mem16] >>= imm16
481 def SHRmi32 : I2A8 <"shr", 0xC1, MRM5m >; // [mem32] >>= imm32
483 def SARrCL8 : I2A8 <"sar", 0xD2, MRM7r > , UsesCL; // R8 >>>= cl
484 def SARrCL16 : I2A8 <"sar", 0xD3, MRM7r >, OpSize, UsesCL; // R16 >>>= cl
485 def SARrCL32 : I2A8 <"sar", 0xD3, MRM7r > , UsesCL; // R32 >>>= cl
486 def SARmCL8 : I2A8 <"sar", 0xD2, MRM7m > , UsesCL; // [mem8] >>>= cl
487 def SARmCL16 : I2A8 <"sar", 0xD3, MRM7m >, OpSize, UsesCL; // [mem16] >>>= cl
488 def SARmCL32 : I2A8 <"sar", 0xD3, MRM7m > , UsesCL; // [mem32] >>>= cl
490 def SARri8 : I2A8 <"sar", 0xC0, MRM7r >; // R8 >>>= imm8
491 def SARri16 : I2A8 <"sar", 0xC1, MRM7r >, OpSize; // R16 >>>= imm16
492 def SARri32 : I2A8 <"sar", 0xC1, MRM7r >; // R32 >>>= imm32
493 def SARmi8 : I2A8 <"sar", 0xC0, MRM7m >; // [mem8] >>>= imm8
494 def SARmi16 : I2A8 <"sar", 0xC1, MRM7m >, OpSize; // [mem16] >>>= imm16
495 def SARmi32 : I2A8 <"sar", 0xC1, MRM7m >; // [mem32] >>>= imm32
497 def SHLDrrCL32 : I2A8 <"shld", 0xA5, MRMDestReg>, TB, UsesCL; // R32 <<= R32,R32 cl
498 def SHLDmrCL32 : I2A8 <"shld", 0xA5, MRMDestMem>, TB, UsesCL; // [mem32] <<= [mem32],R32 cl
499 def SHLDrri32 : I2A8 <"shld", 0xA4, MRMDestReg>, TB; // R32 <<= R32,R32 imm8
500 def SHLDmri32 : I2A8 <"shld", 0xA4, MRMDestMem>, TB; // [mem32] <<= [mem32],R32 imm8
502 def SHRDrrCL32 : I2A8 <"shrd", 0xAD, MRMDestReg>, TB, UsesCL; // R32 >>= R32,R32 cl
503 def SHRDmrCL32 : I2A8 <"shrd", 0xAD, MRMDestMem>, TB, UsesCL; // [mem32] >>= [mem32],R32 cl
504 def SHRDrri32 : I2A8 <"shrd", 0xAC, MRMDestReg>, TB; // R32 >>= R32,R32 imm8
505 def SHRDmri32 : I2A8 <"shrd", 0xAC, MRMDestMem>, TB; // [mem32] >>= [mem32],R32 imm8
507 // Condition code ops, incl. set if equal/not equal/...
508 def SAHF : X86Inst<"sahf" , 0x9E, RawFrm, Arg8>, Imp<[AH],[]>; // flags = AH
510 def SETBr : X86Inst<"setb" , 0x92, MRM0r , Arg8>, TB; // R8 = < unsign
511 def SETBm : X86Inst<"setb" , 0x92, MRM0m , Arg8>, TB; // [mem8] = < unsign
512 def SETAEr : X86Inst<"setae", 0x93, MRM0r , Arg8>, TB; // R8 = >= unsign
513 def SETAEm : X86Inst<"setae", 0x93, MRM0m , Arg8>, TB; // [mem8] = >= unsign
514 def SETEr : X86Inst<"sete" , 0x94, MRM0r , Arg8>, TB; // R8 = ==
515 def SETEm : X86Inst<"sete" , 0x94, MRM0m , Arg8>, TB; // [mem8] = ==
516 def SETNEr : X86Inst<"setne", 0x95, MRM0r , Arg8>, TB; // R8 = !=
517 def SETNEm : X86Inst<"setne", 0x95, MRM0m , Arg8>, TB; // [mem8] = !=
518 def SETBEr : X86Inst<"setbe", 0x96, MRM0r , Arg8>, TB; // R8 = <= unsign
519 def SETBEm : X86Inst<"setbe", 0x96, MRM0m , Arg8>, TB; // [mem8] = <= unsign
520 def SETAr : X86Inst<"seta" , 0x97, MRM0r , Arg8>, TB; // R8 = > signed
521 def SETAm : X86Inst<"seta" , 0x97, MRM0m , Arg8>, TB; // [mem8] = > signed
522 def SETSr : X86Inst<"sets" , 0x98, MRM0r , Arg8>, TB; // R8 = <sign bit>
523 def SETSm : X86Inst<"sets" , 0x98, MRM0m , Arg8>, TB; // [mem8] = <sign bit>
524 def SETNSr : X86Inst<"setns", 0x99, MRM0r , Arg8>, TB; // R8 = !<sign bit>
525 def SETNSm : X86Inst<"setns", 0x99, MRM0m , Arg8>, TB; // [mem8] = !<sign bit>
526 def SETLr : X86Inst<"setl" , 0x9C, MRM0r , Arg8>, TB; // R8 = < signed
527 def SETLm : X86Inst<"setl" , 0x9C, MRM0m , Arg8>, TB; // [mem8] = < signed
528 def SETGEr : X86Inst<"setge", 0x9D, MRM0r , Arg8>, TB; // R8 = >= signed
529 def SETGEm : X86Inst<"setge", 0x9D, MRM0m , Arg8>, TB; // [mem8] = >= signed
530 def SETLEr : X86Inst<"setle", 0x9E, MRM0r , Arg8>, TB; // R8 = <= signed
531 def SETLEm : X86Inst<"setle", 0x9E, MRM0m , Arg8>, TB; // [mem8] = <= signed
532 def SETGr : X86Inst<"setg" , 0x9F, MRM0r , Arg8>, TB; // R8 = < signed
533 def SETGm : X86Inst<"setg" , 0x9F, MRM0m , Arg8>, TB; // [mem8] = < signed
535 // Conditional moves. These are modelled as X = cmovXX Y, Z. Eventually
536 // register allocated to cmovXX XY, Z
537 def CMOVErr16 : I2A16<"cmove", 0x44, MRMSrcReg>, TB, OpSize; // if ==, R16 = R16
538 def CMOVNErr32: I2A32<"cmovne",0x45, MRMSrcReg>, TB; // if !=, R32 = R32
539 def CMOVSrr32 : I2A32<"cmovs", 0x48, MRMSrcReg>, TB; // if signed, R32 = R32
541 // Integer comparisons
542 def CMPrr8 : X86Inst<"cmp", 0x38, MRMDestReg, Arg8 >; // compare R8, R8
543 def CMPrr16 : X86Inst<"cmp", 0x39, MRMDestReg, Arg16>, OpSize; // compare R16, R16
544 def CMPrr32 : X86Inst<"cmp", 0x39, MRMDestReg, Arg32>, // compare R32, R32
545 Pattern<(isVoid (unspec2 R32, R32))>;
546 def CMPmr8 : X86Inst<"cmp", 0x38, MRMDestMem, Arg8 >; // compare [mem8], R8
547 def CMPmr16 : X86Inst<"cmp", 0x39, MRMDestMem, Arg16>, OpSize; // compare [mem16], R16
548 def CMPmr32 : X86Inst<"cmp", 0x39, MRMDestMem, Arg32>; // compare [mem32], R32
549 def CMPrm8 : X86Inst<"cmp", 0x3A, MRMSrcMem , Arg8 >; // compare R8, [mem8]
550 def CMPrm16 : X86Inst<"cmp", 0x3B, MRMSrcMem , Arg16>, OpSize; // compare R16, [mem16]
551 def CMPrm32 : X86Inst<"cmp", 0x3B, MRMSrcMem , Arg32>; // compare R32, [mem32]
552 def CMPri8 : X86Inst<"cmp", 0x80, MRM7r , Arg8 >; // compare R8, imm8
553 def CMPri16 : X86Inst<"cmp", 0x81, MRM7r , Arg16>, OpSize; // compare R16, imm16
554 def CMPri32 : X86Inst<"cmp", 0x81, MRM7r , Arg32>; // compare R32, imm32
555 def CMPmi8 : X86Inst<"cmp", 0x80, MRM7m , Arg8 >; // compare [mem8], imm8
556 def CMPmi16 : X86Inst<"cmp", 0x81, MRM7m , Arg16>, OpSize; // compare [mem16], imm16
557 def CMPmi32 : X86Inst<"cmp", 0x81, MRM7m , Arg32>; // compare [mem32], imm32
559 // Sign/Zero extenders
560 def MOVSXr16r8 : X86Inst<"movsx", 0xBE, MRMSrcReg, Arg8>, TB, OpSize; // R16 = signext(R8)
561 def MOVSXr32r8 : X86Inst<"movsx", 0xBE, MRMSrcReg, Arg8>, TB; // R32 = signext(R8)
562 def MOVSXr32r16: X86Inst<"movsx", 0xBF, MRMSrcReg, Arg16>,TB; // R32 = signext(R16)
563 def MOVSXr16m8 : X86Inst<"movsx", 0xBE, MRMSrcMem, Arg8>, TB, OpSize; // R16 = signext([mem8])
564 def MOVSXr32m8 : X86Inst<"movsx", 0xBE, MRMSrcMem, Arg8>, TB; // R32 = signext([mem8])
565 def MOVSXr32m16: X86Inst<"movsx", 0xBF, MRMSrcMem, Arg16>,TB; // R32 = signext([mem16])
567 def MOVZXr16r8 : X86Inst<"movzx", 0xB6, MRMSrcReg, Arg8>, TB, OpSize; // R16 = zeroext(R8)
568 def MOVZXr32r8 : X86Inst<"movzx", 0xB6, MRMSrcReg, Arg8>, TB; // R32 = zeroext(R8)
569 def MOVZXr32r16: X86Inst<"movzx", 0xB7, MRMSrcReg, Arg16>,TB; // R32 = zeroext(R16)
570 def MOVZXr16m8 : X86Inst<"movzx", 0xB6, MRMSrcMem, Arg8>, TB, OpSize; // R16 = zeroext([mem8])
571 def MOVZXr32m8 : X86Inst<"movzx", 0xB6, MRMSrcMem, Arg8>, TB; // R32 = zeroext([mem8])
572 def MOVZXr32m16: X86Inst<"movzx", 0xB7, MRMSrcMem, Arg16>,TB; // R32 = zeroext([mem16])
575 //===----------------------------------------------------------------------===//
576 // Floating point support
577 //===----------------------------------------------------------------------===//
579 // FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP'
581 // Floating point pseudo instructions...
582 class FPInst<string n, bits<8> o, Format F, ArgType t, FPFormat fp>
583 : X86Inst<n, o, F, t> { let FPForm = fp; let FPFormBits = FPForm.Value; }
585 // Pseudo instructions for floating point. We use these pseudo instructions
586 // because they can be expanded by the fp spackifier into one of many different
587 // forms of instructions for doing these operations. Until the stackifier runs,
588 // we prefer to be abstract.
589 def FpMOV : FPInst<"FMOV", 0, Pseudo, ArgF80, SpecialFP>; // f1 = fmov f2
590 def FpADD : FPInst<"FADD", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fadd f2, f3
591 def FpSUB : FPInst<"FSUB", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fsub f2, f3
592 def FpMUL : FPInst<"FMUL", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fmul f2, f3
593 def FpDIV : FPInst<"FDIV", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fdiv f2, f3
595 def FpUCOM : FPInst<"FUCOM", 0, Pseudo, ArgF80, TwoArgFP>; // FPSW = fucom f1, f2
597 def FpGETRESULT : FPInst<"FGETRESULT",0, Pseudo, ArgF80, SpecialFP>; // FPR = ST(0)
599 def FpSETRESULT : FPInst<"FSETRESULT",0, Pseudo, ArgF80, SpecialFP>; // ST(0) = FPR
601 // Floating point loads & stores...
602 def FLDrr : FPInst<"fld" , 0xC0, AddRegFrm, ArgF80, NotFP>, D9; // push(ST(i))
603 def FLDr32 : FPInst<"fld" , 0xD9, MRM0m , ArgF32, ZeroArgFP>; // load float
604 def FLDr64 : FPInst<"fld" , 0xDD, MRM0m , ArgF64, ZeroArgFP>; // load double
605 def FLDr80 : FPInst<"fld" , 0xDB, MRM5m , ArgF80, ZeroArgFP>; // load extended
606 def FILDr16 : FPInst<"fild" , 0xDF, MRM0m , Arg16 , ZeroArgFP>; // load signed short
607 def FILDr32 : FPInst<"fild" , 0xDB, MRM0m , Arg32 , ZeroArgFP>; // load signed int
608 def FILDr64 : FPInst<"fild" , 0xDF, MRM5m , Arg64 , ZeroArgFP>; // load signed long
610 def FSTr32 : FPInst<"fst" , 0xD9, MRM2m , ArgF32, OneArgFP>; // store float
611 def FSTr64 : FPInst<"fst" , 0xDD, MRM2m , ArgF64, OneArgFP>; // store double
612 def FSTPr32 : FPInst<"fstp", 0xD9, MRM3m , ArgF32, OneArgFP>; // store float, pop
613 def FSTPr64 : FPInst<"fstp", 0xDD, MRM3m , ArgF64, OneArgFP>; // store double, pop
614 def FSTPr80 : FPInst<"fstp", 0xDB, MRM7m , ArgF80, OneArgFP>; // store extended, pop
615 def FSTrr : FPInst<"fst" , 0xD0, AddRegFrm, ArgF80, NotFP >, DD; // ST(i) = ST(0)
616 def FSTPrr : FPInst<"fstp", 0xD8, AddRegFrm, ArgF80, NotFP >, DD; // ST(i) = ST(0), pop
618 def FISTr16 : FPInst<"fist", 0xDF, MRM2m , Arg16 , OneArgFP>; // store signed short
619 def FISTr32 : FPInst<"fist", 0xDB, MRM2m , Arg32 , OneArgFP>; // store signed int
620 def FISTPr16 : FPInst<"fistp", 0xDF, MRM3m , Arg16 , NotFP >; // store signed short, pop
621 def FISTPr32 : FPInst<"fistp", 0xDB, MRM3m , Arg32 , NotFP >; // store signed int, pop
622 def FISTPr64 : FPInst<"fistpll", 0xDF, MRM7m , Arg64 , OneArgFP>; // store signed long, pop
624 def FXCH : FPInst<"fxch", 0xC8, AddRegFrm, ArgF80, NotFP>, D9; // fxch ST(i), ST(0)
626 // Floating point constant loads...
627 def FLD0 : FPInst<"fldz", 0xEE, RawFrm, ArgF80, ZeroArgFP>, D9;
628 def FLD1 : FPInst<"fld1", 0xE8, RawFrm, ArgF80, ZeroArgFP>, D9;
631 // Unary operations...
632 def FCHS : FPInst<"fchs", 0xE0, RawFrm, ArgF80, OneArgFPRW>, D9; // f1 = fchs f2
634 def FTST : FPInst<"ftst", 0xE4, RawFrm, ArgF80, OneArgFP>, D9; // ftst ST(0)
636 // Binary arithmetic operations...
637 class FPST0rInst<string n, bits<8> o>
638 : X86Inst<n, o, AddRegFrm, ArgF80>, D8 {
639 list<Register> Uses = [ST0];
640 list<Register> Defs = [ST0];
642 class FPrST0Inst<string n, bits<8> o>
643 : X86Inst<n, o, AddRegFrm, ArgF80>, DC {
644 bit printImplicitUses = 1;
645 list<Register> Uses = [ST0];
647 class FPrST0PInst<string n, bits<8> o>
648 : X86Inst<n, o, AddRegFrm, ArgF80>, DE {
649 list<Register> Uses = [ST0];
652 def FADDST0r : FPST0rInst <"fadd", 0xC0>;
653 def FADDrST0 : FPrST0Inst <"fadd", 0xC0>;
654 def FADDPrST0 : FPrST0PInst<"faddp", 0xC0>;
656 def FSUBRST0r : FPST0rInst <"fsubr", 0xE8>;
657 def FSUBrST0 : FPrST0Inst <"fsub", 0xE8>;
658 def FSUBPrST0 : FPrST0PInst<"fsubp", 0xE8>;
660 def FSUBST0r : FPST0rInst <"fsub", 0xE0>;
661 def FSUBRrST0 : FPrST0Inst <"fsubr", 0xE0>;
662 def FSUBRPrST0 : FPrST0PInst<"fsubrp", 0xE0>;
664 def FMULST0r : FPST0rInst <"fmul", 0xC8>;
665 def FMULrST0 : FPrST0Inst <"fmul", 0xC8>;
666 def FMULPrST0 : FPrST0PInst<"fmulp", 0xC8>;
668 def FDIVRST0r : FPST0rInst <"fdivr", 0xF8>;
669 def FDIVrST0 : FPrST0Inst <"fdiv", 0xF8>;
670 def FDIVPrST0 : FPrST0PInst<"fdivp", 0xF8>;
672 def FDIVST0r : FPST0rInst <"fdiv", 0xF0>; // ST(0) = ST(0) / ST(i)
673 def FDIVRrST0 : FPrST0Inst <"fdivr", 0xF0>; // ST(i) = ST(0) / ST(i)
674 def FDIVRPrST0 : FPrST0PInst<"fdivrp", 0xF0>; // ST(i) = ST(0) / ST(i), pop
676 // Floating point compares
677 def FUCOMr : X86Inst<"fucom" , 0xE0, AddRegFrm, ArgF80>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i)
678 def FUCOMPr : X86Inst<"fucomp" , 0xE8, AddRegFrm, ArgF80>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i), pop
679 def FUCOMPPr : X86Inst<"fucompp", 0xE9, RawFrm , ArgF80>, DA, Imp<[ST0],[]>; // compare ST(0) with ST(1), pop, pop
681 // Floating point flag ops
682 def FNSTSWr8 : X86Inst<"fnstsw" , 0xE0, RawFrm , ArgF80>, DF, Imp<[],[AX]>; // AX = fp flags
683 def FNSTCWm16 : X86Inst<"fnstcw" , 0xD9, MRM7m , Arg16 >; // [mem16] = X87 control world
684 def FLDCWm16 : X86Inst<"fldcw" , 0xD9, MRM5m , Arg16 >; // X87 control world = [mem16]
687 //===----------------------------------------------------------------------===//
688 // Instruction Expanders
691 def RET_R32 : Expander<(ret R32:$reg),
692 [(MOVrr32 EAX, R32:$reg),
695 // FIXME: This should eventually just be implemented by defining a frameidx as a
696 // value address for a load.
697 def LOAD_FI16 : Expander<(set R16:$dest, (load frameidx:$fi)),
698 [(MOVrm16 R16:$dest, frameidx:$fi, 1, 0/*NoReg*/, 0)]>;
700 def LOAD_FI32 : Expander<(set R32:$dest, (load frameidx:$fi)),
701 [(MOVrm32 R32:$dest, frameidx:$fi, 1, 0/*NoReg*/, 0)]>;
704 def LOAD_R16 : Expander<(set R16:$dest, (load R32:$src)),
705 [(MOVrm16 R16:$dest, R32:$src, 1, 0/*NoReg*/, 0)]>;
707 def LOAD_R32 : Expander<(set R32:$dest, (load R32:$src)),
708 [(MOVrm32 R32:$dest, R32:$src, 1, 0/*NoReg*/, 0)]>;
710 def BR_EQ : Expander<(brcond (seteq R32:$a1, R32:$a2),
711 basicblock:$d1, basicblock:$d2),
712 [(CMPrr32 R32:$a1, R32:$a2),
714 (JMP basicblock:$d2)]>;