1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
33 def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
37 def SDTX86BrCond : SDTypeProfile<0, 3,
38 [SDTCisVT<0, OtherVT>,
39 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
41 def SDTX86SetCC : SDTypeProfile<1, 2,
43 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
47 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
49 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
50 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
51 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
53 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
54 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
57 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
59 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
61 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
63 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
65 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
67 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
69 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
71 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
73 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
74 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
75 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
76 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
78 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
80 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
82 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
83 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
85 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
87 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
88 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
90 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
91 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
93 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
94 [SDNPHasChain, SDNPMayStore,
95 SDNPMayLoad, SDNPMemOperand]>;
96 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
97 [SDNPHasChain, SDNPMayStore,
98 SDNPMayLoad, SDNPMemOperand]>;
99 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
100 [SDNPHasChain, SDNPMayStore,
101 SDNPMayLoad, SDNPMemOperand]>;
102 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
103 [SDNPHasChain, SDNPMayStore,
104 SDNPMayLoad, SDNPMemOperand]>;
105 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
106 [SDNPHasChain, SDNPMayStore,
107 SDNPMayLoad, SDNPMemOperand]>;
108 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
109 [SDNPHasChain, SDNPMayStore,
110 SDNPMayLoad, SDNPMemOperand]>;
111 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
112 [SDNPHasChain, SDNPMayStore,
113 SDNPMayLoad, SDNPMemOperand]>;
114 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
115 [SDNPHasChain, SDNPOptInFlag]>;
117 def X86callseq_start :
118 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
119 [SDNPHasChain, SDNPOutFlag]>;
121 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
122 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
124 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
125 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
127 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
128 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
129 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
130 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
133 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
134 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
136 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
137 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
139 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
140 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
141 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
142 SDT_X86SegmentBaseAddress, []>;
144 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
147 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
148 [SDNPHasChain, SDNPOptInFlag]>;
150 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags>;
151 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
152 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags>;
153 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>;
154 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
155 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
157 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
159 //===----------------------------------------------------------------------===//
160 // X86 Operand Definitions.
163 def i32imm_pcrel : Operand<i32> {
164 let PrintMethod = "print_pcrel_imm";
167 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
168 // the index operand of an address, to conform to x86 encoding restrictions.
169 def ptr_rc_nosp : PointerLikeRegClass<1>;
171 // *mem - Operand definitions for the funky X86 addressing mode operands.
173 def X86MemAsmOperand : AsmOperandClass {
177 class X86MemOperand<string printMethod> : Operand<iPTR> {
178 let PrintMethod = printMethod;
179 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
180 let ParserMatchClass = X86MemAsmOperand;
183 def i8mem : X86MemOperand<"printi8mem">;
184 def i16mem : X86MemOperand<"printi16mem">;
185 def i32mem : X86MemOperand<"printi32mem">;
186 def i64mem : X86MemOperand<"printi64mem">;
187 def i128mem : X86MemOperand<"printi128mem">;
188 def i256mem : X86MemOperand<"printi256mem">;
189 def f32mem : X86MemOperand<"printf32mem">;
190 def f64mem : X86MemOperand<"printf64mem">;
191 def f80mem : X86MemOperand<"printf80mem">;
192 def f128mem : X86MemOperand<"printf128mem">;
193 def f256mem : X86MemOperand<"printf256mem">;
195 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
196 // plain GR64, so that it doesn't potentially require a REX prefix.
197 def i8mem_NOREX : Operand<i64> {
198 let PrintMethod = "printi8mem";
199 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
200 let ParserMatchClass = X86MemAsmOperand;
203 def lea32mem : Operand<i32> {
204 let PrintMethod = "printlea32mem";
205 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
206 let ParserMatchClass = X86MemAsmOperand;
209 def SSECC : Operand<i8> {
210 let PrintMethod = "printSSECC";
213 def piclabel: Operand<i32> {
214 let PrintMethod = "printPICLabel";
217 def ImmSExt8AsmOperand : AsmOperandClass {
218 let Name = "ImmSExt8";
219 let SuperClass = ImmAsmOperand;
222 // A couple of more descriptive operand definitions.
223 // 16-bits but only 8 bits are significant.
224 def i16i8imm : Operand<i16> {
225 let ParserMatchClass = ImmSExt8AsmOperand;
227 // 32-bits but only 8 bits are significant.
228 def i32i8imm : Operand<i32> {
229 let ParserMatchClass = ImmSExt8AsmOperand;
232 // Branch targets have OtherVT type and print as pc-relative values.
233 def brtarget : Operand<OtherVT> {
234 let PrintMethod = "print_pcrel_imm";
237 def brtarget8 : Operand<OtherVT> {
238 let PrintMethod = "print_pcrel_imm";
241 //===----------------------------------------------------------------------===//
242 // X86 Complex Pattern Definitions.
245 // Define X86 specific addressing mode.
246 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
247 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
248 [add, sub, mul, X86mul_imm, shl, or, frameindex],
250 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
251 [tglobaltlsaddr], []>;
253 //===----------------------------------------------------------------------===//
254 // X86 Instruction Predicate Definitions.
255 def HasMMX : Predicate<"Subtarget->hasMMX()">;
256 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
257 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
258 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
259 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
260 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
261 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
262 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
263 def HasAVX : Predicate<"Subtarget->hasAVX()">;
264 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
265 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
266 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
267 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
268 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
269 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
270 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
271 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
272 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
273 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
274 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
275 "TM.getCodeModel() != CodeModel::Kernel">;
276 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
277 "TM.getCodeModel() == CodeModel::Kernel">;
278 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
279 def OptForSpeed : Predicate<"!OptForSize">;
280 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
281 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
283 //===----------------------------------------------------------------------===//
284 // X86 Instruction Format Definitions.
287 include "X86InstrFormats.td"
289 //===----------------------------------------------------------------------===//
290 // Pattern fragments...
293 // X86 specific condition code. These correspond to CondCode in
294 // X86InstrInfo.h. They must be kept in synch.
295 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
296 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
297 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
298 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
299 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
300 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
301 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
302 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
303 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
304 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
305 def X86_COND_NO : PatLeaf<(i8 10)>;
306 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
307 def X86_COND_NS : PatLeaf<(i8 12)>;
308 def X86_COND_O : PatLeaf<(i8 13)>;
309 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
310 def X86_COND_S : PatLeaf<(i8 15)>;
312 def i16immSExt8 : PatLeaf<(i16 imm), [{
313 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
314 // sign extended field.
315 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
318 def i32immSExt8 : PatLeaf<(i32 imm), [{
319 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
320 // sign extended field.
321 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
324 // Helper fragments for loads.
325 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
326 // known to be 32-bit aligned or better. Ditto for i8 to i16.
327 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
328 LoadSDNode *LD = cast<LoadSDNode>(N);
329 if (const Value *Src = LD->getSrcValue())
330 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
331 if (PT->getAddressSpace() > 255)
333 ISD::LoadExtType ExtType = LD->getExtensionType();
334 if (ExtType == ISD::NON_EXTLOAD)
336 if (ExtType == ISD::EXTLOAD)
337 return LD->getAlignment() >= 2 && !LD->isVolatile();
341 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
342 LoadSDNode *LD = cast<LoadSDNode>(N);
343 if (const Value *Src = LD->getSrcValue())
344 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
345 if (PT->getAddressSpace() > 255)
347 ISD::LoadExtType ExtType = LD->getExtensionType();
348 if (ExtType == ISD::EXTLOAD)
349 return LD->getAlignment() >= 2 && !LD->isVolatile();
353 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
354 LoadSDNode *LD = cast<LoadSDNode>(N);
355 if (const Value *Src = LD->getSrcValue())
356 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
357 if (PT->getAddressSpace() > 255)
359 ISD::LoadExtType ExtType = LD->getExtensionType();
360 if (ExtType == ISD::NON_EXTLOAD)
362 if (ExtType == ISD::EXTLOAD)
363 return LD->getAlignment() >= 4 && !LD->isVolatile();
367 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
368 LoadSDNode *LD = cast<LoadSDNode>(N);
369 if (const Value *Src = LD->getSrcValue())
370 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
371 if (PT->getAddressSpace() > 255)
373 if (LD->isVolatile())
375 ISD::LoadExtType ExtType = LD->getExtensionType();
376 if (ExtType == ISD::NON_EXTLOAD)
378 if (ExtType == ISD::EXTLOAD)
379 return LD->getAlignment() >= 4;
383 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
384 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
385 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
386 return PT->getAddressSpace() == 256;
390 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
391 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
392 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
393 return PT->getAddressSpace() == 257;
397 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{
398 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
399 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
400 if (PT->getAddressSpace() > 255)
404 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{
405 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
406 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
407 if (PT->getAddressSpace() > 255)
412 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{
413 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
414 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
415 if (PT->getAddressSpace() > 255)
419 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{
420 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
421 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
422 if (PT->getAddressSpace() > 255)
426 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{
427 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
428 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
429 if (PT->getAddressSpace() > 255)
434 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
435 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
436 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
438 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
439 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
440 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
441 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
442 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
443 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
445 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
446 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
447 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
448 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
449 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
450 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
453 // An 'and' node with a single use.
454 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
455 return N->hasOneUse();
457 // An 'srl' node with a single use.
458 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
459 return N->hasOneUse();
461 // An 'trunc' node with a single use.
462 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
463 return N->hasOneUse();
466 // 'shld' and 'shrd' instruction patterns. Note that even though these have
467 // the srl and shl in their patterns, the C++ code must still check for them,
468 // because predicates are tested before children nodes are explored.
470 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
471 (or (srl node:$src1, node:$amt1),
472 (shl node:$src2, node:$amt2)), [{
473 assert(N->getOpcode() == ISD::OR);
474 return N->getOperand(0).getOpcode() == ISD::SRL &&
475 N->getOperand(1).getOpcode() == ISD::SHL &&
476 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
477 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
478 N->getOperand(0).getConstantOperandVal(1) ==
479 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
482 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
483 (or (shl node:$src1, node:$amt1),
484 (srl node:$src2, node:$amt2)), [{
485 assert(N->getOpcode() == ISD::OR);
486 return N->getOperand(0).getOpcode() == ISD::SHL &&
487 N->getOperand(1).getOpcode() == ISD::SRL &&
488 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
489 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
490 N->getOperand(0).getConstantOperandVal(1) ==
491 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
494 //===----------------------------------------------------------------------===//
495 // Instruction list...
498 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
499 // a stack adjustment and the codegen must know that they may modify the stack
500 // pointer before prolog-epilog rewriting occurs.
501 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
502 // sub / add which can clobber EFLAGS.
503 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
504 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
506 [(X86callseq_start timm:$amt)]>,
507 Requires<[In32BitMode]>;
508 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
510 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
511 Requires<[In32BitMode]>;
515 let neverHasSideEffects = 1 in {
516 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
517 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
518 "nopl\t$zero", []>, TB;
522 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int 3", []>;
523 def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
526 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
527 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
531 //===----------------------------------------------------------------------===//
532 // Control Flow Instructions...
535 // Return instructions.
536 let isTerminator = 1, isReturn = 1, isBarrier = 1,
537 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
538 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
541 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
543 [(X86retflag imm:$amt)]>;
546 // All branches are RawFrm, Void, Branch, and Terminators
547 let isBranch = 1, isTerminator = 1 in
548 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
549 I<opcode, RawFrm, (outs), ins, asm, pattern>;
551 let isBranch = 1, isBarrier = 1 in {
552 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
553 def JMP8 : IBr<0xEB, (ins brtarget8:$dst), "jmp\t$dst", []>;
557 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
558 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
559 [(brind GR32:$dst)]>;
560 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
561 [(brind (loadi32 addr:$dst))]>;
564 // Conditional branches
565 let Uses = [EFLAGS] in {
566 // Short conditional jumps
567 def JO8 : IBr<0x70, (ins brtarget8:$dst), "jo\t$dst", []>;
568 def JNO8 : IBr<0x71, (ins brtarget8:$dst), "jno\t$dst", []>;
569 def JB8 : IBr<0x72, (ins brtarget8:$dst), "jb\t$dst", []>;
570 def JAE8 : IBr<0x73, (ins brtarget8:$dst), "jae\t$dst", []>;
571 def JE8 : IBr<0x74, (ins brtarget8:$dst), "je\t$dst", []>;
572 def JNE8 : IBr<0x75, (ins brtarget8:$dst), "jne\t$dst", []>;
573 def JBE8 : IBr<0x76, (ins brtarget8:$dst), "jbe\t$dst", []>;
574 def JA8 : IBr<0x77, (ins brtarget8:$dst), "ja\t$dst", []>;
575 def JS8 : IBr<0x78, (ins brtarget8:$dst), "js\t$dst", []>;
576 def JNS8 : IBr<0x79, (ins brtarget8:$dst), "jns\t$dst", []>;
577 def JP8 : IBr<0x7A, (ins brtarget8:$dst), "jp\t$dst", []>;
578 def JNP8 : IBr<0x7B, (ins brtarget8:$dst), "jnp\t$dst", []>;
579 def JL8 : IBr<0x7C, (ins brtarget8:$dst), "jl\t$dst", []>;
580 def JGE8 : IBr<0x7D, (ins brtarget8:$dst), "jge\t$dst", []>;
581 def JLE8 : IBr<0x7E, (ins brtarget8:$dst), "jle\t$dst", []>;
582 def JG8 : IBr<0x7F, (ins brtarget8:$dst), "jg\t$dst", []>;
584 def JCXZ8 : IBr<0xE3, (ins brtarget8:$dst), "jcxz\t$dst", []>;
586 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
587 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
588 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
589 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
590 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
591 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
592 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
593 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
594 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
595 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
596 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
597 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
599 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
600 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
601 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
602 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
603 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
604 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
605 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
606 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
608 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
609 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
610 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
611 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
612 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
613 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
614 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
615 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
616 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
617 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
618 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
619 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
622 //===----------------------------------------------------------------------===//
623 // Call Instructions...
626 // All calls clobber the non-callee saved registers. ESP is marked as
627 // a use to prevent stack-pointer assignments that appear immediately
628 // before calls from potentially appearing dead. Uses for argument
629 // registers are added manually.
630 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
631 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
632 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
633 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
635 def CALLpcrel32 : Ii32<0xE8, RawFrm,
636 (outs), (ins i32imm_pcrel:$dst,variable_ops),
638 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
639 "call\t{*}$dst", [(X86call GR32:$dst)]>;
640 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
641 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
646 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
647 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops),
648 "#TC_RETURN $dst $offset",
651 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
652 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops),
653 "#TC_RETURN $dst $offset",
656 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
658 def TAILJMPd : IBr<0xE9, (ins i32imm_pcrel:$dst), "jmp\t$dst # TAILCALL",
660 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
661 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
663 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
664 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
665 "jmp\t{*}$dst # TAILCALL", []>;
667 //===----------------------------------------------------------------------===//
668 // Miscellaneous Instructions...
670 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
671 def LEAVE : I<0xC9, RawFrm,
672 (outs), (ins), "leave", []>;
674 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
676 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
679 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
682 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
683 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
684 "push{l}\t$imm", []>;
685 def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
686 "push{l}\t$imm", []>;
687 def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
688 "push{l}\t$imm", []>;
691 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
692 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
693 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
694 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
696 let isTwoAddress = 1 in // GR32 = bswap GR32
697 def BSWAP32r : I<0xC8, AddRegFrm,
698 (outs GR32:$dst), (ins GR32:$src),
700 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
703 // Bit scan instructions.
704 let Defs = [EFLAGS] in {
705 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
706 "bsf{w}\t{$src, $dst|$dst, $src}",
707 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
708 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
709 "bsf{w}\t{$src, $dst|$dst, $src}",
710 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
711 (implicit EFLAGS)]>, TB;
712 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
713 "bsf{l}\t{$src, $dst|$dst, $src}",
714 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
715 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
716 "bsf{l}\t{$src, $dst|$dst, $src}",
717 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
718 (implicit EFLAGS)]>, TB;
720 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
721 "bsr{w}\t{$src, $dst|$dst, $src}",
722 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
723 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
724 "bsr{w}\t{$src, $dst|$dst, $src}",
725 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
726 (implicit EFLAGS)]>, TB;
727 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
728 "bsr{l}\t{$src, $dst|$dst, $src}",
729 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
730 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
731 "bsr{l}\t{$src, $dst|$dst, $src}",
732 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
733 (implicit EFLAGS)]>, TB;
736 let neverHasSideEffects = 1 in
737 def LEA16r : I<0x8D, MRMSrcMem,
738 (outs GR16:$dst), (ins i32mem:$src),
739 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
740 let isReMaterializable = 1 in
741 def LEA32r : I<0x8D, MRMSrcMem,
742 (outs GR32:$dst), (ins lea32mem:$src),
743 "lea{l}\t{$src|$dst}, {$dst|$src}",
744 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
746 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
747 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
748 [(X86rep_movs i8)]>, REP;
749 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
750 [(X86rep_movs i16)]>, REP, OpSize;
751 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
752 [(X86rep_movs i32)]>, REP;
755 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
756 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
757 [(X86rep_stos i8)]>, REP;
758 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
759 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
760 [(X86rep_stos i16)]>, REP, OpSize;
761 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
762 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
763 [(X86rep_stos i32)]>, REP;
765 let Defs = [RAX, RDX] in
766 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
769 let isBarrier = 1, hasCtrlDep = 1 in {
770 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
773 //===----------------------------------------------------------------------===//
774 // Input/Output Instructions...
776 let Defs = [AL], Uses = [DX] in
777 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
778 "in{b}\t{%dx, %al|%AL, %DX}", []>;
779 let Defs = [AX], Uses = [DX] in
780 def IN16rr : I<0xED, RawFrm, (outs), (ins),
781 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
782 let Defs = [EAX], Uses = [DX] in
783 def IN32rr : I<0xED, RawFrm, (outs), (ins),
784 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
787 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
788 "in{b}\t{$port, %al|%AL, $port}", []>;
790 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
791 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
793 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
794 "in{l}\t{$port, %eax|%EAX, $port}", []>;
796 let Uses = [DX, AL] in
797 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
798 "out{b}\t{%al, %dx|%DX, %AL}", []>;
799 let Uses = [DX, AX] in
800 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
801 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
802 let Uses = [DX, EAX] in
803 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
804 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
807 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
808 "out{b}\t{%al, $port|$port, %AL}", []>;
810 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
811 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
813 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
814 "out{l}\t{%eax, $port|$port, %EAX}", []>;
816 //===----------------------------------------------------------------------===//
817 // Move Instructions...
819 let neverHasSideEffects = 1 in {
820 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
821 "mov{b}\t{$src, $dst|$dst, $src}", []>;
822 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
823 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
824 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
825 "mov{l}\t{$src, $dst|$dst, $src}", []>;
827 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
828 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
829 "mov{b}\t{$src, $dst|$dst, $src}",
830 [(set GR8:$dst, imm:$src)]>;
831 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
832 "mov{w}\t{$src, $dst|$dst, $src}",
833 [(set GR16:$dst, imm:$src)]>, OpSize;
834 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
835 "mov{l}\t{$src, $dst|$dst, $src}",
836 [(set GR32:$dst, imm:$src)]>;
838 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
839 "mov{b}\t{$src, $dst|$dst, $src}",
840 [(store (i8 imm:$src), addr:$dst)]>;
841 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
842 "mov{w}\t{$src, $dst|$dst, $src}",
843 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
844 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
845 "mov{l}\t{$src, $dst|$dst, $src}",
846 [(store (i32 imm:$src), addr:$dst)]>;
848 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
849 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
850 "mov{b}\t{$src, $dst|$dst, $src}",
851 [(set GR8:$dst, (loadi8 addr:$src))]>;
852 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
853 "mov{w}\t{$src, $dst|$dst, $src}",
854 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
855 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
856 "mov{l}\t{$src, $dst|$dst, $src}",
857 [(set GR32:$dst, (loadi32 addr:$src))]>;
860 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
861 "mov{b}\t{$src, $dst|$dst, $src}",
862 [(store GR8:$src, addr:$dst)]>;
863 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
864 "mov{w}\t{$src, $dst|$dst, $src}",
865 [(store GR16:$src, addr:$dst)]>, OpSize;
866 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
867 "mov{l}\t{$src, $dst|$dst, $src}",
868 [(store GR32:$src, addr:$dst)]>;
870 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
871 // that they can be used for copying and storing h registers, which can't be
872 // encoded when a REX prefix is present.
873 let neverHasSideEffects = 1 in
874 def MOV8rr_NOREX : I<0x88, MRMDestReg,
875 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
876 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
878 def MOV8mr_NOREX : I<0x88, MRMDestMem,
879 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
880 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
882 canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
883 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
884 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
885 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
887 //===----------------------------------------------------------------------===//
888 // Fixed-Register Multiplication and Division Instructions...
891 // Extra precision multiplication
892 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
893 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
894 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
895 // This probably ought to be moved to a def : Pat<> if the
896 // syntax can be accepted.
897 [(set AL, (mul AL, GR8:$src)),
898 (implicit EFLAGS)]>; // AL,AH = AL*GR8
900 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
901 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
903 []>, OpSize; // AX,DX = AX*GR16
905 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
906 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
908 []>; // EAX,EDX = EAX*GR32
910 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
911 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
913 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
914 // This probably ought to be moved to a def : Pat<> if the
915 // syntax can be accepted.
916 [(set AL, (mul AL, (loadi8 addr:$src))),
917 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
919 let mayLoad = 1, neverHasSideEffects = 1 in {
920 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
921 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
923 []>, OpSize; // AX,DX = AX*[mem16]
925 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
926 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
928 []>; // EAX,EDX = EAX*[mem32]
931 let neverHasSideEffects = 1 in {
932 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
933 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
935 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
936 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
937 OpSize; // AX,DX = AX*GR16
938 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
939 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
940 // EAX,EDX = EAX*GR32
942 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
943 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
944 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
945 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
946 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
947 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
948 let Defs = [EAX,EDX], Uses = [EAX] in
949 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
950 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
952 } // neverHasSideEffects
954 // unsigned division/remainder
955 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
956 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
958 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
959 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
960 "div{w}\t$src", []>, OpSize;
961 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
962 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
965 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
966 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
968 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
969 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
970 "div{w}\t$src", []>, OpSize;
971 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
972 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
976 // Signed division/remainder.
977 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
978 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
979 "idiv{b}\t$src", []>;
980 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
981 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
982 "idiv{w}\t$src", []>, OpSize;
983 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
984 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
985 "idiv{l}\t$src", []>;
986 let mayLoad = 1, mayLoad = 1 in {
987 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
988 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
989 "idiv{b}\t$src", []>;
990 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
991 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
992 "idiv{w}\t$src", []>, OpSize;
993 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
994 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
995 "idiv{l}\t$src", []>;
998 //===----------------------------------------------------------------------===//
999 // Two address Instructions.
1001 let isTwoAddress = 1 in {
1003 // Conditional moves
1004 let Uses = [EFLAGS] in {
1005 let isCommutable = 1 in {
1006 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1007 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1008 "cmovb\t{$src2, $dst|$dst, $src2}",
1009 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1010 X86_COND_B, EFLAGS))]>,
1012 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1013 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1014 "cmovb\t{$src2, $dst|$dst, $src2}",
1015 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1016 X86_COND_B, EFLAGS))]>,
1018 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1019 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1020 "cmovae\t{$src2, $dst|$dst, $src2}",
1021 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1022 X86_COND_AE, EFLAGS))]>,
1024 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1025 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1026 "cmovae\t{$src2, $dst|$dst, $src2}",
1027 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1028 X86_COND_AE, EFLAGS))]>,
1030 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1031 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1032 "cmove\t{$src2, $dst|$dst, $src2}",
1033 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1034 X86_COND_E, EFLAGS))]>,
1036 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1037 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1038 "cmove\t{$src2, $dst|$dst, $src2}",
1039 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1040 X86_COND_E, EFLAGS))]>,
1042 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1043 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1044 "cmovne\t{$src2, $dst|$dst, $src2}",
1045 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1046 X86_COND_NE, EFLAGS))]>,
1048 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1049 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1050 "cmovne\t{$src2, $dst|$dst, $src2}",
1051 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1052 X86_COND_NE, EFLAGS))]>,
1054 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1055 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1056 "cmovbe\t{$src2, $dst|$dst, $src2}",
1057 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1058 X86_COND_BE, EFLAGS))]>,
1060 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1061 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1062 "cmovbe\t{$src2, $dst|$dst, $src2}",
1063 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1064 X86_COND_BE, EFLAGS))]>,
1066 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1067 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1068 "cmova\t{$src2, $dst|$dst, $src2}",
1069 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1070 X86_COND_A, EFLAGS))]>,
1072 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1073 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1074 "cmova\t{$src2, $dst|$dst, $src2}",
1075 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1076 X86_COND_A, EFLAGS))]>,
1078 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1079 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1080 "cmovl\t{$src2, $dst|$dst, $src2}",
1081 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1082 X86_COND_L, EFLAGS))]>,
1084 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1085 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1086 "cmovl\t{$src2, $dst|$dst, $src2}",
1087 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1088 X86_COND_L, EFLAGS))]>,
1090 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1091 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1092 "cmovge\t{$src2, $dst|$dst, $src2}",
1093 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1094 X86_COND_GE, EFLAGS))]>,
1096 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1097 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1098 "cmovge\t{$src2, $dst|$dst, $src2}",
1099 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1100 X86_COND_GE, EFLAGS))]>,
1102 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1103 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1104 "cmovle\t{$src2, $dst|$dst, $src2}",
1105 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1106 X86_COND_LE, EFLAGS))]>,
1108 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1109 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1110 "cmovle\t{$src2, $dst|$dst, $src2}",
1111 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1112 X86_COND_LE, EFLAGS))]>,
1114 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1115 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1116 "cmovg\t{$src2, $dst|$dst, $src2}",
1117 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1118 X86_COND_G, EFLAGS))]>,
1120 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1121 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1122 "cmovg\t{$src2, $dst|$dst, $src2}",
1123 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1124 X86_COND_G, EFLAGS))]>,
1126 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1127 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1128 "cmovs\t{$src2, $dst|$dst, $src2}",
1129 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1130 X86_COND_S, EFLAGS))]>,
1132 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1133 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1134 "cmovs\t{$src2, $dst|$dst, $src2}",
1135 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1136 X86_COND_S, EFLAGS))]>,
1138 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1139 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1140 "cmovns\t{$src2, $dst|$dst, $src2}",
1141 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1142 X86_COND_NS, EFLAGS))]>,
1144 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1145 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1146 "cmovns\t{$src2, $dst|$dst, $src2}",
1147 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1148 X86_COND_NS, EFLAGS))]>,
1150 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1151 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1152 "cmovp\t{$src2, $dst|$dst, $src2}",
1153 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1154 X86_COND_P, EFLAGS))]>,
1156 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1157 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1158 "cmovp\t{$src2, $dst|$dst, $src2}",
1159 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1160 X86_COND_P, EFLAGS))]>,
1162 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1163 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1164 "cmovnp\t{$src2, $dst|$dst, $src2}",
1165 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1166 X86_COND_NP, EFLAGS))]>,
1168 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1169 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1170 "cmovnp\t{$src2, $dst|$dst, $src2}",
1171 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1172 X86_COND_NP, EFLAGS))]>,
1174 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1175 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1176 "cmovo\t{$src2, $dst|$dst, $src2}",
1177 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1178 X86_COND_O, EFLAGS))]>,
1180 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1181 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1182 "cmovo\t{$src2, $dst|$dst, $src2}",
1183 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1184 X86_COND_O, EFLAGS))]>,
1186 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1187 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1188 "cmovno\t{$src2, $dst|$dst, $src2}",
1189 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1190 X86_COND_NO, EFLAGS))]>,
1192 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1193 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1194 "cmovno\t{$src2, $dst|$dst, $src2}",
1195 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1196 X86_COND_NO, EFLAGS))]>,
1198 } // isCommutable = 1
1200 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1201 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1202 "cmovb\t{$src2, $dst|$dst, $src2}",
1203 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1204 X86_COND_B, EFLAGS))]>,
1206 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1207 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1208 "cmovb\t{$src2, $dst|$dst, $src2}",
1209 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1210 X86_COND_B, EFLAGS))]>,
1212 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1213 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1214 "cmovae\t{$src2, $dst|$dst, $src2}",
1215 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1216 X86_COND_AE, EFLAGS))]>,
1218 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1219 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1220 "cmovae\t{$src2, $dst|$dst, $src2}",
1221 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1222 X86_COND_AE, EFLAGS))]>,
1224 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1225 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1226 "cmove\t{$src2, $dst|$dst, $src2}",
1227 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1228 X86_COND_E, EFLAGS))]>,
1230 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1231 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1232 "cmove\t{$src2, $dst|$dst, $src2}",
1233 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1234 X86_COND_E, EFLAGS))]>,
1236 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1237 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1238 "cmovne\t{$src2, $dst|$dst, $src2}",
1239 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1240 X86_COND_NE, EFLAGS))]>,
1242 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1243 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1244 "cmovne\t{$src2, $dst|$dst, $src2}",
1245 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1246 X86_COND_NE, EFLAGS))]>,
1248 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1249 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1250 "cmovbe\t{$src2, $dst|$dst, $src2}",
1251 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1252 X86_COND_BE, EFLAGS))]>,
1254 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1255 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1256 "cmovbe\t{$src2, $dst|$dst, $src2}",
1257 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1258 X86_COND_BE, EFLAGS))]>,
1260 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1261 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1262 "cmova\t{$src2, $dst|$dst, $src2}",
1263 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1264 X86_COND_A, EFLAGS))]>,
1266 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1267 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1268 "cmova\t{$src2, $dst|$dst, $src2}",
1269 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1270 X86_COND_A, EFLAGS))]>,
1272 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1273 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1274 "cmovl\t{$src2, $dst|$dst, $src2}",
1275 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1276 X86_COND_L, EFLAGS))]>,
1278 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1279 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1280 "cmovl\t{$src2, $dst|$dst, $src2}",
1281 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1282 X86_COND_L, EFLAGS))]>,
1284 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1285 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1286 "cmovge\t{$src2, $dst|$dst, $src2}",
1287 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1288 X86_COND_GE, EFLAGS))]>,
1290 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1291 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1292 "cmovge\t{$src2, $dst|$dst, $src2}",
1293 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1294 X86_COND_GE, EFLAGS))]>,
1296 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1297 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1298 "cmovle\t{$src2, $dst|$dst, $src2}",
1299 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1300 X86_COND_LE, EFLAGS))]>,
1302 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1303 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1304 "cmovle\t{$src2, $dst|$dst, $src2}",
1305 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1306 X86_COND_LE, EFLAGS))]>,
1308 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1309 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1310 "cmovg\t{$src2, $dst|$dst, $src2}",
1311 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1312 X86_COND_G, EFLAGS))]>,
1314 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1315 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1316 "cmovg\t{$src2, $dst|$dst, $src2}",
1317 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1318 X86_COND_G, EFLAGS))]>,
1320 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1321 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1322 "cmovs\t{$src2, $dst|$dst, $src2}",
1323 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1324 X86_COND_S, EFLAGS))]>,
1326 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1327 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1328 "cmovs\t{$src2, $dst|$dst, $src2}",
1329 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1330 X86_COND_S, EFLAGS))]>,
1332 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1333 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1334 "cmovns\t{$src2, $dst|$dst, $src2}",
1335 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1336 X86_COND_NS, EFLAGS))]>,
1338 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1339 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1340 "cmovns\t{$src2, $dst|$dst, $src2}",
1341 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1342 X86_COND_NS, EFLAGS))]>,
1344 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1345 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1346 "cmovp\t{$src2, $dst|$dst, $src2}",
1347 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1348 X86_COND_P, EFLAGS))]>,
1350 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1351 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1352 "cmovp\t{$src2, $dst|$dst, $src2}",
1353 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1354 X86_COND_P, EFLAGS))]>,
1356 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1357 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1358 "cmovnp\t{$src2, $dst|$dst, $src2}",
1359 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1360 X86_COND_NP, EFLAGS))]>,
1362 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1363 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1364 "cmovnp\t{$src2, $dst|$dst, $src2}",
1365 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1366 X86_COND_NP, EFLAGS))]>,
1368 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1369 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1370 "cmovo\t{$src2, $dst|$dst, $src2}",
1371 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1372 X86_COND_O, EFLAGS))]>,
1374 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1375 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1376 "cmovo\t{$src2, $dst|$dst, $src2}",
1377 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1378 X86_COND_O, EFLAGS))]>,
1380 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1381 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1382 "cmovno\t{$src2, $dst|$dst, $src2}",
1383 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1384 X86_COND_NO, EFLAGS))]>,
1386 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1387 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1388 "cmovno\t{$src2, $dst|$dst, $src2}",
1389 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1390 X86_COND_NO, EFLAGS))]>,
1392 } // Uses = [EFLAGS]
1395 // unary instructions
1396 let CodeSize = 2 in {
1397 let Defs = [EFLAGS] in {
1398 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1399 [(set GR8:$dst, (ineg GR8:$src)),
1400 (implicit EFLAGS)]>;
1401 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1402 [(set GR16:$dst, (ineg GR16:$src)),
1403 (implicit EFLAGS)]>, OpSize;
1404 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1405 [(set GR32:$dst, (ineg GR32:$src)),
1406 (implicit EFLAGS)]>;
1407 let isTwoAddress = 0 in {
1408 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1409 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1410 (implicit EFLAGS)]>;
1411 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1412 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1413 (implicit EFLAGS)]>, OpSize;
1414 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1415 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1416 (implicit EFLAGS)]>;
1418 } // Defs = [EFLAGS]
1420 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1421 let AddedComplexity = 15 in {
1422 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1423 [(set GR8:$dst, (not GR8:$src))]>;
1424 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1425 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1426 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1427 [(set GR32:$dst, (not GR32:$src))]>;
1429 let isTwoAddress = 0 in {
1430 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1431 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1432 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1433 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1434 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1435 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1439 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1440 let Defs = [EFLAGS] in {
1442 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1443 [(set GR8:$dst, (add GR8:$src, 1)),
1444 (implicit EFLAGS)]>;
1445 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1446 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1447 [(set GR16:$dst, (add GR16:$src, 1)),
1448 (implicit EFLAGS)]>,
1449 OpSize, Requires<[In32BitMode]>;
1450 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1451 [(set GR32:$dst, (add GR32:$src, 1)),
1452 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1454 let isTwoAddress = 0, CodeSize = 2 in {
1455 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1456 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1457 (implicit EFLAGS)]>;
1458 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1459 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1460 (implicit EFLAGS)]>,
1461 OpSize, Requires<[In32BitMode]>;
1462 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1463 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1464 (implicit EFLAGS)]>,
1465 Requires<[In32BitMode]>;
1469 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1470 [(set GR8:$dst, (add GR8:$src, -1)),
1471 (implicit EFLAGS)]>;
1472 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1473 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1474 [(set GR16:$dst, (add GR16:$src, -1)),
1475 (implicit EFLAGS)]>,
1476 OpSize, Requires<[In32BitMode]>;
1477 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1478 [(set GR32:$dst, (add GR32:$src, -1)),
1479 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1482 let isTwoAddress = 0, CodeSize = 2 in {
1483 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1484 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1485 (implicit EFLAGS)]>;
1486 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1487 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1488 (implicit EFLAGS)]>,
1489 OpSize, Requires<[In32BitMode]>;
1490 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1491 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1492 (implicit EFLAGS)]>,
1493 Requires<[In32BitMode]>;
1495 } // Defs = [EFLAGS]
1497 // Logical operators...
1498 let Defs = [EFLAGS] in {
1499 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1500 def AND8rr : I<0x20, MRMDestReg,
1501 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1502 "and{b}\t{$src2, $dst|$dst, $src2}",
1503 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
1504 (implicit EFLAGS)]>;
1505 def AND16rr : I<0x21, MRMDestReg,
1506 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1507 "and{w}\t{$src2, $dst|$dst, $src2}",
1508 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
1509 (implicit EFLAGS)]>, OpSize;
1510 def AND32rr : I<0x21, MRMDestReg,
1511 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1512 "and{l}\t{$src2, $dst|$dst, $src2}",
1513 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
1514 (implicit EFLAGS)]>;
1517 def AND8rm : I<0x22, MRMSrcMem,
1518 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1519 "and{b}\t{$src2, $dst|$dst, $src2}",
1520 [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
1521 (implicit EFLAGS)]>;
1522 def AND16rm : I<0x23, MRMSrcMem,
1523 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1524 "and{w}\t{$src2, $dst|$dst, $src2}",
1525 [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
1526 (implicit EFLAGS)]>, OpSize;
1527 def AND32rm : I<0x23, MRMSrcMem,
1528 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1529 "and{l}\t{$src2, $dst|$dst, $src2}",
1530 [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
1531 (implicit EFLAGS)]>;
1533 def AND8ri : Ii8<0x80, MRM4r,
1534 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1535 "and{b}\t{$src2, $dst|$dst, $src2}",
1536 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
1537 (implicit EFLAGS)]>;
1538 def AND16ri : Ii16<0x81, MRM4r,
1539 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1540 "and{w}\t{$src2, $dst|$dst, $src2}",
1541 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
1542 (implicit EFLAGS)]>, OpSize;
1543 def AND32ri : Ii32<0x81, MRM4r,
1544 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1545 "and{l}\t{$src2, $dst|$dst, $src2}",
1546 [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
1547 (implicit EFLAGS)]>;
1548 def AND16ri8 : Ii8<0x83, MRM4r,
1549 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1550 "and{w}\t{$src2, $dst|$dst, $src2}",
1551 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
1552 (implicit EFLAGS)]>,
1554 def AND32ri8 : Ii8<0x83, MRM4r,
1555 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1556 "and{l}\t{$src2, $dst|$dst, $src2}",
1557 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
1558 (implicit EFLAGS)]>;
1560 let isTwoAddress = 0 in {
1561 def AND8mr : I<0x20, MRMDestMem,
1562 (outs), (ins i8mem :$dst, GR8 :$src),
1563 "and{b}\t{$src, $dst|$dst, $src}",
1564 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1565 (implicit EFLAGS)]>;
1566 def AND16mr : I<0x21, MRMDestMem,
1567 (outs), (ins i16mem:$dst, GR16:$src),
1568 "and{w}\t{$src, $dst|$dst, $src}",
1569 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1570 (implicit EFLAGS)]>,
1572 def AND32mr : I<0x21, MRMDestMem,
1573 (outs), (ins i32mem:$dst, GR32:$src),
1574 "and{l}\t{$src, $dst|$dst, $src}",
1575 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1576 (implicit EFLAGS)]>;
1577 def AND8mi : Ii8<0x80, MRM4m,
1578 (outs), (ins i8mem :$dst, i8imm :$src),
1579 "and{b}\t{$src, $dst|$dst, $src}",
1580 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1581 (implicit EFLAGS)]>;
1582 def AND16mi : Ii16<0x81, MRM4m,
1583 (outs), (ins i16mem:$dst, i16imm:$src),
1584 "and{w}\t{$src, $dst|$dst, $src}",
1585 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1586 (implicit EFLAGS)]>,
1588 def AND32mi : Ii32<0x81, MRM4m,
1589 (outs), (ins i32mem:$dst, i32imm:$src),
1590 "and{l}\t{$src, $dst|$dst, $src}",
1591 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1592 (implicit EFLAGS)]>;
1593 def AND16mi8 : Ii8<0x83, MRM4m,
1594 (outs), (ins i16mem:$dst, i16i8imm :$src),
1595 "and{w}\t{$src, $dst|$dst, $src}",
1596 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1597 (implicit EFLAGS)]>,
1599 def AND32mi8 : Ii8<0x83, MRM4m,
1600 (outs), (ins i32mem:$dst, i32i8imm :$src),
1601 "and{l}\t{$src, $dst|$dst, $src}",
1602 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1603 (implicit EFLAGS)]>;
1607 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1608 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1609 "or{b}\t{$src2, $dst|$dst, $src2}",
1610 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
1611 (implicit EFLAGS)]>;
1612 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1613 "or{w}\t{$src2, $dst|$dst, $src2}",
1614 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
1615 (implicit EFLAGS)]>, OpSize;
1616 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1617 "or{l}\t{$src2, $dst|$dst, $src2}",
1618 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
1619 (implicit EFLAGS)]>;
1621 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1622 "or{b}\t{$src2, $dst|$dst, $src2}",
1623 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
1624 (implicit EFLAGS)]>;
1625 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1626 "or{w}\t{$src2, $dst|$dst, $src2}",
1627 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
1628 (implicit EFLAGS)]>, OpSize;
1629 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1630 "or{l}\t{$src2, $dst|$dst, $src2}",
1631 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
1632 (implicit EFLAGS)]>;
1634 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1635 "or{b}\t{$src2, $dst|$dst, $src2}",
1636 [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
1637 (implicit EFLAGS)]>;
1638 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1639 "or{w}\t{$src2, $dst|$dst, $src2}",
1640 [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
1641 (implicit EFLAGS)]>, OpSize;
1642 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1643 "or{l}\t{$src2, $dst|$dst, $src2}",
1644 [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
1645 (implicit EFLAGS)]>;
1647 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1648 "or{w}\t{$src2, $dst|$dst, $src2}",
1649 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
1650 (implicit EFLAGS)]>, OpSize;
1651 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1652 "or{l}\t{$src2, $dst|$dst, $src2}",
1653 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
1654 (implicit EFLAGS)]>;
1655 let isTwoAddress = 0 in {
1656 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1657 "or{b}\t{$src, $dst|$dst, $src}",
1658 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1659 (implicit EFLAGS)]>;
1660 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1661 "or{w}\t{$src, $dst|$dst, $src}",
1662 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1663 (implicit EFLAGS)]>, OpSize;
1664 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1665 "or{l}\t{$src, $dst|$dst, $src}",
1666 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1667 (implicit EFLAGS)]>;
1668 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1669 "or{b}\t{$src, $dst|$dst, $src}",
1670 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1671 (implicit EFLAGS)]>;
1672 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1673 "or{w}\t{$src, $dst|$dst, $src}",
1674 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1675 (implicit EFLAGS)]>,
1677 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1678 "or{l}\t{$src, $dst|$dst, $src}",
1679 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1680 (implicit EFLAGS)]>;
1681 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1682 "or{w}\t{$src, $dst|$dst, $src}",
1683 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1684 (implicit EFLAGS)]>,
1686 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1687 "or{l}\t{$src, $dst|$dst, $src}",
1688 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1689 (implicit EFLAGS)]>;
1690 } // isTwoAddress = 0
1693 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1694 def XOR8rr : I<0x30, MRMDestReg,
1695 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1696 "xor{b}\t{$src2, $dst|$dst, $src2}",
1697 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
1698 (implicit EFLAGS)]>;
1699 def XOR16rr : I<0x31, MRMDestReg,
1700 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1701 "xor{w}\t{$src2, $dst|$dst, $src2}",
1702 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
1703 (implicit EFLAGS)]>, OpSize;
1704 def XOR32rr : I<0x31, MRMDestReg,
1705 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1706 "xor{l}\t{$src2, $dst|$dst, $src2}",
1707 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
1708 (implicit EFLAGS)]>;
1709 } // isCommutable = 1
1711 def XOR8rm : I<0x32, MRMSrcMem ,
1712 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1713 "xor{b}\t{$src2, $dst|$dst, $src2}",
1714 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
1715 (implicit EFLAGS)]>;
1716 def XOR16rm : I<0x33, MRMSrcMem ,
1717 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1718 "xor{w}\t{$src2, $dst|$dst, $src2}",
1719 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
1720 (implicit EFLAGS)]>,
1722 def XOR32rm : I<0x33, MRMSrcMem ,
1723 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1724 "xor{l}\t{$src2, $dst|$dst, $src2}",
1725 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
1726 (implicit EFLAGS)]>;
1728 def XOR8ri : Ii8<0x80, MRM6r,
1729 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1730 "xor{b}\t{$src2, $dst|$dst, $src2}",
1731 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
1732 (implicit EFLAGS)]>;
1733 def XOR16ri : Ii16<0x81, MRM6r,
1734 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1735 "xor{w}\t{$src2, $dst|$dst, $src2}",
1736 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
1737 (implicit EFLAGS)]>, OpSize;
1738 def XOR32ri : Ii32<0x81, MRM6r,
1739 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1740 "xor{l}\t{$src2, $dst|$dst, $src2}",
1741 [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
1742 (implicit EFLAGS)]>;
1743 def XOR16ri8 : Ii8<0x83, MRM6r,
1744 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1745 "xor{w}\t{$src2, $dst|$dst, $src2}",
1746 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
1747 (implicit EFLAGS)]>,
1749 def XOR32ri8 : Ii8<0x83, MRM6r,
1750 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1751 "xor{l}\t{$src2, $dst|$dst, $src2}",
1752 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
1753 (implicit EFLAGS)]>;
1755 let isTwoAddress = 0 in {
1756 def XOR8mr : I<0x30, MRMDestMem,
1757 (outs), (ins i8mem :$dst, GR8 :$src),
1758 "xor{b}\t{$src, $dst|$dst, $src}",
1759 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
1760 (implicit EFLAGS)]>;
1761 def XOR16mr : I<0x31, MRMDestMem,
1762 (outs), (ins i16mem:$dst, GR16:$src),
1763 "xor{w}\t{$src, $dst|$dst, $src}",
1764 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
1765 (implicit EFLAGS)]>,
1767 def XOR32mr : I<0x31, MRMDestMem,
1768 (outs), (ins i32mem:$dst, GR32:$src),
1769 "xor{l}\t{$src, $dst|$dst, $src}",
1770 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
1771 (implicit EFLAGS)]>;
1772 def XOR8mi : Ii8<0x80, MRM6m,
1773 (outs), (ins i8mem :$dst, i8imm :$src),
1774 "xor{b}\t{$src, $dst|$dst, $src}",
1775 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
1776 (implicit EFLAGS)]>;
1777 def XOR16mi : Ii16<0x81, MRM6m,
1778 (outs), (ins i16mem:$dst, i16imm:$src),
1779 "xor{w}\t{$src, $dst|$dst, $src}",
1780 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
1781 (implicit EFLAGS)]>,
1783 def XOR32mi : Ii32<0x81, MRM6m,
1784 (outs), (ins i32mem:$dst, i32imm:$src),
1785 "xor{l}\t{$src, $dst|$dst, $src}",
1786 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
1787 (implicit EFLAGS)]>;
1788 def XOR16mi8 : Ii8<0x83, MRM6m,
1789 (outs), (ins i16mem:$dst, i16i8imm :$src),
1790 "xor{w}\t{$src, $dst|$dst, $src}",
1791 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
1792 (implicit EFLAGS)]>,
1794 def XOR32mi8 : Ii8<0x83, MRM6m,
1795 (outs), (ins i32mem:$dst, i32i8imm :$src),
1796 "xor{l}\t{$src, $dst|$dst, $src}",
1797 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
1798 (implicit EFLAGS)]>;
1799 } // isTwoAddress = 0
1800 } // Defs = [EFLAGS]
1802 // Shift instructions
1803 let Defs = [EFLAGS] in {
1804 let Uses = [CL] in {
1805 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1806 "shl{b}\t{%cl, $dst|$dst, CL}",
1807 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1808 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1809 "shl{w}\t{%cl, $dst|$dst, CL}",
1810 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1811 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1812 "shl{l}\t{%cl, $dst|$dst, CL}",
1813 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1816 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1817 "shl{b}\t{$src2, $dst|$dst, $src2}",
1818 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1819 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1820 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1821 "shl{w}\t{$src2, $dst|$dst, $src2}",
1822 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1823 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1824 "shl{l}\t{$src2, $dst|$dst, $src2}",
1825 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1826 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1828 } // isConvertibleToThreeAddress = 1
1830 let isTwoAddress = 0 in {
1831 let Uses = [CL] in {
1832 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1833 "shl{b}\t{%cl, $dst|$dst, CL}",
1834 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1835 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1836 "shl{w}\t{%cl, $dst|$dst, CL}",
1837 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1838 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1839 "shl{l}\t{%cl, $dst|$dst, CL}",
1840 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1842 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1843 "shl{b}\t{$src, $dst|$dst, $src}",
1844 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1845 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1846 "shl{w}\t{$src, $dst|$dst, $src}",
1847 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1849 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1850 "shl{l}\t{$src, $dst|$dst, $src}",
1851 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1854 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1856 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1857 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1859 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1861 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1863 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1866 let Uses = [CL] in {
1867 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1868 "shr{b}\t{%cl, $dst|$dst, CL}",
1869 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1870 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1871 "shr{w}\t{%cl, $dst|$dst, CL}",
1872 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1873 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1874 "shr{l}\t{%cl, $dst|$dst, CL}",
1875 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1878 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1879 "shr{b}\t{$src2, $dst|$dst, $src2}",
1880 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1881 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1882 "shr{w}\t{$src2, $dst|$dst, $src2}",
1883 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1884 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1885 "shr{l}\t{$src2, $dst|$dst, $src2}",
1886 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1889 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1891 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1892 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1894 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1895 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1897 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1899 let isTwoAddress = 0 in {
1900 let Uses = [CL] in {
1901 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1902 "shr{b}\t{%cl, $dst|$dst, CL}",
1903 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1904 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1905 "shr{w}\t{%cl, $dst|$dst, CL}",
1906 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1908 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1909 "shr{l}\t{%cl, $dst|$dst, CL}",
1910 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1912 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1913 "shr{b}\t{$src, $dst|$dst, $src}",
1914 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1915 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1916 "shr{w}\t{$src, $dst|$dst, $src}",
1917 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1919 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1920 "shr{l}\t{$src, $dst|$dst, $src}",
1921 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1924 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1926 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1927 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1929 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1930 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1932 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1935 let Uses = [CL] in {
1936 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1937 "sar{b}\t{%cl, $dst|$dst, CL}",
1938 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1939 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1940 "sar{w}\t{%cl, $dst|$dst, CL}",
1941 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1942 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1943 "sar{l}\t{%cl, $dst|$dst, CL}",
1944 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1947 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1948 "sar{b}\t{$src2, $dst|$dst, $src2}",
1949 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1950 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1951 "sar{w}\t{$src2, $dst|$dst, $src2}",
1952 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1954 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1955 "sar{l}\t{$src2, $dst|$dst, $src2}",
1956 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1959 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1961 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1962 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1964 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1965 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1967 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1969 let isTwoAddress = 0 in {
1970 let Uses = [CL] in {
1971 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1972 "sar{b}\t{%cl, $dst|$dst, CL}",
1973 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
1974 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1975 "sar{w}\t{%cl, $dst|$dst, CL}",
1976 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1977 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1978 "sar{l}\t{%cl, $dst|$dst, CL}",
1979 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1981 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1982 "sar{b}\t{$src, $dst|$dst, $src}",
1983 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1984 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1985 "sar{w}\t{$src, $dst|$dst, $src}",
1986 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1988 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1989 "sar{l}\t{$src, $dst|$dst, $src}",
1990 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1993 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1995 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1996 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1998 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2000 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2002 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2005 // Rotate instructions
2006 // FIXME: provide shorter instructions when imm8 == 1
2007 let Uses = [CL] in {
2008 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
2009 "rol{b}\t{%cl, $dst|$dst, CL}",
2010 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
2011 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
2012 "rol{w}\t{%cl, $dst|$dst, CL}",
2013 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
2014 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
2015 "rol{l}\t{%cl, $dst|$dst, CL}",
2016 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2019 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2020 "rol{b}\t{$src2, $dst|$dst, $src2}",
2021 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2022 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2023 "rol{w}\t{$src2, $dst|$dst, $src2}",
2024 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2025 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2026 "rol{l}\t{$src2, $dst|$dst, $src2}",
2027 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2030 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2032 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2033 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2035 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2036 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2038 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2040 let isTwoAddress = 0 in {
2041 let Uses = [CL] in {
2042 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2043 "rol{b}\t{%cl, $dst|$dst, CL}",
2044 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2045 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2046 "rol{w}\t{%cl, $dst|$dst, CL}",
2047 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2048 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2049 "rol{l}\t{%cl, $dst|$dst, CL}",
2050 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2052 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2053 "rol{b}\t{$src, $dst|$dst, $src}",
2054 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2055 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2056 "rol{w}\t{$src, $dst|$dst, $src}",
2057 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2059 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2060 "rol{l}\t{$src, $dst|$dst, $src}",
2061 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2064 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2066 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2067 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2069 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2071 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2073 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2076 let Uses = [CL] in {
2077 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2078 "ror{b}\t{%cl, $dst|$dst, CL}",
2079 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2080 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2081 "ror{w}\t{%cl, $dst|$dst, CL}",
2082 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2083 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2084 "ror{l}\t{%cl, $dst|$dst, CL}",
2085 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2088 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2089 "ror{b}\t{$src2, $dst|$dst, $src2}",
2090 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2091 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2092 "ror{w}\t{$src2, $dst|$dst, $src2}",
2093 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2094 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2095 "ror{l}\t{$src2, $dst|$dst, $src2}",
2096 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2099 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2101 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2102 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2104 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2105 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2107 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2109 let isTwoAddress = 0 in {
2110 let Uses = [CL] in {
2111 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2112 "ror{b}\t{%cl, $dst|$dst, CL}",
2113 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2114 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2115 "ror{w}\t{%cl, $dst|$dst, CL}",
2116 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2117 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2118 "ror{l}\t{%cl, $dst|$dst, CL}",
2119 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2121 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2122 "ror{b}\t{$src, $dst|$dst, $src}",
2123 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2124 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2125 "ror{w}\t{$src, $dst|$dst, $src}",
2126 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2128 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2129 "ror{l}\t{$src, $dst|$dst, $src}",
2130 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2133 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2135 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2136 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2138 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2140 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2142 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2147 // Double shift instructions (generalizations of rotate)
2148 let Uses = [CL] in {
2149 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2150 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2151 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2152 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2153 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2154 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2155 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2156 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2157 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2159 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2160 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2161 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2165 let isCommutable = 1 in { // These instructions commute to each other.
2166 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2167 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2168 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2169 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2172 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2173 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2174 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2175 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2178 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2179 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2180 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2181 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2184 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2185 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2186 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2187 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2192 let isTwoAddress = 0 in {
2193 let Uses = [CL] in {
2194 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2195 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2196 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2198 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2199 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2200 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2203 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2204 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2205 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2206 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2207 (i8 imm:$src3)), addr:$dst)]>,
2209 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2210 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2211 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2212 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2213 (i8 imm:$src3)), addr:$dst)]>,
2216 let Uses = [CL] in {
2217 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2218 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2219 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2220 addr:$dst)]>, TB, OpSize;
2221 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2222 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2223 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2224 addr:$dst)]>, TB, OpSize;
2226 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2227 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2228 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2229 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2230 (i8 imm:$src3)), addr:$dst)]>,
2232 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2233 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2234 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2235 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2236 (i8 imm:$src3)), addr:$dst)]>,
2239 } // Defs = [EFLAGS]
2243 let Defs = [EFLAGS] in {
2244 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2245 // Register-Register Addition
2246 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2247 (ins GR8 :$src1, GR8 :$src2),
2248 "add{b}\t{$src2, $dst|$dst, $src2}",
2249 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
2250 (implicit EFLAGS)]>;
2252 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2253 // Register-Register Addition
2254 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2255 (ins GR16:$src1, GR16:$src2),
2256 "add{w}\t{$src2, $dst|$dst, $src2}",
2257 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2258 (implicit EFLAGS)]>, OpSize;
2259 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2260 (ins GR32:$src1, GR32:$src2),
2261 "add{l}\t{$src2, $dst|$dst, $src2}",
2262 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2263 (implicit EFLAGS)]>;
2264 } // end isConvertibleToThreeAddress
2265 } // end isCommutable
2267 // Register-Memory Addition
2268 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2269 (ins GR8 :$src1, i8mem :$src2),
2270 "add{b}\t{$src2, $dst|$dst, $src2}",
2271 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2272 (implicit EFLAGS)]>;
2273 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2274 (ins GR16:$src1, i16mem:$src2),
2275 "add{w}\t{$src2, $dst|$dst, $src2}",
2276 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2277 (implicit EFLAGS)]>, OpSize;
2278 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2279 (ins GR32:$src1, i32mem:$src2),
2280 "add{l}\t{$src2, $dst|$dst, $src2}",
2281 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2282 (implicit EFLAGS)]>;
2284 // Register-Integer Addition
2285 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2286 "add{b}\t{$src2, $dst|$dst, $src2}",
2287 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2288 (implicit EFLAGS)]>;
2290 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2291 // Register-Integer Addition
2292 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2293 (ins GR16:$src1, i16imm:$src2),
2294 "add{w}\t{$src2, $dst|$dst, $src2}",
2295 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2296 (implicit EFLAGS)]>, OpSize;
2297 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2298 (ins GR32:$src1, i32imm:$src2),
2299 "add{l}\t{$src2, $dst|$dst, $src2}",
2300 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2301 (implicit EFLAGS)]>;
2302 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2303 (ins GR16:$src1, i16i8imm:$src2),
2304 "add{w}\t{$src2, $dst|$dst, $src2}",
2305 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2306 (implicit EFLAGS)]>, OpSize;
2307 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2308 (ins GR32:$src1, i32i8imm:$src2),
2309 "add{l}\t{$src2, $dst|$dst, $src2}",
2310 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2311 (implicit EFLAGS)]>;
2314 let isTwoAddress = 0 in {
2315 // Memory-Register Addition
2316 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2317 "add{b}\t{$src2, $dst|$dst, $src2}",
2318 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2319 (implicit EFLAGS)]>;
2320 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2321 "add{w}\t{$src2, $dst|$dst, $src2}",
2322 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2323 (implicit EFLAGS)]>, OpSize;
2324 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2325 "add{l}\t{$src2, $dst|$dst, $src2}",
2326 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2327 (implicit EFLAGS)]>;
2328 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2329 "add{b}\t{$src2, $dst|$dst, $src2}",
2330 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2331 (implicit EFLAGS)]>;
2332 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2333 "add{w}\t{$src2, $dst|$dst, $src2}",
2334 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2335 (implicit EFLAGS)]>, OpSize;
2336 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2337 "add{l}\t{$src2, $dst|$dst, $src2}",
2338 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2339 (implicit EFLAGS)]>;
2340 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2341 "add{w}\t{$src2, $dst|$dst, $src2}",
2342 [(store (add (load addr:$dst), i16immSExt8:$src2),
2344 (implicit EFLAGS)]>, OpSize;
2345 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2346 "add{l}\t{$src2, $dst|$dst, $src2}",
2347 [(store (add (load addr:$dst), i32immSExt8:$src2),
2349 (implicit EFLAGS)]>;
2352 let Uses = [EFLAGS] in {
2353 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2354 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2355 "adc{b}\t{$src2, $dst|$dst, $src2}",
2356 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2357 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2358 (ins GR16:$src1, GR16:$src2),
2359 "adc{w}\t{$src2, $dst|$dst, $src2}",
2360 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2361 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2362 (ins GR32:$src1, GR32:$src2),
2363 "adc{l}\t{$src2, $dst|$dst, $src2}",
2364 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2366 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2367 (ins GR8:$src1, i8mem:$src2),
2368 "adc{b}\t{$src2, $dst|$dst, $src2}",
2369 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2370 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2371 (ins GR16:$src1, i16mem:$src2),
2372 "adc{w}\t{$src2, $dst|$dst, $src2}",
2373 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2375 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2376 (ins GR32:$src1, i32mem:$src2),
2377 "adc{l}\t{$src2, $dst|$dst, $src2}",
2378 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2379 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2380 "adc{b}\t{$src2, $dst|$dst, $src2}",
2381 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2382 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2383 (ins GR16:$src1, i16imm:$src2),
2384 "adc{w}\t{$src2, $dst|$dst, $src2}",
2385 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2386 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2387 (ins GR16:$src1, i16i8imm:$src2),
2388 "adc{w}\t{$src2, $dst|$dst, $src2}",
2389 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2391 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2392 (ins GR32:$src1, i32imm:$src2),
2393 "adc{l}\t{$src2, $dst|$dst, $src2}",
2394 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2395 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2396 (ins GR32:$src1, i32i8imm:$src2),
2397 "adc{l}\t{$src2, $dst|$dst, $src2}",
2398 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2400 let isTwoAddress = 0 in {
2401 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2402 "adc{b}\t{$src2, $dst|$dst, $src2}",
2403 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2404 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2405 "adc{w}\t{$src2, $dst|$dst, $src2}",
2406 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2408 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2409 "adc{l}\t{$src2, $dst|$dst, $src2}",
2410 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2411 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2412 "adc{b}\t{$src2, $dst|$dst, $src2}",
2413 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2414 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2415 "adc{w}\t{$src2, $dst|$dst, $src2}",
2416 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2418 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2419 "adc{w}\t{$src2, $dst|$dst, $src2}",
2420 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2422 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2423 "adc{l}\t{$src2, $dst|$dst, $src2}",
2424 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2425 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2426 "adc{l}\t{$src2, $dst|$dst, $src2}",
2427 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2429 } // Uses = [EFLAGS]
2431 // Register-Register Subtraction
2432 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2433 "sub{b}\t{$src2, $dst|$dst, $src2}",
2434 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2435 (implicit EFLAGS)]>;
2436 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2437 "sub{w}\t{$src2, $dst|$dst, $src2}",
2438 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2439 (implicit EFLAGS)]>, OpSize;
2440 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2441 "sub{l}\t{$src2, $dst|$dst, $src2}",
2442 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2443 (implicit EFLAGS)]>;
2445 // Register-Memory Subtraction
2446 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2447 (ins GR8 :$src1, i8mem :$src2),
2448 "sub{b}\t{$src2, $dst|$dst, $src2}",
2449 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2450 (implicit EFLAGS)]>;
2451 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2452 (ins GR16:$src1, i16mem:$src2),
2453 "sub{w}\t{$src2, $dst|$dst, $src2}",
2454 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2455 (implicit EFLAGS)]>, OpSize;
2456 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2457 (ins GR32:$src1, i32mem:$src2),
2458 "sub{l}\t{$src2, $dst|$dst, $src2}",
2459 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2460 (implicit EFLAGS)]>;
2462 // Register-Integer Subtraction
2463 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2464 (ins GR8:$src1, i8imm:$src2),
2465 "sub{b}\t{$src2, $dst|$dst, $src2}",
2466 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2467 (implicit EFLAGS)]>;
2468 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2469 (ins GR16:$src1, i16imm:$src2),
2470 "sub{w}\t{$src2, $dst|$dst, $src2}",
2471 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2472 (implicit EFLAGS)]>, OpSize;
2473 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2474 (ins GR32:$src1, i32imm:$src2),
2475 "sub{l}\t{$src2, $dst|$dst, $src2}",
2476 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2477 (implicit EFLAGS)]>;
2478 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2479 (ins GR16:$src1, i16i8imm:$src2),
2480 "sub{w}\t{$src2, $dst|$dst, $src2}",
2481 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2482 (implicit EFLAGS)]>, OpSize;
2483 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2484 (ins GR32:$src1, i32i8imm:$src2),
2485 "sub{l}\t{$src2, $dst|$dst, $src2}",
2486 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2487 (implicit EFLAGS)]>;
2489 let isTwoAddress = 0 in {
2490 // Memory-Register Subtraction
2491 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2492 "sub{b}\t{$src2, $dst|$dst, $src2}",
2493 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2494 (implicit EFLAGS)]>;
2495 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2496 "sub{w}\t{$src2, $dst|$dst, $src2}",
2497 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2498 (implicit EFLAGS)]>, OpSize;
2499 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2500 "sub{l}\t{$src2, $dst|$dst, $src2}",
2501 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2502 (implicit EFLAGS)]>;
2504 // Memory-Integer Subtraction
2505 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2506 "sub{b}\t{$src2, $dst|$dst, $src2}",
2507 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2508 (implicit EFLAGS)]>;
2509 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2510 "sub{w}\t{$src2, $dst|$dst, $src2}",
2511 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2512 (implicit EFLAGS)]>, OpSize;
2513 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2514 "sub{l}\t{$src2, $dst|$dst, $src2}",
2515 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2516 (implicit EFLAGS)]>;
2517 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2518 "sub{w}\t{$src2, $dst|$dst, $src2}",
2519 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2521 (implicit EFLAGS)]>, OpSize;
2522 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2523 "sub{l}\t{$src2, $dst|$dst, $src2}",
2524 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2526 (implicit EFLAGS)]>;
2529 let Uses = [EFLAGS] in {
2530 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
2531 (ins GR8:$src1, GR8:$src2),
2532 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2533 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
2534 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
2535 (ins GR16:$src1, GR16:$src2),
2536 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2537 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
2538 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
2539 (ins GR32:$src1, GR32:$src2),
2540 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2541 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2543 let isTwoAddress = 0 in {
2544 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2545 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2546 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
2547 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2548 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2549 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
2551 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2552 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2553 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2554 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2555 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2556 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2557 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
2558 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2559 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2561 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2562 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2563 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2565 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2566 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2567 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2568 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2569 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2570 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2572 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
2573 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2574 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
2575 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
2576 (ins GR16:$src1, i16mem:$src2),
2577 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2578 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
2580 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
2581 (ins GR32:$src1, i32mem:$src2),
2582 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2583 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2584 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2585 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2586 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
2587 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
2588 (ins GR16:$src1, i16imm:$src2),
2589 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2590 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
2591 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
2592 (ins GR16:$src1, i16i8imm:$src2),
2593 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2594 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
2596 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
2597 (ins GR32:$src1, i32imm:$src2),
2598 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2599 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2600 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
2601 (ins GR32:$src1, i32i8imm:$src2),
2602 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2603 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2604 } // Uses = [EFLAGS]
2605 } // Defs = [EFLAGS]
2607 let Defs = [EFLAGS] in {
2608 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2609 // Register-Register Signed Integer Multiply
2610 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2611 "imul{w}\t{$src2, $dst|$dst, $src2}",
2612 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
2613 (implicit EFLAGS)]>, TB, OpSize;
2614 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2615 "imul{l}\t{$src2, $dst|$dst, $src2}",
2616 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
2617 (implicit EFLAGS)]>, TB;
2620 // Register-Memory Signed Integer Multiply
2621 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
2622 (ins GR16:$src1, i16mem:$src2),
2623 "imul{w}\t{$src2, $dst|$dst, $src2}",
2624 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
2625 (implicit EFLAGS)]>, TB, OpSize;
2626 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2627 "imul{l}\t{$src2, $dst|$dst, $src2}",
2628 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
2629 (implicit EFLAGS)]>, TB;
2630 } // Defs = [EFLAGS]
2631 } // end Two Address instructions
2633 // Suprisingly enough, these are not two address instructions!
2634 let Defs = [EFLAGS] in {
2635 // Register-Integer Signed Integer Multiply
2636 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2637 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2638 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2639 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
2640 (implicit EFLAGS)]>, OpSize;
2641 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2642 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2643 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2644 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
2645 (implicit EFLAGS)]>;
2646 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2647 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2648 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2649 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
2650 (implicit EFLAGS)]>, OpSize;
2651 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2652 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2653 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2654 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
2655 (implicit EFLAGS)]>;
2657 // Memory-Integer Signed Integer Multiply
2658 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2659 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2660 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2661 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
2662 (implicit EFLAGS)]>, OpSize;
2663 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2664 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2665 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2666 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
2667 (implicit EFLAGS)]>;
2668 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2669 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2670 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2671 [(set GR16:$dst, (mul (load addr:$src1),
2672 i16immSExt8:$src2)),
2673 (implicit EFLAGS)]>, OpSize;
2674 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2675 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2676 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2677 [(set GR32:$dst, (mul (load addr:$src1),
2678 i32immSExt8:$src2)),
2679 (implicit EFLAGS)]>;
2680 } // Defs = [EFLAGS]
2682 //===----------------------------------------------------------------------===//
2683 // Test instructions are just like AND, except they don't generate a result.
2685 let Defs = [EFLAGS] in {
2686 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2687 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2688 "test{b}\t{$src2, $src1|$src1, $src2}",
2689 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
2690 (implicit EFLAGS)]>;
2691 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2692 "test{w}\t{$src2, $src1|$src1, $src2}",
2693 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
2694 (implicit EFLAGS)]>,
2696 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2697 "test{l}\t{$src2, $src1|$src1, $src2}",
2698 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
2699 (implicit EFLAGS)]>;
2702 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2703 "test{b}\t{$src2, $src1|$src1, $src2}",
2704 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2705 (implicit EFLAGS)]>;
2706 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2707 "test{w}\t{$src2, $src1|$src1, $src2}",
2708 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2709 (implicit EFLAGS)]>, OpSize;
2710 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2711 "test{l}\t{$src2, $src1|$src1, $src2}",
2712 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2713 (implicit EFLAGS)]>;
2715 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2716 (outs), (ins GR8:$src1, i8imm:$src2),
2717 "test{b}\t{$src2, $src1|$src1, $src2}",
2718 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
2719 (implicit EFLAGS)]>;
2720 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2721 (outs), (ins GR16:$src1, i16imm:$src2),
2722 "test{w}\t{$src2, $src1|$src1, $src2}",
2723 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
2724 (implicit EFLAGS)]>, OpSize;
2725 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2726 (outs), (ins GR32:$src1, i32imm:$src2),
2727 "test{l}\t{$src2, $src1|$src1, $src2}",
2728 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
2729 (implicit EFLAGS)]>;
2731 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2732 (outs), (ins i8mem:$src1, i8imm:$src2),
2733 "test{b}\t{$src2, $src1|$src1, $src2}",
2734 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2735 (implicit EFLAGS)]>;
2736 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2737 (outs), (ins i16mem:$src1, i16imm:$src2),
2738 "test{w}\t{$src2, $src1|$src1, $src2}",
2739 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2740 (implicit EFLAGS)]>, OpSize;
2741 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2742 (outs), (ins i32mem:$src1, i32imm:$src2),
2743 "test{l}\t{$src2, $src1|$src1, $src2}",
2744 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2745 (implicit EFLAGS)]>;
2746 } // Defs = [EFLAGS]
2749 // Condition code ops, incl. set if equal/not equal/...
2750 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2751 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2752 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2753 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2755 let Uses = [EFLAGS] in {
2756 def SETEr : I<0x94, MRM0r,
2757 (outs GR8 :$dst), (ins),
2759 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2761 def SETEm : I<0x94, MRM0m,
2762 (outs), (ins i8mem:$dst),
2764 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2767 def SETNEr : I<0x95, MRM0r,
2768 (outs GR8 :$dst), (ins),
2770 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2772 def SETNEm : I<0x95, MRM0m,
2773 (outs), (ins i8mem:$dst),
2775 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2778 def SETLr : I<0x9C, MRM0r,
2779 (outs GR8 :$dst), (ins),
2781 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2782 TB; // GR8 = < signed
2783 def SETLm : I<0x9C, MRM0m,
2784 (outs), (ins i8mem:$dst),
2786 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2787 TB; // [mem8] = < signed
2789 def SETGEr : I<0x9D, MRM0r,
2790 (outs GR8 :$dst), (ins),
2792 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2793 TB; // GR8 = >= signed
2794 def SETGEm : I<0x9D, MRM0m,
2795 (outs), (ins i8mem:$dst),
2797 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2798 TB; // [mem8] = >= signed
2800 def SETLEr : I<0x9E, MRM0r,
2801 (outs GR8 :$dst), (ins),
2803 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2804 TB; // GR8 = <= signed
2805 def SETLEm : I<0x9E, MRM0m,
2806 (outs), (ins i8mem:$dst),
2808 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2809 TB; // [mem8] = <= signed
2811 def SETGr : I<0x9F, MRM0r,
2812 (outs GR8 :$dst), (ins),
2814 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2815 TB; // GR8 = > signed
2816 def SETGm : I<0x9F, MRM0m,
2817 (outs), (ins i8mem:$dst),
2819 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2820 TB; // [mem8] = > signed
2822 def SETBr : I<0x92, MRM0r,
2823 (outs GR8 :$dst), (ins),
2825 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2826 TB; // GR8 = < unsign
2827 def SETBm : I<0x92, MRM0m,
2828 (outs), (ins i8mem:$dst),
2830 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
2831 TB; // [mem8] = < unsign
2833 def SETAEr : I<0x93, MRM0r,
2834 (outs GR8 :$dst), (ins),
2836 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
2837 TB; // GR8 = >= unsign
2838 def SETAEm : I<0x93, MRM0m,
2839 (outs), (ins i8mem:$dst),
2841 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
2842 TB; // [mem8] = >= unsign
2844 def SETBEr : I<0x96, MRM0r,
2845 (outs GR8 :$dst), (ins),
2847 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
2848 TB; // GR8 = <= unsign
2849 def SETBEm : I<0x96, MRM0m,
2850 (outs), (ins i8mem:$dst),
2852 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
2853 TB; // [mem8] = <= unsign
2855 def SETAr : I<0x97, MRM0r,
2856 (outs GR8 :$dst), (ins),
2858 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
2859 TB; // GR8 = > signed
2860 def SETAm : I<0x97, MRM0m,
2861 (outs), (ins i8mem:$dst),
2863 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
2864 TB; // [mem8] = > signed
2866 def SETSr : I<0x98, MRM0r,
2867 (outs GR8 :$dst), (ins),
2869 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
2870 TB; // GR8 = <sign bit>
2871 def SETSm : I<0x98, MRM0m,
2872 (outs), (ins i8mem:$dst),
2874 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
2875 TB; // [mem8] = <sign bit>
2876 def SETNSr : I<0x99, MRM0r,
2877 (outs GR8 :$dst), (ins),
2879 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
2880 TB; // GR8 = !<sign bit>
2881 def SETNSm : I<0x99, MRM0m,
2882 (outs), (ins i8mem:$dst),
2884 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
2885 TB; // [mem8] = !<sign bit>
2887 def SETPr : I<0x9A, MRM0r,
2888 (outs GR8 :$dst), (ins),
2890 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
2892 def SETPm : I<0x9A, MRM0m,
2893 (outs), (ins i8mem:$dst),
2895 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
2896 TB; // [mem8] = parity
2897 def SETNPr : I<0x9B, MRM0r,
2898 (outs GR8 :$dst), (ins),
2900 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
2901 TB; // GR8 = not parity
2902 def SETNPm : I<0x9B, MRM0m,
2903 (outs), (ins i8mem:$dst),
2905 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
2906 TB; // [mem8] = not parity
2908 def SETOr : I<0x90, MRM0r,
2909 (outs GR8 :$dst), (ins),
2911 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
2912 TB; // GR8 = overflow
2913 def SETOm : I<0x90, MRM0m,
2914 (outs), (ins i8mem:$dst),
2916 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
2917 TB; // [mem8] = overflow
2918 def SETNOr : I<0x91, MRM0r,
2919 (outs GR8 :$dst), (ins),
2921 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
2922 TB; // GR8 = not overflow
2923 def SETNOm : I<0x91, MRM0m,
2924 (outs), (ins i8mem:$dst),
2926 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
2927 TB; // [mem8] = not overflow
2928 } // Uses = [EFLAGS]
2931 // Integer comparisons
2932 let Defs = [EFLAGS] in {
2933 def CMP8rr : I<0x38, MRMDestReg,
2934 (outs), (ins GR8 :$src1, GR8 :$src2),
2935 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2936 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2937 def CMP16rr : I<0x39, MRMDestReg,
2938 (outs), (ins GR16:$src1, GR16:$src2),
2939 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2940 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
2941 def CMP32rr : I<0x39, MRMDestReg,
2942 (outs), (ins GR32:$src1, GR32:$src2),
2943 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2944 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
2945 def CMP8mr : I<0x38, MRMDestMem,
2946 (outs), (ins i8mem :$src1, GR8 :$src2),
2947 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2948 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
2949 (implicit EFLAGS)]>;
2950 def CMP16mr : I<0x39, MRMDestMem,
2951 (outs), (ins i16mem:$src1, GR16:$src2),
2952 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2953 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
2954 (implicit EFLAGS)]>, OpSize;
2955 def CMP32mr : I<0x39, MRMDestMem,
2956 (outs), (ins i32mem:$src1, GR32:$src2),
2957 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2958 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
2959 (implicit EFLAGS)]>;
2960 def CMP8rm : I<0x3A, MRMSrcMem,
2961 (outs), (ins GR8 :$src1, i8mem :$src2),
2962 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2963 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
2964 (implicit EFLAGS)]>;
2965 def CMP16rm : I<0x3B, MRMSrcMem,
2966 (outs), (ins GR16:$src1, i16mem:$src2),
2967 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2968 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
2969 (implicit EFLAGS)]>, OpSize;
2970 def CMP32rm : I<0x3B, MRMSrcMem,
2971 (outs), (ins GR32:$src1, i32mem:$src2),
2972 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2973 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
2974 (implicit EFLAGS)]>;
2975 def CMP8ri : Ii8<0x80, MRM7r,
2976 (outs), (ins GR8:$src1, i8imm:$src2),
2977 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2978 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
2979 def CMP16ri : Ii16<0x81, MRM7r,
2980 (outs), (ins GR16:$src1, i16imm:$src2),
2981 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2982 [(X86cmp GR16:$src1, imm:$src2),
2983 (implicit EFLAGS)]>, OpSize;
2984 def CMP32ri : Ii32<0x81, MRM7r,
2985 (outs), (ins GR32:$src1, i32imm:$src2),
2986 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2987 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
2988 def CMP8mi : Ii8 <0x80, MRM7m,
2989 (outs), (ins i8mem :$src1, i8imm :$src2),
2990 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2991 [(X86cmp (loadi8 addr:$src1), imm:$src2),
2992 (implicit EFLAGS)]>;
2993 def CMP16mi : Ii16<0x81, MRM7m,
2994 (outs), (ins i16mem:$src1, i16imm:$src2),
2995 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2996 [(X86cmp (loadi16 addr:$src1), imm:$src2),
2997 (implicit EFLAGS)]>, OpSize;
2998 def CMP32mi : Ii32<0x81, MRM7m,
2999 (outs), (ins i32mem:$src1, i32imm:$src2),
3000 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3001 [(X86cmp (loadi32 addr:$src1), imm:$src2),
3002 (implicit EFLAGS)]>;
3003 def CMP16ri8 : Ii8<0x83, MRM7r,
3004 (outs), (ins GR16:$src1, i16i8imm:$src2),
3005 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3006 [(X86cmp GR16:$src1, i16immSExt8:$src2),
3007 (implicit EFLAGS)]>, OpSize;
3008 def CMP16mi8 : Ii8<0x83, MRM7m,
3009 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3010 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3011 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
3012 (implicit EFLAGS)]>, OpSize;
3013 def CMP32mi8 : Ii8<0x83, MRM7m,
3014 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3015 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3016 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
3017 (implicit EFLAGS)]>;
3018 def CMP32ri8 : Ii8<0x83, MRM7r,
3019 (outs), (ins GR32:$src1, i32i8imm:$src2),
3020 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3021 [(X86cmp GR32:$src1, i32immSExt8:$src2),
3022 (implicit EFLAGS)]>;
3023 } // Defs = [EFLAGS]
3026 // TODO: BTC, BTR, and BTS
3027 let Defs = [EFLAGS] in {
3028 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3029 "bt{w}\t{$src2, $src1|$src1, $src2}",
3030 [(X86bt GR16:$src1, GR16:$src2),
3031 (implicit EFLAGS)]>, OpSize, TB;
3032 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3033 "bt{l}\t{$src2, $src1|$src1, $src2}",
3034 [(X86bt GR32:$src1, GR32:$src2),
3035 (implicit EFLAGS)]>, TB;
3037 // Unlike with the register+register form, the memory+register form of the
3038 // bt instruction does not ignore the high bits of the index. From ISel's
3039 // perspective, this is pretty bizarre. Disable these instructions for now.
3040 //def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3041 // "bt{w}\t{$src2, $src1|$src1, $src2}",
3042 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3043 // (implicit EFLAGS)]>, OpSize, TB, Requires<[FastBTMem]>;
3044 //def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3045 // "bt{l}\t{$src2, $src1|$src1, $src2}",
3046 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3047 // (implicit EFLAGS)]>, TB, Requires<[FastBTMem]>;
3049 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3050 "bt{w}\t{$src2, $src1|$src1, $src2}",
3051 [(X86bt GR16:$src1, i16immSExt8:$src2),
3052 (implicit EFLAGS)]>, OpSize, TB;
3053 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3054 "bt{l}\t{$src2, $src1|$src1, $src2}",
3055 [(X86bt GR32:$src1, i32immSExt8:$src2),
3056 (implicit EFLAGS)]>, TB;
3057 // Note that these instructions don't need FastBTMem because that
3058 // only applies when the other operand is in a register. When it's
3059 // an immediate, bt is still fast.
3060 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3061 "bt{w}\t{$src2, $src1|$src1, $src2}",
3062 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
3063 (implicit EFLAGS)]>, OpSize, TB;
3064 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3065 "bt{l}\t{$src2, $src1|$src1, $src2}",
3066 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
3067 (implicit EFLAGS)]>, TB;
3068 } // Defs = [EFLAGS]
3070 // Sign/Zero extenders
3071 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3072 // of the register here. This has a smaller encoding and avoids a
3073 // partial-register update.
3074 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3075 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3076 [(set GR16:$dst, (sext GR8:$src))]>, TB;
3077 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3078 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3079 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3080 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3081 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3082 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3083 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3084 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3085 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3086 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3087 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3088 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3089 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3090 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3091 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3093 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3094 // of the register here. This has a smaller encoding and avoids a
3095 // partial-register update.
3096 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3097 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3098 [(set GR16:$dst, (zext GR8:$src))]>, TB;
3099 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3100 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3101 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3102 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3103 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3104 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3105 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3106 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3107 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3108 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3109 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3110 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3111 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3112 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3113 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3115 // These are the same as the regular regular MOVZX32rr8 and MOVZX32rm8
3116 // except that they use GR32_NOREX for the output operand register class
3117 // instead of GR32. This allows them to operate on h registers on x86-64.
3118 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3119 (outs GR32_NOREX:$dst), (ins GR8:$src),
3120 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3123 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3124 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3125 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3128 let neverHasSideEffects = 1 in {
3129 let Defs = [AX], Uses = [AL] in
3130 def CBW : I<0x98, RawFrm, (outs), (ins),
3131 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3132 let Defs = [EAX], Uses = [AX] in
3133 def CWDE : I<0x98, RawFrm, (outs), (ins),
3134 "{cwtl|cwde}", []>; // EAX = signext(AX)
3136 let Defs = [AX,DX], Uses = [AX] in
3137 def CWD : I<0x99, RawFrm, (outs), (ins),
3138 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3139 let Defs = [EAX,EDX], Uses = [EAX] in
3140 def CDQ : I<0x99, RawFrm, (outs), (ins),
3141 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3144 //===----------------------------------------------------------------------===//
3145 // Alias Instructions
3146 //===----------------------------------------------------------------------===//
3148 // Alias instructions that map movr0 to xor.
3149 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3150 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1 in {
3151 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
3152 "xor{b}\t$dst, $dst",
3153 [(set GR8:$dst, 0)]>;
3154 // Use xorl instead of xorw since we don't care about the high 16 bits,
3155 // it's smaller, and it avoids a partial-register update.
3156 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3157 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
3158 [(set GR16:$dst, 0)]>;
3159 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
3160 "xor{l}\t$dst, $dst",
3161 [(set GR32:$dst, 0)]>;
3164 //===----------------------------------------------------------------------===//
3165 // Thread Local Storage Instructions
3168 // All calls clobber the non-callee saved registers. ESP is marked as
3169 // a use to prevent stack-pointer assignments that appear immediately
3170 // before calls from potentially appearing dead.
3171 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3172 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3173 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3174 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3176 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3177 "leal\t$sym, %eax; "
3178 "call\t___tls_get_addr@PLT",
3179 [(X86tlsaddr tls32addr:$sym)]>,
3180 Requires<[In32BitMode]>;
3182 let AddedComplexity = 5 in
3183 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3184 "movl\t%gs:$src, $dst",
3185 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3187 let AddedComplexity = 5 in
3188 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3189 "movl\t%fs:$src, $dst",
3190 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3192 //===----------------------------------------------------------------------===//
3193 // DWARF Pseudo Instructions
3196 def DWARF_LOC : I<0, Pseudo, (outs),
3197 (ins i32imm:$line, i32imm:$col, i32imm:$file),
3198 ".loc\t$file $line $col",
3199 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
3202 //===----------------------------------------------------------------------===//
3203 // EH Pseudo Instructions
3205 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3207 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3208 "ret\t#eh_return, addr: $addr",
3209 [(X86ehret GR32:$addr)]>;
3213 //===----------------------------------------------------------------------===//
3217 // Atomic swap. These are just normal xchg instructions. But since a memory
3218 // operand is referenced, the atomicity is ensured.
3219 let Constraints = "$val = $dst" in {
3220 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3221 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3222 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3223 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3224 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3225 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3227 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3228 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3229 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3232 // Atomic compare and swap.
3233 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3234 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3236 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3237 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3239 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3240 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
3243 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3246 let Defs = [AX, EFLAGS], Uses = [AX] in {
3247 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3249 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3250 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3252 let Defs = [AL, EFLAGS], Uses = [AL] in {
3253 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3255 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3256 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3259 // Atomic exchange and add
3260 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3261 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3263 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3264 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3266 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3268 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3269 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3271 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3273 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3274 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3278 // Optimized codegen when the non-memory output is not used.
3279 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3280 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3282 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3283 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3285 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3286 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3288 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3289 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3291 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3292 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3294 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3295 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3297 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3298 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3300 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3301 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3303 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3305 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3307 "inc{b}\t$dst", []>, LOCK;
3308 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3310 "inc{w}\t$dst", []>, OpSize, LOCK;
3311 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3313 "inc{l}\t$dst", []>, LOCK;
3315 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3317 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3318 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3320 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3321 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3323 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3324 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3326 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3327 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3329 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3330 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3332 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3333 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3335 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3336 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3338 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3340 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3342 "dec{b}\t$dst", []>, LOCK;
3343 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3345 "dec{w}\t$dst", []>, OpSize, LOCK;
3346 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3348 "dec{l}\t$dst", []>, LOCK;
3350 // Atomic exchange, and, or, xor
3351 let Constraints = "$val = $dst", Defs = [EFLAGS],
3352 usesCustomDAGSchedInserter = 1 in {
3353 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3354 "#ATOMAND32 PSEUDO!",
3355 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3356 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3357 "#ATOMOR32 PSEUDO!",
3358 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
3359 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3360 "#ATOMXOR32 PSEUDO!",
3361 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
3362 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3363 "#ATOMNAND32 PSEUDO!",
3364 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
3365 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3366 "#ATOMMIN32 PSEUDO!",
3367 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
3368 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3369 "#ATOMMAX32 PSEUDO!",
3370 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
3371 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3372 "#ATOMUMIN32 PSEUDO!",
3373 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
3374 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3375 "#ATOMUMAX32 PSEUDO!",
3376 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
3378 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3379 "#ATOMAND16 PSEUDO!",
3380 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
3381 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3382 "#ATOMOR16 PSEUDO!",
3383 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
3384 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3385 "#ATOMXOR16 PSEUDO!",
3386 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
3387 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3388 "#ATOMNAND16 PSEUDO!",
3389 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
3390 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3391 "#ATOMMIN16 PSEUDO!",
3392 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
3393 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3394 "#ATOMMAX16 PSEUDO!",
3395 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
3396 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3397 "#ATOMUMIN16 PSEUDO!",
3398 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
3399 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3400 "#ATOMUMAX16 PSEUDO!",
3401 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
3403 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3404 "#ATOMAND8 PSEUDO!",
3405 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
3406 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3408 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
3409 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3410 "#ATOMXOR8 PSEUDO!",
3411 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
3412 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3413 "#ATOMNAND8 PSEUDO!",
3414 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
3417 let Constraints = "$val1 = $dst1, $val2 = $dst2",
3418 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
3419 Uses = [EAX, EBX, ECX, EDX],
3420 mayLoad = 1, mayStore = 1,
3421 usesCustomDAGSchedInserter = 1 in {
3422 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3423 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3424 "#ATOMAND6432 PSEUDO!", []>;
3425 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3426 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3427 "#ATOMOR6432 PSEUDO!", []>;
3428 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3429 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3430 "#ATOMXOR6432 PSEUDO!", []>;
3431 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3432 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3433 "#ATOMNAND6432 PSEUDO!", []>;
3434 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3435 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3436 "#ATOMADD6432 PSEUDO!", []>;
3437 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3438 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3439 "#ATOMSUB6432 PSEUDO!", []>;
3440 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3441 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3442 "#ATOMSWAP6432 PSEUDO!", []>;
3445 //===----------------------------------------------------------------------===//
3446 // Non-Instruction Patterns
3447 //===----------------------------------------------------------------------===//
3449 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
3450 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
3451 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
3452 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
3453 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
3454 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
3456 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
3457 (ADD32ri GR32:$src1, tconstpool:$src2)>;
3458 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
3459 (ADD32ri GR32:$src1, tjumptable:$src2)>;
3460 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
3461 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
3462 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
3463 (ADD32ri GR32:$src1, texternalsym:$src2)>;
3465 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
3466 (MOV32mi addr:$dst, tglobaladdr:$src)>;
3467 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
3468 (MOV32mi addr:$dst, texternalsym:$src)>;
3472 def : Pat<(X86tcret GR32:$dst, imm:$off),
3473 (TCRETURNri GR32:$dst, imm:$off)>;
3475 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
3476 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3478 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
3479 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3481 // Normal calls, with various flavors of addresses.
3482 def : Pat<(X86call (i32 tglobaladdr:$dst)),
3483 (CALLpcrel32 tglobaladdr:$dst)>;
3484 def : Pat<(X86call (i32 texternalsym:$dst)),
3485 (CALLpcrel32 texternalsym:$dst)>;
3486 def : Pat<(X86call (i32 imm:$dst)),
3487 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
3489 // X86 specific add which produces a flag.
3490 def : Pat<(addc GR32:$src1, GR32:$src2),
3491 (ADD32rr GR32:$src1, GR32:$src2)>;
3492 def : Pat<(addc GR32:$src1, (load addr:$src2)),
3493 (ADD32rm GR32:$src1, addr:$src2)>;
3494 def : Pat<(addc GR32:$src1, imm:$src2),
3495 (ADD32ri GR32:$src1, imm:$src2)>;
3496 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
3497 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3499 def : Pat<(subc GR32:$src1, GR32:$src2),
3500 (SUB32rr GR32:$src1, GR32:$src2)>;
3501 def : Pat<(subc GR32:$src1, (load addr:$src2)),
3502 (SUB32rm GR32:$src1, addr:$src2)>;
3503 def : Pat<(subc GR32:$src1, imm:$src2),
3504 (SUB32ri GR32:$src1, imm:$src2)>;
3505 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
3506 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3510 // TEST R,R is smaller than CMP R,0
3511 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
3512 (TEST8rr GR8:$src1, GR8:$src1)>;
3513 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
3514 (TEST16rr GR16:$src1, GR16:$src1)>;
3515 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
3516 (TEST32rr GR32:$src1, GR32:$src1)>;
3518 // Conditional moves with folded loads with operands swapped and conditions
3520 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
3521 (CMOVAE16rm GR16:$src2, addr:$src1)>;
3522 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
3523 (CMOVAE32rm GR32:$src2, addr:$src1)>;
3524 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
3525 (CMOVB16rm GR16:$src2, addr:$src1)>;
3526 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
3527 (CMOVB32rm GR32:$src2, addr:$src1)>;
3528 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
3529 (CMOVNE16rm GR16:$src2, addr:$src1)>;
3530 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
3531 (CMOVNE32rm GR32:$src2, addr:$src1)>;
3532 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
3533 (CMOVE16rm GR16:$src2, addr:$src1)>;
3534 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
3535 (CMOVE32rm GR32:$src2, addr:$src1)>;
3536 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
3537 (CMOVA16rm GR16:$src2, addr:$src1)>;
3538 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
3539 (CMOVA32rm GR32:$src2, addr:$src1)>;
3540 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
3541 (CMOVBE16rm GR16:$src2, addr:$src1)>;
3542 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
3543 (CMOVBE32rm GR32:$src2, addr:$src1)>;
3544 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
3545 (CMOVGE16rm GR16:$src2, addr:$src1)>;
3546 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
3547 (CMOVGE32rm GR32:$src2, addr:$src1)>;
3548 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
3549 (CMOVL16rm GR16:$src2, addr:$src1)>;
3550 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
3551 (CMOVL32rm GR32:$src2, addr:$src1)>;
3552 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
3553 (CMOVG16rm GR16:$src2, addr:$src1)>;
3554 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
3555 (CMOVG32rm GR32:$src2, addr:$src1)>;
3556 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
3557 (CMOVLE16rm GR16:$src2, addr:$src1)>;
3558 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
3559 (CMOVLE32rm GR32:$src2, addr:$src1)>;
3560 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
3561 (CMOVNP16rm GR16:$src2, addr:$src1)>;
3562 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
3563 (CMOVNP32rm GR32:$src2, addr:$src1)>;
3564 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
3565 (CMOVP16rm GR16:$src2, addr:$src1)>;
3566 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
3567 (CMOVP32rm GR32:$src2, addr:$src1)>;
3568 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
3569 (CMOVNS16rm GR16:$src2, addr:$src1)>;
3570 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
3571 (CMOVNS32rm GR32:$src2, addr:$src1)>;
3572 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
3573 (CMOVS16rm GR16:$src2, addr:$src1)>;
3574 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
3575 (CMOVS32rm GR32:$src2, addr:$src1)>;
3576 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
3577 (CMOVNO16rm GR16:$src2, addr:$src1)>;
3578 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
3579 (CMOVNO32rm GR32:$src2, addr:$src1)>;
3580 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
3581 (CMOVO16rm GR16:$src2, addr:$src1)>;
3582 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
3583 (CMOVO32rm GR32:$src2, addr:$src1)>;
3585 // zextload bool -> zextload byte
3586 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3587 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3588 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3590 // extload bool -> extload byte
3591 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3592 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>,
3593 Requires<[In32BitMode]>;
3594 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3595 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>,
3596 Requires<[In32BitMode]>;
3597 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
3598 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
3601 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>,
3602 Requires<[In32BitMode]>;
3603 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>,
3604 Requires<[In32BitMode]>;
3605 def : Pat<(i32 (anyext GR16:$src)),
3606 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
3608 // (and (i32 load), 255) -> (zextload i8)
3609 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
3610 (MOVZX32rm8 addr:$src)>;
3611 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
3612 (MOVZX32rm16 addr:$src)>;
3614 //===----------------------------------------------------------------------===//
3616 //===----------------------------------------------------------------------===//
3618 // Odd encoding trick: -128 fits into an 8-bit immediate field while
3619 // +128 doesn't, so in this special case use a sub instead of an add.
3620 def : Pat<(add GR16:$src1, 128),
3621 (SUB16ri8 GR16:$src1, -128)>;
3622 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
3623 (SUB16mi8 addr:$dst, -128)>;
3624 def : Pat<(add GR32:$src1, 128),
3625 (SUB32ri8 GR32:$src1, -128)>;
3626 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
3627 (SUB32mi8 addr:$dst, -128)>;
3629 // r & (2^16-1) ==> movz
3630 def : Pat<(and GR32:$src1, 0xffff),
3631 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
3632 // r & (2^8-1) ==> movz
3633 def : Pat<(and GR32:$src1, 0xff),
3634 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src1, GR32_ABCD),
3636 Requires<[In32BitMode]>;
3637 // r & (2^8-1) ==> movz
3638 def : Pat<(and GR16:$src1, 0xff),
3639 (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD),
3641 Requires<[In32BitMode]>;
3643 // sext_inreg patterns
3644 def : Pat<(sext_inreg GR32:$src, i16),
3645 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
3646 def : Pat<(sext_inreg GR32:$src, i8),
3647 (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3649 Requires<[In32BitMode]>;
3650 def : Pat<(sext_inreg GR16:$src, i8),
3651 (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3653 Requires<[In32BitMode]>;
3656 def : Pat<(i16 (trunc GR32:$src)),
3657 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
3658 def : Pat<(i8 (trunc GR32:$src)),
3659 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3661 Requires<[In32BitMode]>;
3662 def : Pat<(i8 (trunc GR16:$src)),
3663 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3665 Requires<[In32BitMode]>;
3667 // h-register tricks
3668 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
3669 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3670 x86_subreg_8bit_hi)>,
3671 Requires<[In32BitMode]>;
3672 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
3673 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3674 x86_subreg_8bit_hi)>,
3675 Requires<[In32BitMode]>;
3676 def : Pat<(srl_su GR16:$src, (i8 8)),
3679 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3680 x86_subreg_8bit_hi)),
3682 Requires<[In32BitMode]>;
3683 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
3684 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3685 x86_subreg_8bit_hi))>,
3686 Requires<[In32BitMode]>;
3687 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
3688 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3689 x86_subreg_8bit_hi))>,
3690 Requires<[In32BitMode]>;
3692 // (shl x, 1) ==> (add x, x)
3693 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
3694 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
3695 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
3697 // (shl x (and y, 31)) ==> (shl x, y)
3698 def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
3699 (SHL8rCL GR8:$src1)>;
3700 def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
3701 (SHL16rCL GR16:$src1)>;
3702 def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
3703 (SHL32rCL GR32:$src1)>;
3704 def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3705 (SHL8mCL addr:$dst)>;
3706 def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3707 (SHL16mCL addr:$dst)>;
3708 def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3709 (SHL32mCL addr:$dst)>;
3711 def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
3712 (SHR8rCL GR8:$src1)>;
3713 def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
3714 (SHR16rCL GR16:$src1)>;
3715 def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
3716 (SHR32rCL GR32:$src1)>;
3717 def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3718 (SHR8mCL addr:$dst)>;
3719 def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3720 (SHR16mCL addr:$dst)>;
3721 def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3722 (SHR32mCL addr:$dst)>;
3724 def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
3725 (SAR8rCL GR8:$src1)>;
3726 def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
3727 (SAR16rCL GR16:$src1)>;
3728 def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
3729 (SAR32rCL GR32:$src1)>;
3730 def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3731 (SAR8mCL addr:$dst)>;
3732 def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3733 (SAR16mCL addr:$dst)>;
3734 def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3735 (SAR32mCL addr:$dst)>;
3737 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
3738 def : Pat<(or (srl GR32:$src1, CL:$amt),
3739 (shl GR32:$src2, (sub 32, CL:$amt))),
3740 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3742 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
3743 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3744 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3746 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
3747 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3748 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3750 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3751 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3753 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3755 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3756 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3758 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
3759 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3760 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3762 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
3763 def : Pat<(or (shl GR32:$src1, CL:$amt),
3764 (srl GR32:$src2, (sub 32, CL:$amt))),
3765 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3767 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
3768 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3769 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3771 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
3772 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3773 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3775 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3776 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3778 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3780 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3781 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3783 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
3784 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3785 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3787 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
3788 def : Pat<(or (srl GR16:$src1, CL:$amt),
3789 (shl GR16:$src2, (sub 16, CL:$amt))),
3790 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3792 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
3793 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3794 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3796 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
3797 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3798 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3800 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3801 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3803 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3805 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3806 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3808 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
3809 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3810 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3812 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
3813 def : Pat<(or (shl GR16:$src1, CL:$amt),
3814 (srl GR16:$src2, (sub 16, CL:$amt))),
3815 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3817 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
3818 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3819 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3821 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
3822 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3823 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3825 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3826 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3828 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3830 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3831 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3833 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
3834 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3835 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3837 //===----------------------------------------------------------------------===//
3838 // EFLAGS-defining Patterns
3839 //===----------------------------------------------------------------------===//
3841 // Register-Register Addition with EFLAGS result
3842 def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
3844 (ADD8rr GR8:$src1, GR8:$src2)>;
3845 def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
3847 (ADD16rr GR16:$src1, GR16:$src2)>;
3848 def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
3850 (ADD32rr GR32:$src1, GR32:$src2)>;
3852 // Register-Memory Addition with EFLAGS result
3853 def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
3855 (ADD8rm GR8:$src1, addr:$src2)>;
3856 def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
3858 (ADD16rm GR16:$src1, addr:$src2)>;
3859 def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
3861 (ADD32rm GR32:$src1, addr:$src2)>;
3863 // Register-Integer Addition with EFLAGS result
3864 def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
3866 (ADD8ri GR8:$src1, imm:$src2)>;
3867 def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
3869 (ADD16ri GR16:$src1, imm:$src2)>;
3870 def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
3872 (ADD32ri GR32:$src1, imm:$src2)>;
3873 def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
3875 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
3876 def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
3878 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3880 // Memory-Register Addition with EFLAGS result
3881 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
3884 (ADD8mr addr:$dst, GR8:$src2)>;
3885 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
3888 (ADD16mr addr:$dst, GR16:$src2)>;
3889 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
3892 (ADD32mr addr:$dst, GR32:$src2)>;
3894 // Memory-Integer Addition with EFLAGS result
3895 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
3898 (ADD8mi addr:$dst, imm:$src2)>;
3899 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
3902 (ADD16mi addr:$dst, imm:$src2)>;
3903 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
3906 (ADD32mi addr:$dst, imm:$src2)>;
3907 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
3910 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
3911 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
3914 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
3916 // Register-Register Subtraction with EFLAGS result
3917 def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
3919 (SUB8rr GR8:$src1, GR8:$src2)>;
3920 def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
3922 (SUB16rr GR16:$src1, GR16:$src2)>;
3923 def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
3925 (SUB32rr GR32:$src1, GR32:$src2)>;
3927 // Register-Memory Subtraction with EFLAGS result
3928 def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
3930 (SUB8rm GR8:$src1, addr:$src2)>;
3931 def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
3933 (SUB16rm GR16:$src1, addr:$src2)>;
3934 def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
3936 (SUB32rm GR32:$src1, addr:$src2)>;
3938 // Register-Integer Subtraction with EFLAGS result
3939 def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
3941 (SUB8ri GR8:$src1, imm:$src2)>;
3942 def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
3944 (SUB16ri GR16:$src1, imm:$src2)>;
3945 def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
3947 (SUB32ri GR32:$src1, imm:$src2)>;
3948 def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
3950 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
3951 def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
3953 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3955 // Memory-Register Subtraction with EFLAGS result
3956 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
3959 (SUB8mr addr:$dst, GR8:$src2)>;
3960 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
3963 (SUB16mr addr:$dst, GR16:$src2)>;
3964 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
3967 (SUB32mr addr:$dst, GR32:$src2)>;
3969 // Memory-Integer Subtraction with EFLAGS result
3970 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
3973 (SUB8mi addr:$dst, imm:$src2)>;
3974 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
3977 (SUB16mi addr:$dst, imm:$src2)>;
3978 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
3981 (SUB32mi addr:$dst, imm:$src2)>;
3982 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
3985 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
3986 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
3989 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
3992 // Register-Register Signed Integer Multiply with EFLAGS result
3993 def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
3995 (IMUL16rr GR16:$src1, GR16:$src2)>;
3996 def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
3998 (IMUL32rr GR32:$src1, GR32:$src2)>;
4000 // Register-Memory Signed Integer Multiply with EFLAGS result
4001 def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
4003 (IMUL16rm GR16:$src1, addr:$src2)>;
4004 def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
4006 (IMUL32rm GR32:$src1, addr:$src2)>;
4008 // Register-Integer Signed Integer Multiply with EFLAGS result
4009 def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
4011 (IMUL16rri GR16:$src1, imm:$src2)>;
4012 def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
4014 (IMUL32rri GR32:$src1, imm:$src2)>;
4015 def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
4017 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4018 def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
4020 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4022 // Memory-Integer Signed Integer Multiply with EFLAGS result
4023 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
4025 (IMUL16rmi addr:$src1, imm:$src2)>;
4026 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
4028 (IMUL32rmi addr:$src1, imm:$src2)>;
4029 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
4031 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4032 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
4034 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4036 // Optimize multiply by 2 with EFLAGS result.
4037 let AddedComplexity = 2 in {
4038 def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
4040 (ADD16rr GR16:$src1, GR16:$src1)>;
4042 def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
4044 (ADD32rr GR32:$src1, GR32:$src1)>;
4047 // INC and DEC with EFLAGS result. Note that these do not set CF.
4048 def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
4050 def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
4053 def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
4055 def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
4059 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
4060 (INC16r GR16:$src)>, Requires<[In32BitMode]>;
4061 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
4063 (INC16m addr:$dst)>, Requires<[In32BitMode]>;
4064 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
4065 (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
4066 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
4068 (DEC16m addr:$dst)>, Requires<[In32BitMode]>;
4070 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
4071 (INC32r GR32:$src)>, Requires<[In32BitMode]>;
4072 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
4074 (INC32m addr:$dst)>, Requires<[In32BitMode]>;
4075 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
4076 (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
4077 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
4079 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
4081 //===----------------------------------------------------------------------===//
4082 // Floating Point Stack Support
4083 //===----------------------------------------------------------------------===//
4085 include "X86InstrFPStack.td"
4087 //===----------------------------------------------------------------------===//
4089 //===----------------------------------------------------------------------===//
4091 include "X86Instr64bit.td"
4093 //===----------------------------------------------------------------------===//
4094 // XMM Floating point support (requires SSE / SSE2)
4095 //===----------------------------------------------------------------------===//
4097 include "X86InstrSSE.td"
4099 //===----------------------------------------------------------------------===//
4100 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
4101 //===----------------------------------------------------------------------===//
4103 include "X86InstrMMX.td"