1 //===----------------------------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
32 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
34 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTX86BrCond : SDTypeProfile<0, 3,
39 [SDTCisVT<0, OtherVT>,
40 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
42 def SDTX86SetCC : SDTypeProfile<1, 2,
44 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86SetCC_C : SDTypeProfile<1, 2,
47 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
49 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
51 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
53 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
54 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
55 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
57 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
58 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
61 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
63 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
67 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
69 def SDTX86Void : SDTypeProfile<0, 0, []>;
71 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
73 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
75 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
77 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
79 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
81 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
82 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
83 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
84 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
86 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
87 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
89 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
90 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
92 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
93 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
95 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
96 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
98 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
99 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
101 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
102 [SDNPHasChain, SDNPMayStore,
103 SDNPMayLoad, SDNPMemOperand]>;
104 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
105 [SDNPHasChain, SDNPMayStore,
106 SDNPMayLoad, SDNPMemOperand]>;
107 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
108 [SDNPHasChain, SDNPMayStore,
109 SDNPMayLoad, SDNPMemOperand]>;
110 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
111 [SDNPHasChain, SDNPMayStore,
112 SDNPMayLoad, SDNPMemOperand]>;
113 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
114 [SDNPHasChain, SDNPMayStore,
115 SDNPMayLoad, SDNPMemOperand]>;
116 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
117 [SDNPHasChain, SDNPMayStore,
118 SDNPMayLoad, SDNPMemOperand]>;
119 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
120 [SDNPHasChain, SDNPMayStore,
121 SDNPMayLoad, SDNPMemOperand]>;
122 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
123 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
125 def X86vastart_save_xmm_regs :
126 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
127 SDT_X86VASTART_SAVE_XMM_REGS,
128 [SDNPHasChain, SDNPVariadic]>;
130 def X86callseq_start :
131 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
132 [SDNPHasChain, SDNPOutFlag]>;
134 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
135 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
137 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
138 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
141 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
142 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
143 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
144 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
147 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
148 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
150 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
151 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
153 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
154 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
155 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
156 SDT_X86SegmentBaseAddress, []>;
158 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
161 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
162 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
164 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
166 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
167 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
169 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
172 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
173 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
174 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
176 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
178 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
181 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
183 def X86MingwAlloca : SDNode<"X86ISD::MINGW_ALLOCA", SDTX86Void,
184 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
186 //===----------------------------------------------------------------------===//
187 // X86 Operand Definitions.
190 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
191 // the index operand of an address, to conform to x86 encoding restrictions.
192 def ptr_rc_nosp : PointerLikeRegClass<1>;
194 // *mem - Operand definitions for the funky X86 addressing mode operands.
196 def X86MemAsmOperand : AsmOperandClass {
198 let SuperClasses = [];
200 def X86NoSegMemAsmOperand : AsmOperandClass {
201 let Name = "NoSegMem";
202 let SuperClasses = [X86MemAsmOperand];
204 def X86AbsMemAsmOperand : AsmOperandClass {
206 let SuperClasses = [X86NoSegMemAsmOperand];
208 class X86MemOperand<string printMethod> : Operand<iPTR> {
209 let PrintMethod = printMethod;
210 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
211 let ParserMatchClass = X86MemAsmOperand;
214 def opaque32mem : X86MemOperand<"printopaquemem">;
215 def opaque48mem : X86MemOperand<"printopaquemem">;
216 def opaque80mem : X86MemOperand<"printopaquemem">;
217 def opaque512mem : X86MemOperand<"printopaquemem">;
219 def i8mem : X86MemOperand<"printi8mem">;
220 def i16mem : X86MemOperand<"printi16mem">;
221 def i32mem : X86MemOperand<"printi32mem">;
222 def i64mem : X86MemOperand<"printi64mem">;
223 def i128mem : X86MemOperand<"printi128mem">;
224 //def i256mem : X86MemOperand<"printi256mem">;
225 def f32mem : X86MemOperand<"printf32mem">;
226 def f64mem : X86MemOperand<"printf64mem">;
227 def f80mem : X86MemOperand<"printf80mem">;
228 def f128mem : X86MemOperand<"printf128mem">;
229 //def f256mem : X86MemOperand<"printf256mem">;
231 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
232 // plain GR64, so that it doesn't potentially require a REX prefix.
233 def i8mem_NOREX : Operand<i64> {
234 let PrintMethod = "printi8mem";
235 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
236 let ParserMatchClass = X86MemAsmOperand;
239 // Special i32mem for addresses of load folding tail calls. These are not
240 // allowed to use callee-saved registers since they must be scheduled
241 // after callee-saved register are popped.
242 def i32mem_TC : Operand<i32> {
243 let PrintMethod = "printi32mem";
244 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
245 let ParserMatchClass = X86MemAsmOperand;
248 def lea32mem : Operand<i32> {
249 let PrintMethod = "printlea32mem";
250 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
251 let ParserMatchClass = X86NoSegMemAsmOperand;
254 let ParserMatchClass = X86AbsMemAsmOperand,
255 PrintMethod = "print_pcrel_imm" in {
256 def i32imm_pcrel : Operand<i32>;
258 def offset8 : Operand<i64>;
259 def offset16 : Operand<i64>;
260 def offset32 : Operand<i64>;
261 def offset64 : Operand<i64>;
263 // Branch targets have OtherVT type and print as pc-relative values.
264 def brtarget : Operand<OtherVT>;
265 def brtarget8 : Operand<OtherVT>;
269 def SSECC : Operand<i8> {
270 let PrintMethod = "printSSECC";
273 class ImmSExtAsmOperandClass : AsmOperandClass {
274 let SuperClasses = [ImmAsmOperand];
275 let RenderMethod = "addImmOperands";
278 // Sign-extended immediate classes. We don't need to define the full lattice
279 // here because there is no instruction with an ambiguity between ImmSExti64i32
282 // The strange ranges come from the fact that the assembler always works with
283 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
284 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
286 // [0, 0x7FFFFFFF] | [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
287 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
288 let Name = "ImmSExti64i32";
291 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
292 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
293 let Name = "ImmSExti16i8";
294 let SuperClasses = [ImmSExti64i32AsmOperand];
297 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
298 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
299 let Name = "ImmSExti32i8";
302 // [0, 0x0000007F] | [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
303 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
304 let Name = "ImmSExti64i8";
305 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, ImmSExti64i32AsmOperand];
308 // A couple of more descriptive operand definitions.
309 // 16-bits but only 8 bits are significant.
310 def i16i8imm : Operand<i16> {
311 let ParserMatchClass = ImmSExti16i8AsmOperand;
313 // 32-bits but only 8 bits are significant.
314 def i32i8imm : Operand<i32> {
315 let ParserMatchClass = ImmSExti32i8AsmOperand;
318 //===----------------------------------------------------------------------===//
319 // X86 Complex Pattern Definitions.
322 // Define X86 specific addressing mode.
323 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
324 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
325 [add, sub, mul, X86mul_imm, shl, or, frameindex],
327 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
328 [tglobaltlsaddr], []>;
330 //===----------------------------------------------------------------------===//
331 // X86 Instruction Predicate Definitions.
332 def HasCMov : Predicate<"Subtarget->hasCMov()">;
333 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
334 def HasMMX : Predicate<"Subtarget->hasMMX()">;
335 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
336 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
337 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
338 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
339 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
340 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
341 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
342 def HasAVX : Predicate<"Subtarget->hasAVX()">;
343 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
344 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
345 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
346 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
347 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
348 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
349 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
350 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
351 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
352 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
353 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
354 "TM.getCodeModel() != CodeModel::Kernel">;
355 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
356 "TM.getCodeModel() == CodeModel::Kernel">;
357 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
358 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
359 def OptForSize : Predicate<"OptForSize">;
360 def OptForSpeed : Predicate<"!OptForSize">;
361 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
362 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
363 def HasAES : Predicate<"Subtarget->hasAES()">;
365 //===----------------------------------------------------------------------===//
366 // X86 Instruction Format Definitions.
369 include "X86InstrFormats.td"
371 //===----------------------------------------------------------------------===//
372 // Pattern fragments...
375 // X86 specific condition code. These correspond to CondCode in
376 // X86InstrInfo.h. They must be kept in synch.
377 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
378 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
379 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
380 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
381 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
382 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
383 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
384 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
385 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
386 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
387 def X86_COND_NO : PatLeaf<(i8 10)>;
388 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
389 def X86_COND_NS : PatLeaf<(i8 12)>;
390 def X86_COND_O : PatLeaf<(i8 13)>;
391 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
392 def X86_COND_S : PatLeaf<(i8 15)>;
394 def immSext8 : PatLeaf<(imm), [{
395 return N->getSExtValue() == (int8_t)N->getSExtValue();
398 def i16immSExt8 : PatLeaf<(i16 immSext8)>;
399 def i32immSExt8 : PatLeaf<(i32 immSext8)>;
401 /// Load patterns: these constraint the match to the right address space.
402 def dsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
403 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
404 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
405 if (PT->getAddressSpace() > 255)
410 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
411 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
412 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
413 return PT->getAddressSpace() == 256;
417 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
418 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
419 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
420 return PT->getAddressSpace() == 257;
425 // Helper fragments for loads.
426 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
427 // known to be 32-bit aligned or better. Ditto for i8 to i16.
428 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
429 LoadSDNode *LD = cast<LoadSDNode>(N);
430 if (const Value *Src = LD->getSrcValue())
431 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
432 if (PT->getAddressSpace() > 255)
434 ISD::LoadExtType ExtType = LD->getExtensionType();
435 if (ExtType == ISD::NON_EXTLOAD)
437 if (ExtType == ISD::EXTLOAD)
438 return LD->getAlignment() >= 2 && !LD->isVolatile();
442 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
443 LoadSDNode *LD = cast<LoadSDNode>(N);
444 if (const Value *Src = LD->getSrcValue())
445 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
446 if (PT->getAddressSpace() > 255)
448 ISD::LoadExtType ExtType = LD->getExtensionType();
449 if (ExtType == ISD::EXTLOAD)
450 return LD->getAlignment() >= 2 && !LD->isVolatile();
454 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
455 LoadSDNode *LD = cast<LoadSDNode>(N);
456 if (const Value *Src = LD->getSrcValue())
457 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
458 if (PT->getAddressSpace() > 255)
460 ISD::LoadExtType ExtType = LD->getExtensionType();
461 if (ExtType == ISD::NON_EXTLOAD)
463 if (ExtType == ISD::EXTLOAD)
464 return LD->getAlignment() >= 4 && !LD->isVolatile();
468 def loadi8 : PatFrag<(ops node:$ptr), (i8 (dsload node:$ptr))>;
469 def loadi64 : PatFrag<(ops node:$ptr), (i64 (dsload node:$ptr))>;
470 def loadf32 : PatFrag<(ops node:$ptr), (f32 (dsload node:$ptr))>;
471 def loadf64 : PatFrag<(ops node:$ptr), (f64 (dsload node:$ptr))>;
472 def loadf80 : PatFrag<(ops node:$ptr), (f80 (dsload node:$ptr))>;
474 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
475 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
476 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
478 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
479 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
480 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
481 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
482 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
483 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
485 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
486 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
487 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
488 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
489 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
490 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
493 // An 'and' node with a single use.
494 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
495 return N->hasOneUse();
497 // An 'srl' node with a single use.
498 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
499 return N->hasOneUse();
501 // An 'trunc' node with a single use.
502 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
503 return N->hasOneUse();
506 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
507 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
508 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
509 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
511 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
512 APInt Mask = APInt::getAllOnesValue(BitWidth);
513 APInt KnownZero0, KnownOne0;
514 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
515 APInt KnownZero1, KnownOne1;
516 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
517 return (~KnownZero0 & ~KnownZero1) == 0;
520 //===----------------------------------------------------------------------===//
521 // Instruction list...
524 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
525 // a stack adjustment and the codegen must know that they may modify the stack
526 // pointer before prolog-epilog rewriting occurs.
527 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
528 // sub / add which can clobber EFLAGS.
529 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
530 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
532 [(X86callseq_start timm:$amt)]>,
533 Requires<[In32BitMode]>;
534 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
536 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
537 Requires<[In32BitMode]>;
540 // x86-64 va_start lowering magic.
541 let usesCustomInserter = 1 in {
542 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
545 i64imm:$regsavefi, i64imm:$offset,
547 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
548 [(X86vastart_save_xmm_regs GR8:$al,
552 // Dynamic stack allocation yields _alloca call for Cygwin/Mingw targets. Calls
553 // to _alloca is needed to probe the stack when allocating more than 4k bytes in
554 // one go. Touching the stack at 4K increments is necessary to ensure that the
555 // guard pages used by the OS virtual memory manager are allocated in correct
557 // The main point of having separate instruction are extra unmodelled effects
558 // (compared to ordinary calls) like stack pointer change.
560 def MINGW_ALLOCA : I<0, Pseudo, (outs), (ins),
561 "# dynamic stack allocation",
566 let neverHasSideEffects = 1 in {
567 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
568 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
569 "nop{w}\t$zero", []>, TB, OpSize;
570 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
571 "nop{l}\t$zero", []>, TB;
575 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
576 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", []>;
577 // FIXME: need to make sure that "int $3" matches int3
578 def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
579 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize;
580 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>;
582 // PIC base construction. This expands to code that looks like this:
585 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
586 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
589 //===----------------------------------------------------------------------===//
590 // Control Flow Instructions.
593 // Return instructions.
594 let isTerminator = 1, isReturn = 1, isBarrier = 1,
595 hasCtrlDep = 1, FPForm = SpecialFP in {
596 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
599 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
601 [(X86retflag timm:$amt)]>;
602 def LRET : I <0xCB, RawFrm, (outs), (ins),
604 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
608 // Unconditional branches.
609 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
610 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
611 "jmp\t$dst", [(br bb:$dst)]>;
612 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
616 // Conditional Branches.
617 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
618 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
619 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
620 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
621 [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
625 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
626 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
627 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
628 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
629 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
630 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
631 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
632 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
633 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
634 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
635 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
636 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
637 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
638 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
639 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
640 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
642 // FIXME: What about the CX/RCX versions of this instruction?
643 let Uses = [ECX], isBranch = 1, isTerminator = 1 in
644 def JCXZ8 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
649 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
650 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
651 [(brind GR32:$dst)]>;
652 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
653 [(brind (loadi32 addr:$dst))]>;
655 def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
656 (ins i16imm:$seg, i16imm:$off),
657 "ljmp{w}\t$seg, $off", []>, OpSize;
658 def FARJMP32i : Iseg32<0xEA, RawFrm, (outs),
659 (ins i16imm:$seg, i32imm:$off),
660 "ljmp{l}\t$seg, $off", []>;
662 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
663 "ljmp{w}\t{*}$dst", []>, OpSize;
664 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
665 "ljmp{l}\t{*}$dst", []>;
671 def LOOP : I<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>;
672 def LOOPE : I<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>;
673 def LOOPNE : I<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>;
675 //===----------------------------------------------------------------------===//
676 // Call Instructions...
679 // All calls clobber the non-callee saved registers. ESP is marked as
680 // a use to prevent stack-pointer assignments that appear immediately
681 // before calls from potentially appearing dead. Uses for argument
682 // registers are added manually.
683 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
684 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
685 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
686 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
688 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
689 (outs), (ins i32imm_pcrel:$dst,variable_ops),
691 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
692 "call\t{*}$dst", [(X86call GR32:$dst)]>;
693 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
694 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
696 def FARCALL16i : Iseg16<0x9A, RawFrm, (outs),
697 (ins i16imm:$seg, i16imm:$off),
698 "lcall{w}\t$seg, $off", []>, OpSize;
699 def FARCALL32i : Iseg32<0x9A, RawFrm, (outs),
700 (ins i16imm:$seg, i32imm:$off),
701 "lcall{l}\t$seg, $off", []>;
703 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
704 "lcall{w}\t{*}$dst", []>, OpSize;
705 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
706 "lcall{l}\t{*}$dst", []>;
709 // Constructing a stack frame.
711 def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl),
712 "enter\t$len, $lvl", []>;
716 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
717 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
718 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
719 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
720 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
722 def TCRETURNdi : I<0, Pseudo, (outs),
723 (ins i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
724 "#TC_RETURN $dst $offset", []>;
725 def TCRETURNri : I<0, Pseudo, (outs),
726 (ins GR32_TC:$dst, i32imm:$offset, variable_ops),
727 "#TC_RETURN $dst $offset", []>;
729 def TCRETURNmi : I<0, Pseudo, (outs),
730 (ins i32mem_TC:$dst, i32imm:$offset, variable_ops),
731 "#TC_RETURN $dst $offset", []>;
733 // FIXME: The should be pseudo instructions that are lowered when going to
735 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
736 (ins i32imm_pcrel:$dst, variable_ops),
737 "jmp\t$dst # TAILCALL",
739 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops),
740 "jmp{l}\t{*}$dst # TAILCALL",
743 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops),
744 "jmp{l}\t{*}$dst # TAILCALL", []>;
746 // FIXME: This is a hack so that MCInst lowering can preserve the TAILCALL
747 // marker on instructions, while still being able to relax.
748 let isCodeGenOnly = 1 in {
749 def TAILJMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
750 "jmp\t$dst # TAILCALL", []>;
754 //===----------------------------------------------------------------------===//
755 // Miscellaneous Instructions...
757 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
758 def LEAVE : I<0xC9, RawFrm,
759 (outs), (ins), "leave", []>;
761 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
762 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
764 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
765 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
766 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
767 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
769 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
770 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
772 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
774 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
776 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
777 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
779 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
781 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
782 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
785 let mayStore = 1 in {
786 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
788 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
789 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
791 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
793 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
794 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
798 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
799 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
800 "push{l}\t$imm", []>;
801 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
802 "push{w}\t$imm", []>, OpSize;
803 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
804 "push{l}\t$imm", []>;
807 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
808 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
809 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
810 Requires<[In32BitMode]>;
812 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
813 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
814 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
815 Requires<[In32BitMode]>;
818 let isTwoAddress = 1 in // GR32 = bswap GR32
819 def BSWAP32r : I<0xC8, AddRegFrm,
820 (outs GR32:$dst), (ins GR32:$src),
822 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
825 // Bit scan instructions.
826 let Defs = [EFLAGS] in {
827 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
828 "bsf{w}\t{$src, $dst|$dst, $src}",
829 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
830 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
831 "bsf{w}\t{$src, $dst|$dst, $src}",
832 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
834 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
835 "bsf{l}\t{$src, $dst|$dst, $src}",
836 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
837 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
838 "bsf{l}\t{$src, $dst|$dst, $src}",
839 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
841 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
842 "bsr{w}\t{$src, $dst|$dst, $src}",
843 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
844 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
845 "bsr{w}\t{$src, $dst|$dst, $src}",
846 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
848 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
849 "bsr{l}\t{$src, $dst|$dst, $src}",
850 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
851 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
852 "bsr{l}\t{$src, $dst|$dst, $src}",
853 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
856 let neverHasSideEffects = 1 in
857 def LEA16r : I<0x8D, MRMSrcMem,
858 (outs GR16:$dst), (ins lea32mem:$src),
859 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
860 let isReMaterializable = 1 in
861 def LEA32r : I<0x8D, MRMSrcMem,
862 (outs GR32:$dst), (ins lea32mem:$src),
863 "lea{l}\t{$src|$dst}, {$dst|$src}",
864 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
866 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
867 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
868 [(X86rep_movs i8)]>, REP;
869 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
870 [(X86rep_movs i16)]>, REP, OpSize;
871 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
872 [(X86rep_movs i32)]>, REP;
875 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
876 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
877 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
878 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
879 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
882 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
883 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
884 [(X86rep_stos i8)]>, REP;
885 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
886 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
887 [(X86rep_stos i16)]>, REP, OpSize;
888 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
889 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
890 [(X86rep_stos i32)]>, REP;
892 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
893 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
894 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
895 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
896 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
897 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
898 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
900 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
901 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
902 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
904 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
905 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
906 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
908 let Defs = [RAX, RDX] in
909 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
912 let Defs = [RAX, RCX, RDX] in
913 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
915 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
916 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
919 def SYSCALL : I<0x05, RawFrm,
920 (outs), (ins), "syscall", []>, TB;
921 def SYSRET : I<0x07, RawFrm,
922 (outs), (ins), "sysret", []>, TB;
923 def SYSENTER : I<0x34, RawFrm,
924 (outs), (ins), "sysenter", []>, TB;
925 def SYSEXIT : I<0x35, RawFrm,
926 (outs), (ins), "sysexit", []>, TB;
928 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
931 //===----------------------------------------------------------------------===//
932 // Input/Output Instructions...
934 let Defs = [AL], Uses = [DX] in
935 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
936 "in{b}\t{%dx, %al|%AL, %DX}", []>;
937 let Defs = [AX], Uses = [DX] in
938 def IN16rr : I<0xED, RawFrm, (outs), (ins),
939 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
940 let Defs = [EAX], Uses = [DX] in
941 def IN32rr : I<0xED, RawFrm, (outs), (ins),
942 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
945 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
946 "in{b}\t{$port, %al|%AL, $port}", []>;
948 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
949 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
951 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
952 "in{l}\t{$port, %eax|%EAX, $port}", []>;
954 let Uses = [DX, AL] in
955 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
956 "out{b}\t{%al, %dx|%DX, %AL}", []>;
957 let Uses = [DX, AX] in
958 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
959 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
960 let Uses = [DX, EAX] in
961 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
962 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
965 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
966 "out{b}\t{%al, $port|$port, %AL}", []>;
968 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
969 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
971 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
972 "out{l}\t{%eax, $port|$port, %EAX}", []>;
974 def IN8 : I<0x6C, RawFrm, (outs), (ins),
976 def IN16 : I<0x6D, RawFrm, (outs), (ins),
977 "ins{w}", []>, OpSize;
978 def IN32 : I<0x6D, RawFrm, (outs), (ins),
981 //===----------------------------------------------------------------------===//
982 // Move Instructions...
984 let neverHasSideEffects = 1 in {
985 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
986 "mov{b}\t{$src, $dst|$dst, $src}", []>;
987 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
988 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
989 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
990 "mov{l}\t{$src, $dst|$dst, $src}", []>;
992 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
993 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
994 "mov{b}\t{$src, $dst|$dst, $src}",
995 [(set GR8:$dst, imm:$src)]>;
996 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
997 "mov{w}\t{$src, $dst|$dst, $src}",
998 [(set GR16:$dst, imm:$src)]>, OpSize;
999 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1000 "mov{l}\t{$src, $dst|$dst, $src}",
1001 [(set GR32:$dst, imm:$src)]>;
1004 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1005 "mov{b}\t{$src, $dst|$dst, $src}",
1006 [(store (i8 imm:$src), addr:$dst)]>;
1007 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1008 "mov{w}\t{$src, $dst|$dst, $src}",
1009 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
1010 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1011 "mov{l}\t{$src, $dst|$dst, $src}",
1012 [(store (i32 imm:$src), addr:$dst)]>;
1014 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
1015 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
1016 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
1017 "mov{b}\t{$src, %al|%al, $src}", []>;
1018 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
1019 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1020 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1021 "mov{l}\t{$src, %eax|%eax, $src}", []>;
1022 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1023 "mov{b}\t{%al, $dst|$dst, %al}", []>;
1024 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1025 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize;
1026 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1027 "mov{l}\t{%eax, $dst|$dst, %eax}", []>;
1029 // Moves to and from segment registers
1030 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
1031 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1032 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
1033 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1034 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
1035 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1036 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
1037 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1039 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1040 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1041 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1042 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1043 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1044 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1046 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1047 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1048 "mov{b}\t{$src, $dst|$dst, $src}",
1049 [(set GR8:$dst, (loadi8 addr:$src))]>;
1050 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1051 "mov{w}\t{$src, $dst|$dst, $src}",
1052 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
1053 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1054 "mov{l}\t{$src, $dst|$dst, $src}",
1055 [(set GR32:$dst, (loadi32 addr:$src))]>;
1058 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1059 "mov{b}\t{$src, $dst|$dst, $src}",
1060 [(store GR8:$src, addr:$dst)]>;
1061 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1062 "mov{w}\t{$src, $dst|$dst, $src}",
1063 [(store GR16:$src, addr:$dst)]>, OpSize;
1064 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1065 "mov{l}\t{$src, $dst|$dst, $src}",
1066 [(store GR32:$src, addr:$dst)]>;
1068 /// Versions of MOV32rr, MOV32rm, and MOV32mr for i32mem_TC and GR32_TC.
1069 let neverHasSideEffects = 1 in
1070 def MOV32rr_TC : I<0x89, MRMDestReg, (outs GR32_TC:$dst), (ins GR32_TC:$src),
1071 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1074 canFoldAsLoad = 1, isReMaterializable = 1 in
1075 def MOV32rm_TC : I<0x8B, MRMSrcMem, (outs GR32_TC:$dst), (ins i32mem_TC:$src),
1076 "mov{l}\t{$src, $dst|$dst, $src}",
1080 def MOV32mr_TC : I<0x89, MRMDestMem, (outs), (ins i32mem_TC:$dst, GR32_TC:$src),
1081 "mov{l}\t{$src, $dst|$dst, $src}",
1084 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1085 // that they can be used for copying and storing h registers, which can't be
1086 // encoded when a REX prefix is present.
1087 let neverHasSideEffects = 1 in
1088 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1089 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1090 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1092 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1093 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1094 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1096 canFoldAsLoad = 1, isReMaterializable = 1 in
1097 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1098 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1099 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1101 // Moves to and from debug registers
1102 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
1103 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1104 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
1105 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1107 // Moves to and from control registers
1108 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
1109 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1110 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
1111 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1113 //===----------------------------------------------------------------------===//
1114 // Fixed-Register Multiplication and Division Instructions...
1117 // Extra precision multiplication
1119 // AL is really implied by AX, by the registers in Defs must match the
1120 // SDNode results (i8, i32).
1121 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1122 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
1123 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1124 // This probably ought to be moved to a def : Pat<> if the
1125 // syntax can be accepted.
1126 [(set AL, (mul AL, GR8:$src)),
1127 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1129 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1130 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1132 []>, OpSize; // AX,DX = AX*GR16
1134 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1135 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1137 []>; // EAX,EDX = EAX*GR32
1139 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1140 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1142 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1143 // This probably ought to be moved to a def : Pat<> if the
1144 // syntax can be accepted.
1145 [(set AL, (mul AL, (loadi8 addr:$src))),
1146 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1148 let mayLoad = 1, neverHasSideEffects = 1 in {
1149 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1150 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1152 []>, OpSize; // AX,DX = AX*[mem16]
1154 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1155 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1157 []>; // EAX,EDX = EAX*[mem32]
1160 let neverHasSideEffects = 1 in {
1161 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1162 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1164 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1165 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1166 OpSize; // AX,DX = AX*GR16
1167 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1168 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1169 // EAX,EDX = EAX*GR32
1170 let mayLoad = 1 in {
1171 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1172 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1173 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1174 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1175 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1176 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1177 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1178 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1179 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1181 } // neverHasSideEffects
1183 // unsigned division/remainder
1184 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1185 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1186 "div{b}\t$src", []>;
1187 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1188 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1189 "div{w}\t$src", []>, OpSize;
1190 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1191 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1192 "div{l}\t$src", []>;
1193 let mayLoad = 1 in {
1194 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1195 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1196 "div{b}\t$src", []>;
1197 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1198 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1199 "div{w}\t$src", []>, OpSize;
1200 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1201 // EDX:EAX/[mem32] = EAX,EDX
1202 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
1203 "div{l}\t$src", []>;
1206 // Signed division/remainder.
1207 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1208 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1209 "idiv{b}\t$src", []>;
1210 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1211 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1212 "idiv{w}\t$src", []>, OpSize;
1213 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1214 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1215 "idiv{l}\t$src", []>;
1216 let mayLoad = 1, mayLoad = 1 in {
1217 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1218 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1219 "idiv{b}\t$src", []>;
1220 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1221 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1222 "idiv{w}\t$src", []>, OpSize;
1223 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1224 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1225 // EDX:EAX/[mem32] = EAX,EDX
1226 "idiv{l}\t$src", []>;
1229 //===----------------------------------------------------------------------===//
1230 // Two address Instructions.
1232 let isTwoAddress = 1 in {
1234 // Conditional moves
1235 let Uses = [EFLAGS] in {
1237 let Predicates = [HasCMov] in {
1238 let isCommutable = 1 in {
1239 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1240 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1241 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1242 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1243 X86_COND_B, EFLAGS))]>,
1245 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1246 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1247 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1248 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1249 X86_COND_B, EFLAGS))]>,
1251 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1252 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1253 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1254 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1255 X86_COND_AE, EFLAGS))]>,
1257 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1258 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1259 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1260 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1261 X86_COND_AE, EFLAGS))]>,
1263 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1264 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1265 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1266 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1267 X86_COND_E, EFLAGS))]>,
1269 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1270 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1271 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1272 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1273 X86_COND_E, EFLAGS))]>,
1275 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1276 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1277 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1278 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1279 X86_COND_NE, EFLAGS))]>,
1281 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1282 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1283 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1284 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1285 X86_COND_NE, EFLAGS))]>,
1287 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1288 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1289 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1290 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1291 X86_COND_BE, EFLAGS))]>,
1293 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1294 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1295 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1296 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1297 X86_COND_BE, EFLAGS))]>,
1299 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1300 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1301 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1302 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1303 X86_COND_A, EFLAGS))]>,
1305 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1306 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1307 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1308 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1309 X86_COND_A, EFLAGS))]>,
1311 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1312 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1313 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1314 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1315 X86_COND_L, EFLAGS))]>,
1317 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1318 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1319 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1320 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1321 X86_COND_L, EFLAGS))]>,
1323 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1324 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1325 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1326 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1327 X86_COND_GE, EFLAGS))]>,
1329 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1330 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1331 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1332 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1333 X86_COND_GE, EFLAGS))]>,
1335 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1336 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1337 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1338 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1339 X86_COND_LE, EFLAGS))]>,
1341 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1342 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1343 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1344 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1345 X86_COND_LE, EFLAGS))]>,
1347 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1348 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1349 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1350 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1351 X86_COND_G, EFLAGS))]>,
1353 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1354 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1355 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1356 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1357 X86_COND_G, EFLAGS))]>,
1359 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1360 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1361 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1362 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1363 X86_COND_S, EFLAGS))]>,
1365 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1366 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1367 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1368 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1369 X86_COND_S, EFLAGS))]>,
1371 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1372 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1373 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1374 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1375 X86_COND_NS, EFLAGS))]>,
1377 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1378 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1379 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1380 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1381 X86_COND_NS, EFLAGS))]>,
1383 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1384 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1385 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1386 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1387 X86_COND_P, EFLAGS))]>,
1389 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1390 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1391 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1392 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1393 X86_COND_P, EFLAGS))]>,
1395 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1396 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1397 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1398 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1399 X86_COND_NP, EFLAGS))]>,
1401 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1402 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1403 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1404 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1405 X86_COND_NP, EFLAGS))]>,
1407 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1408 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1409 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1410 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1411 X86_COND_O, EFLAGS))]>,
1413 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1414 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1415 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1416 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1417 X86_COND_O, EFLAGS))]>,
1419 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1420 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1421 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1422 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1423 X86_COND_NO, EFLAGS))]>,
1425 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1426 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1427 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1428 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1429 X86_COND_NO, EFLAGS))]>,
1431 } // isCommutable = 1
1433 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1434 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1435 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1436 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1437 X86_COND_B, EFLAGS))]>,
1439 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1440 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1441 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1442 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1443 X86_COND_B, EFLAGS))]>,
1445 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1446 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1447 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1448 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1449 X86_COND_AE, EFLAGS))]>,
1451 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1452 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1453 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1454 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1455 X86_COND_AE, EFLAGS))]>,
1457 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1458 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1459 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1460 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1461 X86_COND_E, EFLAGS))]>,
1463 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1464 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1465 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1466 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1467 X86_COND_E, EFLAGS))]>,
1469 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1470 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1471 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1472 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1473 X86_COND_NE, EFLAGS))]>,
1475 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1476 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1477 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1478 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1479 X86_COND_NE, EFLAGS))]>,
1481 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1482 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1483 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1484 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1485 X86_COND_BE, EFLAGS))]>,
1487 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1488 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1489 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1490 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1491 X86_COND_BE, EFLAGS))]>,
1493 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1494 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1495 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1496 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1497 X86_COND_A, EFLAGS))]>,
1499 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1500 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1501 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1502 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1503 X86_COND_A, EFLAGS))]>,
1505 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1506 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1507 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1508 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1509 X86_COND_L, EFLAGS))]>,
1511 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1512 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1513 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1514 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1515 X86_COND_L, EFLAGS))]>,
1517 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1518 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1519 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1520 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1521 X86_COND_GE, EFLAGS))]>,
1523 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1524 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1525 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1526 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1527 X86_COND_GE, EFLAGS))]>,
1529 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1530 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1531 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1532 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1533 X86_COND_LE, EFLAGS))]>,
1535 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1536 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1537 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1538 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1539 X86_COND_LE, EFLAGS))]>,
1541 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1542 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1543 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1544 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1545 X86_COND_G, EFLAGS))]>,
1547 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1548 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1549 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1550 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1551 X86_COND_G, EFLAGS))]>,
1553 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1554 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1555 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1556 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1557 X86_COND_S, EFLAGS))]>,
1559 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1560 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1561 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1562 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1563 X86_COND_S, EFLAGS))]>,
1565 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1566 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1567 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1568 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1569 X86_COND_NS, EFLAGS))]>,
1571 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1572 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1573 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1574 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1575 X86_COND_NS, EFLAGS))]>,
1577 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1578 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1579 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1580 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1581 X86_COND_P, EFLAGS))]>,
1583 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1584 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1585 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1586 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1587 X86_COND_P, EFLAGS))]>,
1589 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1590 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1591 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1592 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1593 X86_COND_NP, EFLAGS))]>,
1595 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1596 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1597 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1598 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1599 X86_COND_NP, EFLAGS))]>,
1601 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1602 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1603 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1604 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1605 X86_COND_O, EFLAGS))]>,
1607 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1608 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1609 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1610 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1611 X86_COND_O, EFLAGS))]>,
1613 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1614 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1615 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1616 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1617 X86_COND_NO, EFLAGS))]>,
1619 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1620 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1621 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1622 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1623 X86_COND_NO, EFLAGS))]>,
1625 } // Predicates = [HasCMov]
1627 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1628 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1629 // however that requires promoting the operands, and can induce additional
1630 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1631 // clobber EFLAGS, because if one of the operands is zero, the expansion
1632 // could involve an xor.
1633 let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in {
1634 def CMOV_GR8 : I<0, Pseudo,
1635 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1636 "#CMOV_GR8 PSEUDO!",
1637 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1638 imm:$cond, EFLAGS))]>;
1640 let Predicates = [NoCMov] in {
1641 def CMOV_GR32 : I<0, Pseudo,
1642 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
1643 "#CMOV_GR32* PSEUDO!",
1645 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
1646 def CMOV_GR16 : I<0, Pseudo,
1647 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
1648 "#CMOV_GR16* PSEUDO!",
1650 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
1651 def CMOV_RFP32 : I<0, Pseudo,
1652 (outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
1653 "#CMOV_RFP32 PSEUDO!",
1654 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
1656 def CMOV_RFP64 : I<0, Pseudo,
1657 (outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
1658 "#CMOV_RFP64 PSEUDO!",
1659 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
1661 def CMOV_RFP80 : I<0, Pseudo,
1662 (outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
1663 "#CMOV_RFP80 PSEUDO!",
1664 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
1666 } // Predicates = [NoCMov]
1667 } // UsesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS]
1668 } // Uses = [EFLAGS]
1671 // unary instructions
1672 let CodeSize = 2 in {
1673 let Defs = [EFLAGS] in {
1674 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1675 [(set GR8:$dst, (ineg GR8:$src)),
1676 (implicit EFLAGS)]>;
1677 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1678 [(set GR16:$dst, (ineg GR16:$src)),
1679 (implicit EFLAGS)]>, OpSize;
1680 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1681 [(set GR32:$dst, (ineg GR32:$src)),
1682 (implicit EFLAGS)]>;
1683 let isTwoAddress = 0 in {
1684 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1685 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1686 (implicit EFLAGS)]>;
1687 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1688 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1689 (implicit EFLAGS)]>, OpSize;
1690 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1691 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1692 (implicit EFLAGS)]>;
1694 } // Defs = [EFLAGS]
1696 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1697 let AddedComplexity = 15 in {
1698 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1699 [(set GR8:$dst, (not GR8:$src))]>;
1700 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1701 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1702 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1703 [(set GR32:$dst, (not GR32:$src))]>;
1705 let isTwoAddress = 0 in {
1706 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1707 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1708 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1709 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1710 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1711 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1715 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1716 let Defs = [EFLAGS] in {
1718 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1719 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src))]>;
1721 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1722 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1724 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src))]>,
1725 OpSize, Requires<[In32BitMode]>;
1726 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1728 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src))]>,
1729 Requires<[In32BitMode]>;
1731 let isTwoAddress = 0, CodeSize = 2 in {
1732 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1733 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1734 (implicit EFLAGS)]>;
1735 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1736 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1737 (implicit EFLAGS)]>,
1738 OpSize, Requires<[In32BitMode]>;
1739 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1740 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1741 (implicit EFLAGS)]>,
1742 Requires<[In32BitMode]>;
1746 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1747 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src))]>;
1748 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1749 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1751 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src))]>,
1752 OpSize, Requires<[In32BitMode]>;
1753 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1755 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src))]>,
1756 Requires<[In32BitMode]>;
1759 let isTwoAddress = 0, CodeSize = 2 in {
1760 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1761 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1762 (implicit EFLAGS)]>;
1763 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1764 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1765 (implicit EFLAGS)]>,
1766 OpSize, Requires<[In32BitMode]>;
1767 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1768 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1769 (implicit EFLAGS)]>,
1770 Requires<[In32BitMode]>;
1772 } // Defs = [EFLAGS]
1774 // Logical operators...
1775 let Defs = [EFLAGS] in {
1776 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1777 def AND8rr : I<0x20, MRMDestReg,
1778 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1779 "and{b}\t{$src2, $dst|$dst, $src2}",
1780 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, GR8:$src2))]>;
1781 def AND16rr : I<0x21, MRMDestReg,
1782 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1783 "and{w}\t{$src2, $dst|$dst, $src2}",
1784 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1785 GR16:$src2))]>, OpSize;
1786 def AND32rr : I<0x21, MRMDestReg,
1787 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1788 "and{l}\t{$src2, $dst|$dst, $src2}",
1789 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1793 // AND instructions with the destination register in REG and the source register
1794 // in R/M. Included for the disassembler.
1795 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1796 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1797 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1798 (ins GR16:$src1, GR16:$src2),
1799 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1800 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1801 (ins GR32:$src1, GR32:$src2),
1802 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1804 def AND8rm : I<0x22, MRMSrcMem,
1805 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1806 "and{b}\t{$src2, $dst|$dst, $src2}",
1807 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1808 (loadi8 addr:$src2)))]>;
1809 def AND16rm : I<0x23, MRMSrcMem,
1810 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1811 "and{w}\t{$src2, $dst|$dst, $src2}",
1812 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1813 (loadi16 addr:$src2)))]>,
1815 def AND32rm : I<0x23, MRMSrcMem,
1816 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1817 "and{l}\t{$src2, $dst|$dst, $src2}",
1818 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1819 (loadi32 addr:$src2)))]>;
1821 def AND8ri : Ii8<0x80, MRM4r,
1822 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1823 "and{b}\t{$src2, $dst|$dst, $src2}",
1824 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1826 def AND16ri : Ii16<0x81, MRM4r,
1827 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1828 "and{w}\t{$src2, $dst|$dst, $src2}",
1829 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1830 imm:$src2))]>, OpSize;
1831 def AND32ri : Ii32<0x81, MRM4r,
1832 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1833 "and{l}\t{$src2, $dst|$dst, $src2}",
1834 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1836 def AND16ri8 : Ii8<0x83, MRM4r,
1837 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1838 "and{w}\t{$src2, $dst|$dst, $src2}",
1839 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1840 i16immSExt8:$src2))]>,
1842 def AND32ri8 : Ii8<0x83, MRM4r,
1843 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1844 "and{l}\t{$src2, $dst|$dst, $src2}",
1845 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1846 i32immSExt8:$src2))]>;
1848 let isTwoAddress = 0 in {
1849 def AND8mr : I<0x20, MRMDestMem,
1850 (outs), (ins i8mem :$dst, GR8 :$src),
1851 "and{b}\t{$src, $dst|$dst, $src}",
1852 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1853 (implicit EFLAGS)]>;
1854 def AND16mr : I<0x21, MRMDestMem,
1855 (outs), (ins i16mem:$dst, GR16:$src),
1856 "and{w}\t{$src, $dst|$dst, $src}",
1857 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1858 (implicit EFLAGS)]>,
1860 def AND32mr : I<0x21, MRMDestMem,
1861 (outs), (ins i32mem:$dst, GR32:$src),
1862 "and{l}\t{$src, $dst|$dst, $src}",
1863 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1864 (implicit EFLAGS)]>;
1865 def AND8mi : Ii8<0x80, MRM4m,
1866 (outs), (ins i8mem :$dst, i8imm :$src),
1867 "and{b}\t{$src, $dst|$dst, $src}",
1868 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1869 (implicit EFLAGS)]>;
1870 def AND16mi : Ii16<0x81, MRM4m,
1871 (outs), (ins i16mem:$dst, i16imm:$src),
1872 "and{w}\t{$src, $dst|$dst, $src}",
1873 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1874 (implicit EFLAGS)]>,
1876 def AND32mi : Ii32<0x81, MRM4m,
1877 (outs), (ins i32mem:$dst, i32imm:$src),
1878 "and{l}\t{$src, $dst|$dst, $src}",
1879 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1880 (implicit EFLAGS)]>;
1881 def AND16mi8 : Ii8<0x83, MRM4m,
1882 (outs), (ins i16mem:$dst, i16i8imm :$src),
1883 "and{w}\t{$src, $dst|$dst, $src}",
1884 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1885 (implicit EFLAGS)]>,
1887 def AND32mi8 : Ii8<0x83, MRM4m,
1888 (outs), (ins i32mem:$dst, i32i8imm :$src),
1889 "and{l}\t{$src, $dst|$dst, $src}",
1890 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1891 (implicit EFLAGS)]>;
1893 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1894 "and{b}\t{$src, %al|%al, $src}", []>;
1895 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1896 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1897 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1898 "and{l}\t{$src, %eax|%eax, $src}", []>;
1903 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1904 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1905 (ins GR8 :$src1, GR8 :$src2),
1906 "or{b}\t{$src2, $dst|$dst, $src2}",
1907 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
1908 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1909 (ins GR16:$src1, GR16:$src2),
1910 "or{w}\t{$src2, $dst|$dst, $src2}",
1911 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
1913 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1914 (ins GR32:$src1, GR32:$src2),
1915 "or{l}\t{$src2, $dst|$dst, $src2}",
1916 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
1919 // OR instructions with the destination register in REG and the source register
1920 // in R/M. Included for the disassembler.
1921 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1922 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1923 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1924 (ins GR16:$src1, GR16:$src2),
1925 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1926 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1927 (ins GR32:$src1, GR32:$src2),
1928 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
1930 def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst),
1931 (ins GR8 :$src1, i8mem :$src2),
1932 "or{b}\t{$src2, $dst|$dst, $src2}",
1933 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
1934 (load addr:$src2)))]>;
1935 def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst),
1936 (ins GR16:$src1, i16mem:$src2),
1937 "or{w}\t{$src2, $dst|$dst, $src2}",
1938 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1939 (load addr:$src2)))]>,
1941 def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst),
1942 (ins GR32:$src1, i32mem:$src2),
1943 "or{l}\t{$src2, $dst|$dst, $src2}",
1944 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1945 (load addr:$src2)))]>;
1947 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
1948 (ins GR8 :$src1, i8imm:$src2),
1949 "or{b}\t{$src2, $dst|$dst, $src2}",
1950 [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
1951 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
1952 (ins GR16:$src1, i16imm:$src2),
1953 "or{w}\t{$src2, $dst|$dst, $src2}",
1954 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1955 imm:$src2))]>, OpSize;
1956 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
1957 (ins GR32:$src1, i32imm:$src2),
1958 "or{l}\t{$src2, $dst|$dst, $src2}",
1959 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1962 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
1963 (ins GR16:$src1, i16i8imm:$src2),
1964 "or{w}\t{$src2, $dst|$dst, $src2}",
1965 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1966 i16immSExt8:$src2))]>, OpSize;
1967 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
1968 (ins GR32:$src1, i32i8imm:$src2),
1969 "or{l}\t{$src2, $dst|$dst, $src2}",
1970 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1971 i32immSExt8:$src2))]>;
1972 let isTwoAddress = 0 in {
1973 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1974 "or{b}\t{$src, $dst|$dst, $src}",
1975 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1976 (implicit EFLAGS)]>;
1977 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1978 "or{w}\t{$src, $dst|$dst, $src}",
1979 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1980 (implicit EFLAGS)]>, OpSize;
1981 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1982 "or{l}\t{$src, $dst|$dst, $src}",
1983 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1984 (implicit EFLAGS)]>;
1985 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1986 "or{b}\t{$src, $dst|$dst, $src}",
1987 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1988 (implicit EFLAGS)]>;
1989 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1990 "or{w}\t{$src, $dst|$dst, $src}",
1991 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1992 (implicit EFLAGS)]>,
1994 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1995 "or{l}\t{$src, $dst|$dst, $src}",
1996 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1997 (implicit EFLAGS)]>;
1998 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1999 "or{w}\t{$src, $dst|$dst, $src}",
2000 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
2001 (implicit EFLAGS)]>,
2003 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
2004 "or{l}\t{$src, $dst|$dst, $src}",
2005 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
2006 (implicit EFLAGS)]>;
2008 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
2009 "or{b}\t{$src, %al|%al, $src}", []>;
2010 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
2011 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2012 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
2013 "or{l}\t{$src, %eax|%eax, $src}", []>;
2014 } // isTwoAddress = 0
2017 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
2018 def XOR8rr : I<0x30, MRMDestReg,
2019 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
2020 "xor{b}\t{$src2, $dst|$dst, $src2}",
2021 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2023 def XOR16rr : I<0x31, MRMDestReg,
2024 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2025 "xor{w}\t{$src2, $dst|$dst, $src2}",
2026 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2027 GR16:$src2))]>, OpSize;
2028 def XOR32rr : I<0x31, MRMDestReg,
2029 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2030 "xor{l}\t{$src2, $dst|$dst, $src2}",
2031 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2033 } // isCommutable = 1
2035 // XOR instructions with the destination register in REG and the source register
2036 // in R/M. Included for the disassembler.
2037 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2038 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
2039 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
2040 (ins GR16:$src1, GR16:$src2),
2041 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2042 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
2043 (ins GR32:$src1, GR32:$src2),
2044 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
2046 def XOR8rm : I<0x32, MRMSrcMem,
2047 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
2048 "xor{b}\t{$src2, $dst|$dst, $src2}",
2049 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2050 (load addr:$src2)))]>;
2051 def XOR16rm : I<0x33, MRMSrcMem,
2052 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2053 "xor{w}\t{$src2, $dst|$dst, $src2}",
2054 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2055 (load addr:$src2)))]>,
2057 def XOR32rm : I<0x33, MRMSrcMem,
2058 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2059 "xor{l}\t{$src2, $dst|$dst, $src2}",
2060 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2061 (load addr:$src2)))]>;
2063 def XOR8ri : Ii8<0x80, MRM6r,
2064 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2065 "xor{b}\t{$src2, $dst|$dst, $src2}",
2066 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
2067 def XOR16ri : Ii16<0x81, MRM6r,
2068 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2069 "xor{w}\t{$src2, $dst|$dst, $src2}",
2070 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2071 imm:$src2))]>, OpSize;
2072 def XOR32ri : Ii32<0x81, MRM6r,
2073 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2074 "xor{l}\t{$src2, $dst|$dst, $src2}",
2075 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2077 def XOR16ri8 : Ii8<0x83, MRM6r,
2078 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2079 "xor{w}\t{$src2, $dst|$dst, $src2}",
2080 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2081 i16immSExt8:$src2))]>,
2083 def XOR32ri8 : Ii8<0x83, MRM6r,
2084 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2085 "xor{l}\t{$src2, $dst|$dst, $src2}",
2086 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2087 i32immSExt8:$src2))]>;
2089 let isTwoAddress = 0 in {
2090 def XOR8mr : I<0x30, MRMDestMem,
2091 (outs), (ins i8mem :$dst, GR8 :$src),
2092 "xor{b}\t{$src, $dst|$dst, $src}",
2093 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
2094 (implicit EFLAGS)]>;
2095 def XOR16mr : I<0x31, MRMDestMem,
2096 (outs), (ins i16mem:$dst, GR16:$src),
2097 "xor{w}\t{$src, $dst|$dst, $src}",
2098 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
2099 (implicit EFLAGS)]>,
2101 def XOR32mr : I<0x31, MRMDestMem,
2102 (outs), (ins i32mem:$dst, GR32:$src),
2103 "xor{l}\t{$src, $dst|$dst, $src}",
2104 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
2105 (implicit EFLAGS)]>;
2106 def XOR8mi : Ii8<0x80, MRM6m,
2107 (outs), (ins i8mem :$dst, i8imm :$src),
2108 "xor{b}\t{$src, $dst|$dst, $src}",
2109 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
2110 (implicit EFLAGS)]>;
2111 def XOR16mi : Ii16<0x81, MRM6m,
2112 (outs), (ins i16mem:$dst, i16imm:$src),
2113 "xor{w}\t{$src, $dst|$dst, $src}",
2114 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
2115 (implicit EFLAGS)]>,
2117 def XOR32mi : Ii32<0x81, MRM6m,
2118 (outs), (ins i32mem:$dst, i32imm:$src),
2119 "xor{l}\t{$src, $dst|$dst, $src}",
2120 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
2121 (implicit EFLAGS)]>;
2122 def XOR16mi8 : Ii8<0x83, MRM6m,
2123 (outs), (ins i16mem:$dst, i16i8imm :$src),
2124 "xor{w}\t{$src, $dst|$dst, $src}",
2125 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
2126 (implicit EFLAGS)]>,
2128 def XOR32mi8 : Ii8<0x83, MRM6m,
2129 (outs), (ins i32mem:$dst, i32i8imm :$src),
2130 "xor{l}\t{$src, $dst|$dst, $src}",
2131 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
2132 (implicit EFLAGS)]>;
2134 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
2135 "xor{b}\t{$src, %al|%al, $src}", []>;
2136 def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
2137 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2138 def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
2139 "xor{l}\t{$src, %eax|%eax, $src}", []>;
2140 } // isTwoAddress = 0
2141 } // Defs = [EFLAGS]
2143 // Shift instructions
2144 let Defs = [EFLAGS] in {
2145 let Uses = [CL] in {
2146 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
2147 "shl{b}\t{%cl, $dst|$dst, CL}",
2148 [(set GR8:$dst, (shl GR8:$src, CL))]>;
2149 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
2150 "shl{w}\t{%cl, $dst|$dst, CL}",
2151 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
2152 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
2153 "shl{l}\t{%cl, $dst|$dst, CL}",
2154 [(set GR32:$dst, (shl GR32:$src, CL))]>;
2157 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2158 "shl{b}\t{$src2, $dst|$dst, $src2}",
2159 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
2160 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2161 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2162 "shl{w}\t{$src2, $dst|$dst, $src2}",
2163 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2164 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2165 "shl{l}\t{$src2, $dst|$dst, $src2}",
2166 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
2168 // NOTE: We don't include patterns for shifts of a register by one, because
2169 // 'add reg,reg' is cheaper.
2171 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
2172 "shl{b}\t$dst", []>;
2173 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2174 "shl{w}\t$dst", []>, OpSize;
2175 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2176 "shl{l}\t$dst", []>;
2178 } // isConvertibleToThreeAddress = 1
2180 let isTwoAddress = 0 in {
2181 let Uses = [CL] in {
2182 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
2183 "shl{b}\t{%cl, $dst|$dst, CL}",
2184 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
2185 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
2186 "shl{w}\t{%cl, $dst|$dst, CL}",
2187 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2188 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
2189 "shl{l}\t{%cl, $dst|$dst, CL}",
2190 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
2192 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
2193 "shl{b}\t{$src, $dst|$dst, $src}",
2194 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2195 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
2196 "shl{w}\t{$src, $dst|$dst, $src}",
2197 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2199 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
2200 "shl{l}\t{$src, $dst|$dst, $src}",
2201 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2204 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
2206 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2207 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
2209 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2211 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2213 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2216 let Uses = [CL] in {
2217 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
2218 "shr{b}\t{%cl, $dst|$dst, CL}",
2219 [(set GR8:$dst, (srl GR8:$src, CL))]>;
2220 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
2221 "shr{w}\t{%cl, $dst|$dst, CL}",
2222 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
2223 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
2224 "shr{l}\t{%cl, $dst|$dst, CL}",
2225 [(set GR32:$dst, (srl GR32:$src, CL))]>;
2228 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2229 "shr{b}\t{$src2, $dst|$dst, $src2}",
2230 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2231 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2232 "shr{w}\t{$src2, $dst|$dst, $src2}",
2233 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2234 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2235 "shr{l}\t{$src2, $dst|$dst, $src2}",
2236 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2239 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2241 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2242 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2244 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2245 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2247 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2249 let isTwoAddress = 0 in {
2250 let Uses = [CL] in {
2251 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2252 "shr{b}\t{%cl, $dst|$dst, CL}",
2253 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2254 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2255 "shr{w}\t{%cl, $dst|$dst, CL}",
2256 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2258 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2259 "shr{l}\t{%cl, $dst|$dst, CL}",
2260 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2262 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2263 "shr{b}\t{$src, $dst|$dst, $src}",
2264 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2265 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2266 "shr{w}\t{$src, $dst|$dst, $src}",
2267 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2269 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2270 "shr{l}\t{$src, $dst|$dst, $src}",
2271 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2274 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2276 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2277 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2279 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2280 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2282 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2285 let Uses = [CL] in {
2286 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
2287 "sar{b}\t{%cl, $dst|$dst, CL}",
2288 [(set GR8:$dst, (sra GR8:$src, CL))]>;
2289 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
2290 "sar{w}\t{%cl, $dst|$dst, CL}",
2291 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
2292 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
2293 "sar{l}\t{%cl, $dst|$dst, CL}",
2294 [(set GR32:$dst, (sra GR32:$src, CL))]>;
2297 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2298 "sar{b}\t{$src2, $dst|$dst, $src2}",
2299 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2300 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2301 "sar{w}\t{$src2, $dst|$dst, $src2}",
2302 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2304 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2305 "sar{l}\t{$src2, $dst|$dst, $src2}",
2306 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2309 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2311 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2312 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2314 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2315 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2317 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2319 let isTwoAddress = 0 in {
2320 let Uses = [CL] in {
2321 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2322 "sar{b}\t{%cl, $dst|$dst, CL}",
2323 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2324 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2325 "sar{w}\t{%cl, $dst|$dst, CL}",
2326 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2327 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2328 "sar{l}\t{%cl, $dst|$dst, CL}",
2329 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2331 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2332 "sar{b}\t{$src, $dst|$dst, $src}",
2333 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2334 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2335 "sar{w}\t{$src, $dst|$dst, $src}",
2336 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2338 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2339 "sar{l}\t{$src, $dst|$dst, $src}",
2340 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2343 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2345 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2346 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2348 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2350 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2352 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2355 // Rotate instructions
2357 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2358 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2359 let Uses = [CL] in {
2360 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2361 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2363 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2364 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2366 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2367 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2368 let Uses = [CL] in {
2369 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2370 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2372 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2373 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2375 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2376 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2377 let Uses = [CL] in {
2378 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2379 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2381 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2382 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2384 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2385 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2386 let Uses = [CL] in {
2387 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2388 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2390 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2391 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2393 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2394 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2395 let Uses = [CL] in {
2396 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2397 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2399 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2400 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2402 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2403 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2404 let Uses = [CL] in {
2405 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2406 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2408 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2409 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2411 let isTwoAddress = 0 in {
2412 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
2413 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2414 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2415 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2416 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
2417 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2418 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2419 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2420 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
2421 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2422 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2423 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2424 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
2425 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2426 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2427 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2428 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
2429 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2430 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2431 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2432 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
2433 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2434 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2435 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2437 let Uses = [CL] in {
2438 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
2439 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2440 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
2441 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2442 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
2443 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2444 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
2445 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2446 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
2447 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2448 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
2449 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2453 // FIXME: provide shorter instructions when imm8 == 1
2454 let Uses = [CL] in {
2455 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
2456 "rol{b}\t{%cl, $dst|$dst, CL}",
2457 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
2458 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
2459 "rol{w}\t{%cl, $dst|$dst, CL}",
2460 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
2461 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
2462 "rol{l}\t{%cl, $dst|$dst, CL}",
2463 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2466 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2467 "rol{b}\t{$src2, $dst|$dst, $src2}",
2468 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2469 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2470 "rol{w}\t{$src2, $dst|$dst, $src2}",
2471 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2473 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2474 "rol{l}\t{$src2, $dst|$dst, $src2}",
2475 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2478 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2480 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2481 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2483 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2484 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2486 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2488 let isTwoAddress = 0 in {
2489 let Uses = [CL] in {
2490 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2491 "rol{b}\t{%cl, $dst|$dst, CL}",
2492 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2493 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2494 "rol{w}\t{%cl, $dst|$dst, CL}",
2495 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2496 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2497 "rol{l}\t{%cl, $dst|$dst, CL}",
2498 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2500 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2501 "rol{b}\t{$src, $dst|$dst, $src}",
2502 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2503 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2504 "rol{w}\t{$src, $dst|$dst, $src}",
2505 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2507 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2508 "rol{l}\t{$src, $dst|$dst, $src}",
2509 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2512 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2514 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2515 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2517 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2519 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2521 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2524 let Uses = [CL] in {
2525 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2526 "ror{b}\t{%cl, $dst|$dst, CL}",
2527 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2528 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2529 "ror{w}\t{%cl, $dst|$dst, CL}",
2530 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2531 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2532 "ror{l}\t{%cl, $dst|$dst, CL}",
2533 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2536 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2537 "ror{b}\t{$src2, $dst|$dst, $src2}",
2538 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2539 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2540 "ror{w}\t{$src2, $dst|$dst, $src2}",
2541 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2543 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2544 "ror{l}\t{$src2, $dst|$dst, $src2}",
2545 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2548 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2550 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2551 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2553 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2554 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2556 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2558 let isTwoAddress = 0 in {
2559 let Uses = [CL] in {
2560 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2561 "ror{b}\t{%cl, $dst|$dst, CL}",
2562 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2563 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2564 "ror{w}\t{%cl, $dst|$dst, CL}",
2565 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2566 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2567 "ror{l}\t{%cl, $dst|$dst, CL}",
2568 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2570 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2571 "ror{b}\t{$src, $dst|$dst, $src}",
2572 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2573 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2574 "ror{w}\t{$src, $dst|$dst, $src}",
2575 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2577 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2578 "ror{l}\t{$src, $dst|$dst, $src}",
2579 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2582 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2584 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2585 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2587 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2589 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2591 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2596 // Double shift instructions (generalizations of rotate)
2597 let Uses = [CL] in {
2598 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2599 (ins GR32:$src1, GR32:$src2),
2600 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2601 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2602 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2603 (ins GR32:$src1, GR32:$src2),
2604 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2605 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2606 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2607 (ins GR16:$src1, GR16:$src2),
2608 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2609 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2611 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2612 (ins GR16:$src1, GR16:$src2),
2613 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2614 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2618 let isCommutable = 1 in { // These instructions commute to each other.
2619 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2621 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2622 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2623 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2626 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2628 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2629 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2630 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2633 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2635 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2636 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2637 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2640 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2642 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2643 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2644 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2649 let isTwoAddress = 0 in {
2650 let Uses = [CL] in {
2651 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2652 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2653 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2655 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2656 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2657 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2660 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2661 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2662 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2663 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2664 (i8 imm:$src3)), addr:$dst)]>,
2666 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2667 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2668 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2669 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2670 (i8 imm:$src3)), addr:$dst)]>,
2673 let Uses = [CL] in {
2674 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2675 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2676 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2677 addr:$dst)]>, TB, OpSize;
2678 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2679 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2680 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2681 addr:$dst)]>, TB, OpSize;
2683 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2684 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2685 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2686 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2687 (i8 imm:$src3)), addr:$dst)]>,
2689 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2690 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2691 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2692 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2693 (i8 imm:$src3)), addr:$dst)]>,
2696 } // Defs = [EFLAGS]
2700 let Defs = [EFLAGS] in {
2701 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2702 // Register-Register Addition
2703 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2704 (ins GR8 :$src1, GR8 :$src2),
2705 "add{b}\t{$src2, $dst|$dst, $src2}",
2706 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
2708 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2709 // Register-Register Addition
2710 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2711 (ins GR16:$src1, GR16:$src2),
2712 "add{w}\t{$src2, $dst|$dst, $src2}",
2713 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2714 GR16:$src2))]>, OpSize;
2715 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2716 (ins GR32:$src1, GR32:$src2),
2717 "add{l}\t{$src2, $dst|$dst, $src2}",
2718 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2720 } // end isConvertibleToThreeAddress
2721 } // end isCommutable
2723 // These are alternate spellings for use by the disassembler, we mark them as
2724 // code gen only to ensure they aren't matched by the assembler.
2725 let isCodeGenOnly = 1 in {
2726 def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2727 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2728 def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2729 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2730 def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR32:$dst),(ins GR32:$src1, GR32:$src2),
2731 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2734 // Register-Memory Addition
2735 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2736 (ins GR8 :$src1, i8mem :$src2),
2737 "add{b}\t{$src2, $dst|$dst, $src2}",
2738 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
2739 (load addr:$src2)))]>;
2740 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2741 (ins GR16:$src1, i16mem:$src2),
2742 "add{w}\t{$src2, $dst|$dst, $src2}",
2743 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2744 (load addr:$src2)))]>, OpSize;
2745 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2746 (ins GR32:$src1, i32mem:$src2),
2747 "add{l}\t{$src2, $dst|$dst, $src2}",
2748 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2749 (load addr:$src2)))]>;
2751 // Register-Integer Addition
2752 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2753 "add{b}\t{$src2, $dst|$dst, $src2}",
2754 [(set GR8:$dst, EFLAGS,
2755 (X86add_flag GR8:$src1, imm:$src2))]>;
2757 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2758 // Register-Integer Addition
2759 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2760 (ins GR16:$src1, i16imm:$src2),
2761 "add{w}\t{$src2, $dst|$dst, $src2}",
2762 [(set GR16:$dst, EFLAGS,
2763 (X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
2764 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2765 (ins GR32:$src1, i32imm:$src2),
2766 "add{l}\t{$src2, $dst|$dst, $src2}",
2767 [(set GR32:$dst, EFLAGS,
2768 (X86add_flag GR32:$src1, imm:$src2))]>;
2769 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2770 (ins GR16:$src1, i16i8imm:$src2),
2771 "add{w}\t{$src2, $dst|$dst, $src2}",
2772 [(set GR16:$dst, EFLAGS,
2773 (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2774 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2775 (ins GR32:$src1, i32i8imm:$src2),
2776 "add{l}\t{$src2, $dst|$dst, $src2}",
2777 [(set GR32:$dst, EFLAGS,
2778 (X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
2781 let isTwoAddress = 0 in {
2782 // Memory-Register Addition
2783 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2784 "add{b}\t{$src2, $dst|$dst, $src2}",
2785 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2786 (implicit EFLAGS)]>;
2787 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2788 "add{w}\t{$src2, $dst|$dst, $src2}",
2789 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2790 (implicit EFLAGS)]>, OpSize;
2791 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2792 "add{l}\t{$src2, $dst|$dst, $src2}",
2793 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2794 (implicit EFLAGS)]>;
2795 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2796 "add{b}\t{$src2, $dst|$dst, $src2}",
2797 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2798 (implicit EFLAGS)]>;
2799 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2800 "add{w}\t{$src2, $dst|$dst, $src2}",
2801 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2802 (implicit EFLAGS)]>, OpSize;
2803 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2804 "add{l}\t{$src2, $dst|$dst, $src2}",
2805 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2806 (implicit EFLAGS)]>;
2807 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2808 "add{w}\t{$src2, $dst|$dst, $src2}",
2809 [(store (add (load addr:$dst), i16immSExt8:$src2),
2811 (implicit EFLAGS)]>, OpSize;
2812 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2813 "add{l}\t{$src2, $dst|$dst, $src2}",
2814 [(store (add (load addr:$dst), i32immSExt8:$src2),
2816 (implicit EFLAGS)]>;
2819 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2820 "add{b}\t{$src, %al|%al, $src}", []>;
2821 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2822 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2823 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2824 "add{l}\t{$src, %eax|%eax, $src}", []>;
2827 let Uses = [EFLAGS] in {
2828 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2829 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2830 "adc{b}\t{$src2, $dst|$dst, $src2}",
2831 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2832 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2833 (ins GR16:$src1, GR16:$src2),
2834 "adc{w}\t{$src2, $dst|$dst, $src2}",
2835 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2836 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2837 (ins GR32:$src1, GR32:$src2),
2838 "adc{l}\t{$src2, $dst|$dst, $src2}",
2839 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2842 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2843 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2844 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2845 (ins GR16:$src1, GR16:$src2),
2846 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2847 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2848 (ins GR32:$src1, GR32:$src2),
2849 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2851 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2852 (ins GR8:$src1, i8mem:$src2),
2853 "adc{b}\t{$src2, $dst|$dst, $src2}",
2854 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2855 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2856 (ins GR16:$src1, i16mem:$src2),
2857 "adc{w}\t{$src2, $dst|$dst, $src2}",
2858 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2860 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2861 (ins GR32:$src1, i32mem:$src2),
2862 "adc{l}\t{$src2, $dst|$dst, $src2}",
2863 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2864 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2865 "adc{b}\t{$src2, $dst|$dst, $src2}",
2866 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2867 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2868 (ins GR16:$src1, i16imm:$src2),
2869 "adc{w}\t{$src2, $dst|$dst, $src2}",
2870 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2871 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2872 (ins GR16:$src1, i16i8imm:$src2),
2873 "adc{w}\t{$src2, $dst|$dst, $src2}",
2874 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2876 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2877 (ins GR32:$src1, i32imm:$src2),
2878 "adc{l}\t{$src2, $dst|$dst, $src2}",
2879 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2880 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2881 (ins GR32:$src1, i32i8imm:$src2),
2882 "adc{l}\t{$src2, $dst|$dst, $src2}",
2883 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2885 let isTwoAddress = 0 in {
2886 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2887 "adc{b}\t{$src2, $dst|$dst, $src2}",
2888 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2889 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2890 "adc{w}\t{$src2, $dst|$dst, $src2}",
2891 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2893 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2894 "adc{l}\t{$src2, $dst|$dst, $src2}",
2895 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2896 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2897 "adc{b}\t{$src2, $dst|$dst, $src2}",
2898 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2899 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2900 "adc{w}\t{$src2, $dst|$dst, $src2}",
2901 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2903 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2904 "adc{w}\t{$src2, $dst|$dst, $src2}",
2905 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2907 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2908 "adc{l}\t{$src2, $dst|$dst, $src2}",
2909 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2910 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2911 "adc{l}\t{$src2, $dst|$dst, $src2}",
2912 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2914 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2915 "adc{b}\t{$src, %al|%al, $src}", []>;
2916 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2917 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2918 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2919 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2921 } // Uses = [EFLAGS]
2923 // Register-Register Subtraction
2924 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2925 "sub{b}\t{$src2, $dst|$dst, $src2}",
2926 [(set GR8:$dst, EFLAGS,
2927 (X86sub_flag GR8:$src1, GR8:$src2))]>;
2928 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2929 "sub{w}\t{$src2, $dst|$dst, $src2}",
2930 [(set GR16:$dst, EFLAGS,
2931 (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
2932 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2933 "sub{l}\t{$src2, $dst|$dst, $src2}",
2934 [(set GR32:$dst, EFLAGS,
2935 (X86sub_flag GR32:$src1, GR32:$src2))]>;
2937 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2938 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
2939 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
2940 (ins GR16:$src1, GR16:$src2),
2941 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2942 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
2943 (ins GR32:$src1, GR32:$src2),
2944 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
2946 // Register-Memory Subtraction
2947 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2948 (ins GR8 :$src1, i8mem :$src2),
2949 "sub{b}\t{$src2, $dst|$dst, $src2}",
2950 [(set GR8:$dst, EFLAGS,
2951 (X86sub_flag GR8:$src1, (load addr:$src2)))]>;
2952 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2953 (ins GR16:$src1, i16mem:$src2),
2954 "sub{w}\t{$src2, $dst|$dst, $src2}",
2955 [(set GR16:$dst, EFLAGS,
2956 (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
2957 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2958 (ins GR32:$src1, i32mem:$src2),
2959 "sub{l}\t{$src2, $dst|$dst, $src2}",
2960 [(set GR32:$dst, EFLAGS,
2961 (X86sub_flag GR32:$src1, (load addr:$src2)))]>;
2963 // Register-Integer Subtraction
2964 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2965 (ins GR8:$src1, i8imm:$src2),
2966 "sub{b}\t{$src2, $dst|$dst, $src2}",
2967 [(set GR8:$dst, EFLAGS,
2968 (X86sub_flag GR8:$src1, imm:$src2))]>;
2969 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2970 (ins GR16:$src1, i16imm:$src2),
2971 "sub{w}\t{$src2, $dst|$dst, $src2}",
2972 [(set GR16:$dst, EFLAGS,
2973 (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
2974 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2975 (ins GR32:$src1, i32imm:$src2),
2976 "sub{l}\t{$src2, $dst|$dst, $src2}",
2977 [(set GR32:$dst, EFLAGS,
2978 (X86sub_flag GR32:$src1, imm:$src2))]>;
2979 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2980 (ins GR16:$src1, i16i8imm:$src2),
2981 "sub{w}\t{$src2, $dst|$dst, $src2}",
2982 [(set GR16:$dst, EFLAGS,
2983 (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2984 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2985 (ins GR32:$src1, i32i8imm:$src2),
2986 "sub{l}\t{$src2, $dst|$dst, $src2}",
2987 [(set GR32:$dst, EFLAGS,
2988 (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
2990 let isTwoAddress = 0 in {
2991 // Memory-Register Subtraction
2992 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2993 "sub{b}\t{$src2, $dst|$dst, $src2}",
2994 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2995 (implicit EFLAGS)]>;
2996 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2997 "sub{w}\t{$src2, $dst|$dst, $src2}",
2998 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2999 (implicit EFLAGS)]>, OpSize;
3000 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3001 "sub{l}\t{$src2, $dst|$dst, $src2}",
3002 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
3003 (implicit EFLAGS)]>;
3005 // Memory-Integer Subtraction
3006 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3007 "sub{b}\t{$src2, $dst|$dst, $src2}",
3008 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
3009 (implicit EFLAGS)]>;
3010 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3011 "sub{w}\t{$src2, $dst|$dst, $src2}",
3012 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
3013 (implicit EFLAGS)]>, OpSize;
3014 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3015 "sub{l}\t{$src2, $dst|$dst, $src2}",
3016 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
3017 (implicit EFLAGS)]>;
3018 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3019 "sub{w}\t{$src2, $dst|$dst, $src2}",
3020 [(store (sub (load addr:$dst), i16immSExt8:$src2),
3022 (implicit EFLAGS)]>, OpSize;
3023 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3024 "sub{l}\t{$src2, $dst|$dst, $src2}",
3025 [(store (sub (load addr:$dst), i32immSExt8:$src2),
3027 (implicit EFLAGS)]>;
3029 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
3030 "sub{b}\t{$src, %al|%al, $src}", []>;
3031 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
3032 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3033 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
3034 "sub{l}\t{$src, %eax|%eax, $src}", []>;
3037 let Uses = [EFLAGS] in {
3038 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
3039 (ins GR8:$src1, GR8:$src2),
3040 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3041 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
3042 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
3043 (ins GR16:$src1, GR16:$src2),
3044 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3045 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
3046 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
3047 (ins GR32:$src1, GR32:$src2),
3048 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3049 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
3051 let isTwoAddress = 0 in {
3052 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3053 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3054 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
3055 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3056 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3057 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
3059 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3060 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3061 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
3062 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
3063 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3064 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
3065 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
3066 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3067 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
3069 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3070 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3071 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
3073 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
3074 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3075 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
3076 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3077 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3078 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
3080 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
3081 "sbb{b}\t{$src, %al|%al, $src}", []>;
3082 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
3083 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3084 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
3085 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
3088 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3089 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
3090 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
3091 (ins GR16:$src1, GR16:$src2),
3092 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3093 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
3094 (ins GR32:$src1, GR32:$src2),
3095 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
3097 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
3098 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3099 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
3100 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
3101 (ins GR16:$src1, i16mem:$src2),
3102 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3103 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
3105 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
3106 (ins GR32:$src1, i32mem:$src2),
3107 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3108 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
3109 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
3110 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3111 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
3112 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
3113 (ins GR16:$src1, i16imm:$src2),
3114 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3115 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
3116 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
3117 (ins GR16:$src1, i16i8imm:$src2),
3118 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3119 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
3121 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
3122 (ins GR32:$src1, i32imm:$src2),
3123 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3124 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
3125 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
3126 (ins GR32:$src1, i32i8imm:$src2),
3127 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3128 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
3129 } // Uses = [EFLAGS]
3130 } // Defs = [EFLAGS]
3132 let Defs = [EFLAGS] in {
3133 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
3134 // Register-Register Signed Integer Multiply
3135 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3136 "imul{w}\t{$src2, $dst|$dst, $src2}",
3137 [(set GR16:$dst, EFLAGS,
3138 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
3139 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3140 "imul{l}\t{$src2, $dst|$dst, $src2}",
3141 [(set GR32:$dst, EFLAGS,
3142 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
3145 // Register-Memory Signed Integer Multiply
3146 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
3147 (ins GR16:$src1, i16mem:$src2),
3148 "imul{w}\t{$src2, $dst|$dst, $src2}",
3149 [(set GR16:$dst, EFLAGS,
3150 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
3152 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
3153 (ins GR32:$src1, i32mem:$src2),
3154 "imul{l}\t{$src2, $dst|$dst, $src2}",
3155 [(set GR32:$dst, EFLAGS,
3156 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
3157 } // Defs = [EFLAGS]
3158 } // end Two Address instructions
3160 // Suprisingly enough, these are not two address instructions!
3161 let Defs = [EFLAGS] in {
3162 // Register-Integer Signed Integer Multiply
3163 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
3164 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
3165 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3166 [(set GR16:$dst, EFLAGS,
3167 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
3168 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
3169 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
3170 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3171 [(set GR32:$dst, EFLAGS,
3172 (X86smul_flag GR32:$src1, imm:$src2))]>;
3173 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
3174 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
3175 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3176 [(set GR16:$dst, EFLAGS,
3177 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
3179 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
3180 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
3181 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3182 [(set GR32:$dst, EFLAGS,
3183 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
3185 // Memory-Integer Signed Integer Multiply
3186 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
3187 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
3188 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3189 [(set GR16:$dst, EFLAGS,
3190 (X86smul_flag (load addr:$src1), imm:$src2))]>,
3192 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
3193 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
3194 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3195 [(set GR32:$dst, EFLAGS,
3196 (X86smul_flag (load addr:$src1), imm:$src2))]>;
3197 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
3198 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
3199 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3200 [(set GR16:$dst, EFLAGS,
3201 (X86smul_flag (load addr:$src1),
3202 i16immSExt8:$src2))]>, OpSize;
3203 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
3204 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
3205 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3206 [(set GR32:$dst, EFLAGS,
3207 (X86smul_flag (load addr:$src1),
3208 i32immSExt8:$src2))]>;
3209 } // Defs = [EFLAGS]
3211 //===----------------------------------------------------------------------===//
3212 // Test instructions are just like AND, except they don't generate a result.
3214 let Defs = [EFLAGS] in {
3215 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
3216 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3217 "test{b}\t{$src2, $src1|$src1, $src2}",
3218 [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
3219 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3220 "test{w}\t{$src2, $src1|$src1, $src2}",
3221 [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
3224 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3225 "test{l}\t{$src2, $src1|$src1, $src2}",
3226 [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
3230 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
3231 "test{b}\t{$src, %al|%al, $src}", []>;
3232 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
3233 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3234 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
3235 "test{l}\t{$src, %eax|%eax, $src}", []>;
3237 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
3238 "test{b}\t{$src2, $src1|$src1, $src2}",
3239 [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
3241 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
3242 "test{w}\t{$src2, $src1|$src1, $src2}",
3243 [(set EFLAGS, (X86cmp (and GR16:$src1,
3244 (loadi16 addr:$src2)), 0))]>, OpSize;
3245 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
3246 "test{l}\t{$src2, $src1|$src1, $src2}",
3247 [(set EFLAGS, (X86cmp (and GR32:$src1,
3248 (loadi32 addr:$src2)), 0))]>;
3250 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
3251 (outs), (ins GR8:$src1, i8imm:$src2),
3252 "test{b}\t{$src2, $src1|$src1, $src2}",
3253 [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
3254 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
3255 (outs), (ins GR16:$src1, i16imm:$src2),
3256 "test{w}\t{$src2, $src1|$src1, $src2}",
3257 [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
3259 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
3260 (outs), (ins GR32:$src1, i32imm:$src2),
3261 "test{l}\t{$src2, $src1|$src1, $src2}",
3262 [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
3264 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
3265 (outs), (ins i8mem:$src1, i8imm:$src2),
3266 "test{b}\t{$src2, $src1|$src1, $src2}",
3267 [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
3269 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3270 (outs), (ins i16mem:$src1, i16imm:$src2),
3271 "test{w}\t{$src2, $src1|$src1, $src2}",
3272 [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
3274 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3275 (outs), (ins i32mem:$src1, i32imm:$src2),
3276 "test{l}\t{$src2, $src1|$src1, $src2}",
3277 [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
3279 } // Defs = [EFLAGS]
3282 // Condition code ops, incl. set if equal/not equal/...
3283 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3284 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3285 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3286 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3288 let Uses = [EFLAGS] in {
3289 // Use sbb to materialize carry bit.
3290 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
3291 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
3292 // However, Pat<> can't replicate the destination reg into the inputs of the
3294 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
3296 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
3297 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3298 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
3299 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
3301 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
3302 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3305 def SETEr : I<0x94, MRM0r,
3306 (outs GR8 :$dst), (ins),
3308 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3310 def SETEm : I<0x94, MRM0m,
3311 (outs), (ins i8mem:$dst),
3313 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3316 def SETNEr : I<0x95, MRM0r,
3317 (outs GR8 :$dst), (ins),
3319 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3321 def SETNEm : I<0x95, MRM0m,
3322 (outs), (ins i8mem:$dst),
3324 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3327 def SETLr : I<0x9C, MRM0r,
3328 (outs GR8 :$dst), (ins),
3330 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3331 TB; // GR8 = < signed
3332 def SETLm : I<0x9C, MRM0m,
3333 (outs), (ins i8mem:$dst),
3335 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3336 TB; // [mem8] = < signed
3338 def SETGEr : I<0x9D, MRM0r,
3339 (outs GR8 :$dst), (ins),
3341 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3342 TB; // GR8 = >= signed
3343 def SETGEm : I<0x9D, MRM0m,
3344 (outs), (ins i8mem:$dst),
3346 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3347 TB; // [mem8] = >= signed
3349 def SETLEr : I<0x9E, MRM0r,
3350 (outs GR8 :$dst), (ins),
3352 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3353 TB; // GR8 = <= signed
3354 def SETLEm : I<0x9E, MRM0m,
3355 (outs), (ins i8mem:$dst),
3357 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3358 TB; // [mem8] = <= signed
3360 def SETGr : I<0x9F, MRM0r,
3361 (outs GR8 :$dst), (ins),
3363 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3364 TB; // GR8 = > signed
3365 def SETGm : I<0x9F, MRM0m,
3366 (outs), (ins i8mem:$dst),
3368 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3369 TB; // [mem8] = > signed
3371 def SETBr : I<0x92, MRM0r,
3372 (outs GR8 :$dst), (ins),
3374 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3375 TB; // GR8 = < unsign
3376 def SETBm : I<0x92, MRM0m,
3377 (outs), (ins i8mem:$dst),
3379 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3380 TB; // [mem8] = < unsign
3382 def SETAEr : I<0x93, MRM0r,
3383 (outs GR8 :$dst), (ins),
3385 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3386 TB; // GR8 = >= unsign
3387 def SETAEm : I<0x93, MRM0m,
3388 (outs), (ins i8mem:$dst),
3390 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3391 TB; // [mem8] = >= unsign
3393 def SETBEr : I<0x96, MRM0r,
3394 (outs GR8 :$dst), (ins),
3396 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3397 TB; // GR8 = <= unsign
3398 def SETBEm : I<0x96, MRM0m,
3399 (outs), (ins i8mem:$dst),
3401 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3402 TB; // [mem8] = <= unsign
3404 def SETAr : I<0x97, MRM0r,
3405 (outs GR8 :$dst), (ins),
3407 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3408 TB; // GR8 = > signed
3409 def SETAm : I<0x97, MRM0m,
3410 (outs), (ins i8mem:$dst),
3412 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3413 TB; // [mem8] = > signed
3415 def SETSr : I<0x98, MRM0r,
3416 (outs GR8 :$dst), (ins),
3418 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3419 TB; // GR8 = <sign bit>
3420 def SETSm : I<0x98, MRM0m,
3421 (outs), (ins i8mem:$dst),
3423 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3424 TB; // [mem8] = <sign bit>
3425 def SETNSr : I<0x99, MRM0r,
3426 (outs GR8 :$dst), (ins),
3428 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3429 TB; // GR8 = !<sign bit>
3430 def SETNSm : I<0x99, MRM0m,
3431 (outs), (ins i8mem:$dst),
3433 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3434 TB; // [mem8] = !<sign bit>
3436 def SETPr : I<0x9A, MRM0r,
3437 (outs GR8 :$dst), (ins),
3439 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3441 def SETPm : I<0x9A, MRM0m,
3442 (outs), (ins i8mem:$dst),
3444 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3445 TB; // [mem8] = parity
3446 def SETNPr : I<0x9B, MRM0r,
3447 (outs GR8 :$dst), (ins),
3449 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3450 TB; // GR8 = not parity
3451 def SETNPm : I<0x9B, MRM0m,
3452 (outs), (ins i8mem:$dst),
3454 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3455 TB; // [mem8] = not parity
3457 def SETOr : I<0x90, MRM0r,
3458 (outs GR8 :$dst), (ins),
3460 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3461 TB; // GR8 = overflow
3462 def SETOm : I<0x90, MRM0m,
3463 (outs), (ins i8mem:$dst),
3465 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3466 TB; // [mem8] = overflow
3467 def SETNOr : I<0x91, MRM0r,
3468 (outs GR8 :$dst), (ins),
3470 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3471 TB; // GR8 = not overflow
3472 def SETNOm : I<0x91, MRM0m,
3473 (outs), (ins i8mem:$dst),
3475 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3476 TB; // [mem8] = not overflow
3477 } // Uses = [EFLAGS]
3480 // Integer comparisons
3481 let Defs = [EFLAGS] in {
3482 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3483 "cmp{b}\t{$src, %al|%al, $src}", []>;
3484 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3485 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3486 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3487 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3489 def CMP8rr : I<0x38, MRMDestReg,
3490 (outs), (ins GR8 :$src1, GR8 :$src2),
3491 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3492 [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
3493 def CMP16rr : I<0x39, MRMDestReg,
3494 (outs), (ins GR16:$src1, GR16:$src2),
3495 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3496 [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
3497 def CMP32rr : I<0x39, MRMDestReg,
3498 (outs), (ins GR32:$src1, GR32:$src2),
3499 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3500 [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
3501 def CMP8mr : I<0x38, MRMDestMem,
3502 (outs), (ins i8mem :$src1, GR8 :$src2),
3503 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3504 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
3505 def CMP16mr : I<0x39, MRMDestMem,
3506 (outs), (ins i16mem:$src1, GR16:$src2),
3507 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3508 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
3510 def CMP32mr : I<0x39, MRMDestMem,
3511 (outs), (ins i32mem:$src1, GR32:$src2),
3512 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3513 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
3514 def CMP8rm : I<0x3A, MRMSrcMem,
3515 (outs), (ins GR8 :$src1, i8mem :$src2),
3516 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3517 [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
3518 def CMP16rm : I<0x3B, MRMSrcMem,
3519 (outs), (ins GR16:$src1, i16mem:$src2),
3520 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3521 [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
3523 def CMP32rm : I<0x3B, MRMSrcMem,
3524 (outs), (ins GR32:$src1, i32mem:$src2),
3525 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3526 [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
3528 // These are alternate spellings for use by the disassembler, we mark them as
3529 // code gen only to ensure they aren't matched by the assembler.
3530 let isCodeGenOnly = 1 in {
3531 def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3532 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3533 def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3534 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3535 def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3536 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3539 def CMP8ri : Ii8<0x80, MRM7r,
3540 (outs), (ins GR8:$src1, i8imm:$src2),
3541 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3542 [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
3543 def CMP16ri : Ii16<0x81, MRM7r,
3544 (outs), (ins GR16:$src1, i16imm:$src2),
3545 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3546 [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
3547 def CMP32ri : Ii32<0x81, MRM7r,
3548 (outs), (ins GR32:$src1, i32imm:$src2),
3549 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3550 [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
3551 def CMP8mi : Ii8 <0x80, MRM7m,
3552 (outs), (ins i8mem :$src1, i8imm :$src2),
3553 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3554 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
3555 def CMP16mi : Ii16<0x81, MRM7m,
3556 (outs), (ins i16mem:$src1, i16imm:$src2),
3557 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3558 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
3560 def CMP32mi : Ii32<0x81, MRM7m,
3561 (outs), (ins i32mem:$src1, i32imm:$src2),
3562 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3563 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
3564 def CMP16ri8 : Ii8<0x83, MRM7r,
3565 (outs), (ins GR16:$src1, i16i8imm:$src2),
3566 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3567 [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
3569 def CMP16mi8 : Ii8<0x83, MRM7m,
3570 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3571 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3572 [(set EFLAGS, (X86cmp (loadi16 addr:$src1),
3573 i16immSExt8:$src2))]>, OpSize;
3574 def CMP32mi8 : Ii8<0x83, MRM7m,
3575 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3576 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3577 [(set EFLAGS, (X86cmp (loadi32 addr:$src1),
3578 i32immSExt8:$src2))]>;
3579 def CMP32ri8 : Ii8<0x83, MRM7r,
3580 (outs), (ins GR32:$src1, i32i8imm:$src2),
3581 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3582 [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
3583 } // Defs = [EFLAGS]
3586 // TODO: BTC, BTR, and BTS
3587 let Defs = [EFLAGS] in {
3588 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3589 "bt{w}\t{$src2, $src1|$src1, $src2}",
3590 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
3591 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3592 "bt{l}\t{$src2, $src1|$src1, $src2}",
3593 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
3595 // Unlike with the register+register form, the memory+register form of the
3596 // bt instruction does not ignore the high bits of the index. From ISel's
3597 // perspective, this is pretty bizarre. Make these instructions disassembly
3600 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3601 "bt{w}\t{$src2, $src1|$src1, $src2}",
3602 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3603 // (implicit EFLAGS)]
3605 >, OpSize, TB, Requires<[FastBTMem]>;
3606 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3607 "bt{l}\t{$src2, $src1|$src1, $src2}",
3608 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3609 // (implicit EFLAGS)]
3611 >, TB, Requires<[FastBTMem]>;
3613 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3614 "bt{w}\t{$src2, $src1|$src1, $src2}",
3615 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
3617 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3618 "bt{l}\t{$src2, $src1|$src1, $src2}",
3619 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
3620 // Note that these instructions don't need FastBTMem because that
3621 // only applies when the other operand is in a register. When it's
3622 // an immediate, bt is still fast.
3623 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3624 "bt{w}\t{$src2, $src1|$src1, $src2}",
3625 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
3627 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3628 "bt{l}\t{$src2, $src1|$src1, $src2}",
3629 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
3632 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3633 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3634 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3635 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3636 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3637 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3638 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3639 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3640 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3641 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3642 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3643 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3644 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3645 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3646 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3647 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3649 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3650 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3651 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3652 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3653 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3654 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3655 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3656 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3657 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3658 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3659 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3660 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3661 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3662 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3663 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3664 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3666 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3667 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3668 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3669 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3670 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3671 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3672 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3673 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3674 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3675 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3676 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3677 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3678 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3679 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3680 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3681 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3682 } // Defs = [EFLAGS]
3684 // Sign/Zero extenders
3685 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3686 // of the register here. This has a smaller encoding and avoids a
3687 // partial-register update. Actual movsbw included for the disassembler.
3688 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3689 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3690 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3691 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3692 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3693 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3694 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3695 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3696 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3697 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3698 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3699 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3700 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3701 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3702 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3703 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3704 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3705 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3706 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3707 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3709 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3710 // of the register here. This has a smaller encoding and avoids a
3711 // partial-register update. Actual movzbw included for the disassembler.
3712 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3713 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3714 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3715 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3716 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3717 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3718 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3719 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3720 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3721 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3722 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3723 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3724 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3725 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3726 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3727 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3728 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3729 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3730 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3731 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3733 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
3734 // except that they use GR32_NOREX for the output operand register class
3735 // instead of GR32. This allows them to operate on h registers on x86-64.
3736 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3737 (outs GR32_NOREX:$dst), (ins GR8:$src),
3738 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3741 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3742 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3743 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3746 let neverHasSideEffects = 1 in {
3747 let Defs = [AX], Uses = [AL] in
3748 def CBW : I<0x98, RawFrm, (outs), (ins),
3749 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3750 let Defs = [EAX], Uses = [AX] in
3751 def CWDE : I<0x98, RawFrm, (outs), (ins),
3752 "{cwtl|cwde}", []>; // EAX = signext(AX)
3754 let Defs = [AX,DX], Uses = [AX] in
3755 def CWD : I<0x99, RawFrm, (outs), (ins),
3756 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3757 let Defs = [EAX,EDX], Uses = [EAX] in
3758 def CDQ : I<0x99, RawFrm, (outs), (ins),
3759 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3762 //===----------------------------------------------------------------------===//
3763 // Alias Instructions
3764 //===----------------------------------------------------------------------===//
3766 // Alias instructions that map movr0 to xor.
3767 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3768 // FIXME: Set encoding to pseudo.
3769 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3770 isCodeGenOnly = 1 in {
3771 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
3772 [(set GR8:$dst, 0)]>;
3774 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
3775 // encoding and avoids a partial-register update sometimes, but doing so
3776 // at isel time interferes with rematerialization in the current register
3777 // allocator. For now, this is rewritten when the instruction is lowered
3779 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3781 [(set GR16:$dst, 0)]>, OpSize;
3783 // FIXME: Set encoding to pseudo.
3784 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
3785 [(set GR32:$dst, 0)]>;
3788 //===----------------------------------------------------------------------===//
3789 // Thread Local Storage Instructions
3792 // All calls clobber the non-callee saved registers. ESP is marked as
3793 // a use to prevent stack-pointer assignments that appear immediately
3794 // before calls from potentially appearing dead.
3795 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3796 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3797 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3798 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3800 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3801 "leal\t$sym, %eax; "
3802 "call\t___tls_get_addr@PLT",
3803 [(X86tlsaddr tls32addr:$sym)]>,
3804 Requires<[In32BitMode]>;
3806 let AddedComplexity = 5, isCodeGenOnly = 1 in
3807 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3808 "movl\t%gs:$src, $dst",
3809 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3811 let AddedComplexity = 5, isCodeGenOnly = 1 in
3812 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3813 "movl\t%fs:$src, $dst",
3814 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3816 //===----------------------------------------------------------------------===//
3817 // EH Pseudo Instructions
3819 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3820 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3821 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3822 "ret\t#eh_return, addr: $addr",
3823 [(X86ehret GR32:$addr)]>;
3827 //===----------------------------------------------------------------------===//
3831 // Atomic swap. These are just normal xchg instructions. But since a memory
3832 // operand is referenced, the atomicity is ensured.
3833 let Constraints = "$val = $dst" in {
3834 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3835 (ins GR32:$val, i32mem:$ptr),
3836 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3837 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3838 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3839 (ins GR16:$val, i16mem:$ptr),
3840 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3841 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3843 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3844 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3845 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3847 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3848 "xchg{l}\t{$val, $src|$src, $val}", []>;
3849 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3850 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3851 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3852 "xchg{b}\t{$val, $src|$src, $val}", []>;
3855 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3856 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3857 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3858 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
3860 // Atomic compare and swap.
3861 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3862 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3864 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3865 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3867 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3868 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
3871 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3874 let Defs = [AX, EFLAGS], Uses = [AX] in {
3875 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3877 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3878 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3880 let Defs = [AL, EFLAGS], Uses = [AL] in {
3881 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3883 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3884 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3887 // Atomic exchange and add
3888 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3889 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
3891 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3892 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3894 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
3896 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3897 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3899 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3901 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3902 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3906 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3907 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3908 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3909 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3910 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3911 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3913 let mayLoad = 1, mayStore = 1 in {
3914 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3915 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3916 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3917 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3918 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3919 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3922 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3923 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3924 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3925 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3926 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3927 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3929 let mayLoad = 1, mayStore = 1 in {
3930 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3931 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3932 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3933 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3934 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3935 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3938 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
3939 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
3940 "cmpxchg8b\t$dst", []>, TB;
3942 // Optimized codegen when the non-memory output is not used.
3943 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3944 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1 in {
3945 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3947 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3948 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3950 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3951 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3953 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3954 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3956 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3957 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3959 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3960 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3962 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3963 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3965 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3966 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3968 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3970 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3972 "inc{b}\t$dst", []>, LOCK;
3973 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3975 "inc{w}\t$dst", []>, OpSize, LOCK;
3976 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3978 "inc{l}\t$dst", []>, LOCK;
3980 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3982 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3983 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3985 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3986 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3988 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3989 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3991 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3992 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3994 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3995 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3997 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3998 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
4000 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4001 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
4003 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4005 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
4007 "dec{b}\t$dst", []>, LOCK;
4008 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
4010 "dec{w}\t$dst", []>, OpSize, LOCK;
4011 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
4013 "dec{l}\t$dst", []>, LOCK;
4016 // Atomic exchange, and, or, xor
4017 let Constraints = "$val = $dst", Defs = [EFLAGS],
4018 usesCustomInserter = 1 in {
4019 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4020 "#ATOMAND32 PSEUDO!",
4021 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
4022 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4023 "#ATOMOR32 PSEUDO!",
4024 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
4025 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4026 "#ATOMXOR32 PSEUDO!",
4027 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
4028 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4029 "#ATOMNAND32 PSEUDO!",
4030 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
4031 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
4032 "#ATOMMIN32 PSEUDO!",
4033 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
4034 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4035 "#ATOMMAX32 PSEUDO!",
4036 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
4037 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4038 "#ATOMUMIN32 PSEUDO!",
4039 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
4040 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4041 "#ATOMUMAX32 PSEUDO!",
4042 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
4044 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4045 "#ATOMAND16 PSEUDO!",
4046 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
4047 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4048 "#ATOMOR16 PSEUDO!",
4049 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
4050 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4051 "#ATOMXOR16 PSEUDO!",
4052 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
4053 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4054 "#ATOMNAND16 PSEUDO!",
4055 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
4056 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
4057 "#ATOMMIN16 PSEUDO!",
4058 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
4059 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4060 "#ATOMMAX16 PSEUDO!",
4061 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
4062 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4063 "#ATOMUMIN16 PSEUDO!",
4064 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
4065 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4066 "#ATOMUMAX16 PSEUDO!",
4067 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
4069 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4070 "#ATOMAND8 PSEUDO!",
4071 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
4072 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4074 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
4075 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4076 "#ATOMXOR8 PSEUDO!",
4077 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
4078 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4079 "#ATOMNAND8 PSEUDO!",
4080 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
4083 let Constraints = "$val1 = $dst1, $val2 = $dst2",
4084 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
4085 Uses = [EAX, EBX, ECX, EDX],
4086 mayLoad = 1, mayStore = 1,
4087 usesCustomInserter = 1 in {
4088 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4089 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4090 "#ATOMAND6432 PSEUDO!", []>;
4091 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4092 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4093 "#ATOMOR6432 PSEUDO!", []>;
4094 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4095 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4096 "#ATOMXOR6432 PSEUDO!", []>;
4097 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4098 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4099 "#ATOMNAND6432 PSEUDO!", []>;
4100 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4101 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4102 "#ATOMADD6432 PSEUDO!", []>;
4103 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4104 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4105 "#ATOMSUB6432 PSEUDO!", []>;
4106 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4107 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4108 "#ATOMSWAP6432 PSEUDO!", []>;
4111 // Segmentation support instructions.
4113 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4114 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4115 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4116 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4118 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
4119 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
4120 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4121 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4122 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4124 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4125 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4126 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4127 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4128 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4129 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4130 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4131 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4133 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
4135 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
4136 "str{w}\t{$dst}", []>, TB;
4137 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
4138 "str{w}\t{$dst}", []>, TB;
4139 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
4140 "ltr{w}\t{$src}", []>, TB;
4141 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
4142 "ltr{w}\t{$src}", []>, TB;
4144 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
4145 "push{w}\t%fs", []>, OpSize, TB;
4146 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
4147 "push{l}\t%fs", []>, TB;
4148 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
4149 "push{w}\t%gs", []>, OpSize, TB;
4150 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
4151 "push{l}\t%gs", []>, TB;
4153 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
4154 "pop{w}\t%fs", []>, OpSize, TB;
4155 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
4156 "pop{l}\t%fs", []>, TB;
4157 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
4158 "pop{w}\t%gs", []>, OpSize, TB;
4159 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
4160 "pop{l}\t%gs", []>, TB;
4162 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4163 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4164 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4165 "lds{l}\t{$src, $dst|$dst, $src}", []>;
4166 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4167 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4168 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4169 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
4170 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4171 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4172 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4173 "les{l}\t{$src, $dst|$dst, $src}", []>;
4174 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4175 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4176 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4177 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4178 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4179 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4180 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4181 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4183 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
4184 "verr\t$seg", []>, TB;
4185 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
4186 "verr\t$seg", []>, TB;
4187 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
4188 "verw\t$seg", []>, TB;
4189 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
4190 "verw\t$seg", []>, TB;
4192 // Descriptor-table support instructions
4194 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
4195 "sgdt\t$dst", []>, TB;
4196 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
4197 "sidt\t$dst", []>, TB;
4198 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
4199 "sldt{w}\t$dst", []>, TB;
4200 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
4201 "sldt{w}\t$dst", []>, TB;
4202 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
4203 "lgdt\t$src", []>, TB;
4204 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
4205 "lidt\t$src", []>, TB;
4206 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
4207 "lldt{w}\t$src", []>, TB;
4208 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
4209 "lldt{w}\t$src", []>, TB;
4211 // Lock instruction prefix
4212 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
4214 // Repeat string operation instruction prefixes
4215 // These uses the DF flag in the EFLAGS register to inc or dec ECX
4216 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
4217 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
4218 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
4219 // Repeat while not equal (used with CMPS and SCAS)
4220 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
4223 // Segment override instruction prefixes
4224 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
4225 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
4226 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
4227 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
4228 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
4229 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
4231 // String manipulation instructions
4233 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
4234 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
4235 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
4237 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
4238 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
4239 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
4241 // CPU flow control instructions
4243 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
4244 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
4246 // FPU control instructions
4248 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
4250 // Flag instructions
4252 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
4253 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
4254 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
4255 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
4256 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
4257 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
4258 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
4260 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
4262 // Table lookup instructions
4264 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
4266 // Specialized register support
4268 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
4269 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
4270 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
4272 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
4273 "smsw{w}\t$dst", []>, OpSize, TB;
4274 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
4275 "smsw{l}\t$dst", []>, TB;
4276 // For memory operands, there is only a 16-bit form
4277 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
4278 "smsw{w}\t$dst", []>, TB;
4280 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
4281 "lmsw{w}\t$src", []>, TB;
4282 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
4283 "lmsw{w}\t$src", []>, TB;
4285 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
4287 // Cache instructions
4289 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
4290 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
4295 def INVEPT : I<0x80, RawFrm, (outs), (ins), "invept", []>, OpSize, T8;
4297 def INVVPID : I<0x81, RawFrm, (outs), (ins), "invvpid", []>, OpSize, T8;
4299 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
4300 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4301 "vmclear\t$vmcs", []>, OpSize, TB;
4303 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
4305 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
4306 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4307 "vmptrld\t$vmcs", []>, TB;
4308 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4309 "vmptrst\t$vmcs", []>, TB;
4310 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
4311 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4312 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
4313 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4314 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
4315 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4316 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4317 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4318 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4319 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4320 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4321 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4322 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4323 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4324 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4325 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4327 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
4328 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
4329 "vmxon\t{$vmxon}", []>, XS;
4331 //===----------------------------------------------------------------------===//
4332 // Non-Instruction Patterns
4333 //===----------------------------------------------------------------------===//
4335 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
4336 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
4337 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
4338 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
4339 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
4340 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
4341 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
4343 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
4344 (ADD32ri GR32:$src1, tconstpool:$src2)>;
4345 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
4346 (ADD32ri GR32:$src1, tjumptable:$src2)>;
4347 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
4348 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
4349 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
4350 (ADD32ri GR32:$src1, texternalsym:$src2)>;
4351 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
4352 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
4354 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
4355 (MOV32mi addr:$dst, tglobaladdr:$src)>;
4356 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
4357 (MOV32mi addr:$dst, texternalsym:$src)>;
4358 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
4359 (MOV32mi addr:$dst, tblockaddress:$src)>;
4363 def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
4364 (TCRETURNri GR32_TC:$dst, imm:$off)>,
4365 Requires<[In32BitMode]>;
4367 // FIXME: This is disabled for 32-bit PIC mode because the global base
4368 // register which is part of the address mode may be assigned a
4369 // callee-saved register.
4370 def : Pat<(X86tcret (load addr:$dst), imm:$off),
4371 (TCRETURNmi addr:$dst, imm:$off)>,
4372 Requires<[In32BitMode, IsNotPIC]>;
4374 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
4375 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4376 Requires<[In32BitMode]>;
4378 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
4379 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4380 Requires<[In32BitMode]>;
4382 // Normal calls, with various flavors of addresses.
4383 def : Pat<(X86call (i32 tglobaladdr:$dst)),
4384 (CALLpcrel32 tglobaladdr:$dst)>;
4385 def : Pat<(X86call (i32 texternalsym:$dst)),
4386 (CALLpcrel32 texternalsym:$dst)>;
4387 def : Pat<(X86call (i32 imm:$dst)),
4388 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
4390 // X86 specific add which produces a flag.
4391 def : Pat<(addc GR32:$src1, GR32:$src2),
4392 (ADD32rr GR32:$src1, GR32:$src2)>;
4393 def : Pat<(addc GR32:$src1, (load addr:$src2)),
4394 (ADD32rm GR32:$src1, addr:$src2)>;
4395 def : Pat<(addc GR32:$src1, imm:$src2),
4396 (ADD32ri GR32:$src1, imm:$src2)>;
4397 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
4398 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4400 def : Pat<(subc GR32:$src1, GR32:$src2),
4401 (SUB32rr GR32:$src1, GR32:$src2)>;
4402 def : Pat<(subc GR32:$src1, (load addr:$src2)),
4403 (SUB32rm GR32:$src1, addr:$src2)>;
4404 def : Pat<(subc GR32:$src1, imm:$src2),
4405 (SUB32ri GR32:$src1, imm:$src2)>;
4406 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
4407 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4411 // TEST R,R is smaller than CMP R,0
4412 def : Pat<(X86cmp GR8:$src1, 0),
4413 (TEST8rr GR8:$src1, GR8:$src1)>;
4414 def : Pat<(X86cmp GR16:$src1, 0),
4415 (TEST16rr GR16:$src1, GR16:$src1)>;
4416 def : Pat<(X86cmp GR32:$src1, 0),
4417 (TEST32rr GR32:$src1, GR32:$src1)>;
4419 // Conditional moves with folded loads with operands swapped and conditions
4421 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
4422 (CMOVAE16rm GR16:$src2, addr:$src1)>;
4423 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
4424 (CMOVAE32rm GR32:$src2, addr:$src1)>;
4425 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
4426 (CMOVB16rm GR16:$src2, addr:$src1)>;
4427 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
4428 (CMOVB32rm GR32:$src2, addr:$src1)>;
4429 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
4430 (CMOVNE16rm GR16:$src2, addr:$src1)>;
4431 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
4432 (CMOVNE32rm GR32:$src2, addr:$src1)>;
4433 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
4434 (CMOVE16rm GR16:$src2, addr:$src1)>;
4435 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
4436 (CMOVE32rm GR32:$src2, addr:$src1)>;
4437 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
4438 (CMOVA16rm GR16:$src2, addr:$src1)>;
4439 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
4440 (CMOVA32rm GR32:$src2, addr:$src1)>;
4441 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
4442 (CMOVBE16rm GR16:$src2, addr:$src1)>;
4443 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
4444 (CMOVBE32rm GR32:$src2, addr:$src1)>;
4445 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
4446 (CMOVGE16rm GR16:$src2, addr:$src1)>;
4447 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
4448 (CMOVGE32rm GR32:$src2, addr:$src1)>;
4449 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
4450 (CMOVL16rm GR16:$src2, addr:$src1)>;
4451 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
4452 (CMOVL32rm GR32:$src2, addr:$src1)>;
4453 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
4454 (CMOVG16rm GR16:$src2, addr:$src1)>;
4455 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
4456 (CMOVG32rm GR32:$src2, addr:$src1)>;
4457 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
4458 (CMOVLE16rm GR16:$src2, addr:$src1)>;
4459 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
4460 (CMOVLE32rm GR32:$src2, addr:$src1)>;
4461 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
4462 (CMOVNP16rm GR16:$src2, addr:$src1)>;
4463 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
4464 (CMOVNP32rm GR32:$src2, addr:$src1)>;
4465 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
4466 (CMOVP16rm GR16:$src2, addr:$src1)>;
4467 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
4468 (CMOVP32rm GR32:$src2, addr:$src1)>;
4469 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
4470 (CMOVNS16rm GR16:$src2, addr:$src1)>;
4471 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
4472 (CMOVNS32rm GR32:$src2, addr:$src1)>;
4473 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
4474 (CMOVS16rm GR16:$src2, addr:$src1)>;
4475 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
4476 (CMOVS32rm GR32:$src2, addr:$src1)>;
4477 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
4478 (CMOVNO16rm GR16:$src2, addr:$src1)>;
4479 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
4480 (CMOVNO32rm GR32:$src2, addr:$src1)>;
4481 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
4482 (CMOVO16rm GR16:$src2, addr:$src1)>;
4483 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
4484 (CMOVO32rm GR32:$src2, addr:$src1)>;
4486 // zextload bool -> zextload byte
4487 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4488 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4489 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4491 // extload bool -> extload byte
4492 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4493 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4494 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4495 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
4496 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
4497 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
4499 // anyext. Define these to do an explicit zero-extend to
4500 // avoid partial-register updates.
4501 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
4502 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
4504 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
4505 def : Pat<(i32 (anyext GR16:$src)),
4506 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
4509 //===----------------------------------------------------------------------===//
4511 //===----------------------------------------------------------------------===//
4513 // Odd encoding trick: -128 fits into an 8-bit immediate field while
4514 // +128 doesn't, so in this special case use a sub instead of an add.
4515 def : Pat<(add GR16:$src1, 128),
4516 (SUB16ri8 GR16:$src1, -128)>;
4517 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
4518 (SUB16mi8 addr:$dst, -128)>;
4519 def : Pat<(add GR32:$src1, 128),
4520 (SUB32ri8 GR32:$src1, -128)>;
4521 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
4522 (SUB32mi8 addr:$dst, -128)>;
4524 // r & (2^16-1) ==> movz
4525 def : Pat<(and GR32:$src1, 0xffff),
4526 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
4527 // r & (2^8-1) ==> movz
4528 def : Pat<(and GR32:$src1, 0xff),
4529 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
4532 Requires<[In32BitMode]>;
4533 // r & (2^8-1) ==> movz
4534 def : Pat<(and GR16:$src1, 0xff),
4535 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
4538 Requires<[In32BitMode]>;
4540 // sext_inreg patterns
4541 def : Pat<(sext_inreg GR32:$src, i16),
4542 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
4543 def : Pat<(sext_inreg GR32:$src, i8),
4544 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4547 Requires<[In32BitMode]>;
4548 def : Pat<(sext_inreg GR16:$src, i8),
4549 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4552 Requires<[In32BitMode]>;
4555 def : Pat<(i16 (trunc GR32:$src)),
4556 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
4557 def : Pat<(i8 (trunc GR32:$src)),
4558 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4560 Requires<[In32BitMode]>;
4561 def : Pat<(i8 (trunc GR16:$src)),
4562 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4564 Requires<[In32BitMode]>;
4566 // h-register tricks
4567 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
4568 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4570 Requires<[In32BitMode]>;
4571 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
4572 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4574 Requires<[In32BitMode]>;
4575 def : Pat<(srl GR16:$src, (i8 8)),
4578 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4581 Requires<[In32BitMode]>;
4582 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4583 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4586 Requires<[In32BitMode]>;
4587 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4588 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4591 Requires<[In32BitMode]>;
4592 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4593 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4596 Requires<[In32BitMode]>;
4597 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
4598 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4601 Requires<[In32BitMode]>;
4603 // (shl x, 1) ==> (add x, x)
4604 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
4605 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
4606 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
4608 // (shl x (and y, 31)) ==> (shl x, y)
4609 def : Pat<(shl GR8:$src1, (and CL, 31)),
4610 (SHL8rCL GR8:$src1)>;
4611 def : Pat<(shl GR16:$src1, (and CL, 31)),
4612 (SHL16rCL GR16:$src1)>;
4613 def : Pat<(shl GR32:$src1, (and CL, 31)),
4614 (SHL32rCL GR32:$src1)>;
4615 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4616 (SHL8mCL addr:$dst)>;
4617 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4618 (SHL16mCL addr:$dst)>;
4619 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4620 (SHL32mCL addr:$dst)>;
4622 def : Pat<(srl GR8:$src1, (and CL, 31)),
4623 (SHR8rCL GR8:$src1)>;
4624 def : Pat<(srl GR16:$src1, (and CL, 31)),
4625 (SHR16rCL GR16:$src1)>;
4626 def : Pat<(srl GR32:$src1, (and CL, 31)),
4627 (SHR32rCL GR32:$src1)>;
4628 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4629 (SHR8mCL addr:$dst)>;
4630 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4631 (SHR16mCL addr:$dst)>;
4632 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4633 (SHR32mCL addr:$dst)>;
4635 def : Pat<(sra GR8:$src1, (and CL, 31)),
4636 (SAR8rCL GR8:$src1)>;
4637 def : Pat<(sra GR16:$src1, (and CL, 31)),
4638 (SAR16rCL GR16:$src1)>;
4639 def : Pat<(sra GR32:$src1, (and CL, 31)),
4640 (SAR32rCL GR32:$src1)>;
4641 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4642 (SAR8mCL addr:$dst)>;
4643 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4644 (SAR16mCL addr:$dst)>;
4645 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4646 (SAR32mCL addr:$dst)>;
4648 // (anyext (setcc_carry)) -> (setcc_carry)
4649 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4651 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4653 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
4656 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
4657 let AddedComplexity = 5 in { // Try this before the selecting to OR
4658 def : Pat<(or_is_add GR16:$src1, imm:$src2),
4659 (ADD16ri GR16:$src1, imm:$src2)>;
4660 def : Pat<(or_is_add GR32:$src1, imm:$src2),
4661 (ADD32ri GR32:$src1, imm:$src2)>;
4662 def : Pat<(or_is_add GR16:$src1, i16immSExt8:$src2),
4663 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4664 def : Pat<(or_is_add GR32:$src1, i32immSExt8:$src2),
4665 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4666 def : Pat<(or_is_add GR16:$src1, GR16:$src2),
4667 (ADD16rr GR16:$src1, GR16:$src2)>;
4668 def : Pat<(or_is_add GR32:$src1, GR32:$src2),
4669 (ADD32rr GR32:$src1, GR32:$src2)>;
4670 } // AddedComplexity
4672 //===----------------------------------------------------------------------===//
4673 // EFLAGS-defining Patterns
4674 //===----------------------------------------------------------------------===//
4677 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
4678 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
4679 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
4682 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
4683 (ADD8rm GR8:$src1, addr:$src2)>;
4684 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
4685 (ADD16rm GR16:$src1, addr:$src2)>;
4686 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
4687 (ADD32rm GR32:$src1, addr:$src2)>;
4690 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
4691 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
4692 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
4693 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
4694 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4695 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
4696 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4699 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
4700 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
4701 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
4704 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
4705 (SUB8rm GR8:$src1, addr:$src2)>;
4706 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
4707 (SUB16rm GR16:$src1, addr:$src2)>;
4708 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
4709 (SUB32rm GR32:$src1, addr:$src2)>;
4712 def : Pat<(sub GR8:$src1, imm:$src2),
4713 (SUB8ri GR8:$src1, imm:$src2)>;
4714 def : Pat<(sub GR16:$src1, imm:$src2),
4715 (SUB16ri GR16:$src1, imm:$src2)>;
4716 def : Pat<(sub GR32:$src1, imm:$src2),
4717 (SUB32ri GR32:$src1, imm:$src2)>;
4718 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
4719 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4720 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
4721 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4724 def : Pat<(mul GR16:$src1, GR16:$src2),
4725 (IMUL16rr GR16:$src1, GR16:$src2)>;
4726 def : Pat<(mul GR32:$src1, GR32:$src2),
4727 (IMUL32rr GR32:$src1, GR32:$src2)>;
4730 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
4731 (IMUL16rm GR16:$src1, addr:$src2)>;
4732 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
4733 (IMUL32rm GR32:$src1, addr:$src2)>;
4736 def : Pat<(mul GR16:$src1, imm:$src2),
4737 (IMUL16rri GR16:$src1, imm:$src2)>;
4738 def : Pat<(mul GR32:$src1, imm:$src2),
4739 (IMUL32rri GR32:$src1, imm:$src2)>;
4740 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
4741 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4742 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
4743 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4745 // reg = mul mem, imm
4746 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
4747 (IMUL16rmi addr:$src1, imm:$src2)>;
4748 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
4749 (IMUL32rmi addr:$src1, imm:$src2)>;
4750 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
4751 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4752 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
4753 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4755 // Optimize multiply by 2 with EFLAGS result.
4756 let AddedComplexity = 2 in {
4757 def : Pat<(X86smul_flag GR16:$src1, 2), (ADD16rr GR16:$src1, GR16:$src1)>;
4758 def : Pat<(X86smul_flag GR32:$src1, 2), (ADD32rr GR32:$src1, GR32:$src1)>;
4761 // Patterns for nodes that do not produce flags, for instructions that do.
4764 def : Pat<(add GR8:$src , 1), (INC8r GR8:$src)>;
4765 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>;
4766 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>;
4769 def : Pat<(add GR8:$src , -1), (DEC8r GR8:$src)>;
4770 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
4771 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
4774 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
4775 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
4776 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
4779 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
4780 (OR8rm GR8:$src1, addr:$src2)>;
4781 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
4782 (OR16rm GR16:$src1, addr:$src2)>;
4783 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
4784 (OR32rm GR32:$src1, addr:$src2)>;
4787 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
4788 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
4789 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
4790 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
4791 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4792 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
4793 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4796 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
4797 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
4798 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
4801 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
4802 (XOR8rm GR8:$src1, addr:$src2)>;
4803 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
4804 (XOR16rm GR16:$src1, addr:$src2)>;
4805 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
4806 (XOR32rm GR32:$src1, addr:$src2)>;
4809 def : Pat<(xor GR8:$src1, imm:$src2),
4810 (XOR8ri GR8:$src1, imm:$src2)>;
4811 def : Pat<(xor GR16:$src1, imm:$src2),
4812 (XOR16ri GR16:$src1, imm:$src2)>;
4813 def : Pat<(xor GR32:$src1, imm:$src2),
4814 (XOR32ri GR32:$src1, imm:$src2)>;
4815 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
4816 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4817 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
4818 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4821 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
4822 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
4823 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
4826 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
4827 (AND8rm GR8:$src1, addr:$src2)>;
4828 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
4829 (AND16rm GR16:$src1, addr:$src2)>;
4830 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
4831 (AND32rm GR32:$src1, addr:$src2)>;
4834 def : Pat<(and GR8:$src1, imm:$src2),
4835 (AND8ri GR8:$src1, imm:$src2)>;
4836 def : Pat<(and GR16:$src1, imm:$src2),
4837 (AND16ri GR16:$src1, imm:$src2)>;
4838 def : Pat<(and GR32:$src1, imm:$src2),
4839 (AND32ri GR32:$src1, imm:$src2)>;
4840 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
4841 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
4842 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
4843 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
4845 //===----------------------------------------------------------------------===//
4846 // Floating Point Stack Support
4847 //===----------------------------------------------------------------------===//
4849 include "X86InstrFPStack.td"
4851 //===----------------------------------------------------------------------===//
4853 //===----------------------------------------------------------------------===//
4855 include "X86Instr64bit.td"
4857 //===----------------------------------------------------------------------===//
4858 // SIMD support (SSE, MMX and AVX)
4859 //===----------------------------------------------------------------------===//
4861 include "X86InstrFragmentsSIMD.td"
4863 //===----------------------------------------------------------------------===//
4864 // XMM Floating point support (requires SSE / SSE2)
4865 //===----------------------------------------------------------------------===//
4867 include "X86InstrSSE.td"
4869 //===----------------------------------------------------------------------===//
4870 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
4871 //===----------------------------------------------------------------------===//
4873 include "X86InstrMMX.td"