1 //===----------------------------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
32 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
34 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTX86BrCond : SDTypeProfile<0, 3,
39 [SDTCisVT<0, OtherVT>,
40 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
42 def SDTX86SetCC : SDTypeProfile<1, 2,
44 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86SetCC_C : SDTypeProfile<1, 2,
47 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
49 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
51 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
53 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
54 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
55 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
57 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
58 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
61 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
63 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
67 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
69 def SDTX86Void : SDTypeProfile<0, 0, []>;
71 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
73 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
75 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
77 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
79 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
81 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
82 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
83 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
84 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
86 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
87 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
89 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
90 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
92 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
93 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
95 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
96 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
98 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
99 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
101 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
102 [SDNPHasChain, SDNPMayStore,
103 SDNPMayLoad, SDNPMemOperand]>;
104 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
105 [SDNPHasChain, SDNPMayStore,
106 SDNPMayLoad, SDNPMemOperand]>;
107 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
108 [SDNPHasChain, SDNPMayStore,
109 SDNPMayLoad, SDNPMemOperand]>;
110 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
111 [SDNPHasChain, SDNPMayStore,
112 SDNPMayLoad, SDNPMemOperand]>;
113 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
114 [SDNPHasChain, SDNPMayStore,
115 SDNPMayLoad, SDNPMemOperand]>;
116 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
117 [SDNPHasChain, SDNPMayStore,
118 SDNPMayLoad, SDNPMemOperand]>;
119 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
120 [SDNPHasChain, SDNPMayStore,
121 SDNPMayLoad, SDNPMemOperand]>;
122 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
123 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
125 def X86vastart_save_xmm_regs :
126 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
127 SDT_X86VASTART_SAVE_XMM_REGS,
128 [SDNPHasChain, SDNPVariadic]>;
130 def X86callseq_start :
131 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
132 [SDNPHasChain, SDNPOutFlag]>;
134 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
135 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
137 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
138 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
141 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
142 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
143 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
144 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
147 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
148 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
150 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
151 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
153 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
154 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
155 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
156 SDT_X86SegmentBaseAddress, []>;
158 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
161 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
162 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
164 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
166 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
167 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
169 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
172 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
173 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
174 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
176 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
178 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
181 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
183 def X86MingwAlloca : SDNode<"X86ISD::MINGW_ALLOCA", SDTX86Void,
184 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
186 //===----------------------------------------------------------------------===//
187 // X86 Operand Definitions.
190 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
191 // the index operand of an address, to conform to x86 encoding restrictions.
192 def ptr_rc_nosp : PointerLikeRegClass<1>;
194 // *mem - Operand definitions for the funky X86 addressing mode operands.
196 def X86MemAsmOperand : AsmOperandClass {
200 def X86NoSegMemAsmOperand : AsmOperandClass {
201 let Name = "NoSegMem";
202 let SuperClass = X86MemAsmOperand;
204 def X86AbsMemAsmOperand : AsmOperandClass {
206 let SuperClass = X86NoSegMemAsmOperand;
208 class X86MemOperand<string printMethod> : Operand<iPTR> {
209 let PrintMethod = printMethod;
210 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
211 let ParserMatchClass = X86MemAsmOperand;
214 def opaque32mem : X86MemOperand<"printopaquemem">;
215 def opaque48mem : X86MemOperand<"printopaquemem">;
216 def opaque80mem : X86MemOperand<"printopaquemem">;
217 def opaque512mem : X86MemOperand<"printopaquemem">;
219 def i8mem : X86MemOperand<"printi8mem">;
220 def i16mem : X86MemOperand<"printi16mem">;
221 def i32mem : X86MemOperand<"printi32mem">;
222 def i64mem : X86MemOperand<"printi64mem">;
223 def i128mem : X86MemOperand<"printi128mem">;
224 //def i256mem : X86MemOperand<"printi256mem">;
225 def f32mem : X86MemOperand<"printf32mem">;
226 def f64mem : X86MemOperand<"printf64mem">;
227 def f80mem : X86MemOperand<"printf80mem">;
228 def f128mem : X86MemOperand<"printf128mem">;
229 //def f256mem : X86MemOperand<"printf256mem">;
231 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
232 // plain GR64, so that it doesn't potentially require a REX prefix.
233 def i8mem_NOREX : Operand<i64> {
234 let PrintMethod = "printi8mem";
235 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
236 let ParserMatchClass = X86MemAsmOperand;
239 // Special i32mem for addresses of load folding tail calls. These are not
240 // allowed to use callee-saved registers since they must be scheduled
241 // after callee-saved register are popped.
242 def i32mem_TC : Operand<i32> {
243 let PrintMethod = "printi32mem";
244 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
245 let ParserMatchClass = X86MemAsmOperand;
248 def lea32mem : Operand<i32> {
249 let PrintMethod = "printlea32mem";
250 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
251 let ParserMatchClass = X86NoSegMemAsmOperand;
254 let ParserMatchClass = X86AbsMemAsmOperand,
255 PrintMethod = "print_pcrel_imm" in {
256 def i32imm_pcrel : Operand<i32>;
258 def offset8 : Operand<i64>;
259 def offset16 : Operand<i64>;
260 def offset32 : Operand<i64>;
261 def offset64 : Operand<i64>;
263 // Branch targets have OtherVT type and print as pc-relative values.
264 def brtarget : Operand<OtherVT>;
265 def brtarget8 : Operand<OtherVT>;
269 def SSECC : Operand<i8> {
270 let PrintMethod = "printSSECC";
273 def ImmSExt8AsmOperand : AsmOperandClass {
274 let Name = "ImmSExt8";
275 let SuperClass = ImmAsmOperand;
278 // A couple of more descriptive operand definitions.
279 // 16-bits but only 8 bits are significant.
280 def i16i8imm : Operand<i16> {
281 let ParserMatchClass = ImmSExt8AsmOperand;
283 // 32-bits but only 8 bits are significant.
284 def i32i8imm : Operand<i32> {
285 let ParserMatchClass = ImmSExt8AsmOperand;
288 //===----------------------------------------------------------------------===//
289 // X86 Complex Pattern Definitions.
292 // Define X86 specific addressing mode.
293 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
294 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
295 [add, sub, mul, X86mul_imm, shl, or, frameindex],
297 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
298 [tglobaltlsaddr], []>;
300 //===----------------------------------------------------------------------===//
301 // X86 Instruction Predicate Definitions.
302 def HasCMov : Predicate<"Subtarget->hasCMov()">;
303 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
304 def HasMMX : Predicate<"Subtarget->hasMMX()">;
305 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
306 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
307 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
308 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
309 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
310 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
311 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
312 def HasAVX : Predicate<"Subtarget->hasAVX()">;
313 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
314 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
315 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
316 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
317 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
318 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
319 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
320 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
321 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
322 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
323 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
324 "TM.getCodeModel() != CodeModel::Kernel">;
325 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
326 "TM.getCodeModel() == CodeModel::Kernel">;
327 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
328 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
329 def OptForSize : Predicate<"OptForSize">;
330 def OptForSpeed : Predicate<"!OptForSize">;
331 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
332 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
333 def HasAES : Predicate<"Subtarget->hasAES()">;
335 //===----------------------------------------------------------------------===//
336 // X86 Instruction Format Definitions.
339 include "X86InstrFormats.td"
341 //===----------------------------------------------------------------------===//
342 // Pattern fragments...
345 // X86 specific condition code. These correspond to CondCode in
346 // X86InstrInfo.h. They must be kept in synch.
347 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
348 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
349 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
350 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
351 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
352 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
353 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
354 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
355 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
356 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
357 def X86_COND_NO : PatLeaf<(i8 10)>;
358 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
359 def X86_COND_NS : PatLeaf<(i8 12)>;
360 def X86_COND_O : PatLeaf<(i8 13)>;
361 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
362 def X86_COND_S : PatLeaf<(i8 15)>;
364 def immSext8 : PatLeaf<(imm), [{
365 return N->getSExtValue() == (int8_t)N->getSExtValue();
368 def i16immSExt8 : PatLeaf<(i16 immSext8)>;
369 def i32immSExt8 : PatLeaf<(i32 immSext8)>;
371 /// Load patterns: these constraint the match to the right address space.
372 def dsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
373 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
374 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
375 if (PT->getAddressSpace() > 255)
380 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
381 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
382 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
383 return PT->getAddressSpace() == 256;
387 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
388 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
389 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
390 return PT->getAddressSpace() == 257;
395 // Helper fragments for loads.
396 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
397 // known to be 32-bit aligned or better. Ditto for i8 to i16.
398 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
399 LoadSDNode *LD = cast<LoadSDNode>(N);
400 if (const Value *Src = LD->getSrcValue())
401 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
402 if (PT->getAddressSpace() > 255)
404 ISD::LoadExtType ExtType = LD->getExtensionType();
405 if (ExtType == ISD::NON_EXTLOAD)
407 if (ExtType == ISD::EXTLOAD)
408 return LD->getAlignment() >= 2 && !LD->isVolatile();
412 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
413 LoadSDNode *LD = cast<LoadSDNode>(N);
414 if (const Value *Src = LD->getSrcValue())
415 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
416 if (PT->getAddressSpace() > 255)
418 ISD::LoadExtType ExtType = LD->getExtensionType();
419 if (ExtType == ISD::EXTLOAD)
420 return LD->getAlignment() >= 2 && !LD->isVolatile();
424 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
425 LoadSDNode *LD = cast<LoadSDNode>(N);
426 if (const Value *Src = LD->getSrcValue())
427 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
428 if (PT->getAddressSpace() > 255)
430 ISD::LoadExtType ExtType = LD->getExtensionType();
431 if (ExtType == ISD::NON_EXTLOAD)
433 if (ExtType == ISD::EXTLOAD)
434 return LD->getAlignment() >= 4 && !LD->isVolatile();
438 def loadi8 : PatFrag<(ops node:$ptr), (i8 (dsload node:$ptr))>;
439 def loadi64 : PatFrag<(ops node:$ptr), (i64 (dsload node:$ptr))>;
440 def loadf32 : PatFrag<(ops node:$ptr), (f32 (dsload node:$ptr))>;
441 def loadf64 : PatFrag<(ops node:$ptr), (f64 (dsload node:$ptr))>;
442 def loadf80 : PatFrag<(ops node:$ptr), (f80 (dsload node:$ptr))>;
444 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
445 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
446 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
448 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
449 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
450 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
451 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
452 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
453 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
455 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
456 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
457 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
458 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
459 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
460 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
463 // An 'and' node with a single use.
464 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
465 return N->hasOneUse();
467 // An 'srl' node with a single use.
468 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
469 return N->hasOneUse();
471 // An 'trunc' node with a single use.
472 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
473 return N->hasOneUse();
476 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
477 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
478 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
479 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
481 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
482 APInt Mask = APInt::getAllOnesValue(BitWidth);
483 APInt KnownZero0, KnownOne0;
484 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
485 APInt KnownZero1, KnownOne1;
486 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
487 return (~KnownZero0 & ~KnownZero1) == 0;
490 //===----------------------------------------------------------------------===//
491 // Instruction list...
494 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
495 // a stack adjustment and the codegen must know that they may modify the stack
496 // pointer before prolog-epilog rewriting occurs.
497 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
498 // sub / add which can clobber EFLAGS.
499 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
500 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
502 [(X86callseq_start timm:$amt)]>,
503 Requires<[In32BitMode]>;
504 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
506 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
507 Requires<[In32BitMode]>;
510 // x86-64 va_start lowering magic.
511 let usesCustomInserter = 1 in {
512 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
515 i64imm:$regsavefi, i64imm:$offset,
517 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
518 [(X86vastart_save_xmm_regs GR8:$al,
522 // Dynamic stack allocation yields _alloca call for Cygwin/Mingw targets. Calls
523 // to _alloca is needed to probe the stack when allocating more than 4k bytes in
524 // one go. Touching the stack at 4K increments is necessary to ensure that the
525 // guard pages used by the OS virtual memory manager are allocated in correct
527 // The main point of having separate instruction are extra unmodelled effects
528 // (compared to ordinary calls) like stack pointer change.
530 def MINGW_ALLOCA : I<0, Pseudo, (outs), (ins),
531 "# dynamic stack allocation",
536 let neverHasSideEffects = 1 in {
537 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
538 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
539 "nop{w}\t$zero", []>, TB, OpSize;
540 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
541 "nop{l}\t$zero", []>, TB;
545 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int\t3", []>;
546 def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
547 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize;
548 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>;
550 // PIC base construction. This expands to code that looks like this:
553 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
554 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
557 //===----------------------------------------------------------------------===//
558 // Control Flow Instructions.
561 // Return instructions.
562 let isTerminator = 1, isReturn = 1, isBarrier = 1,
563 hasCtrlDep = 1, FPForm = SpecialFP in {
564 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
567 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
569 [(X86retflag timm:$amt)]>;
570 def LRET : I <0xCB, RawFrm, (outs), (ins),
572 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
576 // Unconditional branches.
577 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
578 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
579 "jmp\t$dst", [(br bb:$dst)]>;
580 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
584 // Conditional Branches.
585 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
586 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
587 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
588 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
589 [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
593 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
594 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
595 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
596 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
597 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
598 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
599 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
600 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
601 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
602 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
603 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
604 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
605 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
606 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
607 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
608 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
610 // FIXME: What about the CX/RCX versions of this instruction?
611 let Uses = [ECX], isBranch = 1, isTerminator = 1 in
612 def JCXZ8 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
617 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
618 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
619 [(brind GR32:$dst)]>;
620 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
621 [(brind (loadi32 addr:$dst))]>;
623 def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
624 (ins i16imm:$seg, i16imm:$off),
625 "ljmp{w}\t$seg, $off", []>, OpSize;
626 def FARJMP32i : Iseg32<0xEA, RawFrm, (outs),
627 (ins i16imm:$seg, i32imm:$off),
628 "ljmp{l}\t$seg, $off", []>;
630 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
631 "ljmp{w}\t{*}$dst", []>, OpSize;
632 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
633 "ljmp{l}\t{*}$dst", []>;
639 def LOOP : I<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>;
640 def LOOPE : I<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>;
641 def LOOPNE : I<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>;
643 //===----------------------------------------------------------------------===//
644 // Call Instructions...
647 // All calls clobber the non-callee saved registers. ESP is marked as
648 // a use to prevent stack-pointer assignments that appear immediately
649 // before calls from potentially appearing dead. Uses for argument
650 // registers are added manually.
651 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
652 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
653 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
654 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
656 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
657 (outs), (ins i32imm_pcrel:$dst,variable_ops),
659 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
660 "call\t{*}$dst", [(X86call GR32:$dst)]>;
661 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
662 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
664 def FARCALL16i : Iseg16<0x9A, RawFrm, (outs),
665 (ins i16imm:$seg, i16imm:$off),
666 "lcall{w}\t$seg, $off", []>, OpSize;
667 def FARCALL32i : Iseg32<0x9A, RawFrm, (outs),
668 (ins i16imm:$seg, i32imm:$off),
669 "lcall{l}\t$seg, $off", []>;
671 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
672 "lcall{w}\t{*}$dst", []>, OpSize;
673 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
674 "lcall{l}\t{*}$dst", []>;
677 // Constructing a stack frame.
679 def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl),
680 "enter\t$len, $lvl", []>;
684 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
685 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
686 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
687 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
688 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
690 def TCRETURNdi : I<0, Pseudo, (outs),
691 (ins i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
692 "#TC_RETURN $dst $offset", []>;
693 def TCRETURNri : I<0, Pseudo, (outs),
694 (ins GR32_TC:$dst, i32imm:$offset, variable_ops),
695 "#TC_RETURN $dst $offset", []>;
696 def TCRETURNmi : I<0, Pseudo, (outs),
697 (ins i32mem_TC:$dst, i32imm:$offset, variable_ops),
698 "#TC_RETURN $dst $offset", []>;
700 // FIXME: The should be pseudo instructions that are lowered when going to
702 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
703 (ins i32imm_pcrel:$dst, variable_ops),
704 "jmp\t$dst # TAILCALL",
706 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops),
707 "jmp{l}\t{*}$dst # TAILCALL",
709 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops),
710 "jmp{l}\t{*}$dst # TAILCALL", []>;
713 //===----------------------------------------------------------------------===//
714 // Miscellaneous Instructions...
716 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
717 def LEAVE : I<0xC9, RawFrm,
718 (outs), (ins), "leave", []>;
720 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
721 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
722 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
723 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
724 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
725 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
726 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
727 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
729 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
731 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
733 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
734 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
736 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
738 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
739 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
742 let mayStore = 1 in {
743 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
745 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
746 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
748 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
750 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
751 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
755 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
756 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
757 "push{l}\t$imm", []>;
758 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
759 "push{w}\t$imm", []>, OpSize;
760 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
761 "push{l}\t$imm", []>;
764 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
765 def POPF : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
766 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf{l}", []>;
768 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
769 def PUSHF : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
770 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf{l}", []>;
773 let isTwoAddress = 1 in // GR32 = bswap GR32
774 def BSWAP32r : I<0xC8, AddRegFrm,
775 (outs GR32:$dst), (ins GR32:$src),
777 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
780 // Bit scan instructions.
781 let Defs = [EFLAGS] in {
782 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
783 "bsf{w}\t{$src, $dst|$dst, $src}",
784 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
785 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
786 "bsf{w}\t{$src, $dst|$dst, $src}",
787 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
789 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
790 "bsf{l}\t{$src, $dst|$dst, $src}",
791 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
792 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
793 "bsf{l}\t{$src, $dst|$dst, $src}",
794 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
796 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
797 "bsr{w}\t{$src, $dst|$dst, $src}",
798 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
799 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
800 "bsr{w}\t{$src, $dst|$dst, $src}",
801 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
803 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
804 "bsr{l}\t{$src, $dst|$dst, $src}",
805 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
806 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
807 "bsr{l}\t{$src, $dst|$dst, $src}",
808 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
811 let neverHasSideEffects = 1 in
812 def LEA16r : I<0x8D, MRMSrcMem,
813 (outs GR16:$dst), (ins lea32mem:$src),
814 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
815 let isReMaterializable = 1 in
816 def LEA32r : I<0x8D, MRMSrcMem,
817 (outs GR32:$dst), (ins lea32mem:$src),
818 "lea{l}\t{$src|$dst}, {$dst|$src}",
819 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
821 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
822 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
823 [(X86rep_movs i8)]>, REP;
824 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
825 [(X86rep_movs i16)]>, REP, OpSize;
826 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
827 [(X86rep_movs i32)]>, REP;
830 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
831 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
832 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
833 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
834 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
837 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
838 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
839 [(X86rep_stos i8)]>, REP;
840 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
841 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
842 [(X86rep_stos i16)]>, REP, OpSize;
843 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
844 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
845 [(X86rep_stos i32)]>, REP;
847 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
848 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
849 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
850 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
851 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
852 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
853 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
855 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
856 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
857 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
859 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
860 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
861 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
863 let Defs = [RAX, RDX] in
864 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
867 let Defs = [RAX, RCX, RDX] in
868 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
870 let isBarrier = 1, hasCtrlDep = 1 in {
871 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
874 def SYSCALL : I<0x05, RawFrm,
875 (outs), (ins), "syscall", []>, TB;
876 def SYSRET : I<0x07, RawFrm,
877 (outs), (ins), "sysret", []>, TB;
878 def SYSENTER : I<0x34, RawFrm,
879 (outs), (ins), "sysenter", []>, TB;
880 def SYSEXIT : I<0x35, RawFrm,
881 (outs), (ins), "sysexit", []>, TB;
883 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
886 //===----------------------------------------------------------------------===//
887 // Input/Output Instructions...
889 let Defs = [AL], Uses = [DX] in
890 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
891 "in{b}\t{%dx, %al|%AL, %DX}", []>;
892 let Defs = [AX], Uses = [DX] in
893 def IN16rr : I<0xED, RawFrm, (outs), (ins),
894 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
895 let Defs = [EAX], Uses = [DX] in
896 def IN32rr : I<0xED, RawFrm, (outs), (ins),
897 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
900 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
901 "in{b}\t{$port, %al|%AL, $port}", []>;
903 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
904 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
906 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
907 "in{l}\t{$port, %eax|%EAX, $port}", []>;
909 let Uses = [DX, AL] in
910 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
911 "out{b}\t{%al, %dx|%DX, %AL}", []>;
912 let Uses = [DX, AX] in
913 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
914 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
915 let Uses = [DX, EAX] in
916 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
917 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
920 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
921 "out{b}\t{%al, $port|$port, %AL}", []>;
923 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
924 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
926 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
927 "out{l}\t{%eax, $port|$port, %EAX}", []>;
929 def IN8 : I<0x6C, RawFrm, (outs), (ins),
931 def IN16 : I<0x6D, RawFrm, (outs), (ins),
932 "ins{w}", []>, OpSize;
933 def IN32 : I<0x6D, RawFrm, (outs), (ins),
936 //===----------------------------------------------------------------------===//
937 // Move Instructions...
939 let neverHasSideEffects = 1 in {
940 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
941 "mov{b}\t{$src, $dst|$dst, $src}", []>;
942 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
943 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
944 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
945 "mov{l}\t{$src, $dst|$dst, $src}", []>;
947 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
948 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
949 "mov{b}\t{$src, $dst|$dst, $src}",
950 [(set GR8:$dst, imm:$src)]>;
951 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
952 "mov{w}\t{$src, $dst|$dst, $src}",
953 [(set GR16:$dst, imm:$src)]>, OpSize;
954 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
955 "mov{l}\t{$src, $dst|$dst, $src}",
956 [(set GR32:$dst, imm:$src)]>;
959 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
960 "mov{b}\t{$src, $dst|$dst, $src}",
961 [(store (i8 imm:$src), addr:$dst)]>;
962 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
963 "mov{w}\t{$src, $dst|$dst, $src}",
964 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
965 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
966 "mov{l}\t{$src, $dst|$dst, $src}",
967 [(store (i32 imm:$src), addr:$dst)]>;
969 /// moffs8, moffs16, moffs32 and moffs64 versions of moves. The immediate is a
970 /// 32-bit offset from the PC.
971 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
972 "mov{b}\t{$src, %al|%al, $src}", []>;
973 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
974 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
975 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
976 "mov{l}\t{$src, %eax|%eax, $src}", []>;
977 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
978 "mov{b}\t{%al, $dst|$dst, %al}", []>;
979 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
980 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize;
981 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
982 "mov{l}\t{%eax, $dst|$dst, %eax}", []>;
984 // Moves to and from segment registers
985 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
986 "mov{w}\t{$src, $dst|$dst, $src}", []>;
987 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
988 "mov{w}\t{$src, $dst|$dst, $src}", []>;
989 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
990 "mov{w}\t{$src, $dst|$dst, $src}", []>;
991 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
992 "mov{w}\t{$src, $dst|$dst, $src}", []>;
994 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
995 "mov{b}\t{$src, $dst|$dst, $src}", []>;
996 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
997 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
998 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
999 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1001 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1002 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1003 "mov{b}\t{$src, $dst|$dst, $src}",
1004 [(set GR8:$dst, (loadi8 addr:$src))]>;
1005 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1006 "mov{w}\t{$src, $dst|$dst, $src}",
1007 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
1008 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1009 "mov{l}\t{$src, $dst|$dst, $src}",
1010 [(set GR32:$dst, (loadi32 addr:$src))]>;
1013 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1014 "mov{b}\t{$src, $dst|$dst, $src}",
1015 [(store GR8:$src, addr:$dst)]>;
1016 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1017 "mov{w}\t{$src, $dst|$dst, $src}",
1018 [(store GR16:$src, addr:$dst)]>, OpSize;
1019 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1020 "mov{l}\t{$src, $dst|$dst, $src}",
1021 [(store GR32:$src, addr:$dst)]>;
1023 /// Versions of MOV32rr, MOV32rm, and MOV32mr for i32mem_TC and GR32_TC.
1024 let neverHasSideEffects = 1 in
1025 def MOV32rr_TC : I<0x89, MRMDestReg, (outs GR32_TC:$dst), (ins GR32_TC:$src),
1026 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1029 canFoldAsLoad = 1, isReMaterializable = 1 in
1030 def MOV32rm_TC : I<0x8B, MRMSrcMem, (outs GR32_TC:$dst), (ins i32mem_TC:$src),
1031 "mov{l}\t{$src, $dst|$dst, $src}",
1035 def MOV32mr_TC : I<0x89, MRMDestMem, (outs), (ins i32mem_TC:$dst, GR32_TC:$src),
1036 "mov{l}\t{$src, $dst|$dst, $src}",
1039 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1040 // that they can be used for copying and storing h registers, which can't be
1041 // encoded when a REX prefix is present.
1042 let neverHasSideEffects = 1 in
1043 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1044 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1045 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1047 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1048 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1049 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1051 canFoldAsLoad = 1, isReMaterializable = 1 in
1052 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1053 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1054 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1056 // Moves to and from debug registers
1057 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
1058 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1059 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
1060 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1062 // Moves to and from control registers
1063 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
1064 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1065 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
1066 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1068 //===----------------------------------------------------------------------===//
1069 // Fixed-Register Multiplication and Division Instructions...
1072 // Extra precision multiplication
1074 // AL is really implied by AX, by the registers in Defs must match the
1075 // SDNode results (i8, i32).
1076 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1077 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
1078 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1079 // This probably ought to be moved to a def : Pat<> if the
1080 // syntax can be accepted.
1081 [(set AL, (mul AL, GR8:$src)),
1082 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1084 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1085 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1087 []>, OpSize; // AX,DX = AX*GR16
1089 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1090 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1092 []>; // EAX,EDX = EAX*GR32
1094 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1095 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1097 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1098 // This probably ought to be moved to a def : Pat<> if the
1099 // syntax can be accepted.
1100 [(set AL, (mul AL, (loadi8 addr:$src))),
1101 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1103 let mayLoad = 1, neverHasSideEffects = 1 in {
1104 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1105 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1107 []>, OpSize; // AX,DX = AX*[mem16]
1109 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1110 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1112 []>; // EAX,EDX = EAX*[mem32]
1115 let neverHasSideEffects = 1 in {
1116 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1117 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1119 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1120 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1121 OpSize; // AX,DX = AX*GR16
1122 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1123 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1124 // EAX,EDX = EAX*GR32
1125 let mayLoad = 1 in {
1126 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1127 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1128 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1129 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1130 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1131 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1132 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1133 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1134 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1136 } // neverHasSideEffects
1138 // unsigned division/remainder
1139 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1140 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1141 "div{b}\t$src", []>;
1142 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1143 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1144 "div{w}\t$src", []>, OpSize;
1145 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1146 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1147 "div{l}\t$src", []>;
1148 let mayLoad = 1 in {
1149 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1150 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1151 "div{b}\t$src", []>;
1152 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1153 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1154 "div{w}\t$src", []>, OpSize;
1155 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1156 // EDX:EAX/[mem32] = EAX,EDX
1157 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
1158 "div{l}\t$src", []>;
1161 // Signed division/remainder.
1162 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1163 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1164 "idiv{b}\t$src", []>;
1165 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1166 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1167 "idiv{w}\t$src", []>, OpSize;
1168 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1169 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1170 "idiv{l}\t$src", []>;
1171 let mayLoad = 1, mayLoad = 1 in {
1172 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1173 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1174 "idiv{b}\t$src", []>;
1175 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1176 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1177 "idiv{w}\t$src", []>, OpSize;
1178 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1179 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1180 // EDX:EAX/[mem32] = EAX,EDX
1181 "idiv{l}\t$src", []>;
1184 //===----------------------------------------------------------------------===//
1185 // Two address Instructions.
1187 let isTwoAddress = 1 in {
1189 // Conditional moves
1190 let Uses = [EFLAGS] in {
1192 let Predicates = [HasCMov] in {
1193 let isCommutable = 1 in {
1194 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1195 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1196 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1197 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1198 X86_COND_B, EFLAGS))]>,
1200 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1201 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1202 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1203 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1204 X86_COND_B, EFLAGS))]>,
1206 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1207 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1208 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1209 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1210 X86_COND_AE, EFLAGS))]>,
1212 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1213 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1214 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1215 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1216 X86_COND_AE, EFLAGS))]>,
1218 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1219 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1220 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1221 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1222 X86_COND_E, EFLAGS))]>,
1224 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1225 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1226 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1227 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1228 X86_COND_E, EFLAGS))]>,
1230 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1231 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1232 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1233 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1234 X86_COND_NE, EFLAGS))]>,
1236 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1237 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1238 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1239 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1240 X86_COND_NE, EFLAGS))]>,
1242 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1243 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1244 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1245 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1246 X86_COND_BE, EFLAGS))]>,
1248 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1249 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1250 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1251 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1252 X86_COND_BE, EFLAGS))]>,
1254 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1255 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1256 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1257 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1258 X86_COND_A, EFLAGS))]>,
1260 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1261 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1262 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1263 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1264 X86_COND_A, EFLAGS))]>,
1266 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1267 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1268 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1269 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1270 X86_COND_L, EFLAGS))]>,
1272 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1273 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1274 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1275 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1276 X86_COND_L, EFLAGS))]>,
1278 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1279 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1280 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1281 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1282 X86_COND_GE, EFLAGS))]>,
1284 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1285 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1286 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1287 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1288 X86_COND_GE, EFLAGS))]>,
1290 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1291 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1292 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1293 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1294 X86_COND_LE, EFLAGS))]>,
1296 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1297 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1298 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1299 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1300 X86_COND_LE, EFLAGS))]>,
1302 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1303 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1304 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1305 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1306 X86_COND_G, EFLAGS))]>,
1308 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1309 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1310 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1311 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1312 X86_COND_G, EFLAGS))]>,
1314 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1315 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1316 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1317 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1318 X86_COND_S, EFLAGS))]>,
1320 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1321 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1322 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1323 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1324 X86_COND_S, EFLAGS))]>,
1326 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1327 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1328 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1329 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1330 X86_COND_NS, EFLAGS))]>,
1332 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1333 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1334 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1335 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1336 X86_COND_NS, EFLAGS))]>,
1338 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1339 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1340 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1341 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1342 X86_COND_P, EFLAGS))]>,
1344 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1345 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1346 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1347 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1348 X86_COND_P, EFLAGS))]>,
1350 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1351 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1352 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1353 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1354 X86_COND_NP, EFLAGS))]>,
1356 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1357 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1358 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1359 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1360 X86_COND_NP, EFLAGS))]>,
1362 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1363 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1364 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1365 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1366 X86_COND_O, EFLAGS))]>,
1368 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1369 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1370 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1371 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1372 X86_COND_O, EFLAGS))]>,
1374 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1375 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1376 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1377 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1378 X86_COND_NO, EFLAGS))]>,
1380 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1381 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1382 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1383 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1384 X86_COND_NO, EFLAGS))]>,
1386 } // isCommutable = 1
1388 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1389 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1390 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1391 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1392 X86_COND_B, EFLAGS))]>,
1394 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1395 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1396 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1397 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1398 X86_COND_B, EFLAGS))]>,
1400 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1401 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1402 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1403 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1404 X86_COND_AE, EFLAGS))]>,
1406 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1407 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1408 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1409 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1410 X86_COND_AE, EFLAGS))]>,
1412 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1413 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1414 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1415 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1416 X86_COND_E, EFLAGS))]>,
1418 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1419 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1420 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1421 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1422 X86_COND_E, EFLAGS))]>,
1424 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1425 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1426 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1427 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1428 X86_COND_NE, EFLAGS))]>,
1430 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1431 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1432 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1433 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1434 X86_COND_NE, EFLAGS))]>,
1436 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1437 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1438 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1439 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1440 X86_COND_BE, EFLAGS))]>,
1442 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1443 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1444 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1445 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1446 X86_COND_BE, EFLAGS))]>,
1448 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1449 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1450 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1451 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1452 X86_COND_A, EFLAGS))]>,
1454 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1455 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1456 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1457 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1458 X86_COND_A, EFLAGS))]>,
1460 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1461 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1462 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1463 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1464 X86_COND_L, EFLAGS))]>,
1466 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1467 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1468 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1469 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1470 X86_COND_L, EFLAGS))]>,
1472 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1473 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1474 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1475 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1476 X86_COND_GE, EFLAGS))]>,
1478 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1479 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1480 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1481 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1482 X86_COND_GE, EFLAGS))]>,
1484 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1485 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1486 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1487 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1488 X86_COND_LE, EFLAGS))]>,
1490 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1491 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1492 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1493 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1494 X86_COND_LE, EFLAGS))]>,
1496 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1497 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1498 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1499 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1500 X86_COND_G, EFLAGS))]>,
1502 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1503 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1504 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1505 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1506 X86_COND_G, EFLAGS))]>,
1508 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1509 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1510 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1511 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1512 X86_COND_S, EFLAGS))]>,
1514 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1515 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1516 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1517 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1518 X86_COND_S, EFLAGS))]>,
1520 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1521 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1522 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1523 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1524 X86_COND_NS, EFLAGS))]>,
1526 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1527 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1528 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1529 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1530 X86_COND_NS, EFLAGS))]>,
1532 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1533 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1534 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1535 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1536 X86_COND_P, EFLAGS))]>,
1538 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1539 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1540 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1541 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1542 X86_COND_P, EFLAGS))]>,
1544 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1545 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1546 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1547 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1548 X86_COND_NP, EFLAGS))]>,
1550 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1551 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1552 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1553 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1554 X86_COND_NP, EFLAGS))]>,
1556 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1557 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1558 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1559 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1560 X86_COND_O, EFLAGS))]>,
1562 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1563 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1564 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1565 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1566 X86_COND_O, EFLAGS))]>,
1568 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1569 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1570 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1571 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1572 X86_COND_NO, EFLAGS))]>,
1574 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1575 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1576 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1577 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1578 X86_COND_NO, EFLAGS))]>,
1580 } // Predicates = [HasCMov]
1582 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1583 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1584 // however that requires promoting the operands, and can induce additional
1585 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1586 // clobber EFLAGS, because if one of the operands is zero, the expansion
1587 // could involve an xor.
1588 let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in {
1589 def CMOV_GR8 : I<0, Pseudo,
1590 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1591 "#CMOV_GR8 PSEUDO!",
1592 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1593 imm:$cond, EFLAGS))]>;
1595 let Predicates = [NoCMov] in {
1596 def CMOV_GR32 : I<0, Pseudo,
1597 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
1598 "#CMOV_GR32* PSEUDO!",
1600 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
1601 def CMOV_GR16 : I<0, Pseudo,
1602 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
1603 "#CMOV_GR16* PSEUDO!",
1605 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
1606 def CMOV_RFP32 : I<0, Pseudo,
1607 (outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
1608 "#CMOV_RFP32 PSEUDO!",
1609 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
1611 def CMOV_RFP64 : I<0, Pseudo,
1612 (outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
1613 "#CMOV_RFP64 PSEUDO!",
1614 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
1616 def CMOV_RFP80 : I<0, Pseudo,
1617 (outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
1618 "#CMOV_RFP80 PSEUDO!",
1619 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
1621 } // Predicates = [NoCMov]
1622 } // UsesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS]
1623 } // Uses = [EFLAGS]
1626 // unary instructions
1627 let CodeSize = 2 in {
1628 let Defs = [EFLAGS] in {
1629 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1630 [(set GR8:$dst, (ineg GR8:$src)),
1631 (implicit EFLAGS)]>;
1632 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1633 [(set GR16:$dst, (ineg GR16:$src)),
1634 (implicit EFLAGS)]>, OpSize;
1635 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1636 [(set GR32:$dst, (ineg GR32:$src)),
1637 (implicit EFLAGS)]>;
1638 let isTwoAddress = 0 in {
1639 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1640 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1641 (implicit EFLAGS)]>;
1642 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1643 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1644 (implicit EFLAGS)]>, OpSize;
1645 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1646 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1647 (implicit EFLAGS)]>;
1649 } // Defs = [EFLAGS]
1651 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1652 let AddedComplexity = 15 in {
1653 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1654 [(set GR8:$dst, (not GR8:$src))]>;
1655 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1656 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1657 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1658 [(set GR32:$dst, (not GR32:$src))]>;
1660 let isTwoAddress = 0 in {
1661 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1662 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1663 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1664 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1665 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1666 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1670 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1671 let Defs = [EFLAGS] in {
1673 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1674 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src))]>;
1676 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1677 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1679 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src))]>,
1680 OpSize, Requires<[In32BitMode]>;
1681 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1683 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src))]>,
1684 Requires<[In32BitMode]>;
1686 let isTwoAddress = 0, CodeSize = 2 in {
1687 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1688 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1689 (implicit EFLAGS)]>;
1690 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1691 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1692 (implicit EFLAGS)]>,
1693 OpSize, Requires<[In32BitMode]>;
1694 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1695 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1696 (implicit EFLAGS)]>,
1697 Requires<[In32BitMode]>;
1701 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1702 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src))]>;
1703 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1704 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1706 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src))]>,
1707 OpSize, Requires<[In32BitMode]>;
1708 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1710 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src))]>,
1711 Requires<[In32BitMode]>;
1714 let isTwoAddress = 0, CodeSize = 2 in {
1715 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1716 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1717 (implicit EFLAGS)]>;
1718 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1719 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1720 (implicit EFLAGS)]>,
1721 OpSize, Requires<[In32BitMode]>;
1722 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1723 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1724 (implicit EFLAGS)]>,
1725 Requires<[In32BitMode]>;
1727 } // Defs = [EFLAGS]
1729 // Logical operators...
1730 let Defs = [EFLAGS] in {
1731 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1732 def AND8rr : I<0x20, MRMDestReg,
1733 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1734 "and{b}\t{$src2, $dst|$dst, $src2}",
1735 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, GR8:$src2))]>;
1736 def AND16rr : I<0x21, MRMDestReg,
1737 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1738 "and{w}\t{$src2, $dst|$dst, $src2}",
1739 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1740 GR16:$src2))]>, OpSize;
1741 def AND32rr : I<0x21, MRMDestReg,
1742 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1743 "and{l}\t{$src2, $dst|$dst, $src2}",
1744 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1748 // AND instructions with the destination register in REG and the source register
1749 // in R/M. Included for the disassembler.
1750 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1751 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1752 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1753 (ins GR16:$src1, GR16:$src2),
1754 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1755 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1756 (ins GR32:$src1, GR32:$src2),
1757 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1759 def AND8rm : I<0x22, MRMSrcMem,
1760 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1761 "and{b}\t{$src2, $dst|$dst, $src2}",
1762 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1763 (loadi8 addr:$src2)))]>;
1764 def AND16rm : I<0x23, MRMSrcMem,
1765 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1766 "and{w}\t{$src2, $dst|$dst, $src2}",
1767 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1768 (loadi16 addr:$src2)))]>,
1770 def AND32rm : I<0x23, MRMSrcMem,
1771 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1772 "and{l}\t{$src2, $dst|$dst, $src2}",
1773 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1774 (loadi32 addr:$src2)))]>;
1776 def AND8ri : Ii8<0x80, MRM4r,
1777 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1778 "and{b}\t{$src2, $dst|$dst, $src2}",
1779 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1781 def AND16ri : Ii16<0x81, MRM4r,
1782 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1783 "and{w}\t{$src2, $dst|$dst, $src2}",
1784 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1785 imm:$src2))]>, OpSize;
1786 def AND32ri : Ii32<0x81, MRM4r,
1787 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1788 "and{l}\t{$src2, $dst|$dst, $src2}",
1789 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1791 def AND16ri8 : Ii8<0x83, MRM4r,
1792 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1793 "and{w}\t{$src2, $dst|$dst, $src2}",
1794 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1795 i16immSExt8:$src2))]>,
1797 def AND32ri8 : Ii8<0x83, MRM4r,
1798 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1799 "and{l}\t{$src2, $dst|$dst, $src2}",
1800 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1801 i32immSExt8:$src2))]>;
1803 let isTwoAddress = 0 in {
1804 def AND8mr : I<0x20, MRMDestMem,
1805 (outs), (ins i8mem :$dst, GR8 :$src),
1806 "and{b}\t{$src, $dst|$dst, $src}",
1807 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1808 (implicit EFLAGS)]>;
1809 def AND16mr : I<0x21, MRMDestMem,
1810 (outs), (ins i16mem:$dst, GR16:$src),
1811 "and{w}\t{$src, $dst|$dst, $src}",
1812 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1813 (implicit EFLAGS)]>,
1815 def AND32mr : I<0x21, MRMDestMem,
1816 (outs), (ins i32mem:$dst, GR32:$src),
1817 "and{l}\t{$src, $dst|$dst, $src}",
1818 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1819 (implicit EFLAGS)]>;
1820 def AND8mi : Ii8<0x80, MRM4m,
1821 (outs), (ins i8mem :$dst, i8imm :$src),
1822 "and{b}\t{$src, $dst|$dst, $src}",
1823 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1824 (implicit EFLAGS)]>;
1825 def AND16mi : Ii16<0x81, MRM4m,
1826 (outs), (ins i16mem:$dst, i16imm:$src),
1827 "and{w}\t{$src, $dst|$dst, $src}",
1828 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1829 (implicit EFLAGS)]>,
1831 def AND32mi : Ii32<0x81, MRM4m,
1832 (outs), (ins i32mem:$dst, i32imm:$src),
1833 "and{l}\t{$src, $dst|$dst, $src}",
1834 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1835 (implicit EFLAGS)]>;
1836 def AND16mi8 : Ii8<0x83, MRM4m,
1837 (outs), (ins i16mem:$dst, i16i8imm :$src),
1838 "and{w}\t{$src, $dst|$dst, $src}",
1839 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1840 (implicit EFLAGS)]>,
1842 def AND32mi8 : Ii8<0x83, MRM4m,
1843 (outs), (ins i32mem:$dst, i32i8imm :$src),
1844 "and{l}\t{$src, $dst|$dst, $src}",
1845 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1846 (implicit EFLAGS)]>;
1848 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1849 "and{b}\t{$src, %al|%al, $src}", []>;
1850 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1851 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1852 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1853 "and{l}\t{$src, %eax|%eax, $src}", []>;
1858 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1859 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1860 (ins GR8 :$src1, GR8 :$src2),
1861 "or{b}\t{$src2, $dst|$dst, $src2}",
1862 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
1863 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1864 (ins GR16:$src1, GR16:$src2),
1865 "or{w}\t{$src2, $dst|$dst, $src2}",
1866 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
1868 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1869 (ins GR32:$src1, GR32:$src2),
1870 "or{l}\t{$src2, $dst|$dst, $src2}",
1871 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
1874 // OR instructions with the destination register in REG and the source register
1875 // in R/M. Included for the disassembler.
1876 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1877 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1878 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1879 (ins GR16:$src1, GR16:$src2),
1880 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1881 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1882 (ins GR32:$src1, GR32:$src2),
1883 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
1885 def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst),
1886 (ins GR8 :$src1, i8mem :$src2),
1887 "or{b}\t{$src2, $dst|$dst, $src2}",
1888 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
1889 (load addr:$src2)))]>;
1890 def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst),
1891 (ins GR16:$src1, i16mem:$src2),
1892 "or{w}\t{$src2, $dst|$dst, $src2}",
1893 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1894 (load addr:$src2)))]>,
1896 def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst),
1897 (ins GR32:$src1, i32mem:$src2),
1898 "or{l}\t{$src2, $dst|$dst, $src2}",
1899 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1900 (load addr:$src2)))]>;
1902 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
1903 (ins GR8 :$src1, i8imm:$src2),
1904 "or{b}\t{$src2, $dst|$dst, $src2}",
1905 [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
1906 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
1907 (ins GR16:$src1, i16imm:$src2),
1908 "or{w}\t{$src2, $dst|$dst, $src2}",
1909 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1910 imm:$src2))]>, OpSize;
1911 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
1912 (ins GR32:$src1, i32imm:$src2),
1913 "or{l}\t{$src2, $dst|$dst, $src2}",
1914 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1917 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
1918 (ins GR16:$src1, i16i8imm:$src2),
1919 "or{w}\t{$src2, $dst|$dst, $src2}",
1920 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1921 i16immSExt8:$src2))]>, OpSize;
1922 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
1923 (ins GR32:$src1, i32i8imm:$src2),
1924 "or{l}\t{$src2, $dst|$dst, $src2}",
1925 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1926 i32immSExt8:$src2))]>;
1927 let isTwoAddress = 0 in {
1928 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1929 "or{b}\t{$src, $dst|$dst, $src}",
1930 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1931 (implicit EFLAGS)]>;
1932 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1933 "or{w}\t{$src, $dst|$dst, $src}",
1934 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1935 (implicit EFLAGS)]>, OpSize;
1936 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1937 "or{l}\t{$src, $dst|$dst, $src}",
1938 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1939 (implicit EFLAGS)]>;
1940 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1941 "or{b}\t{$src, $dst|$dst, $src}",
1942 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1943 (implicit EFLAGS)]>;
1944 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1945 "or{w}\t{$src, $dst|$dst, $src}",
1946 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1947 (implicit EFLAGS)]>,
1949 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1950 "or{l}\t{$src, $dst|$dst, $src}",
1951 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1952 (implicit EFLAGS)]>;
1953 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1954 "or{w}\t{$src, $dst|$dst, $src}",
1955 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1956 (implicit EFLAGS)]>,
1958 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1959 "or{l}\t{$src, $dst|$dst, $src}",
1960 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1961 (implicit EFLAGS)]>;
1963 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
1964 "or{b}\t{$src, %al|%al, $src}", []>;
1965 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
1966 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1967 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
1968 "or{l}\t{$src, %eax|%eax, $src}", []>;
1969 } // isTwoAddress = 0
1972 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1973 def XOR8rr : I<0x30, MRMDestReg,
1974 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1975 "xor{b}\t{$src2, $dst|$dst, $src2}",
1976 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
1978 def XOR16rr : I<0x31, MRMDestReg,
1979 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1980 "xor{w}\t{$src2, $dst|$dst, $src2}",
1981 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
1982 GR16:$src2))]>, OpSize;
1983 def XOR32rr : I<0x31, MRMDestReg,
1984 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1985 "xor{l}\t{$src2, $dst|$dst, $src2}",
1986 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
1988 } // isCommutable = 1
1990 // XOR instructions with the destination register in REG and the source register
1991 // in R/M. Included for the disassembler.
1992 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1993 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
1994 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
1995 (ins GR16:$src1, GR16:$src2),
1996 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1997 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
1998 (ins GR32:$src1, GR32:$src2),
1999 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
2001 def XOR8rm : I<0x32, MRMSrcMem,
2002 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
2003 "xor{b}\t{$src2, $dst|$dst, $src2}",
2004 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2005 (load addr:$src2)))]>;
2006 def XOR16rm : I<0x33, MRMSrcMem,
2007 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2008 "xor{w}\t{$src2, $dst|$dst, $src2}",
2009 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2010 (load addr:$src2)))]>,
2012 def XOR32rm : I<0x33, MRMSrcMem,
2013 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2014 "xor{l}\t{$src2, $dst|$dst, $src2}",
2015 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2016 (load addr:$src2)))]>;
2018 def XOR8ri : Ii8<0x80, MRM6r,
2019 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2020 "xor{b}\t{$src2, $dst|$dst, $src2}",
2021 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
2022 def XOR16ri : Ii16<0x81, MRM6r,
2023 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2024 "xor{w}\t{$src2, $dst|$dst, $src2}",
2025 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2026 imm:$src2))]>, OpSize;
2027 def XOR32ri : Ii32<0x81, MRM6r,
2028 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2029 "xor{l}\t{$src2, $dst|$dst, $src2}",
2030 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2032 def XOR16ri8 : Ii8<0x83, MRM6r,
2033 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2034 "xor{w}\t{$src2, $dst|$dst, $src2}",
2035 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2036 i16immSExt8:$src2))]>,
2038 def XOR32ri8 : Ii8<0x83, MRM6r,
2039 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2040 "xor{l}\t{$src2, $dst|$dst, $src2}",
2041 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2042 i32immSExt8:$src2))]>;
2044 let isTwoAddress = 0 in {
2045 def XOR8mr : I<0x30, MRMDestMem,
2046 (outs), (ins i8mem :$dst, GR8 :$src),
2047 "xor{b}\t{$src, $dst|$dst, $src}",
2048 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
2049 (implicit EFLAGS)]>;
2050 def XOR16mr : I<0x31, MRMDestMem,
2051 (outs), (ins i16mem:$dst, GR16:$src),
2052 "xor{w}\t{$src, $dst|$dst, $src}",
2053 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
2054 (implicit EFLAGS)]>,
2056 def XOR32mr : I<0x31, MRMDestMem,
2057 (outs), (ins i32mem:$dst, GR32:$src),
2058 "xor{l}\t{$src, $dst|$dst, $src}",
2059 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
2060 (implicit EFLAGS)]>;
2061 def XOR8mi : Ii8<0x80, MRM6m,
2062 (outs), (ins i8mem :$dst, i8imm :$src),
2063 "xor{b}\t{$src, $dst|$dst, $src}",
2064 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
2065 (implicit EFLAGS)]>;
2066 def XOR16mi : Ii16<0x81, MRM6m,
2067 (outs), (ins i16mem:$dst, i16imm:$src),
2068 "xor{w}\t{$src, $dst|$dst, $src}",
2069 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
2070 (implicit EFLAGS)]>,
2072 def XOR32mi : Ii32<0x81, MRM6m,
2073 (outs), (ins i32mem:$dst, i32imm:$src),
2074 "xor{l}\t{$src, $dst|$dst, $src}",
2075 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
2076 (implicit EFLAGS)]>;
2077 def XOR16mi8 : Ii8<0x83, MRM6m,
2078 (outs), (ins i16mem:$dst, i16i8imm :$src),
2079 "xor{w}\t{$src, $dst|$dst, $src}",
2080 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
2081 (implicit EFLAGS)]>,
2083 def XOR32mi8 : Ii8<0x83, MRM6m,
2084 (outs), (ins i32mem:$dst, i32i8imm :$src),
2085 "xor{l}\t{$src, $dst|$dst, $src}",
2086 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
2087 (implicit EFLAGS)]>;
2089 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
2090 "xor{b}\t{$src, %al|%al, $src}", []>;
2091 def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
2092 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2093 def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
2094 "xor{l}\t{$src, %eax|%eax, $src}", []>;
2095 } // isTwoAddress = 0
2096 } // Defs = [EFLAGS]
2098 // Shift instructions
2099 let Defs = [EFLAGS] in {
2100 let Uses = [CL] in {
2101 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
2102 "shl{b}\t{%cl, $dst|$dst, CL}",
2103 [(set GR8:$dst, (shl GR8:$src, CL))]>;
2104 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
2105 "shl{w}\t{%cl, $dst|$dst, CL}",
2106 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
2107 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
2108 "shl{l}\t{%cl, $dst|$dst, CL}",
2109 [(set GR32:$dst, (shl GR32:$src, CL))]>;
2112 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2113 "shl{b}\t{$src2, $dst|$dst, $src2}",
2114 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
2115 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2116 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2117 "shl{w}\t{$src2, $dst|$dst, $src2}",
2118 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2119 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2120 "shl{l}\t{$src2, $dst|$dst, $src2}",
2121 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
2123 // NOTE: We don't include patterns for shifts of a register by one, because
2124 // 'add reg,reg' is cheaper.
2126 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
2127 "shl{b}\t$dst", []>;
2128 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2129 "shl{w}\t$dst", []>, OpSize;
2130 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2131 "shl{l}\t$dst", []>;
2133 } // isConvertibleToThreeAddress = 1
2135 let isTwoAddress = 0 in {
2136 let Uses = [CL] in {
2137 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
2138 "shl{b}\t{%cl, $dst|$dst, CL}",
2139 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
2140 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
2141 "shl{w}\t{%cl, $dst|$dst, CL}",
2142 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2143 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
2144 "shl{l}\t{%cl, $dst|$dst, CL}",
2145 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
2147 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
2148 "shl{b}\t{$src, $dst|$dst, $src}",
2149 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2150 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
2151 "shl{w}\t{$src, $dst|$dst, $src}",
2152 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2154 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
2155 "shl{l}\t{$src, $dst|$dst, $src}",
2156 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2159 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
2161 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2162 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
2164 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2166 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2168 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2171 let Uses = [CL] in {
2172 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
2173 "shr{b}\t{%cl, $dst|$dst, CL}",
2174 [(set GR8:$dst, (srl GR8:$src, CL))]>;
2175 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
2176 "shr{w}\t{%cl, $dst|$dst, CL}",
2177 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
2178 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
2179 "shr{l}\t{%cl, $dst|$dst, CL}",
2180 [(set GR32:$dst, (srl GR32:$src, CL))]>;
2183 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2184 "shr{b}\t{$src2, $dst|$dst, $src2}",
2185 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2186 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2187 "shr{w}\t{$src2, $dst|$dst, $src2}",
2188 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2189 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2190 "shr{l}\t{$src2, $dst|$dst, $src2}",
2191 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2194 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2196 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2197 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2199 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2200 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2202 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2204 let isTwoAddress = 0 in {
2205 let Uses = [CL] in {
2206 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2207 "shr{b}\t{%cl, $dst|$dst, CL}",
2208 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2209 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2210 "shr{w}\t{%cl, $dst|$dst, CL}",
2211 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2213 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2214 "shr{l}\t{%cl, $dst|$dst, CL}",
2215 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2217 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2218 "shr{b}\t{$src, $dst|$dst, $src}",
2219 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2220 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2221 "shr{w}\t{$src, $dst|$dst, $src}",
2222 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2224 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2225 "shr{l}\t{$src, $dst|$dst, $src}",
2226 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2229 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2231 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2232 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2234 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2235 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2237 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2240 let Uses = [CL] in {
2241 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
2242 "sar{b}\t{%cl, $dst|$dst, CL}",
2243 [(set GR8:$dst, (sra GR8:$src, CL))]>;
2244 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
2245 "sar{w}\t{%cl, $dst|$dst, CL}",
2246 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
2247 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
2248 "sar{l}\t{%cl, $dst|$dst, CL}",
2249 [(set GR32:$dst, (sra GR32:$src, CL))]>;
2252 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2253 "sar{b}\t{$src2, $dst|$dst, $src2}",
2254 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2255 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2256 "sar{w}\t{$src2, $dst|$dst, $src2}",
2257 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2259 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2260 "sar{l}\t{$src2, $dst|$dst, $src2}",
2261 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2264 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2266 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2267 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2269 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2270 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2272 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2274 let isTwoAddress = 0 in {
2275 let Uses = [CL] in {
2276 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2277 "sar{b}\t{%cl, $dst|$dst, CL}",
2278 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2279 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2280 "sar{w}\t{%cl, $dst|$dst, CL}",
2281 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2282 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2283 "sar{l}\t{%cl, $dst|$dst, CL}",
2284 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2286 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2287 "sar{b}\t{$src, $dst|$dst, $src}",
2288 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2289 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2290 "sar{w}\t{$src, $dst|$dst, $src}",
2291 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2293 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2294 "sar{l}\t{$src, $dst|$dst, $src}",
2295 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2298 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2300 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2301 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2303 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2305 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2307 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2310 // Rotate instructions
2312 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2313 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2314 let Uses = [CL] in {
2315 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2316 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2318 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2319 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2321 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2322 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2323 let Uses = [CL] in {
2324 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2325 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2327 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2328 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2330 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2331 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2332 let Uses = [CL] in {
2333 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2334 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2336 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2337 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2339 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2340 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2341 let Uses = [CL] in {
2342 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2343 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2345 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2346 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2348 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2349 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2350 let Uses = [CL] in {
2351 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2352 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2354 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2355 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2357 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2358 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2359 let Uses = [CL] in {
2360 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2361 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2363 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2364 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2366 let isTwoAddress = 0 in {
2367 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
2368 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2369 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2370 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2371 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
2372 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2373 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2374 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2375 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
2376 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2377 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2378 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2379 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
2380 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2381 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2382 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2383 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
2384 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2385 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2386 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2387 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
2388 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2389 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2390 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2392 let Uses = [CL] in {
2393 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
2394 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2395 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
2396 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2397 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
2398 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2399 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
2400 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2401 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
2402 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2403 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
2404 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2408 // FIXME: provide shorter instructions when imm8 == 1
2409 let Uses = [CL] in {
2410 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
2411 "rol{b}\t{%cl, $dst|$dst, CL}",
2412 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
2413 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
2414 "rol{w}\t{%cl, $dst|$dst, CL}",
2415 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
2416 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
2417 "rol{l}\t{%cl, $dst|$dst, CL}",
2418 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2421 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2422 "rol{b}\t{$src2, $dst|$dst, $src2}",
2423 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2424 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2425 "rol{w}\t{$src2, $dst|$dst, $src2}",
2426 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2428 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2429 "rol{l}\t{$src2, $dst|$dst, $src2}",
2430 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2433 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2435 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2436 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2438 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2439 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2441 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2443 let isTwoAddress = 0 in {
2444 let Uses = [CL] in {
2445 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2446 "rol{b}\t{%cl, $dst|$dst, CL}",
2447 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2448 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2449 "rol{w}\t{%cl, $dst|$dst, CL}",
2450 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2451 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2452 "rol{l}\t{%cl, $dst|$dst, CL}",
2453 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2455 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2456 "rol{b}\t{$src, $dst|$dst, $src}",
2457 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2458 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2459 "rol{w}\t{$src, $dst|$dst, $src}",
2460 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2462 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2463 "rol{l}\t{$src, $dst|$dst, $src}",
2464 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2467 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2469 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2470 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2472 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2474 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2476 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2479 let Uses = [CL] in {
2480 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2481 "ror{b}\t{%cl, $dst|$dst, CL}",
2482 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2483 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2484 "ror{w}\t{%cl, $dst|$dst, CL}",
2485 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2486 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2487 "ror{l}\t{%cl, $dst|$dst, CL}",
2488 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2491 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2492 "ror{b}\t{$src2, $dst|$dst, $src2}",
2493 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2494 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2495 "ror{w}\t{$src2, $dst|$dst, $src2}",
2496 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2498 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2499 "ror{l}\t{$src2, $dst|$dst, $src2}",
2500 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2503 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2505 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2506 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2508 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2509 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2511 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2513 let isTwoAddress = 0 in {
2514 let Uses = [CL] in {
2515 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2516 "ror{b}\t{%cl, $dst|$dst, CL}",
2517 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2518 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2519 "ror{w}\t{%cl, $dst|$dst, CL}",
2520 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2521 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2522 "ror{l}\t{%cl, $dst|$dst, CL}",
2523 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2525 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2526 "ror{b}\t{$src, $dst|$dst, $src}",
2527 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2528 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2529 "ror{w}\t{$src, $dst|$dst, $src}",
2530 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2532 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2533 "ror{l}\t{$src, $dst|$dst, $src}",
2534 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2537 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2539 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2540 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2542 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2544 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2546 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2551 // Double shift instructions (generalizations of rotate)
2552 let Uses = [CL] in {
2553 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2554 (ins GR32:$src1, GR32:$src2),
2555 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2556 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2557 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2558 (ins GR32:$src1, GR32:$src2),
2559 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2560 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2561 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2562 (ins GR16:$src1, GR16:$src2),
2563 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2564 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2566 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2567 (ins GR16:$src1, GR16:$src2),
2568 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2569 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2573 let isCommutable = 1 in { // These instructions commute to each other.
2574 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2576 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2577 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2578 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2581 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2583 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2584 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2585 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2588 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2590 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2591 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2592 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2595 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2597 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2598 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2599 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2604 let isTwoAddress = 0 in {
2605 let Uses = [CL] in {
2606 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2607 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2608 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2610 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2611 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2612 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2615 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2616 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2617 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2618 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2619 (i8 imm:$src3)), addr:$dst)]>,
2621 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2622 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2623 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2624 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2625 (i8 imm:$src3)), addr:$dst)]>,
2628 let Uses = [CL] in {
2629 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2630 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2631 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2632 addr:$dst)]>, TB, OpSize;
2633 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2634 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2635 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2636 addr:$dst)]>, TB, OpSize;
2638 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2639 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2640 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2641 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2642 (i8 imm:$src3)), addr:$dst)]>,
2644 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2645 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2646 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2647 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2648 (i8 imm:$src3)), addr:$dst)]>,
2651 } // Defs = [EFLAGS]
2655 let Defs = [EFLAGS] in {
2656 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2657 // Register-Register Addition
2658 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2659 (ins GR8 :$src1, GR8 :$src2),
2660 "add{b}\t{$src2, $dst|$dst, $src2}",
2661 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
2663 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2664 // Register-Register Addition
2665 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2666 (ins GR16:$src1, GR16:$src2),
2667 "add{w}\t{$src2, $dst|$dst, $src2}",
2668 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2669 GR16:$src2))]>, OpSize;
2670 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2671 (ins GR32:$src1, GR32:$src2),
2672 "add{l}\t{$src2, $dst|$dst, $src2}",
2673 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2675 } // end isConvertibleToThreeAddress
2676 } // end isCommutable
2678 // These are alternate spellings for use by the disassembler, we mark them as
2679 // code gen only to ensure they aren't matched by the assembler.
2680 let isCodeGenOnly = 1 in {
2681 def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2682 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2683 def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2684 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2685 def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR32:$dst),(ins GR32:$src1, GR32:$src2),
2686 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2689 // Register-Memory Addition
2690 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2691 (ins GR8 :$src1, i8mem :$src2),
2692 "add{b}\t{$src2, $dst|$dst, $src2}",
2693 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
2694 (load addr:$src2)))]>;
2695 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2696 (ins GR16:$src1, i16mem:$src2),
2697 "add{w}\t{$src2, $dst|$dst, $src2}",
2698 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2699 (load addr:$src2)))]>, OpSize;
2700 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2701 (ins GR32:$src1, i32mem:$src2),
2702 "add{l}\t{$src2, $dst|$dst, $src2}",
2703 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2704 (load addr:$src2)))]>;
2706 // Register-Integer Addition
2707 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2708 "add{b}\t{$src2, $dst|$dst, $src2}",
2709 [(set GR8:$dst, EFLAGS,
2710 (X86add_flag GR8:$src1, imm:$src2))]>;
2712 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2713 // Register-Integer Addition
2714 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2715 (ins GR16:$src1, i16imm:$src2),
2716 "add{w}\t{$src2, $dst|$dst, $src2}",
2717 [(set GR16:$dst, EFLAGS,
2718 (X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
2719 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2720 (ins GR32:$src1, i32imm:$src2),
2721 "add{l}\t{$src2, $dst|$dst, $src2}",
2722 [(set GR32:$dst, EFLAGS,
2723 (X86add_flag GR32:$src1, imm:$src2))]>;
2724 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2725 (ins GR16:$src1, i16i8imm:$src2),
2726 "add{w}\t{$src2, $dst|$dst, $src2}",
2727 [(set GR16:$dst, EFLAGS,
2728 (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2729 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2730 (ins GR32:$src1, i32i8imm:$src2),
2731 "add{l}\t{$src2, $dst|$dst, $src2}",
2732 [(set GR32:$dst, EFLAGS,
2733 (X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
2736 let isTwoAddress = 0 in {
2737 // Memory-Register Addition
2738 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2739 "add{b}\t{$src2, $dst|$dst, $src2}",
2740 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2741 (implicit EFLAGS)]>;
2742 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2743 "add{w}\t{$src2, $dst|$dst, $src2}",
2744 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2745 (implicit EFLAGS)]>, OpSize;
2746 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2747 "add{l}\t{$src2, $dst|$dst, $src2}",
2748 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2749 (implicit EFLAGS)]>;
2750 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2751 "add{b}\t{$src2, $dst|$dst, $src2}",
2752 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2753 (implicit EFLAGS)]>;
2754 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2755 "add{w}\t{$src2, $dst|$dst, $src2}",
2756 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2757 (implicit EFLAGS)]>, OpSize;
2758 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2759 "add{l}\t{$src2, $dst|$dst, $src2}",
2760 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2761 (implicit EFLAGS)]>;
2762 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2763 "add{w}\t{$src2, $dst|$dst, $src2}",
2764 [(store (add (load addr:$dst), i16immSExt8:$src2),
2766 (implicit EFLAGS)]>, OpSize;
2767 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2768 "add{l}\t{$src2, $dst|$dst, $src2}",
2769 [(store (add (load addr:$dst), i32immSExt8:$src2),
2771 (implicit EFLAGS)]>;
2774 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2775 "add{b}\t{$src, %al|%al, $src}", []>;
2776 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2777 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2778 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2779 "add{l}\t{$src, %eax|%eax, $src}", []>;
2782 let Uses = [EFLAGS] in {
2783 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2784 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2785 "adc{b}\t{$src2, $dst|$dst, $src2}",
2786 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2787 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2788 (ins GR16:$src1, GR16:$src2),
2789 "adc{w}\t{$src2, $dst|$dst, $src2}",
2790 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2791 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2792 (ins GR32:$src1, GR32:$src2),
2793 "adc{l}\t{$src2, $dst|$dst, $src2}",
2794 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2797 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2798 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2799 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2800 (ins GR16:$src1, GR16:$src2),
2801 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2802 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2803 (ins GR32:$src1, GR32:$src2),
2804 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2806 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2807 (ins GR8:$src1, i8mem:$src2),
2808 "adc{b}\t{$src2, $dst|$dst, $src2}",
2809 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2810 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2811 (ins GR16:$src1, i16mem:$src2),
2812 "adc{w}\t{$src2, $dst|$dst, $src2}",
2813 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2815 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2816 (ins GR32:$src1, i32mem:$src2),
2817 "adc{l}\t{$src2, $dst|$dst, $src2}",
2818 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2819 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2820 "adc{b}\t{$src2, $dst|$dst, $src2}",
2821 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2822 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2823 (ins GR16:$src1, i16imm:$src2),
2824 "adc{w}\t{$src2, $dst|$dst, $src2}",
2825 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2826 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2827 (ins GR16:$src1, i16i8imm:$src2),
2828 "adc{w}\t{$src2, $dst|$dst, $src2}",
2829 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2831 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2832 (ins GR32:$src1, i32imm:$src2),
2833 "adc{l}\t{$src2, $dst|$dst, $src2}",
2834 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2835 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2836 (ins GR32:$src1, i32i8imm:$src2),
2837 "adc{l}\t{$src2, $dst|$dst, $src2}",
2838 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2840 let isTwoAddress = 0 in {
2841 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2842 "adc{b}\t{$src2, $dst|$dst, $src2}",
2843 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2844 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2845 "adc{w}\t{$src2, $dst|$dst, $src2}",
2846 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2848 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2849 "adc{l}\t{$src2, $dst|$dst, $src2}",
2850 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2851 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2852 "adc{b}\t{$src2, $dst|$dst, $src2}",
2853 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2854 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2855 "adc{w}\t{$src2, $dst|$dst, $src2}",
2856 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2858 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2859 "adc{w}\t{$src2, $dst|$dst, $src2}",
2860 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2862 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2863 "adc{l}\t{$src2, $dst|$dst, $src2}",
2864 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2865 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2866 "adc{l}\t{$src2, $dst|$dst, $src2}",
2867 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2869 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2870 "adc{b}\t{$src, %al|%al, $src}", []>;
2871 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2872 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2873 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2874 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2876 } // Uses = [EFLAGS]
2878 // Register-Register Subtraction
2879 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2880 "sub{b}\t{$src2, $dst|$dst, $src2}",
2881 [(set GR8:$dst, EFLAGS,
2882 (X86sub_flag GR8:$src1, GR8:$src2))]>;
2883 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2884 "sub{w}\t{$src2, $dst|$dst, $src2}",
2885 [(set GR16:$dst, EFLAGS,
2886 (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
2887 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2888 "sub{l}\t{$src2, $dst|$dst, $src2}",
2889 [(set GR32:$dst, EFLAGS,
2890 (X86sub_flag GR32:$src1, GR32:$src2))]>;
2892 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2893 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
2894 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
2895 (ins GR16:$src1, GR16:$src2),
2896 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2897 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
2898 (ins GR32:$src1, GR32:$src2),
2899 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
2901 // Register-Memory Subtraction
2902 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2903 (ins GR8 :$src1, i8mem :$src2),
2904 "sub{b}\t{$src2, $dst|$dst, $src2}",
2905 [(set GR8:$dst, EFLAGS,
2906 (X86sub_flag GR8:$src1, (load addr:$src2)))]>;
2907 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2908 (ins GR16:$src1, i16mem:$src2),
2909 "sub{w}\t{$src2, $dst|$dst, $src2}",
2910 [(set GR16:$dst, EFLAGS,
2911 (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
2912 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2913 (ins GR32:$src1, i32mem:$src2),
2914 "sub{l}\t{$src2, $dst|$dst, $src2}",
2915 [(set GR32:$dst, EFLAGS,
2916 (X86sub_flag GR32:$src1, (load addr:$src2)))]>;
2918 // Register-Integer Subtraction
2919 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2920 (ins GR8:$src1, i8imm:$src2),
2921 "sub{b}\t{$src2, $dst|$dst, $src2}",
2922 [(set GR8:$dst, EFLAGS,
2923 (X86sub_flag GR8:$src1, imm:$src2))]>;
2924 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2925 (ins GR16:$src1, i16imm:$src2),
2926 "sub{w}\t{$src2, $dst|$dst, $src2}",
2927 [(set GR16:$dst, EFLAGS,
2928 (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
2929 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2930 (ins GR32:$src1, i32imm:$src2),
2931 "sub{l}\t{$src2, $dst|$dst, $src2}",
2932 [(set GR32:$dst, EFLAGS,
2933 (X86sub_flag GR32:$src1, imm:$src2))]>;
2934 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2935 (ins GR16:$src1, i16i8imm:$src2),
2936 "sub{w}\t{$src2, $dst|$dst, $src2}",
2937 [(set GR16:$dst, EFLAGS,
2938 (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2939 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2940 (ins GR32:$src1, i32i8imm:$src2),
2941 "sub{l}\t{$src2, $dst|$dst, $src2}",
2942 [(set GR32:$dst, EFLAGS,
2943 (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
2945 let isTwoAddress = 0 in {
2946 // Memory-Register Subtraction
2947 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2948 "sub{b}\t{$src2, $dst|$dst, $src2}",
2949 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2950 (implicit EFLAGS)]>;
2951 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2952 "sub{w}\t{$src2, $dst|$dst, $src2}",
2953 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2954 (implicit EFLAGS)]>, OpSize;
2955 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2956 "sub{l}\t{$src2, $dst|$dst, $src2}",
2957 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2958 (implicit EFLAGS)]>;
2960 // Memory-Integer Subtraction
2961 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2962 "sub{b}\t{$src2, $dst|$dst, $src2}",
2963 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2964 (implicit EFLAGS)]>;
2965 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2966 "sub{w}\t{$src2, $dst|$dst, $src2}",
2967 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2968 (implicit EFLAGS)]>, OpSize;
2969 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2970 "sub{l}\t{$src2, $dst|$dst, $src2}",
2971 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2972 (implicit EFLAGS)]>;
2973 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2974 "sub{w}\t{$src2, $dst|$dst, $src2}",
2975 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2977 (implicit EFLAGS)]>, OpSize;
2978 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2979 "sub{l}\t{$src2, $dst|$dst, $src2}",
2980 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2982 (implicit EFLAGS)]>;
2984 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
2985 "sub{b}\t{$src, %al|%al, $src}", []>;
2986 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
2987 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2988 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
2989 "sub{l}\t{$src, %eax|%eax, $src}", []>;
2992 let Uses = [EFLAGS] in {
2993 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
2994 (ins GR8:$src1, GR8:$src2),
2995 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2996 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
2997 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
2998 (ins GR16:$src1, GR16:$src2),
2999 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3000 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
3001 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
3002 (ins GR32:$src1, GR32:$src2),
3003 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3004 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
3006 let isTwoAddress = 0 in {
3007 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3008 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3009 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
3010 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3011 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3012 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
3014 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3015 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3016 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
3017 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
3018 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3019 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
3020 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
3021 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3022 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
3024 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3025 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3026 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
3028 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
3029 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3030 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
3031 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3032 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3033 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
3035 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
3036 "sbb{b}\t{$src, %al|%al, $src}", []>;
3037 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
3038 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3039 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
3040 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
3043 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3044 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
3045 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
3046 (ins GR16:$src1, GR16:$src2),
3047 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3048 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
3049 (ins GR32:$src1, GR32:$src2),
3050 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
3052 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
3053 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3054 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
3055 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
3056 (ins GR16:$src1, i16mem:$src2),
3057 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3058 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
3060 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
3061 (ins GR32:$src1, i32mem:$src2),
3062 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3063 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
3064 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
3065 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3066 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
3067 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
3068 (ins GR16:$src1, i16imm:$src2),
3069 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3070 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
3071 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
3072 (ins GR16:$src1, i16i8imm:$src2),
3073 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3074 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
3076 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
3077 (ins GR32:$src1, i32imm:$src2),
3078 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3079 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
3080 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
3081 (ins GR32:$src1, i32i8imm:$src2),
3082 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3083 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
3084 } // Uses = [EFLAGS]
3085 } // Defs = [EFLAGS]
3087 let Defs = [EFLAGS] in {
3088 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
3089 // Register-Register Signed Integer Multiply
3090 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3091 "imul{w}\t{$src2, $dst|$dst, $src2}",
3092 [(set GR16:$dst, EFLAGS,
3093 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
3094 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3095 "imul{l}\t{$src2, $dst|$dst, $src2}",
3096 [(set GR32:$dst, EFLAGS,
3097 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
3100 // Register-Memory Signed Integer Multiply
3101 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
3102 (ins GR16:$src1, i16mem:$src2),
3103 "imul{w}\t{$src2, $dst|$dst, $src2}",
3104 [(set GR16:$dst, EFLAGS,
3105 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
3107 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
3108 (ins GR32:$src1, i32mem:$src2),
3109 "imul{l}\t{$src2, $dst|$dst, $src2}",
3110 [(set GR32:$dst, EFLAGS,
3111 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
3112 } // Defs = [EFLAGS]
3113 } // end Two Address instructions
3115 // Suprisingly enough, these are not two address instructions!
3116 let Defs = [EFLAGS] in {
3117 // Register-Integer Signed Integer Multiply
3118 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
3119 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
3120 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3121 [(set GR16:$dst, EFLAGS,
3122 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
3123 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
3124 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
3125 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3126 [(set GR32:$dst, EFLAGS,
3127 (X86smul_flag GR32:$src1, imm:$src2))]>;
3128 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
3129 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
3130 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3131 [(set GR16:$dst, EFLAGS,
3132 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
3134 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
3135 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
3136 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3137 [(set GR32:$dst, EFLAGS,
3138 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
3140 // Memory-Integer Signed Integer Multiply
3141 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
3142 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
3143 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3144 [(set GR16:$dst, EFLAGS,
3145 (X86smul_flag (load addr:$src1), imm:$src2))]>,
3147 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
3148 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
3149 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3150 [(set GR32:$dst, EFLAGS,
3151 (X86smul_flag (load addr:$src1), imm:$src2))]>;
3152 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
3153 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
3154 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3155 [(set GR16:$dst, EFLAGS,
3156 (X86smul_flag (load addr:$src1),
3157 i16immSExt8:$src2))]>, OpSize;
3158 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
3159 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
3160 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3161 [(set GR32:$dst, EFLAGS,
3162 (X86smul_flag (load addr:$src1),
3163 i32immSExt8:$src2))]>;
3164 } // Defs = [EFLAGS]
3166 //===----------------------------------------------------------------------===//
3167 // Test instructions are just like AND, except they don't generate a result.
3169 let Defs = [EFLAGS] in {
3170 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
3171 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3172 "test{b}\t{$src2, $src1|$src1, $src2}",
3173 [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
3174 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3175 "test{w}\t{$src2, $src1|$src1, $src2}",
3176 [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
3179 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3180 "test{l}\t{$src2, $src1|$src1, $src2}",
3181 [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
3185 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
3186 "test{b}\t{$src, %al|%al, $src}", []>;
3187 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
3188 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3189 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
3190 "test{l}\t{$src, %eax|%eax, $src}", []>;
3192 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
3193 "test{b}\t{$src2, $src1|$src1, $src2}",
3194 [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
3196 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
3197 "test{w}\t{$src2, $src1|$src1, $src2}",
3198 [(set EFLAGS, (X86cmp (and GR16:$src1,
3199 (loadi16 addr:$src2)), 0))]>, OpSize;
3200 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
3201 "test{l}\t{$src2, $src1|$src1, $src2}",
3202 [(set EFLAGS, (X86cmp (and GR32:$src1,
3203 (loadi32 addr:$src2)), 0))]>;
3205 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
3206 (outs), (ins GR8:$src1, i8imm:$src2),
3207 "test{b}\t{$src2, $src1|$src1, $src2}",
3208 [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
3209 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
3210 (outs), (ins GR16:$src1, i16imm:$src2),
3211 "test{w}\t{$src2, $src1|$src1, $src2}",
3212 [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
3214 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
3215 (outs), (ins GR32:$src1, i32imm:$src2),
3216 "test{l}\t{$src2, $src1|$src1, $src2}",
3217 [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
3219 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
3220 (outs), (ins i8mem:$src1, i8imm:$src2),
3221 "test{b}\t{$src2, $src1|$src1, $src2}",
3222 [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
3224 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3225 (outs), (ins i16mem:$src1, i16imm:$src2),
3226 "test{w}\t{$src2, $src1|$src1, $src2}",
3227 [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
3229 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3230 (outs), (ins i32mem:$src1, i32imm:$src2),
3231 "test{l}\t{$src2, $src1|$src1, $src2}",
3232 [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
3234 } // Defs = [EFLAGS]
3237 // Condition code ops, incl. set if equal/not equal/...
3238 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3239 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3240 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3241 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3243 let Uses = [EFLAGS] in {
3244 // Use sbb to materialize carry bit.
3245 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
3246 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
3247 // However, Pat<> can't replicate the destination reg into the inputs of the
3249 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
3251 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
3252 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3253 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
3254 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
3256 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
3257 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3260 def SETEr : I<0x94, MRM0r,
3261 (outs GR8 :$dst), (ins),
3263 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3265 def SETEm : I<0x94, MRM0m,
3266 (outs), (ins i8mem:$dst),
3268 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3271 def SETNEr : I<0x95, MRM0r,
3272 (outs GR8 :$dst), (ins),
3274 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3276 def SETNEm : I<0x95, MRM0m,
3277 (outs), (ins i8mem:$dst),
3279 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3282 def SETLr : I<0x9C, MRM0r,
3283 (outs GR8 :$dst), (ins),
3285 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3286 TB; // GR8 = < signed
3287 def SETLm : I<0x9C, MRM0m,
3288 (outs), (ins i8mem:$dst),
3290 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3291 TB; // [mem8] = < signed
3293 def SETGEr : I<0x9D, MRM0r,
3294 (outs GR8 :$dst), (ins),
3296 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3297 TB; // GR8 = >= signed
3298 def SETGEm : I<0x9D, MRM0m,
3299 (outs), (ins i8mem:$dst),
3301 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3302 TB; // [mem8] = >= signed
3304 def SETLEr : I<0x9E, MRM0r,
3305 (outs GR8 :$dst), (ins),
3307 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3308 TB; // GR8 = <= signed
3309 def SETLEm : I<0x9E, MRM0m,
3310 (outs), (ins i8mem:$dst),
3312 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3313 TB; // [mem8] = <= signed
3315 def SETGr : I<0x9F, MRM0r,
3316 (outs GR8 :$dst), (ins),
3318 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3319 TB; // GR8 = > signed
3320 def SETGm : I<0x9F, MRM0m,
3321 (outs), (ins i8mem:$dst),
3323 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3324 TB; // [mem8] = > signed
3326 def SETBr : I<0x92, MRM0r,
3327 (outs GR8 :$dst), (ins),
3329 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3330 TB; // GR8 = < unsign
3331 def SETBm : I<0x92, MRM0m,
3332 (outs), (ins i8mem:$dst),
3334 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3335 TB; // [mem8] = < unsign
3337 def SETAEr : I<0x93, MRM0r,
3338 (outs GR8 :$dst), (ins),
3340 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3341 TB; // GR8 = >= unsign
3342 def SETAEm : I<0x93, MRM0m,
3343 (outs), (ins i8mem:$dst),
3345 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3346 TB; // [mem8] = >= unsign
3348 def SETBEr : I<0x96, MRM0r,
3349 (outs GR8 :$dst), (ins),
3351 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3352 TB; // GR8 = <= unsign
3353 def SETBEm : I<0x96, MRM0m,
3354 (outs), (ins i8mem:$dst),
3356 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3357 TB; // [mem8] = <= unsign
3359 def SETAr : I<0x97, MRM0r,
3360 (outs GR8 :$dst), (ins),
3362 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3363 TB; // GR8 = > signed
3364 def SETAm : I<0x97, MRM0m,
3365 (outs), (ins i8mem:$dst),
3367 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3368 TB; // [mem8] = > signed
3370 def SETSr : I<0x98, MRM0r,
3371 (outs GR8 :$dst), (ins),
3373 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3374 TB; // GR8 = <sign bit>
3375 def SETSm : I<0x98, MRM0m,
3376 (outs), (ins i8mem:$dst),
3378 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3379 TB; // [mem8] = <sign bit>
3380 def SETNSr : I<0x99, MRM0r,
3381 (outs GR8 :$dst), (ins),
3383 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3384 TB; // GR8 = !<sign bit>
3385 def SETNSm : I<0x99, MRM0m,
3386 (outs), (ins i8mem:$dst),
3388 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3389 TB; // [mem8] = !<sign bit>
3391 def SETPr : I<0x9A, MRM0r,
3392 (outs GR8 :$dst), (ins),
3394 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3396 def SETPm : I<0x9A, MRM0m,
3397 (outs), (ins i8mem:$dst),
3399 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3400 TB; // [mem8] = parity
3401 def SETNPr : I<0x9B, MRM0r,
3402 (outs GR8 :$dst), (ins),
3404 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3405 TB; // GR8 = not parity
3406 def SETNPm : I<0x9B, MRM0m,
3407 (outs), (ins i8mem:$dst),
3409 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3410 TB; // [mem8] = not parity
3412 def SETOr : I<0x90, MRM0r,
3413 (outs GR8 :$dst), (ins),
3415 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3416 TB; // GR8 = overflow
3417 def SETOm : I<0x90, MRM0m,
3418 (outs), (ins i8mem:$dst),
3420 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3421 TB; // [mem8] = overflow
3422 def SETNOr : I<0x91, MRM0r,
3423 (outs GR8 :$dst), (ins),
3425 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3426 TB; // GR8 = not overflow
3427 def SETNOm : I<0x91, MRM0m,
3428 (outs), (ins i8mem:$dst),
3430 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3431 TB; // [mem8] = not overflow
3432 } // Uses = [EFLAGS]
3435 // Integer comparisons
3436 let Defs = [EFLAGS] in {
3437 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3438 "cmp{b}\t{$src, %al|%al, $src}", []>;
3439 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3440 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3441 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3442 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3444 def CMP8rr : I<0x38, MRMDestReg,
3445 (outs), (ins GR8 :$src1, GR8 :$src2),
3446 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3447 [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
3448 def CMP16rr : I<0x39, MRMDestReg,
3449 (outs), (ins GR16:$src1, GR16:$src2),
3450 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3451 [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
3452 def CMP32rr : I<0x39, MRMDestReg,
3453 (outs), (ins GR32:$src1, GR32:$src2),
3454 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3455 [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
3456 def CMP8mr : I<0x38, MRMDestMem,
3457 (outs), (ins i8mem :$src1, GR8 :$src2),
3458 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3459 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
3460 def CMP16mr : I<0x39, MRMDestMem,
3461 (outs), (ins i16mem:$src1, GR16:$src2),
3462 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3463 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
3465 def CMP32mr : I<0x39, MRMDestMem,
3466 (outs), (ins i32mem:$src1, GR32:$src2),
3467 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3468 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
3469 def CMP8rm : I<0x3A, MRMSrcMem,
3470 (outs), (ins GR8 :$src1, i8mem :$src2),
3471 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3472 [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
3473 def CMP16rm : I<0x3B, MRMSrcMem,
3474 (outs), (ins GR16:$src1, i16mem:$src2),
3475 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3476 [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
3478 def CMP32rm : I<0x3B, MRMSrcMem,
3479 (outs), (ins GR32:$src1, i32mem:$src2),
3480 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3481 [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
3483 // These are alternate spellings for use by the disassembler, we mark them as
3484 // code gen only to ensure they aren't matched by the assembler.
3485 let isCodeGenOnly = 1 in {
3486 def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3487 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3488 def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3489 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3490 def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3491 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3494 def CMP8ri : Ii8<0x80, MRM7r,
3495 (outs), (ins GR8:$src1, i8imm:$src2),
3496 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3497 [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
3498 def CMP16ri : Ii16<0x81, MRM7r,
3499 (outs), (ins GR16:$src1, i16imm:$src2),
3500 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3501 [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
3502 def CMP32ri : Ii32<0x81, MRM7r,
3503 (outs), (ins GR32:$src1, i32imm:$src2),
3504 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3505 [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
3506 def CMP8mi : Ii8 <0x80, MRM7m,
3507 (outs), (ins i8mem :$src1, i8imm :$src2),
3508 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3509 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
3510 def CMP16mi : Ii16<0x81, MRM7m,
3511 (outs), (ins i16mem:$src1, i16imm:$src2),
3512 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3513 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
3515 def CMP32mi : Ii32<0x81, MRM7m,
3516 (outs), (ins i32mem:$src1, i32imm:$src2),
3517 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3518 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
3519 def CMP16ri8 : Ii8<0x83, MRM7r,
3520 (outs), (ins GR16:$src1, i16i8imm:$src2),
3521 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3522 [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
3524 def CMP16mi8 : Ii8<0x83, MRM7m,
3525 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3526 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3527 [(set EFLAGS, (X86cmp (loadi16 addr:$src1),
3528 i16immSExt8:$src2))]>, OpSize;
3529 def CMP32mi8 : Ii8<0x83, MRM7m,
3530 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3531 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3532 [(set EFLAGS, (X86cmp (loadi32 addr:$src1),
3533 i32immSExt8:$src2))]>;
3534 def CMP32ri8 : Ii8<0x83, MRM7r,
3535 (outs), (ins GR32:$src1, i32i8imm:$src2),
3536 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3537 [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
3538 } // Defs = [EFLAGS]
3541 // TODO: BTC, BTR, and BTS
3542 let Defs = [EFLAGS] in {
3543 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3544 "bt{w}\t{$src2, $src1|$src1, $src2}",
3545 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
3546 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3547 "bt{l}\t{$src2, $src1|$src1, $src2}",
3548 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
3550 // Unlike with the register+register form, the memory+register form of the
3551 // bt instruction does not ignore the high bits of the index. From ISel's
3552 // perspective, this is pretty bizarre. Make these instructions disassembly
3555 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3556 "bt{w}\t{$src2, $src1|$src1, $src2}",
3557 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3558 // (implicit EFLAGS)]
3560 >, OpSize, TB, Requires<[FastBTMem]>;
3561 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3562 "bt{l}\t{$src2, $src1|$src1, $src2}",
3563 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3564 // (implicit EFLAGS)]
3566 >, TB, Requires<[FastBTMem]>;
3568 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3569 "bt{w}\t{$src2, $src1|$src1, $src2}",
3570 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
3572 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3573 "bt{l}\t{$src2, $src1|$src1, $src2}",
3574 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
3575 // Note that these instructions don't need FastBTMem because that
3576 // only applies when the other operand is in a register. When it's
3577 // an immediate, bt is still fast.
3578 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3579 "bt{w}\t{$src2, $src1|$src1, $src2}",
3580 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
3582 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3583 "bt{l}\t{$src2, $src1|$src1, $src2}",
3584 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
3587 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3588 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3589 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3590 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3591 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3592 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3593 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3594 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3595 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3596 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3597 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3598 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3599 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3600 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3601 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3602 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3604 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3605 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3606 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3607 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3608 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3609 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3610 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3611 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3612 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3613 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3614 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3615 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3616 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3617 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3618 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3619 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3621 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3622 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3623 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3624 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3625 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3626 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3627 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3628 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3629 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3630 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3631 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3632 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3633 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3634 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3635 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3636 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3637 } // Defs = [EFLAGS]
3639 // Sign/Zero extenders
3640 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3641 // of the register here. This has a smaller encoding and avoids a
3642 // partial-register update. Actual movsbw included for the disassembler.
3643 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3644 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3645 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3646 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3647 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3648 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3649 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3650 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3651 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3652 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3653 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3654 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3655 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3656 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3657 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3658 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3659 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3660 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3661 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3662 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3664 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3665 // of the register here. This has a smaller encoding and avoids a
3666 // partial-register update. Actual movzbw included for the disassembler.
3667 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3668 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3669 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3670 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3671 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3672 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3673 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3674 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3675 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3676 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3677 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3678 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3679 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3680 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3681 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3682 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3683 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3684 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3685 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3686 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3688 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
3689 // except that they use GR32_NOREX for the output operand register class
3690 // instead of GR32. This allows them to operate on h registers on x86-64.
3691 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3692 (outs GR32_NOREX:$dst), (ins GR8:$src),
3693 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3696 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3697 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3698 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3701 let neverHasSideEffects = 1 in {
3702 let Defs = [AX], Uses = [AL] in
3703 def CBW : I<0x98, RawFrm, (outs), (ins),
3704 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3705 let Defs = [EAX], Uses = [AX] in
3706 def CWDE : I<0x98, RawFrm, (outs), (ins),
3707 "{cwtl|cwde}", []>; // EAX = signext(AX)
3709 let Defs = [AX,DX], Uses = [AX] in
3710 def CWD : I<0x99, RawFrm, (outs), (ins),
3711 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3712 let Defs = [EAX,EDX], Uses = [EAX] in
3713 def CDQ : I<0x99, RawFrm, (outs), (ins),
3714 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3717 //===----------------------------------------------------------------------===//
3718 // Alias Instructions
3719 //===----------------------------------------------------------------------===//
3721 // Alias instructions that map movr0 to xor.
3722 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3723 // FIXME: Set encoding to pseudo.
3724 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3725 isCodeGenOnly = 1 in {
3726 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
3727 [(set GR8:$dst, 0)]>;
3729 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
3730 // encoding and avoids a partial-register update sometimes, but doing so
3731 // at isel time interferes with rematerialization in the current register
3732 // allocator. For now, this is rewritten when the instruction is lowered
3734 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3736 [(set GR16:$dst, 0)]>, OpSize;
3738 // FIXME: Set encoding to pseudo.
3739 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
3740 [(set GR32:$dst, 0)]>;
3743 //===----------------------------------------------------------------------===//
3744 // Thread Local Storage Instructions
3747 // All calls clobber the non-callee saved registers. ESP is marked as
3748 // a use to prevent stack-pointer assignments that appear immediately
3749 // before calls from potentially appearing dead.
3750 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3751 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3752 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3753 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3755 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3756 "leal\t$sym, %eax; "
3757 "call\t___tls_get_addr@PLT",
3758 [(X86tlsaddr tls32addr:$sym)]>,
3759 Requires<[In32BitMode]>;
3761 let AddedComplexity = 5, isCodeGenOnly = 1 in
3762 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3763 "movl\t%gs:$src, $dst",
3764 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3766 let AddedComplexity = 5, isCodeGenOnly = 1 in
3767 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3768 "movl\t%fs:$src, $dst",
3769 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3771 //===----------------------------------------------------------------------===//
3772 // EH Pseudo Instructions
3774 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3775 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3776 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3777 "ret\t#eh_return, addr: $addr",
3778 [(X86ehret GR32:$addr)]>;
3782 //===----------------------------------------------------------------------===//
3786 // Atomic swap. These are just normal xchg instructions. But since a memory
3787 // operand is referenced, the atomicity is ensured.
3788 let Constraints = "$val = $dst" in {
3789 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3790 (ins GR32:$val, i32mem:$ptr),
3791 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3792 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3793 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3794 (ins GR16:$val, i16mem:$ptr),
3795 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3796 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3798 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3799 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3800 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3802 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3803 "xchg{l}\t{$val, $src|$src, $val}", []>;
3804 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3805 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3806 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3807 "xchg{b}\t{$val, $src|$src, $val}", []>;
3810 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3811 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3812 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3813 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
3815 // Atomic compare and swap.
3816 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3817 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3819 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3820 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3822 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3823 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
3826 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3829 let Defs = [AX, EFLAGS], Uses = [AX] in {
3830 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3832 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3833 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3835 let Defs = [AL, EFLAGS], Uses = [AL] in {
3836 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3838 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3839 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3842 // Atomic exchange and add
3843 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3844 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
3846 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3847 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3849 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
3851 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3852 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3854 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3856 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3857 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3861 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3862 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3863 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3864 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3865 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3866 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3868 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3869 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3870 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3871 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3872 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3873 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3875 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3876 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3877 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3878 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3879 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3880 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3882 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3883 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3884 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3885 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3886 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3887 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3889 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
3890 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
3891 "cmpxchg8b\t$dst", []>, TB;
3893 // Optimized codegen when the non-memory output is not used.
3894 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3895 let Defs = [EFLAGS] in {
3896 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3898 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3899 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3901 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3902 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3904 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3905 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3907 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3908 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3910 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3911 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3913 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3914 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3916 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3917 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3919 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3921 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3923 "inc{b}\t$dst", []>, LOCK;
3924 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3926 "inc{w}\t$dst", []>, OpSize, LOCK;
3927 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3929 "inc{l}\t$dst", []>, LOCK;
3931 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3933 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3934 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3936 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3937 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3939 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3940 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3942 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3943 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3945 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3946 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3948 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3949 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3951 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3952 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3954 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3956 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3958 "dec{b}\t$dst", []>, LOCK;
3959 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3961 "dec{w}\t$dst", []>, OpSize, LOCK;
3962 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3964 "dec{l}\t$dst", []>, LOCK;
3967 // Atomic exchange, and, or, xor
3968 let Constraints = "$val = $dst", Defs = [EFLAGS],
3969 usesCustomInserter = 1 in {
3970 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3971 "#ATOMAND32 PSEUDO!",
3972 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3973 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3974 "#ATOMOR32 PSEUDO!",
3975 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
3976 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3977 "#ATOMXOR32 PSEUDO!",
3978 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
3979 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3980 "#ATOMNAND32 PSEUDO!",
3981 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
3982 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3983 "#ATOMMIN32 PSEUDO!",
3984 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
3985 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3986 "#ATOMMAX32 PSEUDO!",
3987 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
3988 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3989 "#ATOMUMIN32 PSEUDO!",
3990 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
3991 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3992 "#ATOMUMAX32 PSEUDO!",
3993 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
3995 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3996 "#ATOMAND16 PSEUDO!",
3997 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
3998 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3999 "#ATOMOR16 PSEUDO!",
4000 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
4001 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4002 "#ATOMXOR16 PSEUDO!",
4003 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
4004 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4005 "#ATOMNAND16 PSEUDO!",
4006 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
4007 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
4008 "#ATOMMIN16 PSEUDO!",
4009 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
4010 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4011 "#ATOMMAX16 PSEUDO!",
4012 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
4013 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4014 "#ATOMUMIN16 PSEUDO!",
4015 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
4016 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4017 "#ATOMUMAX16 PSEUDO!",
4018 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
4020 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4021 "#ATOMAND8 PSEUDO!",
4022 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
4023 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4025 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
4026 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4027 "#ATOMXOR8 PSEUDO!",
4028 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
4029 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4030 "#ATOMNAND8 PSEUDO!",
4031 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
4034 let Constraints = "$val1 = $dst1, $val2 = $dst2",
4035 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
4036 Uses = [EAX, EBX, ECX, EDX],
4037 mayLoad = 1, mayStore = 1,
4038 usesCustomInserter = 1 in {
4039 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4040 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4041 "#ATOMAND6432 PSEUDO!", []>;
4042 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4043 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4044 "#ATOMOR6432 PSEUDO!", []>;
4045 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4046 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4047 "#ATOMXOR6432 PSEUDO!", []>;
4048 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4049 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4050 "#ATOMNAND6432 PSEUDO!", []>;
4051 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4052 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4053 "#ATOMADD6432 PSEUDO!", []>;
4054 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4055 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4056 "#ATOMSUB6432 PSEUDO!", []>;
4057 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4058 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4059 "#ATOMSWAP6432 PSEUDO!", []>;
4062 // Segmentation support instructions.
4064 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4065 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4066 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4067 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4069 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
4070 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
4071 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4072 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4073 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4075 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4076 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4077 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4078 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4079 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4080 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4081 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4082 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4084 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
4086 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
4087 "str{w}\t{$dst}", []>, TB;
4088 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
4089 "str{w}\t{$dst}", []>, TB;
4090 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
4091 "ltr{w}\t{$src}", []>, TB;
4092 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
4093 "ltr{w}\t{$src}", []>, TB;
4095 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
4096 "push{w}\t%fs", []>, OpSize, TB;
4097 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
4098 "push{l}\t%fs", []>, TB;
4099 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
4100 "push{w}\t%gs", []>, OpSize, TB;
4101 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
4102 "push{l}\t%gs", []>, TB;
4104 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
4105 "pop{w}\t%fs", []>, OpSize, TB;
4106 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
4107 "pop{l}\t%fs", []>, TB;
4108 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
4109 "pop{w}\t%gs", []>, OpSize, TB;
4110 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
4111 "pop{l}\t%gs", []>, TB;
4113 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4114 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4115 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4116 "lds{l}\t{$src, $dst|$dst, $src}", []>;
4117 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4118 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4119 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4120 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
4121 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4122 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4123 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4124 "les{l}\t{$src, $dst|$dst, $src}", []>;
4125 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4126 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4127 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4128 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4129 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4130 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4131 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4132 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4134 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
4135 "verr\t$seg", []>, TB;
4136 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
4137 "verr\t$seg", []>, TB;
4138 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
4139 "verw\t$seg", []>, TB;
4140 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
4141 "verw\t$seg", []>, TB;
4143 // Descriptor-table support instructions
4145 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
4146 "sgdt\t$dst", []>, TB;
4147 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
4148 "sidt\t$dst", []>, TB;
4149 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
4150 "sldt{w}\t$dst", []>, TB;
4151 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
4152 "sldt{w}\t$dst", []>, TB;
4153 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
4154 "lgdt\t$src", []>, TB;
4155 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
4156 "lidt\t$src", []>, TB;
4157 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
4158 "lldt{w}\t$src", []>, TB;
4159 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
4160 "lldt{w}\t$src", []>, TB;
4162 // Lock instruction prefix
4163 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
4165 // Repeat string operation instruction prefixes
4166 // These uses the DF flag in the EFLAGS register to inc or dec ECX
4167 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
4168 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
4169 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
4170 // Repeat while not equal (used with CMPS and SCAS)
4171 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
4174 // Segment override instruction prefixes
4175 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
4176 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
4177 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
4178 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
4179 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
4180 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
4182 // String manipulation instructions
4184 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
4185 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
4186 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
4188 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
4189 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
4190 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
4192 // CPU flow control instructions
4194 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
4195 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
4197 // FPU control instructions
4199 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
4201 // Flag instructions
4203 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
4204 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
4205 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
4206 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
4207 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
4208 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
4209 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
4211 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
4213 // Table lookup instructions
4215 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
4217 // Specialized register support
4219 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
4220 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
4221 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
4223 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
4224 "smsw{w}\t$dst", []>, OpSize, TB;
4225 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
4226 "smsw{l}\t$dst", []>, TB;
4227 // For memory operands, there is only a 16-bit form
4228 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
4229 "smsw{w}\t$dst", []>, TB;
4231 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
4232 "lmsw{w}\t$src", []>, TB;
4233 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
4234 "lmsw{w}\t$src", []>, TB;
4236 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
4238 // Cache instructions
4240 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
4241 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
4246 def INVEPT : I<0x80, RawFrm, (outs), (ins), "invept", []>, OpSize, T8;
4248 def INVVPID : I<0x81, RawFrm, (outs), (ins), "invvpid", []>, OpSize, T8;
4250 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
4251 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4252 "vmclear\t$vmcs", []>, OpSize, TB;
4254 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
4256 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
4257 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4258 "vmptrld\t$vmcs", []>, TB;
4259 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4260 "vmptrst\t$vmcs", []>, TB;
4261 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
4262 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4263 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
4264 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4265 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
4266 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4267 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4268 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4269 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4270 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4271 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4272 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4273 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4274 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4275 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4276 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4278 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
4279 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
4280 "vmxon\t{$vmxon}", []>, XS;
4282 //===----------------------------------------------------------------------===//
4283 // Non-Instruction Patterns
4284 //===----------------------------------------------------------------------===//
4286 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
4287 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
4288 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
4289 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
4290 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
4291 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
4292 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
4294 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
4295 (ADD32ri GR32:$src1, tconstpool:$src2)>;
4296 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
4297 (ADD32ri GR32:$src1, tjumptable:$src2)>;
4298 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
4299 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
4300 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
4301 (ADD32ri GR32:$src1, texternalsym:$src2)>;
4302 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
4303 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
4305 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
4306 (MOV32mi addr:$dst, tglobaladdr:$src)>;
4307 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
4308 (MOV32mi addr:$dst, texternalsym:$src)>;
4309 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
4310 (MOV32mi addr:$dst, tblockaddress:$src)>;
4314 def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
4315 (TCRETURNri GR32_TC:$dst, imm:$off)>,
4316 Requires<[In32BitMode]>;
4318 // FIXME: This is disabled for 32-bit PIC mode because the global base
4319 // register which is part of the address mode may be assigned a
4320 // callee-saved register.
4321 def : Pat<(X86tcret (load addr:$dst), imm:$off),
4322 (TCRETURNmi addr:$dst, imm:$off)>,
4323 Requires<[In32BitMode, IsNotPIC]>;
4325 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
4326 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4327 Requires<[In32BitMode]>;
4329 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
4330 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4331 Requires<[In32BitMode]>;
4333 // Normal calls, with various flavors of addresses.
4334 def : Pat<(X86call (i32 tglobaladdr:$dst)),
4335 (CALLpcrel32 tglobaladdr:$dst)>;
4336 def : Pat<(X86call (i32 texternalsym:$dst)),
4337 (CALLpcrel32 texternalsym:$dst)>;
4338 def : Pat<(X86call (i32 imm:$dst)),
4339 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
4341 // X86 specific add which produces a flag.
4342 def : Pat<(addc GR32:$src1, GR32:$src2),
4343 (ADD32rr GR32:$src1, GR32:$src2)>;
4344 def : Pat<(addc GR32:$src1, (load addr:$src2)),
4345 (ADD32rm GR32:$src1, addr:$src2)>;
4346 def : Pat<(addc GR32:$src1, imm:$src2),
4347 (ADD32ri GR32:$src1, imm:$src2)>;
4348 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
4349 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4351 def : Pat<(subc GR32:$src1, GR32:$src2),
4352 (SUB32rr GR32:$src1, GR32:$src2)>;
4353 def : Pat<(subc GR32:$src1, (load addr:$src2)),
4354 (SUB32rm GR32:$src1, addr:$src2)>;
4355 def : Pat<(subc GR32:$src1, imm:$src2),
4356 (SUB32ri GR32:$src1, imm:$src2)>;
4357 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
4358 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4362 // TEST R,R is smaller than CMP R,0
4363 def : Pat<(X86cmp GR8:$src1, 0),
4364 (TEST8rr GR8:$src1, GR8:$src1)>;
4365 def : Pat<(X86cmp GR16:$src1, 0),
4366 (TEST16rr GR16:$src1, GR16:$src1)>;
4367 def : Pat<(X86cmp GR32:$src1, 0),
4368 (TEST32rr GR32:$src1, GR32:$src1)>;
4370 // Conditional moves with folded loads with operands swapped and conditions
4372 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
4373 (CMOVAE16rm GR16:$src2, addr:$src1)>;
4374 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
4375 (CMOVAE32rm GR32:$src2, addr:$src1)>;
4376 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
4377 (CMOVB16rm GR16:$src2, addr:$src1)>;
4378 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
4379 (CMOVB32rm GR32:$src2, addr:$src1)>;
4380 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
4381 (CMOVNE16rm GR16:$src2, addr:$src1)>;
4382 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
4383 (CMOVNE32rm GR32:$src2, addr:$src1)>;
4384 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
4385 (CMOVE16rm GR16:$src2, addr:$src1)>;
4386 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
4387 (CMOVE32rm GR32:$src2, addr:$src1)>;
4388 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
4389 (CMOVA16rm GR16:$src2, addr:$src1)>;
4390 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
4391 (CMOVA32rm GR32:$src2, addr:$src1)>;
4392 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
4393 (CMOVBE16rm GR16:$src2, addr:$src1)>;
4394 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
4395 (CMOVBE32rm GR32:$src2, addr:$src1)>;
4396 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
4397 (CMOVGE16rm GR16:$src2, addr:$src1)>;
4398 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
4399 (CMOVGE32rm GR32:$src2, addr:$src1)>;
4400 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
4401 (CMOVL16rm GR16:$src2, addr:$src1)>;
4402 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
4403 (CMOVL32rm GR32:$src2, addr:$src1)>;
4404 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
4405 (CMOVG16rm GR16:$src2, addr:$src1)>;
4406 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
4407 (CMOVG32rm GR32:$src2, addr:$src1)>;
4408 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
4409 (CMOVLE16rm GR16:$src2, addr:$src1)>;
4410 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
4411 (CMOVLE32rm GR32:$src2, addr:$src1)>;
4412 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
4413 (CMOVNP16rm GR16:$src2, addr:$src1)>;
4414 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
4415 (CMOVNP32rm GR32:$src2, addr:$src1)>;
4416 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
4417 (CMOVP16rm GR16:$src2, addr:$src1)>;
4418 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
4419 (CMOVP32rm GR32:$src2, addr:$src1)>;
4420 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
4421 (CMOVNS16rm GR16:$src2, addr:$src1)>;
4422 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
4423 (CMOVNS32rm GR32:$src2, addr:$src1)>;
4424 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
4425 (CMOVS16rm GR16:$src2, addr:$src1)>;
4426 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
4427 (CMOVS32rm GR32:$src2, addr:$src1)>;
4428 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
4429 (CMOVNO16rm GR16:$src2, addr:$src1)>;
4430 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
4431 (CMOVNO32rm GR32:$src2, addr:$src1)>;
4432 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
4433 (CMOVO16rm GR16:$src2, addr:$src1)>;
4434 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
4435 (CMOVO32rm GR32:$src2, addr:$src1)>;
4437 // zextload bool -> zextload byte
4438 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4439 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4440 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4442 // extload bool -> extload byte
4443 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4444 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4445 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4446 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
4447 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
4448 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
4450 // anyext. Define these to do an explicit zero-extend to
4451 // avoid partial-register updates.
4452 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
4453 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
4455 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
4456 def : Pat<(i32 (anyext GR16:$src)),
4457 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
4460 //===----------------------------------------------------------------------===//
4462 //===----------------------------------------------------------------------===//
4464 // Odd encoding trick: -128 fits into an 8-bit immediate field while
4465 // +128 doesn't, so in this special case use a sub instead of an add.
4466 def : Pat<(add GR16:$src1, 128),
4467 (SUB16ri8 GR16:$src1, -128)>;
4468 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
4469 (SUB16mi8 addr:$dst, -128)>;
4470 def : Pat<(add GR32:$src1, 128),
4471 (SUB32ri8 GR32:$src1, -128)>;
4472 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
4473 (SUB32mi8 addr:$dst, -128)>;
4475 // r & (2^16-1) ==> movz
4476 def : Pat<(and GR32:$src1, 0xffff),
4477 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
4478 // r & (2^8-1) ==> movz
4479 def : Pat<(and GR32:$src1, 0xff),
4480 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
4483 Requires<[In32BitMode]>;
4484 // r & (2^8-1) ==> movz
4485 def : Pat<(and GR16:$src1, 0xff),
4486 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
4489 Requires<[In32BitMode]>;
4491 // sext_inreg patterns
4492 def : Pat<(sext_inreg GR32:$src, i16),
4493 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
4494 def : Pat<(sext_inreg GR32:$src, i8),
4495 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4498 Requires<[In32BitMode]>;
4499 def : Pat<(sext_inreg GR16:$src, i8),
4500 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4503 Requires<[In32BitMode]>;
4506 def : Pat<(i16 (trunc GR32:$src)),
4507 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
4508 def : Pat<(i8 (trunc GR32:$src)),
4509 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4511 Requires<[In32BitMode]>;
4512 def : Pat<(i8 (trunc GR16:$src)),
4513 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4515 Requires<[In32BitMode]>;
4517 // h-register tricks
4518 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
4519 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4520 x86_subreg_8bit_hi)>,
4521 Requires<[In32BitMode]>;
4522 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
4523 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4524 x86_subreg_8bit_hi)>,
4525 Requires<[In32BitMode]>;
4526 def : Pat<(srl GR16:$src, (i8 8)),
4529 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4530 x86_subreg_8bit_hi)),
4532 Requires<[In32BitMode]>;
4533 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4534 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4536 x86_subreg_8bit_hi))>,
4537 Requires<[In32BitMode]>;
4538 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4539 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4541 x86_subreg_8bit_hi))>,
4542 Requires<[In32BitMode]>;
4543 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4544 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4546 x86_subreg_8bit_hi))>,
4547 Requires<[In32BitMode]>;
4548 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
4549 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4551 x86_subreg_8bit_hi))>,
4552 Requires<[In32BitMode]>;
4554 // (shl x, 1) ==> (add x, x)
4555 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
4556 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
4557 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
4559 // (shl x (and y, 31)) ==> (shl x, y)
4560 def : Pat<(shl GR8:$src1, (and CL, 31)),
4561 (SHL8rCL GR8:$src1)>;
4562 def : Pat<(shl GR16:$src1, (and CL, 31)),
4563 (SHL16rCL GR16:$src1)>;
4564 def : Pat<(shl GR32:$src1, (and CL, 31)),
4565 (SHL32rCL GR32:$src1)>;
4566 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4567 (SHL8mCL addr:$dst)>;
4568 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4569 (SHL16mCL addr:$dst)>;
4570 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4571 (SHL32mCL addr:$dst)>;
4573 def : Pat<(srl GR8:$src1, (and CL, 31)),
4574 (SHR8rCL GR8:$src1)>;
4575 def : Pat<(srl GR16:$src1, (and CL, 31)),
4576 (SHR16rCL GR16:$src1)>;
4577 def : Pat<(srl GR32:$src1, (and CL, 31)),
4578 (SHR32rCL GR32:$src1)>;
4579 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4580 (SHR8mCL addr:$dst)>;
4581 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4582 (SHR16mCL addr:$dst)>;
4583 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4584 (SHR32mCL addr:$dst)>;
4586 def : Pat<(sra GR8:$src1, (and CL, 31)),
4587 (SAR8rCL GR8:$src1)>;
4588 def : Pat<(sra GR16:$src1, (and CL, 31)),
4589 (SAR16rCL GR16:$src1)>;
4590 def : Pat<(sra GR32:$src1, (and CL, 31)),
4591 (SAR32rCL GR32:$src1)>;
4592 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4593 (SAR8mCL addr:$dst)>;
4594 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4595 (SAR16mCL addr:$dst)>;
4596 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4597 (SAR32mCL addr:$dst)>;
4599 // (anyext (setcc_carry)) -> (setcc_carry)
4600 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4602 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4604 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
4607 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
4608 let AddedComplexity = 5 in { // Try this before the selecting to OR
4609 def : Pat<(or_is_add GR16:$src1, imm:$src2),
4610 (ADD16ri GR16:$src1, imm:$src2)>;
4611 def : Pat<(or_is_add GR32:$src1, imm:$src2),
4612 (ADD32ri GR32:$src1, imm:$src2)>;
4613 def : Pat<(or_is_add GR16:$src1, i16immSExt8:$src2),
4614 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4615 def : Pat<(or_is_add GR32:$src1, i32immSExt8:$src2),
4616 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4617 def : Pat<(or_is_add GR16:$src1, GR16:$src2),
4618 (ADD16rr GR16:$src1, GR16:$src2)>;
4619 def : Pat<(or_is_add GR32:$src1, GR32:$src2),
4620 (ADD32rr GR32:$src1, GR32:$src2)>;
4621 } // AddedComplexity
4623 //===----------------------------------------------------------------------===//
4624 // EFLAGS-defining Patterns
4625 //===----------------------------------------------------------------------===//
4628 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
4629 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
4630 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
4633 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
4634 (ADD8rm GR8:$src1, addr:$src2)>;
4635 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
4636 (ADD16rm GR16:$src1, addr:$src2)>;
4637 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
4638 (ADD32rm GR32:$src1, addr:$src2)>;
4641 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
4642 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
4643 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
4644 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
4645 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4646 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
4647 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4650 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
4651 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
4652 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
4655 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
4656 (SUB8rm GR8:$src1, addr:$src2)>;
4657 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
4658 (SUB16rm GR16:$src1, addr:$src2)>;
4659 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
4660 (SUB32rm GR32:$src1, addr:$src2)>;
4663 def : Pat<(sub GR8:$src1, imm:$src2),
4664 (SUB8ri GR8:$src1, imm:$src2)>;
4665 def : Pat<(sub GR16:$src1, imm:$src2),
4666 (SUB16ri GR16:$src1, imm:$src2)>;
4667 def : Pat<(sub GR32:$src1, imm:$src2),
4668 (SUB32ri GR32:$src1, imm:$src2)>;
4669 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
4670 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4671 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
4672 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4675 def : Pat<(mul GR16:$src1, GR16:$src2),
4676 (IMUL16rr GR16:$src1, GR16:$src2)>;
4677 def : Pat<(mul GR32:$src1, GR32:$src2),
4678 (IMUL32rr GR32:$src1, GR32:$src2)>;
4681 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
4682 (IMUL16rm GR16:$src1, addr:$src2)>;
4683 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
4684 (IMUL32rm GR32:$src1, addr:$src2)>;
4687 def : Pat<(mul GR16:$src1, imm:$src2),
4688 (IMUL16rri GR16:$src1, imm:$src2)>;
4689 def : Pat<(mul GR32:$src1, imm:$src2),
4690 (IMUL32rri GR32:$src1, imm:$src2)>;
4691 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
4692 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4693 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
4694 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4696 // reg = mul mem, imm
4697 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
4698 (IMUL16rmi addr:$src1, imm:$src2)>;
4699 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
4700 (IMUL32rmi addr:$src1, imm:$src2)>;
4701 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
4702 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4703 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
4704 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4706 // Optimize multiply by 2 with EFLAGS result.
4707 let AddedComplexity = 2 in {
4708 def : Pat<(X86smul_flag GR16:$src1, 2), (ADD16rr GR16:$src1, GR16:$src1)>;
4709 def : Pat<(X86smul_flag GR32:$src1, 2), (ADD32rr GR32:$src1, GR32:$src1)>;
4712 // Patterns for nodes that do not produce flags, for instructions that do.
4715 def : Pat<(add GR8:$src , 1), (INC8r GR8:$src)>;
4716 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>;
4717 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>;
4720 def : Pat<(add GR8:$src , -1), (DEC8r GR8:$src)>;
4721 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
4722 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
4725 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
4726 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
4727 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
4730 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
4731 (OR8rm GR8:$src1, addr:$src2)>;
4732 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
4733 (OR16rm GR16:$src1, addr:$src2)>;
4734 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
4735 (OR32rm GR32:$src1, addr:$src2)>;
4738 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
4739 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
4740 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
4741 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
4742 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4743 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
4744 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4747 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
4748 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
4749 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
4752 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
4753 (XOR8rm GR8:$src1, addr:$src2)>;
4754 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
4755 (XOR16rm GR16:$src1, addr:$src2)>;
4756 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
4757 (XOR32rm GR32:$src1, addr:$src2)>;
4760 def : Pat<(xor GR8:$src1, imm:$src2),
4761 (XOR8ri GR8:$src1, imm:$src2)>;
4762 def : Pat<(xor GR16:$src1, imm:$src2),
4763 (XOR16ri GR16:$src1, imm:$src2)>;
4764 def : Pat<(xor GR32:$src1, imm:$src2),
4765 (XOR32ri GR32:$src1, imm:$src2)>;
4766 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
4767 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4768 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
4769 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4772 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
4773 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
4774 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
4777 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
4778 (AND8rm GR8:$src1, addr:$src2)>;
4779 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
4780 (AND16rm GR16:$src1, addr:$src2)>;
4781 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
4782 (AND32rm GR32:$src1, addr:$src2)>;
4785 def : Pat<(and GR8:$src1, imm:$src2),
4786 (AND8ri GR8:$src1, imm:$src2)>;
4787 def : Pat<(and GR16:$src1, imm:$src2),
4788 (AND16ri GR16:$src1, imm:$src2)>;
4789 def : Pat<(and GR32:$src1, imm:$src2),
4790 (AND32ri GR32:$src1, imm:$src2)>;
4791 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
4792 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
4793 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
4794 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
4796 //===----------------------------------------------------------------------===//
4797 // Floating Point Stack Support
4798 //===----------------------------------------------------------------------===//
4800 include "X86InstrFPStack.td"
4802 //===----------------------------------------------------------------------===//
4804 //===----------------------------------------------------------------------===//
4806 include "X86Instr64bit.td"
4808 //===----------------------------------------------------------------------===//
4809 // SIMD support (SSE, MMX and AVX)
4810 //===----------------------------------------------------------------------===//
4812 include "X86InstrFragmentsSIMD.td"
4814 //===----------------------------------------------------------------------===//
4815 // XMM Floating point support (requires SSE / SSE2)
4816 //===----------------------------------------------------------------------===//
4818 include "X86InstrSSE.td"
4820 //===----------------------------------------------------------------------===//
4821 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
4822 //===----------------------------------------------------------------------===//
4824 include "X86InstrMMX.td"