1 //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Format specifies the encoding used by the instruction. This is part of the
17 // ad-hoc solution used to emit machine instruction encodings by our machine
19 class Format<bits<5> val> {
23 def Pseudo : Format<0>; def RawFrm : Format<1>;
24 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
25 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
26 def MRMSrcMem : Format<6>;
27 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
28 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
29 def MRM6r : Format<22>; def MRM7r : Format<23>;
30 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
31 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
32 def MRM6m : Format<30>; def MRM7m : Format<31>;
34 // ImmType - This specifies the immediate type used by an instruction. This is
35 // part of the ad-hoc solution used to emit machine instruction encodings by our
36 // machine code emitter.
37 class ImmType<bits<2> val> {
40 def NoImm : ImmType<0>;
41 def Imm8 : ImmType<1>;
42 def Imm16 : ImmType<2>;
43 def Imm32 : ImmType<3>;
45 // MemType - This specifies the immediate type used by an instruction. This is
46 // part of the ad-hoc solution used to emit machine instruction encodings by our
47 // machine code emitter.
48 class MemType<bits<3> val> {
51 def NoMem : MemType<0>;
52 def Mem8 : MemType<1>;
53 def Mem16 : MemType<2>;
54 def Mem32 : MemType<3>;
55 def Mem64 : MemType<4>;
56 def Mem80 : MemType<5>;
57 def Mem128 : MemType<6>;
59 // FPFormat - This specifies what form this FP instruction has. This is used by
60 // the Floating-Point stackifier pass.
61 class FPFormat<bits<3> val> {
64 def NotFP : FPFormat<0>;
65 def ZeroArgFP : FPFormat<1>;
66 def OneArgFP : FPFormat<2>;
67 def OneArgFPRW : FPFormat<3>;
68 def TwoArgFP : FPFormat<4>;
69 def CompareFP : FPFormat<5>;
70 def CondMovFP : FPFormat<6>;
71 def SpecialFP : FPFormat<7>;
74 class X86Inst<string nam, bits<8> opcod, Format f, MemType m, ImmType i> : Instruction {
75 let Namespace = "X86";
78 bits<8> Opcode = opcod;
80 bits<5> FormBits = Form.Value;
82 bits<3> MemTypeBits = MemT.Value;
84 bits<2> ImmTypeBits = ImmT.Value;
87 // Attributes specific to X86 instructions...
89 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
91 // Flag whether implicit register usage is printed after the instruction.
92 bit printImplicitUsesAfter = 0;
94 bits<4> Prefix = 0; // Which prefix byte does this inst have?
95 FPFormat FPForm; // What flavor of FP instruction is this?
96 bits<3> FPFormBits = 0;
99 class Imp<list<Register> uses, list<Register> defs> {
100 list<Register> Uses = uses;
101 list<Register> Defs = defs;
104 // II - InstructionInfo - this will eventually replace the I class.
105 class II<dag ops, string AsmStr> {
106 dag OperandList = ops;
107 string AsmString = AsmStr;
111 // Prefix byte classes which are used to indicate to the ad-hoc machine code
112 // emitter that various prefix bytes are required.
113 class OpSize { bit hasOpSizePrefix = 1; }
114 class TB { bits<4> Prefix = 1; }
115 class REP { bits<4> Prefix = 2; }
116 class D8 { bits<4> Prefix = 3; }
117 class D9 { bits<4> Prefix = 4; }
118 class DA { bits<4> Prefix = 5; }
119 class DB { bits<4> Prefix = 6; }
120 class DC { bits<4> Prefix = 7; }
121 class DD { bits<4> Prefix = 8; }
122 class DE { bits<4> Prefix = 9; }
123 class DF { bits<4> Prefix = 10; }
126 //===----------------------------------------------------------------------===//
127 // Instruction templates...
129 class I<bits<8> o, Format f, dag ops, string asm> : X86Inst<"", o, f, NoMem, NoImm>, II<ops, asm>;
131 class Im<string n, bits<8> o, Format f, MemType m> : X86Inst<n, o, f, m, NoImm>;
132 class Im8 <string n, bits<8> o, Format f> : Im<n, o, f, Mem8 >;
133 class Im16<string n, bits<8> o, Format f> : Im<n, o, f, Mem16>;
134 class Im32<string n, bits<8> o, Format f> : Im<n, o, f, Mem32>;
136 class Ii<bits<8> o, Format f, ImmType i> : X86Inst<"", o, f, NoMem, i>;
137 class Ii8 <bits<8> o, Format f, dag ops, string asm> : Ii<o, f, Imm8 >, II<ops, asm>;
138 class Ii16<bits<8> o, Format f, dag ops, string asm> : Ii<o, f, Imm16>, II<ops, asm>;
139 class Ii32<bits<8> o, Format f, dag ops, string asm> : Ii<o, f, Imm32>, II<ops, asm>;
141 class Im8i8 <string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem8 , Imm8 >;
142 class Im16i16<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem16, Imm16>;
143 class Im32i32<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem32, Imm32>;
145 class Im16i8<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem16, Imm8>;
146 class Im32i8<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem32, Imm8>;
148 //===----------------------------------------------------------------------===//
149 // Instruction list...
152 def PHI : I<0, Pseudo, (ops), "PHINODE">; // PHI node.
153 def NOOP : I<0x90, RawFrm, (ops), "nop">; // nop
155 def ADJCALLSTACKDOWN : I<0, Pseudo, (ops), "#ADJCALLSTACKDOWN">;
156 def ADJCALLSTACKUP : I<0, Pseudo, (ops), "#ADJCALLSTACKUP">;
157 def IMPLICIT_USE : I<0, Pseudo, (ops), "#IMPLICIT_USE">;
158 def IMPLICIT_DEF : I<0, Pseudo, (ops), "#IMPLICIT_DEF">;
159 let isTerminator = 1 in
160 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
161 def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL">;
163 //===----------------------------------------------------------------------===//
164 // Control Flow Instructions...
167 // Return instruction...
168 let isTerminator = 1, isReturn = 1, isBarrier = 1 in
169 def RET : I<0xC3, RawFrm, (ops), "ret">;
171 // All branches are RawFrm, Void, Branch, and Terminators
172 let isBranch = 1, isTerminator = 1 in
173 class IBr<bits<8> opcode, dag ops, string asm> : I<opcode, RawFrm, ops, asm>;
176 def JMP : IBr<0xE9, (ops i32imm:$dst), "jmp $dst">;
177 def JB : IBr<0x82, (ops i32imm:$dst), "jb $dst">, TB;
178 def JAE : IBr<0x83, (ops i32imm:$dst), "jae $dst">, TB;
179 def JE : IBr<0x84, (ops i32imm:$dst), "je $dst">, TB;
180 def JNE : IBr<0x85, (ops i32imm:$dst), "jne $dst">, TB;
181 def JBE : IBr<0x86, (ops i32imm:$dst), "jbe $dst">, TB;
182 def JA : IBr<0x87, (ops i32imm:$dst), "ja $dst">, TB;
183 def JS : IBr<0x88, (ops i32imm:$dst), "js $dst">, TB;
184 def JNS : IBr<0x89, (ops i32imm:$dst), "jns $dst">, TB;
185 def JL : IBr<0x8C, (ops i32imm:$dst), "jl $dst">, TB;
186 def JGE : IBr<0x8D, (ops i32imm:$dst), "jge $dst">, TB;
187 def JLE : IBr<0x8E, (ops i32imm:$dst), "jle $dst">, TB;
188 def JG : IBr<0x8F, (ops i32imm:$dst), "jg $dst">, TB;
191 //===----------------------------------------------------------------------===//
192 // Call Instructions...
195 // All calls clobber the non-callee saved registers...
196 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6] in {
197 def CALLpcrel32 : X86Inst<"call", 0xE8, RawFrm, NoMem, NoImm>; // FIXME: 'call' doesn't allow 'OFFSET'
198 def CALL32r : I<0xFF, MRM2r, (ops R32:$dst), "call $dst">;
199 def CALL32m : Im32<"call", 0xFF, MRM2m>;
203 //===----------------------------------------------------------------------===//
204 // Miscellaneous Instructions...
206 def LEAVE : I<0xC9, RawFrm,
207 (ops), "leave">, Imp<[EBP,ESP],[EBP,ESP]>;
208 def POP32r : I<0x58, AddRegFrm,
209 (ops R32:$reg), "pop $reg">, Imp<[ESP],[ESP]>;
211 let isTwoAddress = 1 in // R32 = bswap R32
212 def BSWAP32r : I<0xC8, AddRegFrm,
213 (ops R32:$dst, R32:$src), "bswap $dst">, TB;
215 def XCHG8rr : I<0x86, MRMDestReg, // xchg R8, R8
216 (ops R8:$src1, R8:$src2), "xchg $src1, $src2">;
217 def XCHG16rr : I<0x87, MRMDestReg, // xchg R16, R16
218 (ops R16:$src1, R16:$src2), "xchg $src1, $src2">, OpSize;
219 def XCHG32rr : I<0x87, MRMDestReg, // xchg R32, R32
220 (ops R32:$src1, R32:$src2), "xchg $src1, $src2">;
222 def XCHG8mr : Im8 <"xchg", 0x86, MRMDestMem>; // xchg [mem8], R8
223 def XCHG16mr : Im16<"xchg", 0x87, MRMDestMem>, OpSize; // xchg [mem16], R16
224 def XCHG32mr : Im32<"xchg", 0x87, MRMDestMem>; // xchg [mem32], R32
225 def XCHG8rm : Im8 <"xchg", 0x86, MRMSrcMem >; // xchg R8, [mem8]
226 def XCHG16rm : Im16<"xchg", 0x87, MRMSrcMem >, OpSize; // xchg R16, [mem16]
227 def XCHG32rm : Im32<"xchg", 0x87, MRMSrcMem >; // xchg R32, [mem32]
229 def LEA16r : Im32<"lea", 0x8D, MRMSrcMem>, OpSize; // R16 = lea [mem]
230 def LEA32r : Im32<"lea", 0x8D, MRMSrcMem>; // R32 = lea [mem]
233 def REP_MOVSB : I<0xA4, RawFrm, (ops), "rep movsb">,
234 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
235 def REP_MOVSW : I<0xA5, RawFrm, (ops), "rep movsw">,
236 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize;
237 def REP_MOVSD : I<0xA5, RawFrm, (ops), "rep movsd">,
238 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
240 def REP_STOSB : I<0xAA, RawFrm, (ops), "rep stosb">,
241 Imp<[AL,ECX,EDI], [ECX,EDI]>, REP;
242 def REP_STOSW : I<0xAB, RawFrm, (ops), "rep stosw">,
243 Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize;
244 def REP_STOSD : I<0xAB, RawFrm, (ops), "rep stosd">,
245 Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP;
248 //===----------------------------------------------------------------------===//
249 // Input/Output Instructions...
251 def IN8rr : I<0xEC, RawFrm, (ops),
252 "in %AL, %DX">, Imp<[DX], [AL]>;
253 def IN16rr : I<0xED, RawFrm, (ops),
254 "in %AX, %DX">, Imp<[DX], [AX]>, OpSize;
255 def IN32rr : I<0xED, RawFrm, (ops),
256 "in %EAX, %DX">, Imp<[DX],[EAX]>;
258 def IN8ri : Ii16<0xE4, RawFrm, (ops i16imm:$port),
259 "in %AL, $port">, Imp<[], [AL]>;
260 def IN16ri : Ii16<0xE5, RawFrm, (ops i16imm:$port),
261 "in %AX, $port">, Imp<[], [AX]>, OpSize;
262 def IN32ri : Ii16<0xE5, RawFrm, (ops i16imm:$port),
263 "in %EAX, $port">, Imp<[],[EAX]>;
265 def OUT8rr : I<0xEE, RawFrm, (ops),
266 "out %DX, %AL">, Imp<[DX, AL], []>;
267 def OUT16rr : I<0xEF, RawFrm, (ops),
268 "out %DX, %AX">, Imp<[DX, AX], []>, OpSize;
269 def OUT32rr : I<0xEF, RawFrm, (ops),
270 "out %DX, %EAX">, Imp<[DX, EAX], []>;
272 def OUT8ir : Ii16<0xE6, RawFrm, (ops i16imm:$port),
273 "out $port, %AL">, Imp<[AL], []>;
274 def OUT16ir : Ii16<0xE7, RawFrm, (ops i16imm:$port),
275 "out $port, %AX">, Imp<[AX], []>, OpSize;
276 def OUT32ir : Ii16<0xE7, RawFrm, (ops i16imm:$port),
277 "out $port, %EAX">, Imp<[EAX], []>;
279 //===----------------------------------------------------------------------===//
280 // Move Instructions...
282 def MOV8rr : I<0x88, MRMDestReg, (ops R8 :$dst, R8 :$src), "mov $dst, $src">;
283 def MOV16rr : I<0x89, MRMDestReg, (ops R16:$dst, R16:$src), "mov $dst, $src">, OpSize;
284 def MOV32rr : I<0x89, MRMDestReg, (ops R32:$dst, R32:$src), "mov $dst, $src">;
285 def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops R8 :$dst, i8imm :$src), "mov $dst, $src">;
286 def MOV16ri : Ii16<0xB8, AddRegFrm, (ops R16:$dst, i16imm:$src), "mov $dst, $src">, OpSize;
287 def MOV32ri : Ii32<0xB8, AddRegFrm, (ops R32:$dst, i32imm:$src), "mov $dst, $src">;
288 def MOV8mi : Im8i8 <"mov", 0xC6, MRM0m >; // [mem8] = imm8
289 def MOV16mi : Im16i16<"mov", 0xC7, MRM0m >, OpSize; // [mem16] = imm16
290 def MOV32mi : Im32i32<"mov", 0xC7, MRM0m >; // [mem32] = imm32
292 def MOV8rm : Im8 <"mov", 0x8A, MRMSrcMem>; // R8 = [mem8]
293 def MOV16rm : Im16 <"mov", 0x8B, MRMSrcMem>, OpSize; // R16 = [mem16]
294 def MOV32rm : Im32 <"mov", 0x8B, MRMSrcMem>; // R32 = [mem32]
296 def MOV8mr : Im8 <"mov", 0x88, MRMDestMem>; // [mem8] = R8
297 def MOV16mr : Im16 <"mov", 0x89, MRMDestMem>, OpSize; // [mem16] = R16
298 def MOV32mr : Im32 <"mov", 0x89, MRMDestMem>; // [mem32] = R32
300 //===----------------------------------------------------------------------===//
301 // Fixed-Register Multiplication and Division Instructions...
304 // Extra precision multiplication
305 def MUL8r : I<0xF6, MRM4r, (ops R8:$src), "mul $src">,
306 Imp<[AL],[AX]>; // AL,AH = AL*R8
307 def MUL16r : I<0xF7, MRM4r, (ops R16:$src), "mul $src">,
308 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
309 def MUL32r : I<0xF7, MRM4r, (ops R32:$src), "mul $src">,
310 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
311 def MUL8m : Im8 <"mul", 0xF6, MRM4m>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
312 def MUL16m : Im16<"mul", 0xF7, MRM4m>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*[mem16]
313 def MUL32m : Im32<"mul", 0xF7, MRM4m>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
315 // unsigned division/remainder
316 def DIV8r : I<0xF6, MRM6r, (ops R8:$src), "div $src">,
317 Imp<[AX],[AX]>; // AX/r8 = AL,AH
318 def DIV16r : I<0xF7, MRM6r, (ops R16:$src), "div $src">,
319 Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
320 def DIV32r : I<0xF7, MRM6r, (ops R32:$src), "div $src">,
321 Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
322 def DIV8m : Im8 <"div", 0xF6, MRM6m>, Imp<[AX],[AX]>; // AX/[mem8] = AL,AH
323 def DIV16m : Im16<"div", 0xF7, MRM6m>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[mem16] = AX,DX
324 def DIV32m : Im32<"div", 0xF7, MRM6m>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX
326 // Signed division/remainder.
327 def IDIV8r : I<0xF6, MRM7r, (ops R8:$src), "idiv $src">,
328 Imp<[AX],[AX]>; // AX/r8 = AL,AH
329 def IDIV16r: I<0xF7, MRM7r, (ops R16:$src), "idiv $src">,
330 Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
331 def IDIV32r: I<0xF7, MRM7r, (ops R32:$src), "idiv $src">,
332 Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
333 def IDIV8m : Im8 <"idiv",0xF6, MRM7m>, Imp<[AX],[AX]>; // AX/[mem8] = AL,AH
334 def IDIV16m: Im16<"idiv",0xF7, MRM7m>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[mem16] = AX,DX
335 def IDIV32m: Im32<"idiv",0xF7, MRM7m>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX
337 // Sign-extenders for division.
338 def CBW : I<0x98, RawFrm, (ops), "cbw">, Imp<[AL],[AH]>; // AX = signext(AL)
339 def CWD : I<0x99, RawFrm, (ops), "cwd">, Imp<[AX],[DX]>; // DX:AX = signext(AX)
340 def CDQ : I<0x99, RawFrm, (ops), "cdq">, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX)
343 //===----------------------------------------------------------------------===//
344 // Two address Instructions...
346 let isTwoAddress = 1 in {
349 def CMOVB16rr : I<0x42, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
350 "cmovb $dst, $src2">, TB, OpSize; // if <u, R16 = R16
351 def CMOVB16rm : Im16<"cmovb", 0x42, MRMSrcMem>, TB, OpSize; // if <u, R16 = [mem16]
352 def CMOVB32rr : I<0x42, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
353 "cmovb $dst, $src2">, TB; // if <u, R32 = R32
354 def CMOVB32rm : Im32<"cmovb", 0x42, MRMSrcMem>, TB; // if <u, R32 = [mem32]
356 def CMOVAE16rr: I<0x43, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
357 "cmovae $dst, $src2">, TB, OpSize; // if >=u, R16 = R16
358 def CMOVAE16rm: Im16<"cmovae", 0x43, MRMSrcMem>, TB, OpSize; // if >=u, R16 = [mem16]
359 def CMOVAE32rr: I<0x43, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
360 "cmovae $dst, $src2">, TB; // if >=u, R32 = R32
361 def CMOVAE32rm: Im32<"cmovae", 0x43, MRMSrcMem>, TB; // if >=u, R32 = [mem32]
363 def CMOVE16rr : I<0x44, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
364 "cmove $dst, $src2">, TB, OpSize; // if ==, R16 = R16
365 def CMOVE16rm : Im16<"cmove", 0x44, MRMSrcMem>, TB, OpSize; // if ==, R16 = [mem16]
366 def CMOVE32rr : I<0x44, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
367 "cmove $dst, $src2">, TB; // if ==, R32 = R32
368 def CMOVE32rm : Im32<"cmove", 0x44, MRMSrcMem>, TB; // if ==, R32 = [mem32]
370 def CMOVNE16rr: I<0x45, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
371 "cmovne $dst, $src2">, TB, OpSize; // if !=, R16 = R16
372 def CMOVNE16rm: Im16<"cmovne",0x45, MRMSrcMem>, TB, OpSize; // if !=, R16 = [mem16]
373 def CMOVNE32rr: I<0x45, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
374 "cmovne $dst, $src2">, TB; // if !=, R32 = R32
375 def CMOVNE32rm: Im32<"cmovne",0x45, MRMSrcMem>, TB; // if !=, R32 = [mem32]
377 def CMOVBE16rr: I<0x46, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
378 "cmovbe $dst, $src2">, TB, OpSize; // if <=u, R16 = R16
379 def CMOVBE16rm: Im16<"cmovbe",0x46, MRMSrcMem>, TB, OpSize; // if <=u, R16 = [mem16]
380 def CMOVBE32rr: I<0x46, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
381 "cmovbe $dst, $src2">, TB; // if <=u, R32 = R32
382 def CMOVBE32rm: Im32<"cmovbe",0x46, MRMSrcMem>, TB; // if <=u, R32 = [mem32]
384 def CMOVA16rr : I<0x47, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
385 "cmova $dst, $src2">, TB, OpSize; // if >u, R16 = R16
386 def CMOVA16rm : Im16<"cmova", 0x47, MRMSrcMem>, TB, OpSize; // if >u, R16 = [mem16]
387 def CMOVA32rr : I<0x47, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
388 "cmova $dst, $src2">, TB; // if >u, R32 = R32
389 def CMOVA32rm : Im32<"cmova", 0x47, MRMSrcMem>, TB; // if >u, R32 = [mem32]
391 def CMOVS16rr : I<0x48, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
392 "cmovs $dst, $src2">, TB, OpSize; // if signed, R16 = R16
393 def CMOVS16rm : Im16<"cmovs", 0x48, MRMSrcMem>, TB, OpSize; // if signed, R16 = [mem16]
394 def CMOVS32rr : I<0x48, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
395 "cmovs $dst, $src2">, TB; // if signed, R32 = R32
396 def CMOVS32rm : Im32<"cmovs", 0x48, MRMSrcMem>, TB; // if signed, R32 = [mem32]
398 def CMOVNS16rr: I<0x49, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
399 "cmovns $dst, $src2">, TB, OpSize; // if !signed, R16 = R16
400 def CMOVNS16rm: Im16<"cmovns",0x49, MRMSrcMem>, TB, OpSize; // if !signed, R16 = [mem16]
401 def CMOVNS32rr: I<0x49, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
402 "cmovns $dst, $src2">, TB; // if !signed, R32 = R32
403 def CMOVNS32rm: Im32<"cmovns",0x49, MRMSrcMem>, TB; // if !signed, R32 = [mem32]
405 def CMOVL16rr : I<0x4C, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
406 "cmovl $dst, $src2">, TB, OpSize; // if <s, R16 = R16
407 def CMOVL16rm : Im16<"cmovl", 0x4C, MRMSrcMem>, TB, OpSize; // if <s, R16 = [mem16]
408 def CMOVL32rr : I<0x4C, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
409 "cmovl $dst, $src2">, TB; // if <s, R32 = R32
410 def CMOVL32rm : Im32<"cmovl", 0x4C, MRMSrcMem>, TB; // if <s, R32 = [mem32]
412 def CMOVGE16rr: I<0x4D, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
413 "cmovge $dst, $src2">, TB, OpSize; // if >=s, R16 = R16
414 def CMOVGE16rm: Im16<"cmovge",0x4D, MRMSrcMem>, TB, OpSize; // if >=s, R16 = [mem16]
415 def CMOVGE32rr: I<0x4D, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
416 "cmovge $dst, $src2">, TB; // if >=s, R32 = R32
417 def CMOVGE32rm: Im32<"cmovge",0x4D, MRMSrcMem>, TB; // if >=s, R32 = [mem32]
419 def CMOVLE16rr: I<0x4E, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
420 "cmovle $dst, $src2">, TB, OpSize; // if <=s, R16 = R16
421 def CMOVLE16rm: Im16<"cmovle",0x4E, MRMSrcMem>, TB, OpSize; // if <=s, R16 = [mem16]
422 def CMOVLE32rr: I<0x4E, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
423 "cmovle $dst, $src2">, TB; // if <=s, R32 = R32
424 def CMOVLE32rm: Im32<"cmovle",0x4E, MRMSrcMem>, TB; // if <=s, R32 = [mem32]
426 def CMOVG16rr : I<0x4F, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
427 "cmovg $dst, $src2">, TB, OpSize; // if >s, R16 = R16
428 def CMOVG16rm : Im16<"cmovg", 0x4F, MRMSrcMem>, TB, OpSize; // if >s, R16 = [mem16]
429 def CMOVG32rr : I<0x4F, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
430 "cmovg $dst, $src2">, TB; // if >s, R32 = R32
431 def CMOVG32rm : Im32<"cmovg", 0x4F, MRMSrcMem>, TB; // if >s, R32 = [mem32]
433 // unary instructions
434 def NEG8r : I<0xF6, MRM3r, (ops R8 :$dst, R8 :$src), "neg $dst">;
435 def NEG16r : I<0xF7, MRM3r, (ops R16:$dst, R16:$src), "neg $dst">, OpSize;
436 def NEG32r : I<0xF7, MRM3r, (ops R32:$dst, R32:$src), "neg $dst">;
437 def NEG8m : Im8 <"neg", 0xF6, MRM3m>; // [mem8] = -[mem8] = 0-[mem8]
438 def NEG16m : Im16<"neg", 0xF7, MRM3m>, OpSize; // [mem16] = -[mem16] = 0-[mem16]
439 def NEG32m : Im32<"neg", 0xF7, MRM3m>; // [mem32] = -[mem32] = 0-[mem32]
441 def NOT8r : I<0xF6, MRM2r, (ops R8 :$dst, R8 :$src), "not $dst">;
442 def NOT16r : I<0xF7, MRM2r, (ops R16:$dst, R16:$src), "not $dst">, OpSize;
443 def NOT32r : I<0xF7, MRM2r, (ops R32:$dst, R32:$src), "not $dst">;
444 def NOT8m : Im8 <"not", 0xF6, MRM2m>; // [mem8] = ~[mem8] = [mem8^-1]
445 def NOT16m : Im16<"not", 0xF7, MRM2m>, OpSize; // [mem16] = ~[mem16] = [mem16^-1]
446 def NOT32m : Im32<"not", 0xF7, MRM2m>; // [mem32] = ~[mem32] = [mem32^-1]
448 def INC8r : I<0xFE, MRM0r, (ops R8 :$dst, R8 :$src), "inc $dst">;
449 def INC16r : I<0xFF, MRM0r, (ops R16:$dst, R16:$src), "inc $dst">, OpSize;
450 def INC32r : I<0xFF, MRM0r, (ops R32:$dst, R32:$src), "inc $dst">;
451 def INC8m : Im8 <"inc", 0xFE, MRM0m>; // ++R8
452 def INC16m : Im16<"inc", 0xFF, MRM0m>, OpSize; // ++R16
453 def INC32m : Im32<"inc", 0xFF, MRM0m>; // ++R32
455 def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec $dst">;
456 def DEC16r : I<0xFF, MRM1r, (ops R16:$dst, R16:$src), "dec $dst">, OpSize;
457 def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec $dst">;
458 def DEC8m : Im8 <"dec", 0xFE, MRM1m>; // --[mem8]
459 def DEC16m : Im16<"dec", 0xFF, MRM1m>, OpSize; // --[mem16]
460 def DEC32m : Im32<"dec", 0xFF, MRM1m>; // --[mem32]
462 // Logical operators...
463 def AND8rr : I<0x20, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), "and $dst, $src2">;
464 def AND16rr : I<0x21, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), "and $dst, $src2">, OpSize;
465 def AND32rr : I<0x21, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), "and $dst, $src2">;
466 def AND8mr : Im8 <"and", 0x20, MRMDestMem>; // [mem8] &= R8
467 def AND16mr : Im16 <"and", 0x21, MRMDestMem>, OpSize; // [mem16] &= R16
468 def AND32mr : Im32 <"and", 0x21, MRMDestMem>; // [mem32] &= R32
469 def AND8rm : Im8 <"and", 0x22, MRMSrcMem >; // R8 &= [mem8]
470 def AND16rm : Im16 <"and", 0x23, MRMSrcMem >, OpSize; // R16 &= [mem16]
471 def AND32rm : Im32 <"and", 0x23, MRMSrcMem >; // R32 &= [mem32]
473 def AND8ri : Ii8 <0x80, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm :$src2),
475 def AND16ri : Ii16<0x81, MRM4r, (ops R16:$dst, R16:$src1, i16imm:$src2),
476 "and $dst, $src2">, OpSize;
477 def AND32ri : Ii32<0x81, MRM4r, (ops R32:$dst, R32:$src1, i32imm:$src2),
479 def AND8mi : Im8i8 <"and", 0x80, MRM4m >; // [mem8] &= imm8
480 def AND16mi : Im16i16<"and", 0x81, MRM4m >, OpSize; // [mem16] &= imm16
481 def AND32mi : Im32i32<"and", 0x81, MRM4m >; // [mem32] &= imm32
483 def AND16ri8 : Ii8<0x83, MRM4r, (ops R16:$dst, R16:$src1, i8imm:$src2),
484 "and $dst, $src2" >, OpSize;
485 def AND32ri8 : Ii8<0x83, MRM4r, (ops R32:$dst, R32:$src1, i8imm:$src2),
487 def AND16mi8 : Im16i8<"and", 0x83, MRM4m >, OpSize; // [mem16] &= imm8
488 def AND32mi8 : Im32i8<"and", 0x83, MRM4m >; // [mem32] &= imm8
491 def OR8rr : I<0x08, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
493 def OR16rr : I<0x09, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
494 "or $dst, $src2">, OpSize;
495 def OR32rr : I<0x09, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
497 def OR8mr : Im8 <"or" , 0x08, MRMDestMem>; // [mem8] |= R8
498 def OR16mr : Im16 <"or" , 0x09, MRMDestMem>, OpSize; // [mem16] |= R16
499 def OR32mr : Im32 <"or" , 0x09, MRMDestMem>; // [mem32] |= R32
500 def OR8rm : Im8 <"or" , 0x0A, MRMSrcMem >; // R8 |= [mem8]
501 def OR16rm : Im16 <"or" , 0x0B, MRMSrcMem >, OpSize; // R16 |= [mem16]
502 def OR32rm : Im32 <"or" , 0x0B, MRMSrcMem >; // R32 |= [mem32]
504 def OR8ri : Ii8 <0x80, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
506 def OR16ri : Ii16<0x81, MRM1r, (ops R16:$dst, R16:$src1, i16imm:$src2),
507 "or $dst, $src2">, OpSize;
508 def OR32ri : Ii32<0x81, MRM1r, (ops R32:$dst, R32:$src1, i32imm:$src2),
510 def OR8mi : Im8i8 <"or" , 0x80, MRM1m>; // [mem8] |= imm8
511 def OR16mi : Im16i16<"or" , 0x81, MRM1m>, OpSize; // [mem16] |= imm16
512 def OR32mi : Im32i32<"or" , 0x81, MRM1m>; // [mem32] |= imm32
514 def OR16ri8 : Ii8<0x83, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
515 "or $dst, $src2">, OpSize;
516 def OR32ri8 : Ii8<0x83, MRM1r, (ops R32:$dst, R32:$src1, i8imm:$src2),
518 def OR16mi8 : Im16i8<"or" , 0x83, MRM1m>, OpSize; // [mem16] |= imm8
519 def OR32mi8 : Im32i8<"or" , 0x83, MRM1m>; // [mem32] |= imm8
522 def XOR8rr : I<0x30, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), "xor $dst, $src2">;
523 def XOR16rr : I<0x31, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), "xor $dst, $src2">, OpSize;
524 def XOR32rr : I<0x31, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), "xor $dst, $src2">;
525 def XOR8mr : Im8 <"xor", 0x30, MRMDestMem>; // [mem8] ^= R8
526 def XOR16mr : Im16 <"xor", 0x31, MRMDestMem>, OpSize; // [mem16] ^= R16
527 def XOR32mr : Im32 <"xor", 0x31, MRMDestMem>; // [mem32] ^= R32
528 def XOR8rm : Im8 <"xor", 0x32, MRMSrcMem >; // R8 ^= [mem8]
529 def XOR16rm : Im16 <"xor", 0x33, MRMSrcMem >, OpSize; // R16 ^= [mem16]
530 def XOR32rm : Im32 <"xor", 0x33, MRMSrcMem >; // R32 ^= [mem32]
532 def XOR8ri : Ii8 <0x80, MRM6r, (ops R8:$dst, R8:$src1, i8imm:$src2), "xor $dst, $src2">;
533 def XOR16ri : Ii16 <0x81, MRM6r, (ops R16:$dst, R16:$src1, i16imm:$src2), "xor $dst, $src2">, OpSize;
534 def XOR32ri : Ii32 <0x81, MRM6r, (ops R32:$dst, R32:$src1, i32imm:$src2), "xor $dst, $src2">;
535 def XOR8mi : Im8i8 <"xor", 0x80, MRM6m >; // [mem8] ^= R8
536 def XOR16mi : Im16i16<"xor", 0x81, MRM6m >, OpSize; // [mem16] ^= R16
537 def XOR32mi : Im32i32<"xor", 0x81, MRM6m >; // [mem32] ^= R32
539 def XOR16ri8 : Ii8<0x83, MRM6r, (ops R16:$dst, R16:$src1, i8imm:$src2),
540 "xor $dst, $src2">, OpSize;
541 def XOR32ri8 : Ii8<0x83, MRM6r, (ops R32:$dst, R32:$src1, i8imm:$src2),
543 def XOR16mi8 : Im16i8<"xor", 0x83, MRM6m >, OpSize; // [mem16] ^= imm8
544 def XOR32mi8 : Im32i8<"xor", 0x83, MRM6m >; // [mem32] ^= imm8
546 // Shift instructions
547 // FIXME: provide shorter instructions when imm8 == 1
548 let Uses = [CL], printImplicitUsesAfter = 1 in {
549 def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src), "shl $dst, %CL">;
550 def SHL16rCL : I<0xD3, MRM4r, (ops R16:$dst, R16:$src), "shl $dst, %CL">, OpSize;
551 def SHL32rCL : I<0xD3, MRM4r, (ops R32:$dst, R32:$src), "shl $dst, %CL">;
552 def SHL8mCL : Im8 <"shl", 0xD2, MRM4m > ; // [mem8] <<= cl
553 def SHL16mCL : Im16 <"shl", 0xD3, MRM4m >, OpSize; // [mem16] <<= cl
554 def SHL32mCL : Im32 <"shl", 0xD3, MRM4m > ; // [mem32] <<= cl
557 def SHL8ri : Ii8<0xC0, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
559 def SHL16ri : Ii8<0xC1, MRM4r, (ops R16:$dst, R16:$src1, i8imm:$src2),
560 "shl $dst, $src2">, OpSize;
561 def SHL32ri : Ii8<0xC1, MRM4r, (ops R32:$dst, R32:$src1, i8imm:$src2),
563 def SHL8mi : Im8i8 <"shl", 0xC0, MRM4m >; // [mem8] <<= imm8
564 def SHL16mi : Im16i8<"shl", 0xC1, MRM4m >, OpSize; // [mem16] <<= imm8
565 def SHL32mi : Im32i8<"shl", 0xC1, MRM4m >; // [mem32] <<= imm8
567 let Uses = [CL], printImplicitUsesAfter = 1 in {
568 def SHR8rCL : I<0xD2, MRM5r, (ops R8 :$dst, R8 :$src), "shr $dst, %CL">;
569 def SHR16rCL : I<0xD3, MRM5r, (ops R16:$dst, R16:$src), "shr $dst, %CL">, OpSize;
570 def SHR32rCL : I<0xD3, MRM5r, (ops R32:$dst, R32:$src), "shr $dst, %CL">;
571 def SHR8mCL : Im8 <"shr", 0xD2, MRM5m > ; // [mem8] >>= cl
572 def SHR16mCL : Im16 <"shr", 0xD3, MRM5m >, OpSize; // [mem16] >>= cl
573 def SHR32mCL : Im32 <"shr", 0xD3, MRM5m > ; // [mem32] >>= cl
576 def SHR8ri : Ii8 <0xC0, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2), "shr $dst, $src2">;
577 def SHR16ri : Ii8 <0xC1, MRM5r, (ops R16:$dst, R16:$src1, i8imm:$src2), "shr $dst, $src2">, OpSize;
578 def SHR32ri : Ii8 <0xC1, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2), "shr $dst, $src2">;
579 def SHR8mi : Im8i8 <"shr", 0xC0, MRM5m >; // [mem8] >>= imm8
580 def SHR16mi : Im16i8<"shr", 0xC1, MRM5m >, OpSize; // [mem16] >>= imm8
581 def SHR32mi : Im32i8<"shr", 0xC1, MRM5m >; // [mem32] >>= imm8
583 let Uses = [CL], printImplicitUsesAfter = 1 in {
584 def SAR8rCL : I<0xD2, MRM7r, (ops R8 :$dst, R8 :$src), "sar $dst, %CL">;
585 def SAR16rCL : I<0xD3, MRM7r, (ops R16:$dst, R16:$src), "sar $dst, %CL">, OpSize;
586 def SAR32rCL : I<0xD3, MRM7r, (ops R32:$dst, R32:$src), "sar $dst, %CL">;
587 def SAR8mCL : Im8 <"sar", 0xD2, MRM7m > ; // [mem8] >>>= cl
588 def SAR16mCL : Im16 <"sar", 0xD3, MRM7m >, OpSize; // [mem16] >>>= cl
589 def SAR32mCL : Im32 <"sar", 0xD3, MRM7m > ; // [mem32] >>>= cl
592 def SAR8ri : Ii8<0xC0, MRM7r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
594 def SAR16ri : Ii8<0xC1, MRM7r, (ops R16:$dst, R16:$src1, i8imm:$src2),
595 "sar $dst, $src2">, OpSize;
596 def SAR32ri : Ii8<0xC1, MRM7r, (ops R32:$dst, R32:$src1, i8imm:$src2),
598 def SAR8mi : Im8i8 <"sar", 0xC0, MRM7m >; // [mem8] >>>= imm8
599 def SAR16mi : Im16i8<"sar", 0xC1, MRM7m >, OpSize; // [mem16] >>>= imm8
600 def SAR32mi : Im32i8<"sar", 0xC1, MRM7m >; // [mem32] >>>= imm8
602 let Uses = [CL], printImplicitUsesAfter = 1 in {
603 def SHLD32rrCL : I<0xA5, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
604 "shld $dst, $src2, %CL">, TB;
605 def SHLD32mrCL : Im32 <"shld", 0xA5, MRMDestMem>, TB; // [mem32] <<= [mem32],R32 cl
606 def SHRD32rrCL : I<0xAD, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
607 "shrd $dst, $src2, %CL">, TB;
608 def SHRD32mrCL : Im32 <"shrd", 0xAD, MRMDestMem>, TB; // [mem32] >>= [mem32],R32 cl
611 def SHLD32rri8 : Ii8 <0xA4, MRMDestReg, (ops R8:$dst, R8:$src1, i8imm:$src2),
612 "shld $dst, $src2">, TB;
613 def SHLD32mri8 : Im32i8<"shld", 0xA4, MRMDestMem>, TB; // [mem32] <<= [mem32],R32 imm8
614 def SHRD32rri8 : Ii8 <0xAC, MRMDestReg, (ops R16:$dst, R16:$src1, i8imm:$src2),
615 "shrd $dst, $src2">, TB;
616 def SHRD32mri8 : Im32i8<"shrd", 0xAC, MRMDestMem>, TB; // [mem32] >>= [mem32],R32 imm8
620 def ADD8rr : I<0x00, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), "add $dst, $src2">;
621 def ADD16rr : I<0x01, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), "add $dst, $src2">, OpSize;
622 def ADD32rr : I<0x01, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), "add $dst, $src2">;
623 def ADD8mr : Im8 <"add", 0x00, MRMDestMem>; // [mem8] += R8
624 def ADD16mr : Im16 <"add", 0x01, MRMDestMem>, OpSize; // [mem16] += R16
625 def ADD32mr : Im32 <"add", 0x01, MRMDestMem>; // [mem32] += R32
626 def ADD8rm : Im8 <"add", 0x02, MRMSrcMem >; // R8 += [mem8]
627 def ADD16rm : Im16 <"add", 0x03, MRMSrcMem >, OpSize; // R16 += [mem16]
628 def ADD32rm : Im32 <"add", 0x03, MRMSrcMem >; // R32 += [mem32]
630 def ADD8ri : Ii8 <0x80, MRM0r, (ops R8:$dst, R8:$src1, i8imm:$src2), "add $dst, $src2">;
631 def ADD16ri : Ii16 <0x81, MRM0r, (ops R16:$dst, R16:$src1, i16imm:$src2), "add $dst, $src2">, OpSize;
632 def ADD32ri : Ii32 <0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2), "add $dst, $src2">;
633 def ADD8mi : Im8i8 <"add", 0x80, MRM0m >; // [mem8] += I8
634 def ADD16mi : Im16i16<"add", 0x81, MRM0m >, OpSize; // [mem16] += I16
635 def ADD32mi : Im32i32<"add", 0x81, MRM0m >; // [mem32] += I32
637 def ADD16ri8 : Ii8 <0x83, MRM0r, (ops R16:$dst, R16:$src1, i8imm:$src2), "add $dst, $src2">, OpSize;
638 def ADD32ri8 : Ii8 <0x83, MRM0r, (ops R32:$dst, R32:$src1, i8imm:$src2), "add $dst, $src2">;
639 def ADD16mi8 : Im16i8<"add", 0x83, MRM0m >, OpSize; // [mem16] += I8
640 def ADD32mi8 : Im32i8<"add", 0x83, MRM0m >; // [mem32] += I8
642 def ADC32rr : I<0x11, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), "adc $dst, $src2">;
643 def ADC32mr : Im32 <"adc", 0x11, MRMDestMem>; // [mem32] += R32+Carry
644 def ADC32rm : Im32 <"adc", 0x13, MRMSrcMem >; // R32 += [mem32]+Carry
645 def ADC32ri : Ii32 <0x81, MRM2r, (ops R32:$dst, R32:$src1, i32imm:$src2), "adc $dst, $src2">;
646 def ADC32ri8 : Ii8 <0x83, MRM2r, (ops R32:$dst, R32:$src1, i8imm:$src2), "adc $dst, $src2">;
647 def ADC32mi : Im32i32<"adc", 0x81, MRM2m >; // [mem32] += I32+Carry
648 def ADC32mi8 : Im32i8 <"adc", 0x83, MRM2m >; // [mem32] += I8+Carry
650 def SUB8rr : I<0x28, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), "sub $dst, $src2">;
651 def SUB16rr : I<0x29, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), "sub $dst, $src2">, OpSize;
652 def SUB32rr : I<0x29, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), "sub $dst, $src2">;
653 def SUB8mr : Im8 <"sub", 0x28, MRMDestMem>; // [mem8] -= R8
654 def SUB16mr : Im16 <"sub", 0x29, MRMDestMem>, OpSize; // [mem16] -= R16
655 def SUB32mr : Im32 <"sub", 0x29, MRMDestMem>; // [mem32] -= R32
656 def SUB8rm : Im8 <"sub", 0x2A, MRMSrcMem >; // R8 -= [mem8]
657 def SUB16rm : Im16 <"sub", 0x2B, MRMSrcMem >, OpSize; // R16 -= [mem16]
658 def SUB32rm : Im32 <"sub", 0x2B, MRMSrcMem >; // R32 -= [mem32]
660 def SUB8ri : Ii8 <0x80, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2),
662 def SUB16ri : Ii16<0x81, MRM5r, (ops R16:$dst, R16:$src1, i16imm:$src2),
663 "sub $dst, $src2">, OpSize;
664 def SUB32ri : Ii32<0x81, MRM5r, (ops R32:$dst, R32:$src1, i32imm:$src2),
666 def SUB8mi : Im8i8 <"sub", 0x80, MRM5m >; // [mem8] -= I8
667 def SUB16mi : Im16i16<"sub", 0x81, MRM5m >, OpSize; // [mem16] -= I16
668 def SUB32mi : Im32i32<"sub", 0x81, MRM5m >; // [mem32] -= I32
670 def SUB16ri8 : Ii8<0x83, MRM5r, (ops R16:$dst, R16:$src1, i8imm:$src2),
671 "sub $dst, $src2">, OpSize;
672 def SUB32ri8 : Ii8<0x83, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2),
674 def SUB16mi8 : Im16i8<"sub", 0x83, MRM5m >, OpSize; // [mem16] -= I8
675 def SUB32mi8 : Im32i8<"sub", 0x83, MRM5m >; // [mem32] -= I8
677 def SBB32rr : I<0x19, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
679 def SBB32mr : Im32<"sbb", 0x19, MRMDestMem>; // [mem32] -= R32+Carry
680 def SBB32rm : Im32<"sbb", 0x1B, MRMSrcMem >; // R32 -= [mem32]+Carry
681 def SBB32ri : Ii32<0x81, MRM3r, (ops R32:$dst, R32:$src1, i32imm:$src2),
683 def SBB32ri8 : Ii8<0x83, MRM3r, (ops R32:$dst, R32:$src1, i8imm:$src2),
685 def SBB32mi : Im32i32<"sbb", 0x81, MRM3m>; // [mem32] -= I32+Carry
686 def SBB32mi8 : Im32i8 <"sbb", 0x83, MRM3m>; // [mem32] -= I8+Carry
688 def IMUL16rr : I<0xAF, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2), "imul $dst, $src2">, TB, OpSize;
689 def IMUL32rr : I<0xAF, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), "imul $dst, $src2">, TB;
690 def IMUL16rm : Im16 <"imul", 0xAF, MRMSrcMem>, TB, OpSize;
691 def IMUL32rm : Im32 <"imul", 0xAF, MRMSrcMem>, TB ;
693 } // end Two Address instructions
695 // These are suprisingly enough not two address instructions!
696 def IMUL16rri : Ii16<0x69, MRMSrcReg, (ops R16:$dst, R16:$src1, i16imm:$src2),
697 "imul $dst, $src1, $src2">, OpSize; // R16 = R16*I16
698 def IMUL32rri : Ii32<0x69, MRMSrcReg, (ops R32:$dst, R32:$src1, i32imm:$src2),
699 "imul $dst, $src1, $src2">; // R32 = R32*I32
700 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, (ops R16:$dst, R16:$src1, i8imm:$src2),
701 "imul $dst, $src1, $src2">, OpSize; // R16 = R16*I8
702 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, (ops R32:$dst, R32:$src1, i8imm:$src2),
703 "imul $dst, $src1, $src2">; // R32 = R32*I8
704 def IMUL16rmi : Im16i16<"imul",0x69, MRMSrcMem>, OpSize; // R16 = [mem16]*I16
705 def IMUL32rmi : Im32i32<"imul",0x69, MRMSrcMem>; // R32 = [mem32]*I32
706 def IMUL16rmi8 : Im16i8<"imul", 0x6B, MRMSrcMem>, OpSize; // R16 = [mem16]*I8
707 def IMUL32rmi8 : Im32i8<"imul", 0x6B, MRMSrcMem>; // R32 = [mem32]*I8
709 //===----------------------------------------------------------------------===//
710 // Test instructions are just like AND, except they don't generate a result.
711 def TEST8rr : I<0x84, MRMDestReg, (ops R8:$src1, R8:$src2),
712 "test $src1, $src2">;
713 def TEST16rr : I<0x85, MRMDestReg, (ops R16:$src1, R16:$src2),
714 "test $src1, $src2">, OpSize;
715 def TEST32rr : I<0x85, MRMDestReg, (ops R32:$src1, R32:$src2),
716 "test $src1, $src2">;
717 def TEST8mr : Im8 <"test", 0x84, MRMDestMem>; // flags = [mem8] & R8
718 def TEST16mr : Im16 <"test", 0x85, MRMDestMem>, OpSize; // flags = [mem16] & R16
719 def TEST32mr : Im32 <"test", 0x85, MRMDestMem>; // flags = [mem32] & R32
720 def TEST8rm : Im8 <"test", 0x84, MRMSrcMem >; // flags = R8 & [mem8]
721 def TEST16rm : Im16 <"test", 0x85, MRMSrcMem >, OpSize; // flags = R16 & [mem16]
722 def TEST32rm : Im32 <"test", 0x85, MRMSrcMem >; // flags = R32 & [mem32]
724 def TEST8ri : Ii8 <0xF6, MRM0r, (ops R8:$dst, i8imm:$src),
725 "test $dst, $src">; // flags = R8 & imm8
726 def TEST16ri : Ii16 <0xF7, MRM0r, (ops R16:$dst, i16imm:$src),
727 "test $dst, $src">, OpSize; // flags = R16 & imm16
728 def TEST32ri : Ii32 <0xF7, MRM0r, (ops R32:$dst, i32imm:$src),
729 "test $dst, $src">; // flags = R32 & imm32
730 def TEST8mi : Im8i8 <"test", 0xF6, MRM0m >; // flags = [mem8] & imm8
731 def TEST16mi : Im16i16<"test", 0xF7, MRM0m >, OpSize; // flags = [mem16] & imm16
732 def TEST32mi : Im32i32<"test", 0xF7, MRM0m >; // flags = [mem32] & imm32
736 // Condition code ops, incl. set if equal/not equal/...
737 def SAHF : I<0x9E, RawFrm, (ops), "sahf">, Imp<[AH],[]>; // flags = AH
738 def LAHF : I<0x9F, RawFrm, (ops), "lahf">, Imp<[],[AH]>; // AH = flags
740 def SETBr : I<0x92, MRM0r, (ops R8:$dst), "setb $dst">, TB; // R8 = < unsign
741 def SETBm : Im8<"setb" , 0x92, MRM0m>, TB; // [mem8] = < unsign
742 def SETAEr : I<0x93, MRM0r, (ops R8:$dst), "setae $dst">, TB; // R8 = >= unsign
743 def SETAEm : Im8<"setae", 0x93, MRM0m>, TB; // [mem8] = >= unsign
744 def SETEr : I<0x94, MRM0r, (ops R8:$dst), "sete $dst">, TB; // R8 = ==
745 def SETEm : Im8<"sete" , 0x94, MRM0m>, TB; // [mem8] = ==
746 def SETNEr : I<0x95, MRM0r, (ops R8:$dst), "setne $dst">, TB; // R8 = !=
747 def SETNEm : Im8<"setne", 0x95, MRM0m>, TB; // [mem8] = !=
748 def SETBEr : I<0x96, MRM0r, (ops R8:$dst), "setbe $dst">, TB; // R8 = <= unsign
749 def SETBEm : Im8<"setbe", 0x96, MRM0m>, TB; // [mem8] = <= unsign
750 def SETAr : I<0x97, MRM0r, (ops R8:$dst), "seta $dst">, TB; // R8 = > signed
751 def SETAm : Im8<"seta" , 0x97, MRM0m>, TB; // [mem8] = > signed
752 def SETSr : I<0x98, MRM0r, (ops R8:$dst), "sets $dst">, TB; // R8 = <sign bit>
753 def SETSm : Im8<"sets" , 0x98, MRM0m>, TB; // [mem8] = <sign bit>
754 def SETNSr : I<0x99, MRM0r, (ops R8:$dst), "setns $dst">, TB; // R8 = !<sign bit>
755 def SETNSm : Im8<"setns", 0x99, MRM0m>, TB; // [mem8] = !<sign bit>
756 def SETPr : I<0x9A, MRM0r, (ops R8:$dst), "setp $dst">, TB; // R8 = parity
757 def SETPm : Im8<"setp" , 0x9A, MRM0m>, TB; // [mem8] = parity
758 def SETLr : I<0x9C, MRM0r, (ops R8:$dst), "setl $dst">, TB; // R8 = < signed
759 def SETLm : Im8<"setl" , 0x9C, MRM0m>, TB; // [mem8] = < signed
760 def SETGEr : I<0x9D, MRM0r, (ops R8:$dst), "setge $dst">, TB; // R8 = >= signed
761 def SETGEm : Im8<"setge", 0x9D, MRM0m>, TB; // [mem8] = >= signed
762 def SETLEr : I<0x9E, MRM0r, (ops R8:$dst), "setle $dst">, TB; // R8 = <= signed
763 def SETLEm : Im8<"setle", 0x9E, MRM0m>, TB; // [mem8] = <= signed
764 def SETGr : I<0x9F, MRM0r, (ops R8:$dst), "setg $dst">, TB; // R8 = < signed
765 def SETGm : Im8<"setg" , 0x9F, MRM0m>, TB; // [mem8] = < signed
767 // Integer comparisons
768 def CMP8rr : I<0x38, MRMDestReg, (ops R8 :$src1, R8 :$src2), "cmp $src1, $src2">;
769 def CMP16rr : I<0x39, MRMDestReg, (ops R16:$src1, R16:$src2), "cmp $src1, $src2">, OpSize;
770 def CMP32rr : I<0x39, MRMDestReg, (ops R32:$src1, R32:$src2), "cmp $src1, $src2">;
771 def CMP8mr : Im8 <"cmp", 0x38, MRMDestMem>; // compare [mem8], R8
772 def CMP16mr : Im16 <"cmp", 0x39, MRMDestMem>, OpSize; // compare [mem16], R16
773 def CMP32mr : Im32 <"cmp", 0x39, MRMDestMem>; // compare [mem32], R32
774 def CMP8rm : Im8 <"cmp", 0x3A, MRMSrcMem >; // compare R8, [mem8]
775 def CMP16rm : Im16 <"cmp", 0x3B, MRMSrcMem >, OpSize; // compare R16, [mem16]
776 def CMP32rm : Im32 <"cmp", 0x3B, MRMSrcMem >; // compare R32, [mem32]
777 def CMP8ri : Ii8 <0x80, MRM7r, (ops R16:$dst, i8imm:$src), "cmp $dst, $src">;
778 def CMP16ri : Ii16 <0x81, MRM7r, (ops R16:$dst, i16imm:$src), "cmp $dst, $src">, OpSize;
779 def CMP32ri : Ii32 <0x81, MRM7r, (ops R32:$dst, i32imm:$src), "cmp $dst, $src">;
780 def CMP8mi : Im8i8 <"cmp", 0x80, MRM7m >; // compare [mem8], imm8
781 def CMP16mi : Im16i16<"cmp", 0x81, MRM7m >, OpSize; // compare [mem16], imm16
782 def CMP32mi : Im32i32<"cmp", 0x81, MRM7m >; // compare [mem32], imm32
784 // Sign/Zero extenders
785 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops R16:$dst, R8 :$src), "movsx $dst, $src">, TB, OpSize;
786 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops R32:$dst, R8 :$src), "movsx $dst, $src">, TB;
787 def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops R32:$dst, R16:$src), "movsx $dst, $src">, TB;
788 def MOVSX16rm8 : Im8 <"movsx", 0xBE, MRMSrcMem>, TB, OpSize; // R16 = signext([mem8])
789 def MOVSX32rm8 : Im8 <"movsx", 0xBE, MRMSrcMem>, TB; // R32 = signext([mem8])
790 def MOVSX32rm16: Im16<"movsx", 0xBF, MRMSrcMem>, TB; // R32 = signext([mem16])
792 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops R16:$dst, R8 :$src), "movzx $dst, $src">, TB, OpSize;
793 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops R32:$dst, R8 :$src), "movzx $dst, $src">, TB;
794 def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops R32:$dst, R16:$src), "movzx $dst, $src">, TB;
795 def MOVZX16rm8 : Im8 <"movzx", 0xB6, MRMSrcMem>, TB, OpSize; // R16 = zeroext([mem8])
796 def MOVZX32rm8 : Im8 <"movzx", 0xB6, MRMSrcMem>, TB; // R32 = zeroext([mem8])
797 def MOVZX32rm16: Im16<"movzx", 0xB7, MRMSrcMem>, TB; // R32 = zeroext([mem16])
800 //===----------------------------------------------------------------------===//
801 // Floating point support
802 //===----------------------------------------------------------------------===//
804 // FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP'
806 // Floating point instruction templates
807 class FPInst<string n, bits<8> o, Format F, FPFormat fp, MemType m, ImmType i>
808 : X86Inst<n, o, F, m, i> { let FPForm = fp; let FPFormBits = FPForm.Value; }
810 class FPI<bits<8> o, Format F, FPFormat fp> : FPInst<"", o, F, fp, NoMem, NoImm>;
812 class FPIM<string n, bits<8> o, Format F, FPFormat fp, MemType m> : FPInst<n, o, F, fp, m, NoImm>;
814 class FPI16m<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem16>;
815 class FPI32m<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem32>;
816 class FPI64m<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem64>;
817 class FPI80m<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem80>;
819 // Pseudo instructions for floating point. We use these pseudo instructions
820 // because they can be expanded by the fp spackifier into one of many different
821 // forms of instructions for doing these operations. Until the stackifier runs,
822 // we prefer to be abstract.
823 def FpMOV : FPI<0, Pseudo, SpecialFP>; // f1 = fmov f2
824 def FpADD : FPI<0, Pseudo, TwoArgFP>; // f1 = fadd f2, f3
825 def FpSUB : FPI<0, Pseudo, TwoArgFP>; // f1 = fsub f2, f3
826 def FpMUL : FPI<0, Pseudo, TwoArgFP>; // f1 = fmul f2, f3
827 def FpDIV : FPI<0, Pseudo, TwoArgFP>; // f1 = fdiv f2, f3
829 def FpGETRESULT : FPI<0, Pseudo, SpecialFP>; // FPR = ST(0)
830 def FpSETRESULT : FPI<0, Pseudo, SpecialFP>; // ST(0) = FPR
832 // FADD reg, mem: Before stackification, these are represented by: R1 = FADD* R2, [mem]
833 def FADD32m : FPI32m<"fadd", 0xD8, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem32real]
834 def FADD64m : FPI64m<"fadd", 0xDC, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem64real]
835 def FIADD16m : FPI16m<"fiadd", 0xDE, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem16int]
836 def FIADD32m : FPI32m<"fiadd", 0xDA, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem32int]
838 // FMUL reg, mem: Before stackification, these are represented by: R1 = FMUL* R2, [mem]
839 def FMUL32m : FPI32m<"fmul", 0xD8, MRM1m, OneArgFPRW>; // ST(0) = ST(0) * [mem32real]
840 def FMUL64m : FPI64m<"fmul", 0xDC, MRM1m, OneArgFPRW>; // ST(0) = ST(0) * [mem64real]
841 def FIMUL16m : FPI16m<"fimul", 0xDE, MRM1m, OneArgFPRW>; // ST(0) = ST(0) * [mem16int]
842 def FIMUL32m : FPI32m<"fimul", 0xDA, MRM1m, OneArgFPRW>; // ST(0) = ST(0) * [mem32int]
844 // FSUB reg, mem: Before stackification, these are represented by: R1 = FSUB* R2, [mem]
845 def FSUB32m : FPI32m<"fsub", 0xD8, MRM4m, OneArgFPRW>; // ST(0) = ST(0) - [mem32real]
846 def FSUB64m : FPI64m<"fsub", 0xDC, MRM4m, OneArgFPRW>; // ST(0) = ST(0) - [mem64real]
847 def FISUB16m : FPI16m<"fisub", 0xDE, MRM4m, OneArgFPRW>; // ST(0) = ST(0) - [mem16int]
848 def FISUB32m : FPI32m<"fisub", 0xDA, MRM4m, OneArgFPRW>; // ST(0) = ST(0) - [mem32int]
850 // FSUBR reg, mem: Before stackification, these are represented by: R1 = FSUBR* R2, [mem]
851 // Note that the order of operands does not reflect the operation being performed.
852 def FSUBR32m : FPI32m<"fsubr", 0xD8, MRM5m, OneArgFPRW>; // ST(0) = [mem32real] - ST(0)
853 def FSUBR64m : FPI64m<"fsubr", 0xDC, MRM5m, OneArgFPRW>; // ST(0) = [mem64real] - ST(0)
854 def FISUBR16m : FPI16m<"fisubr", 0xDE, MRM5m, OneArgFPRW>; // ST(0) = [mem16int] - ST(0)
855 def FISUBR32m : FPI32m<"fisubr", 0xDA, MRM5m, OneArgFPRW>; // ST(0) = [mem32int] - ST(0)
857 // FDIV reg, mem: Before stackification, these are represented by: R1 = FDIV* R2, [mem]
858 def FDIV32m : FPI32m<"fdiv", 0xD8, MRM6m, OneArgFPRW>; // ST(0) = ST(0) / [mem32real]
859 def FDIV64m : FPI64m<"fdiv", 0xDC, MRM6m, OneArgFPRW>; // ST(0) = ST(0) / [mem64real]
860 def FIDIV16m : FPI16m<"fidiv", 0xDE, MRM6m, OneArgFPRW>; // ST(0) = ST(0) / [mem16int]
861 def FIDIV32m : FPI32m<"fidiv", 0xDA, MRM6m, OneArgFPRW>; // ST(0) = ST(0) / [mem32int]
863 // FDIVR reg, mem: Before stackification, these are represented by: R1 = FDIVR* R2, [mem]
864 // Note that the order of operands does not reflect the operation being performed.
865 def FDIVR32m : FPI32m<"fdivr", 0xD8, MRM7m, OneArgFPRW>; // ST(0) = [mem32real] / ST(0)
866 def FDIVR64m : FPI64m<"fdivr", 0xDC, MRM7m, OneArgFPRW>; // ST(0) = [mem64real] / ST(0)
867 def FIDIVR16m : FPI16m<"fidivr", 0xDE, MRM7m, OneArgFPRW>; // ST(0) = [mem16int] / ST(0)
868 def FIDIVR32m : FPI32m<"fidivr", 0xDA, MRM7m, OneArgFPRW>; // ST(0) = [mem32int] / ST(0)
871 // Floating point cmovs...
872 let isTwoAddress = 1, Uses = [ST0], Defs = [ST0] in {
873 def FCMOVB : FPI<0xC0, AddRegFrm, CondMovFP>, DA, // fcmovb ST(i) -> ST(0)
874 II<(ops RST:$op), "fcmovb %ST(0), $op">;
875 def FCMOVBE : FPI<0xD0, AddRegFrm, CondMovFP>, DA, // fcmovbe ST(i) -> ST(0)
876 II<(ops RST:$op), "fcmovbe %ST(0), $op">;
877 def FCMOVE : FPI<0xC8, AddRegFrm, CondMovFP>, DA, // fcmove ST(i) -> ST(0)
878 II<(ops RST:$op), "fcmove %ST(0), $op">;
879 def FCMOVAE : FPI<0xC0, AddRegFrm, CondMovFP>, DB, // fcmovae ST(i) -> ST(0)
880 II<(ops RST:$op), "fcmovae %ST(0), $op">;
881 def FCMOVA : FPI<0xD0, AddRegFrm, CondMovFP>, DB, // fcmova ST(i) -> ST(0)
882 II<(ops RST:$op), "fcmova %ST(0), $op">;
883 def FCMOVNE : FPI<0xC8, AddRegFrm, CondMovFP>, DB, // fcmovne ST(i) -> ST(0)
884 II<(ops RST:$op), "fcmovne %ST(0), $op">;
887 // Floating point loads & stores...
889 def FLDrr : FPI<0xC0, AddRegFrm, NotFP>, D9; // push(ST(i))
890 def FLD32m : FPI32m <"fld" , 0xD9, MRM0m , ZeroArgFP>; // load float
891 def FLD64m : FPI64m <"fld" , 0xDD, MRM0m , ZeroArgFP>; // load double
892 def FLD80m : FPI80m <"fld" , 0xDB, MRM5m , ZeroArgFP>; // load extended
893 def FILD16m : FPI16m <"fild" , 0xDF, MRM0m , ZeroArgFP>; // load signed short
894 def FILD32m : FPI32m <"fild" , 0xDB, MRM0m , ZeroArgFP>; // load signed int
895 def FILD64m : FPI64m <"fild" , 0xDF, MRM5m , ZeroArgFP>; // load signed long
898 def FSTrr : FPI<0xD0, AddRegFrm, NotFP >, DD; // ST(i) = ST(0)
900 def FSTPrr : FPI<0xD8, AddRegFrm, NotFP >, DD; // ST(i) = ST(0), pop
901 def FST32m : FPI32m <"fst" , 0xD9, MRM2m , OneArgFP>; // store float
902 def FST64m : FPI64m <"fst" , 0xDD, MRM2m , OneArgFP>; // store double
903 def FSTP32m : FPI32m <"fstp", 0xD9, MRM3m , OneArgFP>; // store float, pop
904 def FSTP64m : FPI64m <"fstp", 0xDD, MRM3m , OneArgFP>; // store double, pop
905 def FSTP80m : FPI80m <"fstp", 0xDB, MRM7m , OneArgFP>; // store extended, pop
907 def FIST16m : FPI16m <"fist", 0xDF, MRM2m , OneArgFP>; // store signed short
908 def FIST32m : FPI32m <"fist", 0xDB, MRM2m , OneArgFP>; // store signed int
909 def FISTP16m : FPI16m <"fistp", 0xDF, MRM3m , NotFP >; // store signed short, pop
910 def FISTP32m : FPI32m <"fistp", 0xDB, MRM3m , NotFP >; // store signed int, pop
911 def FISTP64m : FPI64m <"fistpll", 0xDF, MRM7m , OneArgFP>; // store signed long, pop
913 def FXCH : FPI<0xC8, AddRegFrm, NotFP>,
914 II<(ops RST:$op), "fxch $op">, D9; // fxch ST(i), ST(0)
916 // Floating point constant loads...
917 def FLD0 : FPI<0xEE, RawFrm, ZeroArgFP>, D9,
919 def FLD1 : FPI<0xE8, RawFrm, ZeroArgFP>, D9,
923 // Unary operations...
924 def FCHS : FPI<0xE0, RawFrm, OneArgFPRW>, // f1 = fchs f2
925 II<(ops), "fchs">, D9;
926 def FTST : FPI<0xE4, RawFrm, OneArgFP>, // ftst ST(0)
927 II<(ops), "ftst">, D9;
929 // Binary arithmetic operations...
930 class FPST0rInst<bits<8> o, dag ops, string asm> : I<o, AddRegFrm, ops, asm>, D8 {
931 list<Register> Uses = [ST0];
932 list<Register> Defs = [ST0];
934 class FPrST0Inst<bits<8> o, dag ops, string asm> : I<o, AddRegFrm, ops, asm>, DC {
935 list<Register> Uses = [ST0];
937 class FPrST0PInst<bits<8> o, dag ops, string asm> : I<o, AddRegFrm, ops, asm>, DE {
938 list<Register> Uses = [ST0];
941 def FADDST0r : FPST0rInst <0xC0, (ops RST:$op), "fadd $op">;
942 def FADDrST0 : FPrST0Inst <0xC0, (ops RST:$op), "fadd $op, %ST(0)">;
943 def FADDPrST0 : FPrST0PInst<0xC0, (ops RST:$op), "faddp $op">;
945 def FSUBRST0r : FPST0rInst <0xE8, (ops RST:$op), "fsubr $op">;
946 def FSUBrST0 : FPrST0Inst <0xE8, (ops RST:$op), "fsub $op, %ST(0)">;
947 def FSUBPrST0 : FPrST0PInst<0xE8, (ops RST:$op), "fsubp $op">;
949 def FSUBST0r : FPST0rInst <0xE0, (ops RST:$op), "fsub $op">;
950 def FSUBRrST0 : FPrST0Inst <0xE0, (ops RST:$op), "fsubr $op, %ST(0)">;
951 def FSUBRPrST0 : FPrST0PInst<0xE0, (ops RST:$op), "fsubrp $op">;
953 def FMULST0r : FPST0rInst <0xC8, (ops RST:$op), "fmul $op">;
954 def FMULrST0 : FPrST0Inst <0xC8, (ops RST:$op), "fmul $op, %ST(0)">;
955 def FMULPrST0 : FPrST0PInst<0xC8, (ops RST:$op), "fmulp $op">;
957 def FDIVRST0r : FPST0rInst <0xF8, (ops RST:$op), "fdivr $op">;
958 def FDIVrST0 : FPrST0Inst <0xF8, (ops RST:$op), "fdiv $op, %ST(0)">;
959 def FDIVPrST0 : FPrST0PInst<0xF8, (ops RST:$op), "fdivp $op">;
961 def FDIVST0r : FPST0rInst <0xF0, (ops RST:$op), "fdiv $op">; // ST(0) = ST(0) / ST(i)
962 def FDIVRrST0 : FPrST0Inst <0xF0, (ops RST:$op), "fdivr $op, %ST(0)">; // ST(i) = ST(0) / ST(i)
963 def FDIVRPrST0 : FPrST0PInst<0xF0, (ops RST:$op), "fdivrp $op">; // ST(i) = ST(0) / ST(i), pop
965 // Floating point compares
966 def FUCOMr : FPI<0xE0, AddRegFrm, CompareFP>, // FPSW = compare ST(0) with ST(i)
967 II<(ops RST:$reg), "fucom $reg">, DD, Imp<[ST0],[]>;
968 def FUCOMPr : I<0xE8, AddRegFrm, (ops RST:$reg),
969 "fucomp $reg">, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i), pop
970 def FUCOMPPr : I<0xE9, RawFrm, (ops),
971 "fucompp">, DA, Imp<[ST0],[]>; // compare ST(0) with ST(1), pop, pop
973 def FUCOMIr : FPI<0xE8, AddRegFrm, CompareFP>, // CC = compare ST(0) with ST(i)
974 II<(ops RST:$reg), "fucomi %ST(0), $reg">, DB, Imp<[ST0],[]>;
975 def FUCOMIPr : I<0xE8, AddRegFrm, (ops RST:$reg),
976 "fucomip %ST(0), $reg">, DF, Imp<[ST0],[]>; // CC = compare ST(0) with ST(i), pop
979 // Floating point flag ops
980 def FNSTSW8r : I<0xE0, RawFrm, (ops), "fnstsw">, DF, Imp<[],[AX]>; // AX = fp flags
982 def FNSTCW16m : Im16<"fnstcw", 0xD9, MRM7m>; // [mem16] = X87 control world
983 def FLDCW16m : Im16<"fldcw" , 0xD9, MRM5m>; // X87 control world = [mem16]