1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 def SDTUnaryArithOvf : SDTypeProfile<1, 1,
32 def SDTBinaryArithOvf : SDTypeProfile<1, 2,
33 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
36 def SDTX86BrCond : SDTypeProfile<0, 3,
37 [SDTCisVT<0, OtherVT>,
38 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
40 def SDTX86SetCC : SDTypeProfile<1, 2,
42 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
44 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
46 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
48 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
49 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
50 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
52 def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
53 def SDT_X86CallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
56 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
58 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
60 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
62 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
64 def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
66 def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
68 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
70 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
72 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
73 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
74 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
75 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
77 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
79 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
81 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
82 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
84 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
86 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
87 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
89 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
90 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
92 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
93 [SDNPHasChain, SDNPMayStore,
94 SDNPMayLoad, SDNPMemOperand]>;
95 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
96 [SDNPHasChain, SDNPMayStore,
97 SDNPMayLoad, SDNPMemOperand]>;
98 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
99 [SDNPHasChain, SDNPMayStore,
100 SDNPMayLoad, SDNPMemOperand]>;
101 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
102 [SDNPHasChain, SDNPMayStore,
103 SDNPMayLoad, SDNPMemOperand]>;
104 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
105 [SDNPHasChain, SDNPMayStore,
106 SDNPMayLoad, SDNPMemOperand]>;
107 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
108 [SDNPHasChain, SDNPMayStore,
109 SDNPMayLoad, SDNPMemOperand]>;
110 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
111 [SDNPHasChain, SDNPMayStore,
112 SDNPMayLoad, SDNPMemOperand]>;
113 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
114 [SDNPHasChain, SDNPOptInFlag]>;
116 def X86callseq_start :
117 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
118 [SDNPHasChain, SDNPOutFlag]>;
120 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
121 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
123 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
124 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
126 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
127 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
129 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
130 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
131 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
132 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
135 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
136 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
138 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
139 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
141 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
142 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
143 def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
145 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
148 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
149 [SDNPHasChain, SDNPOptInFlag]>;
151 def X86add_ovf : SDNode<"X86ISD::ADD", SDTBinaryArithOvf>;
152 def X86sub_ovf : SDNode<"X86ISD::SUB", SDTBinaryArithOvf>;
153 def X86smul_ovf : SDNode<"X86ISD::SMUL", SDTBinaryArithOvf>;
154 def X86umul_ovf : SDNode<"X86ISD::UMUL", SDTUnaryArithOvf>;
156 //===----------------------------------------------------------------------===//
157 // X86 Operand Definitions.
160 // *mem - Operand definitions for the funky X86 addressing mode operands.
162 class X86MemOperand<string printMethod> : Operand<iPTR> {
163 let PrintMethod = printMethod;
164 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
167 def i8mem : X86MemOperand<"printi8mem">;
168 def i16mem : X86MemOperand<"printi16mem">;
169 def i32mem : X86MemOperand<"printi32mem">;
170 def i64mem : X86MemOperand<"printi64mem">;
171 def i128mem : X86MemOperand<"printi128mem">;
172 def f32mem : X86MemOperand<"printf32mem">;
173 def f64mem : X86MemOperand<"printf64mem">;
174 def f80mem : X86MemOperand<"printf80mem">;
175 def f128mem : X86MemOperand<"printf128mem">;
177 def lea32mem : Operand<i32> {
178 let PrintMethod = "printi32mem";
179 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
182 def SSECC : Operand<i8> {
183 let PrintMethod = "printSSECC";
186 def piclabel: Operand<i32> {
187 let PrintMethod = "printPICLabel";
190 // A couple of more descriptive operand definitions.
191 // 16-bits but only 8 bits are significant.
192 def i16i8imm : Operand<i16>;
193 // 32-bits but only 8 bits are significant.
194 def i32i8imm : Operand<i32>;
196 // Branch targets have OtherVT type.
197 def brtarget : Operand<OtherVT>;
199 //===----------------------------------------------------------------------===//
200 // X86 Complex Pattern Definitions.
203 // Define X86 specific addressing mode.
204 def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
205 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
206 [add, mul, shl, or, frameindex], []>;
208 //===----------------------------------------------------------------------===//
209 // X86 Instruction Predicate Definitions.
210 def HasMMX : Predicate<"Subtarget->hasMMX()">;
211 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
212 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
213 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
214 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
215 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
216 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
217 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
218 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
219 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
220 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
221 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
222 def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
223 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
224 def OptForSpeed : Predicate<"!OptForSize">;
225 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
227 //===----------------------------------------------------------------------===//
228 // X86 Instruction Format Definitions.
231 include "X86InstrFormats.td"
233 //===----------------------------------------------------------------------===//
234 // Pattern fragments...
237 // X86 specific condition code. These correspond to CondCode in
238 // X86InstrInfo.h. They must be kept in synch.
239 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
240 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
241 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
242 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
243 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
244 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
245 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
246 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
247 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
248 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
249 def X86_COND_NO : PatLeaf<(i8 10)>;
250 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
251 def X86_COND_NS : PatLeaf<(i8 12)>;
252 def X86_COND_O : PatLeaf<(i8 13)>;
253 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
254 def X86_COND_S : PatLeaf<(i8 15)>;
256 def i16immSExt8 : PatLeaf<(i16 imm), [{
257 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
258 // sign extended field.
259 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
262 def i32immSExt8 : PatLeaf<(i32 imm), [{
263 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
264 // sign extended field.
265 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
268 // Helper fragments for loads.
269 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
270 // known to be 32-bit aligned or better. Ditto for i8 to i16.
271 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
272 LoadSDNode *LD = cast<LoadSDNode>(N);
273 ISD::LoadExtType ExtType = LD->getExtensionType();
274 if (ExtType == ISD::NON_EXTLOAD)
276 if (ExtType == ISD::EXTLOAD)
277 return LD->getAlignment() >= 2 && !LD->isVolatile();
281 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
282 LoadSDNode *LD = cast<LoadSDNode>(N);
283 ISD::LoadExtType ExtType = LD->getExtensionType();
284 if (ExtType == ISD::EXTLOAD)
285 return LD->getAlignment() >= 2 && !LD->isVolatile();
289 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
290 LoadSDNode *LD = cast<LoadSDNode>(N);
291 ISD::LoadExtType ExtType = LD->getExtensionType();
292 if (ExtType == ISD::NON_EXTLOAD)
294 if (ExtType == ISD::EXTLOAD)
295 return LD->getAlignment() >= 4 && !LD->isVolatile();
299 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
300 LoadSDNode *LD = cast<LoadSDNode>(N);
301 if (LD->isVolatile())
303 ISD::LoadExtType ExtType = LD->getExtensionType();
304 if (ExtType == ISD::NON_EXTLOAD)
306 if (ExtType == ISD::EXTLOAD)
307 return LD->getAlignment() >= 4;
311 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
312 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
314 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
315 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
316 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
318 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
319 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
320 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
322 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
323 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
324 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
325 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
326 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
327 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
329 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
330 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
331 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
332 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
333 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
334 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
337 // An 'and' node with a single use.
338 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
339 return N->hasOneUse();
342 // 'shld' and 'shrd' instruction patterns. Note that even though these have
343 // the srl and shl in their patterns, the C++ code must still check for them,
344 // because predicates are tested before children nodes are explored.
346 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
347 (or (srl node:$src1, node:$amt1),
348 (shl node:$src2, node:$amt2)), [{
349 assert(N->getOpcode() == ISD::OR);
350 return N->getOperand(0).getOpcode() == ISD::SRL &&
351 N->getOperand(1).getOpcode() == ISD::SHL &&
352 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
353 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
354 N->getOperand(0).getConstantOperandVal(1) ==
355 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
358 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
359 (or (shl node:$src1, node:$amt1),
360 (srl node:$src2, node:$amt2)), [{
361 assert(N->getOpcode() == ISD::OR);
362 return N->getOperand(0).getOpcode() == ISD::SHL &&
363 N->getOperand(1).getOpcode() == ISD::SRL &&
364 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
365 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
366 N->getOperand(0).getConstantOperandVal(1) ==
367 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
370 //===----------------------------------------------------------------------===//
371 // Instruction list...
374 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
375 // a stack adjustment and the codegen must know that they may modify the stack
376 // pointer before prolog-epilog rewriting occurs.
377 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
378 // sub / add which can clobber EFLAGS.
379 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
380 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
382 [(X86callseq_start timm:$amt)]>,
383 Requires<[In32BitMode]>;
384 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
386 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
387 Requires<[In32BitMode]>;
391 let neverHasSideEffects = 1 in
392 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
395 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
396 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
397 "call\t$label\n\tpop{l}\t$reg", []>;
399 //===----------------------------------------------------------------------===//
400 // Control Flow Instructions...
403 // Return instructions.
404 let isTerminator = 1, isReturn = 1, isBarrier = 1,
405 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
406 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
409 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
411 [(X86retflag imm:$amt)]>;
414 // All branches are RawFrm, Void, Branch, and Terminators
415 let isBranch = 1, isTerminator = 1 in
416 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
417 I<opcode, RawFrm, (outs), ins, asm, pattern>;
419 let isBranch = 1, isBarrier = 1 in
420 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
423 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
424 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
425 [(brind GR32:$dst)]>;
426 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
427 [(brind (loadi32 addr:$dst))]>;
430 // Conditional branches
431 let Uses = [EFLAGS] in {
432 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
433 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
434 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
435 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
436 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
437 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
438 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
439 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
440 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
441 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
442 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
443 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
445 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
446 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
447 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
448 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
449 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
450 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
451 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
452 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
454 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
455 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
456 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
457 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
458 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
459 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
460 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
461 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
462 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
463 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
464 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
465 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
468 //===----------------------------------------------------------------------===//
469 // Call Instructions...
472 // All calls clobber the non-callee saved registers. ESP is marked as
473 // a use to prevent stack-pointer assignments that appear immediately
474 // before calls from potentially appearing dead. Uses for argument
475 // registers are added manually.
476 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
477 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
478 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
479 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
481 def CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:$dst,variable_ops),
482 "call\t${dst:call}", []>;
483 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
484 "call\t{*}$dst", [(X86call GR32:$dst)]>;
485 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
486 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
491 def TAILCALL : I<0, Pseudo, (outs), (ins),
495 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
496 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops),
497 "#TC_RETURN $dst $offset",
500 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
501 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops),
502 "#TC_RETURN $dst $offset",
505 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
507 def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAILCALL",
509 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
510 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
512 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
513 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
514 "jmp\t{*}$dst # TAILCALL", []>;
516 //===----------------------------------------------------------------------===//
517 // Miscellaneous Instructions...
519 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
520 def LEAVE : I<0xC9, RawFrm,
521 (outs), (ins), "leave", []>;
523 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
525 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
528 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
531 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
532 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
533 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
534 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
536 let isTwoAddress = 1 in // GR32 = bswap GR32
537 def BSWAP32r : I<0xC8, AddRegFrm,
538 (outs GR32:$dst), (ins GR32:$src),
540 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
543 // Bit scan instructions.
544 let Defs = [EFLAGS] in {
545 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
546 "bsf{w}\t{$src, $dst|$dst, $src}",
547 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
548 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
549 "bsf{w}\t{$src, $dst|$dst, $src}",
550 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
551 (implicit EFLAGS)]>, TB;
552 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
553 "bsf{l}\t{$src, $dst|$dst, $src}",
554 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
555 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
556 "bsf{l}\t{$src, $dst|$dst, $src}",
557 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
558 (implicit EFLAGS)]>, TB;
560 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
561 "bsr{w}\t{$src, $dst|$dst, $src}",
562 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
563 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
564 "bsr{w}\t{$src, $dst|$dst, $src}",
565 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
566 (implicit EFLAGS)]>, TB;
567 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
568 "bsr{l}\t{$src, $dst|$dst, $src}",
569 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
570 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
571 "bsr{l}\t{$src, $dst|$dst, $src}",
572 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
573 (implicit EFLAGS)]>, TB;
576 let neverHasSideEffects = 1 in
577 def LEA16r : I<0x8D, MRMSrcMem,
578 (outs GR16:$dst), (ins i32mem:$src),
579 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
580 let isReMaterializable = 1 in
581 def LEA32r : I<0x8D, MRMSrcMem,
582 (outs GR32:$dst), (ins lea32mem:$src),
583 "lea{l}\t{$src|$dst}, {$dst|$src}",
584 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
586 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
587 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
588 [(X86rep_movs i8)]>, REP;
589 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
590 [(X86rep_movs i16)]>, REP, OpSize;
591 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
592 [(X86rep_movs i32)]>, REP;
595 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
596 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
597 [(X86rep_stos i8)]>, REP;
598 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
599 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
600 [(X86rep_stos i16)]>, REP, OpSize;
601 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
602 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
603 [(X86rep_stos i32)]>, REP;
605 let Defs = [RAX, RDX] in
606 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
609 let isBarrier = 1, hasCtrlDep = 1 in {
610 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
613 //===----------------------------------------------------------------------===//
614 // Input/Output Instructions...
616 let Defs = [AL], Uses = [DX] in
617 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
618 "in{b}\t{%dx, %al|%AL, %DX}", []>;
619 let Defs = [AX], Uses = [DX] in
620 def IN16rr : I<0xED, RawFrm, (outs), (ins),
621 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
622 let Defs = [EAX], Uses = [DX] in
623 def IN32rr : I<0xED, RawFrm, (outs), (ins),
624 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
627 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
628 "in{b}\t{$port, %al|%AL, $port}", []>;
630 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
631 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
633 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
634 "in{l}\t{$port, %eax|%EAX, $port}", []>;
636 let Uses = [DX, AL] in
637 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
638 "out{b}\t{%al, %dx|%DX, %AL}", []>;
639 let Uses = [DX, AX] in
640 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
641 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
642 let Uses = [DX, EAX] in
643 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
644 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
647 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
648 "out{b}\t{%al, $port|$port, %AL}", []>;
650 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
651 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
653 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
654 "out{l}\t{%eax, $port|$port, %EAX}", []>;
656 //===----------------------------------------------------------------------===//
657 // Move Instructions...
659 let neverHasSideEffects = 1 in {
660 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
661 "mov{b}\t{$src, $dst|$dst, $src}", []>;
662 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
663 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
664 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
665 "mov{l}\t{$src, $dst|$dst, $src}", []>;
667 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
668 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
669 "mov{b}\t{$src, $dst|$dst, $src}",
670 [(set GR8:$dst, imm:$src)]>;
671 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
672 "mov{w}\t{$src, $dst|$dst, $src}",
673 [(set GR16:$dst, imm:$src)]>, OpSize;
674 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
675 "mov{l}\t{$src, $dst|$dst, $src}",
676 [(set GR32:$dst, imm:$src)]>;
678 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
679 "mov{b}\t{$src, $dst|$dst, $src}",
680 [(store (i8 imm:$src), addr:$dst)]>;
681 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
682 "mov{w}\t{$src, $dst|$dst, $src}",
683 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
684 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
685 "mov{l}\t{$src, $dst|$dst, $src}",
686 [(store (i32 imm:$src), addr:$dst)]>;
688 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
689 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
690 "mov{b}\t{$src, $dst|$dst, $src}",
691 [(set GR8:$dst, (load addr:$src))]>;
692 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
693 "mov{w}\t{$src, $dst|$dst, $src}",
694 [(set GR16:$dst, (load addr:$src))]>, OpSize;
695 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
696 "mov{l}\t{$src, $dst|$dst, $src}",
697 [(set GR32:$dst, (load addr:$src))]>;
700 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
701 "mov{b}\t{$src, $dst|$dst, $src}",
702 [(store GR8:$src, addr:$dst)]>;
703 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
704 "mov{w}\t{$src, $dst|$dst, $src}",
705 [(store GR16:$src, addr:$dst)]>, OpSize;
706 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
707 "mov{l}\t{$src, $dst|$dst, $src}",
708 [(store GR32:$src, addr:$dst)]>;
710 //===----------------------------------------------------------------------===//
711 // Fixed-Register Multiplication and Division Instructions...
714 // Extra precision multiplication
715 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
716 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
717 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
718 // This probably ought to be moved to a def : Pat<> if the
719 // syntax can be accepted.
720 [(set AL, (mul AL, GR8:$src)),
721 (implicit EFLAGS)]>; // AL,AH = AL*GR8
723 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
724 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
726 []>, OpSize; // AX,DX = AX*GR16
728 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
729 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
731 []>; // EAX,EDX = EAX*GR32
733 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
734 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
736 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
737 // This probably ought to be moved to a def : Pat<> if the
738 // syntax can be accepted.
739 [(set AL, (mul AL, (loadi8 addr:$src))),
740 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
742 let mayLoad = 1, neverHasSideEffects = 1 in {
743 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
744 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
746 []>, OpSize; // AX,DX = AX*[mem16]
748 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
749 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
751 []>; // EAX,EDX = EAX*[mem32]
754 let neverHasSideEffects = 1 in {
755 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
756 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
758 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
759 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
760 OpSize; // AX,DX = AX*GR16
761 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
762 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
763 // EAX,EDX = EAX*GR32
765 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
766 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
767 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
768 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
769 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
770 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
771 let Defs = [EAX,EDX], Uses = [EAX] in
772 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
773 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
775 } // neverHasSideEffects
777 // unsigned division/remainder
778 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
779 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
781 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
782 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
783 "div{w}\t$src", []>, OpSize;
784 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
785 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
788 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
789 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
791 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
792 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
793 "div{w}\t$src", []>, OpSize;
794 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
795 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
799 // Signed division/remainder.
800 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
801 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
802 "idiv{b}\t$src", []>;
803 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
804 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
805 "idiv{w}\t$src", []>, OpSize;
806 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
807 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
808 "idiv{l}\t$src", []>;
809 let mayLoad = 1, mayLoad = 1 in {
810 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
811 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
812 "idiv{b}\t$src", []>;
813 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
814 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
815 "idiv{w}\t$src", []>, OpSize;
816 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
817 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
818 "idiv{l}\t$src", []>;
821 //===----------------------------------------------------------------------===//
822 // Two address Instructions.
824 let isTwoAddress = 1 in {
827 let Uses = [EFLAGS] in {
828 let isCommutable = 1 in {
829 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
830 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
831 "cmovb\t{$src2, $dst|$dst, $src2}",
832 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
833 X86_COND_B, EFLAGS))]>,
835 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
836 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
837 "cmovb\t{$src2, $dst|$dst, $src2}",
838 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
839 X86_COND_B, EFLAGS))]>,
841 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
842 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
843 "cmovae\t{$src2, $dst|$dst, $src2}",
844 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
845 X86_COND_AE, EFLAGS))]>,
847 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
848 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
849 "cmovae\t{$src2, $dst|$dst, $src2}",
850 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
851 X86_COND_AE, EFLAGS))]>,
853 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
854 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
855 "cmove\t{$src2, $dst|$dst, $src2}",
856 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
857 X86_COND_E, EFLAGS))]>,
859 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
860 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
861 "cmove\t{$src2, $dst|$dst, $src2}",
862 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
863 X86_COND_E, EFLAGS))]>,
865 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
866 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
867 "cmovne\t{$src2, $dst|$dst, $src2}",
868 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
869 X86_COND_NE, EFLAGS))]>,
871 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
872 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
873 "cmovne\t{$src2, $dst|$dst, $src2}",
874 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
875 X86_COND_NE, EFLAGS))]>,
877 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
878 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
879 "cmovbe\t{$src2, $dst|$dst, $src2}",
880 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
881 X86_COND_BE, EFLAGS))]>,
883 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
884 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
885 "cmovbe\t{$src2, $dst|$dst, $src2}",
886 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
887 X86_COND_BE, EFLAGS))]>,
889 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
890 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
891 "cmova\t{$src2, $dst|$dst, $src2}",
892 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
893 X86_COND_A, EFLAGS))]>,
895 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
896 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
897 "cmova\t{$src2, $dst|$dst, $src2}",
898 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
899 X86_COND_A, EFLAGS))]>,
901 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
902 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
903 "cmovl\t{$src2, $dst|$dst, $src2}",
904 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
905 X86_COND_L, EFLAGS))]>,
907 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
908 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
909 "cmovl\t{$src2, $dst|$dst, $src2}",
910 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
911 X86_COND_L, EFLAGS))]>,
913 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
914 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
915 "cmovge\t{$src2, $dst|$dst, $src2}",
916 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
917 X86_COND_GE, EFLAGS))]>,
919 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
920 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
921 "cmovge\t{$src2, $dst|$dst, $src2}",
922 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
923 X86_COND_GE, EFLAGS))]>,
925 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
926 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
927 "cmovle\t{$src2, $dst|$dst, $src2}",
928 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
929 X86_COND_LE, EFLAGS))]>,
931 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
932 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
933 "cmovle\t{$src2, $dst|$dst, $src2}",
934 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
935 X86_COND_LE, EFLAGS))]>,
937 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
938 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
939 "cmovg\t{$src2, $dst|$dst, $src2}",
940 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
941 X86_COND_G, EFLAGS))]>,
943 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
944 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
945 "cmovg\t{$src2, $dst|$dst, $src2}",
946 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
947 X86_COND_G, EFLAGS))]>,
949 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
950 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
951 "cmovs\t{$src2, $dst|$dst, $src2}",
952 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
953 X86_COND_S, EFLAGS))]>,
955 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
956 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
957 "cmovs\t{$src2, $dst|$dst, $src2}",
958 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
959 X86_COND_S, EFLAGS))]>,
961 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
962 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
963 "cmovns\t{$src2, $dst|$dst, $src2}",
964 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
965 X86_COND_NS, EFLAGS))]>,
967 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
968 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
969 "cmovns\t{$src2, $dst|$dst, $src2}",
970 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
971 X86_COND_NS, EFLAGS))]>,
973 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
974 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
975 "cmovp\t{$src2, $dst|$dst, $src2}",
976 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
977 X86_COND_P, EFLAGS))]>,
979 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
980 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
981 "cmovp\t{$src2, $dst|$dst, $src2}",
982 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
983 X86_COND_P, EFLAGS))]>,
985 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
986 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
987 "cmovnp\t{$src2, $dst|$dst, $src2}",
988 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
989 X86_COND_NP, EFLAGS))]>,
991 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
992 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
993 "cmovnp\t{$src2, $dst|$dst, $src2}",
994 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
995 X86_COND_NP, EFLAGS))]>,
997 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
998 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
999 "cmovo\t{$src2, $dst|$dst, $src2}",
1000 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1001 X86_COND_O, EFLAGS))]>,
1003 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1004 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1005 "cmovo\t{$src2, $dst|$dst, $src2}",
1006 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1007 X86_COND_O, EFLAGS))]>,
1009 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1010 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1011 "cmovno\t{$src2, $dst|$dst, $src2}",
1012 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1013 X86_COND_NO, EFLAGS))]>,
1015 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1016 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1017 "cmovno\t{$src2, $dst|$dst, $src2}",
1018 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1019 X86_COND_NO, EFLAGS))]>,
1021 } // isCommutable = 1
1023 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1024 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1025 "cmovb\t{$src2, $dst|$dst, $src2}",
1026 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1027 X86_COND_B, EFLAGS))]>,
1029 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1030 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1031 "cmovb\t{$src2, $dst|$dst, $src2}",
1032 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1033 X86_COND_B, EFLAGS))]>,
1035 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1036 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1037 "cmovae\t{$src2, $dst|$dst, $src2}",
1038 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1039 X86_COND_AE, EFLAGS))]>,
1041 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1042 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1043 "cmovae\t{$src2, $dst|$dst, $src2}",
1044 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1045 X86_COND_AE, EFLAGS))]>,
1047 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1048 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1049 "cmove\t{$src2, $dst|$dst, $src2}",
1050 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1051 X86_COND_E, EFLAGS))]>,
1053 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1054 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1055 "cmove\t{$src2, $dst|$dst, $src2}",
1056 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1057 X86_COND_E, EFLAGS))]>,
1059 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1060 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1061 "cmovne\t{$src2, $dst|$dst, $src2}",
1062 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1063 X86_COND_NE, EFLAGS))]>,
1065 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1066 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1067 "cmovne\t{$src2, $dst|$dst, $src2}",
1068 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1069 X86_COND_NE, EFLAGS))]>,
1071 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1072 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1073 "cmovbe\t{$src2, $dst|$dst, $src2}",
1074 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1075 X86_COND_BE, EFLAGS))]>,
1077 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1078 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1079 "cmovbe\t{$src2, $dst|$dst, $src2}",
1080 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1081 X86_COND_BE, EFLAGS))]>,
1083 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1084 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1085 "cmova\t{$src2, $dst|$dst, $src2}",
1086 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1087 X86_COND_A, EFLAGS))]>,
1089 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1090 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1091 "cmova\t{$src2, $dst|$dst, $src2}",
1092 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1093 X86_COND_A, EFLAGS))]>,
1095 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1096 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1097 "cmovl\t{$src2, $dst|$dst, $src2}",
1098 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1099 X86_COND_L, EFLAGS))]>,
1101 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1102 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1103 "cmovl\t{$src2, $dst|$dst, $src2}",
1104 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1105 X86_COND_L, EFLAGS))]>,
1107 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1108 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1109 "cmovge\t{$src2, $dst|$dst, $src2}",
1110 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1111 X86_COND_GE, EFLAGS))]>,
1113 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1114 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1115 "cmovge\t{$src2, $dst|$dst, $src2}",
1116 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1117 X86_COND_GE, EFLAGS))]>,
1119 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1120 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1121 "cmovle\t{$src2, $dst|$dst, $src2}",
1122 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1123 X86_COND_LE, EFLAGS))]>,
1125 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1126 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1127 "cmovle\t{$src2, $dst|$dst, $src2}",
1128 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1129 X86_COND_LE, EFLAGS))]>,
1131 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1132 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1133 "cmovg\t{$src2, $dst|$dst, $src2}",
1134 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1135 X86_COND_G, EFLAGS))]>,
1137 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1138 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1139 "cmovg\t{$src2, $dst|$dst, $src2}",
1140 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1141 X86_COND_G, EFLAGS))]>,
1143 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1144 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1145 "cmovs\t{$src2, $dst|$dst, $src2}",
1146 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1147 X86_COND_S, EFLAGS))]>,
1149 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1150 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1151 "cmovs\t{$src2, $dst|$dst, $src2}",
1152 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1153 X86_COND_S, EFLAGS))]>,
1155 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1156 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1157 "cmovns\t{$src2, $dst|$dst, $src2}",
1158 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1159 X86_COND_NS, EFLAGS))]>,
1161 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1162 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1163 "cmovns\t{$src2, $dst|$dst, $src2}",
1164 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1165 X86_COND_NS, EFLAGS))]>,
1167 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1168 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1169 "cmovp\t{$src2, $dst|$dst, $src2}",
1170 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1171 X86_COND_P, EFLAGS))]>,
1173 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1174 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1175 "cmovp\t{$src2, $dst|$dst, $src2}",
1176 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1177 X86_COND_P, EFLAGS))]>,
1179 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1180 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1181 "cmovnp\t{$src2, $dst|$dst, $src2}",
1182 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1183 X86_COND_NP, EFLAGS))]>,
1185 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1186 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1187 "cmovnp\t{$src2, $dst|$dst, $src2}",
1188 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1189 X86_COND_NP, EFLAGS))]>,
1191 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1192 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1193 "cmovo\t{$src2, $dst|$dst, $src2}",
1194 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1195 X86_COND_O, EFLAGS))]>,
1197 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1198 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1199 "cmovo\t{$src2, $dst|$dst, $src2}",
1200 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1201 X86_COND_O, EFLAGS))]>,
1203 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1204 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1205 "cmovno\t{$src2, $dst|$dst, $src2}",
1206 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1207 X86_COND_NO, EFLAGS))]>,
1209 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1210 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1211 "cmovno\t{$src2, $dst|$dst, $src2}",
1212 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1213 X86_COND_NO, EFLAGS))]>,
1215 } // Uses = [EFLAGS]
1218 // unary instructions
1219 let CodeSize = 2 in {
1220 let Defs = [EFLAGS] in {
1221 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1222 [(set GR8:$dst, (ineg GR8:$src))]>;
1223 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1224 [(set GR16:$dst, (ineg GR16:$src))]>, OpSize;
1225 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1226 [(set GR32:$dst, (ineg GR32:$src))]>;
1227 let isTwoAddress = 0 in {
1228 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1229 [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
1230 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1231 [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1232 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1233 [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
1236 } // Defs = [EFLAGS]
1238 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1239 [(set GR8:$dst, (not GR8:$src))]>;
1240 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1241 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1242 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1243 [(set GR32:$dst, (not GR32:$src))]>;
1244 let isTwoAddress = 0 in {
1245 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1246 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1247 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1248 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1249 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1250 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1254 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1255 let Defs = [EFLAGS] in {
1257 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1258 [(set GR8:$dst, (add GR8:$src, 1))]>;
1259 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1260 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1261 [(set GR16:$dst, (add GR16:$src, 1))]>,
1262 OpSize, Requires<[In32BitMode]>;
1263 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1264 [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>;
1266 let isTwoAddress = 0, CodeSize = 2 in {
1267 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1268 [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
1269 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1270 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>,
1271 OpSize, Requires<[In32BitMode]>;
1272 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1273 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>,
1274 Requires<[In32BitMode]>;
1278 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1279 [(set GR8:$dst, (add GR8:$src, -1))]>;
1280 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1281 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1282 [(set GR16:$dst, (add GR16:$src, -1))]>,
1283 OpSize, Requires<[In32BitMode]>;
1284 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1285 [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>;
1288 let isTwoAddress = 0, CodeSize = 2 in {
1289 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1290 [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
1291 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1292 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>,
1293 OpSize, Requires<[In32BitMode]>;
1294 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1295 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>,
1296 Requires<[In32BitMode]>;
1298 } // Defs = [EFLAGS]
1300 // Logical operators...
1301 let Defs = [EFLAGS] in {
1302 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1303 def AND8rr : I<0x20, MRMDestReg,
1304 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1305 "and{b}\t{$src2, $dst|$dst, $src2}",
1306 [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>;
1307 def AND16rr : I<0x21, MRMDestReg,
1308 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1309 "and{w}\t{$src2, $dst|$dst, $src2}",
1310 [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize;
1311 def AND32rr : I<0x21, MRMDestReg,
1312 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1313 "and{l}\t{$src2, $dst|$dst, $src2}",
1314 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
1317 def AND8rm : I<0x22, MRMSrcMem,
1318 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1319 "and{b}\t{$src2, $dst|$dst, $src2}",
1320 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>;
1321 def AND16rm : I<0x23, MRMSrcMem,
1322 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1323 "and{w}\t{$src2, $dst|$dst, $src2}",
1324 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize;
1325 def AND32rm : I<0x23, MRMSrcMem,
1326 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1327 "and{l}\t{$src2, $dst|$dst, $src2}",
1328 [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>;
1330 def AND8ri : Ii8<0x80, MRM4r,
1331 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1332 "and{b}\t{$src2, $dst|$dst, $src2}",
1333 [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>;
1334 def AND16ri : Ii16<0x81, MRM4r,
1335 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1336 "and{w}\t{$src2, $dst|$dst, $src2}",
1337 [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize;
1338 def AND32ri : Ii32<0x81, MRM4r,
1339 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1340 "and{l}\t{$src2, $dst|$dst, $src2}",
1341 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
1342 def AND16ri8 : Ii8<0x83, MRM4r,
1343 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1344 "and{w}\t{$src2, $dst|$dst, $src2}",
1345 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>,
1347 def AND32ri8 : Ii8<0x83, MRM4r,
1348 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1349 "and{l}\t{$src2, $dst|$dst, $src2}",
1350 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>;
1352 let isTwoAddress = 0 in {
1353 def AND8mr : I<0x20, MRMDestMem,
1354 (outs), (ins i8mem :$dst, GR8 :$src),
1355 "and{b}\t{$src, $dst|$dst, $src}",
1356 [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>;
1357 def AND16mr : I<0x21, MRMDestMem,
1358 (outs), (ins i16mem:$dst, GR16:$src),
1359 "and{w}\t{$src, $dst|$dst, $src}",
1360 [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>,
1362 def AND32mr : I<0x21, MRMDestMem,
1363 (outs), (ins i32mem:$dst, GR32:$src),
1364 "and{l}\t{$src, $dst|$dst, $src}",
1365 [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>;
1366 def AND8mi : Ii8<0x80, MRM4m,
1367 (outs), (ins i8mem :$dst, i8imm :$src),
1368 "and{b}\t{$src, $dst|$dst, $src}",
1369 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1370 def AND16mi : Ii16<0x81, MRM4m,
1371 (outs), (ins i16mem:$dst, i16imm:$src),
1372 "and{w}\t{$src, $dst|$dst, $src}",
1373 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1375 def AND32mi : Ii32<0x81, MRM4m,
1376 (outs), (ins i32mem:$dst, i32imm:$src),
1377 "and{l}\t{$src, $dst|$dst, $src}",
1378 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1379 def AND16mi8 : Ii8<0x83, MRM4m,
1380 (outs), (ins i16mem:$dst, i16i8imm :$src),
1381 "and{w}\t{$src, $dst|$dst, $src}",
1382 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1384 def AND32mi8 : Ii8<0x83, MRM4m,
1385 (outs), (ins i32mem:$dst, i32i8imm :$src),
1386 "and{l}\t{$src, $dst|$dst, $src}",
1387 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1391 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1392 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1393 "or{b}\t{$src2, $dst|$dst, $src2}",
1394 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
1395 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1396 "or{w}\t{$src2, $dst|$dst, $src2}",
1397 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize;
1398 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1399 "or{l}\t{$src2, $dst|$dst, $src2}",
1400 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
1402 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1403 "or{b}\t{$src2, $dst|$dst, $src2}",
1404 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
1405 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1406 "or{w}\t{$src2, $dst|$dst, $src2}",
1407 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize;
1408 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1409 "or{l}\t{$src2, $dst|$dst, $src2}",
1410 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>;
1412 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1413 "or{b}\t{$src2, $dst|$dst, $src2}",
1414 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
1415 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1416 "or{w}\t{$src2, $dst|$dst, $src2}",
1417 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize;
1418 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1419 "or{l}\t{$src2, $dst|$dst, $src2}",
1420 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
1422 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1423 "or{w}\t{$src2, $dst|$dst, $src2}",
1424 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1425 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1426 "or{l}\t{$src2, $dst|$dst, $src2}",
1427 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>;
1428 let isTwoAddress = 0 in {
1429 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1430 "or{b}\t{$src, $dst|$dst, $src}",
1431 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
1432 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1433 "or{w}\t{$src, $dst|$dst, $src}",
1434 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize;
1435 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1436 "or{l}\t{$src, $dst|$dst, $src}",
1437 [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>;
1438 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1439 "or{b}\t{$src, $dst|$dst, $src}",
1440 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1441 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1442 "or{w}\t{$src, $dst|$dst, $src}",
1443 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1445 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1446 "or{l}\t{$src, $dst|$dst, $src}",
1447 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1448 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1449 "or{w}\t{$src, $dst|$dst, $src}",
1450 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1452 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1453 "or{l}\t{$src, $dst|$dst, $src}",
1454 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1455 } // isTwoAddress = 0
1458 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1459 def XOR8rr : I<0x30, MRMDestReg,
1460 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1461 "xor{b}\t{$src2, $dst|$dst, $src2}",
1462 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>;
1463 def XOR16rr : I<0x31, MRMDestReg,
1464 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1465 "xor{w}\t{$src2, $dst|$dst, $src2}",
1466 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize;
1467 def XOR32rr : I<0x31, MRMDestReg,
1468 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1469 "xor{l}\t{$src2, $dst|$dst, $src2}",
1470 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
1471 } // isCommutable = 1
1473 def XOR8rm : I<0x32, MRMSrcMem ,
1474 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1475 "xor{b}\t{$src2, $dst|$dst, $src2}",
1476 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>;
1477 def XOR16rm : I<0x33, MRMSrcMem ,
1478 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1479 "xor{w}\t{$src2, $dst|$dst, $src2}",
1480 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>,
1482 def XOR32rm : I<0x33, MRMSrcMem ,
1483 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1484 "xor{l}\t{$src2, $dst|$dst, $src2}",
1485 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>;
1487 def XOR8ri : Ii8<0x80, MRM6r,
1488 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1489 "xor{b}\t{$src2, $dst|$dst, $src2}",
1490 [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>;
1491 def XOR16ri : Ii16<0x81, MRM6r,
1492 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1493 "xor{w}\t{$src2, $dst|$dst, $src2}",
1494 [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize;
1495 def XOR32ri : Ii32<0x81, MRM6r,
1496 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1497 "xor{l}\t{$src2, $dst|$dst, $src2}",
1498 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
1499 def XOR16ri8 : Ii8<0x83, MRM6r,
1500 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1501 "xor{w}\t{$src2, $dst|$dst, $src2}",
1502 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>,
1504 def XOR32ri8 : Ii8<0x83, MRM6r,
1505 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1506 "xor{l}\t{$src2, $dst|$dst, $src2}",
1507 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>;
1509 let isTwoAddress = 0 in {
1510 def XOR8mr : I<0x30, MRMDestMem,
1511 (outs), (ins i8mem :$dst, GR8 :$src),
1512 "xor{b}\t{$src, $dst|$dst, $src}",
1513 [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>;
1514 def XOR16mr : I<0x31, MRMDestMem,
1515 (outs), (ins i16mem:$dst, GR16:$src),
1516 "xor{w}\t{$src, $dst|$dst, $src}",
1517 [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>,
1519 def XOR32mr : I<0x31, MRMDestMem,
1520 (outs), (ins i32mem:$dst, GR32:$src),
1521 "xor{l}\t{$src, $dst|$dst, $src}",
1522 [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>;
1523 def XOR8mi : Ii8<0x80, MRM6m,
1524 (outs), (ins i8mem :$dst, i8imm :$src),
1525 "xor{b}\t{$src, $dst|$dst, $src}",
1526 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1527 def XOR16mi : Ii16<0x81, MRM6m,
1528 (outs), (ins i16mem:$dst, i16imm:$src),
1529 "xor{w}\t{$src, $dst|$dst, $src}",
1530 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1532 def XOR32mi : Ii32<0x81, MRM6m,
1533 (outs), (ins i32mem:$dst, i32imm:$src),
1534 "xor{l}\t{$src, $dst|$dst, $src}",
1535 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1536 def XOR16mi8 : Ii8<0x83, MRM6m,
1537 (outs), (ins i16mem:$dst, i16i8imm :$src),
1538 "xor{w}\t{$src, $dst|$dst, $src}",
1539 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1541 def XOR32mi8 : Ii8<0x83, MRM6m,
1542 (outs), (ins i32mem:$dst, i32i8imm :$src),
1543 "xor{l}\t{$src, $dst|$dst, $src}",
1544 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1545 } // isTwoAddress = 0
1546 } // Defs = [EFLAGS]
1548 // Shift instructions
1549 let Defs = [EFLAGS] in {
1550 let Uses = [CL] in {
1551 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1552 "shl{b}\t{%cl, $dst|$dst, %CL}",
1553 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1554 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1555 "shl{w}\t{%cl, $dst|$dst, %CL}",
1556 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1557 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1558 "shl{l}\t{%cl, $dst|$dst, %CL}",
1559 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1562 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1563 "shl{b}\t{$src2, $dst|$dst, $src2}",
1564 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1565 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1566 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1567 "shl{w}\t{$src2, $dst|$dst, $src2}",
1568 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1569 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1570 "shl{l}\t{$src2, $dst|$dst, $src2}",
1571 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1572 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1574 } // isConvertibleToThreeAddress = 1
1576 let isTwoAddress = 0 in {
1577 let Uses = [CL] in {
1578 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1579 "shl{b}\t{%cl, $dst|$dst, %CL}",
1580 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1581 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1582 "shl{w}\t{%cl, $dst|$dst, %CL}",
1583 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1584 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1585 "shl{l}\t{%cl, $dst|$dst, %CL}",
1586 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1588 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1589 "shl{b}\t{$src, $dst|$dst, $src}",
1590 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1591 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1592 "shl{w}\t{$src, $dst|$dst, $src}",
1593 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1595 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1596 "shl{l}\t{$src, $dst|$dst, $src}",
1597 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1600 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1602 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1603 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1605 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1607 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1609 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1612 let Uses = [CL] in {
1613 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1614 "shr{b}\t{%cl, $dst|$dst, %CL}",
1615 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1616 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1617 "shr{w}\t{%cl, $dst|$dst, %CL}",
1618 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1619 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1620 "shr{l}\t{%cl, $dst|$dst, %CL}",
1621 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1624 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1625 "shr{b}\t{$src2, $dst|$dst, $src2}",
1626 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1627 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1628 "shr{w}\t{$src2, $dst|$dst, $src2}",
1629 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1630 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1631 "shr{l}\t{$src2, $dst|$dst, $src2}",
1632 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1635 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1637 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1638 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1640 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1641 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1643 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1645 let isTwoAddress = 0 in {
1646 let Uses = [CL] in {
1647 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1648 "shr{b}\t{%cl, $dst|$dst, %CL}",
1649 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1650 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1651 "shr{w}\t{%cl, $dst|$dst, %CL}",
1652 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1654 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1655 "shr{l}\t{%cl, $dst|$dst, %CL}",
1656 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1658 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1659 "shr{b}\t{$src, $dst|$dst, $src}",
1660 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1661 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1662 "shr{w}\t{$src, $dst|$dst, $src}",
1663 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1665 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1666 "shr{l}\t{$src, $dst|$dst, $src}",
1667 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1670 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1672 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1673 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1675 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1676 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1678 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1681 let Uses = [CL] in {
1682 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1683 "sar{b}\t{%cl, $dst|$dst, %CL}",
1684 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1685 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1686 "sar{w}\t{%cl, $dst|$dst, %CL}",
1687 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1688 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1689 "sar{l}\t{%cl, $dst|$dst, %CL}",
1690 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1693 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1694 "sar{b}\t{$src2, $dst|$dst, $src2}",
1695 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1696 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1697 "sar{w}\t{$src2, $dst|$dst, $src2}",
1698 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1700 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1701 "sar{l}\t{$src2, $dst|$dst, $src2}",
1702 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1705 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1707 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1708 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1710 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1711 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1713 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1715 let isTwoAddress = 0 in {
1716 let Uses = [CL] in {
1717 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1718 "sar{b}\t{%cl, $dst|$dst, %CL}",
1719 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
1720 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1721 "sar{w}\t{%cl, $dst|$dst, %CL}",
1722 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1723 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1724 "sar{l}\t{%cl, $dst|$dst, %CL}",
1725 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1727 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1728 "sar{b}\t{$src, $dst|$dst, $src}",
1729 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1730 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1731 "sar{w}\t{$src, $dst|$dst, $src}",
1732 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1734 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1735 "sar{l}\t{$src, $dst|$dst, $src}",
1736 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1739 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1741 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1742 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1744 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1746 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
1748 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1751 // Rotate instructions
1752 // FIXME: provide shorter instructions when imm8 == 1
1753 let Uses = [CL] in {
1754 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
1755 "rol{b}\t{%cl, $dst|$dst, %CL}",
1756 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
1757 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
1758 "rol{w}\t{%cl, $dst|$dst, %CL}",
1759 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
1760 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
1761 "rol{l}\t{%cl, $dst|$dst, %CL}",
1762 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
1765 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1766 "rol{b}\t{$src2, $dst|$dst, $src2}",
1767 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1768 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1769 "rol{w}\t{$src2, $dst|$dst, $src2}",
1770 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1771 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1772 "rol{l}\t{$src2, $dst|$dst, $src2}",
1773 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1776 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1778 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1779 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
1781 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1782 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1784 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1786 let isTwoAddress = 0 in {
1787 let Uses = [CL] in {
1788 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
1789 "rol{b}\t{%cl, $dst|$dst, %CL}",
1790 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
1791 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
1792 "rol{w}\t{%cl, $dst|$dst, %CL}",
1793 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1794 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
1795 "rol{l}\t{%cl, $dst|$dst, %CL}",
1796 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
1798 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
1799 "rol{b}\t{$src, $dst|$dst, $src}",
1800 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1801 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
1802 "rol{w}\t{$src, $dst|$dst, $src}",
1803 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1805 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
1806 "rol{l}\t{$src, $dst|$dst, $src}",
1807 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1810 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
1812 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1813 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
1815 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1817 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
1819 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1822 let Uses = [CL] in {
1823 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
1824 "ror{b}\t{%cl, $dst|$dst, %CL}",
1825 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
1826 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
1827 "ror{w}\t{%cl, $dst|$dst, %CL}",
1828 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
1829 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
1830 "ror{l}\t{%cl, $dst|$dst, %CL}",
1831 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
1834 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1835 "ror{b}\t{$src2, $dst|$dst, $src2}",
1836 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
1837 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1838 "ror{w}\t{$src2, $dst|$dst, $src2}",
1839 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1840 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1841 "ror{l}\t{$src2, $dst|$dst, $src2}",
1842 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
1845 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1847 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
1848 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
1850 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
1851 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
1853 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
1855 let isTwoAddress = 0 in {
1856 let Uses = [CL] in {
1857 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
1858 "ror{b}\t{%cl, $dst|$dst, %CL}",
1859 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
1860 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
1861 "ror{w}\t{%cl, $dst|$dst, %CL}",
1862 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1863 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
1864 "ror{l}\t{%cl, $dst|$dst, %CL}",
1865 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
1867 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1868 "ror{b}\t{$src, $dst|$dst, $src}",
1869 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1870 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
1871 "ror{w}\t{$src, $dst|$dst, $src}",
1872 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1874 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
1875 "ror{l}\t{$src, $dst|$dst, $src}",
1876 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1879 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
1881 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1882 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
1884 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1886 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
1888 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1893 // Double shift instructions (generalizations of rotate)
1894 let Uses = [CL] in {
1895 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1896 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1897 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
1898 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1899 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1900 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
1901 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1902 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1903 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
1905 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1906 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1907 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
1911 let isCommutable = 1 in { // These instructions commute to each other.
1912 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
1913 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1914 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1915 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
1918 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
1919 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1920 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1921 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
1924 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
1925 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1926 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1927 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
1930 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
1931 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1932 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1933 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
1938 let isTwoAddress = 0 in {
1939 let Uses = [CL] in {
1940 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1941 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1942 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
1944 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1945 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1946 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
1949 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
1950 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1951 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1952 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
1953 (i8 imm:$src3)), addr:$dst)]>,
1955 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
1956 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1957 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1958 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
1959 (i8 imm:$src3)), addr:$dst)]>,
1962 let Uses = [CL] in {
1963 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1964 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1965 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
1966 addr:$dst)]>, TB, OpSize;
1967 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1968 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1969 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
1970 addr:$dst)]>, TB, OpSize;
1972 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
1973 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1974 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1975 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
1976 (i8 imm:$src3)), addr:$dst)]>,
1978 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
1979 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1980 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1981 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
1982 (i8 imm:$src3)), addr:$dst)]>,
1985 } // Defs = [EFLAGS]
1989 let Defs = [EFLAGS] in {
1990 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1991 // Register-Register Addition
1992 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
1993 (ins GR8 :$src1, GR8 :$src2),
1994 "add{b}\t{$src2, $dst|$dst, $src2}",
1995 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
1996 (implicit EFLAGS)]>;
1998 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1999 // Register-Register Addition
2000 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2001 (ins GR16:$src1, GR16:$src2),
2002 "add{w}\t{$src2, $dst|$dst, $src2}",
2003 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2004 (implicit EFLAGS)]>, OpSize;
2005 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2006 (ins GR32:$src1, GR32:$src2),
2007 "add{l}\t{$src2, $dst|$dst, $src2}",
2008 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2009 (implicit EFLAGS)]>;
2010 } // end isConvertibleToThreeAddress
2011 } // end isCommutable
2013 // Register-Memory Addition
2014 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2015 (ins GR8 :$src1, i8mem :$src2),
2016 "add{b}\t{$src2, $dst|$dst, $src2}",
2017 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2018 (implicit EFLAGS)]>;
2019 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2020 (ins GR16:$src1, i16mem:$src2),
2021 "add{w}\t{$src2, $dst|$dst, $src2}",
2022 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2023 (implicit EFLAGS)]>, OpSize;
2024 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2025 (ins GR32:$src1, i32mem:$src2),
2026 "add{l}\t{$src2, $dst|$dst, $src2}",
2027 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2028 (implicit EFLAGS)]>;
2030 // Register-Integer Addition
2031 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2032 "add{b}\t{$src2, $dst|$dst, $src2}",
2033 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2034 (implicit EFLAGS)]>;
2036 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2037 // Register-Integer Addition
2038 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2039 (ins GR16:$src1, i16imm:$src2),
2040 "add{w}\t{$src2, $dst|$dst, $src2}",
2041 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2042 (implicit EFLAGS)]>, OpSize;
2043 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2044 (ins GR32:$src1, i32imm:$src2),
2045 "add{l}\t{$src2, $dst|$dst, $src2}",
2046 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2047 (implicit EFLAGS)]>;
2048 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2049 (ins GR16:$src1, i16i8imm:$src2),
2050 "add{w}\t{$src2, $dst|$dst, $src2}",
2051 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2052 (implicit EFLAGS)]>, OpSize;
2053 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2054 (ins GR32:$src1, i32i8imm:$src2),
2055 "add{l}\t{$src2, $dst|$dst, $src2}",
2056 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2057 (implicit EFLAGS)]>;
2060 let isTwoAddress = 0 in {
2061 // Memory-Register Addition
2062 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2063 "add{b}\t{$src2, $dst|$dst, $src2}",
2064 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2065 (implicit EFLAGS)]>;
2066 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2067 "add{w}\t{$src2, $dst|$dst, $src2}",
2068 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2069 (implicit EFLAGS)]>, OpSize;
2070 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2071 "add{l}\t{$src2, $dst|$dst, $src2}",
2072 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2073 (implicit EFLAGS)]>;
2074 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2075 "add{b}\t{$src2, $dst|$dst, $src2}",
2076 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2077 (implicit EFLAGS)]>;
2078 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2079 "add{w}\t{$src2, $dst|$dst, $src2}",
2080 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2081 (implicit EFLAGS)]>, OpSize;
2082 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2083 "add{l}\t{$src2, $dst|$dst, $src2}",
2084 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2085 (implicit EFLAGS)]>;
2086 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2087 "add{w}\t{$src2, $dst|$dst, $src2}",
2088 [(store (add (load addr:$dst), i16immSExt8:$src2),
2090 (implicit EFLAGS)]>, OpSize;
2091 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2092 "add{l}\t{$src2, $dst|$dst, $src2}",
2093 [(store (add (load addr:$dst), i32immSExt8:$src2),
2095 (implicit EFLAGS)]>;
2098 let Uses = [EFLAGS] in {
2099 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2100 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2101 "adc{l}\t{$src2, $dst|$dst, $src2}",
2102 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2104 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2105 "adc{l}\t{$src2, $dst|$dst, $src2}",
2106 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2107 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2108 "adc{l}\t{$src2, $dst|$dst, $src2}",
2109 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2110 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2111 "adc{l}\t{$src2, $dst|$dst, $src2}",
2112 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2114 let isTwoAddress = 0 in {
2115 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2116 "adc{l}\t{$src2, $dst|$dst, $src2}",
2117 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2118 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2119 "adc{l}\t{$src2, $dst|$dst, $src2}",
2120 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2121 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2122 "adc{l}\t{$src2, $dst|$dst, $src2}",
2123 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2125 } // Uses = [EFLAGS]
2127 // Register-Register Subtraction
2128 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2129 "sub{b}\t{$src2, $dst|$dst, $src2}",
2130 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2131 (implicit EFLAGS)]>;
2132 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2133 "sub{w}\t{$src2, $dst|$dst, $src2}",
2134 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2135 (implicit EFLAGS)]>, OpSize;
2136 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2137 "sub{l}\t{$src2, $dst|$dst, $src2}",
2138 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2139 (implicit EFLAGS)]>;
2141 // Register-Memory Subtraction
2142 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2143 (ins GR8 :$src1, i8mem :$src2),
2144 "sub{b}\t{$src2, $dst|$dst, $src2}",
2145 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2146 (implicit EFLAGS)]>;
2147 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2148 (ins GR16:$src1, i16mem:$src2),
2149 "sub{w}\t{$src2, $dst|$dst, $src2}",
2150 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2151 (implicit EFLAGS)]>, OpSize;
2152 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2153 (ins GR32:$src1, i32mem:$src2),
2154 "sub{l}\t{$src2, $dst|$dst, $src2}",
2155 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2156 (implicit EFLAGS)]>;
2158 // Register-Integer Subtraction
2159 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2160 (ins GR8:$src1, i8imm:$src2),
2161 "sub{b}\t{$src2, $dst|$dst, $src2}",
2162 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2163 (implicit EFLAGS)]>;
2164 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2165 (ins GR16:$src1, i16imm:$src2),
2166 "sub{w}\t{$src2, $dst|$dst, $src2}",
2167 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2168 (implicit EFLAGS)]>, OpSize;
2169 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2170 (ins GR32:$src1, i32imm:$src2),
2171 "sub{l}\t{$src2, $dst|$dst, $src2}",
2172 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2173 (implicit EFLAGS)]>;
2174 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2175 (ins GR16:$src1, i16i8imm:$src2),
2176 "sub{w}\t{$src2, $dst|$dst, $src2}",
2177 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2178 (implicit EFLAGS)]>, OpSize;
2179 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2180 (ins GR32:$src1, i32i8imm:$src2),
2181 "sub{l}\t{$src2, $dst|$dst, $src2}",
2182 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2183 (implicit EFLAGS)]>;
2185 let isTwoAddress = 0 in {
2186 // Memory-Register Subtraction
2187 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2188 "sub{b}\t{$src2, $dst|$dst, $src2}",
2189 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2190 (implicit EFLAGS)]>;
2191 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2192 "sub{w}\t{$src2, $dst|$dst, $src2}",
2193 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2194 (implicit EFLAGS)]>, OpSize;
2195 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2196 "sub{l}\t{$src2, $dst|$dst, $src2}",
2197 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2198 (implicit EFLAGS)]>;
2200 // Memory-Integer Subtraction
2201 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2202 "sub{b}\t{$src2, $dst|$dst, $src2}",
2203 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2204 (implicit EFLAGS)]>;
2205 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2206 "sub{w}\t{$src2, $dst|$dst, $src2}",
2207 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2208 (implicit EFLAGS)]>, OpSize;
2209 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2210 "sub{l}\t{$src2, $dst|$dst, $src2}",
2211 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2212 (implicit EFLAGS)]>;
2213 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2214 "sub{w}\t{$src2, $dst|$dst, $src2}",
2215 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2217 (implicit EFLAGS)]>, OpSize;
2218 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2219 "sub{l}\t{$src2, $dst|$dst, $src2}",
2220 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2222 (implicit EFLAGS)]>;
2225 let Uses = [EFLAGS] in {
2226 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2227 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2228 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2230 let isTwoAddress = 0 in {
2231 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2232 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2233 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2234 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2235 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2236 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2237 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2238 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2239 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2240 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2241 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2242 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2244 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2245 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2246 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2247 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2248 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2249 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2250 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2251 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2252 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2253 } // Uses = [EFLAGS]
2254 } // Defs = [EFLAGS]
2256 let Defs = [EFLAGS] in {
2257 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2258 // Register-Register Signed Integer Multiply
2259 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2260 "imul{w}\t{$src2, $dst|$dst, $src2}",
2261 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
2262 (implicit EFLAGS)]>, TB, OpSize;
2263 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2264 "imul{l}\t{$src2, $dst|$dst, $src2}",
2265 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
2266 (implicit EFLAGS)]>, TB;
2269 // Register-Memory Signed Integer Multiply
2270 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
2271 (ins GR16:$src1, i16mem:$src2),
2272 "imul{w}\t{$src2, $dst|$dst, $src2}",
2273 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
2274 (implicit EFLAGS)]>, TB, OpSize;
2275 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2276 "imul{l}\t{$src2, $dst|$dst, $src2}",
2277 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
2278 (implicit EFLAGS)]>, TB;
2279 } // Defs = [EFLAGS]
2280 } // end Two Address instructions
2282 // Suprisingly enough, these are not two address instructions!
2283 let Defs = [EFLAGS] in {
2284 // Register-Integer Signed Integer Multiply
2285 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2286 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2287 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2288 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
2289 (implicit EFLAGS)]>, OpSize;
2290 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2291 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2292 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2293 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
2294 (implicit EFLAGS)]>;
2295 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2296 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2297 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2298 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
2299 (implicit EFLAGS)]>, OpSize;
2300 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2301 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2302 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2303 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
2304 (implicit EFLAGS)]>;
2306 // Memory-Integer Signed Integer Multiply
2307 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2308 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2309 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2310 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
2311 (implicit EFLAGS)]>, OpSize;
2312 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2313 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2314 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2315 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
2316 (implicit EFLAGS)]>;
2317 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2318 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2319 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2320 [(set GR16:$dst, (mul (load addr:$src1),
2321 i16immSExt8:$src2)),
2322 (implicit EFLAGS)]>, OpSize;
2323 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2324 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2325 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2326 [(set GR32:$dst, (mul (load addr:$src1),
2327 i32immSExt8:$src2)),
2328 (implicit EFLAGS)]>;
2329 } // Defs = [EFLAGS]
2331 //===----------------------------------------------------------------------===//
2332 // Test instructions are just like AND, except they don't generate a result.
2334 let Defs = [EFLAGS] in {
2335 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2336 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2337 "test{b}\t{$src2, $src1|$src1, $src2}",
2338 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
2339 (implicit EFLAGS)]>;
2340 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2341 "test{w}\t{$src2, $src1|$src1, $src2}",
2342 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
2343 (implicit EFLAGS)]>,
2345 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2346 "test{l}\t{$src2, $src1|$src1, $src2}",
2347 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
2348 (implicit EFLAGS)]>;
2351 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2352 "test{b}\t{$src2, $src1|$src1, $src2}",
2353 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2354 (implicit EFLAGS)]>;
2355 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2356 "test{w}\t{$src2, $src1|$src1, $src2}",
2357 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2358 (implicit EFLAGS)]>, OpSize;
2359 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2360 "test{l}\t{$src2, $src1|$src1, $src2}",
2361 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2362 (implicit EFLAGS)]>;
2364 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2365 (outs), (ins GR8:$src1, i8imm:$src2),
2366 "test{b}\t{$src2, $src1|$src1, $src2}",
2367 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
2368 (implicit EFLAGS)]>;
2369 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2370 (outs), (ins GR16:$src1, i16imm:$src2),
2371 "test{w}\t{$src2, $src1|$src1, $src2}",
2372 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
2373 (implicit EFLAGS)]>, OpSize;
2374 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2375 (outs), (ins GR32:$src1, i32imm:$src2),
2376 "test{l}\t{$src2, $src1|$src1, $src2}",
2377 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
2378 (implicit EFLAGS)]>;
2380 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2381 (outs), (ins i8mem:$src1, i8imm:$src2),
2382 "test{b}\t{$src2, $src1|$src1, $src2}",
2383 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2384 (implicit EFLAGS)]>;
2385 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2386 (outs), (ins i16mem:$src1, i16imm:$src2),
2387 "test{w}\t{$src2, $src1|$src1, $src2}",
2388 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2389 (implicit EFLAGS)]>, OpSize;
2390 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2391 (outs), (ins i32mem:$src1, i32imm:$src2),
2392 "test{l}\t{$src2, $src1|$src1, $src2}",
2393 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2394 (implicit EFLAGS)]>;
2395 } // Defs = [EFLAGS]
2398 // Condition code ops, incl. set if equal/not equal/...
2399 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2400 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2401 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2402 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2404 let Uses = [EFLAGS] in {
2405 def SETEr : I<0x94, MRM0r,
2406 (outs GR8 :$dst), (ins),
2408 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2410 def SETEm : I<0x94, MRM0m,
2411 (outs), (ins i8mem:$dst),
2413 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2416 def SETNEr : I<0x95, MRM0r,
2417 (outs GR8 :$dst), (ins),
2419 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2421 def SETNEm : I<0x95, MRM0m,
2422 (outs), (ins i8mem:$dst),
2424 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2427 def SETLr : I<0x9C, MRM0r,
2428 (outs GR8 :$dst), (ins),
2430 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2431 TB; // GR8 = < signed
2432 def SETLm : I<0x9C, MRM0m,
2433 (outs), (ins i8mem:$dst),
2435 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2436 TB; // [mem8] = < signed
2438 def SETGEr : I<0x9D, MRM0r,
2439 (outs GR8 :$dst), (ins),
2441 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2442 TB; // GR8 = >= signed
2443 def SETGEm : I<0x9D, MRM0m,
2444 (outs), (ins i8mem:$dst),
2446 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2447 TB; // [mem8] = >= signed
2449 def SETLEr : I<0x9E, MRM0r,
2450 (outs GR8 :$dst), (ins),
2452 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2453 TB; // GR8 = <= signed
2454 def SETLEm : I<0x9E, MRM0m,
2455 (outs), (ins i8mem:$dst),
2457 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2458 TB; // [mem8] = <= signed
2460 def SETGr : I<0x9F, MRM0r,
2461 (outs GR8 :$dst), (ins),
2463 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2464 TB; // GR8 = > signed
2465 def SETGm : I<0x9F, MRM0m,
2466 (outs), (ins i8mem:$dst),
2468 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2469 TB; // [mem8] = > signed
2471 def SETBr : I<0x92, MRM0r,
2472 (outs GR8 :$dst), (ins),
2474 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2475 TB; // GR8 = < unsign
2476 def SETBm : I<0x92, MRM0m,
2477 (outs), (ins i8mem:$dst),
2479 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
2480 TB; // [mem8] = < unsign
2482 def SETAEr : I<0x93, MRM0r,
2483 (outs GR8 :$dst), (ins),
2485 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
2486 TB; // GR8 = >= unsign
2487 def SETAEm : I<0x93, MRM0m,
2488 (outs), (ins i8mem:$dst),
2490 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
2491 TB; // [mem8] = >= unsign
2493 def SETBEr : I<0x96, MRM0r,
2494 (outs GR8 :$dst), (ins),
2496 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
2497 TB; // GR8 = <= unsign
2498 def SETBEm : I<0x96, MRM0m,
2499 (outs), (ins i8mem:$dst),
2501 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
2502 TB; // [mem8] = <= unsign
2504 def SETAr : I<0x97, MRM0r,
2505 (outs GR8 :$dst), (ins),
2507 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
2508 TB; // GR8 = > signed
2509 def SETAm : I<0x97, MRM0m,
2510 (outs), (ins i8mem:$dst),
2512 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
2513 TB; // [mem8] = > signed
2515 def SETSr : I<0x98, MRM0r,
2516 (outs GR8 :$dst), (ins),
2518 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
2519 TB; // GR8 = <sign bit>
2520 def SETSm : I<0x98, MRM0m,
2521 (outs), (ins i8mem:$dst),
2523 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
2524 TB; // [mem8] = <sign bit>
2525 def SETNSr : I<0x99, MRM0r,
2526 (outs GR8 :$dst), (ins),
2528 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
2529 TB; // GR8 = !<sign bit>
2530 def SETNSm : I<0x99, MRM0m,
2531 (outs), (ins i8mem:$dst),
2533 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
2534 TB; // [mem8] = !<sign bit>
2536 def SETPr : I<0x9A, MRM0r,
2537 (outs GR8 :$dst), (ins),
2539 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
2541 def SETPm : I<0x9A, MRM0m,
2542 (outs), (ins i8mem:$dst),
2544 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
2545 TB; // [mem8] = parity
2546 def SETNPr : I<0x9B, MRM0r,
2547 (outs GR8 :$dst), (ins),
2549 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
2550 TB; // GR8 = not parity
2551 def SETNPm : I<0x9B, MRM0m,
2552 (outs), (ins i8mem:$dst),
2554 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
2555 TB; // [mem8] = not parity
2557 def SETOr : I<0x90, MRM0r,
2558 (outs GR8 :$dst), (ins),
2560 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
2561 TB; // GR8 = overflow
2562 def SETOm : I<0x90, MRM0m,
2563 (outs), (ins i8mem:$dst),
2565 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
2566 TB; // [mem8] = overflow
2567 def SETNOr : I<0x91, MRM0r,
2568 (outs GR8 :$dst), (ins),
2570 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
2571 TB; // GR8 = not overflow
2572 def SETNOm : I<0x91, MRM0m,
2573 (outs), (ins i8mem:$dst),
2575 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
2576 TB; // [mem8] = not overflow
2577 } // Uses = [EFLAGS]
2580 // Integer comparisons
2581 let Defs = [EFLAGS] in {
2582 def CMP8rr : I<0x38, MRMDestReg,
2583 (outs), (ins GR8 :$src1, GR8 :$src2),
2584 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2585 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2586 def CMP16rr : I<0x39, MRMDestReg,
2587 (outs), (ins GR16:$src1, GR16:$src2),
2588 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2589 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
2590 def CMP32rr : I<0x39, MRMDestReg,
2591 (outs), (ins GR32:$src1, GR32:$src2),
2592 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2593 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
2594 def CMP8mr : I<0x38, MRMDestMem,
2595 (outs), (ins i8mem :$src1, GR8 :$src2),
2596 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2597 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
2598 (implicit EFLAGS)]>;
2599 def CMP16mr : I<0x39, MRMDestMem,
2600 (outs), (ins i16mem:$src1, GR16:$src2),
2601 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2602 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
2603 (implicit EFLAGS)]>, OpSize;
2604 def CMP32mr : I<0x39, MRMDestMem,
2605 (outs), (ins i32mem:$src1, GR32:$src2),
2606 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2607 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
2608 (implicit EFLAGS)]>;
2609 def CMP8rm : I<0x3A, MRMSrcMem,
2610 (outs), (ins GR8 :$src1, i8mem :$src2),
2611 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2612 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
2613 (implicit EFLAGS)]>;
2614 def CMP16rm : I<0x3B, MRMSrcMem,
2615 (outs), (ins GR16:$src1, i16mem:$src2),
2616 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2617 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
2618 (implicit EFLAGS)]>, OpSize;
2619 def CMP32rm : I<0x3B, MRMSrcMem,
2620 (outs), (ins GR32:$src1, i32mem:$src2),
2621 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2622 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
2623 (implicit EFLAGS)]>;
2624 def CMP8ri : Ii8<0x80, MRM7r,
2625 (outs), (ins GR8:$src1, i8imm:$src2),
2626 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2627 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
2628 def CMP16ri : Ii16<0x81, MRM7r,
2629 (outs), (ins GR16:$src1, i16imm:$src2),
2630 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2631 [(X86cmp GR16:$src1, imm:$src2),
2632 (implicit EFLAGS)]>, OpSize;
2633 def CMP32ri : Ii32<0x81, MRM7r,
2634 (outs), (ins GR32:$src1, i32imm:$src2),
2635 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2636 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
2637 def CMP8mi : Ii8 <0x80, MRM7m,
2638 (outs), (ins i8mem :$src1, i8imm :$src2),
2639 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2640 [(X86cmp (loadi8 addr:$src1), imm:$src2),
2641 (implicit EFLAGS)]>;
2642 def CMP16mi : Ii16<0x81, MRM7m,
2643 (outs), (ins i16mem:$src1, i16imm:$src2),
2644 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2645 [(X86cmp (loadi16 addr:$src1), imm:$src2),
2646 (implicit EFLAGS)]>, OpSize;
2647 def CMP32mi : Ii32<0x81, MRM7m,
2648 (outs), (ins i32mem:$src1, i32imm:$src2),
2649 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2650 [(X86cmp (loadi32 addr:$src1), imm:$src2),
2651 (implicit EFLAGS)]>;
2652 def CMP16ri8 : Ii8<0x83, MRM7r,
2653 (outs), (ins GR16:$src1, i16i8imm:$src2),
2654 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2655 [(X86cmp GR16:$src1, i16immSExt8:$src2),
2656 (implicit EFLAGS)]>, OpSize;
2657 def CMP16mi8 : Ii8<0x83, MRM7m,
2658 (outs), (ins i16mem:$src1, i16i8imm:$src2),
2659 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2660 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
2661 (implicit EFLAGS)]>, OpSize;
2662 def CMP32mi8 : Ii8<0x83, MRM7m,
2663 (outs), (ins i32mem:$src1, i32i8imm:$src2),
2664 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2665 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
2666 (implicit EFLAGS)]>;
2667 def CMP32ri8 : Ii8<0x83, MRM7r,
2668 (outs), (ins GR32:$src1, i32i8imm:$src2),
2669 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2670 [(X86cmp GR32:$src1, i32immSExt8:$src2),
2671 (implicit EFLAGS)]>;
2672 } // Defs = [EFLAGS]
2675 // TODO: BTC, BTR, and BTS
2676 let Defs = [EFLAGS] in {
2677 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2678 "bt{w}\t{$src2, $src1|$src1, $src2}",
2679 [(X86bt GR16:$src1, GR16:$src2),
2680 (implicit EFLAGS)]>, OpSize, TB;
2681 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2682 "bt{l}\t{$src2, $src1|$src1, $src2}",
2683 [(X86bt GR32:$src1, GR32:$src2),
2684 (implicit EFLAGS)]>, TB;
2685 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
2686 "bt{w}\t{$src2, $src1|$src1, $src2}",
2687 [(X86bt (loadi16 addr:$src1), GR16:$src2),
2688 (implicit EFLAGS)]>, OpSize, TB, Requires<[FastBTMem]>;
2689 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
2690 "bt{l}\t{$src2, $src1|$src1, $src2}",
2691 [(X86bt (loadi32 addr:$src1), GR32:$src2),
2692 (implicit EFLAGS)]>, TB, Requires<[FastBTMem]>;
2694 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
2695 "bt{w}\t{$src2, $src1|$src1, $src2}",
2696 [(X86bt GR16:$src1, i16immSExt8:$src2),
2697 (implicit EFLAGS)]>, OpSize, TB;
2698 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
2699 "bt{l}\t{$src2, $src1|$src1, $src2}",
2700 [(X86bt GR32:$src1, i32immSExt8:$src2),
2701 (implicit EFLAGS)]>, TB;
2702 // Note that these instructions don't need FastBTMem because that
2703 // only applies when the other operand is in a register. When it's
2704 // an immediate, bt is still fast.
2705 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
2706 "bt{w}\t{$src2, $src1|$src1, $src2}",
2707 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
2708 (implicit EFLAGS)]>, OpSize, TB;
2709 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
2710 "bt{l}\t{$src2, $src1|$src1, $src2}",
2711 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
2712 (implicit EFLAGS)]>, TB;
2713 } // Defs = [EFLAGS]
2715 // Sign/Zero extenders
2716 // Use movsbl intead of movsbw; we don't care about the high 16 bits
2717 // of the register here. This has a smaller encoding and avoids a
2718 // partial-register update.
2719 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2720 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2721 [(set GR16:$dst, (sext GR8:$src))]>, TB;
2722 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2723 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2724 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
2725 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2726 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2727 [(set GR32:$dst, (sext GR8:$src))]>, TB;
2728 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2729 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2730 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
2731 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2732 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2733 [(set GR32:$dst, (sext GR16:$src))]>, TB;
2734 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2735 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2736 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
2738 // Use movzbl intead of movzbw; we don't care about the high 16 bits
2739 // of the register here. This has a smaller encoding and avoids a
2740 // partial-register update.
2741 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2742 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2743 [(set GR16:$dst, (zext GR8:$src))]>, TB;
2744 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2745 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2746 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
2747 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2748 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2749 [(set GR32:$dst, (zext GR8:$src))]>, TB;
2750 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2751 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2752 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
2753 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2754 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2755 [(set GR32:$dst, (zext GR16:$src))]>, TB;
2756 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2757 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2758 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
2760 let neverHasSideEffects = 1 in {
2761 let Defs = [AX], Uses = [AL] in
2762 def CBW : I<0x98, RawFrm, (outs), (ins),
2763 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
2764 let Defs = [EAX], Uses = [AX] in
2765 def CWDE : I<0x98, RawFrm, (outs), (ins),
2766 "{cwtl|cwde}", []>; // EAX = signext(AX)
2768 let Defs = [AX,DX], Uses = [AX] in
2769 def CWD : I<0x99, RawFrm, (outs), (ins),
2770 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
2771 let Defs = [EAX,EDX], Uses = [EAX] in
2772 def CDQ : I<0x99, RawFrm, (outs), (ins),
2773 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
2776 //===----------------------------------------------------------------------===//
2777 // Alias Instructions
2778 //===----------------------------------------------------------------------===//
2780 // Alias instructions that map movr0 to xor.
2781 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2782 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1 in {
2783 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
2784 "xor{b}\t$dst, $dst",
2785 [(set GR8:$dst, 0)]>;
2786 // Use xorl instead of xorw since we don't care about the high 16 bits,
2787 // it's smaller, and it avoids a partial-register update.
2788 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
2789 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
2790 [(set GR16:$dst, 0)]>;
2791 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
2792 "xor{l}\t$dst, $dst",
2793 [(set GR32:$dst, 0)]>;
2796 // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
2797 // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
2798 let neverHasSideEffects = 1 in {
2799 def MOV16to16_ : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16:$src),
2800 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2801 def MOV32to32_ : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32:$src),
2802 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2804 def MOV16_rr : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16_:$src),
2805 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2806 def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src),
2807 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2808 } // neverHasSideEffects
2810 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
2811 def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src),
2812 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2813 def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src),
2814 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2816 let mayStore = 1, neverHasSideEffects = 1 in {
2817 def MOV16_mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16_:$src),
2818 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2819 def MOV32_mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32_:$src),
2820 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2823 //===----------------------------------------------------------------------===//
2824 // Thread Local Storage Instructions
2828 def TLS_addr32 : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
2829 "leal\t${sym:mem}(,%ebx,1), $dst",
2830 [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
2832 let AddedComplexity = 10 in
2833 def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
2834 "movl\t%gs:($src), $dst",
2835 [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
2837 let AddedComplexity = 15 in
2838 def TLS_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
2839 "movl\t%gs:${src:mem}, $dst",
2841 (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>,
2844 def TLS_tp : I<0x8B, Pseudo, (outs GR32:$dst), (ins),
2845 "movl\t%gs:0, $dst",
2846 [(set GR32:$dst, X86TLStp)]>, SegGS;
2848 //===----------------------------------------------------------------------===//
2849 // DWARF Pseudo Instructions
2852 def DWARF_LOC : I<0, Pseudo, (outs),
2853 (ins i32imm:$line, i32imm:$col, i32imm:$file),
2854 ".loc\t${file:debug} ${line:debug} ${col:debug}",
2855 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
2858 //===----------------------------------------------------------------------===//
2859 // EH Pseudo Instructions
2861 let isTerminator = 1, isReturn = 1, isBarrier = 1,
2863 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
2864 "ret\t#eh_return, addr: $addr",
2865 [(X86ehret GR32:$addr)]>;
2869 //===----------------------------------------------------------------------===//
2873 // Atomic swap. These are just normal xchg instructions. But since a memory
2874 // operand is referenced, the atomicity is ensured.
2875 let Constraints = "$val = $dst" in {
2876 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2877 "xchg{l}\t{$val, $ptr|$ptr, $val}",
2878 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
2879 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2880 "xchg{w}\t{$val, $ptr|$ptr, $val}",
2881 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
2883 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2884 "xchg{b}\t{$val, $ptr|$ptr, $val}",
2885 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
2888 // Atomic compare and swap.
2889 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
2890 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
2891 "lock\n\tcmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
2892 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
2894 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
2895 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
2896 "lock\n\tcmpxchg8b\t$ptr",
2897 [(X86cas8 addr:$ptr)]>, TB, LOCK;
2900 let Defs = [AX, EFLAGS], Uses = [AX] in {
2901 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
2902 "lock\n\tcmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
2903 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
2905 let Defs = [AL, EFLAGS], Uses = [AL] in {
2906 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
2907 "lock\n\tcmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
2908 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
2911 // Atomic exchange and add
2912 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
2913 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2914 "lock\n\txadd{l}\t{$val, $ptr|$ptr, $val}",
2915 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
2917 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2918 "lock\n\txadd{w}\t{$val, $ptr|$ptr, $val}",
2919 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
2921 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2922 "lock\n\txadd{b}\t{$val, $ptr|$ptr, $val}",
2923 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
2927 // Atomic exchange, and, or, xor
2928 let Constraints = "$val = $dst", Defs = [EFLAGS],
2929 usesCustomDAGSchedInserter = 1 in {
2930 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2931 "#ATOMAND32 PSEUDO!",
2932 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
2933 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2934 "#ATOMOR32 PSEUDO!",
2935 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
2936 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2937 "#ATOMXOR32 PSEUDO!",
2938 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
2939 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2940 "#ATOMNAND32 PSEUDO!",
2941 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
2942 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2943 "#ATOMMIN32 PSEUDO!",
2944 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
2945 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2946 "#ATOMMAX32 PSEUDO!",
2947 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
2948 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2949 "#ATOMUMIN32 PSEUDO!",
2950 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
2951 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2952 "#ATOMUMAX32 PSEUDO!",
2953 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
2955 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2956 "#ATOMAND16 PSEUDO!",
2957 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
2958 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2959 "#ATOMOR16 PSEUDO!",
2960 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
2961 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2962 "#ATOMXOR16 PSEUDO!",
2963 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
2964 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2965 "#ATOMNAND16 PSEUDO!",
2966 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
2967 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2968 "#ATOMMIN16 PSEUDO!",
2969 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
2970 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2971 "#ATOMMAX16 PSEUDO!",
2972 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
2973 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2974 "#ATOMUMIN16 PSEUDO!",
2975 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
2976 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2977 "#ATOMUMAX16 PSEUDO!",
2978 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
2980 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
2981 "#ATOMAND8 PSEUDO!",
2982 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
2983 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
2985 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
2986 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
2987 "#ATOMXOR8 PSEUDO!",
2988 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
2989 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
2990 "#ATOMNAND8 PSEUDO!",
2991 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
2994 let Constraints = "$val1 = $dst1, $val2 = $dst2",
2995 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
2996 Uses = [EAX, EBX, ECX, EDX],
2997 mayLoad = 1, mayStore = 1,
2998 usesCustomDAGSchedInserter = 1 in {
2999 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3000 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3001 "#ATOMAND6432 PSEUDO!", []>;
3002 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3003 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3004 "#ATOMOR6432 PSEUDO!", []>;
3005 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3006 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3007 "#ATOMXOR6432 PSEUDO!", []>;
3008 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3009 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3010 "#ATOMNAND6432 PSEUDO!", []>;
3011 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3012 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3013 "#ATOMADD6432 PSEUDO!", []>;
3014 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3015 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3016 "#ATOMSUB6432 PSEUDO!", []>;
3017 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3018 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3019 "#ATOMSWAP6432 PSEUDO!", []>;
3022 //===----------------------------------------------------------------------===//
3023 // Non-Instruction Patterns
3024 //===----------------------------------------------------------------------===//
3026 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
3027 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
3028 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
3029 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
3030 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
3031 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
3033 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
3034 (ADD32ri GR32:$src1, tconstpool:$src2)>;
3035 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
3036 (ADD32ri GR32:$src1, tjumptable:$src2)>;
3037 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
3038 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
3039 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
3040 (ADD32ri GR32:$src1, texternalsym:$src2)>;
3042 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
3043 (MOV32mi addr:$dst, tglobaladdr:$src)>;
3044 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
3045 (MOV32mi addr:$dst, texternalsym:$src)>;
3049 def : Pat<(X86tailcall GR32:$dst),
3052 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
3054 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
3057 def : Pat<(X86tcret GR32:$dst, imm:$off),
3058 (TCRETURNri GR32:$dst, imm:$off)>;
3060 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
3061 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3063 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
3064 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3066 def : Pat<(X86call (i32 tglobaladdr:$dst)),
3067 (CALLpcrel32 tglobaladdr:$dst)>;
3068 def : Pat<(X86call (i32 texternalsym:$dst)),
3069 (CALLpcrel32 texternalsym:$dst)>;
3071 // X86 specific add which produces a flag.
3072 def : Pat<(addc GR32:$src1, GR32:$src2),
3073 (ADD32rr GR32:$src1, GR32:$src2)>;
3074 def : Pat<(addc GR32:$src1, (load addr:$src2)),
3075 (ADD32rm GR32:$src1, addr:$src2)>;
3076 def : Pat<(addc GR32:$src1, imm:$src2),
3077 (ADD32ri GR32:$src1, imm:$src2)>;
3078 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
3079 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3081 def : Pat<(subc GR32:$src1, GR32:$src2),
3082 (SUB32rr GR32:$src1, GR32:$src2)>;
3083 def : Pat<(subc GR32:$src1, (load addr:$src2)),
3084 (SUB32rm GR32:$src1, addr:$src2)>;
3085 def : Pat<(subc GR32:$src1, imm:$src2),
3086 (SUB32ri GR32:$src1, imm:$src2)>;
3087 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
3088 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3092 // TEST R,R is smaller than CMP R,0
3093 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
3094 (TEST8rr GR8:$src1, GR8:$src1)>;
3095 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
3096 (TEST16rr GR16:$src1, GR16:$src1)>;
3097 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
3098 (TEST32rr GR32:$src1, GR32:$src1)>;
3100 // Conditional moves with folded loads with operands swapped and conditions
3102 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
3103 (CMOVAE16rm GR16:$src2, addr:$src1)>;
3104 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
3105 (CMOVAE32rm GR32:$src2, addr:$src1)>;
3106 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
3107 (CMOVB16rm GR16:$src2, addr:$src1)>;
3108 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
3109 (CMOVB32rm GR32:$src2, addr:$src1)>;
3110 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
3111 (CMOVNE16rm GR16:$src2, addr:$src1)>;
3112 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
3113 (CMOVNE32rm GR32:$src2, addr:$src1)>;
3114 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
3115 (CMOVE16rm GR16:$src2, addr:$src1)>;
3116 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
3117 (CMOVE32rm GR32:$src2, addr:$src1)>;
3118 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
3119 (CMOVA16rm GR16:$src2, addr:$src1)>;
3120 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
3121 (CMOVA32rm GR32:$src2, addr:$src1)>;
3122 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
3123 (CMOVBE16rm GR16:$src2, addr:$src1)>;
3124 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
3125 (CMOVBE32rm GR32:$src2, addr:$src1)>;
3126 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
3127 (CMOVGE16rm GR16:$src2, addr:$src1)>;
3128 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
3129 (CMOVGE32rm GR32:$src2, addr:$src1)>;
3130 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
3131 (CMOVL16rm GR16:$src2, addr:$src1)>;
3132 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
3133 (CMOVL32rm GR32:$src2, addr:$src1)>;
3134 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
3135 (CMOVG16rm GR16:$src2, addr:$src1)>;
3136 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
3137 (CMOVG32rm GR32:$src2, addr:$src1)>;
3138 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
3139 (CMOVLE16rm GR16:$src2, addr:$src1)>;
3140 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
3141 (CMOVLE32rm GR32:$src2, addr:$src1)>;
3142 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
3143 (CMOVNP16rm GR16:$src2, addr:$src1)>;
3144 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
3145 (CMOVNP32rm GR32:$src2, addr:$src1)>;
3146 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
3147 (CMOVP16rm GR16:$src2, addr:$src1)>;
3148 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
3149 (CMOVP32rm GR32:$src2, addr:$src1)>;
3150 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
3151 (CMOVNS16rm GR16:$src2, addr:$src1)>;
3152 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
3153 (CMOVNS32rm GR32:$src2, addr:$src1)>;
3154 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
3155 (CMOVS16rm GR16:$src2, addr:$src1)>;
3156 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
3157 (CMOVS32rm GR32:$src2, addr:$src1)>;
3158 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
3159 (CMOVNO16rm GR16:$src2, addr:$src1)>;
3160 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
3161 (CMOVNO32rm GR32:$src2, addr:$src1)>;
3162 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
3163 (CMOVO16rm GR16:$src2, addr:$src1)>;
3164 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
3165 (CMOVO32rm GR32:$src2, addr:$src1)>;
3167 // zextload bool -> zextload byte
3168 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3169 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3170 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3172 // extload bool -> extload byte
3173 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3174 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>,
3175 Requires<[In32BitMode]>;
3176 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3177 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>,
3178 Requires<[In32BitMode]>;
3179 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
3180 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
3183 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>,
3184 Requires<[In32BitMode]>;
3185 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>,
3186 Requires<[In32BitMode]>;
3187 def : Pat<(i32 (anyext GR16:$src)),
3188 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
3190 // (and (i32 load), 255) -> (zextload i8)
3191 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
3192 (MOVZX32rm8 addr:$src)>;
3193 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
3194 (MOVZX32rm16 addr:$src)>;
3196 //===----------------------------------------------------------------------===//
3198 //===----------------------------------------------------------------------===//
3200 // Odd encoding trick: -128 fits into an 8-bit immediate field while
3201 // +128 doesn't, so in this special case use a sub instead of an add.
3202 def : Pat<(add GR16:$src1, 128),
3203 (SUB16ri8 GR16:$src1, -128)>;
3204 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
3205 (SUB16mi8 addr:$dst, -128)>;
3206 def : Pat<(add GR32:$src1, 128),
3207 (SUB32ri8 GR32:$src1, -128)>;
3208 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
3209 (SUB32mi8 addr:$dst, -128)>;
3211 // r & (2^16-1) ==> movz
3212 def : Pat<(and GR32:$src1, 0xffff),
3213 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit)))>;
3214 // r & (2^8-1) ==> movz
3215 def : Pat<(and GR32:$src1, 0xff),
3216 (MOVZX32rr8 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src1),
3217 x86_subreg_8bit)))>,
3218 Requires<[In32BitMode]>;
3219 // r & (2^8-1) ==> movz
3220 def : Pat<(and GR16:$src1, 0xff),
3221 (MOVZX16rr8 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src1),
3222 x86_subreg_8bit)))>,
3223 Requires<[In32BitMode]>;
3225 // sext_inreg patterns
3226 def : Pat<(sext_inreg GR32:$src, i16),
3227 (MOVSX32rr16 (i16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)))>;
3228 def : Pat<(sext_inreg GR32:$src, i8),
3229 (MOVSX32rr8 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src),
3230 x86_subreg_8bit)))>,
3231 Requires<[In32BitMode]>;
3232 def : Pat<(sext_inreg GR16:$src, i8),
3233 (MOVSX16rr8 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src),
3234 x86_subreg_8bit)))>,
3235 Requires<[In32BitMode]>;
3238 def : Pat<(i16 (trunc GR32:$src)),
3239 (i16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
3240 def : Pat<(i8 (trunc GR32:$src)),
3241 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src), x86_subreg_8bit))>,
3242 Requires<[In32BitMode]>;
3243 def : Pat<(i8 (trunc GR16:$src)),
3244 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src), x86_subreg_8bit))>,
3245 Requires<[In32BitMode]>;
3247 // (shl x, 1) ==> (add x, x)
3248 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
3249 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
3250 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
3252 // (shl x (and y, 31)) ==> (shl x, y)
3253 def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
3254 (SHL8rCL GR8:$src1)>;
3255 def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
3256 (SHL16rCL GR16:$src1)>;
3257 def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
3258 (SHL32rCL GR32:$src1)>;
3259 def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3260 (SHL8mCL addr:$dst)>;
3261 def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3262 (SHL16mCL addr:$dst)>;
3263 def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3264 (SHL32mCL addr:$dst)>;
3266 def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
3267 (SHR8rCL GR8:$src1)>;
3268 def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
3269 (SHR16rCL GR16:$src1)>;
3270 def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
3271 (SHR32rCL GR32:$src1)>;
3272 def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3273 (SHR8mCL addr:$dst)>;
3274 def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3275 (SHR16mCL addr:$dst)>;
3276 def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3277 (SHR32mCL addr:$dst)>;
3279 def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
3280 (SAR8rCL GR8:$src1)>;
3281 def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
3282 (SAR16rCL GR16:$src1)>;
3283 def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
3284 (SAR32rCL GR32:$src1)>;
3285 def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3286 (SAR8mCL addr:$dst)>;
3287 def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3288 (SAR16mCL addr:$dst)>;
3289 def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3290 (SAR32mCL addr:$dst)>;
3292 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
3293 def : Pat<(or (srl GR32:$src1, CL:$amt),
3294 (shl GR32:$src2, (sub 32, CL:$amt))),
3295 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3297 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
3298 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3299 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3301 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
3302 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3303 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3305 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3306 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3308 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3310 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3311 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3313 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
3314 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3315 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3317 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
3318 def : Pat<(or (shl GR32:$src1, CL:$amt),
3319 (srl GR32:$src2, (sub 32, CL:$amt))),
3320 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3322 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
3323 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3324 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3326 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
3327 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3328 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3330 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3331 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3333 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3335 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3336 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3338 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
3339 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3340 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3342 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
3343 def : Pat<(or (srl GR16:$src1, CL:$amt),
3344 (shl GR16:$src2, (sub 16, CL:$amt))),
3345 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3347 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
3348 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3349 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3351 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
3352 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3353 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3355 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3356 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3358 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3360 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3361 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3363 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
3364 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3365 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3367 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
3368 def : Pat<(or (shl GR16:$src1, CL:$amt),
3369 (srl GR16:$src2, (sub 16, CL:$amt))),
3370 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3372 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
3373 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3374 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3376 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
3377 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3378 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3380 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3381 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3383 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3385 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3386 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3388 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
3389 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3390 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3392 //===----------------------------------------------------------------------===//
3393 // Overflow Patterns
3394 //===----------------------------------------------------------------------===//
3396 // Register-Register Addition with Overflow
3397 def : Pat<(parallel (X86add_ovf GR8:$src1, GR8:$src2),
3399 (ADD8rr GR8:$src1, GR8:$src2)>;
3401 // Register-Register Addition with Overflow
3402 def : Pat<(parallel (X86add_ovf GR16:$src1, GR16:$src2),
3404 (ADD16rr GR16:$src1, GR16:$src2)>;
3405 def : Pat<(parallel (X86add_ovf GR32:$src1, GR32:$src2),
3407 (ADD32rr GR32:$src1, GR32:$src2)>;
3409 // Register-Memory Addition with Overflow
3410 def : Pat<(parallel (X86add_ovf GR8:$src1, (load addr:$src2)),
3412 (ADD8rm GR8:$src1, addr:$src2)>;
3413 def : Pat<(parallel (X86add_ovf GR16:$src1, (load addr:$src2)),
3415 (ADD16rm GR16:$src1, addr:$src2)>;
3416 def : Pat<(parallel (X86add_ovf GR32:$src1, (load addr:$src2)),
3418 (ADD32rm GR32:$src1, addr:$src2)>;
3420 // Register-Integer Addition with Overflow
3421 def : Pat<(parallel (X86add_ovf GR8:$src1, imm:$src2),
3423 (ADD8ri GR8:$src1, imm:$src2)>;
3425 // Register-Integer Addition with Overflow
3426 def : Pat<(parallel (X86add_ovf GR16:$src1, imm:$src2),
3428 (ADD16ri GR16:$src1, imm:$src2)>;
3429 def : Pat<(parallel (X86add_ovf GR32:$src1, imm:$src2),
3431 (ADD32ri GR32:$src1, imm:$src2)>;
3432 def : Pat<(parallel (X86add_ovf GR16:$src1, i16immSExt8:$src2),
3434 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
3435 def : Pat<(parallel (X86add_ovf GR32:$src1, i32immSExt8:$src2),
3437 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3439 // Memory-Register Addition with Overflow
3440 def : Pat<(parallel (store (X86add_ovf (load addr:$dst), GR8:$src2),
3443 (ADD8mr addr:$dst, GR8:$src2)>;
3444 def : Pat<(parallel (store (X86add_ovf (load addr:$dst), GR16:$src2),
3447 (ADD16mr addr:$dst, GR16:$src2)>;
3448 def : Pat<(parallel (store (X86add_ovf (load addr:$dst), GR32:$src2),
3451 (ADD32mr addr:$dst, GR32:$src2)>;
3452 def : Pat<(parallel (store (X86add_ovf (loadi8 addr:$dst), imm:$src2),
3455 (ADD8mi addr:$dst, imm:$src2)>;
3456 def : Pat<(parallel (store (X86add_ovf (loadi16 addr:$dst), imm:$src2),
3459 (ADD16mi addr:$dst, imm:$src2)>;
3460 def : Pat<(parallel (store (X86add_ovf (loadi32 addr:$dst), imm:$src2),
3463 (ADD32mi addr:$dst, imm:$src2)>;
3464 def : Pat<(parallel (store (X86add_ovf (load addr:$dst), i16immSExt8:$src2),
3467 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
3468 def : Pat<(parallel (store (X86add_ovf (load addr:$dst), i32immSExt8:$src2),
3471 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
3473 // Register-Register Subtraction with Overflow
3474 def : Pat<(parallel (X86sub_ovf GR8:$src1, GR8:$src2),
3476 (SUB8rr GR8:$src1, GR8:$src2)>;
3477 def : Pat<(parallel (X86sub_ovf GR16:$src1, GR16:$src2),
3479 (SUB16rr GR16:$src1, GR16:$src2)>;
3480 def : Pat<(parallel (X86sub_ovf GR32:$src1, GR32:$src2),
3482 (SUB32rr GR32:$src1, GR32:$src2)>;
3484 // Register-Memory Subtraction with Overflow
3485 def : Pat<(parallel (X86sub_ovf GR8:$src1, (load addr:$src2)),
3487 (SUB8rm GR8:$src1, addr:$src2)>;
3488 def : Pat<(parallel (X86sub_ovf GR16:$src1, (load addr:$src2)),
3490 (SUB16rm GR16:$src1, addr:$src2)>;
3491 def : Pat<(parallel (X86sub_ovf GR32:$src1, (load addr:$src2)),
3493 (SUB32rm GR32:$src1, addr:$src2)>;
3495 // Register-Integer Subtraction with Overflow
3496 def : Pat<(parallel (X86sub_ovf GR8:$src1, imm:$src2),
3498 (SUB8ri GR8:$src1, imm:$src2)>;
3499 def : Pat<(parallel (X86sub_ovf GR16:$src1, imm:$src2),
3501 (SUB16ri GR16:$src1, imm:$src2)>;
3502 def : Pat<(parallel (X86sub_ovf GR32:$src1, imm:$src2),
3504 (SUB32ri GR32:$src1, imm:$src2)>;
3505 def : Pat<(parallel (X86sub_ovf GR16:$src1, i16immSExt8:$src2),
3507 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
3508 def : Pat<(parallel (X86sub_ovf GR32:$src1, i32immSExt8:$src2),
3510 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3512 // Memory-Register Subtraction with Overflow
3513 def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), GR8:$src2),
3516 (SUB8mr addr:$dst, GR8:$src2)>;
3517 def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), GR16:$src2),
3520 (SUB16mr addr:$dst, GR16:$src2)>;
3521 def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), GR32:$src2),
3524 (SUB32mr addr:$dst, GR32:$src2)>;
3526 // Memory-Integer Subtraction with Overflow
3527 def : Pat<(parallel (store (X86sub_ovf (loadi8 addr:$dst), imm:$src2),
3530 (SUB8mi addr:$dst, imm:$src2)>;
3531 def : Pat<(parallel (store (X86sub_ovf (loadi16 addr:$dst), imm:$src2),
3534 (SUB16mi addr:$dst, imm:$src2)>;
3535 def : Pat<(parallel (store (X86sub_ovf (loadi32 addr:$dst), imm:$src2),
3538 (SUB32mi addr:$dst, imm:$src2)>;
3539 def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), i16immSExt8:$src2),
3542 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
3543 def : Pat<(parallel (store (X86sub_ovf (load addr:$dst), i32immSExt8:$src2),
3546 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
3549 // Register-Register Signed Integer Multiply with Overflow
3550 def : Pat<(parallel (X86smul_ovf GR16:$src1, GR16:$src2),
3552 (IMUL16rr GR16:$src1, GR16:$src2)>;
3553 def : Pat<(parallel (X86smul_ovf GR32:$src1, GR32:$src2),
3555 (IMUL32rr GR32:$src1, GR32:$src2)>;
3557 // Register-Memory Signed Integer Multiply with Overflow
3558 def : Pat<(parallel (X86smul_ovf GR16:$src1, (load addr:$src2)),
3560 (IMUL16rm GR16:$src1, addr:$src2)>;
3561 def : Pat<(parallel (X86smul_ovf GR32:$src1, (load addr:$src2)),
3563 (IMUL32rm GR32:$src1, addr:$src2)>;
3565 // Register-Integer Signed Integer Multiply with Overflow
3566 def : Pat<(parallel (X86smul_ovf GR16:$src1, imm:$src2),
3568 (IMUL16rri GR16:$src1, imm:$src2)>;
3569 def : Pat<(parallel (X86smul_ovf GR32:$src1, imm:$src2),
3571 (IMUL32rri GR32:$src1, imm:$src2)>;
3572 def : Pat<(parallel (X86smul_ovf GR16:$src1, i16immSExt8:$src2),
3574 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
3575 def : Pat<(parallel (X86smul_ovf GR32:$src1, i32immSExt8:$src2),
3577 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
3579 // Memory-Integer Signed Integer Multiply with Overflow
3580 def : Pat<(parallel (X86smul_ovf (load addr:$src1), imm:$src2),
3582 (IMUL16rmi addr:$src1, imm:$src2)>;
3583 def : Pat<(parallel (X86smul_ovf (load addr:$src1), imm:$src2),
3585 (IMUL32rmi addr:$src1, imm:$src2)>;
3586 def : Pat<(parallel (X86smul_ovf (load addr:$src1), i16immSExt8:$src2),
3588 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
3589 def : Pat<(parallel (X86smul_ovf (load addr:$src1), i32immSExt8:$src2),
3591 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
3593 //===----------------------------------------------------------------------===//
3594 // Floating Point Stack Support
3595 //===----------------------------------------------------------------------===//
3597 include "X86InstrFPStack.td"
3599 //===----------------------------------------------------------------------===//
3601 //===----------------------------------------------------------------------===//
3603 include "X86Instr64bit.td"
3605 //===----------------------------------------------------------------------===//
3606 // XMM Floating point support (requires SSE / SSE2)
3607 //===----------------------------------------------------------------------===//
3609 include "X86InstrSSE.td"
3611 //===----------------------------------------------------------------------===//
3612 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
3613 //===----------------------------------------------------------------------===//
3615 include "X86InstrMMX.td"