1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
33 def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
37 def SDTX86BrCond : SDTypeProfile<0, 3,
38 [SDTCisVT<0, OtherVT>,
39 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
41 def SDTX86SetCC : SDTypeProfile<1, 2,
43 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
47 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
49 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
50 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
51 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
53 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
54 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
57 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
59 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
61 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
63 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
65 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
67 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
69 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
71 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
73 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
74 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
75 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
76 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
78 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
80 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
82 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
83 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
85 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
87 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
88 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
90 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
91 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
93 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
94 [SDNPHasChain, SDNPMayStore,
95 SDNPMayLoad, SDNPMemOperand]>;
96 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
97 [SDNPHasChain, SDNPMayStore,
98 SDNPMayLoad, SDNPMemOperand]>;
99 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
100 [SDNPHasChain, SDNPMayStore,
101 SDNPMayLoad, SDNPMemOperand]>;
102 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
103 [SDNPHasChain, SDNPMayStore,
104 SDNPMayLoad, SDNPMemOperand]>;
105 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
106 [SDNPHasChain, SDNPMayStore,
107 SDNPMayLoad, SDNPMemOperand]>;
108 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
109 [SDNPHasChain, SDNPMayStore,
110 SDNPMayLoad, SDNPMemOperand]>;
111 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
112 [SDNPHasChain, SDNPMayStore,
113 SDNPMayLoad, SDNPMemOperand]>;
114 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
115 [SDNPHasChain, SDNPOptInFlag]>;
117 def X86callseq_start :
118 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
119 [SDNPHasChain, SDNPOutFlag]>;
121 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
122 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
124 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
125 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
127 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
128 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
129 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
130 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
133 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
134 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
136 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
137 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
139 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
140 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
141 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
142 SDT_X86SegmentBaseAddress, []>;
144 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
147 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
148 [SDNPHasChain, SDNPOptInFlag]>;
150 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags>;
151 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
152 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags>;
153 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>;
154 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
155 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
157 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
159 //===----------------------------------------------------------------------===//
160 // X86 Operand Definitions.
163 def i32imm_pcrel : Operand<i32> {
164 let PrintMethod = "print_pcrel_imm";
167 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
168 // the index operand of an address, to conform to x86 encoding restrictions.
169 def ptr_rc_nosp : PointerLikeRegClass<1>;
171 // *mem - Operand definitions for the funky X86 addressing mode operands.
173 class X86MemOperand<string printMethod> : Operand<iPTR> {
174 let PrintMethod = printMethod;
175 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
176 let ParserMatchClass = "Mem";
179 def i8mem : X86MemOperand<"printi8mem">;
180 def i16mem : X86MemOperand<"printi16mem">;
181 def i32mem : X86MemOperand<"printi32mem">;
182 def i64mem : X86MemOperand<"printi64mem">;
183 def i128mem : X86MemOperand<"printi128mem">;
184 def i256mem : X86MemOperand<"printi256mem">;
185 def f32mem : X86MemOperand<"printf32mem">;
186 def f64mem : X86MemOperand<"printf64mem">;
187 def f80mem : X86MemOperand<"printf80mem">;
188 def f128mem : X86MemOperand<"printf128mem">;
189 def f256mem : X86MemOperand<"printf256mem">;
191 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
192 // plain GR64, so that it doesn't potentially require a REX prefix.
193 def i8mem_NOREX : Operand<i64> {
194 let PrintMethod = "printi8mem";
195 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
196 let ParserMatchClass = "Mem";
199 def lea32mem : Operand<i32> {
200 let PrintMethod = "printlea32mem";
201 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
202 let ParserMatchClass = "Mem";
205 def SSECC : Operand<i8> {
206 let PrintMethod = "printSSECC";
209 def piclabel: Operand<i32> {
210 let PrintMethod = "printPICLabel";
213 // A couple of more descriptive operand definitions.
214 // 16-bits but only 8 bits are significant.
215 def i16i8imm : Operand<i16> {
216 let ParserMatchClass = "ImmSExt8";
217 let ParserMatchSuperClass = "Imm";
219 // 32-bits but only 8 bits are significant.
220 def i32i8imm : Operand<i32> {
221 let ParserMatchClass = "ImmSExt8";
222 let ParserMatchSuperClass = "Imm";
225 // Branch targets have OtherVT type and print as pc-relative values.
226 def brtarget : Operand<OtherVT> {
227 let PrintMethod = "print_pcrel_imm";
230 def brtarget8 : Operand<OtherVT> {
231 let PrintMethod = "print_pcrel_imm";
234 //===----------------------------------------------------------------------===//
235 // X86 Complex Pattern Definitions.
238 // Define X86 specific addressing mode.
239 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
240 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
241 [add, sub, mul, X86mul_imm, shl, or, frameindex],
243 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
244 [tglobaltlsaddr], []>;
246 //===----------------------------------------------------------------------===//
247 // X86 Instruction Predicate Definitions.
248 def HasMMX : Predicate<"Subtarget->hasMMX()">;
249 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
250 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
251 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
252 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
253 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
254 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
255 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
256 def HasAVX : Predicate<"Subtarget->hasAVX()">;
257 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
258 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
259 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
260 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
261 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
262 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
263 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
264 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
265 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
266 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
267 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
268 "TM.getCodeModel() != CodeModel::Kernel">;
269 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
270 "TM.getCodeModel() == CodeModel::Kernel">;
271 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
272 def OptForSpeed : Predicate<"!OptForSize">;
273 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
274 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
276 //===----------------------------------------------------------------------===//
277 // X86 Instruction Format Definitions.
280 include "X86InstrFormats.td"
282 //===----------------------------------------------------------------------===//
283 // Pattern fragments...
286 // X86 specific condition code. These correspond to CondCode in
287 // X86InstrInfo.h. They must be kept in synch.
288 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
289 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
290 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
291 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
292 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
293 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
294 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
295 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
296 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
297 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
298 def X86_COND_NO : PatLeaf<(i8 10)>;
299 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
300 def X86_COND_NS : PatLeaf<(i8 12)>;
301 def X86_COND_O : PatLeaf<(i8 13)>;
302 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
303 def X86_COND_S : PatLeaf<(i8 15)>;
305 def i16immSExt8 : PatLeaf<(i16 imm), [{
306 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
307 // sign extended field.
308 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
311 def i32immSExt8 : PatLeaf<(i32 imm), [{
312 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
313 // sign extended field.
314 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
317 // Helper fragments for loads.
318 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
319 // known to be 32-bit aligned or better. Ditto for i8 to i16.
320 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
321 LoadSDNode *LD = cast<LoadSDNode>(N);
322 if (const Value *Src = LD->getSrcValue())
323 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
324 if (PT->getAddressSpace() > 255)
326 ISD::LoadExtType ExtType = LD->getExtensionType();
327 if (ExtType == ISD::NON_EXTLOAD)
329 if (ExtType == ISD::EXTLOAD)
330 return LD->getAlignment() >= 2 && !LD->isVolatile();
334 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
335 LoadSDNode *LD = cast<LoadSDNode>(N);
336 if (const Value *Src = LD->getSrcValue())
337 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
338 if (PT->getAddressSpace() > 255)
340 ISD::LoadExtType ExtType = LD->getExtensionType();
341 if (ExtType == ISD::EXTLOAD)
342 return LD->getAlignment() >= 2 && !LD->isVolatile();
346 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
347 LoadSDNode *LD = cast<LoadSDNode>(N);
348 if (const Value *Src = LD->getSrcValue())
349 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
350 if (PT->getAddressSpace() > 255)
352 ISD::LoadExtType ExtType = LD->getExtensionType();
353 if (ExtType == ISD::NON_EXTLOAD)
355 if (ExtType == ISD::EXTLOAD)
356 return LD->getAlignment() >= 4 && !LD->isVolatile();
360 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
361 LoadSDNode *LD = cast<LoadSDNode>(N);
362 if (const Value *Src = LD->getSrcValue())
363 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
364 if (PT->getAddressSpace() > 255)
366 if (LD->isVolatile())
368 ISD::LoadExtType ExtType = LD->getExtensionType();
369 if (ExtType == ISD::NON_EXTLOAD)
371 if (ExtType == ISD::EXTLOAD)
372 return LD->getAlignment() >= 4;
376 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
377 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
378 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
379 return PT->getAddressSpace() == 256;
383 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
384 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
385 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
386 return PT->getAddressSpace() == 257;
390 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{
391 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
392 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
393 if (PT->getAddressSpace() > 255)
397 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{
398 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
399 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
400 if (PT->getAddressSpace() > 255)
405 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{
406 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
407 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
408 if (PT->getAddressSpace() > 255)
412 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{
413 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
414 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
415 if (PT->getAddressSpace() > 255)
419 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{
420 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
421 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
422 if (PT->getAddressSpace() > 255)
427 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
428 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
429 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
431 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
432 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
433 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
434 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
435 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
436 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
438 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
439 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
440 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
441 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
442 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
443 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
446 // An 'and' node with a single use.
447 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
448 return N->hasOneUse();
450 // An 'srl' node with a single use.
451 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
452 return N->hasOneUse();
454 // An 'trunc' node with a single use.
455 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
456 return N->hasOneUse();
459 // 'shld' and 'shrd' instruction patterns. Note that even though these have
460 // the srl and shl in their patterns, the C++ code must still check for them,
461 // because predicates are tested before children nodes are explored.
463 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
464 (or (srl node:$src1, node:$amt1),
465 (shl node:$src2, node:$amt2)), [{
466 assert(N->getOpcode() == ISD::OR);
467 return N->getOperand(0).getOpcode() == ISD::SRL &&
468 N->getOperand(1).getOpcode() == ISD::SHL &&
469 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
470 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
471 N->getOperand(0).getConstantOperandVal(1) ==
472 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
475 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
476 (or (shl node:$src1, node:$amt1),
477 (srl node:$src2, node:$amt2)), [{
478 assert(N->getOpcode() == ISD::OR);
479 return N->getOperand(0).getOpcode() == ISD::SHL &&
480 N->getOperand(1).getOpcode() == ISD::SRL &&
481 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
482 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
483 N->getOperand(0).getConstantOperandVal(1) ==
484 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
487 //===----------------------------------------------------------------------===//
488 // Instruction list...
491 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
492 // a stack adjustment and the codegen must know that they may modify the stack
493 // pointer before prolog-epilog rewriting occurs.
494 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
495 // sub / add which can clobber EFLAGS.
496 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
497 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
499 [(X86callseq_start timm:$amt)]>,
500 Requires<[In32BitMode]>;
501 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
503 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
504 Requires<[In32BitMode]>;
508 let neverHasSideEffects = 1 in {
509 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
510 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
511 "nopl\t$zero", []>, TB;
515 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
516 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
520 //===----------------------------------------------------------------------===//
521 // Control Flow Instructions...
524 // Return instructions.
525 let isTerminator = 1, isReturn = 1, isBarrier = 1,
526 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
527 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
530 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
532 [(X86retflag imm:$amt)]>;
535 // All branches are RawFrm, Void, Branch, and Terminators
536 let isBranch = 1, isTerminator = 1 in
537 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
538 I<opcode, RawFrm, (outs), ins, asm, pattern>;
540 let isBranch = 1, isBarrier = 1 in {
541 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
542 def JMP8 : IBr<0xEB, (ins brtarget8:$dst), "jmp\t$dst", []>;
546 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
547 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
548 [(brind GR32:$dst)]>;
549 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
550 [(brind (loadi32 addr:$dst))]>;
553 // Conditional branches
554 let Uses = [EFLAGS] in {
555 // Short conditional jumps
556 def JO8 : IBr<0x70, (ins brtarget8:$dst), "jo\t$dst", []>;
557 def JNO8 : IBr<0x71, (ins brtarget8:$dst), "jno\t$dst", []>;
558 def JB8 : IBr<0x72, (ins brtarget8:$dst), "jb\t$dst", []>;
559 def JAE8 : IBr<0x73, (ins brtarget8:$dst), "jae\t$dst", []>;
560 def JE8 : IBr<0x74, (ins brtarget8:$dst), "je\t$dst", []>;
561 def JNE8 : IBr<0x75, (ins brtarget8:$dst), "jne\t$dst", []>;
562 def JBE8 : IBr<0x76, (ins brtarget8:$dst), "jbe\t$dst", []>;
563 def JA8 : IBr<0x77, (ins brtarget8:$dst), "ja\t$dst", []>;
564 def JS8 : IBr<0x78, (ins brtarget8:$dst), "js\t$dst", []>;
565 def JNS8 : IBr<0x79, (ins brtarget8:$dst), "jns\t$dst", []>;
566 def JP8 : IBr<0x7A, (ins brtarget8:$dst), "jp\t$dst", []>;
567 def JNP8 : IBr<0x7B, (ins brtarget8:$dst), "jnp\t$dst", []>;
568 def JL8 : IBr<0x7C, (ins brtarget8:$dst), "jl\t$dst", []>;
569 def JGE8 : IBr<0x7D, (ins brtarget8:$dst), "jge\t$dst", []>;
570 def JLE8 : IBr<0x7E, (ins brtarget8:$dst), "jle\t$dst", []>;
571 def JG8 : IBr<0x7F, (ins brtarget8:$dst), "jg\t$dst", []>;
573 def JCXZ8 : IBr<0xE3, (ins brtarget8:$dst), "jcxz\t$dst", []>;
575 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
576 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
577 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
578 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
579 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
580 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
581 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
582 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
583 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
584 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
585 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
586 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
588 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
589 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
590 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
591 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
592 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
593 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
594 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
595 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
597 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
598 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
599 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
600 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
601 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
602 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
603 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
604 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
605 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
606 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
607 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
608 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
611 //===----------------------------------------------------------------------===//
612 // Call Instructions...
615 // All calls clobber the non-callee saved registers. ESP is marked as
616 // a use to prevent stack-pointer assignments that appear immediately
617 // before calls from potentially appearing dead. Uses for argument
618 // registers are added manually.
619 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
620 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
621 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
622 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
624 def CALLpcrel32 : Ii32<0xE8, RawFrm,
625 (outs), (ins i32imm_pcrel:$dst,variable_ops),
627 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
628 "call\t{*}$dst", [(X86call GR32:$dst)]>;
629 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
630 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
635 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
636 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops),
637 "#TC_RETURN $dst $offset",
640 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
641 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops),
642 "#TC_RETURN $dst $offset",
645 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
647 def TAILJMPd : IBr<0xE9, (ins i32imm_pcrel:$dst), "jmp\t$dst # TAILCALL",
649 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
650 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
652 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
653 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
654 "jmp\t{*}$dst # TAILCALL", []>;
656 //===----------------------------------------------------------------------===//
657 // Miscellaneous Instructions...
659 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
660 def LEAVE : I<0xC9, RawFrm,
661 (outs), (ins), "leave", []>;
663 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
665 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
668 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
671 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
672 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
673 "push{l}\t$imm", []>;
674 def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
675 "push{l}\t$imm", []>;
676 def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
677 "push{l}\t$imm", []>;
680 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
681 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
682 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
683 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
685 let isTwoAddress = 1 in // GR32 = bswap GR32
686 def BSWAP32r : I<0xC8, AddRegFrm,
687 (outs GR32:$dst), (ins GR32:$src),
689 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
692 // Bit scan instructions.
693 let Defs = [EFLAGS] in {
694 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
695 "bsf{w}\t{$src, $dst|$dst, $src}",
696 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
697 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
698 "bsf{w}\t{$src, $dst|$dst, $src}",
699 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
700 (implicit EFLAGS)]>, TB;
701 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
702 "bsf{l}\t{$src, $dst|$dst, $src}",
703 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
704 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
705 "bsf{l}\t{$src, $dst|$dst, $src}",
706 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
707 (implicit EFLAGS)]>, TB;
709 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
710 "bsr{w}\t{$src, $dst|$dst, $src}",
711 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
712 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
713 "bsr{w}\t{$src, $dst|$dst, $src}",
714 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
715 (implicit EFLAGS)]>, TB;
716 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
717 "bsr{l}\t{$src, $dst|$dst, $src}",
718 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
719 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
720 "bsr{l}\t{$src, $dst|$dst, $src}",
721 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
722 (implicit EFLAGS)]>, TB;
725 let neverHasSideEffects = 1 in
726 def LEA16r : I<0x8D, MRMSrcMem,
727 (outs GR16:$dst), (ins i32mem:$src),
728 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
729 let isReMaterializable = 1 in
730 def LEA32r : I<0x8D, MRMSrcMem,
731 (outs GR32:$dst), (ins lea32mem:$src),
732 "lea{l}\t{$src|$dst}, {$dst|$src}",
733 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
735 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
736 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
737 [(X86rep_movs i8)]>, REP;
738 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
739 [(X86rep_movs i16)]>, REP, OpSize;
740 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
741 [(X86rep_movs i32)]>, REP;
744 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
745 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
746 [(X86rep_stos i8)]>, REP;
747 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
748 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
749 [(X86rep_stos i16)]>, REP, OpSize;
750 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
751 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
752 [(X86rep_stos i32)]>, REP;
754 let Defs = [RAX, RDX] in
755 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
758 let isBarrier = 1, hasCtrlDep = 1 in {
759 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
762 //===----------------------------------------------------------------------===//
763 // Input/Output Instructions...
765 let Defs = [AL], Uses = [DX] in
766 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
767 "in{b}\t{%dx, %al|%AL, %DX}", []>;
768 let Defs = [AX], Uses = [DX] in
769 def IN16rr : I<0xED, RawFrm, (outs), (ins),
770 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
771 let Defs = [EAX], Uses = [DX] in
772 def IN32rr : I<0xED, RawFrm, (outs), (ins),
773 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
776 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
777 "in{b}\t{$port, %al|%AL, $port}", []>;
779 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
780 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
782 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
783 "in{l}\t{$port, %eax|%EAX, $port}", []>;
785 let Uses = [DX, AL] in
786 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
787 "out{b}\t{%al, %dx|%DX, %AL}", []>;
788 let Uses = [DX, AX] in
789 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
790 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
791 let Uses = [DX, EAX] in
792 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
793 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
796 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
797 "out{b}\t{%al, $port|$port, %AL}", []>;
799 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
800 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
802 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
803 "out{l}\t{%eax, $port|$port, %EAX}", []>;
805 //===----------------------------------------------------------------------===//
806 // Move Instructions...
808 let neverHasSideEffects = 1 in {
809 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
810 "mov{b}\t{$src, $dst|$dst, $src}", []>;
811 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
812 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
813 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
814 "mov{l}\t{$src, $dst|$dst, $src}", []>;
816 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
817 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
818 "mov{b}\t{$src, $dst|$dst, $src}",
819 [(set GR8:$dst, imm:$src)]>;
820 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
821 "mov{w}\t{$src, $dst|$dst, $src}",
822 [(set GR16:$dst, imm:$src)]>, OpSize;
823 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
824 "mov{l}\t{$src, $dst|$dst, $src}",
825 [(set GR32:$dst, imm:$src)]>;
827 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
828 "mov{b}\t{$src, $dst|$dst, $src}",
829 [(store (i8 imm:$src), addr:$dst)]>;
830 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
831 "mov{w}\t{$src, $dst|$dst, $src}",
832 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
833 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
834 "mov{l}\t{$src, $dst|$dst, $src}",
835 [(store (i32 imm:$src), addr:$dst)]>;
837 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
838 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
839 "mov{b}\t{$src, $dst|$dst, $src}",
840 [(set GR8:$dst, (loadi8 addr:$src))]>;
841 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
842 "mov{w}\t{$src, $dst|$dst, $src}",
843 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
844 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
845 "mov{l}\t{$src, $dst|$dst, $src}",
846 [(set GR32:$dst, (loadi32 addr:$src))]>;
849 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
850 "mov{b}\t{$src, $dst|$dst, $src}",
851 [(store GR8:$src, addr:$dst)]>;
852 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
853 "mov{w}\t{$src, $dst|$dst, $src}",
854 [(store GR16:$src, addr:$dst)]>, OpSize;
855 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
856 "mov{l}\t{$src, $dst|$dst, $src}",
857 [(store GR32:$src, addr:$dst)]>;
859 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
860 // that they can be used for copying and storing h registers, which can't be
861 // encoded when a REX prefix is present.
862 let neverHasSideEffects = 1 in
863 def MOV8rr_NOREX : I<0x88, MRMDestReg,
864 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
865 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
867 def MOV8mr_NOREX : I<0x88, MRMDestMem,
868 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
869 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
871 canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
872 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
873 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
874 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
876 //===----------------------------------------------------------------------===//
877 // Fixed-Register Multiplication and Division Instructions...
880 // Extra precision multiplication
881 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
882 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
883 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
884 // This probably ought to be moved to a def : Pat<> if the
885 // syntax can be accepted.
886 [(set AL, (mul AL, GR8:$src)),
887 (implicit EFLAGS)]>; // AL,AH = AL*GR8
889 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
890 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
892 []>, OpSize; // AX,DX = AX*GR16
894 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
895 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
897 []>; // EAX,EDX = EAX*GR32
899 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
900 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
902 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
903 // This probably ought to be moved to a def : Pat<> if the
904 // syntax can be accepted.
905 [(set AL, (mul AL, (loadi8 addr:$src))),
906 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
908 let mayLoad = 1, neverHasSideEffects = 1 in {
909 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
910 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
912 []>, OpSize; // AX,DX = AX*[mem16]
914 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
915 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
917 []>; // EAX,EDX = EAX*[mem32]
920 let neverHasSideEffects = 1 in {
921 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
922 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
924 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
925 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
926 OpSize; // AX,DX = AX*GR16
927 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
928 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
929 // EAX,EDX = EAX*GR32
931 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
932 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
933 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
934 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
935 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
936 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
937 let Defs = [EAX,EDX], Uses = [EAX] in
938 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
939 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
941 } // neverHasSideEffects
943 // unsigned division/remainder
944 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
945 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
947 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
948 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
949 "div{w}\t$src", []>, OpSize;
950 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
951 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
954 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
955 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
957 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
958 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
959 "div{w}\t$src", []>, OpSize;
960 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
961 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
965 // Signed division/remainder.
966 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
967 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
968 "idiv{b}\t$src", []>;
969 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
970 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
971 "idiv{w}\t$src", []>, OpSize;
972 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
973 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
974 "idiv{l}\t$src", []>;
975 let mayLoad = 1, mayLoad = 1 in {
976 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
977 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
978 "idiv{b}\t$src", []>;
979 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
980 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
981 "idiv{w}\t$src", []>, OpSize;
982 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
983 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
984 "idiv{l}\t$src", []>;
987 //===----------------------------------------------------------------------===//
988 // Two address Instructions.
990 let isTwoAddress = 1 in {
993 let Uses = [EFLAGS] in {
994 let isCommutable = 1 in {
995 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
996 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
997 "cmovb\t{$src2, $dst|$dst, $src2}",
998 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
999 X86_COND_B, EFLAGS))]>,
1001 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1002 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1003 "cmovb\t{$src2, $dst|$dst, $src2}",
1004 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1005 X86_COND_B, EFLAGS))]>,
1007 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1008 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1009 "cmovae\t{$src2, $dst|$dst, $src2}",
1010 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1011 X86_COND_AE, EFLAGS))]>,
1013 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1014 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1015 "cmovae\t{$src2, $dst|$dst, $src2}",
1016 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1017 X86_COND_AE, EFLAGS))]>,
1019 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1020 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1021 "cmove\t{$src2, $dst|$dst, $src2}",
1022 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1023 X86_COND_E, EFLAGS))]>,
1025 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1026 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1027 "cmove\t{$src2, $dst|$dst, $src2}",
1028 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1029 X86_COND_E, EFLAGS))]>,
1031 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1032 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1033 "cmovne\t{$src2, $dst|$dst, $src2}",
1034 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1035 X86_COND_NE, EFLAGS))]>,
1037 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1038 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1039 "cmovne\t{$src2, $dst|$dst, $src2}",
1040 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1041 X86_COND_NE, EFLAGS))]>,
1043 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1044 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1045 "cmovbe\t{$src2, $dst|$dst, $src2}",
1046 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1047 X86_COND_BE, EFLAGS))]>,
1049 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1050 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1051 "cmovbe\t{$src2, $dst|$dst, $src2}",
1052 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1053 X86_COND_BE, EFLAGS))]>,
1055 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1056 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1057 "cmova\t{$src2, $dst|$dst, $src2}",
1058 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1059 X86_COND_A, EFLAGS))]>,
1061 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1062 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1063 "cmova\t{$src2, $dst|$dst, $src2}",
1064 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1065 X86_COND_A, EFLAGS))]>,
1067 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1068 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1069 "cmovl\t{$src2, $dst|$dst, $src2}",
1070 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1071 X86_COND_L, EFLAGS))]>,
1073 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1074 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1075 "cmovl\t{$src2, $dst|$dst, $src2}",
1076 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1077 X86_COND_L, EFLAGS))]>,
1079 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1080 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1081 "cmovge\t{$src2, $dst|$dst, $src2}",
1082 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1083 X86_COND_GE, EFLAGS))]>,
1085 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1086 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1087 "cmovge\t{$src2, $dst|$dst, $src2}",
1088 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1089 X86_COND_GE, EFLAGS))]>,
1091 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1092 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1093 "cmovle\t{$src2, $dst|$dst, $src2}",
1094 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1095 X86_COND_LE, EFLAGS))]>,
1097 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1098 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1099 "cmovle\t{$src2, $dst|$dst, $src2}",
1100 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1101 X86_COND_LE, EFLAGS))]>,
1103 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1104 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1105 "cmovg\t{$src2, $dst|$dst, $src2}",
1106 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1107 X86_COND_G, EFLAGS))]>,
1109 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1110 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1111 "cmovg\t{$src2, $dst|$dst, $src2}",
1112 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1113 X86_COND_G, EFLAGS))]>,
1115 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1116 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1117 "cmovs\t{$src2, $dst|$dst, $src2}",
1118 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1119 X86_COND_S, EFLAGS))]>,
1121 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1122 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1123 "cmovs\t{$src2, $dst|$dst, $src2}",
1124 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1125 X86_COND_S, EFLAGS))]>,
1127 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1128 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1129 "cmovns\t{$src2, $dst|$dst, $src2}",
1130 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1131 X86_COND_NS, EFLAGS))]>,
1133 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1134 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1135 "cmovns\t{$src2, $dst|$dst, $src2}",
1136 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1137 X86_COND_NS, EFLAGS))]>,
1139 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1140 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1141 "cmovp\t{$src2, $dst|$dst, $src2}",
1142 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1143 X86_COND_P, EFLAGS))]>,
1145 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1146 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1147 "cmovp\t{$src2, $dst|$dst, $src2}",
1148 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1149 X86_COND_P, EFLAGS))]>,
1151 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1152 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1153 "cmovnp\t{$src2, $dst|$dst, $src2}",
1154 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1155 X86_COND_NP, EFLAGS))]>,
1157 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1158 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1159 "cmovnp\t{$src2, $dst|$dst, $src2}",
1160 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1161 X86_COND_NP, EFLAGS))]>,
1163 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1164 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1165 "cmovo\t{$src2, $dst|$dst, $src2}",
1166 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1167 X86_COND_O, EFLAGS))]>,
1169 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1170 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1171 "cmovo\t{$src2, $dst|$dst, $src2}",
1172 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1173 X86_COND_O, EFLAGS))]>,
1175 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1176 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1177 "cmovno\t{$src2, $dst|$dst, $src2}",
1178 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1179 X86_COND_NO, EFLAGS))]>,
1181 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1182 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1183 "cmovno\t{$src2, $dst|$dst, $src2}",
1184 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1185 X86_COND_NO, EFLAGS))]>,
1187 } // isCommutable = 1
1189 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1190 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1191 "cmovb\t{$src2, $dst|$dst, $src2}",
1192 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1193 X86_COND_B, EFLAGS))]>,
1195 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1196 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1197 "cmovb\t{$src2, $dst|$dst, $src2}",
1198 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1199 X86_COND_B, EFLAGS))]>,
1201 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1202 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1203 "cmovae\t{$src2, $dst|$dst, $src2}",
1204 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1205 X86_COND_AE, EFLAGS))]>,
1207 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1208 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1209 "cmovae\t{$src2, $dst|$dst, $src2}",
1210 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1211 X86_COND_AE, EFLAGS))]>,
1213 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1214 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1215 "cmove\t{$src2, $dst|$dst, $src2}",
1216 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1217 X86_COND_E, EFLAGS))]>,
1219 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1220 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1221 "cmove\t{$src2, $dst|$dst, $src2}",
1222 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1223 X86_COND_E, EFLAGS))]>,
1225 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1226 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1227 "cmovne\t{$src2, $dst|$dst, $src2}",
1228 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1229 X86_COND_NE, EFLAGS))]>,
1231 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1232 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1233 "cmovne\t{$src2, $dst|$dst, $src2}",
1234 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1235 X86_COND_NE, EFLAGS))]>,
1237 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1238 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1239 "cmovbe\t{$src2, $dst|$dst, $src2}",
1240 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1241 X86_COND_BE, EFLAGS))]>,
1243 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1244 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1245 "cmovbe\t{$src2, $dst|$dst, $src2}",
1246 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1247 X86_COND_BE, EFLAGS))]>,
1249 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1250 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1251 "cmova\t{$src2, $dst|$dst, $src2}",
1252 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1253 X86_COND_A, EFLAGS))]>,
1255 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1256 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1257 "cmova\t{$src2, $dst|$dst, $src2}",
1258 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1259 X86_COND_A, EFLAGS))]>,
1261 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1262 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1263 "cmovl\t{$src2, $dst|$dst, $src2}",
1264 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1265 X86_COND_L, EFLAGS))]>,
1267 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1268 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1269 "cmovl\t{$src2, $dst|$dst, $src2}",
1270 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1271 X86_COND_L, EFLAGS))]>,
1273 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1274 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1275 "cmovge\t{$src2, $dst|$dst, $src2}",
1276 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1277 X86_COND_GE, EFLAGS))]>,
1279 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1280 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1281 "cmovge\t{$src2, $dst|$dst, $src2}",
1282 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1283 X86_COND_GE, EFLAGS))]>,
1285 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1286 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1287 "cmovle\t{$src2, $dst|$dst, $src2}",
1288 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1289 X86_COND_LE, EFLAGS))]>,
1291 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1292 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1293 "cmovle\t{$src2, $dst|$dst, $src2}",
1294 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1295 X86_COND_LE, EFLAGS))]>,
1297 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1298 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1299 "cmovg\t{$src2, $dst|$dst, $src2}",
1300 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1301 X86_COND_G, EFLAGS))]>,
1303 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1304 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1305 "cmovg\t{$src2, $dst|$dst, $src2}",
1306 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1307 X86_COND_G, EFLAGS))]>,
1309 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1310 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1311 "cmovs\t{$src2, $dst|$dst, $src2}",
1312 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1313 X86_COND_S, EFLAGS))]>,
1315 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1316 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1317 "cmovs\t{$src2, $dst|$dst, $src2}",
1318 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1319 X86_COND_S, EFLAGS))]>,
1321 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1322 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1323 "cmovns\t{$src2, $dst|$dst, $src2}",
1324 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1325 X86_COND_NS, EFLAGS))]>,
1327 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1328 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1329 "cmovns\t{$src2, $dst|$dst, $src2}",
1330 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1331 X86_COND_NS, EFLAGS))]>,
1333 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1334 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1335 "cmovp\t{$src2, $dst|$dst, $src2}",
1336 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1337 X86_COND_P, EFLAGS))]>,
1339 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1340 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1341 "cmovp\t{$src2, $dst|$dst, $src2}",
1342 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1343 X86_COND_P, EFLAGS))]>,
1345 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1346 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1347 "cmovnp\t{$src2, $dst|$dst, $src2}",
1348 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1349 X86_COND_NP, EFLAGS))]>,
1351 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1352 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1353 "cmovnp\t{$src2, $dst|$dst, $src2}",
1354 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1355 X86_COND_NP, EFLAGS))]>,
1357 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1358 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1359 "cmovo\t{$src2, $dst|$dst, $src2}",
1360 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1361 X86_COND_O, EFLAGS))]>,
1363 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1364 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1365 "cmovo\t{$src2, $dst|$dst, $src2}",
1366 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1367 X86_COND_O, EFLAGS))]>,
1369 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1370 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1371 "cmovno\t{$src2, $dst|$dst, $src2}",
1372 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1373 X86_COND_NO, EFLAGS))]>,
1375 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1376 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1377 "cmovno\t{$src2, $dst|$dst, $src2}",
1378 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1379 X86_COND_NO, EFLAGS))]>,
1381 } // Uses = [EFLAGS]
1384 // unary instructions
1385 let CodeSize = 2 in {
1386 let Defs = [EFLAGS] in {
1387 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1388 [(set GR8:$dst, (ineg GR8:$src)),
1389 (implicit EFLAGS)]>;
1390 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1391 [(set GR16:$dst, (ineg GR16:$src)),
1392 (implicit EFLAGS)]>, OpSize;
1393 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1394 [(set GR32:$dst, (ineg GR32:$src)),
1395 (implicit EFLAGS)]>;
1396 let isTwoAddress = 0 in {
1397 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1398 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1399 (implicit EFLAGS)]>;
1400 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1401 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1402 (implicit EFLAGS)]>, OpSize;
1403 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1404 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1405 (implicit EFLAGS)]>;
1407 } // Defs = [EFLAGS]
1409 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1410 let AddedComplexity = 15 in {
1411 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1412 [(set GR8:$dst, (not GR8:$src))]>;
1413 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1414 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1415 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1416 [(set GR32:$dst, (not GR32:$src))]>;
1418 let isTwoAddress = 0 in {
1419 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1420 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1421 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1422 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1423 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1424 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1428 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1429 let Defs = [EFLAGS] in {
1431 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1432 [(set GR8:$dst, (add GR8:$src, 1)),
1433 (implicit EFLAGS)]>;
1434 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1435 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1436 [(set GR16:$dst, (add GR16:$src, 1)),
1437 (implicit EFLAGS)]>,
1438 OpSize, Requires<[In32BitMode]>;
1439 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1440 [(set GR32:$dst, (add GR32:$src, 1)),
1441 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1443 let isTwoAddress = 0, CodeSize = 2 in {
1444 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1445 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1446 (implicit EFLAGS)]>;
1447 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1448 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1449 (implicit EFLAGS)]>,
1450 OpSize, Requires<[In32BitMode]>;
1451 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1452 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1453 (implicit EFLAGS)]>,
1454 Requires<[In32BitMode]>;
1458 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1459 [(set GR8:$dst, (add GR8:$src, -1)),
1460 (implicit EFLAGS)]>;
1461 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1462 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1463 [(set GR16:$dst, (add GR16:$src, -1)),
1464 (implicit EFLAGS)]>,
1465 OpSize, Requires<[In32BitMode]>;
1466 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1467 [(set GR32:$dst, (add GR32:$src, -1)),
1468 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1471 let isTwoAddress = 0, CodeSize = 2 in {
1472 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1473 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1474 (implicit EFLAGS)]>;
1475 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1476 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1477 (implicit EFLAGS)]>,
1478 OpSize, Requires<[In32BitMode]>;
1479 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1480 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1481 (implicit EFLAGS)]>,
1482 Requires<[In32BitMode]>;
1484 } // Defs = [EFLAGS]
1486 // Logical operators...
1487 let Defs = [EFLAGS] in {
1488 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1489 def AND8rr : I<0x20, MRMDestReg,
1490 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1491 "and{b}\t{$src2, $dst|$dst, $src2}",
1492 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
1493 (implicit EFLAGS)]>;
1494 def AND16rr : I<0x21, MRMDestReg,
1495 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1496 "and{w}\t{$src2, $dst|$dst, $src2}",
1497 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
1498 (implicit EFLAGS)]>, OpSize;
1499 def AND32rr : I<0x21, MRMDestReg,
1500 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1501 "and{l}\t{$src2, $dst|$dst, $src2}",
1502 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
1503 (implicit EFLAGS)]>;
1506 def AND8rm : I<0x22, MRMSrcMem,
1507 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1508 "and{b}\t{$src2, $dst|$dst, $src2}",
1509 [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
1510 (implicit EFLAGS)]>;
1511 def AND16rm : I<0x23, MRMSrcMem,
1512 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1513 "and{w}\t{$src2, $dst|$dst, $src2}",
1514 [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
1515 (implicit EFLAGS)]>, OpSize;
1516 def AND32rm : I<0x23, MRMSrcMem,
1517 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1518 "and{l}\t{$src2, $dst|$dst, $src2}",
1519 [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
1520 (implicit EFLAGS)]>;
1522 def AND8ri : Ii8<0x80, MRM4r,
1523 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1524 "and{b}\t{$src2, $dst|$dst, $src2}",
1525 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
1526 (implicit EFLAGS)]>;
1527 def AND16ri : Ii16<0x81, MRM4r,
1528 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1529 "and{w}\t{$src2, $dst|$dst, $src2}",
1530 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
1531 (implicit EFLAGS)]>, OpSize;
1532 def AND32ri : Ii32<0x81, MRM4r,
1533 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1534 "and{l}\t{$src2, $dst|$dst, $src2}",
1535 [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
1536 (implicit EFLAGS)]>;
1537 def AND16ri8 : Ii8<0x83, MRM4r,
1538 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1539 "and{w}\t{$src2, $dst|$dst, $src2}",
1540 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
1541 (implicit EFLAGS)]>,
1543 def AND32ri8 : Ii8<0x83, MRM4r,
1544 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1545 "and{l}\t{$src2, $dst|$dst, $src2}",
1546 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
1547 (implicit EFLAGS)]>;
1549 let isTwoAddress = 0 in {
1550 def AND8mr : I<0x20, MRMDestMem,
1551 (outs), (ins i8mem :$dst, GR8 :$src),
1552 "and{b}\t{$src, $dst|$dst, $src}",
1553 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1554 (implicit EFLAGS)]>;
1555 def AND16mr : I<0x21, MRMDestMem,
1556 (outs), (ins i16mem:$dst, GR16:$src),
1557 "and{w}\t{$src, $dst|$dst, $src}",
1558 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1559 (implicit EFLAGS)]>,
1561 def AND32mr : I<0x21, MRMDestMem,
1562 (outs), (ins i32mem:$dst, GR32:$src),
1563 "and{l}\t{$src, $dst|$dst, $src}",
1564 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1565 (implicit EFLAGS)]>;
1566 def AND8mi : Ii8<0x80, MRM4m,
1567 (outs), (ins i8mem :$dst, i8imm :$src),
1568 "and{b}\t{$src, $dst|$dst, $src}",
1569 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1570 (implicit EFLAGS)]>;
1571 def AND16mi : Ii16<0x81, MRM4m,
1572 (outs), (ins i16mem:$dst, i16imm:$src),
1573 "and{w}\t{$src, $dst|$dst, $src}",
1574 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1575 (implicit EFLAGS)]>,
1577 def AND32mi : Ii32<0x81, MRM4m,
1578 (outs), (ins i32mem:$dst, i32imm:$src),
1579 "and{l}\t{$src, $dst|$dst, $src}",
1580 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1581 (implicit EFLAGS)]>;
1582 def AND16mi8 : Ii8<0x83, MRM4m,
1583 (outs), (ins i16mem:$dst, i16i8imm :$src),
1584 "and{w}\t{$src, $dst|$dst, $src}",
1585 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1586 (implicit EFLAGS)]>,
1588 def AND32mi8 : Ii8<0x83, MRM4m,
1589 (outs), (ins i32mem:$dst, i32i8imm :$src),
1590 "and{l}\t{$src, $dst|$dst, $src}",
1591 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1592 (implicit EFLAGS)]>;
1596 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1597 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1598 "or{b}\t{$src2, $dst|$dst, $src2}",
1599 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
1600 (implicit EFLAGS)]>;
1601 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1602 "or{w}\t{$src2, $dst|$dst, $src2}",
1603 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
1604 (implicit EFLAGS)]>, OpSize;
1605 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1606 "or{l}\t{$src2, $dst|$dst, $src2}",
1607 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
1608 (implicit EFLAGS)]>;
1610 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1611 "or{b}\t{$src2, $dst|$dst, $src2}",
1612 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
1613 (implicit EFLAGS)]>;
1614 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1615 "or{w}\t{$src2, $dst|$dst, $src2}",
1616 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
1617 (implicit EFLAGS)]>, OpSize;
1618 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1619 "or{l}\t{$src2, $dst|$dst, $src2}",
1620 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
1621 (implicit EFLAGS)]>;
1623 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1624 "or{b}\t{$src2, $dst|$dst, $src2}",
1625 [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
1626 (implicit EFLAGS)]>;
1627 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1628 "or{w}\t{$src2, $dst|$dst, $src2}",
1629 [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
1630 (implicit EFLAGS)]>, OpSize;
1631 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1632 "or{l}\t{$src2, $dst|$dst, $src2}",
1633 [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
1634 (implicit EFLAGS)]>;
1636 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1637 "or{w}\t{$src2, $dst|$dst, $src2}",
1638 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
1639 (implicit EFLAGS)]>, OpSize;
1640 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1641 "or{l}\t{$src2, $dst|$dst, $src2}",
1642 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
1643 (implicit EFLAGS)]>;
1644 let isTwoAddress = 0 in {
1645 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1646 "or{b}\t{$src, $dst|$dst, $src}",
1647 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1648 (implicit EFLAGS)]>;
1649 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1650 "or{w}\t{$src, $dst|$dst, $src}",
1651 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1652 (implicit EFLAGS)]>, OpSize;
1653 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1654 "or{l}\t{$src, $dst|$dst, $src}",
1655 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1656 (implicit EFLAGS)]>;
1657 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1658 "or{b}\t{$src, $dst|$dst, $src}",
1659 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1660 (implicit EFLAGS)]>;
1661 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1662 "or{w}\t{$src, $dst|$dst, $src}",
1663 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1664 (implicit EFLAGS)]>,
1666 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1667 "or{l}\t{$src, $dst|$dst, $src}",
1668 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1669 (implicit EFLAGS)]>;
1670 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1671 "or{w}\t{$src, $dst|$dst, $src}",
1672 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1673 (implicit EFLAGS)]>,
1675 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1676 "or{l}\t{$src, $dst|$dst, $src}",
1677 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1678 (implicit EFLAGS)]>;
1679 } // isTwoAddress = 0
1682 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1683 def XOR8rr : I<0x30, MRMDestReg,
1684 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1685 "xor{b}\t{$src2, $dst|$dst, $src2}",
1686 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
1687 (implicit EFLAGS)]>;
1688 def XOR16rr : I<0x31, MRMDestReg,
1689 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1690 "xor{w}\t{$src2, $dst|$dst, $src2}",
1691 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
1692 (implicit EFLAGS)]>, OpSize;
1693 def XOR32rr : I<0x31, MRMDestReg,
1694 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1695 "xor{l}\t{$src2, $dst|$dst, $src2}",
1696 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
1697 (implicit EFLAGS)]>;
1698 } // isCommutable = 1
1700 def XOR8rm : I<0x32, MRMSrcMem ,
1701 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1702 "xor{b}\t{$src2, $dst|$dst, $src2}",
1703 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
1704 (implicit EFLAGS)]>;
1705 def XOR16rm : I<0x33, MRMSrcMem ,
1706 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1707 "xor{w}\t{$src2, $dst|$dst, $src2}",
1708 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
1709 (implicit EFLAGS)]>,
1711 def XOR32rm : I<0x33, MRMSrcMem ,
1712 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1713 "xor{l}\t{$src2, $dst|$dst, $src2}",
1714 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
1715 (implicit EFLAGS)]>;
1717 def XOR8ri : Ii8<0x80, MRM6r,
1718 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1719 "xor{b}\t{$src2, $dst|$dst, $src2}",
1720 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
1721 (implicit EFLAGS)]>;
1722 def XOR16ri : Ii16<0x81, MRM6r,
1723 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1724 "xor{w}\t{$src2, $dst|$dst, $src2}",
1725 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
1726 (implicit EFLAGS)]>, OpSize;
1727 def XOR32ri : Ii32<0x81, MRM6r,
1728 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1729 "xor{l}\t{$src2, $dst|$dst, $src2}",
1730 [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
1731 (implicit EFLAGS)]>;
1732 def XOR16ri8 : Ii8<0x83, MRM6r,
1733 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1734 "xor{w}\t{$src2, $dst|$dst, $src2}",
1735 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
1736 (implicit EFLAGS)]>,
1738 def XOR32ri8 : Ii8<0x83, MRM6r,
1739 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1740 "xor{l}\t{$src2, $dst|$dst, $src2}",
1741 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
1742 (implicit EFLAGS)]>;
1744 let isTwoAddress = 0 in {
1745 def XOR8mr : I<0x30, MRMDestMem,
1746 (outs), (ins i8mem :$dst, GR8 :$src),
1747 "xor{b}\t{$src, $dst|$dst, $src}",
1748 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
1749 (implicit EFLAGS)]>;
1750 def XOR16mr : I<0x31, MRMDestMem,
1751 (outs), (ins i16mem:$dst, GR16:$src),
1752 "xor{w}\t{$src, $dst|$dst, $src}",
1753 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
1754 (implicit EFLAGS)]>,
1756 def XOR32mr : I<0x31, MRMDestMem,
1757 (outs), (ins i32mem:$dst, GR32:$src),
1758 "xor{l}\t{$src, $dst|$dst, $src}",
1759 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
1760 (implicit EFLAGS)]>;
1761 def XOR8mi : Ii8<0x80, MRM6m,
1762 (outs), (ins i8mem :$dst, i8imm :$src),
1763 "xor{b}\t{$src, $dst|$dst, $src}",
1764 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
1765 (implicit EFLAGS)]>;
1766 def XOR16mi : Ii16<0x81, MRM6m,
1767 (outs), (ins i16mem:$dst, i16imm:$src),
1768 "xor{w}\t{$src, $dst|$dst, $src}",
1769 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
1770 (implicit EFLAGS)]>,
1772 def XOR32mi : Ii32<0x81, MRM6m,
1773 (outs), (ins i32mem:$dst, i32imm:$src),
1774 "xor{l}\t{$src, $dst|$dst, $src}",
1775 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
1776 (implicit EFLAGS)]>;
1777 def XOR16mi8 : Ii8<0x83, MRM6m,
1778 (outs), (ins i16mem:$dst, i16i8imm :$src),
1779 "xor{w}\t{$src, $dst|$dst, $src}",
1780 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
1781 (implicit EFLAGS)]>,
1783 def XOR32mi8 : Ii8<0x83, MRM6m,
1784 (outs), (ins i32mem:$dst, i32i8imm :$src),
1785 "xor{l}\t{$src, $dst|$dst, $src}",
1786 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
1787 (implicit EFLAGS)]>;
1788 } // isTwoAddress = 0
1789 } // Defs = [EFLAGS]
1791 // Shift instructions
1792 let Defs = [EFLAGS] in {
1793 let Uses = [CL] in {
1794 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1795 "shl{b}\t{%cl, $dst|$dst, CL}",
1796 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1797 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1798 "shl{w}\t{%cl, $dst|$dst, CL}",
1799 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1800 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1801 "shl{l}\t{%cl, $dst|$dst, CL}",
1802 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1805 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1806 "shl{b}\t{$src2, $dst|$dst, $src2}",
1807 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1808 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1809 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1810 "shl{w}\t{$src2, $dst|$dst, $src2}",
1811 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1812 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1813 "shl{l}\t{$src2, $dst|$dst, $src2}",
1814 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1815 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1817 } // isConvertibleToThreeAddress = 1
1819 let isTwoAddress = 0 in {
1820 let Uses = [CL] in {
1821 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1822 "shl{b}\t{%cl, $dst|$dst, CL}",
1823 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1824 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1825 "shl{w}\t{%cl, $dst|$dst, CL}",
1826 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1827 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1828 "shl{l}\t{%cl, $dst|$dst, CL}",
1829 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1831 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1832 "shl{b}\t{$src, $dst|$dst, $src}",
1833 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1834 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1835 "shl{w}\t{$src, $dst|$dst, $src}",
1836 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1838 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1839 "shl{l}\t{$src, $dst|$dst, $src}",
1840 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1843 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1845 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1846 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1848 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1850 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1852 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1855 let Uses = [CL] in {
1856 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1857 "shr{b}\t{%cl, $dst|$dst, CL}",
1858 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1859 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1860 "shr{w}\t{%cl, $dst|$dst, CL}",
1861 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1862 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1863 "shr{l}\t{%cl, $dst|$dst, CL}",
1864 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1867 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1868 "shr{b}\t{$src2, $dst|$dst, $src2}",
1869 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1870 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1871 "shr{w}\t{$src2, $dst|$dst, $src2}",
1872 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1873 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1874 "shr{l}\t{$src2, $dst|$dst, $src2}",
1875 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1878 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1880 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1881 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1883 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1884 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1886 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1888 let isTwoAddress = 0 in {
1889 let Uses = [CL] in {
1890 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1891 "shr{b}\t{%cl, $dst|$dst, CL}",
1892 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1893 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1894 "shr{w}\t{%cl, $dst|$dst, CL}",
1895 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1897 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1898 "shr{l}\t{%cl, $dst|$dst, CL}",
1899 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1901 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1902 "shr{b}\t{$src, $dst|$dst, $src}",
1903 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1904 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1905 "shr{w}\t{$src, $dst|$dst, $src}",
1906 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1908 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1909 "shr{l}\t{$src, $dst|$dst, $src}",
1910 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1913 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1915 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1916 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1918 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1919 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1921 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1924 let Uses = [CL] in {
1925 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1926 "sar{b}\t{%cl, $dst|$dst, CL}",
1927 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1928 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1929 "sar{w}\t{%cl, $dst|$dst, CL}",
1930 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1931 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1932 "sar{l}\t{%cl, $dst|$dst, CL}",
1933 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1936 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1937 "sar{b}\t{$src2, $dst|$dst, $src2}",
1938 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1939 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1940 "sar{w}\t{$src2, $dst|$dst, $src2}",
1941 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1943 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1944 "sar{l}\t{$src2, $dst|$dst, $src2}",
1945 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1948 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1950 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1951 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1953 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1954 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1956 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1958 let isTwoAddress = 0 in {
1959 let Uses = [CL] in {
1960 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1961 "sar{b}\t{%cl, $dst|$dst, CL}",
1962 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
1963 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1964 "sar{w}\t{%cl, $dst|$dst, CL}",
1965 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1966 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1967 "sar{l}\t{%cl, $dst|$dst, CL}",
1968 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1970 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1971 "sar{b}\t{$src, $dst|$dst, $src}",
1972 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1973 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1974 "sar{w}\t{$src, $dst|$dst, $src}",
1975 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1977 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1978 "sar{l}\t{$src, $dst|$dst, $src}",
1979 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1982 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1984 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1985 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1987 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1989 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
1991 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1994 // Rotate instructions
1995 // FIXME: provide shorter instructions when imm8 == 1
1996 let Uses = [CL] in {
1997 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
1998 "rol{b}\t{%cl, $dst|$dst, CL}",
1999 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
2000 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
2001 "rol{w}\t{%cl, $dst|$dst, CL}",
2002 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
2003 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
2004 "rol{l}\t{%cl, $dst|$dst, CL}",
2005 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2008 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2009 "rol{b}\t{$src2, $dst|$dst, $src2}",
2010 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2011 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2012 "rol{w}\t{$src2, $dst|$dst, $src2}",
2013 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2014 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2015 "rol{l}\t{$src2, $dst|$dst, $src2}",
2016 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2019 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2021 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2022 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2024 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2025 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2027 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2029 let isTwoAddress = 0 in {
2030 let Uses = [CL] in {
2031 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2032 "rol{b}\t{%cl, $dst|$dst, CL}",
2033 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2034 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2035 "rol{w}\t{%cl, $dst|$dst, CL}",
2036 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2037 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2038 "rol{l}\t{%cl, $dst|$dst, CL}",
2039 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2041 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2042 "rol{b}\t{$src, $dst|$dst, $src}",
2043 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2044 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2045 "rol{w}\t{$src, $dst|$dst, $src}",
2046 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2048 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2049 "rol{l}\t{$src, $dst|$dst, $src}",
2050 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2053 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2055 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2056 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2058 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2060 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2062 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2065 let Uses = [CL] in {
2066 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2067 "ror{b}\t{%cl, $dst|$dst, CL}",
2068 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2069 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2070 "ror{w}\t{%cl, $dst|$dst, CL}",
2071 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2072 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2073 "ror{l}\t{%cl, $dst|$dst, CL}",
2074 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2077 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2078 "ror{b}\t{$src2, $dst|$dst, $src2}",
2079 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2080 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2081 "ror{w}\t{$src2, $dst|$dst, $src2}",
2082 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2083 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2084 "ror{l}\t{$src2, $dst|$dst, $src2}",
2085 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2088 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2090 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2091 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2093 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2094 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2096 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2098 let isTwoAddress = 0 in {
2099 let Uses = [CL] in {
2100 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2101 "ror{b}\t{%cl, $dst|$dst, CL}",
2102 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2103 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2104 "ror{w}\t{%cl, $dst|$dst, CL}",
2105 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2106 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2107 "ror{l}\t{%cl, $dst|$dst, CL}",
2108 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2110 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2111 "ror{b}\t{$src, $dst|$dst, $src}",
2112 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2113 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2114 "ror{w}\t{$src, $dst|$dst, $src}",
2115 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2117 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2118 "ror{l}\t{$src, $dst|$dst, $src}",
2119 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2122 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2124 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2125 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2127 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2129 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2131 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2136 // Double shift instructions (generalizations of rotate)
2137 let Uses = [CL] in {
2138 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2139 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2140 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2141 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2142 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2143 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2144 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2145 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2146 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2148 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2149 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2150 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2154 let isCommutable = 1 in { // These instructions commute to each other.
2155 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2156 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2157 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2158 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2161 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2162 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2163 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2164 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2167 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2168 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2169 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2170 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2173 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2174 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2175 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2176 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2181 let isTwoAddress = 0 in {
2182 let Uses = [CL] in {
2183 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2184 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2185 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2187 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2188 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2189 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2192 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2193 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2194 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2195 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2196 (i8 imm:$src3)), addr:$dst)]>,
2198 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2199 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2200 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2201 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2202 (i8 imm:$src3)), addr:$dst)]>,
2205 let Uses = [CL] in {
2206 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2207 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2208 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2209 addr:$dst)]>, TB, OpSize;
2210 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2211 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2212 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2213 addr:$dst)]>, TB, OpSize;
2215 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2216 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2217 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2218 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2219 (i8 imm:$src3)), addr:$dst)]>,
2221 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2222 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2223 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2224 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2225 (i8 imm:$src3)), addr:$dst)]>,
2228 } // Defs = [EFLAGS]
2232 let Defs = [EFLAGS] in {
2233 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2234 // Register-Register Addition
2235 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2236 (ins GR8 :$src1, GR8 :$src2),
2237 "add{b}\t{$src2, $dst|$dst, $src2}",
2238 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
2239 (implicit EFLAGS)]>;
2241 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2242 // Register-Register Addition
2243 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2244 (ins GR16:$src1, GR16:$src2),
2245 "add{w}\t{$src2, $dst|$dst, $src2}",
2246 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2247 (implicit EFLAGS)]>, OpSize;
2248 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2249 (ins GR32:$src1, GR32:$src2),
2250 "add{l}\t{$src2, $dst|$dst, $src2}",
2251 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2252 (implicit EFLAGS)]>;
2253 } // end isConvertibleToThreeAddress
2254 } // end isCommutable
2256 // Register-Memory Addition
2257 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2258 (ins GR8 :$src1, i8mem :$src2),
2259 "add{b}\t{$src2, $dst|$dst, $src2}",
2260 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2261 (implicit EFLAGS)]>;
2262 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2263 (ins GR16:$src1, i16mem:$src2),
2264 "add{w}\t{$src2, $dst|$dst, $src2}",
2265 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2266 (implicit EFLAGS)]>, OpSize;
2267 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2268 (ins GR32:$src1, i32mem:$src2),
2269 "add{l}\t{$src2, $dst|$dst, $src2}",
2270 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2271 (implicit EFLAGS)]>;
2273 // Register-Integer Addition
2274 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2275 "add{b}\t{$src2, $dst|$dst, $src2}",
2276 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2277 (implicit EFLAGS)]>;
2279 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2280 // Register-Integer Addition
2281 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2282 (ins GR16:$src1, i16imm:$src2),
2283 "add{w}\t{$src2, $dst|$dst, $src2}",
2284 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2285 (implicit EFLAGS)]>, OpSize;
2286 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2287 (ins GR32:$src1, i32imm:$src2),
2288 "add{l}\t{$src2, $dst|$dst, $src2}",
2289 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2290 (implicit EFLAGS)]>;
2291 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2292 (ins GR16:$src1, i16i8imm:$src2),
2293 "add{w}\t{$src2, $dst|$dst, $src2}",
2294 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2295 (implicit EFLAGS)]>, OpSize;
2296 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2297 (ins GR32:$src1, i32i8imm:$src2),
2298 "add{l}\t{$src2, $dst|$dst, $src2}",
2299 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2300 (implicit EFLAGS)]>;
2303 let isTwoAddress = 0 in {
2304 // Memory-Register Addition
2305 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2306 "add{b}\t{$src2, $dst|$dst, $src2}",
2307 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2308 (implicit EFLAGS)]>;
2309 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2310 "add{w}\t{$src2, $dst|$dst, $src2}",
2311 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2312 (implicit EFLAGS)]>, OpSize;
2313 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2314 "add{l}\t{$src2, $dst|$dst, $src2}",
2315 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2316 (implicit EFLAGS)]>;
2317 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2318 "add{b}\t{$src2, $dst|$dst, $src2}",
2319 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2320 (implicit EFLAGS)]>;
2321 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2322 "add{w}\t{$src2, $dst|$dst, $src2}",
2323 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2324 (implicit EFLAGS)]>, OpSize;
2325 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2326 "add{l}\t{$src2, $dst|$dst, $src2}",
2327 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2328 (implicit EFLAGS)]>;
2329 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2330 "add{w}\t{$src2, $dst|$dst, $src2}",
2331 [(store (add (load addr:$dst), i16immSExt8:$src2),
2333 (implicit EFLAGS)]>, OpSize;
2334 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2335 "add{l}\t{$src2, $dst|$dst, $src2}",
2336 [(store (add (load addr:$dst), i32immSExt8:$src2),
2338 (implicit EFLAGS)]>;
2341 let Uses = [EFLAGS] in {
2342 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2343 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2344 "adc{b}\t{$src2, $dst|$dst, $src2}",
2345 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2346 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2347 (ins GR16:$src1, GR16:$src2),
2348 "adc{w}\t{$src2, $dst|$dst, $src2}",
2349 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2350 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2351 (ins GR32:$src1, GR32:$src2),
2352 "adc{l}\t{$src2, $dst|$dst, $src2}",
2353 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2355 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2356 (ins GR8:$src1, i8mem:$src2),
2357 "adc{b}\t{$src2, $dst|$dst, $src2}",
2358 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2359 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2360 (ins GR16:$src1, i16mem:$src2),
2361 "adc{w}\t{$src2, $dst|$dst, $src2}",
2362 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2364 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2365 (ins GR32:$src1, i32mem:$src2),
2366 "adc{l}\t{$src2, $dst|$dst, $src2}",
2367 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2368 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2369 "adc{b}\t{$src2, $dst|$dst, $src2}",
2370 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2371 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2372 (ins GR16:$src1, i16imm:$src2),
2373 "adc{w}\t{$src2, $dst|$dst, $src2}",
2374 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2375 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2376 (ins GR16:$src1, i16i8imm:$src2),
2377 "adc{w}\t{$src2, $dst|$dst, $src2}",
2378 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2380 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2381 (ins GR32:$src1, i32imm:$src2),
2382 "adc{l}\t{$src2, $dst|$dst, $src2}",
2383 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2384 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2385 (ins GR32:$src1, i32i8imm:$src2),
2386 "adc{l}\t{$src2, $dst|$dst, $src2}",
2387 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2389 let isTwoAddress = 0 in {
2390 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2391 "adc{b}\t{$src2, $dst|$dst, $src2}",
2392 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2393 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2394 "adc{w}\t{$src2, $dst|$dst, $src2}",
2395 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2397 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2398 "adc{l}\t{$src2, $dst|$dst, $src2}",
2399 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2400 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2401 "adc{b}\t{$src2, $dst|$dst, $src2}",
2402 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2403 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2404 "adc{w}\t{$src2, $dst|$dst, $src2}",
2405 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2407 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2408 "adc{w}\t{$src2, $dst|$dst, $src2}",
2409 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2411 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2412 "adc{l}\t{$src2, $dst|$dst, $src2}",
2413 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2414 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2415 "adc{l}\t{$src2, $dst|$dst, $src2}",
2416 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2418 } // Uses = [EFLAGS]
2420 // Register-Register Subtraction
2421 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2422 "sub{b}\t{$src2, $dst|$dst, $src2}",
2423 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2424 (implicit EFLAGS)]>;
2425 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2426 "sub{w}\t{$src2, $dst|$dst, $src2}",
2427 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2428 (implicit EFLAGS)]>, OpSize;
2429 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2430 "sub{l}\t{$src2, $dst|$dst, $src2}",
2431 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2432 (implicit EFLAGS)]>;
2434 // Register-Memory Subtraction
2435 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2436 (ins GR8 :$src1, i8mem :$src2),
2437 "sub{b}\t{$src2, $dst|$dst, $src2}",
2438 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2439 (implicit EFLAGS)]>;
2440 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2441 (ins GR16:$src1, i16mem:$src2),
2442 "sub{w}\t{$src2, $dst|$dst, $src2}",
2443 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2444 (implicit EFLAGS)]>, OpSize;
2445 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2446 (ins GR32:$src1, i32mem:$src2),
2447 "sub{l}\t{$src2, $dst|$dst, $src2}",
2448 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2449 (implicit EFLAGS)]>;
2451 // Register-Integer Subtraction
2452 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2453 (ins GR8:$src1, i8imm:$src2),
2454 "sub{b}\t{$src2, $dst|$dst, $src2}",
2455 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2456 (implicit EFLAGS)]>;
2457 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2458 (ins GR16:$src1, i16imm:$src2),
2459 "sub{w}\t{$src2, $dst|$dst, $src2}",
2460 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2461 (implicit EFLAGS)]>, OpSize;
2462 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2463 (ins GR32:$src1, i32imm:$src2),
2464 "sub{l}\t{$src2, $dst|$dst, $src2}",
2465 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2466 (implicit EFLAGS)]>;
2467 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2468 (ins GR16:$src1, i16i8imm:$src2),
2469 "sub{w}\t{$src2, $dst|$dst, $src2}",
2470 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2471 (implicit EFLAGS)]>, OpSize;
2472 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2473 (ins GR32:$src1, i32i8imm:$src2),
2474 "sub{l}\t{$src2, $dst|$dst, $src2}",
2475 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2476 (implicit EFLAGS)]>;
2478 let isTwoAddress = 0 in {
2479 // Memory-Register Subtraction
2480 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2481 "sub{b}\t{$src2, $dst|$dst, $src2}",
2482 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2483 (implicit EFLAGS)]>;
2484 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2485 "sub{w}\t{$src2, $dst|$dst, $src2}",
2486 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2487 (implicit EFLAGS)]>, OpSize;
2488 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2489 "sub{l}\t{$src2, $dst|$dst, $src2}",
2490 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2491 (implicit EFLAGS)]>;
2493 // Memory-Integer Subtraction
2494 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2495 "sub{b}\t{$src2, $dst|$dst, $src2}",
2496 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2497 (implicit EFLAGS)]>;
2498 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2499 "sub{w}\t{$src2, $dst|$dst, $src2}",
2500 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2501 (implicit EFLAGS)]>, OpSize;
2502 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2503 "sub{l}\t{$src2, $dst|$dst, $src2}",
2504 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2505 (implicit EFLAGS)]>;
2506 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2507 "sub{w}\t{$src2, $dst|$dst, $src2}",
2508 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2510 (implicit EFLAGS)]>, OpSize;
2511 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2512 "sub{l}\t{$src2, $dst|$dst, $src2}",
2513 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2515 (implicit EFLAGS)]>;
2518 let Uses = [EFLAGS] in {
2519 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
2520 (ins GR8:$src1, GR8:$src2),
2521 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2522 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
2523 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
2524 (ins GR16:$src1, GR16:$src2),
2525 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2526 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
2527 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
2528 (ins GR32:$src1, GR32:$src2),
2529 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2530 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2532 let isTwoAddress = 0 in {
2533 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2534 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2535 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
2536 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2537 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2538 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
2540 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2541 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2542 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2543 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2544 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2545 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2546 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
2547 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2548 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2550 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2551 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2552 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2554 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2555 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2556 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2557 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2558 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2559 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2561 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
2562 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2563 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
2564 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
2565 (ins GR16:$src1, i16mem:$src2),
2566 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2567 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
2569 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
2570 (ins GR32:$src1, i32mem:$src2),
2571 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2572 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2573 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2574 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2575 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
2576 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
2577 (ins GR16:$src1, i16imm:$src2),
2578 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2579 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
2580 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
2581 (ins GR16:$src1, i16i8imm:$src2),
2582 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2583 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
2585 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
2586 (ins GR32:$src1, i32imm:$src2),
2587 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2588 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2589 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
2590 (ins GR32:$src1, i32i8imm:$src2),
2591 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2592 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2593 } // Uses = [EFLAGS]
2594 } // Defs = [EFLAGS]
2596 let Defs = [EFLAGS] in {
2597 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2598 // Register-Register Signed Integer Multiply
2599 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2600 "imul{w}\t{$src2, $dst|$dst, $src2}",
2601 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
2602 (implicit EFLAGS)]>, TB, OpSize;
2603 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2604 "imul{l}\t{$src2, $dst|$dst, $src2}",
2605 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
2606 (implicit EFLAGS)]>, TB;
2609 // Register-Memory Signed Integer Multiply
2610 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
2611 (ins GR16:$src1, i16mem:$src2),
2612 "imul{w}\t{$src2, $dst|$dst, $src2}",
2613 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
2614 (implicit EFLAGS)]>, TB, OpSize;
2615 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2616 "imul{l}\t{$src2, $dst|$dst, $src2}",
2617 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
2618 (implicit EFLAGS)]>, TB;
2619 } // Defs = [EFLAGS]
2620 } // end Two Address instructions
2622 // Suprisingly enough, these are not two address instructions!
2623 let Defs = [EFLAGS] in {
2624 // Register-Integer Signed Integer Multiply
2625 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2626 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2627 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2628 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
2629 (implicit EFLAGS)]>, OpSize;
2630 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2631 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2632 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2633 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
2634 (implicit EFLAGS)]>;
2635 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2636 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2637 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2638 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
2639 (implicit EFLAGS)]>, OpSize;
2640 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2641 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2642 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2643 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
2644 (implicit EFLAGS)]>;
2646 // Memory-Integer Signed Integer Multiply
2647 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2648 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2649 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2650 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
2651 (implicit EFLAGS)]>, OpSize;
2652 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2653 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2654 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2655 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
2656 (implicit EFLAGS)]>;
2657 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2658 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2659 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2660 [(set GR16:$dst, (mul (load addr:$src1),
2661 i16immSExt8:$src2)),
2662 (implicit EFLAGS)]>, OpSize;
2663 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2664 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2665 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2666 [(set GR32:$dst, (mul (load addr:$src1),
2667 i32immSExt8:$src2)),
2668 (implicit EFLAGS)]>;
2669 } // Defs = [EFLAGS]
2671 //===----------------------------------------------------------------------===//
2672 // Test instructions are just like AND, except they don't generate a result.
2674 let Defs = [EFLAGS] in {
2675 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2676 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2677 "test{b}\t{$src2, $src1|$src1, $src2}",
2678 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
2679 (implicit EFLAGS)]>;
2680 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2681 "test{w}\t{$src2, $src1|$src1, $src2}",
2682 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
2683 (implicit EFLAGS)]>,
2685 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2686 "test{l}\t{$src2, $src1|$src1, $src2}",
2687 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
2688 (implicit EFLAGS)]>;
2691 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2692 "test{b}\t{$src2, $src1|$src1, $src2}",
2693 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2694 (implicit EFLAGS)]>;
2695 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2696 "test{w}\t{$src2, $src1|$src1, $src2}",
2697 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2698 (implicit EFLAGS)]>, OpSize;
2699 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2700 "test{l}\t{$src2, $src1|$src1, $src2}",
2701 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2702 (implicit EFLAGS)]>;
2704 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2705 (outs), (ins GR8:$src1, i8imm:$src2),
2706 "test{b}\t{$src2, $src1|$src1, $src2}",
2707 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
2708 (implicit EFLAGS)]>;
2709 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2710 (outs), (ins GR16:$src1, i16imm:$src2),
2711 "test{w}\t{$src2, $src1|$src1, $src2}",
2712 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
2713 (implicit EFLAGS)]>, OpSize;
2714 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2715 (outs), (ins GR32:$src1, i32imm:$src2),
2716 "test{l}\t{$src2, $src1|$src1, $src2}",
2717 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
2718 (implicit EFLAGS)]>;
2720 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2721 (outs), (ins i8mem:$src1, i8imm:$src2),
2722 "test{b}\t{$src2, $src1|$src1, $src2}",
2723 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2724 (implicit EFLAGS)]>;
2725 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2726 (outs), (ins i16mem:$src1, i16imm:$src2),
2727 "test{w}\t{$src2, $src1|$src1, $src2}",
2728 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2729 (implicit EFLAGS)]>, OpSize;
2730 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2731 (outs), (ins i32mem:$src1, i32imm:$src2),
2732 "test{l}\t{$src2, $src1|$src1, $src2}",
2733 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2734 (implicit EFLAGS)]>;
2735 } // Defs = [EFLAGS]
2738 // Condition code ops, incl. set if equal/not equal/...
2739 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2740 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2741 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2742 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2744 let Uses = [EFLAGS] in {
2745 def SETEr : I<0x94, MRM0r,
2746 (outs GR8 :$dst), (ins),
2748 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2750 def SETEm : I<0x94, MRM0m,
2751 (outs), (ins i8mem:$dst),
2753 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2756 def SETNEr : I<0x95, MRM0r,
2757 (outs GR8 :$dst), (ins),
2759 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2761 def SETNEm : I<0x95, MRM0m,
2762 (outs), (ins i8mem:$dst),
2764 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2767 def SETLr : I<0x9C, MRM0r,
2768 (outs GR8 :$dst), (ins),
2770 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2771 TB; // GR8 = < signed
2772 def SETLm : I<0x9C, MRM0m,
2773 (outs), (ins i8mem:$dst),
2775 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2776 TB; // [mem8] = < signed
2778 def SETGEr : I<0x9D, MRM0r,
2779 (outs GR8 :$dst), (ins),
2781 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2782 TB; // GR8 = >= signed
2783 def SETGEm : I<0x9D, MRM0m,
2784 (outs), (ins i8mem:$dst),
2786 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2787 TB; // [mem8] = >= signed
2789 def SETLEr : I<0x9E, MRM0r,
2790 (outs GR8 :$dst), (ins),
2792 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2793 TB; // GR8 = <= signed
2794 def SETLEm : I<0x9E, MRM0m,
2795 (outs), (ins i8mem:$dst),
2797 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2798 TB; // [mem8] = <= signed
2800 def SETGr : I<0x9F, MRM0r,
2801 (outs GR8 :$dst), (ins),
2803 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2804 TB; // GR8 = > signed
2805 def SETGm : I<0x9F, MRM0m,
2806 (outs), (ins i8mem:$dst),
2808 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2809 TB; // [mem8] = > signed
2811 def SETBr : I<0x92, MRM0r,
2812 (outs GR8 :$dst), (ins),
2814 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2815 TB; // GR8 = < unsign
2816 def SETBm : I<0x92, MRM0m,
2817 (outs), (ins i8mem:$dst),
2819 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
2820 TB; // [mem8] = < unsign
2822 def SETAEr : I<0x93, MRM0r,
2823 (outs GR8 :$dst), (ins),
2825 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
2826 TB; // GR8 = >= unsign
2827 def SETAEm : I<0x93, MRM0m,
2828 (outs), (ins i8mem:$dst),
2830 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
2831 TB; // [mem8] = >= unsign
2833 def SETBEr : I<0x96, MRM0r,
2834 (outs GR8 :$dst), (ins),
2836 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
2837 TB; // GR8 = <= unsign
2838 def SETBEm : I<0x96, MRM0m,
2839 (outs), (ins i8mem:$dst),
2841 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
2842 TB; // [mem8] = <= unsign
2844 def SETAr : I<0x97, MRM0r,
2845 (outs GR8 :$dst), (ins),
2847 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
2848 TB; // GR8 = > signed
2849 def SETAm : I<0x97, MRM0m,
2850 (outs), (ins i8mem:$dst),
2852 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
2853 TB; // [mem8] = > signed
2855 def SETSr : I<0x98, MRM0r,
2856 (outs GR8 :$dst), (ins),
2858 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
2859 TB; // GR8 = <sign bit>
2860 def SETSm : I<0x98, MRM0m,
2861 (outs), (ins i8mem:$dst),
2863 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
2864 TB; // [mem8] = <sign bit>
2865 def SETNSr : I<0x99, MRM0r,
2866 (outs GR8 :$dst), (ins),
2868 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
2869 TB; // GR8 = !<sign bit>
2870 def SETNSm : I<0x99, MRM0m,
2871 (outs), (ins i8mem:$dst),
2873 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
2874 TB; // [mem8] = !<sign bit>
2876 def SETPr : I<0x9A, MRM0r,
2877 (outs GR8 :$dst), (ins),
2879 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
2881 def SETPm : I<0x9A, MRM0m,
2882 (outs), (ins i8mem:$dst),
2884 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
2885 TB; // [mem8] = parity
2886 def SETNPr : I<0x9B, MRM0r,
2887 (outs GR8 :$dst), (ins),
2889 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
2890 TB; // GR8 = not parity
2891 def SETNPm : I<0x9B, MRM0m,
2892 (outs), (ins i8mem:$dst),
2894 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
2895 TB; // [mem8] = not parity
2897 def SETOr : I<0x90, MRM0r,
2898 (outs GR8 :$dst), (ins),
2900 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
2901 TB; // GR8 = overflow
2902 def SETOm : I<0x90, MRM0m,
2903 (outs), (ins i8mem:$dst),
2905 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
2906 TB; // [mem8] = overflow
2907 def SETNOr : I<0x91, MRM0r,
2908 (outs GR8 :$dst), (ins),
2910 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
2911 TB; // GR8 = not overflow
2912 def SETNOm : I<0x91, MRM0m,
2913 (outs), (ins i8mem:$dst),
2915 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
2916 TB; // [mem8] = not overflow
2917 } // Uses = [EFLAGS]
2920 // Integer comparisons
2921 let Defs = [EFLAGS] in {
2922 def CMP8rr : I<0x38, MRMDestReg,
2923 (outs), (ins GR8 :$src1, GR8 :$src2),
2924 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2925 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2926 def CMP16rr : I<0x39, MRMDestReg,
2927 (outs), (ins GR16:$src1, GR16:$src2),
2928 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2929 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
2930 def CMP32rr : I<0x39, MRMDestReg,
2931 (outs), (ins GR32:$src1, GR32:$src2),
2932 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2933 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
2934 def CMP8mr : I<0x38, MRMDestMem,
2935 (outs), (ins i8mem :$src1, GR8 :$src2),
2936 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2937 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
2938 (implicit EFLAGS)]>;
2939 def CMP16mr : I<0x39, MRMDestMem,
2940 (outs), (ins i16mem:$src1, GR16:$src2),
2941 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2942 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
2943 (implicit EFLAGS)]>, OpSize;
2944 def CMP32mr : I<0x39, MRMDestMem,
2945 (outs), (ins i32mem:$src1, GR32:$src2),
2946 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2947 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
2948 (implicit EFLAGS)]>;
2949 def CMP8rm : I<0x3A, MRMSrcMem,
2950 (outs), (ins GR8 :$src1, i8mem :$src2),
2951 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2952 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
2953 (implicit EFLAGS)]>;
2954 def CMP16rm : I<0x3B, MRMSrcMem,
2955 (outs), (ins GR16:$src1, i16mem:$src2),
2956 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2957 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
2958 (implicit EFLAGS)]>, OpSize;
2959 def CMP32rm : I<0x3B, MRMSrcMem,
2960 (outs), (ins GR32:$src1, i32mem:$src2),
2961 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2962 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
2963 (implicit EFLAGS)]>;
2964 def CMP8ri : Ii8<0x80, MRM7r,
2965 (outs), (ins GR8:$src1, i8imm:$src2),
2966 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2967 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
2968 def CMP16ri : Ii16<0x81, MRM7r,
2969 (outs), (ins GR16:$src1, i16imm:$src2),
2970 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2971 [(X86cmp GR16:$src1, imm:$src2),
2972 (implicit EFLAGS)]>, OpSize;
2973 def CMP32ri : Ii32<0x81, MRM7r,
2974 (outs), (ins GR32:$src1, i32imm:$src2),
2975 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2976 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
2977 def CMP8mi : Ii8 <0x80, MRM7m,
2978 (outs), (ins i8mem :$src1, i8imm :$src2),
2979 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2980 [(X86cmp (loadi8 addr:$src1), imm:$src2),
2981 (implicit EFLAGS)]>;
2982 def CMP16mi : Ii16<0x81, MRM7m,
2983 (outs), (ins i16mem:$src1, i16imm:$src2),
2984 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2985 [(X86cmp (loadi16 addr:$src1), imm:$src2),
2986 (implicit EFLAGS)]>, OpSize;
2987 def CMP32mi : Ii32<0x81, MRM7m,
2988 (outs), (ins i32mem:$src1, i32imm:$src2),
2989 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2990 [(X86cmp (loadi32 addr:$src1), imm:$src2),
2991 (implicit EFLAGS)]>;
2992 def CMP16ri8 : Ii8<0x83, MRM7r,
2993 (outs), (ins GR16:$src1, i16i8imm:$src2),
2994 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2995 [(X86cmp GR16:$src1, i16immSExt8:$src2),
2996 (implicit EFLAGS)]>, OpSize;
2997 def CMP16mi8 : Ii8<0x83, MRM7m,
2998 (outs), (ins i16mem:$src1, i16i8imm:$src2),
2999 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3000 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
3001 (implicit EFLAGS)]>, OpSize;
3002 def CMP32mi8 : Ii8<0x83, MRM7m,
3003 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3004 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3005 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
3006 (implicit EFLAGS)]>;
3007 def CMP32ri8 : Ii8<0x83, MRM7r,
3008 (outs), (ins GR32:$src1, i32i8imm:$src2),
3009 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3010 [(X86cmp GR32:$src1, i32immSExt8:$src2),
3011 (implicit EFLAGS)]>;
3012 } // Defs = [EFLAGS]
3015 // TODO: BTC, BTR, and BTS
3016 let Defs = [EFLAGS] in {
3017 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3018 "bt{w}\t{$src2, $src1|$src1, $src2}",
3019 [(X86bt GR16:$src1, GR16:$src2),
3020 (implicit EFLAGS)]>, OpSize, TB;
3021 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3022 "bt{l}\t{$src2, $src1|$src1, $src2}",
3023 [(X86bt GR32:$src1, GR32:$src2),
3024 (implicit EFLAGS)]>, TB;
3026 // Unlike with the register+register form, the memory+register form of the
3027 // bt instruction does not ignore the high bits of the index. From ISel's
3028 // perspective, this is pretty bizarre. Disable these instructions for now.
3029 //def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3030 // "bt{w}\t{$src2, $src1|$src1, $src2}",
3031 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3032 // (implicit EFLAGS)]>, OpSize, TB, Requires<[FastBTMem]>;
3033 //def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3034 // "bt{l}\t{$src2, $src1|$src1, $src2}",
3035 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3036 // (implicit EFLAGS)]>, TB, Requires<[FastBTMem]>;
3038 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3039 "bt{w}\t{$src2, $src1|$src1, $src2}",
3040 [(X86bt GR16:$src1, i16immSExt8:$src2),
3041 (implicit EFLAGS)]>, OpSize, TB;
3042 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3043 "bt{l}\t{$src2, $src1|$src1, $src2}",
3044 [(X86bt GR32:$src1, i32immSExt8:$src2),
3045 (implicit EFLAGS)]>, TB;
3046 // Note that these instructions don't need FastBTMem because that
3047 // only applies when the other operand is in a register. When it's
3048 // an immediate, bt is still fast.
3049 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3050 "bt{w}\t{$src2, $src1|$src1, $src2}",
3051 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
3052 (implicit EFLAGS)]>, OpSize, TB;
3053 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3054 "bt{l}\t{$src2, $src1|$src1, $src2}",
3055 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
3056 (implicit EFLAGS)]>, TB;
3057 } // Defs = [EFLAGS]
3059 // Sign/Zero extenders
3060 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3061 // of the register here. This has a smaller encoding and avoids a
3062 // partial-register update.
3063 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3064 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3065 [(set GR16:$dst, (sext GR8:$src))]>, TB;
3066 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3067 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3068 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3069 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3070 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3071 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3072 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3073 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3074 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3075 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3076 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3077 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3078 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3079 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3080 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3082 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3083 // of the register here. This has a smaller encoding and avoids a
3084 // partial-register update.
3085 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3086 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3087 [(set GR16:$dst, (zext GR8:$src))]>, TB;
3088 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3089 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3090 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3091 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3092 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3093 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3094 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3095 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3096 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3097 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3098 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3099 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3100 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3101 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3102 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3104 // These are the same as the regular regular MOVZX32rr8 and MOVZX32rm8
3105 // except that they use GR32_NOREX for the output operand register class
3106 // instead of GR32. This allows them to operate on h registers on x86-64.
3107 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3108 (outs GR32_NOREX:$dst), (ins GR8:$src),
3109 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3112 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3113 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3114 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3117 let neverHasSideEffects = 1 in {
3118 let Defs = [AX], Uses = [AL] in
3119 def CBW : I<0x98, RawFrm, (outs), (ins),
3120 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3121 let Defs = [EAX], Uses = [AX] in
3122 def CWDE : I<0x98, RawFrm, (outs), (ins),
3123 "{cwtl|cwde}", []>; // EAX = signext(AX)
3125 let Defs = [AX,DX], Uses = [AX] in
3126 def CWD : I<0x99, RawFrm, (outs), (ins),
3127 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3128 let Defs = [EAX,EDX], Uses = [EAX] in
3129 def CDQ : I<0x99, RawFrm, (outs), (ins),
3130 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3133 //===----------------------------------------------------------------------===//
3134 // Alias Instructions
3135 //===----------------------------------------------------------------------===//
3137 // Alias instructions that map movr0 to xor.
3138 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3139 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1 in {
3140 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
3141 "xor{b}\t$dst, $dst",
3142 [(set GR8:$dst, 0)]>;
3143 // Use xorl instead of xorw since we don't care about the high 16 bits,
3144 // it's smaller, and it avoids a partial-register update.
3145 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3146 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
3147 [(set GR16:$dst, 0)]>;
3148 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
3149 "xor{l}\t$dst, $dst",
3150 [(set GR32:$dst, 0)]>;
3153 //===----------------------------------------------------------------------===//
3154 // Thread Local Storage Instructions
3157 // All calls clobber the non-callee saved registers. ESP is marked as
3158 // a use to prevent stack-pointer assignments that appear immediately
3159 // before calls from potentially appearing dead.
3160 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3161 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3162 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3163 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3165 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3166 "leal\t$sym, %eax; "
3167 "call\t___tls_get_addr@PLT",
3168 [(X86tlsaddr tls32addr:$sym)]>,
3169 Requires<[In32BitMode]>;
3171 let AddedComplexity = 5 in
3172 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3173 "movl\t%gs:$src, $dst",
3174 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3176 let AddedComplexity = 5 in
3177 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3178 "movl\t%fs:$src, $dst",
3179 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3181 //===----------------------------------------------------------------------===//
3182 // DWARF Pseudo Instructions
3185 def DWARF_LOC : I<0, Pseudo, (outs),
3186 (ins i32imm:$line, i32imm:$col, i32imm:$file),
3187 ".loc\t$file $line $col",
3188 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
3191 //===----------------------------------------------------------------------===//
3192 // EH Pseudo Instructions
3194 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3196 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3197 "ret\t#eh_return, addr: $addr",
3198 [(X86ehret GR32:$addr)]>;
3202 //===----------------------------------------------------------------------===//
3206 // Atomic swap. These are just normal xchg instructions. But since a memory
3207 // operand is referenced, the atomicity is ensured.
3208 let Constraints = "$val = $dst" in {
3209 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3210 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3211 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3212 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3213 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3214 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3216 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3217 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3218 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3221 // Atomic compare and swap.
3222 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3223 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3225 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3226 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3228 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3229 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
3232 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3235 let Defs = [AX, EFLAGS], Uses = [AX] in {
3236 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3238 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3239 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3241 let Defs = [AL, EFLAGS], Uses = [AL] in {
3242 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3244 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3245 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3248 // Atomic exchange and add
3249 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3250 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3252 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3253 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3255 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3257 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3258 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3260 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3262 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3263 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3267 // Optimized codegen when the non-memory output is not used.
3268 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3269 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3271 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3272 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3274 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3275 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3277 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3278 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3280 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3281 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3283 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3284 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3286 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3287 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3289 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3290 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3292 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3294 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3296 "inc{b}\t$dst", []>, LOCK;
3297 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3299 "inc{w}\t$dst", []>, OpSize, LOCK;
3300 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3302 "inc{l}\t$dst", []>, LOCK;
3304 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3306 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3307 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3309 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3310 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3312 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3313 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3315 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3316 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3318 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3319 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3321 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3322 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3324 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3325 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3327 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3329 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3331 "dec{b}\t$dst", []>, LOCK;
3332 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3334 "dec{w}\t$dst", []>, OpSize, LOCK;
3335 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3337 "dec{l}\t$dst", []>, LOCK;
3339 // Atomic exchange, and, or, xor
3340 let Constraints = "$val = $dst", Defs = [EFLAGS],
3341 usesCustomDAGSchedInserter = 1 in {
3342 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3343 "#ATOMAND32 PSEUDO!",
3344 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3345 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3346 "#ATOMOR32 PSEUDO!",
3347 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
3348 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3349 "#ATOMXOR32 PSEUDO!",
3350 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
3351 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3352 "#ATOMNAND32 PSEUDO!",
3353 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
3354 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3355 "#ATOMMIN32 PSEUDO!",
3356 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
3357 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3358 "#ATOMMAX32 PSEUDO!",
3359 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
3360 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3361 "#ATOMUMIN32 PSEUDO!",
3362 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
3363 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3364 "#ATOMUMAX32 PSEUDO!",
3365 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
3367 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3368 "#ATOMAND16 PSEUDO!",
3369 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
3370 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3371 "#ATOMOR16 PSEUDO!",
3372 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
3373 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3374 "#ATOMXOR16 PSEUDO!",
3375 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
3376 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3377 "#ATOMNAND16 PSEUDO!",
3378 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
3379 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3380 "#ATOMMIN16 PSEUDO!",
3381 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
3382 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3383 "#ATOMMAX16 PSEUDO!",
3384 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
3385 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3386 "#ATOMUMIN16 PSEUDO!",
3387 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
3388 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3389 "#ATOMUMAX16 PSEUDO!",
3390 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
3392 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3393 "#ATOMAND8 PSEUDO!",
3394 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
3395 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3397 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
3398 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3399 "#ATOMXOR8 PSEUDO!",
3400 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
3401 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3402 "#ATOMNAND8 PSEUDO!",
3403 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
3406 let Constraints = "$val1 = $dst1, $val2 = $dst2",
3407 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
3408 Uses = [EAX, EBX, ECX, EDX],
3409 mayLoad = 1, mayStore = 1,
3410 usesCustomDAGSchedInserter = 1 in {
3411 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3412 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3413 "#ATOMAND6432 PSEUDO!", []>;
3414 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3415 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3416 "#ATOMOR6432 PSEUDO!", []>;
3417 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3418 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3419 "#ATOMXOR6432 PSEUDO!", []>;
3420 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3421 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3422 "#ATOMNAND6432 PSEUDO!", []>;
3423 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3424 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3425 "#ATOMADD6432 PSEUDO!", []>;
3426 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3427 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3428 "#ATOMSUB6432 PSEUDO!", []>;
3429 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3430 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3431 "#ATOMSWAP6432 PSEUDO!", []>;
3434 //===----------------------------------------------------------------------===//
3435 // Non-Instruction Patterns
3436 //===----------------------------------------------------------------------===//
3438 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
3439 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
3440 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
3441 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
3442 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
3443 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
3445 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
3446 (ADD32ri GR32:$src1, tconstpool:$src2)>;
3447 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
3448 (ADD32ri GR32:$src1, tjumptable:$src2)>;
3449 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
3450 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
3451 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
3452 (ADD32ri GR32:$src1, texternalsym:$src2)>;
3454 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
3455 (MOV32mi addr:$dst, tglobaladdr:$src)>;
3456 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
3457 (MOV32mi addr:$dst, texternalsym:$src)>;
3461 def : Pat<(X86tcret GR32:$dst, imm:$off),
3462 (TCRETURNri GR32:$dst, imm:$off)>;
3464 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
3465 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3467 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
3468 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3470 // Normal calls, with various flavors of addresses.
3471 def : Pat<(X86call (i32 tglobaladdr:$dst)),
3472 (CALLpcrel32 tglobaladdr:$dst)>;
3473 def : Pat<(X86call (i32 texternalsym:$dst)),
3474 (CALLpcrel32 texternalsym:$dst)>;
3475 def : Pat<(X86call (i32 imm:$dst)),
3476 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
3478 // X86 specific add which produces a flag.
3479 def : Pat<(addc GR32:$src1, GR32:$src2),
3480 (ADD32rr GR32:$src1, GR32:$src2)>;
3481 def : Pat<(addc GR32:$src1, (load addr:$src2)),
3482 (ADD32rm GR32:$src1, addr:$src2)>;
3483 def : Pat<(addc GR32:$src1, imm:$src2),
3484 (ADD32ri GR32:$src1, imm:$src2)>;
3485 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
3486 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3488 def : Pat<(subc GR32:$src1, GR32:$src2),
3489 (SUB32rr GR32:$src1, GR32:$src2)>;
3490 def : Pat<(subc GR32:$src1, (load addr:$src2)),
3491 (SUB32rm GR32:$src1, addr:$src2)>;
3492 def : Pat<(subc GR32:$src1, imm:$src2),
3493 (SUB32ri GR32:$src1, imm:$src2)>;
3494 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
3495 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3499 // TEST R,R is smaller than CMP R,0
3500 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
3501 (TEST8rr GR8:$src1, GR8:$src1)>;
3502 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
3503 (TEST16rr GR16:$src1, GR16:$src1)>;
3504 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
3505 (TEST32rr GR32:$src1, GR32:$src1)>;
3507 // Conditional moves with folded loads with operands swapped and conditions
3509 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
3510 (CMOVAE16rm GR16:$src2, addr:$src1)>;
3511 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
3512 (CMOVAE32rm GR32:$src2, addr:$src1)>;
3513 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
3514 (CMOVB16rm GR16:$src2, addr:$src1)>;
3515 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
3516 (CMOVB32rm GR32:$src2, addr:$src1)>;
3517 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
3518 (CMOVNE16rm GR16:$src2, addr:$src1)>;
3519 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
3520 (CMOVNE32rm GR32:$src2, addr:$src1)>;
3521 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
3522 (CMOVE16rm GR16:$src2, addr:$src1)>;
3523 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
3524 (CMOVE32rm GR32:$src2, addr:$src1)>;
3525 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
3526 (CMOVA16rm GR16:$src2, addr:$src1)>;
3527 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
3528 (CMOVA32rm GR32:$src2, addr:$src1)>;
3529 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
3530 (CMOVBE16rm GR16:$src2, addr:$src1)>;
3531 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
3532 (CMOVBE32rm GR32:$src2, addr:$src1)>;
3533 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
3534 (CMOVGE16rm GR16:$src2, addr:$src1)>;
3535 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
3536 (CMOVGE32rm GR32:$src2, addr:$src1)>;
3537 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
3538 (CMOVL16rm GR16:$src2, addr:$src1)>;
3539 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
3540 (CMOVL32rm GR32:$src2, addr:$src1)>;
3541 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
3542 (CMOVG16rm GR16:$src2, addr:$src1)>;
3543 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
3544 (CMOVG32rm GR32:$src2, addr:$src1)>;
3545 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
3546 (CMOVLE16rm GR16:$src2, addr:$src1)>;
3547 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
3548 (CMOVLE32rm GR32:$src2, addr:$src1)>;
3549 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
3550 (CMOVNP16rm GR16:$src2, addr:$src1)>;
3551 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
3552 (CMOVNP32rm GR32:$src2, addr:$src1)>;
3553 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
3554 (CMOVP16rm GR16:$src2, addr:$src1)>;
3555 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
3556 (CMOVP32rm GR32:$src2, addr:$src1)>;
3557 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
3558 (CMOVNS16rm GR16:$src2, addr:$src1)>;
3559 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
3560 (CMOVNS32rm GR32:$src2, addr:$src1)>;
3561 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
3562 (CMOVS16rm GR16:$src2, addr:$src1)>;
3563 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
3564 (CMOVS32rm GR32:$src2, addr:$src1)>;
3565 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
3566 (CMOVNO16rm GR16:$src2, addr:$src1)>;
3567 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
3568 (CMOVNO32rm GR32:$src2, addr:$src1)>;
3569 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
3570 (CMOVO16rm GR16:$src2, addr:$src1)>;
3571 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
3572 (CMOVO32rm GR32:$src2, addr:$src1)>;
3574 // zextload bool -> zextload byte
3575 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3576 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3577 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3579 // extload bool -> extload byte
3580 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3581 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>,
3582 Requires<[In32BitMode]>;
3583 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3584 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>,
3585 Requires<[In32BitMode]>;
3586 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
3587 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
3590 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>,
3591 Requires<[In32BitMode]>;
3592 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>,
3593 Requires<[In32BitMode]>;
3594 def : Pat<(i32 (anyext GR16:$src)),
3595 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
3597 // (and (i32 load), 255) -> (zextload i8)
3598 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
3599 (MOVZX32rm8 addr:$src)>;
3600 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
3601 (MOVZX32rm16 addr:$src)>;
3603 //===----------------------------------------------------------------------===//
3605 //===----------------------------------------------------------------------===//
3607 // Odd encoding trick: -128 fits into an 8-bit immediate field while
3608 // +128 doesn't, so in this special case use a sub instead of an add.
3609 def : Pat<(add GR16:$src1, 128),
3610 (SUB16ri8 GR16:$src1, -128)>;
3611 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
3612 (SUB16mi8 addr:$dst, -128)>;
3613 def : Pat<(add GR32:$src1, 128),
3614 (SUB32ri8 GR32:$src1, -128)>;
3615 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
3616 (SUB32mi8 addr:$dst, -128)>;
3618 // r & (2^16-1) ==> movz
3619 def : Pat<(and GR32:$src1, 0xffff),
3620 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
3621 // r & (2^8-1) ==> movz
3622 def : Pat<(and GR32:$src1, 0xff),
3623 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src1, GR32_ABCD),
3625 Requires<[In32BitMode]>;
3626 // r & (2^8-1) ==> movz
3627 def : Pat<(and GR16:$src1, 0xff),
3628 (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD),
3630 Requires<[In32BitMode]>;
3632 // sext_inreg patterns
3633 def : Pat<(sext_inreg GR32:$src, i16),
3634 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
3635 def : Pat<(sext_inreg GR32:$src, i8),
3636 (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3638 Requires<[In32BitMode]>;
3639 def : Pat<(sext_inreg GR16:$src, i8),
3640 (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3642 Requires<[In32BitMode]>;
3645 def : Pat<(i16 (trunc GR32:$src)),
3646 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
3647 def : Pat<(i8 (trunc GR32:$src)),
3648 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3650 Requires<[In32BitMode]>;
3651 def : Pat<(i8 (trunc GR16:$src)),
3652 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3654 Requires<[In32BitMode]>;
3656 // h-register tricks
3657 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
3658 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3659 x86_subreg_8bit_hi)>,
3660 Requires<[In32BitMode]>;
3661 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
3662 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3663 x86_subreg_8bit_hi)>,
3664 Requires<[In32BitMode]>;
3665 def : Pat<(srl_su GR16:$src, (i8 8)),
3668 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3669 x86_subreg_8bit_hi)),
3671 Requires<[In32BitMode]>;
3672 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
3673 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3674 x86_subreg_8bit_hi))>,
3675 Requires<[In32BitMode]>;
3676 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
3677 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3678 x86_subreg_8bit_hi))>,
3679 Requires<[In32BitMode]>;
3681 // (shl x, 1) ==> (add x, x)
3682 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
3683 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
3684 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
3686 // (shl x (and y, 31)) ==> (shl x, y)
3687 def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
3688 (SHL8rCL GR8:$src1)>;
3689 def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
3690 (SHL16rCL GR16:$src1)>;
3691 def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
3692 (SHL32rCL GR32:$src1)>;
3693 def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3694 (SHL8mCL addr:$dst)>;
3695 def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3696 (SHL16mCL addr:$dst)>;
3697 def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3698 (SHL32mCL addr:$dst)>;
3700 def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
3701 (SHR8rCL GR8:$src1)>;
3702 def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
3703 (SHR16rCL GR16:$src1)>;
3704 def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
3705 (SHR32rCL GR32:$src1)>;
3706 def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3707 (SHR8mCL addr:$dst)>;
3708 def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3709 (SHR16mCL addr:$dst)>;
3710 def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3711 (SHR32mCL addr:$dst)>;
3713 def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
3714 (SAR8rCL GR8:$src1)>;
3715 def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
3716 (SAR16rCL GR16:$src1)>;
3717 def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
3718 (SAR32rCL GR32:$src1)>;
3719 def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3720 (SAR8mCL addr:$dst)>;
3721 def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3722 (SAR16mCL addr:$dst)>;
3723 def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3724 (SAR32mCL addr:$dst)>;
3726 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
3727 def : Pat<(or (srl GR32:$src1, CL:$amt),
3728 (shl GR32:$src2, (sub 32, CL:$amt))),
3729 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3731 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
3732 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3733 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3735 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
3736 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3737 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3739 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3740 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3742 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3744 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3745 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3747 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
3748 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3749 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3751 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
3752 def : Pat<(or (shl GR32:$src1, CL:$amt),
3753 (srl GR32:$src2, (sub 32, CL:$amt))),
3754 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3756 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
3757 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3758 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3760 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
3761 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3762 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3764 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3765 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3767 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3769 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3770 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3772 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
3773 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3774 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3776 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
3777 def : Pat<(or (srl GR16:$src1, CL:$amt),
3778 (shl GR16:$src2, (sub 16, CL:$amt))),
3779 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3781 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
3782 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3783 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3785 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
3786 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3787 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3789 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3790 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3792 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3794 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3795 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3797 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
3798 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3799 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3801 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
3802 def : Pat<(or (shl GR16:$src1, CL:$amt),
3803 (srl GR16:$src2, (sub 16, CL:$amt))),
3804 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3806 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
3807 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3808 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3810 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
3811 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3812 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3814 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3815 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3817 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3819 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3820 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3822 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
3823 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3824 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3826 //===----------------------------------------------------------------------===//
3827 // EFLAGS-defining Patterns
3828 //===----------------------------------------------------------------------===//
3830 // Register-Register Addition with EFLAGS result
3831 def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
3833 (ADD8rr GR8:$src1, GR8:$src2)>;
3834 def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
3836 (ADD16rr GR16:$src1, GR16:$src2)>;
3837 def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
3839 (ADD32rr GR32:$src1, GR32:$src2)>;
3841 // Register-Memory Addition with EFLAGS result
3842 def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
3844 (ADD8rm GR8:$src1, addr:$src2)>;
3845 def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
3847 (ADD16rm GR16:$src1, addr:$src2)>;
3848 def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
3850 (ADD32rm GR32:$src1, addr:$src2)>;
3852 // Register-Integer Addition with EFLAGS result
3853 def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
3855 (ADD8ri GR8:$src1, imm:$src2)>;
3856 def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
3858 (ADD16ri GR16:$src1, imm:$src2)>;
3859 def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
3861 (ADD32ri GR32:$src1, imm:$src2)>;
3862 def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
3864 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
3865 def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
3867 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3869 // Memory-Register Addition with EFLAGS result
3870 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
3873 (ADD8mr addr:$dst, GR8:$src2)>;
3874 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
3877 (ADD16mr addr:$dst, GR16:$src2)>;
3878 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
3881 (ADD32mr addr:$dst, GR32:$src2)>;
3883 // Memory-Integer Addition with EFLAGS result
3884 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
3887 (ADD8mi addr:$dst, imm:$src2)>;
3888 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
3891 (ADD16mi addr:$dst, imm:$src2)>;
3892 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
3895 (ADD32mi addr:$dst, imm:$src2)>;
3896 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
3899 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
3900 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
3903 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
3905 // Register-Register Subtraction with EFLAGS result
3906 def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
3908 (SUB8rr GR8:$src1, GR8:$src2)>;
3909 def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
3911 (SUB16rr GR16:$src1, GR16:$src2)>;
3912 def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
3914 (SUB32rr GR32:$src1, GR32:$src2)>;
3916 // Register-Memory Subtraction with EFLAGS result
3917 def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
3919 (SUB8rm GR8:$src1, addr:$src2)>;
3920 def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
3922 (SUB16rm GR16:$src1, addr:$src2)>;
3923 def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
3925 (SUB32rm GR32:$src1, addr:$src2)>;
3927 // Register-Integer Subtraction with EFLAGS result
3928 def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
3930 (SUB8ri GR8:$src1, imm:$src2)>;
3931 def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
3933 (SUB16ri GR16:$src1, imm:$src2)>;
3934 def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
3936 (SUB32ri GR32:$src1, imm:$src2)>;
3937 def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
3939 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
3940 def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
3942 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3944 // Memory-Register Subtraction with EFLAGS result
3945 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
3948 (SUB8mr addr:$dst, GR8:$src2)>;
3949 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
3952 (SUB16mr addr:$dst, GR16:$src2)>;
3953 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
3956 (SUB32mr addr:$dst, GR32:$src2)>;
3958 // Memory-Integer Subtraction with EFLAGS result
3959 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
3962 (SUB8mi addr:$dst, imm:$src2)>;
3963 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
3966 (SUB16mi addr:$dst, imm:$src2)>;
3967 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
3970 (SUB32mi addr:$dst, imm:$src2)>;
3971 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
3974 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
3975 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
3978 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
3981 // Register-Register Signed Integer Multiply with EFLAGS result
3982 def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
3984 (IMUL16rr GR16:$src1, GR16:$src2)>;
3985 def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
3987 (IMUL32rr GR32:$src1, GR32:$src2)>;
3989 // Register-Memory Signed Integer Multiply with EFLAGS result
3990 def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
3992 (IMUL16rm GR16:$src1, addr:$src2)>;
3993 def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
3995 (IMUL32rm GR32:$src1, addr:$src2)>;
3997 // Register-Integer Signed Integer Multiply with EFLAGS result
3998 def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
4000 (IMUL16rri GR16:$src1, imm:$src2)>;
4001 def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
4003 (IMUL32rri GR32:$src1, imm:$src2)>;
4004 def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
4006 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4007 def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
4009 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4011 // Memory-Integer Signed Integer Multiply with EFLAGS result
4012 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
4014 (IMUL16rmi addr:$src1, imm:$src2)>;
4015 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
4017 (IMUL32rmi addr:$src1, imm:$src2)>;
4018 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
4020 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4021 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
4023 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4025 // Optimize multiply by 2 with EFLAGS result.
4026 let AddedComplexity = 2 in {
4027 def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
4029 (ADD16rr GR16:$src1, GR16:$src1)>;
4031 def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
4033 (ADD32rr GR32:$src1, GR32:$src1)>;
4036 // INC and DEC with EFLAGS result. Note that these do not set CF.
4037 def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
4039 def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
4042 def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
4044 def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
4048 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
4049 (INC16r GR16:$src)>, Requires<[In32BitMode]>;
4050 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
4052 (INC16m addr:$dst)>, Requires<[In32BitMode]>;
4053 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
4054 (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
4055 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
4057 (DEC16m addr:$dst)>, Requires<[In32BitMode]>;
4059 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
4060 (INC32r GR32:$src)>, Requires<[In32BitMode]>;
4061 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
4063 (INC32m addr:$dst)>, Requires<[In32BitMode]>;
4064 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
4065 (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
4066 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
4068 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
4070 //===----------------------------------------------------------------------===//
4071 // Floating Point Stack Support
4072 //===----------------------------------------------------------------------===//
4074 include "X86InstrFPStack.td"
4076 //===----------------------------------------------------------------------===//
4078 //===----------------------------------------------------------------------===//
4080 include "X86Instr64bit.td"
4082 //===----------------------------------------------------------------------===//
4083 // XMM Floating point support (requires SSE / SSE2)
4084 //===----------------------------------------------------------------------===//
4086 include "X86InstrSSE.td"
4088 //===----------------------------------------------------------------------===//
4089 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
4090 //===----------------------------------------------------------------------===//
4092 include "X86InstrMMX.td"