1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 def SDTX86BrCond : SDTypeProfile<0, 3,
31 [SDTCisVT<0, OtherVT>,
32 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
34 def SDTX86SetCC : SDTypeProfile<1, 2,
36 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
38 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
40 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
42 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
44 def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
45 def SDT_X86CallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
48 def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
50 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
52 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
54 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
56 def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
58 def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
62 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
64 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
65 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
66 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
67 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
69 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
71 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
72 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
74 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
76 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
77 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
79 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
80 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
83 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
84 [SDNPHasChain, SDNPOptInFlag]>;
86 def X86callseq_start :
87 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
88 [SDNPHasChain, SDNPOutFlag]>;
90 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
91 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
93 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
94 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
96 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
97 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
99 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
100 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
101 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
102 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
105 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
106 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
108 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
109 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
111 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
112 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
113 def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
115 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
118 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
119 [SDNPHasChain, SDNPOptInFlag]>;
121 //===----------------------------------------------------------------------===//
122 // X86 Operand Definitions.
125 // *mem - Operand definitions for the funky X86 addressing mode operands.
127 class X86MemOperand<string printMethod> : Operand<iPTR> {
128 let PrintMethod = printMethod;
129 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
132 def i8mem : X86MemOperand<"printi8mem">;
133 def i16mem : X86MemOperand<"printi16mem">;
134 def i32mem : X86MemOperand<"printi32mem">;
135 def i64mem : X86MemOperand<"printi64mem">;
136 def i128mem : X86MemOperand<"printi128mem">;
137 def f32mem : X86MemOperand<"printf32mem">;
138 def f64mem : X86MemOperand<"printf64mem">;
139 def f80mem : X86MemOperand<"printf80mem">;
140 def f128mem : X86MemOperand<"printf128mem">;
142 def lea32mem : Operand<i32> {
143 let PrintMethod = "printi32mem";
144 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
147 def SSECC : Operand<i8> {
148 let PrintMethod = "printSSECC";
151 def piclabel: Operand<i32> {
152 let PrintMethod = "printPICLabel";
155 // A couple of more descriptive operand definitions.
156 // 16-bits but only 8 bits are significant.
157 def i16i8imm : Operand<i16>;
158 // 32-bits but only 8 bits are significant.
159 def i32i8imm : Operand<i32>;
161 // Branch targets have OtherVT type.
162 def brtarget : Operand<OtherVT>;
164 //===----------------------------------------------------------------------===//
165 // X86 Complex Pattern Definitions.
168 // Define X86 specific addressing mode.
169 def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
170 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
171 [add, mul, shl, or, frameindex], []>;
173 //===----------------------------------------------------------------------===//
174 // X86 Instruction Predicate Definitions.
175 def HasMMX : Predicate<"Subtarget->hasMMX()">;
176 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
177 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
178 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
179 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
180 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
181 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
182 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
183 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
184 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
185 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
186 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
187 def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
188 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
190 //===----------------------------------------------------------------------===//
191 // X86 Instruction Format Definitions.
194 include "X86InstrFormats.td"
196 //===----------------------------------------------------------------------===//
197 // Pattern fragments...
200 // X86 specific condition code. These correspond to CondCode in
201 // X86InstrInfo.h. They must be kept in synch.
202 def X86_COND_A : PatLeaf<(i8 0)>;
203 def X86_COND_AE : PatLeaf<(i8 1)>;
204 def X86_COND_B : PatLeaf<(i8 2)>;
205 def X86_COND_BE : PatLeaf<(i8 3)>;
206 def X86_COND_E : PatLeaf<(i8 4)>;
207 def X86_COND_G : PatLeaf<(i8 5)>;
208 def X86_COND_GE : PatLeaf<(i8 6)>;
209 def X86_COND_L : PatLeaf<(i8 7)>;
210 def X86_COND_LE : PatLeaf<(i8 8)>;
211 def X86_COND_NE : PatLeaf<(i8 9)>;
212 def X86_COND_NO : PatLeaf<(i8 10)>;
213 def X86_COND_NP : PatLeaf<(i8 11)>;
214 def X86_COND_NS : PatLeaf<(i8 12)>;
215 def X86_COND_O : PatLeaf<(i8 13)>;
216 def X86_COND_P : PatLeaf<(i8 14)>;
217 def X86_COND_S : PatLeaf<(i8 15)>;
219 def i16immSExt8 : PatLeaf<(i16 imm), [{
220 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
221 // sign extended field.
222 return (int16_t)N->getValue() == (int8_t)N->getValue();
225 def i32immSExt8 : PatLeaf<(i32 imm), [{
226 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
227 // sign extended field.
228 return (int32_t)N->getValue() == (int8_t)N->getValue();
231 // Helper fragments for loads.
232 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
233 def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>;
234 def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>;
235 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
237 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
238 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
239 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
241 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
242 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
243 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
245 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
246 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
247 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
248 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
249 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
250 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
252 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
253 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
254 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
255 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
256 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
257 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
260 // An 'and' node with a single use.
261 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
262 return N->hasOneUse();
265 //===----------------------------------------------------------------------===//
266 // Instruction list...
269 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
270 // a stack adjustment and the codegen must know that they may modify the stack
271 // pointer before prolog-epilog rewriting occurs.
272 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
273 // sub / add which can clobber EFLAGS.
274 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
275 def ADJCALLSTACKDOWN : I<0, Pseudo, (outs), (ins i32imm:$amt),
277 [(X86callseq_start imm:$amt)]>;
278 def ADJCALLSTACKUP : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
280 [(X86callseq_end imm:$amt1, imm:$amt2)]>;
284 let neverHasSideEffects = 1 in
285 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
288 let neverHasSideEffects = 1, isNotDuplicable = 1 in
289 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
290 "call\t$label\n\tpop{l}\t$reg", []>;
292 //===----------------------------------------------------------------------===//
293 // Control Flow Instructions...
296 // Return instructions.
297 let isTerminator = 1, isReturn = 1, isBarrier = 1,
298 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
299 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
301 [/*(X86retflag 0)*/ /*FIXME: Disabled: rdar://5791600*/]>;
302 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
304 [(X86retflag imm:$amt)]>;
307 // All branches are RawFrm, Void, Branch, and Terminators
308 let isBranch = 1, isTerminator = 1 in
309 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
310 I<opcode, RawFrm, (outs), ins, asm, pattern>;
312 let isBranch = 1, isBarrier = 1 in
313 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
316 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
317 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
318 [(brind GR32:$dst)]>;
319 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
320 [(brind (loadi32 addr:$dst))]>;
323 // Conditional branches
324 let Uses = [EFLAGS] in {
325 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
326 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
327 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
328 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
329 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
330 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
331 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
332 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
333 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
334 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
335 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
336 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
338 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
339 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
340 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
341 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
342 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
343 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
344 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
345 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
347 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
348 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
349 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
350 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
351 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
352 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
353 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
354 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
355 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
356 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
357 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
358 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
361 //===----------------------------------------------------------------------===//
362 // Call Instructions...
365 // All calls clobber the non-callee saved registers...
366 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
367 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
368 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, EFLAGS] in {
369 def CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:$dst,variable_ops),
370 "call\t${dst:call}", []>;
371 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
372 "call\t{*}$dst", [(X86call GR32:$dst)]>;
373 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
374 "call\t{*}$dst", []>;
379 def TAILCALL : I<0, Pseudo, (outs), (ins),
383 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
384 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops),
385 "#TC_RETURN $dst $offset",
388 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
389 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops),
390 "#TC_RETURN $dst $offset",
393 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
395 def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAILCALL",
397 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
398 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
400 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
401 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
402 "jmp\t{*}$dst # TAILCALL", []>;
404 //===----------------------------------------------------------------------===//
405 // Miscellaneous Instructions...
407 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
408 def LEAVE : I<0xC9, RawFrm,
409 (outs), (ins), "leave", []>;
411 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
413 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
416 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
419 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
420 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
421 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
422 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
424 let isTwoAddress = 1 in // GR32 = bswap GR32
425 def BSWAP32r : I<0xC8, AddRegFrm,
426 (outs GR32:$dst), (ins GR32:$src),
428 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
431 // Bit scan instructions.
432 let Defs = [EFLAGS] in {
433 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
434 "bsf{w}\t{$src, $dst|$dst, $src}",
435 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
436 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
437 "bsf{w}\t{$src, $dst|$dst, $src}",
438 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
439 (implicit EFLAGS)]>, TB;
440 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
441 "bsf{l}\t{$src, $dst|$dst, $src}",
442 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
443 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
444 "bsf{l}\t{$src, $dst|$dst, $src}",
445 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
446 (implicit EFLAGS)]>, TB;
448 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
449 "bsr{w}\t{$src, $dst|$dst, $src}",
450 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
451 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
452 "bsr{w}\t{$src, $dst|$dst, $src}",
453 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
454 (implicit EFLAGS)]>, TB;
455 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
456 "bsr{l}\t{$src, $dst|$dst, $src}",
457 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
458 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
459 "bsr{l}\t{$src, $dst|$dst, $src}",
460 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
461 (implicit EFLAGS)]>, TB;
464 let neverHasSideEffects = 1 in
465 def LEA16r : I<0x8D, MRMSrcMem,
466 (outs GR16:$dst), (ins i32mem:$src),
467 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
468 let isReMaterializable = 1 in
469 def LEA32r : I<0x8D, MRMSrcMem,
470 (outs GR32:$dst), (ins lea32mem:$src),
471 "lea{l}\t{$src|$dst}, {$dst|$src}",
472 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
474 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
475 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
476 [(X86rep_movs i8)]>, REP;
477 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
478 [(X86rep_movs i16)]>, REP, OpSize;
479 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
480 [(X86rep_movs i32)]>, REP;
483 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
484 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
485 [(X86rep_stos i8)]>, REP;
486 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
487 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
488 [(X86rep_stos i16)]>, REP, OpSize;
489 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
490 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
491 [(X86rep_stos i32)]>, REP;
493 let Defs = [RAX, RDX] in
494 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
497 let isBarrier = 1, hasCtrlDep = 1 in {
498 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
501 //===----------------------------------------------------------------------===//
502 // Input/Output Instructions...
504 let Defs = [AL], Uses = [DX] in
505 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
506 "in{b}\t{%dx, %al|%AL, %DX}", []>;
507 let Defs = [AX], Uses = [DX] in
508 def IN16rr : I<0xED, RawFrm, (outs), (ins),
509 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
510 let Defs = [EAX], Uses = [DX] in
511 def IN32rr : I<0xED, RawFrm, (outs), (ins),
512 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
515 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
516 "in{b}\t{$port, %al|%AL, $port}", []>;
518 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
519 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
521 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
522 "in{l}\t{$port, %eax|%EAX, $port}", []>;
524 let Uses = [DX, AL] in
525 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
526 "out{b}\t{%al, %dx|%DX, %AL}", []>;
527 let Uses = [DX, AX] in
528 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
529 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
530 let Uses = [DX, EAX] in
531 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
532 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
535 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
536 "out{b}\t{%al, $port|$port, %AL}", []>;
538 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
539 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
541 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
542 "out{l}\t{%eax, $port|$port, %EAX}", []>;
544 //===----------------------------------------------------------------------===//
545 // Move Instructions...
547 let neverHasSideEffects = 1 in {
548 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
549 "mov{b}\t{$src, $dst|$dst, $src}", []>;
550 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
551 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
552 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
553 "mov{l}\t{$src, $dst|$dst, $src}", []>;
555 let isReMaterializable = 1 in {
556 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
557 "mov{b}\t{$src, $dst|$dst, $src}",
558 [(set GR8:$dst, imm:$src)]>;
559 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
560 "mov{w}\t{$src, $dst|$dst, $src}",
561 [(set GR16:$dst, imm:$src)]>, OpSize;
562 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
563 "mov{l}\t{$src, $dst|$dst, $src}",
564 [(set GR32:$dst, imm:$src)]>;
566 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
567 "mov{b}\t{$src, $dst|$dst, $src}",
568 [(store (i8 imm:$src), addr:$dst)]>;
569 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
570 "mov{w}\t{$src, $dst|$dst, $src}",
571 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
572 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
573 "mov{l}\t{$src, $dst|$dst, $src}",
574 [(store (i32 imm:$src), addr:$dst)]>;
576 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
577 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
578 "mov{b}\t{$src, $dst|$dst, $src}",
579 [(set GR8:$dst, (load addr:$src))]>;
580 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
581 "mov{w}\t{$src, $dst|$dst, $src}",
582 [(set GR16:$dst, (load addr:$src))]>, OpSize;
583 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
584 "mov{l}\t{$src, $dst|$dst, $src}",
585 [(set GR32:$dst, (load addr:$src))]>;
588 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
589 "mov{b}\t{$src, $dst|$dst, $src}",
590 [(store GR8:$src, addr:$dst)]>;
591 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
592 "mov{w}\t{$src, $dst|$dst, $src}",
593 [(store GR16:$src, addr:$dst)]>, OpSize;
594 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
595 "mov{l}\t{$src, $dst|$dst, $src}",
596 [(store GR32:$src, addr:$dst)]>;
598 //===----------------------------------------------------------------------===//
599 // Fixed-Register Multiplication and Division Instructions...
602 // Extra precision multiplication
603 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
604 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
605 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
606 // This probably ought to be moved to a def : Pat<> if the
607 // syntax can be accepted.
608 [(set AL, (mul AL, GR8:$src))]>; // AL,AH = AL*GR8
609 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
610 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>,
611 OpSize; // AX,DX = AX*GR16
612 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
613 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l}\t$src", []>;
614 // EAX,EDX = EAX*GR32
615 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
616 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
618 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
619 // This probably ought to be moved to a def : Pat<> if the
620 // syntax can be accepted.
621 [(set AL, (mul AL, (loadi8 addr:$src)))]>; // AL,AH = AL*[mem8]
622 let mayLoad = 1, neverHasSideEffects = 1 in {
623 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
624 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
625 "mul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
626 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
627 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
628 "mul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
631 let neverHasSideEffects = 1 in {
632 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
633 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
635 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
636 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
637 OpSize; // AX,DX = AX*GR16
638 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
639 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
640 // EAX,EDX = EAX*GR32
642 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
643 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
644 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
645 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
646 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
647 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
648 let Defs = [EAX,EDX], Uses = [EAX] in
649 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
650 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
653 // unsigned division/remainder
654 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
655 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
657 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
658 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
659 "div{w}\t$src", []>, OpSize;
660 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
661 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
664 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
665 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
667 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
668 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
669 "div{w}\t$src", []>, OpSize;
670 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
671 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
675 // Signed division/remainder.
676 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
677 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
678 "idiv{b}\t$src", []>;
679 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
680 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
681 "idiv{w}\t$src", []>, OpSize;
682 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
683 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
684 "idiv{l}\t$src", []>;
685 let mayLoad = 1, mayLoad = 1 in {
686 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
687 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
688 "idiv{b}\t$src", []>;
689 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
690 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
691 "idiv{w}\t$src", []>, OpSize;
692 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
693 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
694 "idiv{l}\t$src", []>;
696 } // neverHasSideEffects
698 //===----------------------------------------------------------------------===//
699 // Two address Instructions.
701 let isTwoAddress = 1 in {
704 let Uses = [EFLAGS] in {
705 let isCommutable = 1 in {
706 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
707 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
708 "cmovb\t{$src2, $dst|$dst, $src2}",
709 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
710 X86_COND_B, EFLAGS))]>,
712 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
713 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
714 "cmovb\t{$src2, $dst|$dst, $src2}",
715 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
716 X86_COND_B, EFLAGS))]>,
719 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
720 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
721 "cmovae\t{$src2, $dst|$dst, $src2}",
722 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
723 X86_COND_AE, EFLAGS))]>,
725 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
726 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
727 "cmovae\t{$src2, $dst|$dst, $src2}",
728 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
729 X86_COND_AE, EFLAGS))]>,
731 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
732 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
733 "cmove\t{$src2, $dst|$dst, $src2}",
734 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
735 X86_COND_E, EFLAGS))]>,
737 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
738 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
739 "cmove\t{$src2, $dst|$dst, $src2}",
740 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
741 X86_COND_E, EFLAGS))]>,
743 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
744 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
745 "cmovne\t{$src2, $dst|$dst, $src2}",
746 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
747 X86_COND_NE, EFLAGS))]>,
749 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
750 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
751 "cmovne\t{$src2, $dst|$dst, $src2}",
752 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
753 X86_COND_NE, EFLAGS))]>,
755 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
756 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
757 "cmovbe\t{$src2, $dst|$dst, $src2}",
758 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
759 X86_COND_BE, EFLAGS))]>,
761 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
762 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
763 "cmovbe\t{$src2, $dst|$dst, $src2}",
764 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
765 X86_COND_BE, EFLAGS))]>,
767 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
768 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
769 "cmova\t{$src2, $dst|$dst, $src2}",
770 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
771 X86_COND_A, EFLAGS))]>,
773 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
774 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
775 "cmova\t{$src2, $dst|$dst, $src2}",
776 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
777 X86_COND_A, EFLAGS))]>,
779 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
780 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
781 "cmovl\t{$src2, $dst|$dst, $src2}",
782 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
783 X86_COND_L, EFLAGS))]>,
785 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
786 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
787 "cmovl\t{$src2, $dst|$dst, $src2}",
788 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
789 X86_COND_L, EFLAGS))]>,
791 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
792 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
793 "cmovge\t{$src2, $dst|$dst, $src2}",
794 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
795 X86_COND_GE, EFLAGS))]>,
797 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
798 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
799 "cmovge\t{$src2, $dst|$dst, $src2}",
800 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
801 X86_COND_GE, EFLAGS))]>,
803 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
804 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
805 "cmovle\t{$src2, $dst|$dst, $src2}",
806 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
807 X86_COND_LE, EFLAGS))]>,
809 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
810 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
811 "cmovle\t{$src2, $dst|$dst, $src2}",
812 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
813 X86_COND_LE, EFLAGS))]>,
815 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
816 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
817 "cmovg\t{$src2, $dst|$dst, $src2}",
818 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
819 X86_COND_G, EFLAGS))]>,
821 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
822 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
823 "cmovg\t{$src2, $dst|$dst, $src2}",
824 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
825 X86_COND_G, EFLAGS))]>,
827 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
828 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
829 "cmovs\t{$src2, $dst|$dst, $src2}",
830 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
831 X86_COND_S, EFLAGS))]>,
833 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
834 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
835 "cmovs\t{$src2, $dst|$dst, $src2}",
836 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
837 X86_COND_S, EFLAGS))]>,
839 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
840 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
841 "cmovns\t{$src2, $dst|$dst, $src2}",
842 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
843 X86_COND_NS, EFLAGS))]>,
845 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
846 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
847 "cmovns\t{$src2, $dst|$dst, $src2}",
848 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
849 X86_COND_NS, EFLAGS))]>,
851 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
852 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
853 "cmovp\t{$src2, $dst|$dst, $src2}",
854 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
855 X86_COND_P, EFLAGS))]>,
857 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
858 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
859 "cmovp\t{$src2, $dst|$dst, $src2}",
860 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
861 X86_COND_P, EFLAGS))]>,
863 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
864 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
865 "cmovnp\t{$src2, $dst|$dst, $src2}",
866 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
867 X86_COND_NP, EFLAGS))]>,
869 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
870 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
871 "cmovnp\t{$src2, $dst|$dst, $src2}",
872 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
873 X86_COND_NP, EFLAGS))]>,
875 } // isCommutable = 1
877 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
878 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
879 "cmovnp\t{$src2, $dst|$dst, $src2}",
880 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
881 X86_COND_NP, EFLAGS))]>,
884 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
885 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
886 "cmovb\t{$src2, $dst|$dst, $src2}",
887 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
888 X86_COND_B, EFLAGS))]>,
890 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
891 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
892 "cmovb\t{$src2, $dst|$dst, $src2}",
893 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
894 X86_COND_B, EFLAGS))]>,
896 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
897 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
898 "cmovae\t{$src2, $dst|$dst, $src2}",
899 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
900 X86_COND_AE, EFLAGS))]>,
902 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
903 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
904 "cmovae\t{$src2, $dst|$dst, $src2}",
905 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
906 X86_COND_AE, EFLAGS))]>,
908 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
909 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
910 "cmove\t{$src2, $dst|$dst, $src2}",
911 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
912 X86_COND_E, EFLAGS))]>,
914 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
915 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
916 "cmove\t{$src2, $dst|$dst, $src2}",
917 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
918 X86_COND_E, EFLAGS))]>,
920 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
921 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
922 "cmovne\t{$src2, $dst|$dst, $src2}",
923 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
924 X86_COND_NE, EFLAGS))]>,
926 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
927 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
928 "cmovne\t{$src2, $dst|$dst, $src2}",
929 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
930 X86_COND_NE, EFLAGS))]>,
932 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
933 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
934 "cmovbe\t{$src2, $dst|$dst, $src2}",
935 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
936 X86_COND_BE, EFLAGS))]>,
938 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
939 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
940 "cmovbe\t{$src2, $dst|$dst, $src2}",
941 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
942 X86_COND_BE, EFLAGS))]>,
944 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
945 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
946 "cmova\t{$src2, $dst|$dst, $src2}",
947 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
948 X86_COND_A, EFLAGS))]>,
950 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
951 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
952 "cmova\t{$src2, $dst|$dst, $src2}",
953 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
954 X86_COND_A, EFLAGS))]>,
956 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
957 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
958 "cmovl\t{$src2, $dst|$dst, $src2}",
959 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
960 X86_COND_L, EFLAGS))]>,
962 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
963 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
964 "cmovl\t{$src2, $dst|$dst, $src2}",
965 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
966 X86_COND_L, EFLAGS))]>,
968 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
969 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
970 "cmovge\t{$src2, $dst|$dst, $src2}",
971 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
972 X86_COND_GE, EFLAGS))]>,
974 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
975 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
976 "cmovge\t{$src2, $dst|$dst, $src2}",
977 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
978 X86_COND_GE, EFLAGS))]>,
980 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
981 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
982 "cmovle\t{$src2, $dst|$dst, $src2}",
983 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
984 X86_COND_LE, EFLAGS))]>,
986 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
987 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
988 "cmovle\t{$src2, $dst|$dst, $src2}",
989 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
990 X86_COND_LE, EFLAGS))]>,
992 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
993 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
994 "cmovg\t{$src2, $dst|$dst, $src2}",
995 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
996 X86_COND_G, EFLAGS))]>,
998 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
999 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1000 "cmovg\t{$src2, $dst|$dst, $src2}",
1001 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1002 X86_COND_G, EFLAGS))]>,
1004 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1005 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1006 "cmovs\t{$src2, $dst|$dst, $src2}",
1007 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1008 X86_COND_S, EFLAGS))]>,
1010 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1011 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1012 "cmovs\t{$src2, $dst|$dst, $src2}",
1013 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1014 X86_COND_S, EFLAGS))]>,
1016 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1017 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1018 "cmovns\t{$src2, $dst|$dst, $src2}",
1019 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1020 X86_COND_NS, EFLAGS))]>,
1022 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1023 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1024 "cmovns\t{$src2, $dst|$dst, $src2}",
1025 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1026 X86_COND_NS, EFLAGS))]>,
1028 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1029 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1030 "cmovp\t{$src2, $dst|$dst, $src2}",
1031 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1032 X86_COND_P, EFLAGS))]>,
1034 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1035 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1036 "cmovp\t{$src2, $dst|$dst, $src2}",
1037 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1038 X86_COND_P, EFLAGS))]>,
1040 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1041 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1042 "cmovnp\t{$src2, $dst|$dst, $src2}",
1043 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1044 X86_COND_NP, EFLAGS))]>,
1046 } // Uses = [EFLAGS]
1049 // unary instructions
1050 let CodeSize = 2 in {
1051 let Defs = [EFLAGS] in {
1052 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1053 [(set GR8:$dst, (ineg GR8:$src))]>;
1054 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1055 [(set GR16:$dst, (ineg GR16:$src))]>, OpSize;
1056 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1057 [(set GR32:$dst, (ineg GR32:$src))]>;
1058 let isTwoAddress = 0 in {
1059 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1060 [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
1061 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1062 [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1063 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1064 [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
1067 } // Defs = [EFLAGS]
1069 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1070 [(set GR8:$dst, (not GR8:$src))]>;
1071 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1072 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1073 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1074 [(set GR32:$dst, (not GR32:$src))]>;
1075 let isTwoAddress = 0 in {
1076 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1077 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1078 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1079 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1080 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1081 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1085 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1086 let Defs = [EFLAGS] in {
1088 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1089 [(set GR8:$dst, (add GR8:$src, 1))]>;
1090 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1091 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1092 [(set GR16:$dst, (add GR16:$src, 1))]>,
1093 OpSize, Requires<[In32BitMode]>;
1094 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1095 [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>;
1097 let isTwoAddress = 0, CodeSize = 2 in {
1098 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1099 [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
1100 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1101 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>,
1102 OpSize, Requires<[In32BitMode]>;
1103 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1104 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>,
1105 Requires<[In32BitMode]>;
1109 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1110 [(set GR8:$dst, (add GR8:$src, -1))]>;
1111 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1112 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1113 [(set GR16:$dst, (add GR16:$src, -1))]>,
1114 OpSize, Requires<[In32BitMode]>;
1115 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1116 [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>;
1119 let isTwoAddress = 0, CodeSize = 2 in {
1120 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1121 [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
1122 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1123 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>,
1124 OpSize, Requires<[In32BitMode]>;
1125 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1126 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>,
1127 Requires<[In32BitMode]>;
1129 } // Defs = [EFLAGS]
1131 // Logical operators...
1132 let Defs = [EFLAGS] in {
1133 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1134 def AND8rr : I<0x20, MRMDestReg,
1135 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1136 "and{b}\t{$src2, $dst|$dst, $src2}",
1137 [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>;
1138 def AND16rr : I<0x21, MRMDestReg,
1139 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1140 "and{w}\t{$src2, $dst|$dst, $src2}",
1141 [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize;
1142 def AND32rr : I<0x21, MRMDestReg,
1143 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1144 "and{l}\t{$src2, $dst|$dst, $src2}",
1145 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
1148 def AND8rm : I<0x22, MRMSrcMem,
1149 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1150 "and{b}\t{$src2, $dst|$dst, $src2}",
1151 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>;
1152 def AND16rm : I<0x23, MRMSrcMem,
1153 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1154 "and{w}\t{$src2, $dst|$dst, $src2}",
1155 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize;
1156 def AND32rm : I<0x23, MRMSrcMem,
1157 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1158 "and{l}\t{$src2, $dst|$dst, $src2}",
1159 [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>;
1161 def AND8ri : Ii8<0x80, MRM4r,
1162 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1163 "and{b}\t{$src2, $dst|$dst, $src2}",
1164 [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>;
1165 def AND16ri : Ii16<0x81, MRM4r,
1166 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1167 "and{w}\t{$src2, $dst|$dst, $src2}",
1168 [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize;
1169 def AND32ri : Ii32<0x81, MRM4r,
1170 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1171 "and{l}\t{$src2, $dst|$dst, $src2}",
1172 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
1173 def AND16ri8 : Ii8<0x83, MRM4r,
1174 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1175 "and{w}\t{$src2, $dst|$dst, $src2}",
1176 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>,
1178 def AND32ri8 : Ii8<0x83, MRM4r,
1179 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1180 "and{l}\t{$src2, $dst|$dst, $src2}",
1181 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>;
1183 let isTwoAddress = 0 in {
1184 def AND8mr : I<0x20, MRMDestMem,
1185 (outs), (ins i8mem :$dst, GR8 :$src),
1186 "and{b}\t{$src, $dst|$dst, $src}",
1187 [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>;
1188 def AND16mr : I<0x21, MRMDestMem,
1189 (outs), (ins i16mem:$dst, GR16:$src),
1190 "and{w}\t{$src, $dst|$dst, $src}",
1191 [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>,
1193 def AND32mr : I<0x21, MRMDestMem,
1194 (outs), (ins i32mem:$dst, GR32:$src),
1195 "and{l}\t{$src, $dst|$dst, $src}",
1196 [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>;
1197 def AND8mi : Ii8<0x80, MRM4m,
1198 (outs), (ins i8mem :$dst, i8imm :$src),
1199 "and{b}\t{$src, $dst|$dst, $src}",
1200 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1201 def AND16mi : Ii16<0x81, MRM4m,
1202 (outs), (ins i16mem:$dst, i16imm:$src),
1203 "and{w}\t{$src, $dst|$dst, $src}",
1204 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1206 def AND32mi : Ii32<0x81, MRM4m,
1207 (outs), (ins i32mem:$dst, i32imm:$src),
1208 "and{l}\t{$src, $dst|$dst, $src}",
1209 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1210 def AND16mi8 : Ii8<0x83, MRM4m,
1211 (outs), (ins i16mem:$dst, i16i8imm :$src),
1212 "and{w}\t{$src, $dst|$dst, $src}",
1213 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1215 def AND32mi8 : Ii8<0x83, MRM4m,
1216 (outs), (ins i32mem:$dst, i32i8imm :$src),
1217 "and{l}\t{$src, $dst|$dst, $src}",
1218 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1222 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1223 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1224 "or{b}\t{$src2, $dst|$dst, $src2}",
1225 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
1226 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1227 "or{w}\t{$src2, $dst|$dst, $src2}",
1228 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize;
1229 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1230 "or{l}\t{$src2, $dst|$dst, $src2}",
1231 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
1233 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1234 "or{b}\t{$src2, $dst|$dst, $src2}",
1235 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
1236 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1237 "or{w}\t{$src2, $dst|$dst, $src2}",
1238 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize;
1239 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1240 "or{l}\t{$src2, $dst|$dst, $src2}",
1241 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>;
1243 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1244 "or{b}\t{$src2, $dst|$dst, $src2}",
1245 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
1246 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1247 "or{w}\t{$src2, $dst|$dst, $src2}",
1248 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize;
1249 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1250 "or{l}\t{$src2, $dst|$dst, $src2}",
1251 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
1253 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1254 "or{w}\t{$src2, $dst|$dst, $src2}",
1255 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1256 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1257 "or{l}\t{$src2, $dst|$dst, $src2}",
1258 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>;
1259 let isTwoAddress = 0 in {
1260 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1261 "or{b}\t{$src, $dst|$dst, $src}",
1262 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
1263 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1264 "or{w}\t{$src, $dst|$dst, $src}",
1265 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize;
1266 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1267 "or{l}\t{$src, $dst|$dst, $src}",
1268 [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>;
1269 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1270 "or{b}\t{$src, $dst|$dst, $src}",
1271 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1272 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1273 "or{w}\t{$src, $dst|$dst, $src}",
1274 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1276 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1277 "or{l}\t{$src, $dst|$dst, $src}",
1278 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1279 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1280 "or{w}\t{$src, $dst|$dst, $src}",
1281 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1283 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1284 "or{l}\t{$src, $dst|$dst, $src}",
1285 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1289 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1290 def XOR8rr : I<0x30, MRMDestReg,
1291 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1292 "xor{b}\t{$src2, $dst|$dst, $src2}",
1293 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>;
1294 def XOR16rr : I<0x31, MRMDestReg,
1295 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1296 "xor{w}\t{$src2, $dst|$dst, $src2}",
1297 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize;
1298 def XOR32rr : I<0x31, MRMDestReg,
1299 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1300 "xor{l}\t{$src2, $dst|$dst, $src2}",
1301 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
1304 def XOR8rm : I<0x32, MRMSrcMem ,
1305 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1306 "xor{b}\t{$src2, $dst|$dst, $src2}",
1307 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>;
1308 def XOR16rm : I<0x33, MRMSrcMem ,
1309 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1310 "xor{w}\t{$src2, $dst|$dst, $src2}",
1311 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>, OpSize;
1312 def XOR32rm : I<0x33, MRMSrcMem ,
1313 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1314 "xor{l}\t{$src2, $dst|$dst, $src2}",
1315 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>;
1317 def XOR8ri : Ii8<0x80, MRM6r,
1318 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1319 "xor{b}\t{$src2, $dst|$dst, $src2}",
1320 [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>;
1321 def XOR16ri : Ii16<0x81, MRM6r,
1322 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1323 "xor{w}\t{$src2, $dst|$dst, $src2}",
1324 [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize;
1325 def XOR32ri : Ii32<0x81, MRM6r,
1326 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1327 "xor{l}\t{$src2, $dst|$dst, $src2}",
1328 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
1329 def XOR16ri8 : Ii8<0x83, MRM6r,
1330 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1331 "xor{w}\t{$src2, $dst|$dst, $src2}",
1332 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>,
1334 def XOR32ri8 : Ii8<0x83, MRM6r,
1335 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1336 "xor{l}\t{$src2, $dst|$dst, $src2}",
1337 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>;
1338 let isTwoAddress = 0 in {
1339 def XOR8mr : I<0x30, MRMDestMem,
1340 (outs), (ins i8mem :$dst, GR8 :$src),
1341 "xor{b}\t{$src, $dst|$dst, $src}",
1342 [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>;
1343 def XOR16mr : I<0x31, MRMDestMem,
1344 (outs), (ins i16mem:$dst, GR16:$src),
1345 "xor{w}\t{$src, $dst|$dst, $src}",
1346 [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>,
1348 def XOR32mr : I<0x31, MRMDestMem,
1349 (outs), (ins i32mem:$dst, GR32:$src),
1350 "xor{l}\t{$src, $dst|$dst, $src}",
1351 [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>;
1352 def XOR8mi : Ii8<0x80, MRM6m,
1353 (outs), (ins i8mem :$dst, i8imm :$src),
1354 "xor{b}\t{$src, $dst|$dst, $src}",
1355 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1356 def XOR16mi : Ii16<0x81, MRM6m,
1357 (outs), (ins i16mem:$dst, i16imm:$src),
1358 "xor{w}\t{$src, $dst|$dst, $src}",
1359 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1361 def XOR32mi : Ii32<0x81, MRM6m,
1362 (outs), (ins i32mem:$dst, i32imm:$src),
1363 "xor{l}\t{$src, $dst|$dst, $src}",
1364 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1365 def XOR16mi8 : Ii8<0x83, MRM6m,
1366 (outs), (ins i16mem:$dst, i16i8imm :$src),
1367 "xor{w}\t{$src, $dst|$dst, $src}",
1368 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1370 def XOR32mi8 : Ii8<0x83, MRM6m,
1371 (outs), (ins i32mem:$dst, i32i8imm :$src),
1372 "xor{l}\t{$src, $dst|$dst, $src}",
1373 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1375 } // Defs = [EFLAGS]
1377 // Shift instructions
1378 let Defs = [EFLAGS] in {
1379 let Uses = [CL] in {
1380 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1381 "shl{b}\t{%cl, $dst|$dst, %CL}",
1382 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1383 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1384 "shl{w}\t{%cl, $dst|$dst, %CL}",
1385 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1386 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1387 "shl{l}\t{%cl, $dst|$dst, %CL}",
1388 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1391 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1392 "shl{b}\t{$src2, $dst|$dst, $src2}",
1393 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1394 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1395 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1396 "shl{w}\t{$src2, $dst|$dst, $src2}",
1397 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1398 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1399 "shl{l}\t{$src2, $dst|$dst, $src2}",
1400 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1401 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1405 let isTwoAddress = 0 in {
1406 let Uses = [CL] in {
1407 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1408 "shl{b}\t{%cl, $dst|$dst, %CL}",
1409 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1410 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1411 "shl{w}\t{%cl, $dst|$dst, %CL}",
1412 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1413 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1414 "shl{l}\t{%cl, $dst|$dst, %CL}",
1415 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1417 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1418 "shl{b}\t{$src, $dst|$dst, $src}",
1419 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1420 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1421 "shl{w}\t{$src, $dst|$dst, $src}",
1422 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1424 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1425 "shl{l}\t{$src, $dst|$dst, $src}",
1426 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1429 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1431 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1432 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1434 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1436 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1438 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1441 let Uses = [CL] in {
1442 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1443 "shr{b}\t{%cl, $dst|$dst, %CL}",
1444 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1445 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1446 "shr{w}\t{%cl, $dst|$dst, %CL}",
1447 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1448 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1449 "shr{l}\t{%cl, $dst|$dst, %CL}",
1450 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1453 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1454 "shr{b}\t{$src2, $dst|$dst, $src2}",
1455 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1456 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1457 "shr{w}\t{$src2, $dst|$dst, $src2}",
1458 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1459 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1460 "shr{l}\t{$src2, $dst|$dst, $src2}",
1461 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1464 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1466 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1467 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1469 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1470 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1472 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1474 let isTwoAddress = 0 in {
1475 let Uses = [CL] in {
1476 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1477 "shr{b}\t{%cl, $dst|$dst, %CL}",
1478 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1479 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1480 "shr{w}\t{%cl, $dst|$dst, %CL}",
1481 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1483 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1484 "shr{l}\t{%cl, $dst|$dst, %CL}",
1485 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1487 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1488 "shr{b}\t{$src, $dst|$dst, $src}",
1489 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1490 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1491 "shr{w}\t{$src, $dst|$dst, $src}",
1492 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1494 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1495 "shr{l}\t{$src, $dst|$dst, $src}",
1496 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1499 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1501 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1502 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1504 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1505 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1507 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1510 let Uses = [CL] in {
1511 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1512 "sar{b}\t{%cl, $dst|$dst, %CL}",
1513 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1514 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1515 "sar{w}\t{%cl, $dst|$dst, %CL}",
1516 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1517 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1518 "sar{l}\t{%cl, $dst|$dst, %CL}",
1519 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1522 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1523 "sar{b}\t{$src2, $dst|$dst, $src2}",
1524 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1525 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1526 "sar{w}\t{$src2, $dst|$dst, $src2}",
1527 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1529 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1530 "sar{l}\t{$src2, $dst|$dst, $src2}",
1531 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1534 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1536 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1537 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1539 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1540 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1542 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1544 let isTwoAddress = 0 in {
1545 let Uses = [CL] in {
1546 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1547 "sar{b}\t{%cl, $dst|$dst, %CL}",
1548 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
1549 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1550 "sar{w}\t{%cl, $dst|$dst, %CL}",
1551 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1552 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1553 "sar{l}\t{%cl, $dst|$dst, %CL}",
1554 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1556 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1557 "sar{b}\t{$src, $dst|$dst, $src}",
1558 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1559 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1560 "sar{w}\t{$src, $dst|$dst, $src}",
1561 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1563 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1564 "sar{l}\t{$src, $dst|$dst, $src}",
1565 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1568 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1570 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1571 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1573 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1575 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
1577 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1580 // Rotate instructions
1581 // FIXME: provide shorter instructions when imm8 == 1
1582 let Uses = [CL] in {
1583 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
1584 "rol{b}\t{%cl, $dst|$dst, %CL}",
1585 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
1586 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
1587 "rol{w}\t{%cl, $dst|$dst, %CL}",
1588 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
1589 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
1590 "rol{l}\t{%cl, $dst|$dst, %CL}",
1591 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
1594 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1595 "rol{b}\t{$src2, $dst|$dst, $src2}",
1596 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1597 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1598 "rol{w}\t{$src2, $dst|$dst, $src2}",
1599 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1600 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1601 "rol{l}\t{$src2, $dst|$dst, $src2}",
1602 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1605 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1607 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1608 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
1610 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1611 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1613 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1615 let isTwoAddress = 0 in {
1616 let Uses = [CL] in {
1617 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
1618 "rol{b}\t{%cl, $dst|$dst, %CL}",
1619 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
1620 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
1621 "rol{w}\t{%cl, $dst|$dst, %CL}",
1622 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1623 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
1624 "rol{l}\t{%cl, $dst|$dst, %CL}",
1625 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
1627 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
1628 "rol{b}\t{$src, $dst|$dst, $src}",
1629 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1630 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
1631 "rol{w}\t{$src, $dst|$dst, $src}",
1632 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1634 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
1635 "rol{l}\t{$src, $dst|$dst, $src}",
1636 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1639 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
1641 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1642 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
1644 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1646 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
1648 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1651 let Uses = [CL] in {
1652 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
1653 "ror{b}\t{%cl, $dst|$dst, %CL}",
1654 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
1655 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
1656 "ror{w}\t{%cl, $dst|$dst, %CL}",
1657 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
1658 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
1659 "ror{l}\t{%cl, $dst|$dst, %CL}",
1660 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
1663 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1664 "ror{b}\t{$src2, $dst|$dst, $src2}",
1665 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
1666 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1667 "ror{w}\t{$src2, $dst|$dst, $src2}",
1668 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1669 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1670 "ror{l}\t{$src2, $dst|$dst, $src2}",
1671 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
1674 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1676 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
1677 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
1679 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
1680 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
1682 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
1684 let isTwoAddress = 0 in {
1685 let Uses = [CL] in {
1686 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
1687 "ror{b}\t{%cl, $dst|$dst, %CL}",
1688 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
1689 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
1690 "ror{w}\t{%cl, $dst|$dst, %CL}",
1691 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1692 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
1693 "ror{l}\t{%cl, $dst|$dst, %CL}",
1694 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
1696 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1697 "ror{b}\t{$src, $dst|$dst, $src}",
1698 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1699 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
1700 "ror{w}\t{$src, $dst|$dst, $src}",
1701 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1703 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
1704 "ror{l}\t{$src, $dst|$dst, $src}",
1705 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1708 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
1710 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1711 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
1713 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1715 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
1717 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1722 // Double shift instructions (generalizations of rotate)
1723 let Uses = [CL] in {
1724 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1725 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1726 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
1727 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1728 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1729 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
1730 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1731 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1732 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
1734 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1735 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1736 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
1740 let isCommutable = 1 in { // These instructions commute to each other.
1741 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
1742 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1743 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1744 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
1747 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
1748 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1749 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1750 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
1753 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
1754 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1755 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1756 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
1759 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
1760 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1761 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1762 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
1767 let isTwoAddress = 0 in {
1768 let Uses = [CL] in {
1769 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1770 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1771 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
1773 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1774 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1775 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
1778 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
1779 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1780 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1781 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
1782 (i8 imm:$src3)), addr:$dst)]>,
1784 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
1785 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1786 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1787 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
1788 (i8 imm:$src3)), addr:$dst)]>,
1791 let Uses = [CL] in {
1792 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1793 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1794 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
1795 addr:$dst)]>, TB, OpSize;
1796 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1797 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1798 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
1799 addr:$dst)]>, TB, OpSize;
1801 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
1802 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1803 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1804 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
1805 (i8 imm:$src3)), addr:$dst)]>,
1807 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
1808 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1809 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1810 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
1811 (i8 imm:$src3)), addr:$dst)]>,
1814 } // Defs = [EFLAGS]
1818 let Defs = [EFLAGS] in {
1819 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1820 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
1821 (ins GR8 :$src1, GR8 :$src2),
1822 "add{b}\t{$src2, $dst|$dst, $src2}",
1823 [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>;
1824 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1825 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
1826 (ins GR16:$src1, GR16:$src2),
1827 "add{w}\t{$src2, $dst|$dst, $src2}",
1828 [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize;
1829 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
1830 (ins GR32:$src1, GR32:$src2),
1831 "add{l}\t{$src2, $dst|$dst, $src2}",
1832 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
1833 } // end isConvertibleToThreeAddress
1834 } // end isCommutable
1835 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
1836 (ins GR8 :$src1, i8mem :$src2),
1837 "add{b}\t{$src2, $dst|$dst, $src2}",
1838 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>;
1839 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
1840 (ins GR16:$src1, i16mem:$src2),
1841 "add{w}\t{$src2, $dst|$dst, $src2}",
1842 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>,OpSize;
1843 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
1844 (ins GR32:$src1, i32mem:$src2),
1845 "add{l}\t{$src2, $dst|$dst, $src2}",
1846 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>;
1848 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1849 "add{b}\t{$src2, $dst|$dst, $src2}",
1850 [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>;
1852 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1853 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
1854 (ins GR16:$src1, i16imm:$src2),
1855 "add{w}\t{$src2, $dst|$dst, $src2}",
1856 [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize;
1857 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
1858 (ins GR32:$src1, i32imm:$src2),
1859 "add{l}\t{$src2, $dst|$dst, $src2}",
1860 [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>;
1861 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
1862 (ins GR16:$src1, i16i8imm:$src2),
1863 "add{w}\t{$src2, $dst|$dst, $src2}",
1864 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1865 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
1866 (ins GR32:$src1, i32i8imm:$src2),
1867 "add{l}\t{$src2, $dst|$dst, $src2}",
1868 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>;
1871 let isTwoAddress = 0 in {
1872 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1873 "add{b}\t{$src2, $dst|$dst, $src2}",
1874 [(store (add (load addr:$dst), GR8:$src2), addr:$dst)]>;
1875 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1876 "add{w}\t{$src2, $dst|$dst, $src2}",
1877 [(store (add (load addr:$dst), GR16:$src2), addr:$dst)]>,
1879 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1880 "add{l}\t{$src2, $dst|$dst, $src2}",
1881 [(store (add (load addr:$dst), GR32:$src2), addr:$dst)]>;
1882 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
1883 "add{b}\t{$src2, $dst|$dst, $src2}",
1884 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1885 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
1886 "add{w}\t{$src2, $dst|$dst, $src2}",
1887 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1889 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
1890 "add{l}\t{$src2, $dst|$dst, $src2}",
1891 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1892 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1893 "add{w}\t{$src2, $dst|$dst, $src2}",
1894 [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1896 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1897 "add{l}\t{$src2, $dst|$dst, $src2}",
1898 [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1901 let Uses = [EFLAGS] in {
1902 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1903 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1904 "adc{l}\t{$src2, $dst|$dst, $src2}",
1905 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
1907 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1908 "adc{l}\t{$src2, $dst|$dst, $src2}",
1909 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
1910 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1911 "adc{l}\t{$src2, $dst|$dst, $src2}",
1912 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
1913 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1914 "adc{l}\t{$src2, $dst|$dst, $src2}",
1915 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
1917 let isTwoAddress = 0 in {
1918 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1919 "adc{l}\t{$src2, $dst|$dst, $src2}",
1920 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
1921 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
1922 "adc{l}\t{$src2, $dst|$dst, $src2}",
1923 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1924 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1925 "adc{l}\t{$src2, $dst|$dst, $src2}",
1926 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1928 } // Uses = [EFLAGS]
1930 def SUB8rr : I<0x28, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1931 "sub{b}\t{$src2, $dst|$dst, $src2}",
1932 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2))]>;
1933 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1934 "sub{w}\t{$src2, $dst|$dst, $src2}",
1935 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2))]>, OpSize;
1936 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1937 "sub{l}\t{$src2, $dst|$dst, $src2}",
1938 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
1939 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1940 "sub{b}\t{$src2, $dst|$dst, $src2}",
1941 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2)))]>;
1942 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1943 "sub{w}\t{$src2, $dst|$dst, $src2}",
1944 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2)))]>, OpSize;
1945 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1946 "sub{l}\t{$src2, $dst|$dst, $src2}",
1947 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2)))]>;
1949 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1950 "sub{b}\t{$src2, $dst|$dst, $src2}",
1951 [(set GR8:$dst, (sub GR8:$src1, imm:$src2))]>;
1952 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1953 "sub{w}\t{$src2, $dst|$dst, $src2}",
1954 [(set GR16:$dst, (sub GR16:$src1, imm:$src2))]>, OpSize;
1955 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1956 "sub{l}\t{$src2, $dst|$dst, $src2}",
1957 [(set GR32:$dst, (sub GR32:$src1, imm:$src2))]>;
1958 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1959 "sub{w}\t{$src2, $dst|$dst, $src2}",
1960 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2))]>,
1962 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1963 "sub{l}\t{$src2, $dst|$dst, $src2}",
1964 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2))]>;
1965 let isTwoAddress = 0 in {
1966 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1967 "sub{b}\t{$src2, $dst|$dst, $src2}",
1968 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst)]>;
1969 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1970 "sub{w}\t{$src2, $dst|$dst, $src2}",
1971 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst)]>,
1973 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1974 "sub{l}\t{$src2, $dst|$dst, $src2}",
1975 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst)]>;
1976 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
1977 "sub{b}\t{$src2, $dst|$dst, $src2}",
1978 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1979 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
1980 "sub{w}\t{$src2, $dst|$dst, $src2}",
1981 [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1983 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
1984 "sub{l}\t{$src2, $dst|$dst, $src2}",
1985 [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1986 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1987 "sub{w}\t{$src2, $dst|$dst, $src2}",
1988 [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1990 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1991 "sub{l}\t{$src2, $dst|$dst, $src2}",
1992 [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1995 let Uses = [EFLAGS] in {
1996 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1997 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1998 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2000 let isTwoAddress = 0 in {
2001 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2002 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2003 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2004 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2005 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2006 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2007 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2008 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2009 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2010 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2011 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2012 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2014 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2015 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2016 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2017 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2018 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2019 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2020 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2021 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2022 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2023 } // Uses = [EFLAGS]
2024 } // Defs = [EFLAGS]
2026 let Defs = [EFLAGS] in {
2027 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2028 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2029 "imul{w}\t{$src2, $dst|$dst, $src2}",
2030 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2))]>, TB, OpSize;
2031 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2032 "imul{l}\t{$src2, $dst|$dst, $src2}",
2033 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>, TB;
2035 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2036 "imul{w}\t{$src2, $dst|$dst, $src2}",
2037 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2)))]>,
2039 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2040 "imul{l}\t{$src2, $dst|$dst, $src2}",
2041 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2)))]>, TB;
2042 } // Defs = [EFLAGS]
2043 } // end Two Address instructions
2045 // Suprisingly enough, these are not two address instructions!
2046 let Defs = [EFLAGS] in {
2047 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2048 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2049 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2050 [(set GR16:$dst, (mul GR16:$src1, imm:$src2))]>, OpSize;
2051 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2052 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2053 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2054 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
2055 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2056 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2057 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2058 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2))]>,
2060 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2061 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2062 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2063 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2))]>;
2065 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2066 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2067 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2068 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2))]>,
2070 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2071 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2072 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2073 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2))]>;
2074 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2075 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2076 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2077 [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>,
2079 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2080 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2081 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2082 [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>;
2083 } // Defs = [EFLAGS]
2085 //===----------------------------------------------------------------------===//
2086 // Test instructions are just like AND, except they don't generate a result.
2088 let Defs = [EFLAGS] in {
2089 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2090 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2091 "test{b}\t{$src2, $src1|$src1, $src2}",
2092 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
2093 (implicit EFLAGS)]>;
2094 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2095 "test{w}\t{$src2, $src1|$src1, $src2}",
2096 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
2097 (implicit EFLAGS)]>,
2099 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2100 "test{l}\t{$src2, $src1|$src1, $src2}",
2101 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
2102 (implicit EFLAGS)]>;
2105 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2106 "test{b}\t{$src2, $src1|$src1, $src2}",
2107 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2108 (implicit EFLAGS)]>;
2109 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2110 "test{w}\t{$src2, $src1|$src1, $src2}",
2111 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2112 (implicit EFLAGS)]>, OpSize;
2113 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2114 "test{l}\t{$src2, $src1|$src1, $src2}",
2115 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2116 (implicit EFLAGS)]>;
2118 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2119 (outs), (ins GR8:$src1, i8imm:$src2),
2120 "test{b}\t{$src2, $src1|$src1, $src2}",
2121 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
2122 (implicit EFLAGS)]>;
2123 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2124 (outs), (ins GR16:$src1, i16imm:$src2),
2125 "test{w}\t{$src2, $src1|$src1, $src2}",
2126 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
2127 (implicit EFLAGS)]>, OpSize;
2128 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2129 (outs), (ins GR32:$src1, i32imm:$src2),
2130 "test{l}\t{$src2, $src1|$src1, $src2}",
2131 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
2132 (implicit EFLAGS)]>;
2134 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2135 (outs), (ins i8mem:$src1, i8imm:$src2),
2136 "test{b}\t{$src2, $src1|$src1, $src2}",
2137 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2138 (implicit EFLAGS)]>;
2139 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2140 (outs), (ins i16mem:$src1, i16imm:$src2),
2141 "test{w}\t{$src2, $src1|$src1, $src2}",
2142 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2143 (implicit EFLAGS)]>, OpSize;
2144 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2145 (outs), (ins i32mem:$src1, i32imm:$src2),
2146 "test{l}\t{$src2, $src1|$src1, $src2}",
2147 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2148 (implicit EFLAGS)]>;
2149 } // Defs = [EFLAGS]
2152 // Condition code ops, incl. set if equal/not equal/...
2153 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2154 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2155 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2156 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2158 let Uses = [EFLAGS] in {
2159 def SETEr : I<0x94, MRM0r,
2160 (outs GR8 :$dst), (ins),
2162 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2164 def SETEm : I<0x94, MRM0m,
2165 (outs), (ins i8mem:$dst),
2167 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2169 def SETNEr : I<0x95, MRM0r,
2170 (outs GR8 :$dst), (ins),
2172 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2174 def SETNEm : I<0x95, MRM0m,
2175 (outs), (ins i8mem:$dst),
2177 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2179 def SETLr : I<0x9C, MRM0r,
2180 (outs GR8 :$dst), (ins),
2182 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2183 TB; // GR8 = < signed
2184 def SETLm : I<0x9C, MRM0m,
2185 (outs), (ins i8mem:$dst),
2187 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2188 TB; // [mem8] = < signed
2189 def SETGEr : I<0x9D, MRM0r,
2190 (outs GR8 :$dst), (ins),
2192 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2193 TB; // GR8 = >= signed
2194 def SETGEm : I<0x9D, MRM0m,
2195 (outs), (ins i8mem:$dst),
2197 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2198 TB; // [mem8] = >= signed
2199 def SETLEr : I<0x9E, MRM0r,
2200 (outs GR8 :$dst), (ins),
2202 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2203 TB; // GR8 = <= signed
2204 def SETLEm : I<0x9E, MRM0m,
2205 (outs), (ins i8mem:$dst),
2207 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2208 TB; // [mem8] = <= signed
2209 def SETGr : I<0x9F, MRM0r,
2210 (outs GR8 :$dst), (ins),
2212 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2213 TB; // GR8 = > signed
2214 def SETGm : I<0x9F, MRM0m,
2215 (outs), (ins i8mem:$dst),
2217 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2218 TB; // [mem8] = > signed
2220 def SETBr : I<0x92, MRM0r,
2221 (outs GR8 :$dst), (ins),
2223 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2224 TB; // GR8 = < unsign
2225 def SETBm : I<0x92, MRM0m,
2226 (outs), (ins i8mem:$dst),
2228 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
2229 TB; // [mem8] = < unsign
2230 def SETAEr : I<0x93, MRM0r,
2231 (outs GR8 :$dst), (ins),
2233 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
2234 TB; // GR8 = >= unsign
2235 def SETAEm : I<0x93, MRM0m,
2236 (outs), (ins i8mem:$dst),
2238 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
2239 TB; // [mem8] = >= unsign
2240 def SETBEr : I<0x96, MRM0r,
2241 (outs GR8 :$dst), (ins),
2243 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
2244 TB; // GR8 = <= unsign
2245 def SETBEm : I<0x96, MRM0m,
2246 (outs), (ins i8mem:$dst),
2248 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
2249 TB; // [mem8] = <= unsign
2250 def SETAr : I<0x97, MRM0r,
2251 (outs GR8 :$dst), (ins),
2253 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
2254 TB; // GR8 = > signed
2255 def SETAm : I<0x97, MRM0m,
2256 (outs), (ins i8mem:$dst),
2258 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
2259 TB; // [mem8] = > signed
2261 def SETSr : I<0x98, MRM0r,
2262 (outs GR8 :$dst), (ins),
2264 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
2265 TB; // GR8 = <sign bit>
2266 def SETSm : I<0x98, MRM0m,
2267 (outs), (ins i8mem:$dst),
2269 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
2270 TB; // [mem8] = <sign bit>
2271 def SETNSr : I<0x99, MRM0r,
2272 (outs GR8 :$dst), (ins),
2274 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
2275 TB; // GR8 = !<sign bit>
2276 def SETNSm : I<0x99, MRM0m,
2277 (outs), (ins i8mem:$dst),
2279 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
2280 TB; // [mem8] = !<sign bit>
2281 def SETPr : I<0x9A, MRM0r,
2282 (outs GR8 :$dst), (ins),
2284 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
2286 def SETPm : I<0x9A, MRM0m,
2287 (outs), (ins i8mem:$dst),
2289 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
2290 TB; // [mem8] = parity
2291 def SETNPr : I<0x9B, MRM0r,
2292 (outs GR8 :$dst), (ins),
2294 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
2295 TB; // GR8 = not parity
2296 def SETNPm : I<0x9B, MRM0m,
2297 (outs), (ins i8mem:$dst),
2299 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
2300 TB; // [mem8] = not parity
2301 } // Uses = [EFLAGS]
2304 // Integer comparisons
2305 let Defs = [EFLAGS] in {
2306 def CMP8rr : I<0x38, MRMDestReg,
2307 (outs), (ins GR8 :$src1, GR8 :$src2),
2308 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2309 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2310 def CMP16rr : I<0x39, MRMDestReg,
2311 (outs), (ins GR16:$src1, GR16:$src2),
2312 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2313 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
2314 def CMP32rr : I<0x39, MRMDestReg,
2315 (outs), (ins GR32:$src1, GR32:$src2),
2316 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2317 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
2318 def CMP8mr : I<0x38, MRMDestMem,
2319 (outs), (ins i8mem :$src1, GR8 :$src2),
2320 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2321 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
2322 (implicit EFLAGS)]>;
2323 def CMP16mr : I<0x39, MRMDestMem,
2324 (outs), (ins i16mem:$src1, GR16:$src2),
2325 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2326 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
2327 (implicit EFLAGS)]>, OpSize;
2328 def CMP32mr : I<0x39, MRMDestMem,
2329 (outs), (ins i32mem:$src1, GR32:$src2),
2330 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2331 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
2332 (implicit EFLAGS)]>;
2333 def CMP8rm : I<0x3A, MRMSrcMem,
2334 (outs), (ins GR8 :$src1, i8mem :$src2),
2335 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2336 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
2337 (implicit EFLAGS)]>;
2338 def CMP16rm : I<0x3B, MRMSrcMem,
2339 (outs), (ins GR16:$src1, i16mem:$src2),
2340 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2341 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
2342 (implicit EFLAGS)]>, OpSize;
2343 def CMP32rm : I<0x3B, MRMSrcMem,
2344 (outs), (ins GR32:$src1, i32mem:$src2),
2345 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2346 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
2347 (implicit EFLAGS)]>;
2348 def CMP8ri : Ii8<0x80, MRM7r,
2349 (outs), (ins GR8:$src1, i8imm:$src2),
2350 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2351 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
2352 def CMP16ri : Ii16<0x81, MRM7r,
2353 (outs), (ins GR16:$src1, i16imm:$src2),
2354 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2355 [(X86cmp GR16:$src1, imm:$src2),
2356 (implicit EFLAGS)]>, OpSize;
2357 def CMP32ri : Ii32<0x81, MRM7r,
2358 (outs), (ins GR32:$src1, i32imm:$src2),
2359 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2360 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
2361 def CMP8mi : Ii8 <0x80, MRM7m,
2362 (outs), (ins i8mem :$src1, i8imm :$src2),
2363 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2364 [(X86cmp (loadi8 addr:$src1), imm:$src2),
2365 (implicit EFLAGS)]>;
2366 def CMP16mi : Ii16<0x81, MRM7m,
2367 (outs), (ins i16mem:$src1, i16imm:$src2),
2368 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2369 [(X86cmp (loadi16 addr:$src1), imm:$src2),
2370 (implicit EFLAGS)]>, OpSize;
2371 def CMP32mi : Ii32<0x81, MRM7m,
2372 (outs), (ins i32mem:$src1, i32imm:$src2),
2373 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2374 [(X86cmp (loadi32 addr:$src1), imm:$src2),
2375 (implicit EFLAGS)]>;
2376 def CMP16ri8 : Ii8<0x83, MRM7r,
2377 (outs), (ins GR16:$src1, i16i8imm:$src2),
2378 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2379 [(X86cmp GR16:$src1, i16immSExt8:$src2),
2380 (implicit EFLAGS)]>, OpSize;
2381 def CMP16mi8 : Ii8<0x83, MRM7m,
2382 (outs), (ins i16mem:$src1, i16i8imm:$src2),
2383 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2384 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
2385 (implicit EFLAGS)]>, OpSize;
2386 def CMP32mi8 : Ii8<0x83, MRM7m,
2387 (outs), (ins i32mem:$src1, i32i8imm:$src2),
2388 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2389 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
2390 (implicit EFLAGS)]>;
2391 def CMP32ri8 : Ii8<0x83, MRM7r,
2392 (outs), (ins GR32:$src1, i32i8imm:$src2),
2393 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2394 [(X86cmp GR32:$src1, i32immSExt8:$src2),
2395 (implicit EFLAGS)]>;
2396 } // Defs = [EFLAGS]
2398 // Sign/Zero extenders
2399 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2400 "movs{bw|x}\t{$src, $dst|$dst, $src}",
2401 [(set GR16:$dst, (sext GR8:$src))]>, TB, OpSize;
2402 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2403 "movs{bw|x}\t{$src, $dst|$dst, $src}",
2404 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize;
2405 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2406 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2407 [(set GR32:$dst, (sext GR8:$src))]>, TB;
2408 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2409 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2410 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
2411 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2412 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2413 [(set GR32:$dst, (sext GR16:$src))]>, TB;
2414 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2415 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2416 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
2418 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2419 "movz{bw|x}\t{$src, $dst|$dst, $src}",
2420 [(set GR16:$dst, (zext GR8:$src))]>, TB, OpSize;
2421 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2422 "movz{bw|x}\t{$src, $dst|$dst, $src}",
2423 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize;
2424 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2425 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2426 [(set GR32:$dst, (zext GR8:$src))]>, TB;
2427 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2428 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2429 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
2430 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2431 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2432 [(set GR32:$dst, (zext GR16:$src))]>, TB;
2433 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2434 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2435 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
2437 let neverHasSideEffects = 1 in {
2438 let Defs = [AX], Uses = [AL] in
2439 def CBW : I<0x98, RawFrm, (outs), (ins),
2440 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
2441 let Defs = [EAX], Uses = [AX] in
2442 def CWDE : I<0x98, RawFrm, (outs), (ins),
2443 "{cwtl|cwde}", []>; // EAX = signext(AX)
2445 let Defs = [AX,DX], Uses = [AX] in
2446 def CWD : I<0x99, RawFrm, (outs), (ins),
2447 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
2448 let Defs = [EAX,EDX], Uses = [EAX] in
2449 def CDQ : I<0x99, RawFrm, (outs), (ins),
2450 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
2453 //===----------------------------------------------------------------------===//
2454 // Alias Instructions
2455 //===----------------------------------------------------------------------===//
2457 // Alias instructions that map movr0 to xor.
2458 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2459 let Defs = [EFLAGS], isReMaterializable = 1 in {
2460 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
2461 "xor{b}\t$dst, $dst",
2462 [(set GR8:$dst, 0)]>;
2463 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
2464 "xor{w}\t$dst, $dst",
2465 [(set GR16:$dst, 0)]>, OpSize;
2466 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
2467 "xor{l}\t$dst, $dst",
2468 [(set GR32:$dst, 0)]>;
2471 // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
2472 // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
2473 let neverHasSideEffects = 1 in {
2474 def MOV16to16_ : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16:$src),
2475 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2476 def MOV32to32_ : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32:$src),
2477 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2479 def MOV16_rr : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16_:$src),
2480 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2481 def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src),
2482 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2483 } // neverHasSideEffects
2485 let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
2486 def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src),
2487 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2488 def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src),
2489 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2491 let mayStore = 1, neverHasSideEffects = 1 in {
2492 def MOV16_mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16_:$src),
2493 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2494 def MOV32_mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32_:$src),
2495 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2498 //===----------------------------------------------------------------------===//
2499 // Thread Local Storage Instructions
2503 def TLS_addr32 : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
2504 "leal\t${sym:mem}(,%ebx,1), $dst",
2505 [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
2507 let AddedComplexity = 10 in
2508 def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
2509 "movl\t%gs:($src), $dst",
2510 [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
2512 let AddedComplexity = 15 in
2513 def TLS_gs_ri : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
2514 "movl\t%gs:${src:mem}, $dst",
2516 (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>;
2518 def TLS_tp : I<0, Pseudo, (outs GR32:$dst), (ins),
2519 "movl\t%gs:0, $dst",
2520 [(set GR32:$dst, X86TLStp)]>;
2522 //===----------------------------------------------------------------------===//
2523 // DWARF Pseudo Instructions
2526 def DWARF_LOC : I<0, Pseudo, (outs),
2527 (ins i32imm:$line, i32imm:$col, i32imm:$file),
2528 ".loc\t${file:debug} ${line:debug} ${col:debug}",
2529 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
2532 //===----------------------------------------------------------------------===//
2533 // EH Pseudo Instructions
2535 let isTerminator = 1, isReturn = 1, isBarrier = 1,
2537 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
2538 "ret\t#eh_return, addr: $addr",
2539 [(X86ehret GR32:$addr)]>;
2543 //===----------------------------------------------------------------------===//
2547 // Atomic swap. These are just normal xchg instructions. But since a memory
2548 // operand is referenced, the atomicity is ensured.
2549 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
2550 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2551 "xchg{l}\t{$val, $ptr|$ptr, $val}",
2552 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
2553 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2554 "xchg{w}\t{$val, $ptr|$ptr, $val}",
2555 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
2557 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2558 "xchg{b}\t{$val, $ptr|$ptr, $val}",
2559 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
2562 // Atomic compare and swap.
2563 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
2564 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
2565 "lock cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
2566 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
2568 let Defs = [EAX, EBX, ECX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
2569 def LCMPXCHG8B : I<0xC7, MRMDestMem, (outs), (ins i32mem:$ptr),
2570 "lock cmpxchg8b\t$ptr",
2571 [(X86cas8 addr:$ptr)]>, TB, LOCK;
2574 let Defs = [AX, EFLAGS], Uses = [AX] in {
2575 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
2576 "lock cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
2577 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
2579 let Defs = [AL, EFLAGS], Uses = [AL] in {
2580 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
2581 "lock cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
2582 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
2585 // Atomic exchange and add
2586 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
2587 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2588 "lock xadd{l}\t{$val, $ptr|$ptr, $val}",
2589 [(set GR32:$dst, (atomic_las_32 addr:$ptr, GR32:$val))]>,
2591 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2592 "lock xadd{w}\t{$val, $ptr|$ptr, $val}",
2593 [(set GR16:$dst, (atomic_las_16 addr:$ptr, GR16:$val))]>,
2595 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2596 "lock xadd{b}\t{$val, $ptr|$ptr, $val}",
2597 [(set GR8:$dst, (atomic_las_8 addr:$ptr, GR8:$val))]>,
2601 // Atomic exchange and and, or, xor
2602 let Constraints = "$val = $dst", Defs = [EFLAGS],
2603 usesCustomDAGSchedInserter = 1 in {
2604 def ATOMAND32 : I<0xC1, MRMSrcMem,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2605 "#ATOMAND32 PSUEDO!",
2606 [(set GR32:$dst, (atomic_load_and addr:$ptr, GR32:$val))]>,
2610 let Constraints = "$val = $dst", Defs = [EFLAGS],
2611 usesCustomDAGSchedInserter = 1 in {
2612 def ATOMOR32 : I<0xC1, MRMSrcMem, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2613 "#ATOMOR32 PSUEDO!",
2614 [(set GR32:$dst, (atomic_load_or addr:$ptr, GR32:$val))]>,
2618 let Constraints = "$val = $dst", Defs = [EFLAGS],
2619 usesCustomDAGSchedInserter = 1 in {
2620 def ATOMXOR32 : I<0xC1, MRMSrcMem,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2621 "#ATOMXOR32 PSUEDO!",
2622 [(set GR32:$dst, (atomic_load_xor addr:$ptr, GR32:$val))]>,
2626 let Constraints = "$val = $dst", Defs = [EFLAGS],
2627 usesCustomDAGSchedInserter = 1 in {
2628 def ATOMMIN32: I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2629 "#ATOMMIN32 PSUEDO!",
2630 [(set GR32:$dst, (atomic_load_min addr:$ptr, GR32:$val))]>,
2634 let Constraints = "$val = $dst", Defs = [EFLAGS],
2635 usesCustomDAGSchedInserter = 1 in {
2636 def ATOMMAX32: I<0xC1, MRMSrcMem, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2637 "#ATOMMAX32 PSUEDO!",
2638 [(set GR32:$dst, (atomic_load_max addr:$ptr, GR32:$val))]>,
2642 let Constraints = "$val = $dst", Defs = [EFLAGS],
2643 usesCustomDAGSchedInserter = 1 in {
2644 def ATOMUMIN32: I<0xC1, MRMSrcMem,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2645 "#ATOMUMIN32 PSUEDO!",
2646 [(set GR32:$dst, (atomic_load_umin addr:$ptr, GR32:$val))]>,
2650 let Constraints = "$val = $dst", Defs = [EFLAGS],
2651 usesCustomDAGSchedInserter = 1 in {
2652 def ATOMUMAX32: I<0xC1, MRMSrcMem,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2653 "#ATOMUMAX32 PSUEDO!",
2654 [(set GR32:$dst, (atomic_load_umax addr:$ptr, GR32:$val))]>,
2658 //===----------------------------------------------------------------------===//
2659 // Non-Instruction Patterns
2660 //===----------------------------------------------------------------------===//
2662 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
2663 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
2664 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
2665 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
2666 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
2667 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
2669 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
2670 (ADD32ri GR32:$src1, tconstpool:$src2)>;
2671 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
2672 (ADD32ri GR32:$src1, tjumptable:$src2)>;
2673 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
2674 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
2675 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
2676 (ADD32ri GR32:$src1, texternalsym:$src2)>;
2678 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
2679 (MOV32mi addr:$dst, tglobaladdr:$src)>;
2680 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
2681 (MOV32mi addr:$dst, texternalsym:$src)>;
2685 def : Pat<(X86tailcall GR32:$dst),
2688 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
2690 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
2693 def : Pat<(X86tcret GR32:$dst, imm:$off),
2694 (TCRETURNri GR32:$dst, imm:$off)>;
2696 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
2697 (TCRETURNdi texternalsym:$dst, imm:$off)>;
2699 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
2700 (TCRETURNdi texternalsym:$dst, imm:$off)>;
2702 def : Pat<(X86call (i32 tglobaladdr:$dst)),
2703 (CALLpcrel32 tglobaladdr:$dst)>;
2704 def : Pat<(X86call (i32 texternalsym:$dst)),
2705 (CALLpcrel32 texternalsym:$dst)>;
2707 // X86 specific add which produces a flag.
2708 def : Pat<(addc GR32:$src1, GR32:$src2),
2709 (ADD32rr GR32:$src1, GR32:$src2)>;
2710 def : Pat<(addc GR32:$src1, (load addr:$src2)),
2711 (ADD32rm GR32:$src1, addr:$src2)>;
2712 def : Pat<(addc GR32:$src1, imm:$src2),
2713 (ADD32ri GR32:$src1, imm:$src2)>;
2714 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
2715 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
2717 def : Pat<(subc GR32:$src1, GR32:$src2),
2718 (SUB32rr GR32:$src1, GR32:$src2)>;
2719 def : Pat<(subc GR32:$src1, (load addr:$src2)),
2720 (SUB32rm GR32:$src1, addr:$src2)>;
2721 def : Pat<(subc GR32:$src1, imm:$src2),
2722 (SUB32ri GR32:$src1, imm:$src2)>;
2723 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
2724 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
2728 // TEST R,R is smaller than CMP R,0
2729 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
2730 (TEST8rr GR8:$src1, GR8:$src1)>;
2731 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
2732 (TEST16rr GR16:$src1, GR16:$src1)>;
2733 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
2734 (TEST32rr GR32:$src1, GR32:$src1)>;
2736 // zextload bool -> zextload byte
2737 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2738 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2739 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2741 // extload bool -> extload byte
2742 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2743 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2744 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2745 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
2746 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
2747 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
2750 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
2751 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
2752 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
2753 def : Pat<(i16 (anyext (loadi8 addr:$src))), (MOVZX16rm8 addr:$src)>;
2754 def : Pat<(i32 (anyext (loadi8 addr:$src))), (MOVZX32rm8 addr:$src)>;
2755 def : Pat<(i32 (anyext (loadi16 addr:$src))), (MOVZX32rm16 addr:$src)>;
2757 // (and (i32 load), 255) -> (zextload i8)
2758 def : Pat<(i32 (and (loadi32 addr:$src), (i32 255))), (MOVZX32rm8 addr:$src)>;
2759 def : Pat<(i32 (and (loadi32 addr:$src), (i32 65535))),(MOVZX32rm16 addr:$src)>;
2761 //===----------------------------------------------------------------------===//
2763 //===----------------------------------------------------------------------===//
2765 // (shl x, 1) ==> (add x, x)
2766 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
2767 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
2768 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
2770 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
2771 def : Pat<(or (srl GR32:$src1, CL:$amt),
2772 (shl GR32:$src2, (sub 32, CL:$amt))),
2773 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
2775 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
2776 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2777 (SHRD32mrCL addr:$dst, GR32:$src2)>;
2779 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
2780 def : Pat<(or (shl GR32:$src1, CL:$amt),
2781 (srl GR32:$src2, (sub 32, CL:$amt))),
2782 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
2784 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
2785 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2786 (SHLD32mrCL addr:$dst, GR32:$src2)>;
2788 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
2789 def : Pat<(or (srl GR16:$src1, CL:$amt),
2790 (shl GR16:$src2, (sub 16, CL:$amt))),
2791 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
2793 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
2794 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2795 (SHRD16mrCL addr:$dst, GR16:$src2)>;
2797 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
2798 def : Pat<(or (shl GR16:$src1, CL:$amt),
2799 (srl GR16:$src2, (sub 16, CL:$amt))),
2800 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
2802 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
2803 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2804 (SHLD16mrCL addr:$dst, GR16:$src2)>;
2806 //===----------------------------------------------------------------------===//
2807 // Floating Point Stack Support
2808 //===----------------------------------------------------------------------===//
2810 include "X86InstrFPStack.td"
2812 //===----------------------------------------------------------------------===//
2814 //===----------------------------------------------------------------------===//
2816 include "X86Instr64bit.td"
2818 //===----------------------------------------------------------------------===//
2819 // XMM Floating point support (requires SSE / SSE2)
2820 //===----------------------------------------------------------------------===//
2822 include "X86InstrSSE.td"
2824 //===----------------------------------------------------------------------===//
2825 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
2826 //===----------------------------------------------------------------------===//
2828 include "X86InstrMMX.td"