1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 def SDTX86BrCond : SDTypeProfile<0, 3,
31 [SDTCisVT<0, OtherVT>,
32 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
34 def SDTX86SetCC : SDTypeProfile<1, 2,
36 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
38 def SDTX86Ret : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>;
40 def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
41 def SDT_X86CallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
44 def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
46 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
48 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
50 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
52 def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
54 def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
56 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
58 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
60 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
61 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
62 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
63 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
65 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
67 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
68 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
70 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
72 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
73 [SDNPHasChain, SDNPOptInFlag]>;
75 def X86callseq_start :
76 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
77 [SDNPHasChain, SDNPOutFlag]>;
79 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
82 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
83 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
85 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
86 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
88 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
89 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
90 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
91 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
94 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
95 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
97 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
98 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
100 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
101 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
102 def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
104 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
107 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
108 [SDNPHasChain, SDNPOptInFlag]>;
110 //===----------------------------------------------------------------------===//
111 // X86 Operand Definitions.
114 // *mem - Operand definitions for the funky X86 addressing mode operands.
116 class X86MemOperand<string printMethod> : Operand<iPTR> {
117 let PrintMethod = printMethod;
118 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
121 def i8mem : X86MemOperand<"printi8mem">;
122 def i16mem : X86MemOperand<"printi16mem">;
123 def i32mem : X86MemOperand<"printi32mem">;
124 def i64mem : X86MemOperand<"printi64mem">;
125 def i128mem : X86MemOperand<"printi128mem">;
126 def f32mem : X86MemOperand<"printf32mem">;
127 def f64mem : X86MemOperand<"printf64mem">;
128 def f80mem : X86MemOperand<"printf80mem">;
129 def f128mem : X86MemOperand<"printf128mem">;
131 def lea32mem : Operand<i32> {
132 let PrintMethod = "printi32mem";
133 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
136 def SSECC : Operand<i8> {
137 let PrintMethod = "printSSECC";
140 def piclabel: Operand<i32> {
141 let PrintMethod = "printPICLabel";
144 // A couple of more descriptive operand definitions.
145 // 16-bits but only 8 bits are significant.
146 def i16i8imm : Operand<i16>;
147 // 32-bits but only 8 bits are significant.
148 def i32i8imm : Operand<i32>;
150 // Branch targets have OtherVT type.
151 def brtarget : Operand<OtherVT>;
153 //===----------------------------------------------------------------------===//
154 // X86 Complex Pattern Definitions.
157 // Define X86 specific addressing mode.
158 def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
159 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
160 [add, mul, shl, or, frameindex], []>;
162 //===----------------------------------------------------------------------===//
163 // X86 Instruction Predicate Definitions.
164 def HasMMX : Predicate<"Subtarget->hasMMX()">;
165 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
166 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
167 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
168 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
169 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
170 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
171 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
172 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
173 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
174 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
175 def HasLow4G : Predicate<"Subtarget->hasLow4GUserSpaceAddress()">;
176 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
177 def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
178 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
180 //===----------------------------------------------------------------------===//
181 // X86 Instruction Format Definitions.
184 include "X86InstrFormats.td"
186 //===----------------------------------------------------------------------===//
187 // Pattern fragments...
190 // X86 specific condition code. These correspond to CondCode in
191 // X86InstrInfo.h. They must be kept in synch.
192 def X86_COND_A : PatLeaf<(i8 0)>;
193 def X86_COND_AE : PatLeaf<(i8 1)>;
194 def X86_COND_B : PatLeaf<(i8 2)>;
195 def X86_COND_BE : PatLeaf<(i8 3)>;
196 def X86_COND_E : PatLeaf<(i8 4)>;
197 def X86_COND_G : PatLeaf<(i8 5)>;
198 def X86_COND_GE : PatLeaf<(i8 6)>;
199 def X86_COND_L : PatLeaf<(i8 7)>;
200 def X86_COND_LE : PatLeaf<(i8 8)>;
201 def X86_COND_NE : PatLeaf<(i8 9)>;
202 def X86_COND_NO : PatLeaf<(i8 10)>;
203 def X86_COND_NP : PatLeaf<(i8 11)>;
204 def X86_COND_NS : PatLeaf<(i8 12)>;
205 def X86_COND_O : PatLeaf<(i8 13)>;
206 def X86_COND_P : PatLeaf<(i8 14)>;
207 def X86_COND_S : PatLeaf<(i8 15)>;
209 def i16immSExt8 : PatLeaf<(i16 imm), [{
210 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
211 // sign extended field.
212 return (int16_t)N->getValue() == (int8_t)N->getValue();
215 def i32immSExt8 : PatLeaf<(i32 imm), [{
216 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
217 // sign extended field.
218 return (int32_t)N->getValue() == (int8_t)N->getValue();
221 // Helper fragments for loads.
222 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
223 def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>;
224 def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>;
225 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
227 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
228 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
229 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
231 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
232 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
233 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
235 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
236 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
237 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
238 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
239 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
240 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
242 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
243 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
244 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
245 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
246 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
247 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
249 //===----------------------------------------------------------------------===//
250 // Instruction list...
253 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
254 // a stack adjustment and the codegen must know that they may modify the stack
255 // pointer before prolog-epilog rewriting occurs.
256 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become sub / add
257 // which can clobber EFLAGS.
258 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
259 def ADJCALLSTACKDOWN : I<0, Pseudo, (outs), (ins i32imm:$amt),
261 [(X86callseq_start imm:$amt)]>;
262 def ADJCALLSTACKUP : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
264 [(X86callseq_end imm:$amt1, imm:$amt2)]>;
266 let isImplicitDef = 1 in {
267 def IMPLICIT_DEF_GR8 : I<0, Pseudo, (outs GR8:$dst), (ins),
268 "#IMPLICIT_DEF $dst",
269 [(set GR8:$dst, (undef))]>;
270 def IMPLICIT_DEF_GR16 : I<0, Pseudo, (outs GR16:$dst), (ins),
271 "#IMPLICIT_DEF $dst",
272 [(set GR16:$dst, (undef))]>;
273 def IMPLICIT_DEF_GR32 : I<0, Pseudo, (outs GR32:$dst), (ins),
274 "#IMPLICIT_DEF $dst",
275 [(set GR32:$dst, (undef))]>;
279 let neverHasSideEffects = 1 in
280 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
283 let neverHasSideEffects = 1, isNotDuplicable = 1 in
284 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
285 "call\t$label\n\tpop{l}\t$reg", []>;
287 //===----------------------------------------------------------------------===//
288 // Control Flow Instructions...
291 // Return instructions.
292 let isTerminator = 1, isReturn = 1, isBarrier = 1,
294 def RET : I<0xC3, RawFrm, (outs), (ins), "ret", [(X86retflag 0)]>;
295 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), "ret\t$amt",
296 [(X86retflag imm:$amt)]>;
299 // All branches are RawFrm, Void, Branch, and Terminators
300 let isBranch = 1, isTerminator = 1 in
301 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
302 I<opcode, RawFrm, (outs), ins, asm, pattern>;
304 let isBranch = 1, isBarrier = 1 in
305 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
308 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
309 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
310 [(brind GR32:$dst)]>;
311 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
312 [(brind (loadi32 addr:$dst))]>;
315 // Conditional branches
316 let Uses = [EFLAGS] in {
317 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
318 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
319 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
320 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
321 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
322 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
323 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
324 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
325 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
326 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
327 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
328 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
330 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
331 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
332 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
333 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
334 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
335 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
336 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
337 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
339 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
340 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
341 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
342 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
343 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
344 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
345 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
346 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
347 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
348 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
349 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
350 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
353 //===----------------------------------------------------------------------===//
354 // Call Instructions...
357 // All calls clobber the non-callee saved registers...
358 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
359 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
360 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, EFLAGS] in {
361 def CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:$dst,variable_ops),
362 "call\t${dst:call}", []>;
363 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
364 "call\t{*}$dst", [(X86call GR32:$dst)]>;
365 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
366 "call\t{*}$dst", []>;
371 def TAILCALL : I<0, Pseudo, (outs), (ins ),
375 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
376 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset),
377 "#TC_RETURN $dst $offset",
380 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
381 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset),
382 "#TC_RETURN $dst $offset",
385 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
386 def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAILCALL",
388 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
389 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
391 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
392 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
393 "jmp\t{*}$dst # TAILCALL", []>;
395 //===----------------------------------------------------------------------===//
396 // Miscellaneous Instructions...
398 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
399 def LEAVE : I<0xC9, RawFrm,
400 (outs), (ins), "leave", []>;
402 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
404 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
407 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
410 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
411 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
412 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
413 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
415 let isTwoAddress = 1 in // GR32 = bswap GR32
416 def BSWAP32r : I<0xC8, AddRegFrm,
417 (outs GR32:$dst), (ins GR32:$src),
419 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
422 // Bit scan instructions.
423 let Defs = [EFLAGS] in {
424 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
425 "bsf{w}\t{$src, $dst|$dst, $src}",
426 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
427 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
428 "bsf{w}\t{$src, $dst|$dst, $src}",
429 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
430 (implicit EFLAGS)]>, TB;
431 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
432 "bsf{l}\t{$src, $dst|$dst, $src}",
433 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
434 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
435 "bsf{l}\t{$src, $dst|$dst, $src}",
436 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
437 (implicit EFLAGS)]>, TB;
439 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
440 "bsr{w}\t{$src, $dst|$dst, $src}",
441 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
442 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
443 "bsr{w}\t{$src, $dst|$dst, $src}",
444 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
445 (implicit EFLAGS)]>, TB;
446 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
447 "bsr{l}\t{$src, $dst|$dst, $src}",
448 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
449 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
450 "bsr{l}\t{$src, $dst|$dst, $src}",
451 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
452 (implicit EFLAGS)]>, TB;
455 let neverHasSideEffects = 1 in
456 def LEA16r : I<0x8D, MRMSrcMem,
457 (outs GR16:$dst), (ins i32mem:$src),
458 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
459 def LEA32r : I<0x8D, MRMSrcMem,
460 (outs GR32:$dst), (ins lea32mem:$src),
461 "lea{l}\t{$src|$dst}, {$dst|$src}",
462 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
464 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
465 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
466 [(X86rep_movs i8)]>, REP;
467 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
468 [(X86rep_movs i16)]>, REP, OpSize;
469 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
470 [(X86rep_movs i32)]>, REP;
473 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
474 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
475 [(X86rep_stos i8)]>, REP;
476 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
477 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
478 [(X86rep_stos i16)]>, REP, OpSize;
479 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
480 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
481 [(X86rep_stos i32)]>, REP;
483 let Defs = [RAX, RDX] in
484 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
487 let isBarrier = 1, hasCtrlDep = 1 in {
488 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
491 //===----------------------------------------------------------------------===//
492 // Input/Output Instructions...
494 let Defs = [AL], Uses = [DX] in
495 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
496 "in{b}\t{%dx, %al|%AL, %DX}", []>;
497 let Defs = [AX], Uses = [DX] in
498 def IN16rr : I<0xED, RawFrm, (outs), (ins),
499 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
500 let Defs = [EAX], Uses = [DX] in
501 def IN32rr : I<0xED, RawFrm, (outs), (ins),
502 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
505 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
506 "in{b}\t{$port, %al|%AL, $port}", []>;
508 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
509 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
511 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
512 "in{l}\t{$port, %eax|%EAX, $port}", []>;
514 let Uses = [DX, AL] in
515 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
516 "out{b}\t{%al, %dx|%DX, %AL}", []>;
517 let Uses = [DX, AX] in
518 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
519 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
520 let Uses = [DX, EAX] in
521 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
522 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
525 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
526 "out{b}\t{%al, $port|$port, %AL}", []>;
528 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
529 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
531 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
532 "out{l}\t{%eax, $port|$port, %EAX}", []>;
534 //===----------------------------------------------------------------------===//
535 // Move Instructions...
537 let neverHasSideEffects = 1 in {
538 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
539 "mov{b}\t{$src, $dst|$dst, $src}", []>;
540 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
541 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
542 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
543 "mov{l}\t{$src, $dst|$dst, $src}", []>;
545 let isReMaterializable = 1 in {
546 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
547 "mov{b}\t{$src, $dst|$dst, $src}",
548 [(set GR8:$dst, imm:$src)]>;
549 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
550 "mov{w}\t{$src, $dst|$dst, $src}",
551 [(set GR16:$dst, imm:$src)]>, OpSize;
552 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
553 "mov{l}\t{$src, $dst|$dst, $src}",
554 [(set GR32:$dst, imm:$src)]>;
556 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
557 "mov{b}\t{$src, $dst|$dst, $src}",
558 [(store (i8 imm:$src), addr:$dst)]>;
559 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
560 "mov{w}\t{$src, $dst|$dst, $src}",
561 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
562 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
563 "mov{l}\t{$src, $dst|$dst, $src}",
564 [(store (i32 imm:$src), addr:$dst)]>;
566 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
567 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
568 "mov{b}\t{$src, $dst|$dst, $src}",
569 [(set GR8:$dst, (load addr:$src))]>;
570 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
571 "mov{w}\t{$src, $dst|$dst, $src}",
572 [(set GR16:$dst, (load addr:$src))]>, OpSize;
573 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
574 "mov{l}\t{$src, $dst|$dst, $src}",
575 [(set GR32:$dst, (load addr:$src))]>;
578 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
579 "mov{b}\t{$src, $dst|$dst, $src}",
580 [(store GR8:$src, addr:$dst)]>;
581 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
582 "mov{w}\t{$src, $dst|$dst, $src}",
583 [(store GR16:$src, addr:$dst)]>, OpSize;
584 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
585 "mov{l}\t{$src, $dst|$dst, $src}",
586 [(store GR32:$src, addr:$dst)]>;
588 //===----------------------------------------------------------------------===//
589 // Fixed-Register Multiplication and Division Instructions...
592 // Extra precision multiplication
593 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
594 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
595 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
596 // This probably ought to be moved to a def : Pat<> if the
597 // syntax can be accepted.
598 [(set AL, (mul AL, GR8:$src))]>; // AL,AH = AL*GR8
599 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
600 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>,
601 OpSize; // AX,DX = AX*GR16
602 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
603 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l}\t$src", []>;
604 // EAX,EDX = EAX*GR32
605 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
606 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
608 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
609 // This probably ought to be moved to a def : Pat<> if the
610 // syntax can be accepted.
611 [(set AL, (mul AL, (loadi8 addr:$src)))]>; // AL,AH = AL*[mem8]
612 let mayLoad = 1, neverHasSideEffects = 1 in {
613 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
614 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
615 "mul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
616 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
617 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
618 "mul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
621 let neverHasSideEffects = 1 in {
622 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
623 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
625 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
626 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
627 OpSize; // AX,DX = AX*GR16
628 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
629 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
630 // EAX,EDX = EAX*GR32
632 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
633 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
634 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
635 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
636 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
637 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
638 let Defs = [EAX,EDX], Uses = [EAX] in
639 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
640 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
643 // unsigned division/remainder
644 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
645 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
647 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
648 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
649 "div{w}\t$src", []>, OpSize;
650 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
651 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
654 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
655 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
657 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
658 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
659 "div{w}\t$src", []>, OpSize;
660 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
661 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
665 // Signed division/remainder.
666 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
667 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
668 "idiv{b}\t$src", []>;
669 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
670 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
671 "idiv{w}\t$src", []>, OpSize;
672 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
673 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
674 "idiv{l}\t$src", []>;
675 let mayLoad = 1, mayLoad = 1 in {
676 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
677 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
678 "idiv{b}\t$src", []>;
679 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
680 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
681 "idiv{w}\t$src", []>, OpSize;
682 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
683 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
684 "idiv{l}\t$src", []>;
686 } // neverHasSideEffects
688 //===----------------------------------------------------------------------===//
689 // Two address Instructions.
691 let isTwoAddress = 1 in {
694 let Uses = [EFLAGS] in {
695 let isCommutable = 1 in {
696 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
697 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
698 "cmovb\t{$src2, $dst|$dst, $src2}",
699 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
700 X86_COND_B, EFLAGS))]>,
702 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
703 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
704 "cmovb\t{$src2, $dst|$dst, $src2}",
705 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
706 X86_COND_B, EFLAGS))]>,
709 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
710 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
711 "cmovae\t{$src2, $dst|$dst, $src2}",
712 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
713 X86_COND_AE, EFLAGS))]>,
715 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
716 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
717 "cmovae\t{$src2, $dst|$dst, $src2}",
718 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
719 X86_COND_AE, EFLAGS))]>,
721 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
722 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
723 "cmove\t{$src2, $dst|$dst, $src2}",
724 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
725 X86_COND_E, EFLAGS))]>,
727 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
728 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
729 "cmove\t{$src2, $dst|$dst, $src2}",
730 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
731 X86_COND_E, EFLAGS))]>,
733 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
734 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
735 "cmovne\t{$src2, $dst|$dst, $src2}",
736 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
737 X86_COND_NE, EFLAGS))]>,
739 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
740 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
741 "cmovne\t{$src2, $dst|$dst, $src2}",
742 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
743 X86_COND_NE, EFLAGS))]>,
745 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
746 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
747 "cmovbe\t{$src2, $dst|$dst, $src2}",
748 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
749 X86_COND_BE, EFLAGS))]>,
751 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
752 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
753 "cmovbe\t{$src2, $dst|$dst, $src2}",
754 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
755 X86_COND_BE, EFLAGS))]>,
757 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
758 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
759 "cmova\t{$src2, $dst|$dst, $src2}",
760 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
761 X86_COND_A, EFLAGS))]>,
763 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
764 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
765 "cmova\t{$src2, $dst|$dst, $src2}",
766 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
767 X86_COND_A, EFLAGS))]>,
769 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
770 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
771 "cmovl\t{$src2, $dst|$dst, $src2}",
772 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
773 X86_COND_L, EFLAGS))]>,
775 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
776 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
777 "cmovl\t{$src2, $dst|$dst, $src2}",
778 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
779 X86_COND_L, EFLAGS))]>,
781 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
782 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
783 "cmovge\t{$src2, $dst|$dst, $src2}",
784 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
785 X86_COND_GE, EFLAGS))]>,
787 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
788 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
789 "cmovge\t{$src2, $dst|$dst, $src2}",
790 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
791 X86_COND_GE, EFLAGS))]>,
793 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
794 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
795 "cmovle\t{$src2, $dst|$dst, $src2}",
796 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
797 X86_COND_LE, EFLAGS))]>,
799 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
800 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
801 "cmovle\t{$src2, $dst|$dst, $src2}",
802 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
803 X86_COND_LE, EFLAGS))]>,
805 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
806 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
807 "cmovg\t{$src2, $dst|$dst, $src2}",
808 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
809 X86_COND_G, EFLAGS))]>,
811 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
812 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
813 "cmovg\t{$src2, $dst|$dst, $src2}",
814 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
815 X86_COND_G, EFLAGS))]>,
817 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
818 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
819 "cmovs\t{$src2, $dst|$dst, $src2}",
820 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
821 X86_COND_S, EFLAGS))]>,
823 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
824 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
825 "cmovs\t{$src2, $dst|$dst, $src2}",
826 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
827 X86_COND_S, EFLAGS))]>,
829 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
830 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
831 "cmovns\t{$src2, $dst|$dst, $src2}",
832 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
833 X86_COND_NS, EFLAGS))]>,
835 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
836 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
837 "cmovns\t{$src2, $dst|$dst, $src2}",
838 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
839 X86_COND_NS, EFLAGS))]>,
841 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
842 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
843 "cmovp\t{$src2, $dst|$dst, $src2}",
844 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
845 X86_COND_P, EFLAGS))]>,
847 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
848 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
849 "cmovp\t{$src2, $dst|$dst, $src2}",
850 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
851 X86_COND_P, EFLAGS))]>,
853 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
854 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
855 "cmovnp\t{$src2, $dst|$dst, $src2}",
856 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
857 X86_COND_NP, EFLAGS))]>,
859 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
860 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
861 "cmovnp\t{$src2, $dst|$dst, $src2}",
862 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
863 X86_COND_NP, EFLAGS))]>,
865 } // isCommutable = 1
867 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
868 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
869 "cmovnp\t{$src2, $dst|$dst, $src2}",
870 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
871 X86_COND_NP, EFLAGS))]>,
874 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
875 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
876 "cmovb\t{$src2, $dst|$dst, $src2}",
877 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
878 X86_COND_B, EFLAGS))]>,
880 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
881 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
882 "cmovb\t{$src2, $dst|$dst, $src2}",
883 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
884 X86_COND_B, EFLAGS))]>,
886 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
887 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
888 "cmovae\t{$src2, $dst|$dst, $src2}",
889 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
890 X86_COND_AE, EFLAGS))]>,
892 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
893 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
894 "cmovae\t{$src2, $dst|$dst, $src2}",
895 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
896 X86_COND_AE, EFLAGS))]>,
898 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
899 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
900 "cmove\t{$src2, $dst|$dst, $src2}",
901 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
902 X86_COND_E, EFLAGS))]>,
904 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
905 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
906 "cmove\t{$src2, $dst|$dst, $src2}",
907 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
908 X86_COND_E, EFLAGS))]>,
910 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
911 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
912 "cmovne\t{$src2, $dst|$dst, $src2}",
913 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
914 X86_COND_NE, EFLAGS))]>,
916 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
917 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
918 "cmovne\t{$src2, $dst|$dst, $src2}",
919 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
920 X86_COND_NE, EFLAGS))]>,
922 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
923 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
924 "cmovbe\t{$src2, $dst|$dst, $src2}",
925 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
926 X86_COND_BE, EFLAGS))]>,
928 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
929 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
930 "cmovbe\t{$src2, $dst|$dst, $src2}",
931 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
932 X86_COND_BE, EFLAGS))]>,
934 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
935 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
936 "cmova\t{$src2, $dst|$dst, $src2}",
937 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
938 X86_COND_A, EFLAGS))]>,
940 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
941 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
942 "cmova\t{$src2, $dst|$dst, $src2}",
943 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
944 X86_COND_A, EFLAGS))]>,
946 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
947 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
948 "cmovl\t{$src2, $dst|$dst, $src2}",
949 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
950 X86_COND_L, EFLAGS))]>,
952 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
953 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
954 "cmovl\t{$src2, $dst|$dst, $src2}",
955 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
956 X86_COND_L, EFLAGS))]>,
958 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
959 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
960 "cmovge\t{$src2, $dst|$dst, $src2}",
961 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
962 X86_COND_GE, EFLAGS))]>,
964 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
965 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
966 "cmovge\t{$src2, $dst|$dst, $src2}",
967 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
968 X86_COND_GE, EFLAGS))]>,
970 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
971 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
972 "cmovle\t{$src2, $dst|$dst, $src2}",
973 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
974 X86_COND_LE, EFLAGS))]>,
976 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
977 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
978 "cmovle\t{$src2, $dst|$dst, $src2}",
979 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
980 X86_COND_LE, EFLAGS))]>,
982 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
983 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
984 "cmovg\t{$src2, $dst|$dst, $src2}",
985 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
986 X86_COND_G, EFLAGS))]>,
988 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
989 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
990 "cmovg\t{$src2, $dst|$dst, $src2}",
991 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
992 X86_COND_G, EFLAGS))]>,
994 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
995 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
996 "cmovs\t{$src2, $dst|$dst, $src2}",
997 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
998 X86_COND_S, EFLAGS))]>,
1000 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1001 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1002 "cmovs\t{$src2, $dst|$dst, $src2}",
1003 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1004 X86_COND_S, EFLAGS))]>,
1006 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1007 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1008 "cmovns\t{$src2, $dst|$dst, $src2}",
1009 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1010 X86_COND_NS, EFLAGS))]>,
1012 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1013 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1014 "cmovns\t{$src2, $dst|$dst, $src2}",
1015 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1016 X86_COND_NS, EFLAGS))]>,
1018 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1019 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1020 "cmovp\t{$src2, $dst|$dst, $src2}",
1021 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1022 X86_COND_P, EFLAGS))]>,
1024 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1025 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1026 "cmovp\t{$src2, $dst|$dst, $src2}",
1027 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1028 X86_COND_P, EFLAGS))]>,
1030 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1031 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1032 "cmovnp\t{$src2, $dst|$dst, $src2}",
1033 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1034 X86_COND_NP, EFLAGS))]>,
1036 } // Uses = [EFLAGS]
1039 // unary instructions
1040 let CodeSize = 2 in {
1041 let Defs = [EFLAGS] in {
1042 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1043 [(set GR8:$dst, (ineg GR8:$src))]>;
1044 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1045 [(set GR16:$dst, (ineg GR16:$src))]>, OpSize;
1046 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1047 [(set GR32:$dst, (ineg GR32:$src))]>;
1048 let isTwoAddress = 0 in {
1049 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1050 [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
1051 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1052 [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1053 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1054 [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
1057 } // Defs = [EFLAGS]
1059 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1060 [(set GR8:$dst, (not GR8:$src))]>;
1061 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1062 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1063 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1064 [(set GR32:$dst, (not GR32:$src))]>;
1065 let isTwoAddress = 0 in {
1066 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1067 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1068 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1069 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1070 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1071 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1075 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1076 let Defs = [EFLAGS] in {
1078 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1079 [(set GR8:$dst, (add GR8:$src, 1))]>;
1080 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1081 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1082 [(set GR16:$dst, (add GR16:$src, 1))]>,
1083 OpSize, Requires<[In32BitMode]>;
1084 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1085 [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>;
1087 let isTwoAddress = 0, CodeSize = 2 in {
1088 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1089 [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
1090 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1091 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>,
1092 OpSize, Requires<[In32BitMode]>;
1093 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1094 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>,
1095 Requires<[In32BitMode]>;
1099 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1100 [(set GR8:$dst, (add GR8:$src, -1))]>;
1101 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1102 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1103 [(set GR16:$dst, (add GR16:$src, -1))]>,
1104 OpSize, Requires<[In32BitMode]>;
1105 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1106 [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>;
1109 let isTwoAddress = 0, CodeSize = 2 in {
1110 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1111 [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
1112 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1113 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>,
1114 OpSize, Requires<[In32BitMode]>;
1115 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1116 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>,
1117 Requires<[In32BitMode]>;
1119 } // Defs = [EFLAGS]
1121 // Logical operators...
1122 let Defs = [EFLAGS] in {
1123 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1124 def AND8rr : I<0x20, MRMDestReg,
1125 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1126 "and{b}\t{$src2, $dst|$dst, $src2}",
1127 [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>;
1128 def AND16rr : I<0x21, MRMDestReg,
1129 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1130 "and{w}\t{$src2, $dst|$dst, $src2}",
1131 [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize;
1132 def AND32rr : I<0x21, MRMDestReg,
1133 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1134 "and{l}\t{$src2, $dst|$dst, $src2}",
1135 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
1138 def AND8rm : I<0x22, MRMSrcMem,
1139 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1140 "and{b}\t{$src2, $dst|$dst, $src2}",
1141 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>;
1142 def AND16rm : I<0x23, MRMSrcMem,
1143 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1144 "and{w}\t{$src2, $dst|$dst, $src2}",
1145 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize;
1146 def AND32rm : I<0x23, MRMSrcMem,
1147 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1148 "and{l}\t{$src2, $dst|$dst, $src2}",
1149 [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>;
1151 def AND8ri : Ii8<0x80, MRM4r,
1152 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1153 "and{b}\t{$src2, $dst|$dst, $src2}",
1154 [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>;
1155 def AND16ri : Ii16<0x81, MRM4r,
1156 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1157 "and{w}\t{$src2, $dst|$dst, $src2}",
1158 [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize;
1159 def AND32ri : Ii32<0x81, MRM4r,
1160 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1161 "and{l}\t{$src2, $dst|$dst, $src2}",
1162 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
1163 def AND16ri8 : Ii8<0x83, MRM4r,
1164 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1165 "and{w}\t{$src2, $dst|$dst, $src2}",
1166 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>,
1168 def AND32ri8 : Ii8<0x83, MRM4r,
1169 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1170 "and{l}\t{$src2, $dst|$dst, $src2}",
1171 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>;
1173 let isTwoAddress = 0 in {
1174 def AND8mr : I<0x20, MRMDestMem,
1175 (outs), (ins i8mem :$dst, GR8 :$src),
1176 "and{b}\t{$src, $dst|$dst, $src}",
1177 [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>;
1178 def AND16mr : I<0x21, MRMDestMem,
1179 (outs), (ins i16mem:$dst, GR16:$src),
1180 "and{w}\t{$src, $dst|$dst, $src}",
1181 [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>,
1183 def AND32mr : I<0x21, MRMDestMem,
1184 (outs), (ins i32mem:$dst, GR32:$src),
1185 "and{l}\t{$src, $dst|$dst, $src}",
1186 [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>;
1187 def AND8mi : Ii8<0x80, MRM4m,
1188 (outs), (ins i8mem :$dst, i8imm :$src),
1189 "and{b}\t{$src, $dst|$dst, $src}",
1190 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1191 def AND16mi : Ii16<0x81, MRM4m,
1192 (outs), (ins i16mem:$dst, i16imm:$src),
1193 "and{w}\t{$src, $dst|$dst, $src}",
1194 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1196 def AND32mi : Ii32<0x81, MRM4m,
1197 (outs), (ins i32mem:$dst, i32imm:$src),
1198 "and{l}\t{$src, $dst|$dst, $src}",
1199 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1200 def AND16mi8 : Ii8<0x83, MRM4m,
1201 (outs), (ins i16mem:$dst, i16i8imm :$src),
1202 "and{w}\t{$src, $dst|$dst, $src}",
1203 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1205 def AND32mi8 : Ii8<0x83, MRM4m,
1206 (outs), (ins i32mem:$dst, i32i8imm :$src),
1207 "and{l}\t{$src, $dst|$dst, $src}",
1208 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1212 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1213 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1214 "or{b}\t{$src2, $dst|$dst, $src2}",
1215 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
1216 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1217 "or{w}\t{$src2, $dst|$dst, $src2}",
1218 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize;
1219 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1220 "or{l}\t{$src2, $dst|$dst, $src2}",
1221 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
1223 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1224 "or{b}\t{$src2, $dst|$dst, $src2}",
1225 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
1226 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1227 "or{w}\t{$src2, $dst|$dst, $src2}",
1228 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize;
1229 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1230 "or{l}\t{$src2, $dst|$dst, $src2}",
1231 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>;
1233 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1234 "or{b}\t{$src2, $dst|$dst, $src2}",
1235 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
1236 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1237 "or{w}\t{$src2, $dst|$dst, $src2}",
1238 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize;
1239 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1240 "or{l}\t{$src2, $dst|$dst, $src2}",
1241 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
1243 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1244 "or{w}\t{$src2, $dst|$dst, $src2}",
1245 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1246 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1247 "or{l}\t{$src2, $dst|$dst, $src2}",
1248 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>;
1249 let isTwoAddress = 0 in {
1250 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1251 "or{b}\t{$src, $dst|$dst, $src}",
1252 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
1253 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1254 "or{w}\t{$src, $dst|$dst, $src}",
1255 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize;
1256 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1257 "or{l}\t{$src, $dst|$dst, $src}",
1258 [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>;
1259 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1260 "or{b}\t{$src, $dst|$dst, $src}",
1261 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1262 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1263 "or{w}\t{$src, $dst|$dst, $src}",
1264 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1266 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1267 "or{l}\t{$src, $dst|$dst, $src}",
1268 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1269 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1270 "or{w}\t{$src, $dst|$dst, $src}",
1271 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1273 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1274 "or{l}\t{$src, $dst|$dst, $src}",
1275 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1279 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1280 def XOR8rr : I<0x30, MRMDestReg,
1281 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1282 "xor{b}\t{$src2, $dst|$dst, $src2}",
1283 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>;
1284 def XOR16rr : I<0x31, MRMDestReg,
1285 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1286 "xor{w}\t{$src2, $dst|$dst, $src2}",
1287 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize;
1288 def XOR32rr : I<0x31, MRMDestReg,
1289 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1290 "xor{l}\t{$src2, $dst|$dst, $src2}",
1291 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
1294 def XOR8rm : I<0x32, MRMSrcMem ,
1295 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1296 "xor{b}\t{$src2, $dst|$dst, $src2}",
1297 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>;
1298 def XOR16rm : I<0x33, MRMSrcMem ,
1299 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1300 "xor{w}\t{$src2, $dst|$dst, $src2}",
1301 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>, OpSize;
1302 def XOR32rm : I<0x33, MRMSrcMem ,
1303 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1304 "xor{l}\t{$src2, $dst|$dst, $src2}",
1305 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>;
1307 def XOR8ri : Ii8<0x80, MRM6r,
1308 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1309 "xor{b}\t{$src2, $dst|$dst, $src2}",
1310 [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>;
1311 def XOR16ri : Ii16<0x81, MRM6r,
1312 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1313 "xor{w}\t{$src2, $dst|$dst, $src2}",
1314 [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize;
1315 def XOR32ri : Ii32<0x81, MRM6r,
1316 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1317 "xor{l}\t{$src2, $dst|$dst, $src2}",
1318 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
1319 def XOR16ri8 : Ii8<0x83, MRM6r,
1320 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1321 "xor{w}\t{$src2, $dst|$dst, $src2}",
1322 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>,
1324 def XOR32ri8 : Ii8<0x83, MRM6r,
1325 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1326 "xor{l}\t{$src2, $dst|$dst, $src2}",
1327 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>;
1328 let isTwoAddress = 0 in {
1329 def XOR8mr : I<0x30, MRMDestMem,
1330 (outs), (ins i8mem :$dst, GR8 :$src),
1331 "xor{b}\t{$src, $dst|$dst, $src}",
1332 [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>;
1333 def XOR16mr : I<0x31, MRMDestMem,
1334 (outs), (ins i16mem:$dst, GR16:$src),
1335 "xor{w}\t{$src, $dst|$dst, $src}",
1336 [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>,
1338 def XOR32mr : I<0x31, MRMDestMem,
1339 (outs), (ins i32mem:$dst, GR32:$src),
1340 "xor{l}\t{$src, $dst|$dst, $src}",
1341 [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>;
1342 def XOR8mi : Ii8<0x80, MRM6m,
1343 (outs), (ins i8mem :$dst, i8imm :$src),
1344 "xor{b}\t{$src, $dst|$dst, $src}",
1345 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1346 def XOR16mi : Ii16<0x81, MRM6m,
1347 (outs), (ins i16mem:$dst, i16imm:$src),
1348 "xor{w}\t{$src, $dst|$dst, $src}",
1349 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1351 def XOR32mi : Ii32<0x81, MRM6m,
1352 (outs), (ins i32mem:$dst, i32imm:$src),
1353 "xor{l}\t{$src, $dst|$dst, $src}",
1354 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1355 def XOR16mi8 : Ii8<0x83, MRM6m,
1356 (outs), (ins i16mem:$dst, i16i8imm :$src),
1357 "xor{w}\t{$src, $dst|$dst, $src}",
1358 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1360 def XOR32mi8 : Ii8<0x83, MRM6m,
1361 (outs), (ins i32mem:$dst, i32i8imm :$src),
1362 "xor{l}\t{$src, $dst|$dst, $src}",
1363 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1365 } // Defs = [EFLAGS]
1367 // Shift instructions
1368 let Defs = [EFLAGS] in {
1369 let Uses = [CL] in {
1370 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1371 "shl{b}\t{%cl, $dst|$dst, %CL}",
1372 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1373 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1374 "shl{w}\t{%cl, $dst|$dst, %CL}",
1375 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1376 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1377 "shl{l}\t{%cl, $dst|$dst, %CL}",
1378 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1381 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1382 "shl{b}\t{$src2, $dst|$dst, $src2}",
1383 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1384 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1385 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1386 "shl{w}\t{$src2, $dst|$dst, $src2}",
1387 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1388 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1389 "shl{l}\t{$src2, $dst|$dst, $src2}",
1390 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1391 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1395 let isTwoAddress = 0 in {
1396 let Uses = [CL] in {
1397 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1398 "shl{b}\t{%cl, $dst|$dst, %CL}",
1399 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1400 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1401 "shl{w}\t{%cl, $dst|$dst, %CL}",
1402 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1403 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1404 "shl{l}\t{%cl, $dst|$dst, %CL}",
1405 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1407 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1408 "shl{b}\t{$src, $dst|$dst, $src}",
1409 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1410 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1411 "shl{w}\t{$src, $dst|$dst, $src}",
1412 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1414 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1415 "shl{l}\t{$src, $dst|$dst, $src}",
1416 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1419 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1421 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1422 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1424 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1426 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1428 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1431 let Uses = [CL] in {
1432 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1433 "shr{b}\t{%cl, $dst|$dst, %CL}",
1434 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1435 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1436 "shr{w}\t{%cl, $dst|$dst, %CL}",
1437 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1438 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1439 "shr{l}\t{%cl, $dst|$dst, %CL}",
1440 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1443 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1444 "shr{b}\t{$src2, $dst|$dst, $src2}",
1445 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1446 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1447 "shr{w}\t{$src2, $dst|$dst, $src2}",
1448 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1449 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1450 "shr{l}\t{$src2, $dst|$dst, $src2}",
1451 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1454 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1456 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1457 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1459 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1460 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1462 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1464 let isTwoAddress = 0 in {
1465 let Uses = [CL] in {
1466 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1467 "shr{b}\t{%cl, $dst|$dst, %CL}",
1468 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1469 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1470 "shr{w}\t{%cl, $dst|$dst, %CL}",
1471 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1473 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1474 "shr{l}\t{%cl, $dst|$dst, %CL}",
1475 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1477 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1478 "shr{b}\t{$src, $dst|$dst, $src}",
1479 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1480 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1481 "shr{w}\t{$src, $dst|$dst, $src}",
1482 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1484 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1485 "shr{l}\t{$src, $dst|$dst, $src}",
1486 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1489 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1491 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1492 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1494 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1495 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1497 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1500 let Uses = [CL] in {
1501 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1502 "sar{b}\t{%cl, $dst|$dst, %CL}",
1503 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1504 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1505 "sar{w}\t{%cl, $dst|$dst, %CL}",
1506 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1507 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1508 "sar{l}\t{%cl, $dst|$dst, %CL}",
1509 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1512 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1513 "sar{b}\t{$src2, $dst|$dst, $src2}",
1514 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1515 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1516 "sar{w}\t{$src2, $dst|$dst, $src2}",
1517 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1519 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1520 "sar{l}\t{$src2, $dst|$dst, $src2}",
1521 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1524 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1526 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1527 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1529 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1530 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1532 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1534 let isTwoAddress = 0 in {
1535 let Uses = [CL] in {
1536 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1537 "sar{b}\t{%cl, $dst|$dst, %CL}",
1538 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
1539 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1540 "sar{w}\t{%cl, $dst|$dst, %CL}",
1541 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1542 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1543 "sar{l}\t{%cl, $dst|$dst, %CL}",
1544 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1546 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1547 "sar{b}\t{$src, $dst|$dst, $src}",
1548 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1549 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1550 "sar{w}\t{$src, $dst|$dst, $src}",
1551 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1553 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1554 "sar{l}\t{$src, $dst|$dst, $src}",
1555 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1558 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1560 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1561 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1563 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1565 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
1567 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1570 // Rotate instructions
1571 // FIXME: provide shorter instructions when imm8 == 1
1572 let Uses = [CL] in {
1573 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
1574 "rol{b}\t{%cl, $dst|$dst, %CL}",
1575 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
1576 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
1577 "rol{w}\t{%cl, $dst|$dst, %CL}",
1578 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
1579 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
1580 "rol{l}\t{%cl, $dst|$dst, %CL}",
1581 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
1584 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1585 "rol{b}\t{$src2, $dst|$dst, $src2}",
1586 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1587 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1588 "rol{w}\t{$src2, $dst|$dst, $src2}",
1589 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1590 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1591 "rol{l}\t{$src2, $dst|$dst, $src2}",
1592 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1595 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1597 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1598 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
1600 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1601 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1603 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1605 let isTwoAddress = 0 in {
1606 let Uses = [CL] in {
1607 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
1608 "rol{b}\t{%cl, $dst|$dst, %CL}",
1609 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
1610 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
1611 "rol{w}\t{%cl, $dst|$dst, %CL}",
1612 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1613 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
1614 "rol{l}\t{%cl, $dst|$dst, %CL}",
1615 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
1617 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
1618 "rol{b}\t{$src, $dst|$dst, $src}",
1619 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1620 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
1621 "rol{w}\t{$src, $dst|$dst, $src}",
1622 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1624 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
1625 "rol{l}\t{$src, $dst|$dst, $src}",
1626 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1629 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
1631 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1632 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
1634 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1636 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
1638 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1641 let Uses = [CL] in {
1642 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
1643 "ror{b}\t{%cl, $dst|$dst, %CL}",
1644 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
1645 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
1646 "ror{w}\t{%cl, $dst|$dst, %CL}",
1647 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
1648 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
1649 "ror{l}\t{%cl, $dst|$dst, %CL}",
1650 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
1653 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1654 "ror{b}\t{$src2, $dst|$dst, $src2}",
1655 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
1656 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1657 "ror{w}\t{$src2, $dst|$dst, $src2}",
1658 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1659 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1660 "ror{l}\t{$src2, $dst|$dst, $src2}",
1661 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
1664 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1666 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
1667 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
1669 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
1670 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
1672 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
1674 let isTwoAddress = 0 in {
1675 let Uses = [CL] in {
1676 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
1677 "ror{b}\t{%cl, $dst|$dst, %CL}",
1678 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
1679 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
1680 "ror{w}\t{%cl, $dst|$dst, %CL}",
1681 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1682 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
1683 "ror{l}\t{%cl, $dst|$dst, %CL}",
1684 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
1686 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1687 "ror{b}\t{$src, $dst|$dst, $src}",
1688 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1689 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
1690 "ror{w}\t{$src, $dst|$dst, $src}",
1691 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1693 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
1694 "ror{l}\t{$src, $dst|$dst, $src}",
1695 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1698 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
1700 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1701 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
1703 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1705 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
1707 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1712 // Double shift instructions (generalizations of rotate)
1713 let Uses = [CL] in {
1714 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1715 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1716 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
1717 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1718 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1719 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
1720 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1721 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1722 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
1724 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1725 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1726 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
1730 let isCommutable = 1 in { // These instructions commute to each other.
1731 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
1732 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1733 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1734 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
1737 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
1738 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1739 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1740 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
1743 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
1744 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1745 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1746 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
1749 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
1750 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1751 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1752 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
1757 let isTwoAddress = 0 in {
1758 let Uses = [CL] in {
1759 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1760 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1761 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
1763 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1764 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1765 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
1768 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
1769 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1770 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1771 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
1772 (i8 imm:$src3)), addr:$dst)]>,
1774 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
1775 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1776 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1777 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
1778 (i8 imm:$src3)), addr:$dst)]>,
1781 let Uses = [CL] in {
1782 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1783 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1784 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
1785 addr:$dst)]>, TB, OpSize;
1786 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1787 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1788 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
1789 addr:$dst)]>, TB, OpSize;
1791 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
1792 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1793 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1794 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
1795 (i8 imm:$src3)), addr:$dst)]>,
1797 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
1798 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1799 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1800 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
1801 (i8 imm:$src3)), addr:$dst)]>,
1804 } // Defs = [EFLAGS]
1808 let Defs = [EFLAGS] in {
1809 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1810 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
1811 (ins GR8 :$src1, GR8 :$src2),
1812 "add{b}\t{$src2, $dst|$dst, $src2}",
1813 [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>;
1814 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1815 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
1816 (ins GR16:$src1, GR16:$src2),
1817 "add{w}\t{$src2, $dst|$dst, $src2}",
1818 [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize;
1819 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
1820 (ins GR32:$src1, GR32:$src2),
1821 "add{l}\t{$src2, $dst|$dst, $src2}",
1822 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
1823 } // end isConvertibleToThreeAddress
1824 } // end isCommutable
1825 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
1826 (ins GR8 :$src1, i8mem :$src2),
1827 "add{b}\t{$src2, $dst|$dst, $src2}",
1828 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>;
1829 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
1830 (ins GR16:$src1, i16mem:$src2),
1831 "add{w}\t{$src2, $dst|$dst, $src2}",
1832 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>,OpSize;
1833 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
1834 (ins GR32:$src1, i32mem:$src2),
1835 "add{l}\t{$src2, $dst|$dst, $src2}",
1836 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>;
1838 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1839 "add{b}\t{$src2, $dst|$dst, $src2}",
1840 [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>;
1842 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1843 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
1844 (ins GR16:$src1, i16imm:$src2),
1845 "add{w}\t{$src2, $dst|$dst, $src2}",
1846 [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize;
1847 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
1848 (ins GR32:$src1, i32imm:$src2),
1849 "add{l}\t{$src2, $dst|$dst, $src2}",
1850 [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>;
1851 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
1852 (ins GR16:$src1, i16i8imm:$src2),
1853 "add{w}\t{$src2, $dst|$dst, $src2}",
1854 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1855 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
1856 (ins GR32:$src1, i32i8imm:$src2),
1857 "add{l}\t{$src2, $dst|$dst, $src2}",
1858 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>;
1861 let isTwoAddress = 0 in {
1862 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1863 "add{b}\t{$src2, $dst|$dst, $src2}",
1864 [(store (add (load addr:$dst), GR8:$src2), addr:$dst)]>;
1865 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1866 "add{w}\t{$src2, $dst|$dst, $src2}",
1867 [(store (add (load addr:$dst), GR16:$src2), addr:$dst)]>,
1869 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1870 "add{l}\t{$src2, $dst|$dst, $src2}",
1871 [(store (add (load addr:$dst), GR32:$src2), addr:$dst)]>;
1872 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
1873 "add{b}\t{$src2, $dst|$dst, $src2}",
1874 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1875 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
1876 "add{w}\t{$src2, $dst|$dst, $src2}",
1877 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1879 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
1880 "add{l}\t{$src2, $dst|$dst, $src2}",
1881 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1882 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1883 "add{w}\t{$src2, $dst|$dst, $src2}",
1884 [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1886 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1887 "add{l}\t{$src2, $dst|$dst, $src2}",
1888 [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1891 let Uses = [EFLAGS] in {
1892 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1893 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1894 "adc{l}\t{$src2, $dst|$dst, $src2}",
1895 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
1897 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1898 "adc{l}\t{$src2, $dst|$dst, $src2}",
1899 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
1900 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1901 "adc{l}\t{$src2, $dst|$dst, $src2}",
1902 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
1903 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1904 "adc{l}\t{$src2, $dst|$dst, $src2}",
1905 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
1907 let isTwoAddress = 0 in {
1908 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1909 "adc{l}\t{$src2, $dst|$dst, $src2}",
1910 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
1911 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
1912 "adc{l}\t{$src2, $dst|$dst, $src2}",
1913 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1914 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1915 "adc{l}\t{$src2, $dst|$dst, $src2}",
1916 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1918 } // Uses = [EFLAGS]
1920 def SUB8rr : I<0x28, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1921 "sub{b}\t{$src2, $dst|$dst, $src2}",
1922 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2))]>;
1923 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1924 "sub{w}\t{$src2, $dst|$dst, $src2}",
1925 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2))]>, OpSize;
1926 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1927 "sub{l}\t{$src2, $dst|$dst, $src2}",
1928 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
1929 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1930 "sub{b}\t{$src2, $dst|$dst, $src2}",
1931 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2)))]>;
1932 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1933 "sub{w}\t{$src2, $dst|$dst, $src2}",
1934 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2)))]>, OpSize;
1935 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1936 "sub{l}\t{$src2, $dst|$dst, $src2}",
1937 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2)))]>;
1939 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1940 "sub{b}\t{$src2, $dst|$dst, $src2}",
1941 [(set GR8:$dst, (sub GR8:$src1, imm:$src2))]>;
1942 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1943 "sub{w}\t{$src2, $dst|$dst, $src2}",
1944 [(set GR16:$dst, (sub GR16:$src1, imm:$src2))]>, OpSize;
1945 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1946 "sub{l}\t{$src2, $dst|$dst, $src2}",
1947 [(set GR32:$dst, (sub GR32:$src1, imm:$src2))]>;
1948 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1949 "sub{w}\t{$src2, $dst|$dst, $src2}",
1950 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2))]>,
1952 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1953 "sub{l}\t{$src2, $dst|$dst, $src2}",
1954 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2))]>;
1955 let isTwoAddress = 0 in {
1956 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1957 "sub{b}\t{$src2, $dst|$dst, $src2}",
1958 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst)]>;
1959 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1960 "sub{w}\t{$src2, $dst|$dst, $src2}",
1961 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst)]>,
1963 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1964 "sub{l}\t{$src2, $dst|$dst, $src2}",
1965 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst)]>;
1966 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
1967 "sub{b}\t{$src2, $dst|$dst, $src2}",
1968 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1969 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
1970 "sub{w}\t{$src2, $dst|$dst, $src2}",
1971 [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1973 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
1974 "sub{l}\t{$src2, $dst|$dst, $src2}",
1975 [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1976 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1977 "sub{w}\t{$src2, $dst|$dst, $src2}",
1978 [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1980 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1981 "sub{l}\t{$src2, $dst|$dst, $src2}",
1982 [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1985 let Uses = [EFLAGS] in {
1986 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1987 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1988 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
1990 let isTwoAddress = 0 in {
1991 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1992 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1993 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
1994 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
1995 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1996 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1997 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
1998 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1999 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2000 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2001 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2002 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2004 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2005 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2006 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2007 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2008 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2009 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2010 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2011 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2012 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2013 } // Uses = [EFLAGS]
2014 } // Defs = [EFLAGS]
2016 let Defs = [EFLAGS] in {
2017 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2018 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2019 "imul{w}\t{$src2, $dst|$dst, $src2}",
2020 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2))]>, TB, OpSize;
2021 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2022 "imul{l}\t{$src2, $dst|$dst, $src2}",
2023 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>, TB;
2025 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2026 "imul{w}\t{$src2, $dst|$dst, $src2}",
2027 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2)))]>,
2029 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2030 "imul{l}\t{$src2, $dst|$dst, $src2}",
2031 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2)))]>, TB;
2032 } // Defs = [EFLAGS]
2033 } // end Two Address instructions
2035 // Suprisingly enough, these are not two address instructions!
2036 let Defs = [EFLAGS] in {
2037 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2038 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2039 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2040 [(set GR16:$dst, (mul GR16:$src1, imm:$src2))]>, OpSize;
2041 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2042 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2043 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2044 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
2045 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2046 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2047 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2048 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2))]>,
2050 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2051 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2052 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2053 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2))]>;
2055 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2056 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2057 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2058 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2))]>,
2060 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2061 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2062 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2063 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2))]>;
2064 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2065 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2066 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2067 [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>,
2069 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2070 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2071 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2072 [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>;
2073 } // Defs = [EFLAGS]
2075 //===----------------------------------------------------------------------===//
2076 // Test instructions are just like AND, except they don't generate a result.
2078 let Defs = [EFLAGS] in {
2079 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2080 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2081 "test{b}\t{$src2, $src1|$src1, $src2}",
2082 [(X86cmp (and GR8:$src1, GR8:$src2), 0),
2083 (implicit EFLAGS)]>;
2084 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2085 "test{w}\t{$src2, $src1|$src1, $src2}",
2086 [(X86cmp (and GR16:$src1, GR16:$src2), 0),
2087 (implicit EFLAGS)]>,
2089 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2090 "test{l}\t{$src2, $src1|$src1, $src2}",
2091 [(X86cmp (and GR32:$src1, GR32:$src2), 0),
2092 (implicit EFLAGS)]>;
2095 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2096 "test{b}\t{$src2, $src1|$src1, $src2}",
2097 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2098 (implicit EFLAGS)]>;
2099 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2100 "test{w}\t{$src2, $src1|$src1, $src2}",
2101 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2102 (implicit EFLAGS)]>, OpSize;
2103 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2104 "test{l}\t{$src2, $src1|$src1, $src2}",
2105 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2106 (implicit EFLAGS)]>;
2108 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2109 (outs), (ins GR8:$src1, i8imm:$src2),
2110 "test{b}\t{$src2, $src1|$src1, $src2}",
2111 [(X86cmp (and GR8:$src1, imm:$src2), 0),
2112 (implicit EFLAGS)]>;
2113 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2114 (outs), (ins GR16:$src1, i16imm:$src2),
2115 "test{w}\t{$src2, $src1|$src1, $src2}",
2116 [(X86cmp (and GR16:$src1, imm:$src2), 0),
2117 (implicit EFLAGS)]>, OpSize;
2118 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2119 (outs), (ins GR32:$src1, i32imm:$src2),
2120 "test{l}\t{$src2, $src1|$src1, $src2}",
2121 [(X86cmp (and GR32:$src1, imm:$src2), 0),
2122 (implicit EFLAGS)]>;
2124 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2125 (outs), (ins i8mem:$src1, i8imm:$src2),
2126 "test{b}\t{$src2, $src1|$src1, $src2}",
2127 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2128 (implicit EFLAGS)]>;
2129 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2130 (outs), (ins i16mem:$src1, i16imm:$src2),
2131 "test{w}\t{$src2, $src1|$src1, $src2}",
2132 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2133 (implicit EFLAGS)]>, OpSize;
2134 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2135 (outs), (ins i32mem:$src1, i32imm:$src2),
2136 "test{l}\t{$src2, $src1|$src1, $src2}",
2137 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2138 (implicit EFLAGS)]>;
2139 } // Defs = [EFLAGS]
2142 // Condition code ops, incl. set if equal/not equal/...
2143 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2144 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2145 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2146 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2148 let Uses = [EFLAGS] in {
2149 def SETEr : I<0x94, MRM0r,
2150 (outs GR8 :$dst), (ins),
2152 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2154 def SETEm : I<0x94, MRM0m,
2155 (outs), (ins i8mem:$dst),
2157 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2159 def SETNEr : I<0x95, MRM0r,
2160 (outs GR8 :$dst), (ins),
2162 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2164 def SETNEm : I<0x95, MRM0m,
2165 (outs), (ins i8mem:$dst),
2167 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2169 def SETLr : I<0x9C, MRM0r,
2170 (outs GR8 :$dst), (ins),
2172 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2173 TB; // GR8 = < signed
2174 def SETLm : I<0x9C, MRM0m,
2175 (outs), (ins i8mem:$dst),
2177 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2178 TB; // [mem8] = < signed
2179 def SETGEr : I<0x9D, MRM0r,
2180 (outs GR8 :$dst), (ins),
2182 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2183 TB; // GR8 = >= signed
2184 def SETGEm : I<0x9D, MRM0m,
2185 (outs), (ins i8mem:$dst),
2187 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2188 TB; // [mem8] = >= signed
2189 def SETLEr : I<0x9E, MRM0r,
2190 (outs GR8 :$dst), (ins),
2192 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2193 TB; // GR8 = <= signed
2194 def SETLEm : I<0x9E, MRM0m,
2195 (outs), (ins i8mem:$dst),
2197 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2198 TB; // [mem8] = <= signed
2199 def SETGr : I<0x9F, MRM0r,
2200 (outs GR8 :$dst), (ins),
2202 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2203 TB; // GR8 = > signed
2204 def SETGm : I<0x9F, MRM0m,
2205 (outs), (ins i8mem:$dst),
2207 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2208 TB; // [mem8] = > signed
2210 def SETBr : I<0x92, MRM0r,
2211 (outs GR8 :$dst), (ins),
2213 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2214 TB; // GR8 = < unsign
2215 def SETBm : I<0x92, MRM0m,
2216 (outs), (ins i8mem:$dst),
2218 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
2219 TB; // [mem8] = < unsign
2220 def SETAEr : I<0x93, MRM0r,
2221 (outs GR8 :$dst), (ins),
2223 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
2224 TB; // GR8 = >= unsign
2225 def SETAEm : I<0x93, MRM0m,
2226 (outs), (ins i8mem:$dst),
2228 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
2229 TB; // [mem8] = >= unsign
2230 def SETBEr : I<0x96, MRM0r,
2231 (outs GR8 :$dst), (ins),
2233 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
2234 TB; // GR8 = <= unsign
2235 def SETBEm : I<0x96, MRM0m,
2236 (outs), (ins i8mem:$dst),
2238 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
2239 TB; // [mem8] = <= unsign
2240 def SETAr : I<0x97, MRM0r,
2241 (outs GR8 :$dst), (ins),
2243 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
2244 TB; // GR8 = > signed
2245 def SETAm : I<0x97, MRM0m,
2246 (outs), (ins i8mem:$dst),
2248 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
2249 TB; // [mem8] = > signed
2251 def SETSr : I<0x98, MRM0r,
2252 (outs GR8 :$dst), (ins),
2254 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
2255 TB; // GR8 = <sign bit>
2256 def SETSm : I<0x98, MRM0m,
2257 (outs), (ins i8mem:$dst),
2259 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
2260 TB; // [mem8] = <sign bit>
2261 def SETNSr : I<0x99, MRM0r,
2262 (outs GR8 :$dst), (ins),
2264 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
2265 TB; // GR8 = !<sign bit>
2266 def SETNSm : I<0x99, MRM0m,
2267 (outs), (ins i8mem:$dst),
2269 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
2270 TB; // [mem8] = !<sign bit>
2271 def SETPr : I<0x9A, MRM0r,
2272 (outs GR8 :$dst), (ins),
2274 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
2276 def SETPm : I<0x9A, MRM0m,
2277 (outs), (ins i8mem:$dst),
2279 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
2280 TB; // [mem8] = parity
2281 def SETNPr : I<0x9B, MRM0r,
2282 (outs GR8 :$dst), (ins),
2284 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
2285 TB; // GR8 = not parity
2286 def SETNPm : I<0x9B, MRM0m,
2287 (outs), (ins i8mem:$dst),
2289 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
2290 TB; // [mem8] = not parity
2291 } // Uses = [EFLAGS]
2294 // Integer comparisons
2295 let Defs = [EFLAGS] in {
2296 def CMP8rr : I<0x38, MRMDestReg,
2297 (outs), (ins GR8 :$src1, GR8 :$src2),
2298 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2299 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2300 def CMP16rr : I<0x39, MRMDestReg,
2301 (outs), (ins GR16:$src1, GR16:$src2),
2302 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2303 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
2304 def CMP32rr : I<0x39, MRMDestReg,
2305 (outs), (ins GR32:$src1, GR32:$src2),
2306 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2307 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
2308 def CMP8mr : I<0x38, MRMDestMem,
2309 (outs), (ins i8mem :$src1, GR8 :$src2),
2310 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2311 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
2312 (implicit EFLAGS)]>;
2313 def CMP16mr : I<0x39, MRMDestMem,
2314 (outs), (ins i16mem:$src1, GR16:$src2),
2315 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2316 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
2317 (implicit EFLAGS)]>, OpSize;
2318 def CMP32mr : I<0x39, MRMDestMem,
2319 (outs), (ins i32mem:$src1, GR32:$src2),
2320 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2321 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
2322 (implicit EFLAGS)]>;
2323 def CMP8rm : I<0x3A, MRMSrcMem,
2324 (outs), (ins GR8 :$src1, i8mem :$src2),
2325 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2326 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
2327 (implicit EFLAGS)]>;
2328 def CMP16rm : I<0x3B, MRMSrcMem,
2329 (outs), (ins GR16:$src1, i16mem:$src2),
2330 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2331 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
2332 (implicit EFLAGS)]>, OpSize;
2333 def CMP32rm : I<0x3B, MRMSrcMem,
2334 (outs), (ins GR32:$src1, i32mem:$src2),
2335 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2336 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
2337 (implicit EFLAGS)]>;
2338 def CMP8ri : Ii8<0x80, MRM7r,
2339 (outs), (ins GR8:$src1, i8imm:$src2),
2340 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2341 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
2342 def CMP16ri : Ii16<0x81, MRM7r,
2343 (outs), (ins GR16:$src1, i16imm:$src2),
2344 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2345 [(X86cmp GR16:$src1, imm:$src2),
2346 (implicit EFLAGS)]>, OpSize;
2347 def CMP32ri : Ii32<0x81, MRM7r,
2348 (outs), (ins GR32:$src1, i32imm:$src2),
2349 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2350 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
2351 def CMP8mi : Ii8 <0x80, MRM7m,
2352 (outs), (ins i8mem :$src1, i8imm :$src2),
2353 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2354 [(X86cmp (loadi8 addr:$src1), imm:$src2),
2355 (implicit EFLAGS)]>;
2356 def CMP16mi : Ii16<0x81, MRM7m,
2357 (outs), (ins i16mem:$src1, i16imm:$src2),
2358 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2359 [(X86cmp (loadi16 addr:$src1), imm:$src2),
2360 (implicit EFLAGS)]>, OpSize;
2361 def CMP32mi : Ii32<0x81, MRM7m,
2362 (outs), (ins i32mem:$src1, i32imm:$src2),
2363 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2364 [(X86cmp (loadi32 addr:$src1), imm:$src2),
2365 (implicit EFLAGS)]>;
2366 def CMP16ri8 : Ii8<0x83, MRM7r,
2367 (outs), (ins GR16:$src1, i16i8imm:$src2),
2368 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2369 [(X86cmp GR16:$src1, i16immSExt8:$src2),
2370 (implicit EFLAGS)]>, OpSize;
2371 def CMP16mi8 : Ii8<0x83, MRM7m,
2372 (outs), (ins i16mem:$src1, i16i8imm:$src2),
2373 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2374 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
2375 (implicit EFLAGS)]>, OpSize;
2376 def CMP32mi8 : Ii8<0x83, MRM7m,
2377 (outs), (ins i32mem:$src1, i32i8imm:$src2),
2378 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2379 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
2380 (implicit EFLAGS)]>;
2381 def CMP32ri8 : Ii8<0x83, MRM7r,
2382 (outs), (ins GR32:$src1, i32i8imm:$src2),
2383 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2384 [(X86cmp GR32:$src1, i32immSExt8:$src2),
2385 (implicit EFLAGS)]>;
2386 } // Defs = [EFLAGS]
2388 // Sign/Zero extenders
2389 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2390 "movs{bw|x}\t{$src, $dst|$dst, $src}",
2391 [(set GR16:$dst, (sext GR8:$src))]>, TB, OpSize;
2392 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2393 "movs{bw|x}\t{$src, $dst|$dst, $src}",
2394 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize;
2395 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2396 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2397 [(set GR32:$dst, (sext GR8:$src))]>, TB;
2398 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2399 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2400 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
2401 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2402 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2403 [(set GR32:$dst, (sext GR16:$src))]>, TB;
2404 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2405 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2406 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
2408 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2409 "movz{bw|x}\t{$src, $dst|$dst, $src}",
2410 [(set GR16:$dst, (zext GR8:$src))]>, TB, OpSize;
2411 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2412 "movz{bw|x}\t{$src, $dst|$dst, $src}",
2413 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize;
2414 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2415 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2416 [(set GR32:$dst, (zext GR8:$src))]>, TB;
2417 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2418 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2419 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
2420 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2421 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2422 [(set GR32:$dst, (zext GR16:$src))]>, TB;
2423 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2424 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2425 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
2427 let neverHasSideEffects = 1 in {
2428 let Defs = [AX], Uses = [AL] in
2429 def CBW : I<0x98, RawFrm, (outs), (ins),
2430 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
2431 let Defs = [EAX], Uses = [AX] in
2432 def CWDE : I<0x98, RawFrm, (outs), (ins),
2433 "{cwtl|cwde}", []>; // EAX = signext(AX)
2435 let Defs = [AX,DX], Uses = [AX] in
2436 def CWD : I<0x99, RawFrm, (outs), (ins),
2437 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
2438 let Defs = [EAX,EDX], Uses = [EAX] in
2439 def CDQ : I<0x99, RawFrm, (outs), (ins),
2440 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
2443 //===----------------------------------------------------------------------===//
2444 // Alias Instructions
2445 //===----------------------------------------------------------------------===//
2447 // Alias instructions that map movr0 to xor.
2448 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2449 let Defs = [EFLAGS], isReMaterializable = 1 in {
2450 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
2451 "xor{b}\t$dst, $dst",
2452 [(set GR8:$dst, 0)]>;
2453 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
2454 "xor{w}\t$dst, $dst",
2455 [(set GR16:$dst, 0)]>, OpSize;
2456 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
2457 "xor{l}\t$dst, $dst",
2458 [(set GR32:$dst, 0)]>;
2461 // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
2462 // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
2463 let neverHasSideEffects = 1 in {
2464 def MOV16to16_ : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16:$src),
2465 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2466 def MOV32to32_ : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32:$src),
2467 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2469 def MOV16_rr : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16_:$src),
2470 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2471 def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src),
2472 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2473 } // neverHasSideEffects
2475 let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
2476 def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src),
2477 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2478 def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src),
2479 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2481 let mayStore = 1, neverHasSideEffects = 1 in {
2482 def MOV16_mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16_:$src),
2483 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2484 def MOV32_mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32_:$src),
2485 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2488 //===----------------------------------------------------------------------===//
2489 // Thread Local Storage Instructions
2493 def TLS_addr : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
2494 "leal\t${sym:mem}(,%ebx,1), $dst",
2495 [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
2497 let AddedComplexity = 10 in
2498 def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
2499 "movl\t%gs:($src), $dst",
2500 [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
2502 let AddedComplexity = 15 in
2503 def TLS_gs_ri : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
2504 "movl\t%gs:${src:mem}, $dst",
2506 (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>;
2508 def TLS_tp : I<0, Pseudo, (outs GR32:$dst), (ins),
2509 "movl\t%gs:0, $dst",
2510 [(set GR32:$dst, X86TLStp)]>;
2512 //===----------------------------------------------------------------------===//
2513 // DWARF Pseudo Instructions
2516 def DWARF_LOC : I<0, Pseudo, (outs),
2517 (ins i32imm:$line, i32imm:$col, i32imm:$file),
2518 ".loc\t${file:debug} ${line:debug} ${col:debug}",
2519 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
2522 //===----------------------------------------------------------------------===//
2523 // EH Pseudo Instructions
2525 let isTerminator = 1, isReturn = 1, isBarrier = 1,
2527 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
2528 "ret\t#eh_return, addr: $addr",
2529 [(X86ehret GR32:$addr)]>;
2533 //===----------------------------------------------------------------------===//
2534 // Non-Instruction Patterns
2535 //===----------------------------------------------------------------------===//
2537 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
2538 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
2539 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
2540 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)), (MOV32ri tglobaltlsaddr:$dst)>;
2541 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
2542 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
2544 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
2545 (ADD32ri GR32:$src1, tconstpool:$src2)>;
2546 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
2547 (ADD32ri GR32:$src1, tjumptable:$src2)>;
2548 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
2549 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
2550 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
2551 (ADD32ri GR32:$src1, texternalsym:$src2)>;
2553 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
2554 (MOV32mi addr:$dst, tglobaladdr:$src)>;
2555 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
2556 (MOV32mi addr:$dst, texternalsym:$src)>;
2560 def : Pat<(X86tailcall GR32:$dst),
2563 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
2565 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
2568 def : Pat<(X86tcret GR32:$dst, imm:$off),
2569 (TCRETURNri GR32:$dst, imm:$off)>;
2571 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
2572 (TCRETURNdi texternalsym:$dst, imm:$off)>;
2574 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
2575 (TCRETURNdi texternalsym:$dst, imm:$off)>;
2577 def : Pat<(X86call (i32 tglobaladdr:$dst)),
2578 (CALLpcrel32 tglobaladdr:$dst)>;
2579 def : Pat<(X86call (i32 texternalsym:$dst)),
2580 (CALLpcrel32 texternalsym:$dst)>;
2582 // X86 specific add which produces a flag.
2583 def : Pat<(addc GR32:$src1, GR32:$src2),
2584 (ADD32rr GR32:$src1, GR32:$src2)>;
2585 def : Pat<(addc GR32:$src1, (load addr:$src2)),
2586 (ADD32rm GR32:$src1, addr:$src2)>;
2587 def : Pat<(addc GR32:$src1, imm:$src2),
2588 (ADD32ri GR32:$src1, imm:$src2)>;
2589 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
2590 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
2592 def : Pat<(subc GR32:$src1, GR32:$src2),
2593 (SUB32rr GR32:$src1, GR32:$src2)>;
2594 def : Pat<(subc GR32:$src1, (load addr:$src2)),
2595 (SUB32rm GR32:$src1, addr:$src2)>;
2596 def : Pat<(subc GR32:$src1, imm:$src2),
2597 (SUB32ri GR32:$src1, imm:$src2)>;
2598 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
2599 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
2603 // TEST R,R is smaller than CMP R,0
2604 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
2605 (TEST8rr GR8:$src1, GR8:$src1)>;
2606 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
2607 (TEST16rr GR16:$src1, GR16:$src1)>;
2608 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
2609 (TEST32rr GR32:$src1, GR32:$src1)>;
2611 // zextload bool -> zextload byte
2612 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2613 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2614 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2616 // extload bool -> extload byte
2617 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2618 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2619 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2620 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
2621 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
2622 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
2625 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
2626 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
2627 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
2628 def : Pat<(i16 (anyext (loadi8 addr:$src))), (MOVZX16rm8 addr:$src)>;
2629 def : Pat<(i32 (anyext (loadi8 addr:$src))), (MOVZX32rm8 addr:$src)>;
2630 def : Pat<(i32 (anyext (loadi16 addr:$src))), (MOVZX32rm16 addr:$src)>;
2632 // (and (i32 load), 255) -> (zextload i8)
2633 def : Pat<(i32 (and (loadi32 addr:$src), (i32 255))), (MOVZX32rm8 addr:$src)>;
2634 def : Pat<(i32 (and (loadi32 addr:$src), (i32 65535))),(MOVZX32rm16 addr:$src)>;
2636 //===----------------------------------------------------------------------===//
2638 //===----------------------------------------------------------------------===//
2640 // (shl x, 1) ==> (add x, x)
2641 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
2642 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
2643 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
2645 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
2646 def : Pat<(or (srl GR32:$src1, CL:$amt),
2647 (shl GR32:$src2, (sub 32, CL:$amt))),
2648 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
2650 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
2651 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2652 (SHRD32mrCL addr:$dst, GR32:$src2)>;
2654 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
2655 def : Pat<(or (shl GR32:$src1, CL:$amt),
2656 (srl GR32:$src2, (sub 32, CL:$amt))),
2657 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
2659 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
2660 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2661 (SHLD32mrCL addr:$dst, GR32:$src2)>;
2663 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
2664 def : Pat<(or (srl GR16:$src1, CL:$amt),
2665 (shl GR16:$src2, (sub 16, CL:$amt))),
2666 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
2668 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
2669 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2670 (SHRD16mrCL addr:$dst, GR16:$src2)>;
2672 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
2673 def : Pat<(or (shl GR16:$src1, CL:$amt),
2674 (srl GR16:$src2, (sub 16, CL:$amt))),
2675 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
2677 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
2678 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2679 (SHLD16mrCL addr:$dst, GR16:$src2)>;
2682 //===----------------------------------------------------------------------===//
2683 // Floating Point Stack Support
2684 //===----------------------------------------------------------------------===//
2686 include "X86InstrFPStack.td"
2688 //===----------------------------------------------------------------------===//
2690 //===----------------------------------------------------------------------===//
2692 include "X86Instr64bit.td"
2694 //===----------------------------------------------------------------------===//
2695 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
2696 //===----------------------------------------------------------------------===//
2698 include "X86InstrMMX.td"
2700 //===----------------------------------------------------------------------===//
2701 // XMM Floating point support (requires SSE / SSE2)
2702 //===----------------------------------------------------------------------===//
2704 include "X86InstrSSE.td"