1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 def SDTX86BrCond : SDTypeProfile<0, 3,
31 [SDTCisVT<0, OtherVT>,
32 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
34 def SDTX86SetCC : SDTypeProfile<1, 2,
36 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
38 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
40 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
42 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
44 def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
45 def SDT_X86CallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
48 def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
50 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
52 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
54 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
56 def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
58 def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
62 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
64 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
65 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
66 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
67 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
69 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
71 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
72 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
74 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
76 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
77 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
79 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
80 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
83 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
84 [SDNPHasChain, SDNPOptInFlag]>;
86 def X86callseq_start :
87 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
88 [SDNPHasChain, SDNPOutFlag]>;
90 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
91 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
93 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
94 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
96 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
97 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
99 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
100 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
101 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
102 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
105 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
106 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
108 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
109 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
111 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
112 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
113 def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
115 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
118 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
119 [SDNPHasChain, SDNPOptInFlag]>;
121 //===----------------------------------------------------------------------===//
122 // X86 Operand Definitions.
125 // *mem - Operand definitions for the funky X86 addressing mode operands.
127 class X86MemOperand<string printMethod> : Operand<iPTR> {
128 let PrintMethod = printMethod;
129 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
132 def i8mem : X86MemOperand<"printi8mem">;
133 def i16mem : X86MemOperand<"printi16mem">;
134 def i32mem : X86MemOperand<"printi32mem">;
135 def i64mem : X86MemOperand<"printi64mem">;
136 def i128mem : X86MemOperand<"printi128mem">;
137 def f32mem : X86MemOperand<"printf32mem">;
138 def f64mem : X86MemOperand<"printf64mem">;
139 def f80mem : X86MemOperand<"printf80mem">;
140 def f128mem : X86MemOperand<"printf128mem">;
142 def lea32mem : Operand<i32> {
143 let PrintMethod = "printi32mem";
144 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
147 def SSECC : Operand<i8> {
148 let PrintMethod = "printSSECC";
151 def piclabel: Operand<i32> {
152 let PrintMethod = "printPICLabel";
155 // A couple of more descriptive operand definitions.
156 // 16-bits but only 8 bits are significant.
157 def i16i8imm : Operand<i16>;
158 // 32-bits but only 8 bits are significant.
159 def i32i8imm : Operand<i32>;
161 // Branch targets have OtherVT type.
162 def brtarget : Operand<OtherVT>;
164 //===----------------------------------------------------------------------===//
165 // X86 Complex Pattern Definitions.
168 // Define X86 specific addressing mode.
169 def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
170 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
171 [add, mul, shl, or, frameindex], []>;
173 //===----------------------------------------------------------------------===//
174 // X86 Instruction Predicate Definitions.
175 def HasMMX : Predicate<"Subtarget->hasMMX()">;
176 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
177 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
178 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
179 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
180 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
181 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
182 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
183 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
184 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
185 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
186 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
187 def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
188 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
190 //===----------------------------------------------------------------------===//
191 // X86 Instruction Format Definitions.
194 include "X86InstrFormats.td"
196 //===----------------------------------------------------------------------===//
197 // Pattern fragments...
200 // X86 specific condition code. These correspond to CondCode in
201 // X86InstrInfo.h. They must be kept in synch.
202 def X86_COND_A : PatLeaf<(i8 0)>;
203 def X86_COND_AE : PatLeaf<(i8 1)>;
204 def X86_COND_B : PatLeaf<(i8 2)>;
205 def X86_COND_BE : PatLeaf<(i8 3)>;
206 def X86_COND_E : PatLeaf<(i8 4)>;
207 def X86_COND_G : PatLeaf<(i8 5)>;
208 def X86_COND_GE : PatLeaf<(i8 6)>;
209 def X86_COND_L : PatLeaf<(i8 7)>;
210 def X86_COND_LE : PatLeaf<(i8 8)>;
211 def X86_COND_NE : PatLeaf<(i8 9)>;
212 def X86_COND_NO : PatLeaf<(i8 10)>;
213 def X86_COND_NP : PatLeaf<(i8 11)>;
214 def X86_COND_NS : PatLeaf<(i8 12)>;
215 def X86_COND_O : PatLeaf<(i8 13)>;
216 def X86_COND_P : PatLeaf<(i8 14)>;
217 def X86_COND_S : PatLeaf<(i8 15)>;
219 def i16immSExt8 : PatLeaf<(i16 imm), [{
220 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
221 // sign extended field.
222 return (int16_t)N->getValue() == (int8_t)N->getValue();
225 def i32immSExt8 : PatLeaf<(i32 imm), [{
226 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
227 // sign extended field.
228 return (int32_t)N->getValue() == (int8_t)N->getValue();
231 // Helper fragments for loads.
232 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
233 def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>;
234 def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>;
235 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
237 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
238 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
239 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
241 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
242 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
243 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
245 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
246 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
247 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
248 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
249 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
250 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
252 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
253 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
254 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
255 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
256 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
257 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
260 // An 'and' node with a single use.
261 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
262 return N->hasOneUse();
265 //===----------------------------------------------------------------------===//
266 // Instruction list...
269 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
270 // a stack adjustment and the codegen must know that they may modify the stack
271 // pointer before prolog-epilog rewriting occurs.
272 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
273 // sub / add which can clobber EFLAGS.
274 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
275 def ADJCALLSTACKDOWN : I<0, Pseudo, (outs), (ins i32imm:$amt),
277 [(X86callseq_start imm:$amt)]>;
278 def ADJCALLSTACKUP : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
280 [(X86callseq_end imm:$amt1, imm:$amt2)]>;
284 let neverHasSideEffects = 1 in
285 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
288 let neverHasSideEffects = 1, isNotDuplicable = 1 in
289 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
290 "call\t$label\n\tpop{l}\t$reg", []>;
292 //===----------------------------------------------------------------------===//
293 // Control Flow Instructions...
296 // Return instructions.
297 let isTerminator = 1, isReturn = 1, isBarrier = 1,
298 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
299 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
301 [/*(X86retflag 0)*/ /*FIXME: Disabled: rdar://5791600*/]>;
302 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
304 [(X86retflag imm:$amt)]>;
307 // All branches are RawFrm, Void, Branch, and Terminators
308 let isBranch = 1, isTerminator = 1 in
309 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
310 I<opcode, RawFrm, (outs), ins, asm, pattern>;
312 let isBranch = 1, isBarrier = 1 in
313 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
316 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
317 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
318 [(brind GR32:$dst)]>;
319 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
320 [(brind (loadi32 addr:$dst))]>;
323 // Conditional branches
324 let Uses = [EFLAGS] in {
325 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
326 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
327 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
328 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
329 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
330 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
331 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
332 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
333 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
334 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
335 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
336 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
338 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
339 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
340 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
341 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
342 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
343 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
344 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
345 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
347 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
348 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
349 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
350 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
351 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
352 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
353 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
354 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
355 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
356 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
357 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
358 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
361 //===----------------------------------------------------------------------===//
362 // Call Instructions...
365 // All calls clobber the non-callee saved registers...
366 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
367 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
368 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, EFLAGS] in {
369 def CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:$dst,variable_ops),
370 "call\t${dst:call}", []>;
371 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
372 "call\t{*}$dst", [(X86call GR32:$dst)]>;
373 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
374 "call\t{*}$dst", []>;
379 def TAILCALL : I<0, Pseudo, (outs), (ins),
383 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
384 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops),
385 "#TC_RETURN $dst $offset",
388 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
389 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops),
390 "#TC_RETURN $dst $offset",
393 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
394 def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAILCALL",
396 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
397 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
399 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
400 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
401 "jmp\t{*}$dst # TAILCALL", []>;
403 //===----------------------------------------------------------------------===//
404 // Miscellaneous Instructions...
406 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
407 def LEAVE : I<0xC9, RawFrm,
408 (outs), (ins), "leave", []>;
410 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
412 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
415 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
418 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
419 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
420 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
421 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
423 let isTwoAddress = 1 in // GR32 = bswap GR32
424 def BSWAP32r : I<0xC8, AddRegFrm,
425 (outs GR32:$dst), (ins GR32:$src),
427 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
430 // Bit scan instructions.
431 let Defs = [EFLAGS] in {
432 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
433 "bsf{w}\t{$src, $dst|$dst, $src}",
434 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
435 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
436 "bsf{w}\t{$src, $dst|$dst, $src}",
437 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
438 (implicit EFLAGS)]>, TB;
439 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
440 "bsf{l}\t{$src, $dst|$dst, $src}",
441 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
442 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
443 "bsf{l}\t{$src, $dst|$dst, $src}",
444 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
445 (implicit EFLAGS)]>, TB;
447 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
448 "bsr{w}\t{$src, $dst|$dst, $src}",
449 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
450 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
451 "bsr{w}\t{$src, $dst|$dst, $src}",
452 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
453 (implicit EFLAGS)]>, TB;
454 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
455 "bsr{l}\t{$src, $dst|$dst, $src}",
456 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
457 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
458 "bsr{l}\t{$src, $dst|$dst, $src}",
459 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
460 (implicit EFLAGS)]>, TB;
463 let neverHasSideEffects = 1 in
464 def LEA16r : I<0x8D, MRMSrcMem,
465 (outs GR16:$dst), (ins i32mem:$src),
466 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
467 let isReMaterializable = 1 in
468 def LEA32r : I<0x8D, MRMSrcMem,
469 (outs GR32:$dst), (ins lea32mem:$src),
470 "lea{l}\t{$src|$dst}, {$dst|$src}",
471 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
473 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
474 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
475 [(X86rep_movs i8)]>, REP;
476 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
477 [(X86rep_movs i16)]>, REP, OpSize;
478 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
479 [(X86rep_movs i32)]>, REP;
482 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
483 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
484 [(X86rep_stos i8)]>, REP;
485 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
486 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
487 [(X86rep_stos i16)]>, REP, OpSize;
488 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
489 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
490 [(X86rep_stos i32)]>, REP;
492 let Defs = [RAX, RDX] in
493 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
496 let isBarrier = 1, hasCtrlDep = 1 in {
497 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
500 //===----------------------------------------------------------------------===//
501 // Input/Output Instructions...
503 let Defs = [AL], Uses = [DX] in
504 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
505 "in{b}\t{%dx, %al|%AL, %DX}", []>;
506 let Defs = [AX], Uses = [DX] in
507 def IN16rr : I<0xED, RawFrm, (outs), (ins),
508 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
509 let Defs = [EAX], Uses = [DX] in
510 def IN32rr : I<0xED, RawFrm, (outs), (ins),
511 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
514 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
515 "in{b}\t{$port, %al|%AL, $port}", []>;
517 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
518 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
520 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
521 "in{l}\t{$port, %eax|%EAX, $port}", []>;
523 let Uses = [DX, AL] in
524 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
525 "out{b}\t{%al, %dx|%DX, %AL}", []>;
526 let Uses = [DX, AX] in
527 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
528 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
529 let Uses = [DX, EAX] in
530 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
531 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
534 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
535 "out{b}\t{%al, $port|$port, %AL}", []>;
537 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
538 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
540 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
541 "out{l}\t{%eax, $port|$port, %EAX}", []>;
543 //===----------------------------------------------------------------------===//
544 // Move Instructions...
546 let neverHasSideEffects = 1 in {
547 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
548 "mov{b}\t{$src, $dst|$dst, $src}", []>;
549 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
550 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
551 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
552 "mov{l}\t{$src, $dst|$dst, $src}", []>;
554 let isReMaterializable = 1 in {
555 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
556 "mov{b}\t{$src, $dst|$dst, $src}",
557 [(set GR8:$dst, imm:$src)]>;
558 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
559 "mov{w}\t{$src, $dst|$dst, $src}",
560 [(set GR16:$dst, imm:$src)]>, OpSize;
561 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
562 "mov{l}\t{$src, $dst|$dst, $src}",
563 [(set GR32:$dst, imm:$src)]>;
565 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
566 "mov{b}\t{$src, $dst|$dst, $src}",
567 [(store (i8 imm:$src), addr:$dst)]>;
568 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
569 "mov{w}\t{$src, $dst|$dst, $src}",
570 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
571 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
572 "mov{l}\t{$src, $dst|$dst, $src}",
573 [(store (i32 imm:$src), addr:$dst)]>;
575 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
576 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
577 "mov{b}\t{$src, $dst|$dst, $src}",
578 [(set GR8:$dst, (load addr:$src))]>;
579 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
580 "mov{w}\t{$src, $dst|$dst, $src}",
581 [(set GR16:$dst, (load addr:$src))]>, OpSize;
582 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
583 "mov{l}\t{$src, $dst|$dst, $src}",
584 [(set GR32:$dst, (load addr:$src))]>;
587 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
588 "mov{b}\t{$src, $dst|$dst, $src}",
589 [(store GR8:$src, addr:$dst)]>;
590 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
591 "mov{w}\t{$src, $dst|$dst, $src}",
592 [(store GR16:$src, addr:$dst)]>, OpSize;
593 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
594 "mov{l}\t{$src, $dst|$dst, $src}",
595 [(store GR32:$src, addr:$dst)]>;
597 //===----------------------------------------------------------------------===//
598 // Fixed-Register Multiplication and Division Instructions...
601 // Extra precision multiplication
602 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
603 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
604 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
605 // This probably ought to be moved to a def : Pat<> if the
606 // syntax can be accepted.
607 [(set AL, (mul AL, GR8:$src))]>; // AL,AH = AL*GR8
608 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
609 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>,
610 OpSize; // AX,DX = AX*GR16
611 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
612 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l}\t$src", []>;
613 // EAX,EDX = EAX*GR32
614 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
615 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
617 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
618 // This probably ought to be moved to a def : Pat<> if the
619 // syntax can be accepted.
620 [(set AL, (mul AL, (loadi8 addr:$src)))]>; // AL,AH = AL*[mem8]
621 let mayLoad = 1, neverHasSideEffects = 1 in {
622 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
623 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
624 "mul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
625 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
626 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
627 "mul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
630 let neverHasSideEffects = 1 in {
631 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
632 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
634 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
635 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
636 OpSize; // AX,DX = AX*GR16
637 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
638 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
639 // EAX,EDX = EAX*GR32
641 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
642 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
643 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
644 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
645 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
646 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
647 let Defs = [EAX,EDX], Uses = [EAX] in
648 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
649 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
652 // unsigned division/remainder
653 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
654 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
656 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
657 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
658 "div{w}\t$src", []>, OpSize;
659 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
660 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
663 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
664 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
666 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
667 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
668 "div{w}\t$src", []>, OpSize;
669 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
670 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
674 // Signed division/remainder.
675 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
676 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
677 "idiv{b}\t$src", []>;
678 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
679 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
680 "idiv{w}\t$src", []>, OpSize;
681 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
682 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
683 "idiv{l}\t$src", []>;
684 let mayLoad = 1, mayLoad = 1 in {
685 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
686 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
687 "idiv{b}\t$src", []>;
688 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
689 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
690 "idiv{w}\t$src", []>, OpSize;
691 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
692 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
693 "idiv{l}\t$src", []>;
695 } // neverHasSideEffects
697 //===----------------------------------------------------------------------===//
698 // Two address Instructions.
700 let isTwoAddress = 1 in {
703 let Uses = [EFLAGS] in {
704 let isCommutable = 1 in {
705 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
706 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
707 "cmovb\t{$src2, $dst|$dst, $src2}",
708 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
709 X86_COND_B, EFLAGS))]>,
711 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
712 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
713 "cmovb\t{$src2, $dst|$dst, $src2}",
714 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
715 X86_COND_B, EFLAGS))]>,
718 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
719 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
720 "cmovae\t{$src2, $dst|$dst, $src2}",
721 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
722 X86_COND_AE, EFLAGS))]>,
724 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
725 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
726 "cmovae\t{$src2, $dst|$dst, $src2}",
727 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
728 X86_COND_AE, EFLAGS))]>,
730 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
731 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
732 "cmove\t{$src2, $dst|$dst, $src2}",
733 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
734 X86_COND_E, EFLAGS))]>,
736 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
737 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
738 "cmove\t{$src2, $dst|$dst, $src2}",
739 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
740 X86_COND_E, EFLAGS))]>,
742 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
743 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
744 "cmovne\t{$src2, $dst|$dst, $src2}",
745 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
746 X86_COND_NE, EFLAGS))]>,
748 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
749 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
750 "cmovne\t{$src2, $dst|$dst, $src2}",
751 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
752 X86_COND_NE, EFLAGS))]>,
754 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
755 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
756 "cmovbe\t{$src2, $dst|$dst, $src2}",
757 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
758 X86_COND_BE, EFLAGS))]>,
760 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
761 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
762 "cmovbe\t{$src2, $dst|$dst, $src2}",
763 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
764 X86_COND_BE, EFLAGS))]>,
766 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
767 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
768 "cmova\t{$src2, $dst|$dst, $src2}",
769 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
770 X86_COND_A, EFLAGS))]>,
772 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
773 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
774 "cmova\t{$src2, $dst|$dst, $src2}",
775 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
776 X86_COND_A, EFLAGS))]>,
778 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
779 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
780 "cmovl\t{$src2, $dst|$dst, $src2}",
781 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
782 X86_COND_L, EFLAGS))]>,
784 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
785 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
786 "cmovl\t{$src2, $dst|$dst, $src2}",
787 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
788 X86_COND_L, EFLAGS))]>,
790 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
791 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
792 "cmovge\t{$src2, $dst|$dst, $src2}",
793 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
794 X86_COND_GE, EFLAGS))]>,
796 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
797 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
798 "cmovge\t{$src2, $dst|$dst, $src2}",
799 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
800 X86_COND_GE, EFLAGS))]>,
802 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
803 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
804 "cmovle\t{$src2, $dst|$dst, $src2}",
805 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
806 X86_COND_LE, EFLAGS))]>,
808 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
809 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
810 "cmovle\t{$src2, $dst|$dst, $src2}",
811 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
812 X86_COND_LE, EFLAGS))]>,
814 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
815 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
816 "cmovg\t{$src2, $dst|$dst, $src2}",
817 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
818 X86_COND_G, EFLAGS))]>,
820 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
821 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
822 "cmovg\t{$src2, $dst|$dst, $src2}",
823 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
824 X86_COND_G, EFLAGS))]>,
826 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
827 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
828 "cmovs\t{$src2, $dst|$dst, $src2}",
829 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
830 X86_COND_S, EFLAGS))]>,
832 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
833 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
834 "cmovs\t{$src2, $dst|$dst, $src2}",
835 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
836 X86_COND_S, EFLAGS))]>,
838 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
839 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
840 "cmovns\t{$src2, $dst|$dst, $src2}",
841 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
842 X86_COND_NS, EFLAGS))]>,
844 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
845 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
846 "cmovns\t{$src2, $dst|$dst, $src2}",
847 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
848 X86_COND_NS, EFLAGS))]>,
850 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
851 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
852 "cmovp\t{$src2, $dst|$dst, $src2}",
853 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
854 X86_COND_P, EFLAGS))]>,
856 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
857 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
858 "cmovp\t{$src2, $dst|$dst, $src2}",
859 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
860 X86_COND_P, EFLAGS))]>,
862 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
863 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
864 "cmovnp\t{$src2, $dst|$dst, $src2}",
865 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
866 X86_COND_NP, EFLAGS))]>,
868 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
869 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
870 "cmovnp\t{$src2, $dst|$dst, $src2}",
871 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
872 X86_COND_NP, EFLAGS))]>,
874 } // isCommutable = 1
876 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
877 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
878 "cmovnp\t{$src2, $dst|$dst, $src2}",
879 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
880 X86_COND_NP, EFLAGS))]>,
883 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
884 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
885 "cmovb\t{$src2, $dst|$dst, $src2}",
886 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
887 X86_COND_B, EFLAGS))]>,
889 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
890 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
891 "cmovb\t{$src2, $dst|$dst, $src2}",
892 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
893 X86_COND_B, EFLAGS))]>,
895 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
896 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
897 "cmovae\t{$src2, $dst|$dst, $src2}",
898 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
899 X86_COND_AE, EFLAGS))]>,
901 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
902 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
903 "cmovae\t{$src2, $dst|$dst, $src2}",
904 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
905 X86_COND_AE, EFLAGS))]>,
907 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
908 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
909 "cmove\t{$src2, $dst|$dst, $src2}",
910 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
911 X86_COND_E, EFLAGS))]>,
913 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
914 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
915 "cmove\t{$src2, $dst|$dst, $src2}",
916 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
917 X86_COND_E, EFLAGS))]>,
919 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
920 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
921 "cmovne\t{$src2, $dst|$dst, $src2}",
922 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
923 X86_COND_NE, EFLAGS))]>,
925 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
926 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
927 "cmovne\t{$src2, $dst|$dst, $src2}",
928 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
929 X86_COND_NE, EFLAGS))]>,
931 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
932 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
933 "cmovbe\t{$src2, $dst|$dst, $src2}",
934 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
935 X86_COND_BE, EFLAGS))]>,
937 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
938 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
939 "cmovbe\t{$src2, $dst|$dst, $src2}",
940 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
941 X86_COND_BE, EFLAGS))]>,
943 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
944 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
945 "cmova\t{$src2, $dst|$dst, $src2}",
946 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
947 X86_COND_A, EFLAGS))]>,
949 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
950 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
951 "cmova\t{$src2, $dst|$dst, $src2}",
952 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
953 X86_COND_A, EFLAGS))]>,
955 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
956 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
957 "cmovl\t{$src2, $dst|$dst, $src2}",
958 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
959 X86_COND_L, EFLAGS))]>,
961 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
962 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
963 "cmovl\t{$src2, $dst|$dst, $src2}",
964 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
965 X86_COND_L, EFLAGS))]>,
967 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
968 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
969 "cmovge\t{$src2, $dst|$dst, $src2}",
970 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
971 X86_COND_GE, EFLAGS))]>,
973 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
974 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
975 "cmovge\t{$src2, $dst|$dst, $src2}",
976 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
977 X86_COND_GE, EFLAGS))]>,
979 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
980 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
981 "cmovle\t{$src2, $dst|$dst, $src2}",
982 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
983 X86_COND_LE, EFLAGS))]>,
985 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
986 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
987 "cmovle\t{$src2, $dst|$dst, $src2}",
988 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
989 X86_COND_LE, EFLAGS))]>,
991 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
992 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
993 "cmovg\t{$src2, $dst|$dst, $src2}",
994 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
995 X86_COND_G, EFLAGS))]>,
997 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
998 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
999 "cmovg\t{$src2, $dst|$dst, $src2}",
1000 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1001 X86_COND_G, EFLAGS))]>,
1003 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1004 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1005 "cmovs\t{$src2, $dst|$dst, $src2}",
1006 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1007 X86_COND_S, EFLAGS))]>,
1009 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1010 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1011 "cmovs\t{$src2, $dst|$dst, $src2}",
1012 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1013 X86_COND_S, EFLAGS))]>,
1015 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1016 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1017 "cmovns\t{$src2, $dst|$dst, $src2}",
1018 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1019 X86_COND_NS, EFLAGS))]>,
1021 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1022 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1023 "cmovns\t{$src2, $dst|$dst, $src2}",
1024 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1025 X86_COND_NS, EFLAGS))]>,
1027 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1028 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1029 "cmovp\t{$src2, $dst|$dst, $src2}",
1030 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1031 X86_COND_P, EFLAGS))]>,
1033 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1034 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1035 "cmovp\t{$src2, $dst|$dst, $src2}",
1036 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1037 X86_COND_P, EFLAGS))]>,
1039 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1040 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1041 "cmovnp\t{$src2, $dst|$dst, $src2}",
1042 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1043 X86_COND_NP, EFLAGS))]>,
1045 } // Uses = [EFLAGS]
1048 // unary instructions
1049 let CodeSize = 2 in {
1050 let Defs = [EFLAGS] in {
1051 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1052 [(set GR8:$dst, (ineg GR8:$src))]>;
1053 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1054 [(set GR16:$dst, (ineg GR16:$src))]>, OpSize;
1055 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1056 [(set GR32:$dst, (ineg GR32:$src))]>;
1057 let isTwoAddress = 0 in {
1058 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1059 [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
1060 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1061 [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1062 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1063 [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
1066 } // Defs = [EFLAGS]
1068 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1069 [(set GR8:$dst, (not GR8:$src))]>;
1070 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1071 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1072 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1073 [(set GR32:$dst, (not GR32:$src))]>;
1074 let isTwoAddress = 0 in {
1075 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1076 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1077 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1078 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1079 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1080 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1084 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1085 let Defs = [EFLAGS] in {
1087 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1088 [(set GR8:$dst, (add GR8:$src, 1))]>;
1089 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1090 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1091 [(set GR16:$dst, (add GR16:$src, 1))]>,
1092 OpSize, Requires<[In32BitMode]>;
1093 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1094 [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>;
1096 let isTwoAddress = 0, CodeSize = 2 in {
1097 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1098 [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
1099 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1100 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>,
1101 OpSize, Requires<[In32BitMode]>;
1102 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1103 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>,
1104 Requires<[In32BitMode]>;
1108 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1109 [(set GR8:$dst, (add GR8:$src, -1))]>;
1110 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1111 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1112 [(set GR16:$dst, (add GR16:$src, -1))]>,
1113 OpSize, Requires<[In32BitMode]>;
1114 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1115 [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>;
1118 let isTwoAddress = 0, CodeSize = 2 in {
1119 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1120 [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
1121 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1122 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>,
1123 OpSize, Requires<[In32BitMode]>;
1124 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1125 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>,
1126 Requires<[In32BitMode]>;
1128 } // Defs = [EFLAGS]
1130 // Logical operators...
1131 let Defs = [EFLAGS] in {
1132 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1133 def AND8rr : I<0x20, MRMDestReg,
1134 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1135 "and{b}\t{$src2, $dst|$dst, $src2}",
1136 [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>;
1137 def AND16rr : I<0x21, MRMDestReg,
1138 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1139 "and{w}\t{$src2, $dst|$dst, $src2}",
1140 [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize;
1141 def AND32rr : I<0x21, MRMDestReg,
1142 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1143 "and{l}\t{$src2, $dst|$dst, $src2}",
1144 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
1147 def AND8rm : I<0x22, MRMSrcMem,
1148 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1149 "and{b}\t{$src2, $dst|$dst, $src2}",
1150 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>;
1151 def AND16rm : I<0x23, MRMSrcMem,
1152 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1153 "and{w}\t{$src2, $dst|$dst, $src2}",
1154 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize;
1155 def AND32rm : I<0x23, MRMSrcMem,
1156 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1157 "and{l}\t{$src2, $dst|$dst, $src2}",
1158 [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>;
1160 def AND8ri : Ii8<0x80, MRM4r,
1161 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1162 "and{b}\t{$src2, $dst|$dst, $src2}",
1163 [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>;
1164 def AND16ri : Ii16<0x81, MRM4r,
1165 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1166 "and{w}\t{$src2, $dst|$dst, $src2}",
1167 [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize;
1168 def AND32ri : Ii32<0x81, MRM4r,
1169 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1170 "and{l}\t{$src2, $dst|$dst, $src2}",
1171 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
1172 def AND16ri8 : Ii8<0x83, MRM4r,
1173 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1174 "and{w}\t{$src2, $dst|$dst, $src2}",
1175 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>,
1177 def AND32ri8 : Ii8<0x83, MRM4r,
1178 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1179 "and{l}\t{$src2, $dst|$dst, $src2}",
1180 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>;
1182 let isTwoAddress = 0 in {
1183 def AND8mr : I<0x20, MRMDestMem,
1184 (outs), (ins i8mem :$dst, GR8 :$src),
1185 "and{b}\t{$src, $dst|$dst, $src}",
1186 [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>;
1187 def AND16mr : I<0x21, MRMDestMem,
1188 (outs), (ins i16mem:$dst, GR16:$src),
1189 "and{w}\t{$src, $dst|$dst, $src}",
1190 [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>,
1192 def AND32mr : I<0x21, MRMDestMem,
1193 (outs), (ins i32mem:$dst, GR32:$src),
1194 "and{l}\t{$src, $dst|$dst, $src}",
1195 [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>;
1196 def AND8mi : Ii8<0x80, MRM4m,
1197 (outs), (ins i8mem :$dst, i8imm :$src),
1198 "and{b}\t{$src, $dst|$dst, $src}",
1199 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1200 def AND16mi : Ii16<0x81, MRM4m,
1201 (outs), (ins i16mem:$dst, i16imm:$src),
1202 "and{w}\t{$src, $dst|$dst, $src}",
1203 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1205 def AND32mi : Ii32<0x81, MRM4m,
1206 (outs), (ins i32mem:$dst, i32imm:$src),
1207 "and{l}\t{$src, $dst|$dst, $src}",
1208 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1209 def AND16mi8 : Ii8<0x83, MRM4m,
1210 (outs), (ins i16mem:$dst, i16i8imm :$src),
1211 "and{w}\t{$src, $dst|$dst, $src}",
1212 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1214 def AND32mi8 : Ii8<0x83, MRM4m,
1215 (outs), (ins i32mem:$dst, i32i8imm :$src),
1216 "and{l}\t{$src, $dst|$dst, $src}",
1217 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1221 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1222 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1223 "or{b}\t{$src2, $dst|$dst, $src2}",
1224 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
1225 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1226 "or{w}\t{$src2, $dst|$dst, $src2}",
1227 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize;
1228 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1229 "or{l}\t{$src2, $dst|$dst, $src2}",
1230 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
1232 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1233 "or{b}\t{$src2, $dst|$dst, $src2}",
1234 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
1235 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1236 "or{w}\t{$src2, $dst|$dst, $src2}",
1237 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize;
1238 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1239 "or{l}\t{$src2, $dst|$dst, $src2}",
1240 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>;
1242 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1243 "or{b}\t{$src2, $dst|$dst, $src2}",
1244 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
1245 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1246 "or{w}\t{$src2, $dst|$dst, $src2}",
1247 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize;
1248 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1249 "or{l}\t{$src2, $dst|$dst, $src2}",
1250 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
1252 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1253 "or{w}\t{$src2, $dst|$dst, $src2}",
1254 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1255 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1256 "or{l}\t{$src2, $dst|$dst, $src2}",
1257 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>;
1258 let isTwoAddress = 0 in {
1259 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1260 "or{b}\t{$src, $dst|$dst, $src}",
1261 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
1262 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1263 "or{w}\t{$src, $dst|$dst, $src}",
1264 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize;
1265 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1266 "or{l}\t{$src, $dst|$dst, $src}",
1267 [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>;
1268 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1269 "or{b}\t{$src, $dst|$dst, $src}",
1270 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1271 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1272 "or{w}\t{$src, $dst|$dst, $src}",
1273 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1275 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1276 "or{l}\t{$src, $dst|$dst, $src}",
1277 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1278 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1279 "or{w}\t{$src, $dst|$dst, $src}",
1280 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1282 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1283 "or{l}\t{$src, $dst|$dst, $src}",
1284 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1288 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1289 def XOR8rr : I<0x30, MRMDestReg,
1290 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1291 "xor{b}\t{$src2, $dst|$dst, $src2}",
1292 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>;
1293 def XOR16rr : I<0x31, MRMDestReg,
1294 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1295 "xor{w}\t{$src2, $dst|$dst, $src2}",
1296 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize;
1297 def XOR32rr : I<0x31, MRMDestReg,
1298 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1299 "xor{l}\t{$src2, $dst|$dst, $src2}",
1300 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
1303 def XOR8rm : I<0x32, MRMSrcMem ,
1304 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1305 "xor{b}\t{$src2, $dst|$dst, $src2}",
1306 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>;
1307 def XOR16rm : I<0x33, MRMSrcMem ,
1308 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1309 "xor{w}\t{$src2, $dst|$dst, $src2}",
1310 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>, OpSize;
1311 def XOR32rm : I<0x33, MRMSrcMem ,
1312 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1313 "xor{l}\t{$src2, $dst|$dst, $src2}",
1314 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>;
1316 def XOR8ri : Ii8<0x80, MRM6r,
1317 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1318 "xor{b}\t{$src2, $dst|$dst, $src2}",
1319 [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>;
1320 def XOR16ri : Ii16<0x81, MRM6r,
1321 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1322 "xor{w}\t{$src2, $dst|$dst, $src2}",
1323 [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize;
1324 def XOR32ri : Ii32<0x81, MRM6r,
1325 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1326 "xor{l}\t{$src2, $dst|$dst, $src2}",
1327 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
1328 def XOR16ri8 : Ii8<0x83, MRM6r,
1329 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1330 "xor{w}\t{$src2, $dst|$dst, $src2}",
1331 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>,
1333 def XOR32ri8 : Ii8<0x83, MRM6r,
1334 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1335 "xor{l}\t{$src2, $dst|$dst, $src2}",
1336 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>;
1337 let isTwoAddress = 0 in {
1338 def XOR8mr : I<0x30, MRMDestMem,
1339 (outs), (ins i8mem :$dst, GR8 :$src),
1340 "xor{b}\t{$src, $dst|$dst, $src}",
1341 [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>;
1342 def XOR16mr : I<0x31, MRMDestMem,
1343 (outs), (ins i16mem:$dst, GR16:$src),
1344 "xor{w}\t{$src, $dst|$dst, $src}",
1345 [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>,
1347 def XOR32mr : I<0x31, MRMDestMem,
1348 (outs), (ins i32mem:$dst, GR32:$src),
1349 "xor{l}\t{$src, $dst|$dst, $src}",
1350 [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>;
1351 def XOR8mi : Ii8<0x80, MRM6m,
1352 (outs), (ins i8mem :$dst, i8imm :$src),
1353 "xor{b}\t{$src, $dst|$dst, $src}",
1354 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1355 def XOR16mi : Ii16<0x81, MRM6m,
1356 (outs), (ins i16mem:$dst, i16imm:$src),
1357 "xor{w}\t{$src, $dst|$dst, $src}",
1358 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1360 def XOR32mi : Ii32<0x81, MRM6m,
1361 (outs), (ins i32mem:$dst, i32imm:$src),
1362 "xor{l}\t{$src, $dst|$dst, $src}",
1363 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1364 def XOR16mi8 : Ii8<0x83, MRM6m,
1365 (outs), (ins i16mem:$dst, i16i8imm :$src),
1366 "xor{w}\t{$src, $dst|$dst, $src}",
1367 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1369 def XOR32mi8 : Ii8<0x83, MRM6m,
1370 (outs), (ins i32mem:$dst, i32i8imm :$src),
1371 "xor{l}\t{$src, $dst|$dst, $src}",
1372 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1374 } // Defs = [EFLAGS]
1376 // Shift instructions
1377 let Defs = [EFLAGS] in {
1378 let Uses = [CL] in {
1379 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1380 "shl{b}\t{%cl, $dst|$dst, %CL}",
1381 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1382 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1383 "shl{w}\t{%cl, $dst|$dst, %CL}",
1384 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1385 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1386 "shl{l}\t{%cl, $dst|$dst, %CL}",
1387 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1390 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1391 "shl{b}\t{$src2, $dst|$dst, $src2}",
1392 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1393 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1394 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1395 "shl{w}\t{$src2, $dst|$dst, $src2}",
1396 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1397 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1398 "shl{l}\t{$src2, $dst|$dst, $src2}",
1399 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1400 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1404 let isTwoAddress = 0 in {
1405 let Uses = [CL] in {
1406 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1407 "shl{b}\t{%cl, $dst|$dst, %CL}",
1408 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1409 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1410 "shl{w}\t{%cl, $dst|$dst, %CL}",
1411 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1412 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1413 "shl{l}\t{%cl, $dst|$dst, %CL}",
1414 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1416 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1417 "shl{b}\t{$src, $dst|$dst, $src}",
1418 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1419 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1420 "shl{w}\t{$src, $dst|$dst, $src}",
1421 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1423 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1424 "shl{l}\t{$src, $dst|$dst, $src}",
1425 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1428 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1430 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1431 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1433 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1435 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1437 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1440 let Uses = [CL] in {
1441 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1442 "shr{b}\t{%cl, $dst|$dst, %CL}",
1443 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1444 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1445 "shr{w}\t{%cl, $dst|$dst, %CL}",
1446 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1447 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1448 "shr{l}\t{%cl, $dst|$dst, %CL}",
1449 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1452 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1453 "shr{b}\t{$src2, $dst|$dst, $src2}",
1454 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1455 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1456 "shr{w}\t{$src2, $dst|$dst, $src2}",
1457 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1458 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1459 "shr{l}\t{$src2, $dst|$dst, $src2}",
1460 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1463 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1465 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1466 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1468 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1469 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1471 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1473 let isTwoAddress = 0 in {
1474 let Uses = [CL] in {
1475 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1476 "shr{b}\t{%cl, $dst|$dst, %CL}",
1477 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1478 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1479 "shr{w}\t{%cl, $dst|$dst, %CL}",
1480 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1482 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1483 "shr{l}\t{%cl, $dst|$dst, %CL}",
1484 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1486 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1487 "shr{b}\t{$src, $dst|$dst, $src}",
1488 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1489 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1490 "shr{w}\t{$src, $dst|$dst, $src}",
1491 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1493 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1494 "shr{l}\t{$src, $dst|$dst, $src}",
1495 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1498 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1500 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1501 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1503 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1504 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1506 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1509 let Uses = [CL] in {
1510 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1511 "sar{b}\t{%cl, $dst|$dst, %CL}",
1512 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1513 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1514 "sar{w}\t{%cl, $dst|$dst, %CL}",
1515 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1516 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1517 "sar{l}\t{%cl, $dst|$dst, %CL}",
1518 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1521 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1522 "sar{b}\t{$src2, $dst|$dst, $src2}",
1523 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1524 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1525 "sar{w}\t{$src2, $dst|$dst, $src2}",
1526 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1528 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1529 "sar{l}\t{$src2, $dst|$dst, $src2}",
1530 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1533 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1535 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1536 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1538 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1539 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1541 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1543 let isTwoAddress = 0 in {
1544 let Uses = [CL] in {
1545 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1546 "sar{b}\t{%cl, $dst|$dst, %CL}",
1547 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
1548 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1549 "sar{w}\t{%cl, $dst|$dst, %CL}",
1550 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1551 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1552 "sar{l}\t{%cl, $dst|$dst, %CL}",
1553 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1555 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1556 "sar{b}\t{$src, $dst|$dst, $src}",
1557 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1558 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1559 "sar{w}\t{$src, $dst|$dst, $src}",
1560 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1562 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1563 "sar{l}\t{$src, $dst|$dst, $src}",
1564 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1567 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1569 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1570 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1572 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1574 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
1576 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1579 // Rotate instructions
1580 // FIXME: provide shorter instructions when imm8 == 1
1581 let Uses = [CL] in {
1582 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
1583 "rol{b}\t{%cl, $dst|$dst, %CL}",
1584 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
1585 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
1586 "rol{w}\t{%cl, $dst|$dst, %CL}",
1587 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
1588 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
1589 "rol{l}\t{%cl, $dst|$dst, %CL}",
1590 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
1593 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1594 "rol{b}\t{$src2, $dst|$dst, $src2}",
1595 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1596 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1597 "rol{w}\t{$src2, $dst|$dst, $src2}",
1598 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1599 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1600 "rol{l}\t{$src2, $dst|$dst, $src2}",
1601 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1604 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1606 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1607 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
1609 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1610 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1612 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1614 let isTwoAddress = 0 in {
1615 let Uses = [CL] in {
1616 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
1617 "rol{b}\t{%cl, $dst|$dst, %CL}",
1618 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
1619 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
1620 "rol{w}\t{%cl, $dst|$dst, %CL}",
1621 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1622 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
1623 "rol{l}\t{%cl, $dst|$dst, %CL}",
1624 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
1626 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
1627 "rol{b}\t{$src, $dst|$dst, $src}",
1628 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1629 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
1630 "rol{w}\t{$src, $dst|$dst, $src}",
1631 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1633 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
1634 "rol{l}\t{$src, $dst|$dst, $src}",
1635 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1638 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
1640 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1641 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
1643 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1645 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
1647 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1650 let Uses = [CL] in {
1651 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
1652 "ror{b}\t{%cl, $dst|$dst, %CL}",
1653 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
1654 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
1655 "ror{w}\t{%cl, $dst|$dst, %CL}",
1656 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
1657 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
1658 "ror{l}\t{%cl, $dst|$dst, %CL}",
1659 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
1662 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1663 "ror{b}\t{$src2, $dst|$dst, $src2}",
1664 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
1665 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1666 "ror{w}\t{$src2, $dst|$dst, $src2}",
1667 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1668 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1669 "ror{l}\t{$src2, $dst|$dst, $src2}",
1670 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
1673 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1675 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
1676 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
1678 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
1679 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
1681 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
1683 let isTwoAddress = 0 in {
1684 let Uses = [CL] in {
1685 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
1686 "ror{b}\t{%cl, $dst|$dst, %CL}",
1687 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
1688 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
1689 "ror{w}\t{%cl, $dst|$dst, %CL}",
1690 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1691 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
1692 "ror{l}\t{%cl, $dst|$dst, %CL}",
1693 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
1695 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1696 "ror{b}\t{$src, $dst|$dst, $src}",
1697 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1698 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
1699 "ror{w}\t{$src, $dst|$dst, $src}",
1700 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1702 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
1703 "ror{l}\t{$src, $dst|$dst, $src}",
1704 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1707 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
1709 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1710 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
1712 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1714 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
1716 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1721 // Double shift instructions (generalizations of rotate)
1722 let Uses = [CL] in {
1723 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1724 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1725 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
1726 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1727 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1728 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
1729 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1730 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1731 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
1733 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1734 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1735 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
1739 let isCommutable = 1 in { // These instructions commute to each other.
1740 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
1741 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1742 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1743 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
1746 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
1747 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1748 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1749 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
1752 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
1753 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1754 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1755 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
1758 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
1759 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1760 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1761 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
1766 let isTwoAddress = 0 in {
1767 let Uses = [CL] in {
1768 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1769 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1770 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
1772 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1773 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1774 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
1777 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
1778 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1779 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1780 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
1781 (i8 imm:$src3)), addr:$dst)]>,
1783 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
1784 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1785 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1786 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
1787 (i8 imm:$src3)), addr:$dst)]>,
1790 let Uses = [CL] in {
1791 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1792 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1793 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
1794 addr:$dst)]>, TB, OpSize;
1795 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1796 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1797 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
1798 addr:$dst)]>, TB, OpSize;
1800 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
1801 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1802 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1803 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
1804 (i8 imm:$src3)), addr:$dst)]>,
1806 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
1807 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1808 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1809 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
1810 (i8 imm:$src3)), addr:$dst)]>,
1813 } // Defs = [EFLAGS]
1817 let Defs = [EFLAGS] in {
1818 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1819 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
1820 (ins GR8 :$src1, GR8 :$src2),
1821 "add{b}\t{$src2, $dst|$dst, $src2}",
1822 [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>;
1823 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1824 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
1825 (ins GR16:$src1, GR16:$src2),
1826 "add{w}\t{$src2, $dst|$dst, $src2}",
1827 [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize;
1828 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
1829 (ins GR32:$src1, GR32:$src2),
1830 "add{l}\t{$src2, $dst|$dst, $src2}",
1831 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
1832 } // end isConvertibleToThreeAddress
1833 } // end isCommutable
1834 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
1835 (ins GR8 :$src1, i8mem :$src2),
1836 "add{b}\t{$src2, $dst|$dst, $src2}",
1837 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>;
1838 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
1839 (ins GR16:$src1, i16mem:$src2),
1840 "add{w}\t{$src2, $dst|$dst, $src2}",
1841 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>,OpSize;
1842 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
1843 (ins GR32:$src1, i32mem:$src2),
1844 "add{l}\t{$src2, $dst|$dst, $src2}",
1845 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>;
1847 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1848 "add{b}\t{$src2, $dst|$dst, $src2}",
1849 [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>;
1851 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1852 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
1853 (ins GR16:$src1, i16imm:$src2),
1854 "add{w}\t{$src2, $dst|$dst, $src2}",
1855 [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize;
1856 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
1857 (ins GR32:$src1, i32imm:$src2),
1858 "add{l}\t{$src2, $dst|$dst, $src2}",
1859 [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>;
1860 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
1861 (ins GR16:$src1, i16i8imm:$src2),
1862 "add{w}\t{$src2, $dst|$dst, $src2}",
1863 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1864 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
1865 (ins GR32:$src1, i32i8imm:$src2),
1866 "add{l}\t{$src2, $dst|$dst, $src2}",
1867 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>;
1870 let isTwoAddress = 0 in {
1871 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1872 "add{b}\t{$src2, $dst|$dst, $src2}",
1873 [(store (add (load addr:$dst), GR8:$src2), addr:$dst)]>;
1874 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1875 "add{w}\t{$src2, $dst|$dst, $src2}",
1876 [(store (add (load addr:$dst), GR16:$src2), addr:$dst)]>,
1878 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1879 "add{l}\t{$src2, $dst|$dst, $src2}",
1880 [(store (add (load addr:$dst), GR32:$src2), addr:$dst)]>;
1881 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
1882 "add{b}\t{$src2, $dst|$dst, $src2}",
1883 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1884 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
1885 "add{w}\t{$src2, $dst|$dst, $src2}",
1886 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1888 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
1889 "add{l}\t{$src2, $dst|$dst, $src2}",
1890 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1891 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1892 "add{w}\t{$src2, $dst|$dst, $src2}",
1893 [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1895 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1896 "add{l}\t{$src2, $dst|$dst, $src2}",
1897 [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1900 let Uses = [EFLAGS] in {
1901 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1902 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1903 "adc{l}\t{$src2, $dst|$dst, $src2}",
1904 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
1906 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1907 "adc{l}\t{$src2, $dst|$dst, $src2}",
1908 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
1909 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1910 "adc{l}\t{$src2, $dst|$dst, $src2}",
1911 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
1912 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1913 "adc{l}\t{$src2, $dst|$dst, $src2}",
1914 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
1916 let isTwoAddress = 0 in {
1917 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1918 "adc{l}\t{$src2, $dst|$dst, $src2}",
1919 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
1920 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
1921 "adc{l}\t{$src2, $dst|$dst, $src2}",
1922 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1923 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1924 "adc{l}\t{$src2, $dst|$dst, $src2}",
1925 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1927 } // Uses = [EFLAGS]
1929 def SUB8rr : I<0x28, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1930 "sub{b}\t{$src2, $dst|$dst, $src2}",
1931 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2))]>;
1932 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1933 "sub{w}\t{$src2, $dst|$dst, $src2}",
1934 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2))]>, OpSize;
1935 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1936 "sub{l}\t{$src2, $dst|$dst, $src2}",
1937 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
1938 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1939 "sub{b}\t{$src2, $dst|$dst, $src2}",
1940 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2)))]>;
1941 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1942 "sub{w}\t{$src2, $dst|$dst, $src2}",
1943 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2)))]>, OpSize;
1944 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1945 "sub{l}\t{$src2, $dst|$dst, $src2}",
1946 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2)))]>;
1948 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1949 "sub{b}\t{$src2, $dst|$dst, $src2}",
1950 [(set GR8:$dst, (sub GR8:$src1, imm:$src2))]>;
1951 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1952 "sub{w}\t{$src2, $dst|$dst, $src2}",
1953 [(set GR16:$dst, (sub GR16:$src1, imm:$src2))]>, OpSize;
1954 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1955 "sub{l}\t{$src2, $dst|$dst, $src2}",
1956 [(set GR32:$dst, (sub GR32:$src1, imm:$src2))]>;
1957 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1958 "sub{w}\t{$src2, $dst|$dst, $src2}",
1959 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2))]>,
1961 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1962 "sub{l}\t{$src2, $dst|$dst, $src2}",
1963 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2))]>;
1964 let isTwoAddress = 0 in {
1965 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1966 "sub{b}\t{$src2, $dst|$dst, $src2}",
1967 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst)]>;
1968 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1969 "sub{w}\t{$src2, $dst|$dst, $src2}",
1970 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst)]>,
1972 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1973 "sub{l}\t{$src2, $dst|$dst, $src2}",
1974 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst)]>;
1975 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
1976 "sub{b}\t{$src2, $dst|$dst, $src2}",
1977 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1978 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
1979 "sub{w}\t{$src2, $dst|$dst, $src2}",
1980 [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1982 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
1983 "sub{l}\t{$src2, $dst|$dst, $src2}",
1984 [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1985 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1986 "sub{w}\t{$src2, $dst|$dst, $src2}",
1987 [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1989 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1990 "sub{l}\t{$src2, $dst|$dst, $src2}",
1991 [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1994 let Uses = [EFLAGS] in {
1995 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1996 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1997 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
1999 let isTwoAddress = 0 in {
2000 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2001 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2002 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2003 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2004 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2005 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2006 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2007 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2008 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2009 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2010 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2011 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2013 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2014 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2015 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2016 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2017 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2018 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2019 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2020 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2021 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2022 } // Uses = [EFLAGS]
2023 } // Defs = [EFLAGS]
2025 let Defs = [EFLAGS] in {
2026 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2027 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2028 "imul{w}\t{$src2, $dst|$dst, $src2}",
2029 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2))]>, TB, OpSize;
2030 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2031 "imul{l}\t{$src2, $dst|$dst, $src2}",
2032 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>, TB;
2034 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2035 "imul{w}\t{$src2, $dst|$dst, $src2}",
2036 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2)))]>,
2038 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2039 "imul{l}\t{$src2, $dst|$dst, $src2}",
2040 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2)))]>, TB;
2041 } // Defs = [EFLAGS]
2042 } // end Two Address instructions
2044 // Suprisingly enough, these are not two address instructions!
2045 let Defs = [EFLAGS] in {
2046 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2047 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2048 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2049 [(set GR16:$dst, (mul GR16:$src1, imm:$src2))]>, OpSize;
2050 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2051 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2052 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2053 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
2054 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2055 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2056 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2057 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2))]>,
2059 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2060 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2061 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2062 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2))]>;
2064 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2065 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2066 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2067 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2))]>,
2069 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2070 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2071 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2072 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2))]>;
2073 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2074 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2075 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2076 [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>,
2078 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2079 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2080 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2081 [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>;
2082 } // Defs = [EFLAGS]
2084 //===----------------------------------------------------------------------===//
2085 // Test instructions are just like AND, except they don't generate a result.
2087 let Defs = [EFLAGS] in {
2088 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2089 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2090 "test{b}\t{$src2, $src1|$src1, $src2}",
2091 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
2092 (implicit EFLAGS)]>;
2093 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2094 "test{w}\t{$src2, $src1|$src1, $src2}",
2095 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
2096 (implicit EFLAGS)]>,
2098 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2099 "test{l}\t{$src2, $src1|$src1, $src2}",
2100 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
2101 (implicit EFLAGS)]>;
2104 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2105 "test{b}\t{$src2, $src1|$src1, $src2}",
2106 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2107 (implicit EFLAGS)]>;
2108 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2109 "test{w}\t{$src2, $src1|$src1, $src2}",
2110 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2111 (implicit EFLAGS)]>, OpSize;
2112 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2113 "test{l}\t{$src2, $src1|$src1, $src2}",
2114 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2115 (implicit EFLAGS)]>;
2117 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2118 (outs), (ins GR8:$src1, i8imm:$src2),
2119 "test{b}\t{$src2, $src1|$src1, $src2}",
2120 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
2121 (implicit EFLAGS)]>;
2122 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2123 (outs), (ins GR16:$src1, i16imm:$src2),
2124 "test{w}\t{$src2, $src1|$src1, $src2}",
2125 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
2126 (implicit EFLAGS)]>, OpSize;
2127 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2128 (outs), (ins GR32:$src1, i32imm:$src2),
2129 "test{l}\t{$src2, $src1|$src1, $src2}",
2130 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
2131 (implicit EFLAGS)]>;
2133 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2134 (outs), (ins i8mem:$src1, i8imm:$src2),
2135 "test{b}\t{$src2, $src1|$src1, $src2}",
2136 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2137 (implicit EFLAGS)]>;
2138 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2139 (outs), (ins i16mem:$src1, i16imm:$src2),
2140 "test{w}\t{$src2, $src1|$src1, $src2}",
2141 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2142 (implicit EFLAGS)]>, OpSize;
2143 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2144 (outs), (ins i32mem:$src1, i32imm:$src2),
2145 "test{l}\t{$src2, $src1|$src1, $src2}",
2146 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2147 (implicit EFLAGS)]>;
2148 } // Defs = [EFLAGS]
2151 // Condition code ops, incl. set if equal/not equal/...
2152 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2153 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2154 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2155 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2157 let Uses = [EFLAGS] in {
2158 def SETEr : I<0x94, MRM0r,
2159 (outs GR8 :$dst), (ins),
2161 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2163 def SETEm : I<0x94, MRM0m,
2164 (outs), (ins i8mem:$dst),
2166 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2168 def SETNEr : I<0x95, MRM0r,
2169 (outs GR8 :$dst), (ins),
2171 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2173 def SETNEm : I<0x95, MRM0m,
2174 (outs), (ins i8mem:$dst),
2176 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2178 def SETLr : I<0x9C, MRM0r,
2179 (outs GR8 :$dst), (ins),
2181 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2182 TB; // GR8 = < signed
2183 def SETLm : I<0x9C, MRM0m,
2184 (outs), (ins i8mem:$dst),
2186 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2187 TB; // [mem8] = < signed
2188 def SETGEr : I<0x9D, MRM0r,
2189 (outs GR8 :$dst), (ins),
2191 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2192 TB; // GR8 = >= signed
2193 def SETGEm : I<0x9D, MRM0m,
2194 (outs), (ins i8mem:$dst),
2196 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2197 TB; // [mem8] = >= signed
2198 def SETLEr : I<0x9E, MRM0r,
2199 (outs GR8 :$dst), (ins),
2201 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2202 TB; // GR8 = <= signed
2203 def SETLEm : I<0x9E, MRM0m,
2204 (outs), (ins i8mem:$dst),
2206 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2207 TB; // [mem8] = <= signed
2208 def SETGr : I<0x9F, MRM0r,
2209 (outs GR8 :$dst), (ins),
2211 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2212 TB; // GR8 = > signed
2213 def SETGm : I<0x9F, MRM0m,
2214 (outs), (ins i8mem:$dst),
2216 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2217 TB; // [mem8] = > signed
2219 def SETBr : I<0x92, MRM0r,
2220 (outs GR8 :$dst), (ins),
2222 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2223 TB; // GR8 = < unsign
2224 def SETBm : I<0x92, MRM0m,
2225 (outs), (ins i8mem:$dst),
2227 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
2228 TB; // [mem8] = < unsign
2229 def SETAEr : I<0x93, MRM0r,
2230 (outs GR8 :$dst), (ins),
2232 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
2233 TB; // GR8 = >= unsign
2234 def SETAEm : I<0x93, MRM0m,
2235 (outs), (ins i8mem:$dst),
2237 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
2238 TB; // [mem8] = >= unsign
2239 def SETBEr : I<0x96, MRM0r,
2240 (outs GR8 :$dst), (ins),
2242 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
2243 TB; // GR8 = <= unsign
2244 def SETBEm : I<0x96, MRM0m,
2245 (outs), (ins i8mem:$dst),
2247 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
2248 TB; // [mem8] = <= unsign
2249 def SETAr : I<0x97, MRM0r,
2250 (outs GR8 :$dst), (ins),
2252 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
2253 TB; // GR8 = > signed
2254 def SETAm : I<0x97, MRM0m,
2255 (outs), (ins i8mem:$dst),
2257 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
2258 TB; // [mem8] = > signed
2260 def SETSr : I<0x98, MRM0r,
2261 (outs GR8 :$dst), (ins),
2263 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
2264 TB; // GR8 = <sign bit>
2265 def SETSm : I<0x98, MRM0m,
2266 (outs), (ins i8mem:$dst),
2268 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
2269 TB; // [mem8] = <sign bit>
2270 def SETNSr : I<0x99, MRM0r,
2271 (outs GR8 :$dst), (ins),
2273 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
2274 TB; // GR8 = !<sign bit>
2275 def SETNSm : I<0x99, MRM0m,
2276 (outs), (ins i8mem:$dst),
2278 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
2279 TB; // [mem8] = !<sign bit>
2280 def SETPr : I<0x9A, MRM0r,
2281 (outs GR8 :$dst), (ins),
2283 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
2285 def SETPm : I<0x9A, MRM0m,
2286 (outs), (ins i8mem:$dst),
2288 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
2289 TB; // [mem8] = parity
2290 def SETNPr : I<0x9B, MRM0r,
2291 (outs GR8 :$dst), (ins),
2293 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
2294 TB; // GR8 = not parity
2295 def SETNPm : I<0x9B, MRM0m,
2296 (outs), (ins i8mem:$dst),
2298 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
2299 TB; // [mem8] = not parity
2300 } // Uses = [EFLAGS]
2303 // Integer comparisons
2304 let Defs = [EFLAGS] in {
2305 def CMP8rr : I<0x38, MRMDestReg,
2306 (outs), (ins GR8 :$src1, GR8 :$src2),
2307 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2308 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2309 def CMP16rr : I<0x39, MRMDestReg,
2310 (outs), (ins GR16:$src1, GR16:$src2),
2311 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2312 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
2313 def CMP32rr : I<0x39, MRMDestReg,
2314 (outs), (ins GR32:$src1, GR32:$src2),
2315 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2316 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
2317 def CMP8mr : I<0x38, MRMDestMem,
2318 (outs), (ins i8mem :$src1, GR8 :$src2),
2319 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2320 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
2321 (implicit EFLAGS)]>;
2322 def CMP16mr : I<0x39, MRMDestMem,
2323 (outs), (ins i16mem:$src1, GR16:$src2),
2324 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2325 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
2326 (implicit EFLAGS)]>, OpSize;
2327 def CMP32mr : I<0x39, MRMDestMem,
2328 (outs), (ins i32mem:$src1, GR32:$src2),
2329 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2330 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
2331 (implicit EFLAGS)]>;
2332 def CMP8rm : I<0x3A, MRMSrcMem,
2333 (outs), (ins GR8 :$src1, i8mem :$src2),
2334 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2335 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
2336 (implicit EFLAGS)]>;
2337 def CMP16rm : I<0x3B, MRMSrcMem,
2338 (outs), (ins GR16:$src1, i16mem:$src2),
2339 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2340 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
2341 (implicit EFLAGS)]>, OpSize;
2342 def CMP32rm : I<0x3B, MRMSrcMem,
2343 (outs), (ins GR32:$src1, i32mem:$src2),
2344 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2345 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
2346 (implicit EFLAGS)]>;
2347 def CMP8ri : Ii8<0x80, MRM7r,
2348 (outs), (ins GR8:$src1, i8imm:$src2),
2349 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2350 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
2351 def CMP16ri : Ii16<0x81, MRM7r,
2352 (outs), (ins GR16:$src1, i16imm:$src2),
2353 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2354 [(X86cmp GR16:$src1, imm:$src2),
2355 (implicit EFLAGS)]>, OpSize;
2356 def CMP32ri : Ii32<0x81, MRM7r,
2357 (outs), (ins GR32:$src1, i32imm:$src2),
2358 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2359 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
2360 def CMP8mi : Ii8 <0x80, MRM7m,
2361 (outs), (ins i8mem :$src1, i8imm :$src2),
2362 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2363 [(X86cmp (loadi8 addr:$src1), imm:$src2),
2364 (implicit EFLAGS)]>;
2365 def CMP16mi : Ii16<0x81, MRM7m,
2366 (outs), (ins i16mem:$src1, i16imm:$src2),
2367 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2368 [(X86cmp (loadi16 addr:$src1), imm:$src2),
2369 (implicit EFLAGS)]>, OpSize;
2370 def CMP32mi : Ii32<0x81, MRM7m,
2371 (outs), (ins i32mem:$src1, i32imm:$src2),
2372 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2373 [(X86cmp (loadi32 addr:$src1), imm:$src2),
2374 (implicit EFLAGS)]>;
2375 def CMP16ri8 : Ii8<0x83, MRM7r,
2376 (outs), (ins GR16:$src1, i16i8imm:$src2),
2377 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2378 [(X86cmp GR16:$src1, i16immSExt8:$src2),
2379 (implicit EFLAGS)]>, OpSize;
2380 def CMP16mi8 : Ii8<0x83, MRM7m,
2381 (outs), (ins i16mem:$src1, i16i8imm:$src2),
2382 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2383 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
2384 (implicit EFLAGS)]>, OpSize;
2385 def CMP32mi8 : Ii8<0x83, MRM7m,
2386 (outs), (ins i32mem:$src1, i32i8imm:$src2),
2387 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2388 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
2389 (implicit EFLAGS)]>;
2390 def CMP32ri8 : Ii8<0x83, MRM7r,
2391 (outs), (ins GR32:$src1, i32i8imm:$src2),
2392 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2393 [(X86cmp GR32:$src1, i32immSExt8:$src2),
2394 (implicit EFLAGS)]>;
2395 } // Defs = [EFLAGS]
2397 // Sign/Zero extenders
2398 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2399 "movs{bw|x}\t{$src, $dst|$dst, $src}",
2400 [(set GR16:$dst, (sext GR8:$src))]>, TB, OpSize;
2401 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2402 "movs{bw|x}\t{$src, $dst|$dst, $src}",
2403 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize;
2404 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2405 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2406 [(set GR32:$dst, (sext GR8:$src))]>, TB;
2407 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2408 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2409 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
2410 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2411 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2412 [(set GR32:$dst, (sext GR16:$src))]>, TB;
2413 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2414 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2415 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
2417 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2418 "movz{bw|x}\t{$src, $dst|$dst, $src}",
2419 [(set GR16:$dst, (zext GR8:$src))]>, TB, OpSize;
2420 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2421 "movz{bw|x}\t{$src, $dst|$dst, $src}",
2422 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize;
2423 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2424 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2425 [(set GR32:$dst, (zext GR8:$src))]>, TB;
2426 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2427 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2428 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
2429 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2430 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2431 [(set GR32:$dst, (zext GR16:$src))]>, TB;
2432 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2433 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2434 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
2436 let neverHasSideEffects = 1 in {
2437 let Defs = [AX], Uses = [AL] in
2438 def CBW : I<0x98, RawFrm, (outs), (ins),
2439 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
2440 let Defs = [EAX], Uses = [AX] in
2441 def CWDE : I<0x98, RawFrm, (outs), (ins),
2442 "{cwtl|cwde}", []>; // EAX = signext(AX)
2444 let Defs = [AX,DX], Uses = [AX] in
2445 def CWD : I<0x99, RawFrm, (outs), (ins),
2446 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
2447 let Defs = [EAX,EDX], Uses = [EAX] in
2448 def CDQ : I<0x99, RawFrm, (outs), (ins),
2449 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
2452 //===----------------------------------------------------------------------===//
2453 // Alias Instructions
2454 //===----------------------------------------------------------------------===//
2456 // Alias instructions that map movr0 to xor.
2457 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2458 let Defs = [EFLAGS], isReMaterializable = 1 in {
2459 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
2460 "xor{b}\t$dst, $dst",
2461 [(set GR8:$dst, 0)]>;
2462 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
2463 "xor{w}\t$dst, $dst",
2464 [(set GR16:$dst, 0)]>, OpSize;
2465 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
2466 "xor{l}\t$dst, $dst",
2467 [(set GR32:$dst, 0)]>;
2470 // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
2471 // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
2472 let neverHasSideEffects = 1 in {
2473 def MOV16to16_ : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16:$src),
2474 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2475 def MOV32to32_ : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32:$src),
2476 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2478 def MOV16_rr : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16_:$src),
2479 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2480 def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src),
2481 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2482 } // neverHasSideEffects
2484 let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
2485 def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src),
2486 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2487 def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src),
2488 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2490 let mayStore = 1, neverHasSideEffects = 1 in {
2491 def MOV16_mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16_:$src),
2492 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2493 def MOV32_mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32_:$src),
2494 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2497 //===----------------------------------------------------------------------===//
2498 // Thread Local Storage Instructions
2502 def TLS_addr : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
2503 "leal\t${sym:mem}(,%ebx,1), $dst",
2504 [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
2506 let AddedComplexity = 10 in
2507 def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
2508 "movl\t%gs:($src), $dst",
2509 [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
2511 let AddedComplexity = 15 in
2512 def TLS_gs_ri : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
2513 "movl\t%gs:${src:mem}, $dst",
2515 (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>;
2517 def TLS_tp : I<0, Pseudo, (outs GR32:$dst), (ins),
2518 "movl\t%gs:0, $dst",
2519 [(set GR32:$dst, X86TLStp)]>;
2521 //===----------------------------------------------------------------------===//
2522 // DWARF Pseudo Instructions
2525 def DWARF_LOC : I<0, Pseudo, (outs),
2526 (ins i32imm:$line, i32imm:$col, i32imm:$file),
2527 ".loc\t${file:debug} ${line:debug} ${col:debug}",
2528 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
2531 //===----------------------------------------------------------------------===//
2532 // EH Pseudo Instructions
2534 let isTerminator = 1, isReturn = 1, isBarrier = 1,
2536 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
2537 "ret\t#eh_return, addr: $addr",
2538 [(X86ehret GR32:$addr)]>;
2542 //===----------------------------------------------------------------------===//
2546 //FIXME: Please check the format Pseudo is certainly wrong, but the opcode and
2547 // prefixes should be correct
2549 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
2550 def CMPXCHG32 : I<0xB1, Pseudo, (outs), (ins i32mem:$ptr, GR32:$swap),
2551 "cmpxchgl $swap,$ptr", []>, TB;
2552 def LCMPXCHG32 : I<0xB1, Pseudo, (outs), (ins i32mem:$ptr, GR32:$swap),
2553 "lock cmpxchgl $swap,$ptr",
2554 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
2556 let Defs = [EAX, EBX, ECX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
2557 def CMPXCHG8B : I<0xC7, Pseudo, (outs), (ins i32mem:$ptr),
2558 "cmpxchg8b $ptr", []>, TB;
2559 def LCMPXCHG8B : I<0xC7, Pseudo, (outs), (ins i32mem:$ptr),
2560 "lock cmpxchg8b $ptr",
2561 [(X86cas8 addr:$ptr)]>, TB, LOCK;
2564 let Defs = [AX, EFLAGS], Uses = [AX] in {
2565 def CMPXCHG16 : I<0xB1, Pseudo, (outs), (ins i16mem:$ptr, GR16:$swap),
2566 "cmpxchgw $swap,($ptr)", []>, TB, OpSize;
2567 def LCMPXCHG16 : I<0xB1, Pseudo, (outs), (ins i16mem:$ptr, GR16:$swap),
2568 "lock cmpxchgw $swap,$ptr",
2569 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
2571 let Defs = [AL, EFLAGS], Uses = [AL] in {
2572 def CMPXCHG8 : I<0xB0, Pseudo, (outs), (ins i8mem:$ptr, GR8:$swap),
2573 "cmpxchgb $swap,($ptr)", []>, TB;
2574 def LCMPXCHG8 : I<0xB0, Pseudo, (outs), (ins i8mem:$ptr, GR8:$swap),
2575 "lock cmpxchgb $swap,$ptr",
2576 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
2579 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
2580 def LXADD32 : I<0xC1, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2581 "lock xadd $val, $ptr",
2582 [(set GR32:$dst, (atomic_las_32 addr:$ptr, GR32:$val))]>,
2584 def LXADD16 : I<0xC1, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2585 "lock xadd $val, $ptr",
2586 [(set GR16:$dst, (atomic_las_16 addr:$ptr, GR16:$val))]>,
2588 def LXADD8 : I<0xC0, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2589 "lock xadd $val, $ptr",
2590 [(set GR8:$dst, (atomic_las_8 addr:$ptr, GR8:$val))]>,
2592 def XADD32 : I<0xC1, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2593 "xadd $val, $ptr", []>, TB;
2594 def XADD16 : I<0xC1, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2595 "xadd $val, $ptr", []>, TB, OpSize;
2596 def XADD8 : I<0xC0, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2597 "xadd $val, $ptr", []>, TB;
2599 def LXCHG32 : I<0x87, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2600 "lock xchg $val, $ptr",
2601 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>, LOCK;
2602 def LXCHG16 : I<0x87, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2603 "lock xchg $val, $ptr",
2604 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
2606 def LXCHG8 : I<0x86, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2607 "lock xchg $val, $ptr",
2608 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>, LOCK;
2609 def XCHG32 : I<0x87, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2610 "xchg $val, $ptr", []>;
2611 def XCHG16 : I<0x87, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2612 "xchg $val, $ptr", []>, OpSize;
2613 def XCHG8 : I<0x86, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2614 "xchg $val, $ptr", []>;
2617 //===----------------------------------------------------------------------===//
2618 // Non-Instruction Patterns
2619 //===----------------------------------------------------------------------===//
2621 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
2622 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
2623 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
2624 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
2625 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
2626 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
2628 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
2629 (ADD32ri GR32:$src1, tconstpool:$src2)>;
2630 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
2631 (ADD32ri GR32:$src1, tjumptable:$src2)>;
2632 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
2633 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
2634 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
2635 (ADD32ri GR32:$src1, texternalsym:$src2)>;
2637 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
2638 (MOV32mi addr:$dst, tglobaladdr:$src)>;
2639 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
2640 (MOV32mi addr:$dst, texternalsym:$src)>;
2644 def : Pat<(X86tailcall GR32:$dst),
2647 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
2649 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
2652 def : Pat<(X86tcret GR32:$dst, imm:$off),
2653 (TCRETURNri GR32:$dst, imm:$off)>;
2655 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
2656 (TCRETURNdi texternalsym:$dst, imm:$off)>;
2658 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
2659 (TCRETURNdi texternalsym:$dst, imm:$off)>;
2661 def : Pat<(X86call (i32 tglobaladdr:$dst)),
2662 (CALLpcrel32 tglobaladdr:$dst)>;
2663 def : Pat<(X86call (i32 texternalsym:$dst)),
2664 (CALLpcrel32 texternalsym:$dst)>;
2666 // X86 specific add which produces a flag.
2667 def : Pat<(addc GR32:$src1, GR32:$src2),
2668 (ADD32rr GR32:$src1, GR32:$src2)>;
2669 def : Pat<(addc GR32:$src1, (load addr:$src2)),
2670 (ADD32rm GR32:$src1, addr:$src2)>;
2671 def : Pat<(addc GR32:$src1, imm:$src2),
2672 (ADD32ri GR32:$src1, imm:$src2)>;
2673 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
2674 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
2676 def : Pat<(subc GR32:$src1, GR32:$src2),
2677 (SUB32rr GR32:$src1, GR32:$src2)>;
2678 def : Pat<(subc GR32:$src1, (load addr:$src2)),
2679 (SUB32rm GR32:$src1, addr:$src2)>;
2680 def : Pat<(subc GR32:$src1, imm:$src2),
2681 (SUB32ri GR32:$src1, imm:$src2)>;
2682 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
2683 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
2687 // TEST R,R is smaller than CMP R,0
2688 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
2689 (TEST8rr GR8:$src1, GR8:$src1)>;
2690 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
2691 (TEST16rr GR16:$src1, GR16:$src1)>;
2692 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
2693 (TEST32rr GR32:$src1, GR32:$src1)>;
2695 // zextload bool -> zextload byte
2696 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2697 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2698 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2700 // extload bool -> extload byte
2701 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2702 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2703 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2704 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
2705 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
2706 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
2709 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
2710 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
2711 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
2712 def : Pat<(i16 (anyext (loadi8 addr:$src))), (MOVZX16rm8 addr:$src)>;
2713 def : Pat<(i32 (anyext (loadi8 addr:$src))), (MOVZX32rm8 addr:$src)>;
2714 def : Pat<(i32 (anyext (loadi16 addr:$src))), (MOVZX32rm16 addr:$src)>;
2716 // (and (i32 load), 255) -> (zextload i8)
2717 def : Pat<(i32 (and (loadi32 addr:$src), (i32 255))), (MOVZX32rm8 addr:$src)>;
2718 def : Pat<(i32 (and (loadi32 addr:$src), (i32 65535))),(MOVZX32rm16 addr:$src)>;
2720 //===----------------------------------------------------------------------===//
2722 //===----------------------------------------------------------------------===//
2724 // (shl x, 1) ==> (add x, x)
2725 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
2726 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
2727 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
2729 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
2730 def : Pat<(or (srl GR32:$src1, CL:$amt),
2731 (shl GR32:$src2, (sub 32, CL:$amt))),
2732 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
2734 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
2735 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2736 (SHRD32mrCL addr:$dst, GR32:$src2)>;
2738 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
2739 def : Pat<(or (shl GR32:$src1, CL:$amt),
2740 (srl GR32:$src2, (sub 32, CL:$amt))),
2741 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
2743 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
2744 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2745 (SHLD32mrCL addr:$dst, GR32:$src2)>;
2747 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
2748 def : Pat<(or (srl GR16:$src1, CL:$amt),
2749 (shl GR16:$src2, (sub 16, CL:$amt))),
2750 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
2752 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
2753 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2754 (SHRD16mrCL addr:$dst, GR16:$src2)>;
2756 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
2757 def : Pat<(or (shl GR16:$src1, CL:$amt),
2758 (srl GR16:$src2, (sub 16, CL:$amt))),
2759 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
2761 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
2762 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2763 (SHLD16mrCL addr:$dst, GR16:$src2)>;
2765 //===----------------------------------------------------------------------===//
2766 // Floating Point Stack Support
2767 //===----------------------------------------------------------------------===//
2769 include "X86InstrFPStack.td"
2771 //===----------------------------------------------------------------------===//
2773 //===----------------------------------------------------------------------===//
2775 include "X86Instr64bit.td"
2777 //===----------------------------------------------------------------------===//
2778 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
2779 //===----------------------------------------------------------------------===//
2781 include "X86InstrMMX.td"
2783 //===----------------------------------------------------------------------===//
2784 // XMM Floating point support (requires SSE / SSE2)
2785 //===----------------------------------------------------------------------===//
2787 include "X86InstrSSE.td"