1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
33 def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
37 def SDTX86BrCond : SDTypeProfile<0, 3,
38 [SDTCisVT<0, OtherVT>,
39 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
41 def SDTX86SetCC : SDTypeProfile<1, 2,
43 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
47 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
49 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
50 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
51 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
53 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
54 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
57 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
59 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
61 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
63 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
65 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
67 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
69 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
71 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
73 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
74 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
75 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
76 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
78 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
80 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
82 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
83 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
85 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
87 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
88 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
90 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
91 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
93 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
94 [SDNPHasChain, SDNPMayStore,
95 SDNPMayLoad, SDNPMemOperand]>;
96 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
97 [SDNPHasChain, SDNPMayStore,
98 SDNPMayLoad, SDNPMemOperand]>;
99 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
100 [SDNPHasChain, SDNPMayStore,
101 SDNPMayLoad, SDNPMemOperand]>;
102 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
103 [SDNPHasChain, SDNPMayStore,
104 SDNPMayLoad, SDNPMemOperand]>;
105 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
106 [SDNPHasChain, SDNPMayStore,
107 SDNPMayLoad, SDNPMemOperand]>;
108 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
109 [SDNPHasChain, SDNPMayStore,
110 SDNPMayLoad, SDNPMemOperand]>;
111 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
112 [SDNPHasChain, SDNPMayStore,
113 SDNPMayLoad, SDNPMemOperand]>;
114 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
115 [SDNPHasChain, SDNPOptInFlag]>;
117 def X86callseq_start :
118 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
119 [SDNPHasChain, SDNPOutFlag]>;
121 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
122 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
124 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
125 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
127 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
128 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
129 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
130 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
133 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
134 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
136 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
137 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
139 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
140 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
141 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
142 SDT_X86SegmentBaseAddress, []>;
144 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
147 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
148 [SDNPHasChain, SDNPOptInFlag]>;
150 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags>;
151 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
152 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags>;
153 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>;
154 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
155 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
157 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
159 //===----------------------------------------------------------------------===//
160 // X86 Operand Definitions.
163 def i32imm_pcrel : Operand<i32> {
164 let PrintMethod = "print_pcrel_imm";
167 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
168 // the index operand of an address, to conform to x86 encoding restrictions.
169 def ptr_rc_nosp : PointerLikeRegClass<1>;
171 // *mem - Operand definitions for the funky X86 addressing mode operands.
173 def X86MemAsmOperand : AsmOperandClass {
177 class X86MemOperand<string printMethod> : Operand<iPTR> {
178 let PrintMethod = printMethod;
179 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
180 let ParserMatchClass = X86MemAsmOperand;
183 def i8mem : X86MemOperand<"printi8mem">;
184 def i16mem : X86MemOperand<"printi16mem">;
185 def i32mem : X86MemOperand<"printi32mem">;
186 def i64mem : X86MemOperand<"printi64mem">;
187 def i128mem : X86MemOperand<"printi128mem">;
188 def i256mem : X86MemOperand<"printi256mem">;
189 def f32mem : X86MemOperand<"printf32mem">;
190 def f64mem : X86MemOperand<"printf64mem">;
191 def f80mem : X86MemOperand<"printf80mem">;
192 def f128mem : X86MemOperand<"printf128mem">;
193 def f256mem : X86MemOperand<"printf256mem">;
195 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
196 // plain GR64, so that it doesn't potentially require a REX prefix.
197 def i8mem_NOREX : Operand<i64> {
198 let PrintMethod = "printi8mem";
199 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
200 let ParserMatchClass = X86MemAsmOperand;
203 def lea32mem : Operand<i32> {
204 let PrintMethod = "printlea32mem";
205 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
206 let ParserMatchClass = X86MemAsmOperand;
209 def SSECC : Operand<i8> {
210 let PrintMethod = "printSSECC";
213 def piclabel: Operand<i32> {
214 let PrintMethod = "printPICLabel";
217 def ImmSExt8AsmOperand : AsmOperandClass {
218 let Name = "ImmSExt8";
219 let SuperClass = ImmAsmOperand;
222 // A couple of more descriptive operand definitions.
223 // 16-bits but only 8 bits are significant.
224 def i16i8imm : Operand<i16> {
225 let ParserMatchClass = ImmSExt8AsmOperand;
227 // 32-bits but only 8 bits are significant.
228 def i32i8imm : Operand<i32> {
229 let ParserMatchClass = ImmSExt8AsmOperand;
232 // Branch targets have OtherVT type and print as pc-relative values.
233 def brtarget : Operand<OtherVT> {
234 let PrintMethod = "print_pcrel_imm";
237 def brtarget8 : Operand<OtherVT> {
238 let PrintMethod = "print_pcrel_imm";
241 //===----------------------------------------------------------------------===//
242 // X86 Complex Pattern Definitions.
245 // Define X86 specific addressing mode.
246 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
247 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
248 [add, sub, mul, X86mul_imm, shl, or, frameindex],
250 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
251 [tglobaltlsaddr], []>;
253 //===----------------------------------------------------------------------===//
254 // X86 Instruction Predicate Definitions.
255 def HasMMX : Predicate<"Subtarget->hasMMX()">;
256 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
257 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
258 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
259 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
260 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
261 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
262 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
263 def HasAVX : Predicate<"Subtarget->hasAVX()">;
264 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
265 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
266 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
267 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
268 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
269 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
270 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
271 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
272 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
273 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
274 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
275 "TM.getCodeModel() != CodeModel::Kernel">;
276 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
277 "TM.getCodeModel() == CodeModel::Kernel">;
278 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
279 def OptForSpeed : Predicate<"!OptForSize">;
280 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
281 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
283 //===----------------------------------------------------------------------===//
284 // X86 Instruction Format Definitions.
287 include "X86InstrFormats.td"
289 //===----------------------------------------------------------------------===//
290 // Pattern fragments...
293 // X86 specific condition code. These correspond to CondCode in
294 // X86InstrInfo.h. They must be kept in synch.
295 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
296 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
297 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
298 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
299 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
300 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
301 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
302 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
303 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
304 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
305 def X86_COND_NO : PatLeaf<(i8 10)>;
306 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
307 def X86_COND_NS : PatLeaf<(i8 12)>;
308 def X86_COND_O : PatLeaf<(i8 13)>;
309 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
310 def X86_COND_S : PatLeaf<(i8 15)>;
312 def i16immSExt8 : PatLeaf<(i16 imm), [{
313 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
314 // sign extended field.
315 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
318 def i32immSExt8 : PatLeaf<(i32 imm), [{
319 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
320 // sign extended field.
321 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
324 // Helper fragments for loads.
325 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
326 // known to be 32-bit aligned or better. Ditto for i8 to i16.
327 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
328 LoadSDNode *LD = cast<LoadSDNode>(N);
329 if (const Value *Src = LD->getSrcValue())
330 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
331 if (PT->getAddressSpace() > 255)
333 ISD::LoadExtType ExtType = LD->getExtensionType();
334 if (ExtType == ISD::NON_EXTLOAD)
336 if (ExtType == ISD::EXTLOAD)
337 return LD->getAlignment() >= 2 && !LD->isVolatile();
341 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
342 LoadSDNode *LD = cast<LoadSDNode>(N);
343 if (const Value *Src = LD->getSrcValue())
344 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
345 if (PT->getAddressSpace() > 255)
347 ISD::LoadExtType ExtType = LD->getExtensionType();
348 if (ExtType == ISD::EXTLOAD)
349 return LD->getAlignment() >= 2 && !LD->isVolatile();
353 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
354 LoadSDNode *LD = cast<LoadSDNode>(N);
355 if (const Value *Src = LD->getSrcValue())
356 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
357 if (PT->getAddressSpace() > 255)
359 ISD::LoadExtType ExtType = LD->getExtensionType();
360 if (ExtType == ISD::NON_EXTLOAD)
362 if (ExtType == ISD::EXTLOAD)
363 return LD->getAlignment() >= 4 && !LD->isVolatile();
367 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
368 LoadSDNode *LD = cast<LoadSDNode>(N);
369 if (const Value *Src = LD->getSrcValue())
370 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
371 if (PT->getAddressSpace() > 255)
373 if (LD->isVolatile())
375 ISD::LoadExtType ExtType = LD->getExtensionType();
376 if (ExtType == ISD::NON_EXTLOAD)
378 if (ExtType == ISD::EXTLOAD)
379 return LD->getAlignment() >= 4;
383 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
384 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
385 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
386 return PT->getAddressSpace() == 256;
390 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
391 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
392 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
393 return PT->getAddressSpace() == 257;
397 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{
398 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
399 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
400 if (PT->getAddressSpace() > 255)
404 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{
405 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
406 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
407 if (PT->getAddressSpace() > 255)
412 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{
413 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
414 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
415 if (PT->getAddressSpace() > 255)
419 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{
420 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
421 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
422 if (PT->getAddressSpace() > 255)
426 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{
427 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
428 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
429 if (PT->getAddressSpace() > 255)
434 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
435 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
436 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
438 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
439 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
440 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
441 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
442 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
443 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
445 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
446 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
447 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
448 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
449 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
450 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
453 // An 'and' node with a single use.
454 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
455 return N->hasOneUse();
457 // An 'srl' node with a single use.
458 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
459 return N->hasOneUse();
461 // An 'trunc' node with a single use.
462 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
463 return N->hasOneUse();
466 // 'shld' and 'shrd' instruction patterns. Note that even though these have
467 // the srl and shl in their patterns, the C++ code must still check for them,
468 // because predicates are tested before children nodes are explored.
470 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
471 (or (srl node:$src1, node:$amt1),
472 (shl node:$src2, node:$amt2)), [{
473 assert(N->getOpcode() == ISD::OR);
474 return N->getOperand(0).getOpcode() == ISD::SRL &&
475 N->getOperand(1).getOpcode() == ISD::SHL &&
476 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
477 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
478 N->getOperand(0).getConstantOperandVal(1) ==
479 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
482 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
483 (or (shl node:$src1, node:$amt1),
484 (srl node:$src2, node:$amt2)), [{
485 assert(N->getOpcode() == ISD::OR);
486 return N->getOperand(0).getOpcode() == ISD::SHL &&
487 N->getOperand(1).getOpcode() == ISD::SRL &&
488 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
489 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
490 N->getOperand(0).getConstantOperandVal(1) ==
491 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
494 //===----------------------------------------------------------------------===//
495 // Instruction list...
498 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
499 // a stack adjustment and the codegen must know that they may modify the stack
500 // pointer before prolog-epilog rewriting occurs.
501 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
502 // sub / add which can clobber EFLAGS.
503 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
504 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
506 [(X86callseq_start timm:$amt)]>,
507 Requires<[In32BitMode]>;
508 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
510 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
511 Requires<[In32BitMode]>;
515 let neverHasSideEffects = 1 in {
516 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
517 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
518 "nopl\t$zero", []>, TB;
522 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int 3", []>;
523 def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
526 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
527 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
531 //===----------------------------------------------------------------------===//
532 // Control Flow Instructions...
535 // Return instructions.
536 let isTerminator = 1, isReturn = 1, isBarrier = 1,
537 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
538 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
541 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
543 [(X86retflag imm:$amt)]>;
546 // All branches are RawFrm, Void, Branch, and Terminators
547 let isBranch = 1, isTerminator = 1 in
548 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
549 I<opcode, RawFrm, (outs), ins, asm, pattern>;
551 let isBranch = 1, isBarrier = 1 in {
552 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
553 def JMP8 : IBr<0xEB, (ins brtarget8:$dst), "jmp\t$dst", []>;
557 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
558 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
559 [(brind GR32:$dst)]>;
560 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
561 [(brind (loadi32 addr:$dst))]>;
564 // Conditional branches
565 let Uses = [EFLAGS] in {
566 // Short conditional jumps
567 def JO8 : IBr<0x70, (ins brtarget8:$dst), "jo\t$dst", []>;
568 def JNO8 : IBr<0x71, (ins brtarget8:$dst), "jno\t$dst", []>;
569 def JB8 : IBr<0x72, (ins brtarget8:$dst), "jb\t$dst", []>;
570 def JAE8 : IBr<0x73, (ins brtarget8:$dst), "jae\t$dst", []>;
571 def JE8 : IBr<0x74, (ins brtarget8:$dst), "je\t$dst", []>;
572 def JNE8 : IBr<0x75, (ins brtarget8:$dst), "jne\t$dst", []>;
573 def JBE8 : IBr<0x76, (ins brtarget8:$dst), "jbe\t$dst", []>;
574 def JA8 : IBr<0x77, (ins brtarget8:$dst), "ja\t$dst", []>;
575 def JS8 : IBr<0x78, (ins brtarget8:$dst), "js\t$dst", []>;
576 def JNS8 : IBr<0x79, (ins brtarget8:$dst), "jns\t$dst", []>;
577 def JP8 : IBr<0x7A, (ins brtarget8:$dst), "jp\t$dst", []>;
578 def JNP8 : IBr<0x7B, (ins brtarget8:$dst), "jnp\t$dst", []>;
579 def JL8 : IBr<0x7C, (ins brtarget8:$dst), "jl\t$dst", []>;
580 def JGE8 : IBr<0x7D, (ins brtarget8:$dst), "jge\t$dst", []>;
581 def JLE8 : IBr<0x7E, (ins brtarget8:$dst), "jle\t$dst", []>;
582 def JG8 : IBr<0x7F, (ins brtarget8:$dst), "jg\t$dst", []>;
584 def JCXZ8 : IBr<0xE3, (ins brtarget8:$dst), "jcxz\t$dst", []>;
586 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
587 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
588 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
589 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
590 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
591 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
592 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
593 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
594 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
595 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
596 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
597 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
599 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
600 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
601 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
602 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
603 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
604 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
605 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
606 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
608 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
609 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
610 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
611 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
612 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
613 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
614 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
615 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
616 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
617 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
618 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
619 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
622 //===----------------------------------------------------------------------===//
623 // Call Instructions...
626 // All calls clobber the non-callee saved registers. ESP is marked as
627 // a use to prevent stack-pointer assignments that appear immediately
628 // before calls from potentially appearing dead. Uses for argument
629 // registers are added manually.
630 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
631 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
632 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
633 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
635 def CALLpcrel32 : Ii32<0xE8, RawFrm,
636 (outs), (ins i32imm_pcrel:$dst,variable_ops),
638 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
639 "call\t{*}$dst", [(X86call GR32:$dst)]>;
640 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
641 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
646 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
647 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops),
648 "#TC_RETURN $dst $offset",
651 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
652 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops),
653 "#TC_RETURN $dst $offset",
656 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
658 def TAILJMPd : IBr<0xE9, (ins i32imm_pcrel:$dst), "jmp\t$dst # TAILCALL",
660 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
661 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
663 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
664 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
665 "jmp\t{*}$dst # TAILCALL", []>;
667 //===----------------------------------------------------------------------===//
668 // Miscellaneous Instructions...
670 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
671 def LEAVE : I<0xC9, RawFrm,
672 (outs), (ins), "leave", []>;
674 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
676 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
679 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
682 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
683 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
684 "push{l}\t$imm", []>;
685 def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
686 "push{l}\t$imm", []>;
687 def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
688 "push{l}\t$imm", []>;
691 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
692 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
693 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
694 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
696 let isTwoAddress = 1 in // GR32 = bswap GR32
697 def BSWAP32r : I<0xC8, AddRegFrm,
698 (outs GR32:$dst), (ins GR32:$src),
700 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
703 // Bit scan instructions.
704 let Defs = [EFLAGS] in {
705 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
706 "bsf{w}\t{$src, $dst|$dst, $src}",
707 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
708 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
709 "bsf{w}\t{$src, $dst|$dst, $src}",
710 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
711 (implicit EFLAGS)]>, TB;
712 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
713 "bsf{l}\t{$src, $dst|$dst, $src}",
714 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
715 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
716 "bsf{l}\t{$src, $dst|$dst, $src}",
717 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
718 (implicit EFLAGS)]>, TB;
720 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
721 "bsr{w}\t{$src, $dst|$dst, $src}",
722 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
723 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
724 "bsr{w}\t{$src, $dst|$dst, $src}",
725 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
726 (implicit EFLAGS)]>, TB;
727 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
728 "bsr{l}\t{$src, $dst|$dst, $src}",
729 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
730 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
731 "bsr{l}\t{$src, $dst|$dst, $src}",
732 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
733 (implicit EFLAGS)]>, TB;
736 let neverHasSideEffects = 1 in
737 def LEA16r : I<0x8D, MRMSrcMem,
738 (outs GR16:$dst), (ins i32mem:$src),
739 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
740 let isReMaterializable = 1 in
741 def LEA32r : I<0x8D, MRMSrcMem,
742 (outs GR32:$dst), (ins lea32mem:$src),
743 "lea{l}\t{$src|$dst}, {$dst|$src}",
744 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
746 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
747 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
748 [(X86rep_movs i8)]>, REP;
749 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
750 [(X86rep_movs i16)]>, REP, OpSize;
751 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
752 [(X86rep_movs i32)]>, REP;
755 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
756 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
757 [(X86rep_stos i8)]>, REP;
758 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
759 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
760 [(X86rep_stos i16)]>, REP, OpSize;
761 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
762 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
763 [(X86rep_stos i32)]>, REP;
765 let Defs = [RAX, RDX] in
766 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
769 let isBarrier = 1, hasCtrlDep = 1 in {
770 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
773 def SYSCALL : I<0x05, RawFrm,
774 (outs), (ins), "syscall", []>, TB;
775 def SYSRET : I<0x07, RawFrm,
776 (outs), (ins), "sysret", []>, TB;
777 def SYSENTER : I<0x34, RawFrm,
778 (outs), (ins), "sysenter", []>, TB;
779 def SYSEXIT : I<0x35, RawFrm,
780 (outs), (ins), "sysexit", []>, TB;
784 //===----------------------------------------------------------------------===//
785 // Input/Output Instructions...
787 let Defs = [AL], Uses = [DX] in
788 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
789 "in{b}\t{%dx, %al|%AL, %DX}", []>;
790 let Defs = [AX], Uses = [DX] in
791 def IN16rr : I<0xED, RawFrm, (outs), (ins),
792 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
793 let Defs = [EAX], Uses = [DX] in
794 def IN32rr : I<0xED, RawFrm, (outs), (ins),
795 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
798 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
799 "in{b}\t{$port, %al|%AL, $port}", []>;
801 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
802 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
804 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
805 "in{l}\t{$port, %eax|%EAX, $port}", []>;
807 let Uses = [DX, AL] in
808 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
809 "out{b}\t{%al, %dx|%DX, %AL}", []>;
810 let Uses = [DX, AX] in
811 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
812 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
813 let Uses = [DX, EAX] in
814 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
815 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
818 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
819 "out{b}\t{%al, $port|$port, %AL}", []>;
821 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
822 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
824 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
825 "out{l}\t{%eax, $port|$port, %EAX}", []>;
827 //===----------------------------------------------------------------------===//
828 // Move Instructions...
830 let neverHasSideEffects = 1 in {
831 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
832 "mov{b}\t{$src, $dst|$dst, $src}", []>;
833 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
834 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
835 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
836 "mov{l}\t{$src, $dst|$dst, $src}", []>;
838 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
839 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
840 "mov{b}\t{$src, $dst|$dst, $src}",
841 [(set GR8:$dst, imm:$src)]>;
842 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
843 "mov{w}\t{$src, $dst|$dst, $src}",
844 [(set GR16:$dst, imm:$src)]>, OpSize;
845 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
846 "mov{l}\t{$src, $dst|$dst, $src}",
847 [(set GR32:$dst, imm:$src)]>;
849 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
850 "mov{b}\t{$src, $dst|$dst, $src}",
851 [(store (i8 imm:$src), addr:$dst)]>;
852 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
853 "mov{w}\t{$src, $dst|$dst, $src}",
854 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
855 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
856 "mov{l}\t{$src, $dst|$dst, $src}",
857 [(store (i32 imm:$src), addr:$dst)]>;
859 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
860 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
861 "mov{b}\t{$src, $dst|$dst, $src}",
862 [(set GR8:$dst, (loadi8 addr:$src))]>;
863 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
864 "mov{w}\t{$src, $dst|$dst, $src}",
865 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
866 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
867 "mov{l}\t{$src, $dst|$dst, $src}",
868 [(set GR32:$dst, (loadi32 addr:$src))]>;
871 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
872 "mov{b}\t{$src, $dst|$dst, $src}",
873 [(store GR8:$src, addr:$dst)]>;
874 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
875 "mov{w}\t{$src, $dst|$dst, $src}",
876 [(store GR16:$src, addr:$dst)]>, OpSize;
877 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
878 "mov{l}\t{$src, $dst|$dst, $src}",
879 [(store GR32:$src, addr:$dst)]>;
881 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
882 // that they can be used for copying and storing h registers, which can't be
883 // encoded when a REX prefix is present.
884 let neverHasSideEffects = 1 in
885 def MOV8rr_NOREX : I<0x88, MRMDestReg,
886 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
887 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
889 def MOV8mr_NOREX : I<0x88, MRMDestMem,
890 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
891 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
893 canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
894 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
895 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
896 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
898 //===----------------------------------------------------------------------===//
899 // Fixed-Register Multiplication and Division Instructions...
902 // Extra precision multiplication
903 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
904 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
905 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
906 // This probably ought to be moved to a def : Pat<> if the
907 // syntax can be accepted.
908 [(set AL, (mul AL, GR8:$src)),
909 (implicit EFLAGS)]>; // AL,AH = AL*GR8
911 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
912 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
914 []>, OpSize; // AX,DX = AX*GR16
916 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
917 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
919 []>; // EAX,EDX = EAX*GR32
921 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
922 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
924 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
925 // This probably ought to be moved to a def : Pat<> if the
926 // syntax can be accepted.
927 [(set AL, (mul AL, (loadi8 addr:$src))),
928 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
930 let mayLoad = 1, neverHasSideEffects = 1 in {
931 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
932 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
934 []>, OpSize; // AX,DX = AX*[mem16]
936 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
937 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
939 []>; // EAX,EDX = EAX*[mem32]
942 let neverHasSideEffects = 1 in {
943 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
944 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
946 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
947 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
948 OpSize; // AX,DX = AX*GR16
949 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
950 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
951 // EAX,EDX = EAX*GR32
953 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
954 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
955 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
956 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
957 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
958 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
959 let Defs = [EAX,EDX], Uses = [EAX] in
960 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
961 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
963 } // neverHasSideEffects
965 // unsigned division/remainder
966 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
967 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
969 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
970 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
971 "div{w}\t$src", []>, OpSize;
972 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
973 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
976 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
977 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
979 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
980 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
981 "div{w}\t$src", []>, OpSize;
982 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
983 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
987 // Signed division/remainder.
988 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
989 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
990 "idiv{b}\t$src", []>;
991 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
992 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
993 "idiv{w}\t$src", []>, OpSize;
994 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
995 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
996 "idiv{l}\t$src", []>;
997 let mayLoad = 1, mayLoad = 1 in {
998 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
999 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1000 "idiv{b}\t$src", []>;
1001 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1002 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1003 "idiv{w}\t$src", []>, OpSize;
1004 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1005 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
1006 "idiv{l}\t$src", []>;
1009 //===----------------------------------------------------------------------===//
1010 // Two address Instructions.
1012 let isTwoAddress = 1 in {
1014 // Conditional moves
1015 let Uses = [EFLAGS] in {
1016 let isCommutable = 1 in {
1017 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1018 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1019 "cmovb\t{$src2, $dst|$dst, $src2}",
1020 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1021 X86_COND_B, EFLAGS))]>,
1023 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1024 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1025 "cmovb\t{$src2, $dst|$dst, $src2}",
1026 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1027 X86_COND_B, EFLAGS))]>,
1029 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1030 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1031 "cmovae\t{$src2, $dst|$dst, $src2}",
1032 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1033 X86_COND_AE, EFLAGS))]>,
1035 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1036 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1037 "cmovae\t{$src2, $dst|$dst, $src2}",
1038 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1039 X86_COND_AE, EFLAGS))]>,
1041 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1042 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1043 "cmove\t{$src2, $dst|$dst, $src2}",
1044 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1045 X86_COND_E, EFLAGS))]>,
1047 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1048 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1049 "cmove\t{$src2, $dst|$dst, $src2}",
1050 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1051 X86_COND_E, EFLAGS))]>,
1053 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1054 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1055 "cmovne\t{$src2, $dst|$dst, $src2}",
1056 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1057 X86_COND_NE, EFLAGS))]>,
1059 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1060 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1061 "cmovne\t{$src2, $dst|$dst, $src2}",
1062 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1063 X86_COND_NE, EFLAGS))]>,
1065 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1066 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1067 "cmovbe\t{$src2, $dst|$dst, $src2}",
1068 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1069 X86_COND_BE, EFLAGS))]>,
1071 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1072 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1073 "cmovbe\t{$src2, $dst|$dst, $src2}",
1074 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1075 X86_COND_BE, EFLAGS))]>,
1077 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1078 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1079 "cmova\t{$src2, $dst|$dst, $src2}",
1080 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1081 X86_COND_A, EFLAGS))]>,
1083 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1084 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1085 "cmova\t{$src2, $dst|$dst, $src2}",
1086 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1087 X86_COND_A, EFLAGS))]>,
1089 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1090 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1091 "cmovl\t{$src2, $dst|$dst, $src2}",
1092 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1093 X86_COND_L, EFLAGS))]>,
1095 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1096 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1097 "cmovl\t{$src2, $dst|$dst, $src2}",
1098 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1099 X86_COND_L, EFLAGS))]>,
1101 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1102 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1103 "cmovge\t{$src2, $dst|$dst, $src2}",
1104 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1105 X86_COND_GE, EFLAGS))]>,
1107 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1108 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1109 "cmovge\t{$src2, $dst|$dst, $src2}",
1110 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1111 X86_COND_GE, EFLAGS))]>,
1113 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1114 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1115 "cmovle\t{$src2, $dst|$dst, $src2}",
1116 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1117 X86_COND_LE, EFLAGS))]>,
1119 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1120 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1121 "cmovle\t{$src2, $dst|$dst, $src2}",
1122 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1123 X86_COND_LE, EFLAGS))]>,
1125 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1126 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1127 "cmovg\t{$src2, $dst|$dst, $src2}",
1128 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1129 X86_COND_G, EFLAGS))]>,
1131 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1132 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1133 "cmovg\t{$src2, $dst|$dst, $src2}",
1134 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1135 X86_COND_G, EFLAGS))]>,
1137 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1138 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1139 "cmovs\t{$src2, $dst|$dst, $src2}",
1140 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1141 X86_COND_S, EFLAGS))]>,
1143 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1144 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1145 "cmovs\t{$src2, $dst|$dst, $src2}",
1146 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1147 X86_COND_S, EFLAGS))]>,
1149 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1150 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1151 "cmovns\t{$src2, $dst|$dst, $src2}",
1152 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1153 X86_COND_NS, EFLAGS))]>,
1155 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1156 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1157 "cmovns\t{$src2, $dst|$dst, $src2}",
1158 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1159 X86_COND_NS, EFLAGS))]>,
1161 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1162 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1163 "cmovp\t{$src2, $dst|$dst, $src2}",
1164 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1165 X86_COND_P, EFLAGS))]>,
1167 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1168 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1169 "cmovp\t{$src2, $dst|$dst, $src2}",
1170 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1171 X86_COND_P, EFLAGS))]>,
1173 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1174 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1175 "cmovnp\t{$src2, $dst|$dst, $src2}",
1176 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1177 X86_COND_NP, EFLAGS))]>,
1179 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1180 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1181 "cmovnp\t{$src2, $dst|$dst, $src2}",
1182 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1183 X86_COND_NP, EFLAGS))]>,
1185 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1186 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1187 "cmovo\t{$src2, $dst|$dst, $src2}",
1188 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1189 X86_COND_O, EFLAGS))]>,
1191 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1192 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1193 "cmovo\t{$src2, $dst|$dst, $src2}",
1194 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1195 X86_COND_O, EFLAGS))]>,
1197 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1198 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1199 "cmovno\t{$src2, $dst|$dst, $src2}",
1200 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1201 X86_COND_NO, EFLAGS))]>,
1203 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1204 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1205 "cmovno\t{$src2, $dst|$dst, $src2}",
1206 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1207 X86_COND_NO, EFLAGS))]>,
1209 } // isCommutable = 1
1211 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1212 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1213 "cmovb\t{$src2, $dst|$dst, $src2}",
1214 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1215 X86_COND_B, EFLAGS))]>,
1217 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1218 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1219 "cmovb\t{$src2, $dst|$dst, $src2}",
1220 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1221 X86_COND_B, EFLAGS))]>,
1223 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1224 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1225 "cmovae\t{$src2, $dst|$dst, $src2}",
1226 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1227 X86_COND_AE, EFLAGS))]>,
1229 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1230 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1231 "cmovae\t{$src2, $dst|$dst, $src2}",
1232 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1233 X86_COND_AE, EFLAGS))]>,
1235 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1236 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1237 "cmove\t{$src2, $dst|$dst, $src2}",
1238 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1239 X86_COND_E, EFLAGS))]>,
1241 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1242 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1243 "cmove\t{$src2, $dst|$dst, $src2}",
1244 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1245 X86_COND_E, EFLAGS))]>,
1247 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1248 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1249 "cmovne\t{$src2, $dst|$dst, $src2}",
1250 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1251 X86_COND_NE, EFLAGS))]>,
1253 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1254 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1255 "cmovne\t{$src2, $dst|$dst, $src2}",
1256 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1257 X86_COND_NE, EFLAGS))]>,
1259 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1260 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1261 "cmovbe\t{$src2, $dst|$dst, $src2}",
1262 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1263 X86_COND_BE, EFLAGS))]>,
1265 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1266 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1267 "cmovbe\t{$src2, $dst|$dst, $src2}",
1268 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1269 X86_COND_BE, EFLAGS))]>,
1271 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1272 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1273 "cmova\t{$src2, $dst|$dst, $src2}",
1274 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1275 X86_COND_A, EFLAGS))]>,
1277 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1278 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1279 "cmova\t{$src2, $dst|$dst, $src2}",
1280 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1281 X86_COND_A, EFLAGS))]>,
1283 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1284 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1285 "cmovl\t{$src2, $dst|$dst, $src2}",
1286 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1287 X86_COND_L, EFLAGS))]>,
1289 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1290 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1291 "cmovl\t{$src2, $dst|$dst, $src2}",
1292 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1293 X86_COND_L, EFLAGS))]>,
1295 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1296 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1297 "cmovge\t{$src2, $dst|$dst, $src2}",
1298 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1299 X86_COND_GE, EFLAGS))]>,
1301 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1302 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1303 "cmovge\t{$src2, $dst|$dst, $src2}",
1304 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1305 X86_COND_GE, EFLAGS))]>,
1307 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1308 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1309 "cmovle\t{$src2, $dst|$dst, $src2}",
1310 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1311 X86_COND_LE, EFLAGS))]>,
1313 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1314 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1315 "cmovle\t{$src2, $dst|$dst, $src2}",
1316 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1317 X86_COND_LE, EFLAGS))]>,
1319 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1320 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1321 "cmovg\t{$src2, $dst|$dst, $src2}",
1322 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1323 X86_COND_G, EFLAGS))]>,
1325 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1326 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1327 "cmovg\t{$src2, $dst|$dst, $src2}",
1328 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1329 X86_COND_G, EFLAGS))]>,
1331 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1332 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1333 "cmovs\t{$src2, $dst|$dst, $src2}",
1334 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1335 X86_COND_S, EFLAGS))]>,
1337 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1338 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1339 "cmovs\t{$src2, $dst|$dst, $src2}",
1340 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1341 X86_COND_S, EFLAGS))]>,
1343 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1344 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1345 "cmovns\t{$src2, $dst|$dst, $src2}",
1346 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1347 X86_COND_NS, EFLAGS))]>,
1349 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1350 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1351 "cmovns\t{$src2, $dst|$dst, $src2}",
1352 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1353 X86_COND_NS, EFLAGS))]>,
1355 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1356 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1357 "cmovp\t{$src2, $dst|$dst, $src2}",
1358 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1359 X86_COND_P, EFLAGS))]>,
1361 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1362 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1363 "cmovp\t{$src2, $dst|$dst, $src2}",
1364 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1365 X86_COND_P, EFLAGS))]>,
1367 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1368 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1369 "cmovnp\t{$src2, $dst|$dst, $src2}",
1370 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1371 X86_COND_NP, EFLAGS))]>,
1373 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1374 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1375 "cmovnp\t{$src2, $dst|$dst, $src2}",
1376 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1377 X86_COND_NP, EFLAGS))]>,
1379 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1380 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1381 "cmovo\t{$src2, $dst|$dst, $src2}",
1382 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1383 X86_COND_O, EFLAGS))]>,
1385 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1386 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1387 "cmovo\t{$src2, $dst|$dst, $src2}",
1388 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1389 X86_COND_O, EFLAGS))]>,
1391 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1392 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1393 "cmovno\t{$src2, $dst|$dst, $src2}",
1394 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1395 X86_COND_NO, EFLAGS))]>,
1397 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1398 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1399 "cmovno\t{$src2, $dst|$dst, $src2}",
1400 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1401 X86_COND_NO, EFLAGS))]>,
1403 } // Uses = [EFLAGS]
1406 // unary instructions
1407 let CodeSize = 2 in {
1408 let Defs = [EFLAGS] in {
1409 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1410 [(set GR8:$dst, (ineg GR8:$src)),
1411 (implicit EFLAGS)]>;
1412 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1413 [(set GR16:$dst, (ineg GR16:$src)),
1414 (implicit EFLAGS)]>, OpSize;
1415 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1416 [(set GR32:$dst, (ineg GR32:$src)),
1417 (implicit EFLAGS)]>;
1418 let isTwoAddress = 0 in {
1419 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1420 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1421 (implicit EFLAGS)]>;
1422 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1423 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1424 (implicit EFLAGS)]>, OpSize;
1425 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1426 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1427 (implicit EFLAGS)]>;
1429 } // Defs = [EFLAGS]
1431 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1432 let AddedComplexity = 15 in {
1433 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1434 [(set GR8:$dst, (not GR8:$src))]>;
1435 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1436 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1437 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1438 [(set GR32:$dst, (not GR32:$src))]>;
1440 let isTwoAddress = 0 in {
1441 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1442 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1443 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1444 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1445 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1446 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1450 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1451 let Defs = [EFLAGS] in {
1453 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1454 [(set GR8:$dst, (add GR8:$src, 1)),
1455 (implicit EFLAGS)]>;
1456 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1457 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1458 [(set GR16:$dst, (add GR16:$src, 1)),
1459 (implicit EFLAGS)]>,
1460 OpSize, Requires<[In32BitMode]>;
1461 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1462 [(set GR32:$dst, (add GR32:$src, 1)),
1463 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1465 let isTwoAddress = 0, CodeSize = 2 in {
1466 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1467 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1468 (implicit EFLAGS)]>;
1469 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1470 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1471 (implicit EFLAGS)]>,
1472 OpSize, Requires<[In32BitMode]>;
1473 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1474 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1475 (implicit EFLAGS)]>,
1476 Requires<[In32BitMode]>;
1480 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1481 [(set GR8:$dst, (add GR8:$src, -1)),
1482 (implicit EFLAGS)]>;
1483 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1484 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1485 [(set GR16:$dst, (add GR16:$src, -1)),
1486 (implicit EFLAGS)]>,
1487 OpSize, Requires<[In32BitMode]>;
1488 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1489 [(set GR32:$dst, (add GR32:$src, -1)),
1490 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1493 let isTwoAddress = 0, CodeSize = 2 in {
1494 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1495 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1496 (implicit EFLAGS)]>;
1497 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1498 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1499 (implicit EFLAGS)]>,
1500 OpSize, Requires<[In32BitMode]>;
1501 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1502 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1503 (implicit EFLAGS)]>,
1504 Requires<[In32BitMode]>;
1506 } // Defs = [EFLAGS]
1508 // Logical operators...
1509 let Defs = [EFLAGS] in {
1510 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1511 def AND8rr : I<0x20, MRMDestReg,
1512 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1513 "and{b}\t{$src2, $dst|$dst, $src2}",
1514 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
1515 (implicit EFLAGS)]>;
1516 def AND16rr : I<0x21, MRMDestReg,
1517 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1518 "and{w}\t{$src2, $dst|$dst, $src2}",
1519 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
1520 (implicit EFLAGS)]>, OpSize;
1521 def AND32rr : I<0x21, MRMDestReg,
1522 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1523 "and{l}\t{$src2, $dst|$dst, $src2}",
1524 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
1525 (implicit EFLAGS)]>;
1528 def AND8rm : I<0x22, MRMSrcMem,
1529 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1530 "and{b}\t{$src2, $dst|$dst, $src2}",
1531 [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
1532 (implicit EFLAGS)]>;
1533 def AND16rm : I<0x23, MRMSrcMem,
1534 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1535 "and{w}\t{$src2, $dst|$dst, $src2}",
1536 [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
1537 (implicit EFLAGS)]>, OpSize;
1538 def AND32rm : I<0x23, MRMSrcMem,
1539 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1540 "and{l}\t{$src2, $dst|$dst, $src2}",
1541 [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
1542 (implicit EFLAGS)]>;
1544 def AND8ri : Ii8<0x80, MRM4r,
1545 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1546 "and{b}\t{$src2, $dst|$dst, $src2}",
1547 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
1548 (implicit EFLAGS)]>;
1549 def AND16ri : Ii16<0x81, MRM4r,
1550 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1551 "and{w}\t{$src2, $dst|$dst, $src2}",
1552 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
1553 (implicit EFLAGS)]>, OpSize;
1554 def AND32ri : Ii32<0x81, MRM4r,
1555 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1556 "and{l}\t{$src2, $dst|$dst, $src2}",
1557 [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
1558 (implicit EFLAGS)]>;
1559 def AND16ri8 : Ii8<0x83, MRM4r,
1560 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1561 "and{w}\t{$src2, $dst|$dst, $src2}",
1562 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
1563 (implicit EFLAGS)]>,
1565 def AND32ri8 : Ii8<0x83, MRM4r,
1566 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1567 "and{l}\t{$src2, $dst|$dst, $src2}",
1568 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
1569 (implicit EFLAGS)]>;
1571 let isTwoAddress = 0 in {
1572 def AND8mr : I<0x20, MRMDestMem,
1573 (outs), (ins i8mem :$dst, GR8 :$src),
1574 "and{b}\t{$src, $dst|$dst, $src}",
1575 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1576 (implicit EFLAGS)]>;
1577 def AND16mr : I<0x21, MRMDestMem,
1578 (outs), (ins i16mem:$dst, GR16:$src),
1579 "and{w}\t{$src, $dst|$dst, $src}",
1580 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1581 (implicit EFLAGS)]>,
1583 def AND32mr : I<0x21, MRMDestMem,
1584 (outs), (ins i32mem:$dst, GR32:$src),
1585 "and{l}\t{$src, $dst|$dst, $src}",
1586 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1587 (implicit EFLAGS)]>;
1588 def AND8mi : Ii8<0x80, MRM4m,
1589 (outs), (ins i8mem :$dst, i8imm :$src),
1590 "and{b}\t{$src, $dst|$dst, $src}",
1591 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1592 (implicit EFLAGS)]>;
1593 def AND16mi : Ii16<0x81, MRM4m,
1594 (outs), (ins i16mem:$dst, i16imm:$src),
1595 "and{w}\t{$src, $dst|$dst, $src}",
1596 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1597 (implicit EFLAGS)]>,
1599 def AND32mi : Ii32<0x81, MRM4m,
1600 (outs), (ins i32mem:$dst, i32imm:$src),
1601 "and{l}\t{$src, $dst|$dst, $src}",
1602 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1603 (implicit EFLAGS)]>;
1604 def AND16mi8 : Ii8<0x83, MRM4m,
1605 (outs), (ins i16mem:$dst, i16i8imm :$src),
1606 "and{w}\t{$src, $dst|$dst, $src}",
1607 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1608 (implicit EFLAGS)]>,
1610 def AND32mi8 : Ii8<0x83, MRM4m,
1611 (outs), (ins i32mem:$dst, i32i8imm :$src),
1612 "and{l}\t{$src, $dst|$dst, $src}",
1613 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1614 (implicit EFLAGS)]>;
1618 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1619 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1620 "or{b}\t{$src2, $dst|$dst, $src2}",
1621 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
1622 (implicit EFLAGS)]>;
1623 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1624 "or{w}\t{$src2, $dst|$dst, $src2}",
1625 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
1626 (implicit EFLAGS)]>, OpSize;
1627 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1628 "or{l}\t{$src2, $dst|$dst, $src2}",
1629 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
1630 (implicit EFLAGS)]>;
1632 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1633 "or{b}\t{$src2, $dst|$dst, $src2}",
1634 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
1635 (implicit EFLAGS)]>;
1636 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1637 "or{w}\t{$src2, $dst|$dst, $src2}",
1638 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
1639 (implicit EFLAGS)]>, OpSize;
1640 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1641 "or{l}\t{$src2, $dst|$dst, $src2}",
1642 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
1643 (implicit EFLAGS)]>;
1645 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1646 "or{b}\t{$src2, $dst|$dst, $src2}",
1647 [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
1648 (implicit EFLAGS)]>;
1649 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1650 "or{w}\t{$src2, $dst|$dst, $src2}",
1651 [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
1652 (implicit EFLAGS)]>, OpSize;
1653 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1654 "or{l}\t{$src2, $dst|$dst, $src2}",
1655 [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
1656 (implicit EFLAGS)]>;
1658 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1659 "or{w}\t{$src2, $dst|$dst, $src2}",
1660 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
1661 (implicit EFLAGS)]>, OpSize;
1662 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1663 "or{l}\t{$src2, $dst|$dst, $src2}",
1664 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
1665 (implicit EFLAGS)]>;
1666 let isTwoAddress = 0 in {
1667 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1668 "or{b}\t{$src, $dst|$dst, $src}",
1669 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1670 (implicit EFLAGS)]>;
1671 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1672 "or{w}\t{$src, $dst|$dst, $src}",
1673 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1674 (implicit EFLAGS)]>, OpSize;
1675 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1676 "or{l}\t{$src, $dst|$dst, $src}",
1677 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1678 (implicit EFLAGS)]>;
1679 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1680 "or{b}\t{$src, $dst|$dst, $src}",
1681 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1682 (implicit EFLAGS)]>;
1683 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1684 "or{w}\t{$src, $dst|$dst, $src}",
1685 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1686 (implicit EFLAGS)]>,
1688 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1689 "or{l}\t{$src, $dst|$dst, $src}",
1690 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1691 (implicit EFLAGS)]>;
1692 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1693 "or{w}\t{$src, $dst|$dst, $src}",
1694 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1695 (implicit EFLAGS)]>,
1697 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1698 "or{l}\t{$src, $dst|$dst, $src}",
1699 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1700 (implicit EFLAGS)]>;
1701 } // isTwoAddress = 0
1704 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1705 def XOR8rr : I<0x30, MRMDestReg,
1706 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1707 "xor{b}\t{$src2, $dst|$dst, $src2}",
1708 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
1709 (implicit EFLAGS)]>;
1710 def XOR16rr : I<0x31, MRMDestReg,
1711 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1712 "xor{w}\t{$src2, $dst|$dst, $src2}",
1713 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
1714 (implicit EFLAGS)]>, OpSize;
1715 def XOR32rr : I<0x31, MRMDestReg,
1716 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1717 "xor{l}\t{$src2, $dst|$dst, $src2}",
1718 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
1719 (implicit EFLAGS)]>;
1720 } // isCommutable = 1
1722 def XOR8rm : I<0x32, MRMSrcMem ,
1723 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1724 "xor{b}\t{$src2, $dst|$dst, $src2}",
1725 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
1726 (implicit EFLAGS)]>;
1727 def XOR16rm : I<0x33, MRMSrcMem ,
1728 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1729 "xor{w}\t{$src2, $dst|$dst, $src2}",
1730 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
1731 (implicit EFLAGS)]>,
1733 def XOR32rm : I<0x33, MRMSrcMem ,
1734 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1735 "xor{l}\t{$src2, $dst|$dst, $src2}",
1736 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
1737 (implicit EFLAGS)]>;
1739 def XOR8ri : Ii8<0x80, MRM6r,
1740 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1741 "xor{b}\t{$src2, $dst|$dst, $src2}",
1742 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
1743 (implicit EFLAGS)]>;
1744 def XOR16ri : Ii16<0x81, MRM6r,
1745 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1746 "xor{w}\t{$src2, $dst|$dst, $src2}",
1747 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
1748 (implicit EFLAGS)]>, OpSize;
1749 def XOR32ri : Ii32<0x81, MRM6r,
1750 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1751 "xor{l}\t{$src2, $dst|$dst, $src2}",
1752 [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
1753 (implicit EFLAGS)]>;
1754 def XOR16ri8 : Ii8<0x83, MRM6r,
1755 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1756 "xor{w}\t{$src2, $dst|$dst, $src2}",
1757 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
1758 (implicit EFLAGS)]>,
1760 def XOR32ri8 : Ii8<0x83, MRM6r,
1761 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1762 "xor{l}\t{$src2, $dst|$dst, $src2}",
1763 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
1764 (implicit EFLAGS)]>;
1766 let isTwoAddress = 0 in {
1767 def XOR8mr : I<0x30, MRMDestMem,
1768 (outs), (ins i8mem :$dst, GR8 :$src),
1769 "xor{b}\t{$src, $dst|$dst, $src}",
1770 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
1771 (implicit EFLAGS)]>;
1772 def XOR16mr : I<0x31, MRMDestMem,
1773 (outs), (ins i16mem:$dst, GR16:$src),
1774 "xor{w}\t{$src, $dst|$dst, $src}",
1775 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
1776 (implicit EFLAGS)]>,
1778 def XOR32mr : I<0x31, MRMDestMem,
1779 (outs), (ins i32mem:$dst, GR32:$src),
1780 "xor{l}\t{$src, $dst|$dst, $src}",
1781 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
1782 (implicit EFLAGS)]>;
1783 def XOR8mi : Ii8<0x80, MRM6m,
1784 (outs), (ins i8mem :$dst, i8imm :$src),
1785 "xor{b}\t{$src, $dst|$dst, $src}",
1786 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
1787 (implicit EFLAGS)]>;
1788 def XOR16mi : Ii16<0x81, MRM6m,
1789 (outs), (ins i16mem:$dst, i16imm:$src),
1790 "xor{w}\t{$src, $dst|$dst, $src}",
1791 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
1792 (implicit EFLAGS)]>,
1794 def XOR32mi : Ii32<0x81, MRM6m,
1795 (outs), (ins i32mem:$dst, i32imm:$src),
1796 "xor{l}\t{$src, $dst|$dst, $src}",
1797 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
1798 (implicit EFLAGS)]>;
1799 def XOR16mi8 : Ii8<0x83, MRM6m,
1800 (outs), (ins i16mem:$dst, i16i8imm :$src),
1801 "xor{w}\t{$src, $dst|$dst, $src}",
1802 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
1803 (implicit EFLAGS)]>,
1805 def XOR32mi8 : Ii8<0x83, MRM6m,
1806 (outs), (ins i32mem:$dst, i32i8imm :$src),
1807 "xor{l}\t{$src, $dst|$dst, $src}",
1808 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
1809 (implicit EFLAGS)]>;
1810 } // isTwoAddress = 0
1811 } // Defs = [EFLAGS]
1813 // Shift instructions
1814 let Defs = [EFLAGS] in {
1815 let Uses = [CL] in {
1816 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1817 "shl{b}\t{%cl, $dst|$dst, CL}",
1818 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1819 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1820 "shl{w}\t{%cl, $dst|$dst, CL}",
1821 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1822 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1823 "shl{l}\t{%cl, $dst|$dst, CL}",
1824 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1827 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1828 "shl{b}\t{$src2, $dst|$dst, $src2}",
1829 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1830 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1831 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1832 "shl{w}\t{$src2, $dst|$dst, $src2}",
1833 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1834 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1835 "shl{l}\t{$src2, $dst|$dst, $src2}",
1836 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1837 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1839 } // isConvertibleToThreeAddress = 1
1841 let isTwoAddress = 0 in {
1842 let Uses = [CL] in {
1843 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1844 "shl{b}\t{%cl, $dst|$dst, CL}",
1845 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1846 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1847 "shl{w}\t{%cl, $dst|$dst, CL}",
1848 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1849 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1850 "shl{l}\t{%cl, $dst|$dst, CL}",
1851 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1853 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1854 "shl{b}\t{$src, $dst|$dst, $src}",
1855 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1856 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1857 "shl{w}\t{$src, $dst|$dst, $src}",
1858 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1860 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1861 "shl{l}\t{$src, $dst|$dst, $src}",
1862 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1865 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1867 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1868 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1870 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1872 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1874 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1877 let Uses = [CL] in {
1878 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1879 "shr{b}\t{%cl, $dst|$dst, CL}",
1880 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1881 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1882 "shr{w}\t{%cl, $dst|$dst, CL}",
1883 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1884 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1885 "shr{l}\t{%cl, $dst|$dst, CL}",
1886 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1889 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1890 "shr{b}\t{$src2, $dst|$dst, $src2}",
1891 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1892 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1893 "shr{w}\t{$src2, $dst|$dst, $src2}",
1894 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1895 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1896 "shr{l}\t{$src2, $dst|$dst, $src2}",
1897 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1900 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1902 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1903 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1905 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1906 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1908 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1910 let isTwoAddress = 0 in {
1911 let Uses = [CL] in {
1912 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1913 "shr{b}\t{%cl, $dst|$dst, CL}",
1914 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1915 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1916 "shr{w}\t{%cl, $dst|$dst, CL}",
1917 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1919 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1920 "shr{l}\t{%cl, $dst|$dst, CL}",
1921 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1923 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1924 "shr{b}\t{$src, $dst|$dst, $src}",
1925 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1926 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1927 "shr{w}\t{$src, $dst|$dst, $src}",
1928 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1930 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1931 "shr{l}\t{$src, $dst|$dst, $src}",
1932 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1935 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1937 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1938 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1940 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1941 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1943 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1946 let Uses = [CL] in {
1947 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1948 "sar{b}\t{%cl, $dst|$dst, CL}",
1949 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1950 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1951 "sar{w}\t{%cl, $dst|$dst, CL}",
1952 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1953 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1954 "sar{l}\t{%cl, $dst|$dst, CL}",
1955 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1958 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1959 "sar{b}\t{$src2, $dst|$dst, $src2}",
1960 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1961 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1962 "sar{w}\t{$src2, $dst|$dst, $src2}",
1963 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1965 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1966 "sar{l}\t{$src2, $dst|$dst, $src2}",
1967 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1970 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1972 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1973 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1975 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1976 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1978 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1980 let isTwoAddress = 0 in {
1981 let Uses = [CL] in {
1982 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1983 "sar{b}\t{%cl, $dst|$dst, CL}",
1984 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
1985 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1986 "sar{w}\t{%cl, $dst|$dst, CL}",
1987 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1988 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1989 "sar{l}\t{%cl, $dst|$dst, CL}",
1990 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1992 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1993 "sar{b}\t{$src, $dst|$dst, $src}",
1994 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1995 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1996 "sar{w}\t{$src, $dst|$dst, $src}",
1997 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1999 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2000 "sar{l}\t{$src, $dst|$dst, $src}",
2001 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2004 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2006 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2007 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2009 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2011 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2013 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2016 // Rotate instructions
2017 // FIXME: provide shorter instructions when imm8 == 1
2018 let Uses = [CL] in {
2019 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
2020 "rol{b}\t{%cl, $dst|$dst, CL}",
2021 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
2022 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
2023 "rol{w}\t{%cl, $dst|$dst, CL}",
2024 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
2025 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
2026 "rol{l}\t{%cl, $dst|$dst, CL}",
2027 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2030 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2031 "rol{b}\t{$src2, $dst|$dst, $src2}",
2032 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2033 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2034 "rol{w}\t{$src2, $dst|$dst, $src2}",
2035 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2036 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2037 "rol{l}\t{$src2, $dst|$dst, $src2}",
2038 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2041 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2043 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2044 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2046 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2047 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2049 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2051 let isTwoAddress = 0 in {
2052 let Uses = [CL] in {
2053 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2054 "rol{b}\t{%cl, $dst|$dst, CL}",
2055 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2056 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2057 "rol{w}\t{%cl, $dst|$dst, CL}",
2058 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2059 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2060 "rol{l}\t{%cl, $dst|$dst, CL}",
2061 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2063 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2064 "rol{b}\t{$src, $dst|$dst, $src}",
2065 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2066 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2067 "rol{w}\t{$src, $dst|$dst, $src}",
2068 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2070 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2071 "rol{l}\t{$src, $dst|$dst, $src}",
2072 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2075 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2077 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2078 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2080 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2082 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2084 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2087 let Uses = [CL] in {
2088 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2089 "ror{b}\t{%cl, $dst|$dst, CL}",
2090 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2091 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2092 "ror{w}\t{%cl, $dst|$dst, CL}",
2093 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2094 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2095 "ror{l}\t{%cl, $dst|$dst, CL}",
2096 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2099 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2100 "ror{b}\t{$src2, $dst|$dst, $src2}",
2101 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2102 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2103 "ror{w}\t{$src2, $dst|$dst, $src2}",
2104 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2105 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2106 "ror{l}\t{$src2, $dst|$dst, $src2}",
2107 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2110 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2112 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2113 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2115 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2116 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2118 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2120 let isTwoAddress = 0 in {
2121 let Uses = [CL] in {
2122 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2123 "ror{b}\t{%cl, $dst|$dst, CL}",
2124 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2125 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2126 "ror{w}\t{%cl, $dst|$dst, CL}",
2127 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2128 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2129 "ror{l}\t{%cl, $dst|$dst, CL}",
2130 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2132 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2133 "ror{b}\t{$src, $dst|$dst, $src}",
2134 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2135 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2136 "ror{w}\t{$src, $dst|$dst, $src}",
2137 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2139 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2140 "ror{l}\t{$src, $dst|$dst, $src}",
2141 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2144 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2146 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2147 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2149 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2151 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2153 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2158 // Double shift instructions (generalizations of rotate)
2159 let Uses = [CL] in {
2160 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2161 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2162 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2163 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2164 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2165 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2166 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2167 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2168 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2170 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2171 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2172 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2176 let isCommutable = 1 in { // These instructions commute to each other.
2177 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2178 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2179 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2180 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2183 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2184 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2185 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2186 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2189 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2190 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2191 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2192 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2195 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2196 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2197 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2198 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2203 let isTwoAddress = 0 in {
2204 let Uses = [CL] in {
2205 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2206 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2207 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2209 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2210 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2211 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2214 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2215 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2216 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2217 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2218 (i8 imm:$src3)), addr:$dst)]>,
2220 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2221 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2222 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2223 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2224 (i8 imm:$src3)), addr:$dst)]>,
2227 let Uses = [CL] in {
2228 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2229 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2230 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2231 addr:$dst)]>, TB, OpSize;
2232 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2233 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2234 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2235 addr:$dst)]>, TB, OpSize;
2237 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2238 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2239 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2240 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2241 (i8 imm:$src3)), addr:$dst)]>,
2243 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2244 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2245 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2246 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2247 (i8 imm:$src3)), addr:$dst)]>,
2250 } // Defs = [EFLAGS]
2254 let Defs = [EFLAGS] in {
2255 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2256 // Register-Register Addition
2257 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2258 (ins GR8 :$src1, GR8 :$src2),
2259 "add{b}\t{$src2, $dst|$dst, $src2}",
2260 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
2261 (implicit EFLAGS)]>;
2263 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2264 // Register-Register Addition
2265 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2266 (ins GR16:$src1, GR16:$src2),
2267 "add{w}\t{$src2, $dst|$dst, $src2}",
2268 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2269 (implicit EFLAGS)]>, OpSize;
2270 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2271 (ins GR32:$src1, GR32:$src2),
2272 "add{l}\t{$src2, $dst|$dst, $src2}",
2273 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2274 (implicit EFLAGS)]>;
2275 } // end isConvertibleToThreeAddress
2276 } // end isCommutable
2278 // Register-Memory Addition
2279 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2280 (ins GR8 :$src1, i8mem :$src2),
2281 "add{b}\t{$src2, $dst|$dst, $src2}",
2282 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2283 (implicit EFLAGS)]>;
2284 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2285 (ins GR16:$src1, i16mem:$src2),
2286 "add{w}\t{$src2, $dst|$dst, $src2}",
2287 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2288 (implicit EFLAGS)]>, OpSize;
2289 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2290 (ins GR32:$src1, i32mem:$src2),
2291 "add{l}\t{$src2, $dst|$dst, $src2}",
2292 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2293 (implicit EFLAGS)]>;
2295 // Register-Integer Addition
2296 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2297 "add{b}\t{$src2, $dst|$dst, $src2}",
2298 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2299 (implicit EFLAGS)]>;
2301 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2302 // Register-Integer Addition
2303 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2304 (ins GR16:$src1, i16imm:$src2),
2305 "add{w}\t{$src2, $dst|$dst, $src2}",
2306 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2307 (implicit EFLAGS)]>, OpSize;
2308 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2309 (ins GR32:$src1, i32imm:$src2),
2310 "add{l}\t{$src2, $dst|$dst, $src2}",
2311 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2312 (implicit EFLAGS)]>;
2313 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2314 (ins GR16:$src1, i16i8imm:$src2),
2315 "add{w}\t{$src2, $dst|$dst, $src2}",
2316 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2317 (implicit EFLAGS)]>, OpSize;
2318 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2319 (ins GR32:$src1, i32i8imm:$src2),
2320 "add{l}\t{$src2, $dst|$dst, $src2}",
2321 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2322 (implicit EFLAGS)]>;
2325 let isTwoAddress = 0 in {
2326 // Memory-Register Addition
2327 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2328 "add{b}\t{$src2, $dst|$dst, $src2}",
2329 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2330 (implicit EFLAGS)]>;
2331 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2332 "add{w}\t{$src2, $dst|$dst, $src2}",
2333 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2334 (implicit EFLAGS)]>, OpSize;
2335 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2336 "add{l}\t{$src2, $dst|$dst, $src2}",
2337 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2338 (implicit EFLAGS)]>;
2339 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2340 "add{b}\t{$src2, $dst|$dst, $src2}",
2341 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2342 (implicit EFLAGS)]>;
2343 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2344 "add{w}\t{$src2, $dst|$dst, $src2}",
2345 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2346 (implicit EFLAGS)]>, OpSize;
2347 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2348 "add{l}\t{$src2, $dst|$dst, $src2}",
2349 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2350 (implicit EFLAGS)]>;
2351 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2352 "add{w}\t{$src2, $dst|$dst, $src2}",
2353 [(store (add (load addr:$dst), i16immSExt8:$src2),
2355 (implicit EFLAGS)]>, OpSize;
2356 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2357 "add{l}\t{$src2, $dst|$dst, $src2}",
2358 [(store (add (load addr:$dst), i32immSExt8:$src2),
2360 (implicit EFLAGS)]>;
2363 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2364 "add\t{$src, %al|%al, $src}", []>;
2365 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2366 "add\t{$src, %ax|%ax, $src}", []>, OpSize;
2367 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2368 "add\t{$src, %eax|%eax, $src}", []>;
2371 let Uses = [EFLAGS] in {
2372 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2373 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2374 "adc{b}\t{$src2, $dst|$dst, $src2}",
2375 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2376 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2377 (ins GR16:$src1, GR16:$src2),
2378 "adc{w}\t{$src2, $dst|$dst, $src2}",
2379 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2380 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2381 (ins GR32:$src1, GR32:$src2),
2382 "adc{l}\t{$src2, $dst|$dst, $src2}",
2383 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2385 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2386 (ins GR8:$src1, i8mem:$src2),
2387 "adc{b}\t{$src2, $dst|$dst, $src2}",
2388 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2389 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2390 (ins GR16:$src1, i16mem:$src2),
2391 "adc{w}\t{$src2, $dst|$dst, $src2}",
2392 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2394 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2395 (ins GR32:$src1, i32mem:$src2),
2396 "adc{l}\t{$src2, $dst|$dst, $src2}",
2397 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2398 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2399 "adc{b}\t{$src2, $dst|$dst, $src2}",
2400 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2401 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2402 (ins GR16:$src1, i16imm:$src2),
2403 "adc{w}\t{$src2, $dst|$dst, $src2}",
2404 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2405 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2406 (ins GR16:$src1, i16i8imm:$src2),
2407 "adc{w}\t{$src2, $dst|$dst, $src2}",
2408 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2410 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2411 (ins GR32:$src1, i32imm:$src2),
2412 "adc{l}\t{$src2, $dst|$dst, $src2}",
2413 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2414 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2415 (ins GR32:$src1, i32i8imm:$src2),
2416 "adc{l}\t{$src2, $dst|$dst, $src2}",
2417 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2419 let isTwoAddress = 0 in {
2420 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2421 "adc{b}\t{$src2, $dst|$dst, $src2}",
2422 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2423 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2424 "adc{w}\t{$src2, $dst|$dst, $src2}",
2425 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2427 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2428 "adc{l}\t{$src2, $dst|$dst, $src2}",
2429 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2430 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2431 "adc{b}\t{$src2, $dst|$dst, $src2}",
2432 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2433 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2434 "adc{w}\t{$src2, $dst|$dst, $src2}",
2435 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2437 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2438 "adc{w}\t{$src2, $dst|$dst, $src2}",
2439 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2441 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2442 "adc{l}\t{$src2, $dst|$dst, $src2}",
2443 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2444 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2445 "adc{l}\t{$src2, $dst|$dst, $src2}",
2446 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2448 } // Uses = [EFLAGS]
2450 // Register-Register Subtraction
2451 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2452 "sub{b}\t{$src2, $dst|$dst, $src2}",
2453 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2454 (implicit EFLAGS)]>;
2455 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2456 "sub{w}\t{$src2, $dst|$dst, $src2}",
2457 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2458 (implicit EFLAGS)]>, OpSize;
2459 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2460 "sub{l}\t{$src2, $dst|$dst, $src2}",
2461 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2462 (implicit EFLAGS)]>;
2464 // Register-Memory Subtraction
2465 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2466 (ins GR8 :$src1, i8mem :$src2),
2467 "sub{b}\t{$src2, $dst|$dst, $src2}",
2468 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2469 (implicit EFLAGS)]>;
2470 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2471 (ins GR16:$src1, i16mem:$src2),
2472 "sub{w}\t{$src2, $dst|$dst, $src2}",
2473 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2474 (implicit EFLAGS)]>, OpSize;
2475 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2476 (ins GR32:$src1, i32mem:$src2),
2477 "sub{l}\t{$src2, $dst|$dst, $src2}",
2478 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2479 (implicit EFLAGS)]>;
2481 // Register-Integer Subtraction
2482 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2483 (ins GR8:$src1, i8imm:$src2),
2484 "sub{b}\t{$src2, $dst|$dst, $src2}",
2485 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2486 (implicit EFLAGS)]>;
2487 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2488 (ins GR16:$src1, i16imm:$src2),
2489 "sub{w}\t{$src2, $dst|$dst, $src2}",
2490 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2491 (implicit EFLAGS)]>, OpSize;
2492 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2493 (ins GR32:$src1, i32imm:$src2),
2494 "sub{l}\t{$src2, $dst|$dst, $src2}",
2495 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2496 (implicit EFLAGS)]>;
2497 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2498 (ins GR16:$src1, i16i8imm:$src2),
2499 "sub{w}\t{$src2, $dst|$dst, $src2}",
2500 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2501 (implicit EFLAGS)]>, OpSize;
2502 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2503 (ins GR32:$src1, i32i8imm:$src2),
2504 "sub{l}\t{$src2, $dst|$dst, $src2}",
2505 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2506 (implicit EFLAGS)]>;
2508 let isTwoAddress = 0 in {
2509 // Memory-Register Subtraction
2510 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2511 "sub{b}\t{$src2, $dst|$dst, $src2}",
2512 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2513 (implicit EFLAGS)]>;
2514 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2515 "sub{w}\t{$src2, $dst|$dst, $src2}",
2516 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2517 (implicit EFLAGS)]>, OpSize;
2518 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2519 "sub{l}\t{$src2, $dst|$dst, $src2}",
2520 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2521 (implicit EFLAGS)]>;
2523 // Memory-Integer Subtraction
2524 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2525 "sub{b}\t{$src2, $dst|$dst, $src2}",
2526 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2527 (implicit EFLAGS)]>;
2528 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2529 "sub{w}\t{$src2, $dst|$dst, $src2}",
2530 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2531 (implicit EFLAGS)]>, OpSize;
2532 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2533 "sub{l}\t{$src2, $dst|$dst, $src2}",
2534 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2535 (implicit EFLAGS)]>;
2536 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2537 "sub{w}\t{$src2, $dst|$dst, $src2}",
2538 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2540 (implicit EFLAGS)]>, OpSize;
2541 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2542 "sub{l}\t{$src2, $dst|$dst, $src2}",
2543 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2545 (implicit EFLAGS)]>;
2548 let Uses = [EFLAGS] in {
2549 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
2550 (ins GR8:$src1, GR8:$src2),
2551 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2552 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
2553 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
2554 (ins GR16:$src1, GR16:$src2),
2555 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2556 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
2557 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
2558 (ins GR32:$src1, GR32:$src2),
2559 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2560 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2562 let isTwoAddress = 0 in {
2563 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2564 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2565 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
2566 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2567 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2568 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
2570 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2571 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2572 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2573 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2574 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2575 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2576 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
2577 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2578 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2580 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2581 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2582 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2584 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2585 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2586 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2587 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2588 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2589 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2591 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
2592 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2593 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
2594 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
2595 (ins GR16:$src1, i16mem:$src2),
2596 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2597 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
2599 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
2600 (ins GR32:$src1, i32mem:$src2),
2601 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2602 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2603 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2604 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2605 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
2606 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
2607 (ins GR16:$src1, i16imm:$src2),
2608 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2609 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
2610 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
2611 (ins GR16:$src1, i16i8imm:$src2),
2612 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2613 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
2615 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
2616 (ins GR32:$src1, i32imm:$src2),
2617 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2618 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2619 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
2620 (ins GR32:$src1, i32i8imm:$src2),
2621 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2622 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2623 } // Uses = [EFLAGS]
2624 } // Defs = [EFLAGS]
2626 let Defs = [EFLAGS] in {
2627 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2628 // Register-Register Signed Integer Multiply
2629 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2630 "imul{w}\t{$src2, $dst|$dst, $src2}",
2631 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
2632 (implicit EFLAGS)]>, TB, OpSize;
2633 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2634 "imul{l}\t{$src2, $dst|$dst, $src2}",
2635 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
2636 (implicit EFLAGS)]>, TB;
2639 // Register-Memory Signed Integer Multiply
2640 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
2641 (ins GR16:$src1, i16mem:$src2),
2642 "imul{w}\t{$src2, $dst|$dst, $src2}",
2643 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
2644 (implicit EFLAGS)]>, TB, OpSize;
2645 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2646 "imul{l}\t{$src2, $dst|$dst, $src2}",
2647 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
2648 (implicit EFLAGS)]>, TB;
2649 } // Defs = [EFLAGS]
2650 } // end Two Address instructions
2652 // Suprisingly enough, these are not two address instructions!
2653 let Defs = [EFLAGS] in {
2654 // Register-Integer Signed Integer Multiply
2655 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2656 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2657 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2658 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
2659 (implicit EFLAGS)]>, OpSize;
2660 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2661 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2662 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2663 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
2664 (implicit EFLAGS)]>;
2665 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2666 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2667 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2668 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
2669 (implicit EFLAGS)]>, OpSize;
2670 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2671 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2672 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2673 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
2674 (implicit EFLAGS)]>;
2676 // Memory-Integer Signed Integer Multiply
2677 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2678 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2679 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2680 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
2681 (implicit EFLAGS)]>, OpSize;
2682 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2683 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2684 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2685 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
2686 (implicit EFLAGS)]>;
2687 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2688 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2689 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2690 [(set GR16:$dst, (mul (load addr:$src1),
2691 i16immSExt8:$src2)),
2692 (implicit EFLAGS)]>, OpSize;
2693 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2694 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2695 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2696 [(set GR32:$dst, (mul (load addr:$src1),
2697 i32immSExt8:$src2)),
2698 (implicit EFLAGS)]>;
2699 } // Defs = [EFLAGS]
2701 //===----------------------------------------------------------------------===//
2702 // Test instructions are just like AND, except they don't generate a result.
2704 let Defs = [EFLAGS] in {
2705 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2706 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2707 "test{b}\t{$src2, $src1|$src1, $src2}",
2708 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
2709 (implicit EFLAGS)]>;
2710 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2711 "test{w}\t{$src2, $src1|$src1, $src2}",
2712 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
2713 (implicit EFLAGS)]>,
2715 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2716 "test{l}\t{$src2, $src1|$src1, $src2}",
2717 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
2718 (implicit EFLAGS)]>;
2721 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2722 "test{b}\t{$src2, $src1|$src1, $src2}",
2723 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2724 (implicit EFLAGS)]>;
2725 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2726 "test{w}\t{$src2, $src1|$src1, $src2}",
2727 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2728 (implicit EFLAGS)]>, OpSize;
2729 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2730 "test{l}\t{$src2, $src1|$src1, $src2}",
2731 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2732 (implicit EFLAGS)]>;
2734 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2735 (outs), (ins GR8:$src1, i8imm:$src2),
2736 "test{b}\t{$src2, $src1|$src1, $src2}",
2737 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
2738 (implicit EFLAGS)]>;
2739 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2740 (outs), (ins GR16:$src1, i16imm:$src2),
2741 "test{w}\t{$src2, $src1|$src1, $src2}",
2742 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
2743 (implicit EFLAGS)]>, OpSize;
2744 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2745 (outs), (ins GR32:$src1, i32imm:$src2),
2746 "test{l}\t{$src2, $src1|$src1, $src2}",
2747 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
2748 (implicit EFLAGS)]>;
2750 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2751 (outs), (ins i8mem:$src1, i8imm:$src2),
2752 "test{b}\t{$src2, $src1|$src1, $src2}",
2753 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2754 (implicit EFLAGS)]>;
2755 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2756 (outs), (ins i16mem:$src1, i16imm:$src2),
2757 "test{w}\t{$src2, $src1|$src1, $src2}",
2758 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2759 (implicit EFLAGS)]>, OpSize;
2760 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2761 (outs), (ins i32mem:$src1, i32imm:$src2),
2762 "test{l}\t{$src2, $src1|$src1, $src2}",
2763 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2764 (implicit EFLAGS)]>;
2765 } // Defs = [EFLAGS]
2768 // Condition code ops, incl. set if equal/not equal/...
2769 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2770 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2771 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2772 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2774 let Uses = [EFLAGS] in {
2775 def SETEr : I<0x94, MRM0r,
2776 (outs GR8 :$dst), (ins),
2778 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2780 def SETEm : I<0x94, MRM0m,
2781 (outs), (ins i8mem:$dst),
2783 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2786 def SETNEr : I<0x95, MRM0r,
2787 (outs GR8 :$dst), (ins),
2789 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2791 def SETNEm : I<0x95, MRM0m,
2792 (outs), (ins i8mem:$dst),
2794 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2797 def SETLr : I<0x9C, MRM0r,
2798 (outs GR8 :$dst), (ins),
2800 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2801 TB; // GR8 = < signed
2802 def SETLm : I<0x9C, MRM0m,
2803 (outs), (ins i8mem:$dst),
2805 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2806 TB; // [mem8] = < signed
2808 def SETGEr : I<0x9D, MRM0r,
2809 (outs GR8 :$dst), (ins),
2811 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2812 TB; // GR8 = >= signed
2813 def SETGEm : I<0x9D, MRM0m,
2814 (outs), (ins i8mem:$dst),
2816 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2817 TB; // [mem8] = >= signed
2819 def SETLEr : I<0x9E, MRM0r,
2820 (outs GR8 :$dst), (ins),
2822 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2823 TB; // GR8 = <= signed
2824 def SETLEm : I<0x9E, MRM0m,
2825 (outs), (ins i8mem:$dst),
2827 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2828 TB; // [mem8] = <= signed
2830 def SETGr : I<0x9F, MRM0r,
2831 (outs GR8 :$dst), (ins),
2833 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2834 TB; // GR8 = > signed
2835 def SETGm : I<0x9F, MRM0m,
2836 (outs), (ins i8mem:$dst),
2838 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2839 TB; // [mem8] = > signed
2841 def SETBr : I<0x92, MRM0r,
2842 (outs GR8 :$dst), (ins),
2844 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2845 TB; // GR8 = < unsign
2846 def SETBm : I<0x92, MRM0m,
2847 (outs), (ins i8mem:$dst),
2849 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
2850 TB; // [mem8] = < unsign
2852 def SETAEr : I<0x93, MRM0r,
2853 (outs GR8 :$dst), (ins),
2855 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
2856 TB; // GR8 = >= unsign
2857 def SETAEm : I<0x93, MRM0m,
2858 (outs), (ins i8mem:$dst),
2860 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
2861 TB; // [mem8] = >= unsign
2863 def SETBEr : I<0x96, MRM0r,
2864 (outs GR8 :$dst), (ins),
2866 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
2867 TB; // GR8 = <= unsign
2868 def SETBEm : I<0x96, MRM0m,
2869 (outs), (ins i8mem:$dst),
2871 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
2872 TB; // [mem8] = <= unsign
2874 def SETAr : I<0x97, MRM0r,
2875 (outs GR8 :$dst), (ins),
2877 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
2878 TB; // GR8 = > signed
2879 def SETAm : I<0x97, MRM0m,
2880 (outs), (ins i8mem:$dst),
2882 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
2883 TB; // [mem8] = > signed
2885 def SETSr : I<0x98, MRM0r,
2886 (outs GR8 :$dst), (ins),
2888 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
2889 TB; // GR8 = <sign bit>
2890 def SETSm : I<0x98, MRM0m,
2891 (outs), (ins i8mem:$dst),
2893 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
2894 TB; // [mem8] = <sign bit>
2895 def SETNSr : I<0x99, MRM0r,
2896 (outs GR8 :$dst), (ins),
2898 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
2899 TB; // GR8 = !<sign bit>
2900 def SETNSm : I<0x99, MRM0m,
2901 (outs), (ins i8mem:$dst),
2903 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
2904 TB; // [mem8] = !<sign bit>
2906 def SETPr : I<0x9A, MRM0r,
2907 (outs GR8 :$dst), (ins),
2909 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
2911 def SETPm : I<0x9A, MRM0m,
2912 (outs), (ins i8mem:$dst),
2914 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
2915 TB; // [mem8] = parity
2916 def SETNPr : I<0x9B, MRM0r,
2917 (outs GR8 :$dst), (ins),
2919 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
2920 TB; // GR8 = not parity
2921 def SETNPm : I<0x9B, MRM0m,
2922 (outs), (ins i8mem:$dst),
2924 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
2925 TB; // [mem8] = not parity
2927 def SETOr : I<0x90, MRM0r,
2928 (outs GR8 :$dst), (ins),
2930 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
2931 TB; // GR8 = overflow
2932 def SETOm : I<0x90, MRM0m,
2933 (outs), (ins i8mem:$dst),
2935 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
2936 TB; // [mem8] = overflow
2937 def SETNOr : I<0x91, MRM0r,
2938 (outs GR8 :$dst), (ins),
2940 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
2941 TB; // GR8 = not overflow
2942 def SETNOm : I<0x91, MRM0m,
2943 (outs), (ins i8mem:$dst),
2945 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
2946 TB; // [mem8] = not overflow
2947 } // Uses = [EFLAGS]
2950 // Integer comparisons
2951 let Defs = [EFLAGS] in {
2952 def CMP8rr : I<0x38, MRMDestReg,
2953 (outs), (ins GR8 :$src1, GR8 :$src2),
2954 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2955 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2956 def CMP16rr : I<0x39, MRMDestReg,
2957 (outs), (ins GR16:$src1, GR16:$src2),
2958 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2959 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
2960 def CMP32rr : I<0x39, MRMDestReg,
2961 (outs), (ins GR32:$src1, GR32:$src2),
2962 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2963 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
2964 def CMP8mr : I<0x38, MRMDestMem,
2965 (outs), (ins i8mem :$src1, GR8 :$src2),
2966 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2967 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
2968 (implicit EFLAGS)]>;
2969 def CMP16mr : I<0x39, MRMDestMem,
2970 (outs), (ins i16mem:$src1, GR16:$src2),
2971 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2972 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
2973 (implicit EFLAGS)]>, OpSize;
2974 def CMP32mr : I<0x39, MRMDestMem,
2975 (outs), (ins i32mem:$src1, GR32:$src2),
2976 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2977 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
2978 (implicit EFLAGS)]>;
2979 def CMP8rm : I<0x3A, MRMSrcMem,
2980 (outs), (ins GR8 :$src1, i8mem :$src2),
2981 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2982 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
2983 (implicit EFLAGS)]>;
2984 def CMP16rm : I<0x3B, MRMSrcMem,
2985 (outs), (ins GR16:$src1, i16mem:$src2),
2986 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2987 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
2988 (implicit EFLAGS)]>, OpSize;
2989 def CMP32rm : I<0x3B, MRMSrcMem,
2990 (outs), (ins GR32:$src1, i32mem:$src2),
2991 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2992 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
2993 (implicit EFLAGS)]>;
2994 def CMP8ri : Ii8<0x80, MRM7r,
2995 (outs), (ins GR8:$src1, i8imm:$src2),
2996 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2997 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
2998 def CMP16ri : Ii16<0x81, MRM7r,
2999 (outs), (ins GR16:$src1, i16imm:$src2),
3000 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3001 [(X86cmp GR16:$src1, imm:$src2),
3002 (implicit EFLAGS)]>, OpSize;
3003 def CMP32ri : Ii32<0x81, MRM7r,
3004 (outs), (ins GR32:$src1, i32imm:$src2),
3005 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3006 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
3007 def CMP8mi : Ii8 <0x80, MRM7m,
3008 (outs), (ins i8mem :$src1, i8imm :$src2),
3009 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3010 [(X86cmp (loadi8 addr:$src1), imm:$src2),
3011 (implicit EFLAGS)]>;
3012 def CMP16mi : Ii16<0x81, MRM7m,
3013 (outs), (ins i16mem:$src1, i16imm:$src2),
3014 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3015 [(X86cmp (loadi16 addr:$src1), imm:$src2),
3016 (implicit EFLAGS)]>, OpSize;
3017 def CMP32mi : Ii32<0x81, MRM7m,
3018 (outs), (ins i32mem:$src1, i32imm:$src2),
3019 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3020 [(X86cmp (loadi32 addr:$src1), imm:$src2),
3021 (implicit EFLAGS)]>;
3022 def CMP16ri8 : Ii8<0x83, MRM7r,
3023 (outs), (ins GR16:$src1, i16i8imm:$src2),
3024 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3025 [(X86cmp GR16:$src1, i16immSExt8:$src2),
3026 (implicit EFLAGS)]>, OpSize;
3027 def CMP16mi8 : Ii8<0x83, MRM7m,
3028 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3029 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3030 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
3031 (implicit EFLAGS)]>, OpSize;
3032 def CMP32mi8 : Ii8<0x83, MRM7m,
3033 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3034 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3035 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
3036 (implicit EFLAGS)]>;
3037 def CMP32ri8 : Ii8<0x83, MRM7r,
3038 (outs), (ins GR32:$src1, i32i8imm:$src2),
3039 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3040 [(X86cmp GR32:$src1, i32immSExt8:$src2),
3041 (implicit EFLAGS)]>;
3042 } // Defs = [EFLAGS]
3045 // TODO: BTC, BTR, and BTS
3046 let Defs = [EFLAGS] in {
3047 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3048 "bt{w}\t{$src2, $src1|$src1, $src2}",
3049 [(X86bt GR16:$src1, GR16:$src2),
3050 (implicit EFLAGS)]>, OpSize, TB;
3051 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3052 "bt{l}\t{$src2, $src1|$src1, $src2}",
3053 [(X86bt GR32:$src1, GR32:$src2),
3054 (implicit EFLAGS)]>, TB;
3056 // Unlike with the register+register form, the memory+register form of the
3057 // bt instruction does not ignore the high bits of the index. From ISel's
3058 // perspective, this is pretty bizarre. Disable these instructions for now.
3059 //def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3060 // "bt{w}\t{$src2, $src1|$src1, $src2}",
3061 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3062 // (implicit EFLAGS)]>, OpSize, TB, Requires<[FastBTMem]>;
3063 //def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3064 // "bt{l}\t{$src2, $src1|$src1, $src2}",
3065 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3066 // (implicit EFLAGS)]>, TB, Requires<[FastBTMem]>;
3068 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3069 "bt{w}\t{$src2, $src1|$src1, $src2}",
3070 [(X86bt GR16:$src1, i16immSExt8:$src2),
3071 (implicit EFLAGS)]>, OpSize, TB;
3072 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3073 "bt{l}\t{$src2, $src1|$src1, $src2}",
3074 [(X86bt GR32:$src1, i32immSExt8:$src2),
3075 (implicit EFLAGS)]>, TB;
3076 // Note that these instructions don't need FastBTMem because that
3077 // only applies when the other operand is in a register. When it's
3078 // an immediate, bt is still fast.
3079 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3080 "bt{w}\t{$src2, $src1|$src1, $src2}",
3081 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
3082 (implicit EFLAGS)]>, OpSize, TB;
3083 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3084 "bt{l}\t{$src2, $src1|$src1, $src2}",
3085 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
3086 (implicit EFLAGS)]>, TB;
3087 } // Defs = [EFLAGS]
3089 // Sign/Zero extenders
3090 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3091 // of the register here. This has a smaller encoding and avoids a
3092 // partial-register update.
3093 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3094 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3095 [(set GR16:$dst, (sext GR8:$src))]>, TB;
3096 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3097 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3098 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3099 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3100 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3101 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3102 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3103 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3104 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3105 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3106 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3107 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3108 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3109 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3110 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3112 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3113 // of the register here. This has a smaller encoding and avoids a
3114 // partial-register update.
3115 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3116 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3117 [(set GR16:$dst, (zext GR8:$src))]>, TB;
3118 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3119 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3120 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3121 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3122 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3123 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3124 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3125 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3126 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3127 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3128 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3129 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3130 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3131 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3132 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3134 // These are the same as the regular regular MOVZX32rr8 and MOVZX32rm8
3135 // except that they use GR32_NOREX for the output operand register class
3136 // instead of GR32. This allows them to operate on h registers on x86-64.
3137 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3138 (outs GR32_NOREX:$dst), (ins GR8:$src),
3139 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3142 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3143 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3144 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3147 let neverHasSideEffects = 1 in {
3148 let Defs = [AX], Uses = [AL] in
3149 def CBW : I<0x98, RawFrm, (outs), (ins),
3150 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3151 let Defs = [EAX], Uses = [AX] in
3152 def CWDE : I<0x98, RawFrm, (outs), (ins),
3153 "{cwtl|cwde}", []>; // EAX = signext(AX)
3155 let Defs = [AX,DX], Uses = [AX] in
3156 def CWD : I<0x99, RawFrm, (outs), (ins),
3157 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3158 let Defs = [EAX,EDX], Uses = [EAX] in
3159 def CDQ : I<0x99, RawFrm, (outs), (ins),
3160 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3163 //===----------------------------------------------------------------------===//
3164 // Alias Instructions
3165 //===----------------------------------------------------------------------===//
3167 // Alias instructions that map movr0 to xor.
3168 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3169 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3170 isCodeGenOnly = 1 in {
3171 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
3172 "xor{b}\t$dst, $dst",
3173 [(set GR8:$dst, 0)]>;
3174 // Use xorl instead of xorw since we don't care about the high 16 bits,
3175 // it's smaller, and it avoids a partial-register update.
3176 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3177 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
3178 [(set GR16:$dst, 0)]>;
3179 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
3180 "xor{l}\t$dst, $dst",
3181 [(set GR32:$dst, 0)]>;
3184 //===----------------------------------------------------------------------===//
3185 // Thread Local Storage Instructions
3188 // All calls clobber the non-callee saved registers. ESP is marked as
3189 // a use to prevent stack-pointer assignments that appear immediately
3190 // before calls from potentially appearing dead.
3191 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3192 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3193 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3194 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3196 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3197 "leal\t$sym, %eax; "
3198 "call\t___tls_get_addr@PLT",
3199 [(X86tlsaddr tls32addr:$sym)]>,
3200 Requires<[In32BitMode]>;
3202 let AddedComplexity = 5 in
3203 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3204 "movl\t%gs:$src, $dst",
3205 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3207 let AddedComplexity = 5 in
3208 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3209 "movl\t%fs:$src, $dst",
3210 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3212 //===----------------------------------------------------------------------===//
3213 // DWARF Pseudo Instructions
3216 def DWARF_LOC : I<0, Pseudo, (outs),
3217 (ins i32imm:$line, i32imm:$col, i32imm:$file),
3218 ".loc\t$file $line $col",
3219 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
3222 //===----------------------------------------------------------------------===//
3223 // EH Pseudo Instructions
3225 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3227 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3228 "ret\t#eh_return, addr: $addr",
3229 [(X86ehret GR32:$addr)]>;
3233 //===----------------------------------------------------------------------===//
3237 // Atomic swap. These are just normal xchg instructions. But since a memory
3238 // operand is referenced, the atomicity is ensured.
3239 let Constraints = "$val = $dst" in {
3240 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3241 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3242 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3243 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3244 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3245 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3247 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3248 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3249 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3252 // Atomic compare and swap.
3253 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3254 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3256 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3257 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3259 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3260 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
3263 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3266 let Defs = [AX, EFLAGS], Uses = [AX] in {
3267 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3269 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3270 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3272 let Defs = [AL, EFLAGS], Uses = [AL] in {
3273 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3275 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3276 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3279 // Atomic exchange and add
3280 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3281 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3283 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3284 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3286 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3288 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3289 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3291 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3293 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3294 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3298 // Optimized codegen when the non-memory output is not used.
3299 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3300 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3302 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3303 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3305 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3306 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3308 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3309 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3311 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3312 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3314 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3315 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3317 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3318 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3320 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3321 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3323 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3325 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3327 "inc{b}\t$dst", []>, LOCK;
3328 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3330 "inc{w}\t$dst", []>, OpSize, LOCK;
3331 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3333 "inc{l}\t$dst", []>, LOCK;
3335 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3337 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3338 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3340 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3341 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3343 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3344 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3346 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3347 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3349 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3350 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3352 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3353 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3355 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3356 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3358 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3360 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3362 "dec{b}\t$dst", []>, LOCK;
3363 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3365 "dec{w}\t$dst", []>, OpSize, LOCK;
3366 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3368 "dec{l}\t$dst", []>, LOCK;
3370 // Atomic exchange, and, or, xor
3371 let Constraints = "$val = $dst", Defs = [EFLAGS],
3372 usesCustomDAGSchedInserter = 1 in {
3373 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3374 "#ATOMAND32 PSEUDO!",
3375 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3376 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3377 "#ATOMOR32 PSEUDO!",
3378 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
3379 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3380 "#ATOMXOR32 PSEUDO!",
3381 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
3382 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3383 "#ATOMNAND32 PSEUDO!",
3384 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
3385 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3386 "#ATOMMIN32 PSEUDO!",
3387 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
3388 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3389 "#ATOMMAX32 PSEUDO!",
3390 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
3391 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3392 "#ATOMUMIN32 PSEUDO!",
3393 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
3394 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3395 "#ATOMUMAX32 PSEUDO!",
3396 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
3398 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3399 "#ATOMAND16 PSEUDO!",
3400 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
3401 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3402 "#ATOMOR16 PSEUDO!",
3403 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
3404 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3405 "#ATOMXOR16 PSEUDO!",
3406 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
3407 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3408 "#ATOMNAND16 PSEUDO!",
3409 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
3410 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3411 "#ATOMMIN16 PSEUDO!",
3412 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
3413 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3414 "#ATOMMAX16 PSEUDO!",
3415 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
3416 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3417 "#ATOMUMIN16 PSEUDO!",
3418 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
3419 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3420 "#ATOMUMAX16 PSEUDO!",
3421 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
3423 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3424 "#ATOMAND8 PSEUDO!",
3425 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
3426 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3428 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
3429 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3430 "#ATOMXOR8 PSEUDO!",
3431 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
3432 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3433 "#ATOMNAND8 PSEUDO!",
3434 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
3437 let Constraints = "$val1 = $dst1, $val2 = $dst2",
3438 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
3439 Uses = [EAX, EBX, ECX, EDX],
3440 mayLoad = 1, mayStore = 1,
3441 usesCustomDAGSchedInserter = 1 in {
3442 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3443 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3444 "#ATOMAND6432 PSEUDO!", []>;
3445 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3446 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3447 "#ATOMOR6432 PSEUDO!", []>;
3448 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3449 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3450 "#ATOMXOR6432 PSEUDO!", []>;
3451 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3452 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3453 "#ATOMNAND6432 PSEUDO!", []>;
3454 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3455 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3456 "#ATOMADD6432 PSEUDO!", []>;
3457 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3458 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3459 "#ATOMSUB6432 PSEUDO!", []>;
3460 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3461 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3462 "#ATOMSWAP6432 PSEUDO!", []>;
3465 //===----------------------------------------------------------------------===//
3466 // Non-Instruction Patterns
3467 //===----------------------------------------------------------------------===//
3469 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
3470 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
3471 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
3472 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
3473 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
3474 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
3476 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
3477 (ADD32ri GR32:$src1, tconstpool:$src2)>;
3478 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
3479 (ADD32ri GR32:$src1, tjumptable:$src2)>;
3480 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
3481 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
3482 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
3483 (ADD32ri GR32:$src1, texternalsym:$src2)>;
3485 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
3486 (MOV32mi addr:$dst, tglobaladdr:$src)>;
3487 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
3488 (MOV32mi addr:$dst, texternalsym:$src)>;
3492 def : Pat<(X86tcret GR32:$dst, imm:$off),
3493 (TCRETURNri GR32:$dst, imm:$off)>;
3495 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
3496 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3498 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
3499 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3501 // Normal calls, with various flavors of addresses.
3502 def : Pat<(X86call (i32 tglobaladdr:$dst)),
3503 (CALLpcrel32 tglobaladdr:$dst)>;
3504 def : Pat<(X86call (i32 texternalsym:$dst)),
3505 (CALLpcrel32 texternalsym:$dst)>;
3506 def : Pat<(X86call (i32 imm:$dst)),
3507 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
3509 // X86 specific add which produces a flag.
3510 def : Pat<(addc GR32:$src1, GR32:$src2),
3511 (ADD32rr GR32:$src1, GR32:$src2)>;
3512 def : Pat<(addc GR32:$src1, (load addr:$src2)),
3513 (ADD32rm GR32:$src1, addr:$src2)>;
3514 def : Pat<(addc GR32:$src1, imm:$src2),
3515 (ADD32ri GR32:$src1, imm:$src2)>;
3516 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
3517 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3519 def : Pat<(subc GR32:$src1, GR32:$src2),
3520 (SUB32rr GR32:$src1, GR32:$src2)>;
3521 def : Pat<(subc GR32:$src1, (load addr:$src2)),
3522 (SUB32rm GR32:$src1, addr:$src2)>;
3523 def : Pat<(subc GR32:$src1, imm:$src2),
3524 (SUB32ri GR32:$src1, imm:$src2)>;
3525 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
3526 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3530 // TEST R,R is smaller than CMP R,0
3531 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
3532 (TEST8rr GR8:$src1, GR8:$src1)>;
3533 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
3534 (TEST16rr GR16:$src1, GR16:$src1)>;
3535 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
3536 (TEST32rr GR32:$src1, GR32:$src1)>;
3538 // Conditional moves with folded loads with operands swapped and conditions
3540 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
3541 (CMOVAE16rm GR16:$src2, addr:$src1)>;
3542 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
3543 (CMOVAE32rm GR32:$src2, addr:$src1)>;
3544 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
3545 (CMOVB16rm GR16:$src2, addr:$src1)>;
3546 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
3547 (CMOVB32rm GR32:$src2, addr:$src1)>;
3548 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
3549 (CMOVNE16rm GR16:$src2, addr:$src1)>;
3550 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
3551 (CMOVNE32rm GR32:$src2, addr:$src1)>;
3552 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
3553 (CMOVE16rm GR16:$src2, addr:$src1)>;
3554 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
3555 (CMOVE32rm GR32:$src2, addr:$src1)>;
3556 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
3557 (CMOVA16rm GR16:$src2, addr:$src1)>;
3558 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
3559 (CMOVA32rm GR32:$src2, addr:$src1)>;
3560 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
3561 (CMOVBE16rm GR16:$src2, addr:$src1)>;
3562 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
3563 (CMOVBE32rm GR32:$src2, addr:$src1)>;
3564 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
3565 (CMOVGE16rm GR16:$src2, addr:$src1)>;
3566 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
3567 (CMOVGE32rm GR32:$src2, addr:$src1)>;
3568 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
3569 (CMOVL16rm GR16:$src2, addr:$src1)>;
3570 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
3571 (CMOVL32rm GR32:$src2, addr:$src1)>;
3572 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
3573 (CMOVG16rm GR16:$src2, addr:$src1)>;
3574 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
3575 (CMOVG32rm GR32:$src2, addr:$src1)>;
3576 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
3577 (CMOVLE16rm GR16:$src2, addr:$src1)>;
3578 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
3579 (CMOVLE32rm GR32:$src2, addr:$src1)>;
3580 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
3581 (CMOVNP16rm GR16:$src2, addr:$src1)>;
3582 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
3583 (CMOVNP32rm GR32:$src2, addr:$src1)>;
3584 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
3585 (CMOVP16rm GR16:$src2, addr:$src1)>;
3586 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
3587 (CMOVP32rm GR32:$src2, addr:$src1)>;
3588 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
3589 (CMOVNS16rm GR16:$src2, addr:$src1)>;
3590 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
3591 (CMOVNS32rm GR32:$src2, addr:$src1)>;
3592 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
3593 (CMOVS16rm GR16:$src2, addr:$src1)>;
3594 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
3595 (CMOVS32rm GR32:$src2, addr:$src1)>;
3596 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
3597 (CMOVNO16rm GR16:$src2, addr:$src1)>;
3598 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
3599 (CMOVNO32rm GR32:$src2, addr:$src1)>;
3600 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
3601 (CMOVO16rm GR16:$src2, addr:$src1)>;
3602 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
3603 (CMOVO32rm GR32:$src2, addr:$src1)>;
3605 // zextload bool -> zextload byte
3606 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3607 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3608 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3610 // extload bool -> extload byte
3611 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3612 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>,
3613 Requires<[In32BitMode]>;
3614 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3615 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>,
3616 Requires<[In32BitMode]>;
3617 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
3618 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
3621 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>,
3622 Requires<[In32BitMode]>;
3623 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>,
3624 Requires<[In32BitMode]>;
3625 def : Pat<(i32 (anyext GR16:$src)),
3626 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
3628 // (and (i32 load), 255) -> (zextload i8)
3629 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
3630 (MOVZX32rm8 addr:$src)>;
3631 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
3632 (MOVZX32rm16 addr:$src)>;
3634 //===----------------------------------------------------------------------===//
3636 //===----------------------------------------------------------------------===//
3638 // Odd encoding trick: -128 fits into an 8-bit immediate field while
3639 // +128 doesn't, so in this special case use a sub instead of an add.
3640 def : Pat<(add GR16:$src1, 128),
3641 (SUB16ri8 GR16:$src1, -128)>;
3642 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
3643 (SUB16mi8 addr:$dst, -128)>;
3644 def : Pat<(add GR32:$src1, 128),
3645 (SUB32ri8 GR32:$src1, -128)>;
3646 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
3647 (SUB32mi8 addr:$dst, -128)>;
3649 // r & (2^16-1) ==> movz
3650 def : Pat<(and GR32:$src1, 0xffff),
3651 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
3652 // r & (2^8-1) ==> movz
3653 def : Pat<(and GR32:$src1, 0xff),
3654 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src1, GR32_ABCD),
3656 Requires<[In32BitMode]>;
3657 // r & (2^8-1) ==> movz
3658 def : Pat<(and GR16:$src1, 0xff),
3659 (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD),
3661 Requires<[In32BitMode]>;
3663 // sext_inreg patterns
3664 def : Pat<(sext_inreg GR32:$src, i16),
3665 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
3666 def : Pat<(sext_inreg GR32:$src, i8),
3667 (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3669 Requires<[In32BitMode]>;
3670 def : Pat<(sext_inreg GR16:$src, i8),
3671 (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3673 Requires<[In32BitMode]>;
3676 def : Pat<(i16 (trunc GR32:$src)),
3677 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
3678 def : Pat<(i8 (trunc GR32:$src)),
3679 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3681 Requires<[In32BitMode]>;
3682 def : Pat<(i8 (trunc GR16:$src)),
3683 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3685 Requires<[In32BitMode]>;
3687 // h-register tricks
3688 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
3689 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3690 x86_subreg_8bit_hi)>,
3691 Requires<[In32BitMode]>;
3692 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
3693 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3694 x86_subreg_8bit_hi)>,
3695 Requires<[In32BitMode]>;
3696 def : Pat<(srl_su GR16:$src, (i8 8)),
3699 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3700 x86_subreg_8bit_hi)),
3702 Requires<[In32BitMode]>;
3703 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
3704 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3705 x86_subreg_8bit_hi))>,
3706 Requires<[In32BitMode]>;
3707 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
3708 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3709 x86_subreg_8bit_hi))>,
3710 Requires<[In32BitMode]>;
3712 // (shl x, 1) ==> (add x, x)
3713 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
3714 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
3715 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
3717 // (shl x (and y, 31)) ==> (shl x, y)
3718 def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
3719 (SHL8rCL GR8:$src1)>;
3720 def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
3721 (SHL16rCL GR16:$src1)>;
3722 def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
3723 (SHL32rCL GR32:$src1)>;
3724 def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3725 (SHL8mCL addr:$dst)>;
3726 def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3727 (SHL16mCL addr:$dst)>;
3728 def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3729 (SHL32mCL addr:$dst)>;
3731 def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
3732 (SHR8rCL GR8:$src1)>;
3733 def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
3734 (SHR16rCL GR16:$src1)>;
3735 def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
3736 (SHR32rCL GR32:$src1)>;
3737 def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3738 (SHR8mCL addr:$dst)>;
3739 def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3740 (SHR16mCL addr:$dst)>;
3741 def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3742 (SHR32mCL addr:$dst)>;
3744 def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
3745 (SAR8rCL GR8:$src1)>;
3746 def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
3747 (SAR16rCL GR16:$src1)>;
3748 def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
3749 (SAR32rCL GR32:$src1)>;
3750 def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3751 (SAR8mCL addr:$dst)>;
3752 def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3753 (SAR16mCL addr:$dst)>;
3754 def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3755 (SAR32mCL addr:$dst)>;
3757 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
3758 def : Pat<(or (srl GR32:$src1, CL:$amt),
3759 (shl GR32:$src2, (sub 32, CL:$amt))),
3760 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3762 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
3763 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3764 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3766 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
3767 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3768 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3770 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3771 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3773 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3775 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3776 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3778 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
3779 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3780 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3782 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
3783 def : Pat<(or (shl GR32:$src1, CL:$amt),
3784 (srl GR32:$src2, (sub 32, CL:$amt))),
3785 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3787 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
3788 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3789 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3791 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
3792 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3793 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3795 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3796 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3798 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3800 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3801 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3803 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
3804 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3805 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3807 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
3808 def : Pat<(or (srl GR16:$src1, CL:$amt),
3809 (shl GR16:$src2, (sub 16, CL:$amt))),
3810 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3812 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
3813 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3814 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3816 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
3817 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3818 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3820 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3821 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3823 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3825 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3826 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3828 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
3829 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3830 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3832 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
3833 def : Pat<(or (shl GR16:$src1, CL:$amt),
3834 (srl GR16:$src2, (sub 16, CL:$amt))),
3835 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3837 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
3838 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3839 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3841 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
3842 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3843 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3845 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3846 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3848 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3850 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3851 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3853 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
3854 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3855 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3857 //===----------------------------------------------------------------------===//
3858 // EFLAGS-defining Patterns
3859 //===----------------------------------------------------------------------===//
3861 // Register-Register Addition with EFLAGS result
3862 def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
3864 (ADD8rr GR8:$src1, GR8:$src2)>;
3865 def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
3867 (ADD16rr GR16:$src1, GR16:$src2)>;
3868 def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
3870 (ADD32rr GR32:$src1, GR32:$src2)>;
3872 // Register-Memory Addition with EFLAGS result
3873 def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
3875 (ADD8rm GR8:$src1, addr:$src2)>;
3876 def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
3878 (ADD16rm GR16:$src1, addr:$src2)>;
3879 def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
3881 (ADD32rm GR32:$src1, addr:$src2)>;
3883 // Register-Integer Addition with EFLAGS result
3884 def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
3886 (ADD8ri GR8:$src1, imm:$src2)>;
3887 def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
3889 (ADD16ri GR16:$src1, imm:$src2)>;
3890 def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
3892 (ADD32ri GR32:$src1, imm:$src2)>;
3893 def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
3895 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
3896 def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
3898 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3900 // Memory-Register Addition with EFLAGS result
3901 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
3904 (ADD8mr addr:$dst, GR8:$src2)>;
3905 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
3908 (ADD16mr addr:$dst, GR16:$src2)>;
3909 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
3912 (ADD32mr addr:$dst, GR32:$src2)>;
3914 // Memory-Integer Addition with EFLAGS result
3915 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
3918 (ADD8mi addr:$dst, imm:$src2)>;
3919 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
3922 (ADD16mi addr:$dst, imm:$src2)>;
3923 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
3926 (ADD32mi addr:$dst, imm:$src2)>;
3927 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
3930 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
3931 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
3934 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
3936 // Register-Register Subtraction with EFLAGS result
3937 def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
3939 (SUB8rr GR8:$src1, GR8:$src2)>;
3940 def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
3942 (SUB16rr GR16:$src1, GR16:$src2)>;
3943 def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
3945 (SUB32rr GR32:$src1, GR32:$src2)>;
3947 // Register-Memory Subtraction with EFLAGS result
3948 def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
3950 (SUB8rm GR8:$src1, addr:$src2)>;
3951 def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
3953 (SUB16rm GR16:$src1, addr:$src2)>;
3954 def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
3956 (SUB32rm GR32:$src1, addr:$src2)>;
3958 // Register-Integer Subtraction with EFLAGS result
3959 def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
3961 (SUB8ri GR8:$src1, imm:$src2)>;
3962 def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
3964 (SUB16ri GR16:$src1, imm:$src2)>;
3965 def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
3967 (SUB32ri GR32:$src1, imm:$src2)>;
3968 def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
3970 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
3971 def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
3973 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3975 // Memory-Register Subtraction with EFLAGS result
3976 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
3979 (SUB8mr addr:$dst, GR8:$src2)>;
3980 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
3983 (SUB16mr addr:$dst, GR16:$src2)>;
3984 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
3987 (SUB32mr addr:$dst, GR32:$src2)>;
3989 // Memory-Integer Subtraction with EFLAGS result
3990 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
3993 (SUB8mi addr:$dst, imm:$src2)>;
3994 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
3997 (SUB16mi addr:$dst, imm:$src2)>;
3998 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
4001 (SUB32mi addr:$dst, imm:$src2)>;
4002 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4005 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
4006 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4009 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
4012 // Register-Register Signed Integer Multiply with EFLAGS result
4013 def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
4015 (IMUL16rr GR16:$src1, GR16:$src2)>;
4016 def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
4018 (IMUL32rr GR32:$src1, GR32:$src2)>;
4020 // Register-Memory Signed Integer Multiply with EFLAGS result
4021 def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
4023 (IMUL16rm GR16:$src1, addr:$src2)>;
4024 def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
4026 (IMUL32rm GR32:$src1, addr:$src2)>;
4028 // Register-Integer Signed Integer Multiply with EFLAGS result
4029 def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
4031 (IMUL16rri GR16:$src1, imm:$src2)>;
4032 def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
4034 (IMUL32rri GR32:$src1, imm:$src2)>;
4035 def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
4037 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4038 def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
4040 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4042 // Memory-Integer Signed Integer Multiply with EFLAGS result
4043 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
4045 (IMUL16rmi addr:$src1, imm:$src2)>;
4046 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
4048 (IMUL32rmi addr:$src1, imm:$src2)>;
4049 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
4051 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4052 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
4054 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4056 // Optimize multiply by 2 with EFLAGS result.
4057 let AddedComplexity = 2 in {
4058 def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
4060 (ADD16rr GR16:$src1, GR16:$src1)>;
4062 def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
4064 (ADD32rr GR32:$src1, GR32:$src1)>;
4067 // INC and DEC with EFLAGS result. Note that these do not set CF.
4068 def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
4070 def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
4073 def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
4075 def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
4079 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
4080 (INC16r GR16:$src)>, Requires<[In32BitMode]>;
4081 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
4083 (INC16m addr:$dst)>, Requires<[In32BitMode]>;
4084 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
4085 (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
4086 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
4088 (DEC16m addr:$dst)>, Requires<[In32BitMode]>;
4090 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
4091 (INC32r GR32:$src)>, Requires<[In32BitMode]>;
4092 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
4094 (INC32m addr:$dst)>, Requires<[In32BitMode]>;
4095 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
4096 (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
4097 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
4099 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
4101 //===----------------------------------------------------------------------===//
4102 // Floating Point Stack Support
4103 //===----------------------------------------------------------------------===//
4105 include "X86InstrFPStack.td"
4107 //===----------------------------------------------------------------------===//
4109 //===----------------------------------------------------------------------===//
4111 include "X86Instr64bit.td"
4113 //===----------------------------------------------------------------------===//
4114 // XMM Floating point support (requires SSE / SSE2)
4115 //===----------------------------------------------------------------------===//
4117 include "X86InstrSSE.td"
4119 //===----------------------------------------------------------------------===//
4120 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
4121 //===----------------------------------------------------------------------===//
4123 include "X86InstrMMX.td"