1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 def SDTX86BrCond : SDTypeProfile<0, 3,
31 [SDTCisVT<0, OtherVT>,
32 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
34 def SDTX86SetCC : SDTypeProfile<1, 2,
36 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
38 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
40 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
42 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
43 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
44 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
46 def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
47 def SDT_X86CallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
50 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
52 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
54 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
56 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
58 def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
60 def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
62 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
64 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
66 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
67 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
68 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
69 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
71 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
73 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
74 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
76 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
78 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
79 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
81 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
82 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
84 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
85 [SDNPHasChain, SDNPMayStore,
86 SDNPMayLoad, SDNPMemOperand]>;
87 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
88 [SDNPHasChain, SDNPMayStore,
89 SDNPMayLoad, SDNPMemOperand]>;
90 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
91 [SDNPHasChain, SDNPMayStore,
92 SDNPMayLoad, SDNPMemOperand]>;
93 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
94 [SDNPHasChain, SDNPMayStore,
95 SDNPMayLoad, SDNPMemOperand]>;
96 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
97 [SDNPHasChain, SDNPMayStore,
98 SDNPMayLoad, SDNPMemOperand]>;
99 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
100 [SDNPHasChain, SDNPMayStore,
101 SDNPMayLoad, SDNPMemOperand]>;
102 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
103 [SDNPHasChain, SDNPMayStore,
104 SDNPMayLoad, SDNPMemOperand]>;
105 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
106 [SDNPHasChain, SDNPOptInFlag]>;
108 def X86callseq_start :
109 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
110 [SDNPHasChain, SDNPOutFlag]>;
112 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
113 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
115 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
116 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
118 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
119 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
121 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
122 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
123 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
124 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
127 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
128 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
130 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
131 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
133 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
134 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
135 def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
137 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
140 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
141 [SDNPHasChain, SDNPOptInFlag]>;
143 //===----------------------------------------------------------------------===//
144 // X86 Operand Definitions.
147 // *mem - Operand definitions for the funky X86 addressing mode operands.
149 class X86MemOperand<string printMethod> : Operand<iPTR> {
150 let PrintMethod = printMethod;
151 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
154 def i8mem : X86MemOperand<"printi8mem">;
155 def i16mem : X86MemOperand<"printi16mem">;
156 def i32mem : X86MemOperand<"printi32mem">;
157 def i64mem : X86MemOperand<"printi64mem">;
158 def i128mem : X86MemOperand<"printi128mem">;
159 def f32mem : X86MemOperand<"printf32mem">;
160 def f64mem : X86MemOperand<"printf64mem">;
161 def f80mem : X86MemOperand<"printf80mem">;
162 def f128mem : X86MemOperand<"printf128mem">;
164 def lea32mem : Operand<i32> {
165 let PrintMethod = "printi32mem";
166 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
169 def SSECC : Operand<i8> {
170 let PrintMethod = "printSSECC";
173 def piclabel: Operand<i32> {
174 let PrintMethod = "printPICLabel";
177 // A couple of more descriptive operand definitions.
178 // 16-bits but only 8 bits are significant.
179 def i16i8imm : Operand<i16>;
180 // 32-bits but only 8 bits are significant.
181 def i32i8imm : Operand<i32>;
183 // Branch targets have OtherVT type.
184 def brtarget : Operand<OtherVT>;
186 //===----------------------------------------------------------------------===//
187 // X86 Complex Pattern Definitions.
190 // Define X86 specific addressing mode.
191 def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
192 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
193 [add, mul, shl, or, frameindex], []>;
195 //===----------------------------------------------------------------------===//
196 // X86 Instruction Predicate Definitions.
197 def HasMMX : Predicate<"Subtarget->hasMMX()">;
198 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
199 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
200 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
201 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
202 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
203 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
204 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
205 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
206 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
207 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
208 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
209 def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
210 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
211 def OptForSpeed : Predicate<"!OptForSize">;
213 //===----------------------------------------------------------------------===//
214 // X86 Instruction Format Definitions.
217 include "X86InstrFormats.td"
219 //===----------------------------------------------------------------------===//
220 // Pattern fragments...
223 // X86 specific condition code. These correspond to CondCode in
224 // X86InstrInfo.h. They must be kept in synch.
225 def X86_COND_A : PatLeaf<(i8 0)>;
226 def X86_COND_AE : PatLeaf<(i8 1)>;
227 def X86_COND_B : PatLeaf<(i8 2)>;
228 def X86_COND_BE : PatLeaf<(i8 3)>;
229 def X86_COND_E : PatLeaf<(i8 4)>;
230 def X86_COND_G : PatLeaf<(i8 5)>;
231 def X86_COND_GE : PatLeaf<(i8 6)>;
232 def X86_COND_L : PatLeaf<(i8 7)>;
233 def X86_COND_LE : PatLeaf<(i8 8)>;
234 def X86_COND_NE : PatLeaf<(i8 9)>;
235 def X86_COND_NO : PatLeaf<(i8 10)>;
236 def X86_COND_NP : PatLeaf<(i8 11)>;
237 def X86_COND_NS : PatLeaf<(i8 12)>;
238 def X86_COND_NC : PatLeaf<(i8 13)>;
239 def X86_COND_O : PatLeaf<(i8 14)>;
240 def X86_COND_P : PatLeaf<(i8 15)>;
241 def X86_COND_S : PatLeaf<(i8 16)>;
242 def X86_COND_C : PatLeaf<(i8 17)>;
244 def i16immSExt8 : PatLeaf<(i16 imm), [{
245 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
246 // sign extended field.
247 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
250 def i32immSExt8 : PatLeaf<(i32 imm), [{
251 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
252 // sign extended field.
253 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
256 // Helper fragments for loads.
257 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
258 // known to be 32-bit aligned or better. Ditto for i8 to i16.
259 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
260 LoadSDNode *LD = cast<LoadSDNode>(N);
261 ISD::LoadExtType ExtType = LD->getExtensionType();
262 if (ExtType == ISD::NON_EXTLOAD)
264 if (ExtType == ISD::EXTLOAD)
265 return LD->getAlignment() >= 2 && !LD->isVolatile();
269 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
270 LoadSDNode *LD = cast<LoadSDNode>(N);
271 ISD::LoadExtType ExtType = LD->getExtensionType();
272 if (ExtType == ISD::EXTLOAD)
273 return LD->getAlignment() >= 2 && !LD->isVolatile();
277 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
278 LoadSDNode *LD = cast<LoadSDNode>(N);
279 ISD::LoadExtType ExtType = LD->getExtensionType();
280 if (ExtType == ISD::NON_EXTLOAD)
282 if (ExtType == ISD::EXTLOAD)
283 return LD->getAlignment() >= 4 && !LD->isVolatile();
287 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
288 LoadSDNode *LD = cast<LoadSDNode>(N);
289 if (LD->isVolatile())
291 ISD::LoadExtType ExtType = LD->getExtensionType();
292 if (ExtType == ISD::NON_EXTLOAD)
294 if (ExtType == ISD::EXTLOAD)
295 return LD->getAlignment() >= 4;
299 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
300 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
302 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
303 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
304 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
306 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
307 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
308 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
310 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
311 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
312 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
313 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
314 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
315 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
317 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
318 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
319 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
320 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
321 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
322 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
325 // An 'and' node with a single use.
326 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
327 return N->hasOneUse();
330 // 'shld' and 'shrd' instruction patterns. Note that even though these have
331 // the srl and shl in their patterns, the C++ code must still check for them,
332 // because predicates are tested before children nodes are explored.
334 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
335 (or (srl node:$src1, node:$amt1),
336 (shl node:$src2, node:$amt2)), [{
337 assert(N->getOpcode() == ISD::OR);
338 return N->getOperand(0).getOpcode() == ISD::SRL &&
339 N->getOperand(1).getOpcode() == ISD::SHL &&
340 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
341 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
342 N->getOperand(0).getConstantOperandVal(1) ==
343 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
346 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
347 (or (shl node:$src1, node:$amt1),
348 (srl node:$src2, node:$amt2)), [{
349 assert(N->getOpcode() == ISD::OR);
350 return N->getOperand(0).getOpcode() == ISD::SHL &&
351 N->getOperand(1).getOpcode() == ISD::SRL &&
352 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
353 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
354 N->getOperand(0).getConstantOperandVal(1) ==
355 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
358 //===----------------------------------------------------------------------===//
359 // Instruction list...
362 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
363 // a stack adjustment and the codegen must know that they may modify the stack
364 // pointer before prolog-epilog rewriting occurs.
365 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
366 // sub / add which can clobber EFLAGS.
367 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
368 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
370 [(X86callseq_start timm:$amt)]>,
371 Requires<[In32BitMode]>;
372 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
374 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
375 Requires<[In32BitMode]>;
379 let neverHasSideEffects = 1 in
380 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
383 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
384 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
385 "call\t$label\n\tpop{l}\t$reg", []>;
387 //===----------------------------------------------------------------------===//
388 // Control Flow Instructions...
391 // Return instructions.
392 let isTerminator = 1, isReturn = 1, isBarrier = 1,
393 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
394 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
397 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
399 [(X86retflag imm:$amt)]>;
402 // All branches are RawFrm, Void, Branch, and Terminators
403 let isBranch = 1, isTerminator = 1 in
404 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
405 I<opcode, RawFrm, (outs), ins, asm, pattern>;
407 let isBranch = 1, isBarrier = 1 in
408 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
411 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
412 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
413 [(brind GR32:$dst)]>;
414 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
415 [(brind (loadi32 addr:$dst))]>;
418 // Conditional branches
419 let Uses = [EFLAGS] in {
420 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
421 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
422 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
423 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
424 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
425 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
426 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
427 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
428 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
429 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
430 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
431 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
433 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
434 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
435 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
436 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
437 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
438 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
439 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
440 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
442 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
443 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
444 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
445 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
446 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
447 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
448 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
449 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
450 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
451 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
452 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
453 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
454 def JC : IBr<0x82, (ins brtarget:$dst), "jc\t$dst",
455 [(X86brcond bb:$dst, X86_COND_C, EFLAGS)]>, TB;
456 def JNC : IBr<0x83, (ins brtarget:$dst), "jnc\t$dst",
457 [(X86brcond bb:$dst, X86_COND_NC, EFLAGS)]>, TB;
460 //===----------------------------------------------------------------------===//
461 // Call Instructions...
464 // All calls clobber the non-callee saved registers. ESP is marked as
465 // a use to prevent stack-pointer assignments that appear immediately
466 // before calls from potentially appearing dead. Uses for argument
467 // registers are added manually.
468 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
469 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
470 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
471 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
473 def CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:$dst,variable_ops),
474 "call\t${dst:call}", []>;
475 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
476 "call\t{*}$dst", [(X86call GR32:$dst)]>;
477 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
478 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
483 def TAILCALL : I<0, Pseudo, (outs), (ins),
487 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
488 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops),
489 "#TC_RETURN $dst $offset",
492 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
493 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops),
494 "#TC_RETURN $dst $offset",
497 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
499 def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAILCALL",
501 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
502 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
504 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
505 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
506 "jmp\t{*}$dst # TAILCALL", []>;
508 //===----------------------------------------------------------------------===//
509 // Miscellaneous Instructions...
511 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
512 def LEAVE : I<0xC9, RawFrm,
513 (outs), (ins), "leave", []>;
515 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
517 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
520 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
523 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
524 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
525 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
526 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
528 let isTwoAddress = 1 in // GR32 = bswap GR32
529 def BSWAP32r : I<0xC8, AddRegFrm,
530 (outs GR32:$dst), (ins GR32:$src),
532 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
535 // Bit scan instructions.
536 let Defs = [EFLAGS] in {
537 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
538 "bsf{w}\t{$src, $dst|$dst, $src}",
539 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
540 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
541 "bsf{w}\t{$src, $dst|$dst, $src}",
542 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
543 (implicit EFLAGS)]>, TB;
544 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
545 "bsf{l}\t{$src, $dst|$dst, $src}",
546 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
547 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
548 "bsf{l}\t{$src, $dst|$dst, $src}",
549 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
550 (implicit EFLAGS)]>, TB;
552 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
553 "bsr{w}\t{$src, $dst|$dst, $src}",
554 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
555 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
556 "bsr{w}\t{$src, $dst|$dst, $src}",
557 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
558 (implicit EFLAGS)]>, TB;
559 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
560 "bsr{l}\t{$src, $dst|$dst, $src}",
561 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
562 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
563 "bsr{l}\t{$src, $dst|$dst, $src}",
564 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
565 (implicit EFLAGS)]>, TB;
568 let neverHasSideEffects = 1 in
569 def LEA16r : I<0x8D, MRMSrcMem,
570 (outs GR16:$dst), (ins i32mem:$src),
571 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
572 let isReMaterializable = 1 in
573 def LEA32r : I<0x8D, MRMSrcMem,
574 (outs GR32:$dst), (ins lea32mem:$src),
575 "lea{l}\t{$src|$dst}, {$dst|$src}",
576 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
578 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
579 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
580 [(X86rep_movs i8)]>, REP;
581 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
582 [(X86rep_movs i16)]>, REP, OpSize;
583 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
584 [(X86rep_movs i32)]>, REP;
587 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
588 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
589 [(X86rep_stos i8)]>, REP;
590 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
591 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
592 [(X86rep_stos i16)]>, REP, OpSize;
593 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
594 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
595 [(X86rep_stos i32)]>, REP;
597 let Defs = [RAX, RDX] in
598 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
601 let isBarrier = 1, hasCtrlDep = 1 in {
602 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
605 //===----------------------------------------------------------------------===//
606 // Input/Output Instructions...
608 let Defs = [AL], Uses = [DX] in
609 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
610 "in{b}\t{%dx, %al|%AL, %DX}", []>;
611 let Defs = [AX], Uses = [DX] in
612 def IN16rr : I<0xED, RawFrm, (outs), (ins),
613 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
614 let Defs = [EAX], Uses = [DX] in
615 def IN32rr : I<0xED, RawFrm, (outs), (ins),
616 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
619 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
620 "in{b}\t{$port, %al|%AL, $port}", []>;
622 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
623 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
625 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
626 "in{l}\t{$port, %eax|%EAX, $port}", []>;
628 let Uses = [DX, AL] in
629 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
630 "out{b}\t{%al, %dx|%DX, %AL}", []>;
631 let Uses = [DX, AX] in
632 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
633 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
634 let Uses = [DX, EAX] in
635 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
636 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
639 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
640 "out{b}\t{%al, $port|$port, %AL}", []>;
642 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
643 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
645 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
646 "out{l}\t{%eax, $port|$port, %EAX}", []>;
648 //===----------------------------------------------------------------------===//
649 // Move Instructions...
651 let neverHasSideEffects = 1 in {
652 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
653 "mov{b}\t{$src, $dst|$dst, $src}", []>;
654 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
655 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
656 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
657 "mov{l}\t{$src, $dst|$dst, $src}", []>;
659 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
660 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
661 "mov{b}\t{$src, $dst|$dst, $src}",
662 [(set GR8:$dst, imm:$src)]>;
663 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
664 "mov{w}\t{$src, $dst|$dst, $src}",
665 [(set GR16:$dst, imm:$src)]>, OpSize;
666 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
667 "mov{l}\t{$src, $dst|$dst, $src}",
668 [(set GR32:$dst, imm:$src)]>;
670 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
671 "mov{b}\t{$src, $dst|$dst, $src}",
672 [(store (i8 imm:$src), addr:$dst)]>;
673 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
674 "mov{w}\t{$src, $dst|$dst, $src}",
675 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
676 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
677 "mov{l}\t{$src, $dst|$dst, $src}",
678 [(store (i32 imm:$src), addr:$dst)]>;
680 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
681 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
682 "mov{b}\t{$src, $dst|$dst, $src}",
683 [(set GR8:$dst, (load addr:$src))]>;
684 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
685 "mov{w}\t{$src, $dst|$dst, $src}",
686 [(set GR16:$dst, (load addr:$src))]>, OpSize;
687 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
688 "mov{l}\t{$src, $dst|$dst, $src}",
689 [(set GR32:$dst, (load addr:$src))]>;
692 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
693 "mov{b}\t{$src, $dst|$dst, $src}",
694 [(store GR8:$src, addr:$dst)]>;
695 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
696 "mov{w}\t{$src, $dst|$dst, $src}",
697 [(store GR16:$src, addr:$dst)]>, OpSize;
698 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
699 "mov{l}\t{$src, $dst|$dst, $src}",
700 [(store GR32:$src, addr:$dst)]>;
702 //===----------------------------------------------------------------------===//
703 // Fixed-Register Multiplication and Division Instructions...
706 // Extra precision multiplication
707 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
708 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
709 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
710 // This probably ought to be moved to a def : Pat<> if the
711 // syntax can be accepted.
712 [(set AL, (mul AL, GR8:$src))]>; // AL,AH = AL*GR8
713 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
714 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src",
715 []>, OpSize; // AX,DX = AX*GR16
716 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
717 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l}\t$src", []>;
718 // EAX,EDX = EAX*GR32
719 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
720 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
722 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
723 // This probably ought to be moved to a def : Pat<> if the
724 // syntax can be accepted.
725 [(set AL, (mul AL, (loadi8 addr:$src)))]>; // AL,AH = AL*[mem8]
726 let mayLoad = 1, neverHasSideEffects = 1 in {
727 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
728 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
729 "mul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
730 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
731 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
732 "mul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
735 let neverHasSideEffects = 1 in {
736 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
737 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
739 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
740 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
741 OpSize; // AX,DX = AX*GR16
742 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
743 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
744 // EAX,EDX = EAX*GR32
746 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
747 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
748 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
749 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
750 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
751 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
752 let Defs = [EAX,EDX], Uses = [EAX] in
753 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
754 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
756 } // neverHasSideEffects
758 // unsigned division/remainder
759 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
760 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
762 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
763 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
764 "div{w}\t$src", []>, OpSize;
765 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
766 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
769 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
770 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
772 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
773 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
774 "div{w}\t$src", []>, OpSize;
775 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
776 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
780 // Signed division/remainder.
781 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
782 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
783 "idiv{b}\t$src", []>;
784 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
785 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
786 "idiv{w}\t$src", []>, OpSize;
787 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
788 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
789 "idiv{l}\t$src", []>;
790 let mayLoad = 1, mayLoad = 1 in {
791 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
792 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
793 "idiv{b}\t$src", []>;
794 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
795 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
796 "idiv{w}\t$src", []>, OpSize;
797 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
798 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
799 "idiv{l}\t$src", []>;
802 //===----------------------------------------------------------------------===//
803 // Two address Instructions.
805 let isTwoAddress = 1 in {
808 let Uses = [EFLAGS] in {
809 let isCommutable = 1 in {
810 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
811 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
812 "cmovb\t{$src2, $dst|$dst, $src2}",
813 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
814 X86_COND_B, EFLAGS))]>,
816 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
817 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
818 "cmovb\t{$src2, $dst|$dst, $src2}",
819 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
820 X86_COND_B, EFLAGS))]>,
823 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
824 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
825 "cmovae\t{$src2, $dst|$dst, $src2}",
826 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
827 X86_COND_AE, EFLAGS))]>,
829 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
830 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
831 "cmovae\t{$src2, $dst|$dst, $src2}",
832 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
833 X86_COND_AE, EFLAGS))]>,
835 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
836 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
837 "cmove\t{$src2, $dst|$dst, $src2}",
838 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
839 X86_COND_E, EFLAGS))]>,
841 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
842 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
843 "cmove\t{$src2, $dst|$dst, $src2}",
844 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
845 X86_COND_E, EFLAGS))]>,
847 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
848 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
849 "cmovne\t{$src2, $dst|$dst, $src2}",
850 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
851 X86_COND_NE, EFLAGS))]>,
853 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
854 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
855 "cmovne\t{$src2, $dst|$dst, $src2}",
856 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
857 X86_COND_NE, EFLAGS))]>,
859 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
860 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
861 "cmovbe\t{$src2, $dst|$dst, $src2}",
862 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
863 X86_COND_BE, EFLAGS))]>,
865 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
866 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
867 "cmovbe\t{$src2, $dst|$dst, $src2}",
868 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
869 X86_COND_BE, EFLAGS))]>,
871 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
872 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
873 "cmova\t{$src2, $dst|$dst, $src2}",
874 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
875 X86_COND_A, EFLAGS))]>,
877 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
878 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
879 "cmova\t{$src2, $dst|$dst, $src2}",
880 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
881 X86_COND_A, EFLAGS))]>,
883 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
884 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
885 "cmovl\t{$src2, $dst|$dst, $src2}",
886 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
887 X86_COND_L, EFLAGS))]>,
889 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
890 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
891 "cmovl\t{$src2, $dst|$dst, $src2}",
892 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
893 X86_COND_L, EFLAGS))]>,
895 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
896 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
897 "cmovge\t{$src2, $dst|$dst, $src2}",
898 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
899 X86_COND_GE, EFLAGS))]>,
901 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
902 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
903 "cmovge\t{$src2, $dst|$dst, $src2}",
904 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
905 X86_COND_GE, EFLAGS))]>,
907 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
908 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
909 "cmovle\t{$src2, $dst|$dst, $src2}",
910 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
911 X86_COND_LE, EFLAGS))]>,
913 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
914 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
915 "cmovle\t{$src2, $dst|$dst, $src2}",
916 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
917 X86_COND_LE, EFLAGS))]>,
919 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
920 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
921 "cmovg\t{$src2, $dst|$dst, $src2}",
922 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
923 X86_COND_G, EFLAGS))]>,
925 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
926 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
927 "cmovg\t{$src2, $dst|$dst, $src2}",
928 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
929 X86_COND_G, EFLAGS))]>,
931 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
932 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
933 "cmovs\t{$src2, $dst|$dst, $src2}",
934 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
935 X86_COND_S, EFLAGS))]>,
937 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
938 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
939 "cmovs\t{$src2, $dst|$dst, $src2}",
940 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
941 X86_COND_S, EFLAGS))]>,
943 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
944 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
945 "cmovns\t{$src2, $dst|$dst, $src2}",
946 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
947 X86_COND_NS, EFLAGS))]>,
949 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
950 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
951 "cmovns\t{$src2, $dst|$dst, $src2}",
952 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
953 X86_COND_NS, EFLAGS))]>,
955 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
956 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
957 "cmovp\t{$src2, $dst|$dst, $src2}",
958 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
959 X86_COND_P, EFLAGS))]>,
961 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
962 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
963 "cmovp\t{$src2, $dst|$dst, $src2}",
964 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
965 X86_COND_P, EFLAGS))]>,
967 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
968 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
969 "cmovnp\t{$src2, $dst|$dst, $src2}",
970 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
971 X86_COND_NP, EFLAGS))]>,
973 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
974 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
975 "cmovnp\t{$src2, $dst|$dst, $src2}",
976 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
977 X86_COND_NP, EFLAGS))]>,
979 } // isCommutable = 1
981 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
982 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
983 "cmovnp\t{$src2, $dst|$dst, $src2}",
984 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
985 X86_COND_NP, EFLAGS))]>,
988 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
989 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
990 "cmovb\t{$src2, $dst|$dst, $src2}",
991 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
992 X86_COND_B, EFLAGS))]>,
994 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
995 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
996 "cmovb\t{$src2, $dst|$dst, $src2}",
997 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
998 X86_COND_B, EFLAGS))]>,
1000 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1001 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1002 "cmovae\t{$src2, $dst|$dst, $src2}",
1003 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1004 X86_COND_AE, EFLAGS))]>,
1006 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1007 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1008 "cmovae\t{$src2, $dst|$dst, $src2}",
1009 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1010 X86_COND_AE, EFLAGS))]>,
1012 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1013 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1014 "cmove\t{$src2, $dst|$dst, $src2}",
1015 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1016 X86_COND_E, EFLAGS))]>,
1018 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1019 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1020 "cmove\t{$src2, $dst|$dst, $src2}",
1021 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1022 X86_COND_E, EFLAGS))]>,
1024 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1025 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1026 "cmovne\t{$src2, $dst|$dst, $src2}",
1027 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1028 X86_COND_NE, EFLAGS))]>,
1030 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1031 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1032 "cmovne\t{$src2, $dst|$dst, $src2}",
1033 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1034 X86_COND_NE, EFLAGS))]>,
1036 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1037 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1038 "cmovbe\t{$src2, $dst|$dst, $src2}",
1039 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1040 X86_COND_BE, EFLAGS))]>,
1042 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1043 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1044 "cmovbe\t{$src2, $dst|$dst, $src2}",
1045 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1046 X86_COND_BE, EFLAGS))]>,
1048 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1049 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1050 "cmova\t{$src2, $dst|$dst, $src2}",
1051 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1052 X86_COND_A, EFLAGS))]>,
1054 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1055 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1056 "cmova\t{$src2, $dst|$dst, $src2}",
1057 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1058 X86_COND_A, EFLAGS))]>,
1060 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1061 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1062 "cmovl\t{$src2, $dst|$dst, $src2}",
1063 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1064 X86_COND_L, EFLAGS))]>,
1066 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1067 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1068 "cmovl\t{$src2, $dst|$dst, $src2}",
1069 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1070 X86_COND_L, EFLAGS))]>,
1072 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1073 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1074 "cmovge\t{$src2, $dst|$dst, $src2}",
1075 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1076 X86_COND_GE, EFLAGS))]>,
1078 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1079 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1080 "cmovge\t{$src2, $dst|$dst, $src2}",
1081 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1082 X86_COND_GE, EFLAGS))]>,
1084 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1085 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1086 "cmovle\t{$src2, $dst|$dst, $src2}",
1087 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1088 X86_COND_LE, EFLAGS))]>,
1090 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1091 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1092 "cmovle\t{$src2, $dst|$dst, $src2}",
1093 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1094 X86_COND_LE, EFLAGS))]>,
1096 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1097 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1098 "cmovg\t{$src2, $dst|$dst, $src2}",
1099 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1100 X86_COND_G, EFLAGS))]>,
1102 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1103 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1104 "cmovg\t{$src2, $dst|$dst, $src2}",
1105 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1106 X86_COND_G, EFLAGS))]>,
1108 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1109 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1110 "cmovs\t{$src2, $dst|$dst, $src2}",
1111 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1112 X86_COND_S, EFLAGS))]>,
1114 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1115 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1116 "cmovs\t{$src2, $dst|$dst, $src2}",
1117 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1118 X86_COND_S, EFLAGS))]>,
1120 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1121 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1122 "cmovns\t{$src2, $dst|$dst, $src2}",
1123 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1124 X86_COND_NS, EFLAGS))]>,
1126 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1127 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1128 "cmovns\t{$src2, $dst|$dst, $src2}",
1129 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1130 X86_COND_NS, EFLAGS))]>,
1132 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1133 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1134 "cmovp\t{$src2, $dst|$dst, $src2}",
1135 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1136 X86_COND_P, EFLAGS))]>,
1138 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1139 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1140 "cmovp\t{$src2, $dst|$dst, $src2}",
1141 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1142 X86_COND_P, EFLAGS))]>,
1144 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1145 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1146 "cmovnp\t{$src2, $dst|$dst, $src2}",
1147 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1148 X86_COND_NP, EFLAGS))]>,
1150 } // Uses = [EFLAGS]
1153 // unary instructions
1154 let CodeSize = 2 in {
1155 let Defs = [EFLAGS] in {
1156 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1157 [(set GR8:$dst, (ineg GR8:$src))]>;
1158 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1159 [(set GR16:$dst, (ineg GR16:$src))]>, OpSize;
1160 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1161 [(set GR32:$dst, (ineg GR32:$src))]>;
1162 let isTwoAddress = 0 in {
1163 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1164 [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
1165 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1166 [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1167 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1168 [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
1171 } // Defs = [EFLAGS]
1173 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1174 [(set GR8:$dst, (not GR8:$src))]>;
1175 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1176 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1177 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1178 [(set GR32:$dst, (not GR32:$src))]>;
1179 let isTwoAddress = 0 in {
1180 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1181 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1182 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1183 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1184 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1185 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1189 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1190 let Defs = [EFLAGS] in {
1192 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1193 [(set GR8:$dst, (add GR8:$src, 1))]>;
1194 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1195 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1196 [(set GR16:$dst, (add GR16:$src, 1))]>,
1197 OpSize, Requires<[In32BitMode]>;
1198 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1199 [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>;
1201 let isTwoAddress = 0, CodeSize = 2 in {
1202 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1203 [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
1204 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1205 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>,
1206 OpSize, Requires<[In32BitMode]>;
1207 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1208 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>,
1209 Requires<[In32BitMode]>;
1213 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1214 [(set GR8:$dst, (add GR8:$src, -1))]>;
1215 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1216 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1217 [(set GR16:$dst, (add GR16:$src, -1))]>,
1218 OpSize, Requires<[In32BitMode]>;
1219 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1220 [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>;
1223 let isTwoAddress = 0, CodeSize = 2 in {
1224 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1225 [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
1226 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1227 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>,
1228 OpSize, Requires<[In32BitMode]>;
1229 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1230 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>,
1231 Requires<[In32BitMode]>;
1233 } // Defs = [EFLAGS]
1235 // Logical operators...
1236 let Defs = [EFLAGS] in {
1237 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1238 def AND8rr : I<0x20, MRMDestReg,
1239 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1240 "and{b}\t{$src2, $dst|$dst, $src2}",
1241 [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>;
1242 def AND16rr : I<0x21, MRMDestReg,
1243 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1244 "and{w}\t{$src2, $dst|$dst, $src2}",
1245 [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize;
1246 def AND32rr : I<0x21, MRMDestReg,
1247 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1248 "and{l}\t{$src2, $dst|$dst, $src2}",
1249 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
1252 def AND8rm : I<0x22, MRMSrcMem,
1253 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1254 "and{b}\t{$src2, $dst|$dst, $src2}",
1255 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>;
1256 def AND16rm : I<0x23, MRMSrcMem,
1257 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1258 "and{w}\t{$src2, $dst|$dst, $src2}",
1259 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize;
1260 def AND32rm : I<0x23, MRMSrcMem,
1261 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1262 "and{l}\t{$src2, $dst|$dst, $src2}",
1263 [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>;
1265 def AND8ri : Ii8<0x80, MRM4r,
1266 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1267 "and{b}\t{$src2, $dst|$dst, $src2}",
1268 [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>;
1269 def AND16ri : Ii16<0x81, MRM4r,
1270 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1271 "and{w}\t{$src2, $dst|$dst, $src2}",
1272 [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize;
1273 def AND32ri : Ii32<0x81, MRM4r,
1274 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1275 "and{l}\t{$src2, $dst|$dst, $src2}",
1276 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
1277 def AND16ri8 : Ii8<0x83, MRM4r,
1278 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1279 "and{w}\t{$src2, $dst|$dst, $src2}",
1280 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>,
1282 def AND32ri8 : Ii8<0x83, MRM4r,
1283 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1284 "and{l}\t{$src2, $dst|$dst, $src2}",
1285 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>;
1287 let isTwoAddress = 0 in {
1288 def AND8mr : I<0x20, MRMDestMem,
1289 (outs), (ins i8mem :$dst, GR8 :$src),
1290 "and{b}\t{$src, $dst|$dst, $src}",
1291 [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>;
1292 def AND16mr : I<0x21, MRMDestMem,
1293 (outs), (ins i16mem:$dst, GR16:$src),
1294 "and{w}\t{$src, $dst|$dst, $src}",
1295 [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>,
1297 def AND32mr : I<0x21, MRMDestMem,
1298 (outs), (ins i32mem:$dst, GR32:$src),
1299 "and{l}\t{$src, $dst|$dst, $src}",
1300 [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>;
1301 def AND8mi : Ii8<0x80, MRM4m,
1302 (outs), (ins i8mem :$dst, i8imm :$src),
1303 "and{b}\t{$src, $dst|$dst, $src}",
1304 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1305 def AND16mi : Ii16<0x81, MRM4m,
1306 (outs), (ins i16mem:$dst, i16imm:$src),
1307 "and{w}\t{$src, $dst|$dst, $src}",
1308 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1310 def AND32mi : Ii32<0x81, MRM4m,
1311 (outs), (ins i32mem:$dst, i32imm:$src),
1312 "and{l}\t{$src, $dst|$dst, $src}",
1313 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1314 def AND16mi8 : Ii8<0x83, MRM4m,
1315 (outs), (ins i16mem:$dst, i16i8imm :$src),
1316 "and{w}\t{$src, $dst|$dst, $src}",
1317 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1319 def AND32mi8 : Ii8<0x83, MRM4m,
1320 (outs), (ins i32mem:$dst, i32i8imm :$src),
1321 "and{l}\t{$src, $dst|$dst, $src}",
1322 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1326 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1327 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1328 "or{b}\t{$src2, $dst|$dst, $src2}",
1329 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
1330 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1331 "or{w}\t{$src2, $dst|$dst, $src2}",
1332 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize;
1333 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1334 "or{l}\t{$src2, $dst|$dst, $src2}",
1335 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
1337 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1338 "or{b}\t{$src2, $dst|$dst, $src2}",
1339 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
1340 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1341 "or{w}\t{$src2, $dst|$dst, $src2}",
1342 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize;
1343 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1344 "or{l}\t{$src2, $dst|$dst, $src2}",
1345 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>;
1347 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1348 "or{b}\t{$src2, $dst|$dst, $src2}",
1349 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
1350 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1351 "or{w}\t{$src2, $dst|$dst, $src2}",
1352 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize;
1353 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1354 "or{l}\t{$src2, $dst|$dst, $src2}",
1355 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
1357 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1358 "or{w}\t{$src2, $dst|$dst, $src2}",
1359 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1360 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1361 "or{l}\t{$src2, $dst|$dst, $src2}",
1362 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>;
1363 let isTwoAddress = 0 in {
1364 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1365 "or{b}\t{$src, $dst|$dst, $src}",
1366 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
1367 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1368 "or{w}\t{$src, $dst|$dst, $src}",
1369 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize;
1370 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1371 "or{l}\t{$src, $dst|$dst, $src}",
1372 [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>;
1373 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1374 "or{b}\t{$src, $dst|$dst, $src}",
1375 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1376 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1377 "or{w}\t{$src, $dst|$dst, $src}",
1378 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1380 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1381 "or{l}\t{$src, $dst|$dst, $src}",
1382 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1383 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1384 "or{w}\t{$src, $dst|$dst, $src}",
1385 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1387 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1388 "or{l}\t{$src, $dst|$dst, $src}",
1389 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1390 } // isTwoAddress = 0
1393 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1394 def XOR8rr : I<0x30, MRMDestReg,
1395 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1396 "xor{b}\t{$src2, $dst|$dst, $src2}",
1397 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>;
1398 def XOR16rr : I<0x31, MRMDestReg,
1399 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1400 "xor{w}\t{$src2, $dst|$dst, $src2}",
1401 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize;
1402 def XOR32rr : I<0x31, MRMDestReg,
1403 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1404 "xor{l}\t{$src2, $dst|$dst, $src2}",
1405 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
1406 } // isCommutable = 1
1408 def XOR8rm : I<0x32, MRMSrcMem ,
1409 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1410 "xor{b}\t{$src2, $dst|$dst, $src2}",
1411 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>;
1412 def XOR16rm : I<0x33, MRMSrcMem ,
1413 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1414 "xor{w}\t{$src2, $dst|$dst, $src2}",
1415 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>,
1417 def XOR32rm : I<0x33, MRMSrcMem ,
1418 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1419 "xor{l}\t{$src2, $dst|$dst, $src2}",
1420 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>;
1422 def XOR8ri : Ii8<0x80, MRM6r,
1423 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1424 "xor{b}\t{$src2, $dst|$dst, $src2}",
1425 [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>;
1426 def XOR16ri : Ii16<0x81, MRM6r,
1427 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1428 "xor{w}\t{$src2, $dst|$dst, $src2}",
1429 [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize;
1430 def XOR32ri : Ii32<0x81, MRM6r,
1431 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1432 "xor{l}\t{$src2, $dst|$dst, $src2}",
1433 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
1434 def XOR16ri8 : Ii8<0x83, MRM6r,
1435 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1436 "xor{w}\t{$src2, $dst|$dst, $src2}",
1437 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>,
1439 def XOR32ri8 : Ii8<0x83, MRM6r,
1440 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1441 "xor{l}\t{$src2, $dst|$dst, $src2}",
1442 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>;
1444 let isTwoAddress = 0 in {
1445 def XOR8mr : I<0x30, MRMDestMem,
1446 (outs), (ins i8mem :$dst, GR8 :$src),
1447 "xor{b}\t{$src, $dst|$dst, $src}",
1448 [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>;
1449 def XOR16mr : I<0x31, MRMDestMem,
1450 (outs), (ins i16mem:$dst, GR16:$src),
1451 "xor{w}\t{$src, $dst|$dst, $src}",
1452 [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>,
1454 def XOR32mr : I<0x31, MRMDestMem,
1455 (outs), (ins i32mem:$dst, GR32:$src),
1456 "xor{l}\t{$src, $dst|$dst, $src}",
1457 [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>;
1458 def XOR8mi : Ii8<0x80, MRM6m,
1459 (outs), (ins i8mem :$dst, i8imm :$src),
1460 "xor{b}\t{$src, $dst|$dst, $src}",
1461 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1462 def XOR16mi : Ii16<0x81, MRM6m,
1463 (outs), (ins i16mem:$dst, i16imm:$src),
1464 "xor{w}\t{$src, $dst|$dst, $src}",
1465 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1467 def XOR32mi : Ii32<0x81, MRM6m,
1468 (outs), (ins i32mem:$dst, i32imm:$src),
1469 "xor{l}\t{$src, $dst|$dst, $src}",
1470 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1471 def XOR16mi8 : Ii8<0x83, MRM6m,
1472 (outs), (ins i16mem:$dst, i16i8imm :$src),
1473 "xor{w}\t{$src, $dst|$dst, $src}",
1474 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1476 def XOR32mi8 : Ii8<0x83, MRM6m,
1477 (outs), (ins i32mem:$dst, i32i8imm :$src),
1478 "xor{l}\t{$src, $dst|$dst, $src}",
1479 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1480 } // isTwoAddress = 0
1481 } // Defs = [EFLAGS]
1483 // Shift instructions
1484 let Defs = [EFLAGS] in {
1485 let Uses = [CL] in {
1486 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1487 "shl{b}\t{%cl, $dst|$dst, %CL}",
1488 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1489 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1490 "shl{w}\t{%cl, $dst|$dst, %CL}",
1491 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1492 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1493 "shl{l}\t{%cl, $dst|$dst, %CL}",
1494 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1497 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1498 "shl{b}\t{$src2, $dst|$dst, $src2}",
1499 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1500 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1501 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1502 "shl{w}\t{$src2, $dst|$dst, $src2}",
1503 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1504 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1505 "shl{l}\t{$src2, $dst|$dst, $src2}",
1506 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1507 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1509 } // isConvertibleToThreeAddress = 1
1511 let isTwoAddress = 0 in {
1512 let Uses = [CL] in {
1513 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1514 "shl{b}\t{%cl, $dst|$dst, %CL}",
1515 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1516 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1517 "shl{w}\t{%cl, $dst|$dst, %CL}",
1518 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1519 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1520 "shl{l}\t{%cl, $dst|$dst, %CL}",
1521 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1523 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1524 "shl{b}\t{$src, $dst|$dst, $src}",
1525 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1526 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1527 "shl{w}\t{$src, $dst|$dst, $src}",
1528 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1530 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1531 "shl{l}\t{$src, $dst|$dst, $src}",
1532 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1535 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1537 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1538 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1540 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1542 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1544 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1547 let Uses = [CL] in {
1548 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1549 "shr{b}\t{%cl, $dst|$dst, %CL}",
1550 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1551 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1552 "shr{w}\t{%cl, $dst|$dst, %CL}",
1553 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1554 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1555 "shr{l}\t{%cl, $dst|$dst, %CL}",
1556 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1559 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1560 "shr{b}\t{$src2, $dst|$dst, $src2}",
1561 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1562 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1563 "shr{w}\t{$src2, $dst|$dst, $src2}",
1564 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1565 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1566 "shr{l}\t{$src2, $dst|$dst, $src2}",
1567 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1570 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1572 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1573 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1575 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1576 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1578 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1580 let isTwoAddress = 0 in {
1581 let Uses = [CL] in {
1582 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1583 "shr{b}\t{%cl, $dst|$dst, %CL}",
1584 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1585 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1586 "shr{w}\t{%cl, $dst|$dst, %CL}",
1587 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1589 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1590 "shr{l}\t{%cl, $dst|$dst, %CL}",
1591 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1593 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1594 "shr{b}\t{$src, $dst|$dst, $src}",
1595 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1596 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1597 "shr{w}\t{$src, $dst|$dst, $src}",
1598 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1600 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1601 "shr{l}\t{$src, $dst|$dst, $src}",
1602 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1605 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1607 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1608 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1610 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1611 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1613 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1616 let Uses = [CL] in {
1617 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1618 "sar{b}\t{%cl, $dst|$dst, %CL}",
1619 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1620 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1621 "sar{w}\t{%cl, $dst|$dst, %CL}",
1622 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1623 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1624 "sar{l}\t{%cl, $dst|$dst, %CL}",
1625 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1628 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1629 "sar{b}\t{$src2, $dst|$dst, $src2}",
1630 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1631 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1632 "sar{w}\t{$src2, $dst|$dst, $src2}",
1633 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1635 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1636 "sar{l}\t{$src2, $dst|$dst, $src2}",
1637 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1640 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1642 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1643 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1645 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1646 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1648 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1650 let isTwoAddress = 0 in {
1651 let Uses = [CL] in {
1652 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1653 "sar{b}\t{%cl, $dst|$dst, %CL}",
1654 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
1655 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1656 "sar{w}\t{%cl, $dst|$dst, %CL}",
1657 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1658 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1659 "sar{l}\t{%cl, $dst|$dst, %CL}",
1660 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1662 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1663 "sar{b}\t{$src, $dst|$dst, $src}",
1664 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1665 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1666 "sar{w}\t{$src, $dst|$dst, $src}",
1667 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1669 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1670 "sar{l}\t{$src, $dst|$dst, $src}",
1671 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1674 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1676 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1677 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1679 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1681 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
1683 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1686 // Rotate instructions
1687 // FIXME: provide shorter instructions when imm8 == 1
1688 let Uses = [CL] in {
1689 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
1690 "rol{b}\t{%cl, $dst|$dst, %CL}",
1691 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
1692 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
1693 "rol{w}\t{%cl, $dst|$dst, %CL}",
1694 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
1695 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
1696 "rol{l}\t{%cl, $dst|$dst, %CL}",
1697 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
1700 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1701 "rol{b}\t{$src2, $dst|$dst, $src2}",
1702 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1703 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1704 "rol{w}\t{$src2, $dst|$dst, $src2}",
1705 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1706 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1707 "rol{l}\t{$src2, $dst|$dst, $src2}",
1708 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1711 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1713 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1714 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
1716 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1717 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1719 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1721 let isTwoAddress = 0 in {
1722 let Uses = [CL] in {
1723 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
1724 "rol{b}\t{%cl, $dst|$dst, %CL}",
1725 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
1726 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
1727 "rol{w}\t{%cl, $dst|$dst, %CL}",
1728 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1729 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
1730 "rol{l}\t{%cl, $dst|$dst, %CL}",
1731 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
1733 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
1734 "rol{b}\t{$src, $dst|$dst, $src}",
1735 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1736 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
1737 "rol{w}\t{$src, $dst|$dst, $src}",
1738 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1740 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
1741 "rol{l}\t{$src, $dst|$dst, $src}",
1742 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1745 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
1747 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1748 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
1750 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1752 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
1754 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1757 let Uses = [CL] in {
1758 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
1759 "ror{b}\t{%cl, $dst|$dst, %CL}",
1760 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
1761 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
1762 "ror{w}\t{%cl, $dst|$dst, %CL}",
1763 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
1764 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
1765 "ror{l}\t{%cl, $dst|$dst, %CL}",
1766 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
1769 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1770 "ror{b}\t{$src2, $dst|$dst, $src2}",
1771 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
1772 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1773 "ror{w}\t{$src2, $dst|$dst, $src2}",
1774 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1775 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1776 "ror{l}\t{$src2, $dst|$dst, $src2}",
1777 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
1780 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1782 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
1783 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
1785 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
1786 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
1788 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
1790 let isTwoAddress = 0 in {
1791 let Uses = [CL] in {
1792 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
1793 "ror{b}\t{%cl, $dst|$dst, %CL}",
1794 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
1795 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
1796 "ror{w}\t{%cl, $dst|$dst, %CL}",
1797 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1798 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
1799 "ror{l}\t{%cl, $dst|$dst, %CL}",
1800 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
1802 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1803 "ror{b}\t{$src, $dst|$dst, $src}",
1804 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1805 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
1806 "ror{w}\t{$src, $dst|$dst, $src}",
1807 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1809 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
1810 "ror{l}\t{$src, $dst|$dst, $src}",
1811 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1814 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
1816 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1817 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
1819 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1821 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
1823 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1828 // Double shift instructions (generalizations of rotate)
1829 let Uses = [CL] in {
1830 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1831 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1832 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
1833 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1834 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1835 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
1836 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1837 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1838 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
1840 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1841 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1842 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
1846 let isCommutable = 1 in { // These instructions commute to each other.
1847 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
1848 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1849 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1850 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
1853 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
1854 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1855 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1856 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
1859 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
1860 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1861 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1862 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
1865 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
1866 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1867 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1868 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
1873 let isTwoAddress = 0 in {
1874 let Uses = [CL] in {
1875 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1876 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1877 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
1879 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1880 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1881 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
1884 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
1885 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1886 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1887 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
1888 (i8 imm:$src3)), addr:$dst)]>,
1890 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
1891 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1892 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1893 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
1894 (i8 imm:$src3)), addr:$dst)]>,
1897 let Uses = [CL] in {
1898 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1899 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1900 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
1901 addr:$dst)]>, TB, OpSize;
1902 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1903 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1904 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
1905 addr:$dst)]>, TB, OpSize;
1907 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
1908 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1909 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1910 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
1911 (i8 imm:$src3)), addr:$dst)]>,
1913 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
1914 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1915 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1916 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
1917 (i8 imm:$src3)), addr:$dst)]>,
1920 } // Defs = [EFLAGS]
1924 let Defs = [EFLAGS] in {
1925 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1926 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
1927 (ins GR8 :$src1, GR8 :$src2),
1928 "add{b}\t{$src2, $dst|$dst, $src2}",
1929 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
1930 (implicit EFLAGS)]>;
1931 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1932 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
1933 (ins GR16:$src1, GR16:$src2),
1934 "add{w}\t{$src2, $dst|$dst, $src2}",
1935 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
1936 (implicit EFLAGS)]>, OpSize;
1937 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
1938 (ins GR32:$src1, GR32:$src2),
1939 "add{l}\t{$src2, $dst|$dst, $src2}",
1940 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
1941 (implicit EFLAGS)]>;
1942 } // end isConvertibleToThreeAddress
1943 } // end isCommutable
1944 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
1945 (ins GR8 :$src1, i8mem :$src2),
1946 "add{b}\t{$src2, $dst|$dst, $src2}",
1947 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
1948 (implicit EFLAGS)]>;
1949 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
1950 (ins GR16:$src1, i16mem:$src2),
1951 "add{w}\t{$src2, $dst|$dst, $src2}",
1952 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
1953 (implicit EFLAGS)]>, OpSize;
1954 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
1955 (ins GR32:$src1, i32mem:$src2),
1956 "add{l}\t{$src2, $dst|$dst, $src2}",
1957 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
1958 (implicit EFLAGS)]>;
1960 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1961 "add{b}\t{$src2, $dst|$dst, $src2}",
1962 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
1963 (implicit EFLAGS)]>;
1965 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1966 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
1967 (ins GR16:$src1, i16imm:$src2),
1968 "add{w}\t{$src2, $dst|$dst, $src2}",
1969 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
1970 (implicit EFLAGS)]>, OpSize;
1971 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
1972 (ins GR32:$src1, i32imm:$src2),
1973 "add{l}\t{$src2, $dst|$dst, $src2}",
1974 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
1975 (implicit EFLAGS)]>;
1976 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
1977 (ins GR16:$src1, i16i8imm:$src2),
1978 "add{w}\t{$src2, $dst|$dst, $src2}",
1979 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
1980 (implicit EFLAGS)]>, OpSize;
1981 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
1982 (ins GR32:$src1, i32i8imm:$src2),
1983 "add{l}\t{$src2, $dst|$dst, $src2}",
1984 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
1985 (implicit EFLAGS)]>;
1988 let isTwoAddress = 0 in {
1989 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1990 "add{b}\t{$src2, $dst|$dst, $src2}",
1991 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
1992 (implicit EFLAGS)]>;
1993 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1994 "add{w}\t{$src2, $dst|$dst, $src2}",
1995 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
1996 (implicit EFLAGS)]>,
1998 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1999 "add{l}\t{$src2, $dst|$dst, $src2}",
2000 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2001 (implicit EFLAGS)]>;
2002 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2003 "add{b}\t{$src2, $dst|$dst, $src2}",
2004 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2005 (implicit EFLAGS)]>;
2006 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2007 "add{w}\t{$src2, $dst|$dst, $src2}",
2008 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2009 (implicit EFLAGS)]>,
2011 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2012 "add{l}\t{$src2, $dst|$dst, $src2}",
2013 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2014 (implicit EFLAGS)]>;
2015 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2016 "add{w}\t{$src2, $dst|$dst, $src2}",
2017 [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst),
2018 (implicit EFLAGS)]>,
2020 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2021 "add{l}\t{$src2, $dst|$dst, $src2}",
2022 [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst),
2023 (implicit EFLAGS)]>;
2026 let Uses = [EFLAGS] in {
2027 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2028 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2029 "adc{l}\t{$src2, $dst|$dst, $src2}",
2030 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2032 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2033 "adc{l}\t{$src2, $dst|$dst, $src2}",
2034 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2035 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2036 "adc{l}\t{$src2, $dst|$dst, $src2}",
2037 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2038 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2039 "adc{l}\t{$src2, $dst|$dst, $src2}",
2040 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2042 let isTwoAddress = 0 in {
2043 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2044 "adc{l}\t{$src2, $dst|$dst, $src2}",
2045 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2046 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2047 "adc{l}\t{$src2, $dst|$dst, $src2}",
2048 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2049 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2050 "adc{l}\t{$src2, $dst|$dst, $src2}",
2051 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2053 } // Uses = [EFLAGS]
2055 def SUB8rr : I<0x28, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
2056 "sub{b}\t{$src2, $dst|$dst, $src2}",
2057 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2058 (implicit EFLAGS)]>;
2059 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2060 "sub{w}\t{$src2, $dst|$dst, $src2}",
2061 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2062 (implicit EFLAGS)]>, OpSize;
2063 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2064 "sub{l}\t{$src2, $dst|$dst, $src2}",
2065 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2066 (implicit EFLAGS)]>;
2067 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
2068 "sub{b}\t{$src2, $dst|$dst, $src2}",
2069 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2070 (implicit EFLAGS)]>;
2071 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2072 "sub{w}\t{$src2, $dst|$dst, $src2}",
2073 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2074 (implicit EFLAGS)]>, OpSize;
2075 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2076 "sub{l}\t{$src2, $dst|$dst, $src2}",
2077 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2078 (implicit EFLAGS)]>;
2080 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2081 "sub{b}\t{$src2, $dst|$dst, $src2}",
2082 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2083 (implicit EFLAGS)]>;
2084 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2085 "sub{w}\t{$src2, $dst|$dst, $src2}",
2086 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2087 (implicit EFLAGS)]>, OpSize;
2088 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2089 "sub{l}\t{$src2, $dst|$dst, $src2}",
2090 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2091 (implicit EFLAGS)]>;
2092 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2093 "sub{w}\t{$src2, $dst|$dst, $src2}",
2094 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2095 (implicit EFLAGS)]>, OpSize;
2096 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2097 "sub{l}\t{$src2, $dst|$dst, $src2}",
2098 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2099 (implicit EFLAGS)]>;
2100 let isTwoAddress = 0 in {
2101 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2102 "sub{b}\t{$src2, $dst|$dst, $src2}",
2103 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2104 (implicit EFLAGS)]>;
2105 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2106 "sub{w}\t{$src2, $dst|$dst, $src2}",
2107 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2108 (implicit EFLAGS)]>, OpSize;
2109 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2110 "sub{l}\t{$src2, $dst|$dst, $src2}",
2111 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2112 (implicit EFLAGS)]>;
2113 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2114 "sub{b}\t{$src2, $dst|$dst, $src2}",
2115 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2116 (implicit EFLAGS)]>;
2117 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2118 "sub{w}\t{$src2, $dst|$dst, $src2}",
2119 [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst),
2120 (implicit EFLAGS)]>, OpSize;
2121 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2122 "sub{l}\t{$src2, $dst|$dst, $src2}",
2123 [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst),
2124 (implicit EFLAGS)]>;
2125 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2126 "sub{w}\t{$src2, $dst|$dst, $src2}",
2127 [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst),
2128 (implicit EFLAGS)]>, OpSize;
2129 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2130 "sub{l}\t{$src2, $dst|$dst, $src2}",
2131 [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst),
2132 (implicit EFLAGS)]>;
2135 let Uses = [EFLAGS] in {
2136 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2137 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2138 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2140 let isTwoAddress = 0 in {
2141 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2142 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2143 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2144 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2145 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2146 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2147 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2148 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2149 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2150 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2151 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2152 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2154 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2155 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2156 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2157 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2158 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2159 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2160 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2161 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2162 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2163 } // Uses = [EFLAGS]
2164 } // Defs = [EFLAGS]
2166 let Defs = [EFLAGS] in {
2167 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2168 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2169 "imul{w}\t{$src2, $dst|$dst, $src2}",
2170 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
2171 (implicit EFLAGS)]>, TB, OpSize;
2172 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2173 "imul{l}\t{$src2, $dst|$dst, $src2}",
2174 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
2175 (implicit EFLAGS)]>, TB;
2177 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2178 "imul{w}\t{$src2, $dst|$dst, $src2}",
2179 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
2180 (implicit EFLAGS)]>,
2182 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2183 "imul{l}\t{$src2, $dst|$dst, $src2}",
2184 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
2185 (implicit EFLAGS)]>, TB;
2186 } // Defs = [EFLAGS]
2187 } // end Two Address instructions
2189 // Suprisingly enough, these are not two address instructions!
2190 let Defs = [EFLAGS] in {
2191 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2192 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2193 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2194 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
2195 (implicit EFLAGS)]>, OpSize;
2196 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2197 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2198 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2199 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
2200 (implicit EFLAGS)]>;
2201 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2202 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2203 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2204 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
2205 (implicit EFLAGS)]>, OpSize;
2206 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2207 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2208 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2209 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
2210 (implicit EFLAGS)]>;
2212 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2213 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2214 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2215 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
2216 (implicit EFLAGS)]>, OpSize;
2217 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2218 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2219 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2220 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
2221 (implicit EFLAGS)]>;
2222 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2223 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2224 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2225 [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2)),
2226 (implicit EFLAGS)]>, OpSize;
2227 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2228 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2229 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2230 [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2)),
2231 (implicit EFLAGS)]>;
2232 } // Defs = [EFLAGS]
2234 //===----------------------------------------------------------------------===//
2235 // Test instructions are just like AND, except they don't generate a result.
2237 let Defs = [EFLAGS] in {
2238 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2239 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2240 "test{b}\t{$src2, $src1|$src1, $src2}",
2241 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
2242 (implicit EFLAGS)]>;
2243 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2244 "test{w}\t{$src2, $src1|$src1, $src2}",
2245 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
2246 (implicit EFLAGS)]>,
2248 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2249 "test{l}\t{$src2, $src1|$src1, $src2}",
2250 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
2251 (implicit EFLAGS)]>;
2254 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2255 "test{b}\t{$src2, $src1|$src1, $src2}",
2256 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2257 (implicit EFLAGS)]>;
2258 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2259 "test{w}\t{$src2, $src1|$src1, $src2}",
2260 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2261 (implicit EFLAGS)]>, OpSize;
2262 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2263 "test{l}\t{$src2, $src1|$src1, $src2}",
2264 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2265 (implicit EFLAGS)]>;
2267 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2268 (outs), (ins GR8:$src1, i8imm:$src2),
2269 "test{b}\t{$src2, $src1|$src1, $src2}",
2270 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
2271 (implicit EFLAGS)]>;
2272 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2273 (outs), (ins GR16:$src1, i16imm:$src2),
2274 "test{w}\t{$src2, $src1|$src1, $src2}",
2275 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
2276 (implicit EFLAGS)]>, OpSize;
2277 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2278 (outs), (ins GR32:$src1, i32imm:$src2),
2279 "test{l}\t{$src2, $src1|$src1, $src2}",
2280 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
2281 (implicit EFLAGS)]>;
2283 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2284 (outs), (ins i8mem:$src1, i8imm:$src2),
2285 "test{b}\t{$src2, $src1|$src1, $src2}",
2286 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2287 (implicit EFLAGS)]>;
2288 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2289 (outs), (ins i16mem:$src1, i16imm:$src2),
2290 "test{w}\t{$src2, $src1|$src1, $src2}",
2291 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2292 (implicit EFLAGS)]>, OpSize;
2293 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2294 (outs), (ins i32mem:$src1, i32imm:$src2),
2295 "test{l}\t{$src2, $src1|$src1, $src2}",
2296 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2297 (implicit EFLAGS)]>;
2298 } // Defs = [EFLAGS]
2301 // Condition code ops, incl. set if equal/not equal/...
2302 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2303 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2304 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2305 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2307 let Uses = [EFLAGS] in {
2308 def SETEr : I<0x94, MRM0r,
2309 (outs GR8 :$dst), (ins),
2311 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2313 def SETEm : I<0x94, MRM0m,
2314 (outs), (ins i8mem:$dst),
2316 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2319 def SETNEr : I<0x95, MRM0r,
2320 (outs GR8 :$dst), (ins),
2322 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2324 def SETNEm : I<0x95, MRM0m,
2325 (outs), (ins i8mem:$dst),
2327 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2330 def SETLr : I<0x9C, MRM0r,
2331 (outs GR8 :$dst), (ins),
2333 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2334 TB; // GR8 = < signed
2335 def SETLm : I<0x9C, MRM0m,
2336 (outs), (ins i8mem:$dst),
2338 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2339 TB; // [mem8] = < signed
2341 def SETGEr : I<0x9D, MRM0r,
2342 (outs GR8 :$dst), (ins),
2344 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2345 TB; // GR8 = >= signed
2346 def SETGEm : I<0x9D, MRM0m,
2347 (outs), (ins i8mem:$dst),
2349 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2350 TB; // [mem8] = >= signed
2352 def SETLEr : I<0x9E, MRM0r,
2353 (outs GR8 :$dst), (ins),
2355 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2356 TB; // GR8 = <= signed
2357 def SETLEm : I<0x9E, MRM0m,
2358 (outs), (ins i8mem:$dst),
2360 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2361 TB; // [mem8] = <= signed
2363 def SETGr : I<0x9F, MRM0r,
2364 (outs GR8 :$dst), (ins),
2366 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2367 TB; // GR8 = > signed
2368 def SETGm : I<0x9F, MRM0m,
2369 (outs), (ins i8mem:$dst),
2371 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2372 TB; // [mem8] = > signed
2374 def SETBr : I<0x92, MRM0r,
2375 (outs GR8 :$dst), (ins),
2377 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2378 TB; // GR8 = < unsign
2379 def SETBm : I<0x92, MRM0m,
2380 (outs), (ins i8mem:$dst),
2382 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
2383 TB; // [mem8] = < unsign
2385 def SETAEr : I<0x93, MRM0r,
2386 (outs GR8 :$dst), (ins),
2388 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
2389 TB; // GR8 = >= unsign
2390 def SETAEm : I<0x93, MRM0m,
2391 (outs), (ins i8mem:$dst),
2393 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
2394 TB; // [mem8] = >= unsign
2396 def SETBEr : I<0x96, MRM0r,
2397 (outs GR8 :$dst), (ins),
2399 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
2400 TB; // GR8 = <= unsign
2401 def SETBEm : I<0x96, MRM0m,
2402 (outs), (ins i8mem:$dst),
2404 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
2405 TB; // [mem8] = <= unsign
2407 def SETAr : I<0x97, MRM0r,
2408 (outs GR8 :$dst), (ins),
2410 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
2411 TB; // GR8 = > signed
2412 def SETAm : I<0x97, MRM0m,
2413 (outs), (ins i8mem:$dst),
2415 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
2416 TB; // [mem8] = > signed
2418 def SETSr : I<0x98, MRM0r,
2419 (outs GR8 :$dst), (ins),
2421 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
2422 TB; // GR8 = <sign bit>
2423 def SETSm : I<0x98, MRM0m,
2424 (outs), (ins i8mem:$dst),
2426 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
2427 TB; // [mem8] = <sign bit>
2428 def SETNSr : I<0x99, MRM0r,
2429 (outs GR8 :$dst), (ins),
2431 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
2432 TB; // GR8 = !<sign bit>
2433 def SETNSm : I<0x99, MRM0m,
2434 (outs), (ins i8mem:$dst),
2436 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
2437 TB; // [mem8] = !<sign bit>
2439 def SETPr : I<0x9A, MRM0r,
2440 (outs GR8 :$dst), (ins),
2442 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
2444 def SETPm : I<0x9A, MRM0m,
2445 (outs), (ins i8mem:$dst),
2447 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
2448 TB; // [mem8] = parity
2449 def SETNPr : I<0x9B, MRM0r,
2450 (outs GR8 :$dst), (ins),
2452 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
2453 TB; // GR8 = not parity
2454 def SETNPm : I<0x9B, MRM0m,
2455 (outs), (ins i8mem:$dst),
2457 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
2458 TB; // [mem8] = not parity
2460 def SETOr : I<0x90, MRM0r,
2461 (outs GR8 :$dst), (ins),
2463 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
2464 TB; // GR8 = overflow
2465 def SETOm : I<0x90, MRM0m,
2466 (outs), (ins i8mem:$dst),
2468 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
2469 TB; // [mem8] = overflow
2470 def SETNOr : I<0x91, MRM0r,
2471 (outs GR8 :$dst), (ins),
2473 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
2474 TB; // GR8 = not overflow
2475 def SETNOm : I<0x91, MRM0m,
2476 (outs), (ins i8mem:$dst),
2478 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
2479 TB; // [mem8] = not overflow
2481 def SETCr : I<0x92, MRM0r,
2482 (outs GR8 :$dst), (ins),
2484 [(set GR8:$dst, (X86setcc X86_COND_C, EFLAGS))]>,
2486 def SETCm : I<0x92, MRM0m,
2487 (outs), (ins i8mem:$dst),
2489 [(store (X86setcc X86_COND_C, EFLAGS), addr:$dst)]>,
2490 TB; // [mem8] = carry
2491 def SETNCr : I<0x93, MRM0r,
2492 (outs GR8 :$dst), (ins),
2494 [(set GR8:$dst, (X86setcc X86_COND_NC, EFLAGS))]>,
2495 TB; // GR8 = not carry
2496 def SETNCm : I<0x93, MRM0m,
2497 (outs), (ins i8mem:$dst),
2499 [(store (X86setcc X86_COND_NC, EFLAGS), addr:$dst)]>,
2500 TB; // [mem8] = not carry
2501 } // Uses = [EFLAGS]
2504 // Integer comparisons
2505 let Defs = [EFLAGS] in {
2506 def CMP8rr : I<0x38, MRMDestReg,
2507 (outs), (ins GR8 :$src1, GR8 :$src2),
2508 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2509 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2510 def CMP16rr : I<0x39, MRMDestReg,
2511 (outs), (ins GR16:$src1, GR16:$src2),
2512 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2513 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
2514 def CMP32rr : I<0x39, MRMDestReg,
2515 (outs), (ins GR32:$src1, GR32:$src2),
2516 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2517 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
2518 def CMP8mr : I<0x38, MRMDestMem,
2519 (outs), (ins i8mem :$src1, GR8 :$src2),
2520 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2521 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
2522 (implicit EFLAGS)]>;
2523 def CMP16mr : I<0x39, MRMDestMem,
2524 (outs), (ins i16mem:$src1, GR16:$src2),
2525 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2526 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
2527 (implicit EFLAGS)]>, OpSize;
2528 def CMP32mr : I<0x39, MRMDestMem,
2529 (outs), (ins i32mem:$src1, GR32:$src2),
2530 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2531 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
2532 (implicit EFLAGS)]>;
2533 def CMP8rm : I<0x3A, MRMSrcMem,
2534 (outs), (ins GR8 :$src1, i8mem :$src2),
2535 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2536 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
2537 (implicit EFLAGS)]>;
2538 def CMP16rm : I<0x3B, MRMSrcMem,
2539 (outs), (ins GR16:$src1, i16mem:$src2),
2540 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2541 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
2542 (implicit EFLAGS)]>, OpSize;
2543 def CMP32rm : I<0x3B, MRMSrcMem,
2544 (outs), (ins GR32:$src1, i32mem:$src2),
2545 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2546 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
2547 (implicit EFLAGS)]>;
2548 def CMP8ri : Ii8<0x80, MRM7r,
2549 (outs), (ins GR8:$src1, i8imm:$src2),
2550 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2551 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
2552 def CMP16ri : Ii16<0x81, MRM7r,
2553 (outs), (ins GR16:$src1, i16imm:$src2),
2554 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2555 [(X86cmp GR16:$src1, imm:$src2),
2556 (implicit EFLAGS)]>, OpSize;
2557 def CMP32ri : Ii32<0x81, MRM7r,
2558 (outs), (ins GR32:$src1, i32imm:$src2),
2559 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2560 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
2561 def CMP8mi : Ii8 <0x80, MRM7m,
2562 (outs), (ins i8mem :$src1, i8imm :$src2),
2563 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2564 [(X86cmp (loadi8 addr:$src1), imm:$src2),
2565 (implicit EFLAGS)]>;
2566 def CMP16mi : Ii16<0x81, MRM7m,
2567 (outs), (ins i16mem:$src1, i16imm:$src2),
2568 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2569 [(X86cmp (loadi16 addr:$src1), imm:$src2),
2570 (implicit EFLAGS)]>, OpSize;
2571 def CMP32mi : Ii32<0x81, MRM7m,
2572 (outs), (ins i32mem:$src1, i32imm:$src2),
2573 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2574 [(X86cmp (loadi32 addr:$src1), imm:$src2),
2575 (implicit EFLAGS)]>;
2576 def CMP16ri8 : Ii8<0x83, MRM7r,
2577 (outs), (ins GR16:$src1, i16i8imm:$src2),
2578 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2579 [(X86cmp GR16:$src1, i16immSExt8:$src2),
2580 (implicit EFLAGS)]>, OpSize;
2581 def CMP16mi8 : Ii8<0x83, MRM7m,
2582 (outs), (ins i16mem:$src1, i16i8imm:$src2),
2583 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2584 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
2585 (implicit EFLAGS)]>, OpSize;
2586 def CMP32mi8 : Ii8<0x83, MRM7m,
2587 (outs), (ins i32mem:$src1, i32i8imm:$src2),
2588 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2589 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
2590 (implicit EFLAGS)]>;
2591 def CMP32ri8 : Ii8<0x83, MRM7r,
2592 (outs), (ins GR32:$src1, i32i8imm:$src2),
2593 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2594 [(X86cmp GR32:$src1, i32immSExt8:$src2),
2595 (implicit EFLAGS)]>;
2596 } // Defs = [EFLAGS]
2598 // Sign/Zero extenders
2599 // Use movsbl intead of movsbw; we don't care about the high 16 bits
2600 // of the register here. This has a smaller encoding and avoids a
2601 // partial-register update.
2602 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2603 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2604 [(set GR16:$dst, (sext GR8:$src))]>, TB;
2605 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2606 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2607 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
2608 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2609 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2610 [(set GR32:$dst, (sext GR8:$src))]>, TB;
2611 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2612 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2613 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
2614 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2615 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2616 [(set GR32:$dst, (sext GR16:$src))]>, TB;
2617 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2618 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2619 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
2621 // Use movzbl intead of movzbw; we don't care about the high 16 bits
2622 // of the register here. This has a smaller encoding and avoids a
2623 // partial-register update.
2624 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2625 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2626 [(set GR16:$dst, (zext GR8:$src))]>, TB;
2627 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2628 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2629 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
2630 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2631 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2632 [(set GR32:$dst, (zext GR8:$src))]>, TB;
2633 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2634 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2635 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
2636 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2637 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2638 [(set GR32:$dst, (zext GR16:$src))]>, TB;
2639 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2640 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2641 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
2643 let neverHasSideEffects = 1 in {
2644 let Defs = [AX], Uses = [AL] in
2645 def CBW : I<0x98, RawFrm, (outs), (ins),
2646 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
2647 let Defs = [EAX], Uses = [AX] in
2648 def CWDE : I<0x98, RawFrm, (outs), (ins),
2649 "{cwtl|cwde}", []>; // EAX = signext(AX)
2651 let Defs = [AX,DX], Uses = [AX] in
2652 def CWD : I<0x99, RawFrm, (outs), (ins),
2653 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
2654 let Defs = [EAX,EDX], Uses = [EAX] in
2655 def CDQ : I<0x99, RawFrm, (outs), (ins),
2656 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
2659 //===----------------------------------------------------------------------===//
2660 // Alias Instructions
2661 //===----------------------------------------------------------------------===//
2663 // Alias instructions that map movr0 to xor.
2664 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2665 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1 in {
2666 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
2667 "xor{b}\t$dst, $dst",
2668 [(set GR8:$dst, 0)]>;
2669 // Use xorl instead of xorw since we don't care about the high 16 bits,
2670 // it's smaller, and it avoids a partial-register update.
2671 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
2672 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
2673 [(set GR16:$dst, 0)]>;
2674 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
2675 "xor{l}\t$dst, $dst",
2676 [(set GR32:$dst, 0)]>;
2679 // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
2680 // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
2681 let neverHasSideEffects = 1 in {
2682 def MOV16to16_ : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16:$src),
2683 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2684 def MOV32to32_ : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32:$src),
2685 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2687 def MOV16_rr : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16_:$src),
2688 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2689 def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src),
2690 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2691 } // neverHasSideEffects
2693 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
2694 def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src),
2695 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2696 def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src),
2697 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2699 let mayStore = 1, neverHasSideEffects = 1 in {
2700 def MOV16_mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16_:$src),
2701 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2702 def MOV32_mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32_:$src),
2703 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2706 //===----------------------------------------------------------------------===//
2707 // Thread Local Storage Instructions
2711 def TLS_addr32 : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
2712 "leal\t${sym:mem}(,%ebx,1), $dst",
2713 [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
2715 let AddedComplexity = 10 in
2716 def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
2717 "movl\t%gs:($src), $dst",
2718 [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
2720 let AddedComplexity = 15 in
2721 def TLS_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
2722 "movl\t%gs:${src:mem}, $dst",
2724 (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>,
2727 def TLS_tp : I<0x8B, Pseudo, (outs GR32:$dst), (ins),
2728 "movl\t%gs:0, $dst",
2729 [(set GR32:$dst, X86TLStp)]>, SegGS;
2731 //===----------------------------------------------------------------------===//
2732 // DWARF Pseudo Instructions
2735 def DWARF_LOC : I<0, Pseudo, (outs),
2736 (ins i32imm:$line, i32imm:$col, i32imm:$file),
2737 ".loc\t${file:debug} ${line:debug} ${col:debug}",
2738 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
2741 //===----------------------------------------------------------------------===//
2742 // EH Pseudo Instructions
2744 let isTerminator = 1, isReturn = 1, isBarrier = 1,
2746 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
2747 "ret\t#eh_return, addr: $addr",
2748 [(X86ehret GR32:$addr)]>;
2752 //===----------------------------------------------------------------------===//
2756 // Atomic swap. These are just normal xchg instructions. But since a memory
2757 // operand is referenced, the atomicity is ensured.
2758 let Constraints = "$val = $dst" in {
2759 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2760 "xchg{l}\t{$val, $ptr|$ptr, $val}",
2761 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
2762 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2763 "xchg{w}\t{$val, $ptr|$ptr, $val}",
2764 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
2766 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2767 "xchg{b}\t{$val, $ptr|$ptr, $val}",
2768 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
2771 // Atomic compare and swap.
2772 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
2773 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
2774 "lock\n\tcmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
2775 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
2777 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
2778 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
2779 "lock\n\tcmpxchg8b\t$ptr",
2780 [(X86cas8 addr:$ptr)]>, TB, LOCK;
2783 let Defs = [AX, EFLAGS], Uses = [AX] in {
2784 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
2785 "lock\n\tcmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
2786 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
2788 let Defs = [AL, EFLAGS], Uses = [AL] in {
2789 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
2790 "lock\n\tcmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
2791 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
2794 // Atomic exchange and add
2795 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
2796 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2797 "lock\n\txadd{l}\t{$val, $ptr|$ptr, $val}",
2798 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
2800 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2801 "lock\n\txadd{w}\t{$val, $ptr|$ptr, $val}",
2802 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
2804 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
2805 "lock\n\txadd{b}\t{$val, $ptr|$ptr, $val}",
2806 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
2810 // Atomic exchange, and, or, xor
2811 let Constraints = "$val = $dst", Defs = [EFLAGS],
2812 usesCustomDAGSchedInserter = 1 in {
2813 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2814 "#ATOMAND32 PSEUDO!",
2815 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
2816 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2817 "#ATOMOR32 PSEUDO!",
2818 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
2819 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2820 "#ATOMXOR32 PSEUDO!",
2821 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
2822 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2823 "#ATOMNAND32 PSEUDO!",
2824 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
2825 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2826 "#ATOMMIN32 PSEUDO!",
2827 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
2828 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2829 "#ATOMMAX32 PSEUDO!",
2830 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
2831 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2832 "#ATOMUMIN32 PSEUDO!",
2833 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
2834 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
2835 "#ATOMUMAX32 PSEUDO!",
2836 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
2838 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2839 "#ATOMAND16 PSEUDO!",
2840 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
2841 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2842 "#ATOMOR16 PSEUDO!",
2843 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
2844 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2845 "#ATOMXOR16 PSEUDO!",
2846 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
2847 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2848 "#ATOMNAND16 PSEUDO!",
2849 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
2850 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2851 "#ATOMMIN16 PSEUDO!",
2852 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
2853 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2854 "#ATOMMAX16 PSEUDO!",
2855 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
2856 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2857 "#ATOMUMIN16 PSEUDO!",
2858 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
2859 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
2860 "#ATOMUMAX16 PSEUDO!",
2861 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
2863 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
2864 "#ATOMAND8 PSEUDO!",
2865 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
2866 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
2868 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
2869 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
2870 "#ATOMXOR8 PSEUDO!",
2871 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
2872 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
2873 "#ATOMNAND8 PSEUDO!",
2874 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
2877 let Constraints = "$val1 = $dst1, $val2 = $dst2",
2878 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
2879 Uses = [EAX, EBX, ECX, EDX],
2880 mayLoad = 1, mayStore = 1,
2881 usesCustomDAGSchedInserter = 1 in {
2882 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2883 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2884 "#ATOMAND6432 PSEUDO!", []>;
2885 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2886 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2887 "#ATOMOR6432 PSEUDO!", []>;
2888 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2889 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2890 "#ATOMXOR6432 PSEUDO!", []>;
2891 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2892 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2893 "#ATOMNAND6432 PSEUDO!", []>;
2894 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2895 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2896 "#ATOMADD6432 PSEUDO!", []>;
2897 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2898 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2899 "#ATOMSUB6432 PSEUDO!", []>;
2900 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
2901 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
2902 "#ATOMSWAP6432 PSEUDO!", []>;
2905 //===----------------------------------------------------------------------===//
2906 // Non-Instruction Patterns
2907 //===----------------------------------------------------------------------===//
2909 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
2910 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
2911 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
2912 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
2913 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
2914 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
2916 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
2917 (ADD32ri GR32:$src1, tconstpool:$src2)>;
2918 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
2919 (ADD32ri GR32:$src1, tjumptable:$src2)>;
2920 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
2921 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
2922 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
2923 (ADD32ri GR32:$src1, texternalsym:$src2)>;
2925 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
2926 (MOV32mi addr:$dst, tglobaladdr:$src)>;
2927 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
2928 (MOV32mi addr:$dst, texternalsym:$src)>;
2932 def : Pat<(X86tailcall GR32:$dst),
2935 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
2937 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
2940 def : Pat<(X86tcret GR32:$dst, imm:$off),
2941 (TCRETURNri GR32:$dst, imm:$off)>;
2943 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
2944 (TCRETURNdi texternalsym:$dst, imm:$off)>;
2946 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
2947 (TCRETURNdi texternalsym:$dst, imm:$off)>;
2949 def : Pat<(X86call (i32 tglobaladdr:$dst)),
2950 (CALLpcrel32 tglobaladdr:$dst)>;
2951 def : Pat<(X86call (i32 texternalsym:$dst)),
2952 (CALLpcrel32 texternalsym:$dst)>;
2954 // X86 specific add which produces a flag.
2955 def : Pat<(addc GR32:$src1, GR32:$src2),
2956 (ADD32rr GR32:$src1, GR32:$src2)>;
2957 def : Pat<(addc GR32:$src1, (load addr:$src2)),
2958 (ADD32rm GR32:$src1, addr:$src2)>;
2959 def : Pat<(addc GR32:$src1, imm:$src2),
2960 (ADD32ri GR32:$src1, imm:$src2)>;
2961 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
2962 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
2964 def : Pat<(subc GR32:$src1, GR32:$src2),
2965 (SUB32rr GR32:$src1, GR32:$src2)>;
2966 def : Pat<(subc GR32:$src1, (load addr:$src2)),
2967 (SUB32rm GR32:$src1, addr:$src2)>;
2968 def : Pat<(subc GR32:$src1, imm:$src2),
2969 (SUB32ri GR32:$src1, imm:$src2)>;
2970 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
2971 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
2975 // TEST R,R is smaller than CMP R,0
2976 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
2977 (TEST8rr GR8:$src1, GR8:$src1)>;
2978 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
2979 (TEST16rr GR16:$src1, GR16:$src1)>;
2980 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
2981 (TEST32rr GR32:$src1, GR32:$src1)>;
2983 // zextload bool -> zextload byte
2984 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2985 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2986 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2988 // extload bool -> extload byte
2989 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2990 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>,
2991 Requires<[In32BitMode]>;
2992 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2993 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>,
2994 Requires<[In32BitMode]>;
2995 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
2996 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
2999 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>,
3000 Requires<[In32BitMode]>;
3001 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>,
3002 Requires<[In32BitMode]>;
3003 def : Pat<(i32 (anyext GR16:$src)),
3004 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
3006 // (and (i32 load), 255) -> (zextload i8)
3007 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
3008 (MOVZX32rm8 addr:$src)>;
3009 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
3010 (MOVZX32rm16 addr:$src)>;
3012 //===----------------------------------------------------------------------===//
3014 //===----------------------------------------------------------------------===//
3016 // Odd encoding trick: -128 fits into an 8-bit immediate field while
3017 // +128 doesn't, so in this special case use a sub instead of an add.
3018 def : Pat<(add GR16:$src1, 128),
3019 (SUB16ri8 GR16:$src1, -128)>;
3020 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
3021 (SUB16mi8 addr:$dst, -128)>;
3022 def : Pat<(add GR32:$src1, 128),
3023 (SUB32ri8 GR32:$src1, -128)>;
3024 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
3025 (SUB32mi8 addr:$dst, -128)>;
3027 // r & (2^16-1) ==> movz
3028 def : Pat<(and GR32:$src1, 0xffff),
3029 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit)))>;
3030 // r & (2^8-1) ==> movz
3031 def : Pat<(and GR32:$src1, 0xff),
3032 (MOVZX32rr8 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src1),
3033 x86_subreg_8bit)))>,
3034 Requires<[In32BitMode]>;
3035 // r & (2^8-1) ==> movz
3036 def : Pat<(and GR16:$src1, 0xff),
3037 (MOVZX16rr8 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src1),
3038 x86_subreg_8bit)))>,
3039 Requires<[In32BitMode]>;
3041 // sext_inreg patterns
3042 def : Pat<(sext_inreg GR32:$src, i16),
3043 (MOVSX32rr16 (i16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)))>;
3044 def : Pat<(sext_inreg GR32:$src, i8),
3045 (MOVSX32rr8 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src),
3046 x86_subreg_8bit)))>,
3047 Requires<[In32BitMode]>;
3048 def : Pat<(sext_inreg GR16:$src, i8),
3049 (MOVSX16rr8 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src),
3050 x86_subreg_8bit)))>,
3051 Requires<[In32BitMode]>;
3054 def : Pat<(i16 (trunc GR32:$src)),
3055 (i16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
3056 def : Pat<(i8 (trunc GR32:$src)),
3057 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src), x86_subreg_8bit))>,
3058 Requires<[In32BitMode]>;
3059 def : Pat<(i8 (trunc GR16:$src)),
3060 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src), x86_subreg_8bit))>,
3061 Requires<[In32BitMode]>;
3063 // (shl x, 1) ==> (add x, x)
3064 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
3065 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
3066 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
3068 // (shl x (and y, 31)) ==> (shl x, y)
3069 def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
3070 (SHL8rCL GR8:$src1)>;
3071 def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
3072 (SHL16rCL GR16:$src1)>;
3073 def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
3074 (SHL32rCL GR32:$src1)>;
3075 def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3076 (SHL8mCL addr:$dst)>;
3077 def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3078 (SHL16mCL addr:$dst)>;
3079 def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3080 (SHL32mCL addr:$dst)>;
3082 def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
3083 (SHR8rCL GR8:$src1)>;
3084 def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
3085 (SHR16rCL GR16:$src1)>;
3086 def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
3087 (SHR32rCL GR32:$src1)>;
3088 def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3089 (SHR8mCL addr:$dst)>;
3090 def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3091 (SHR16mCL addr:$dst)>;
3092 def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3093 (SHR32mCL addr:$dst)>;
3095 def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
3096 (SAR8rCL GR8:$src1)>;
3097 def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
3098 (SAR16rCL GR16:$src1)>;
3099 def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
3100 (SAR32rCL GR32:$src1)>;
3101 def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3102 (SAR8mCL addr:$dst)>;
3103 def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3104 (SAR16mCL addr:$dst)>;
3105 def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3106 (SAR32mCL addr:$dst)>;
3108 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
3109 def : Pat<(or (srl GR32:$src1, CL:$amt),
3110 (shl GR32:$src2, (sub 32, CL:$amt))),
3111 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3113 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
3114 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3115 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3117 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
3118 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3119 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3121 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3122 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3124 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3126 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3127 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3129 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
3130 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3131 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3133 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
3134 def : Pat<(or (shl GR32:$src1, CL:$amt),
3135 (srl GR32:$src2, (sub 32, CL:$amt))),
3136 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3138 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
3139 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3140 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3142 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
3143 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3144 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3146 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3147 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3149 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3151 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3152 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3154 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
3155 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3156 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3158 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
3159 def : Pat<(or (srl GR16:$src1, CL:$amt),
3160 (shl GR16:$src2, (sub 16, CL:$amt))),
3161 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3163 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
3164 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3165 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3167 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
3168 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3169 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3171 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3172 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3174 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3176 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3177 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3179 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
3180 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3181 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3183 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
3184 def : Pat<(or (shl GR16:$src1, CL:$amt),
3185 (srl GR16:$src2, (sub 16, CL:$amt))),
3186 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3188 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
3189 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3190 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3192 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
3193 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3194 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3196 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3197 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3199 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3201 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3202 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3204 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
3205 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3206 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3208 //===----------------------------------------------------------------------===//
3209 // Floating Point Stack Support
3210 //===----------------------------------------------------------------------===//
3212 include "X86InstrFPStack.td"
3214 //===----------------------------------------------------------------------===//
3216 //===----------------------------------------------------------------------===//
3218 include "X86Instr64bit.td"
3220 //===----------------------------------------------------------------------===//
3221 // XMM Floating point support (requires SSE / SSE2)
3222 //===----------------------------------------------------------------------===//
3224 include "X86InstrSSE.td"
3226 //===----------------------------------------------------------------------===//
3227 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
3228 //===----------------------------------------------------------------------===//
3230 include "X86InstrMMX.td"