1 //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Format specifies the encoding used by the instruction. This is part of the
17 // ad-hoc solution used to emit machine instruction encodings by our machine
19 class Format<bits<5> val> {
23 def Pseudo : Format<0>; def RawFrm : Format<1>;
24 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
25 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
26 def MRMSrcMem : Format<6>;
27 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
28 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
29 def MRM6r : Format<22>; def MRM7r : Format<23>;
30 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
31 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
32 def MRM6m : Format<30>; def MRM7m : Format<31>;
34 // ImmType - This specifies the immediate type used by an instruction. This is
35 // part of the ad-hoc solution used to emit machine instruction encodings by our
36 // machine code emitter.
37 class ImmType<bits<2> val> {
40 def NoImm : ImmType<0>;
41 def Imm8 : ImmType<1>;
42 def Imm16 : ImmType<2>;
43 def Imm32 : ImmType<3>;
45 // MemType - This specifies the immediate type used by an instruction. This is
46 // part of the ad-hoc solution used to emit machine instruction encodings by our
47 // machine code emitter.
48 class MemType<bits<3> val> {
51 def NoMem : MemType<0>;
52 def Mem8 : MemType<1>;
53 def Mem16 : MemType<2>;
54 def Mem32 : MemType<3>;
55 def Mem64 : MemType<4>;
56 def Mem80 : MemType<4>;
57 def Mem128 : MemType<6>;
59 // FPFormat - This specifies what form this FP instruction has. This is used by
60 // the Floating-Point stackifier pass.
61 class FPFormat<bits<3> val> {
64 def NotFP : FPFormat<0>;
65 def ZeroArgFP : FPFormat<1>;
66 def OneArgFP : FPFormat<2>;
67 def OneArgFPRW : FPFormat<3>;
68 def TwoArgFP : FPFormat<4>;
69 def SpecialFP : FPFormat<5>;
72 class X86Inst<string nam, bits<8> opcod, Format f, MemType m, ImmType i> : Instruction {
73 let Namespace = "X86";
76 bits<8> Opcode = opcod;
78 bits<5> FormBits = Form.Value;
80 bits<3> MemTypeBits = MemT.Value;
82 bits<2> ImmTypeBits = ImmT.Value;
84 // Attributes specific to X86 instructions...
85 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
86 bit printImplicitUses = 0; // Should we print implicit uses of this inst?
88 bits<4> Prefix = 0; // Which prefix byte does this inst have?
89 FPFormat FPForm; // What flavor of FP instruction is this?
90 bits<3> FPFormBits = 0;
93 class Imp<list<Register> uses, list<Register> defs> {
94 list<Register> Uses = uses;
95 list<Register> Defs = defs;
98 class Pattern<dag P> {
103 // Prefix byte classes which are used to indicate to the ad-hoc machine code
104 // emitter that various prefix bytes are required.
105 class OpSize { bit hasOpSizePrefix = 1; }
106 class TB { bits<4> Prefix = 1; }
107 class REP { bits<4> Prefix = 2; }
108 class D8 { bits<4> Prefix = 3; }
109 class D9 { bits<4> Prefix = 4; }
110 class DA { bits<4> Prefix = 5; }
111 class DB { bits<4> Prefix = 6; }
112 class DC { bits<4> Prefix = 7; }
113 class DD { bits<4> Prefix = 8; }
114 class DE { bits<4> Prefix = 9; }
115 class DF { bits<4> Prefix = 10; }
118 //===----------------------------------------------------------------------===//
119 // Instruction templates...
121 class I<string n, bits<8> o, Format f> : X86Inst<n, o, f, NoMem, NoImm>;
123 class Im<string n, bits<8> o, Format f, MemType m> : X86Inst<n, o, f, m, NoImm>;
124 class Im8 <string n, bits<8> o, Format f> : Im<n, o, f, Mem8 >;
125 class Im16<string n, bits<8> o, Format f> : Im<n, o, f, Mem16>;
126 class Im32<string n, bits<8> o, Format f> : Im<n, o, f, Mem32>;
128 class Ii<string n, bits<8> o, Format f, ImmType i> : X86Inst<n, o, f, NoMem, i>;
129 class Ii8 <string n, bits<8> o, Format f> : Ii<n, o, f, Imm8 >;
130 class Ii16<string n, bits<8> o, Format f> : Ii<n, o, f, Imm16>;
131 class Ii32<string n, bits<8> o, Format f> : Ii<n, o, f, Imm32>;
133 class Im8i8 <string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem8 , Imm8 >;
134 class Im16i16<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem16, Imm16>;
135 class Im32i32<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem32, Imm32>;
137 class Im16i8<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem16, Imm8>;
138 class Im32i8<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem32, Imm8>;
140 // Helper for shift instructions
141 class UsesCL { list<Register> Uses = [CL]; bit printImplicitUses = 1; }
143 //===----------------------------------------------------------------------===//
144 // Instruction list...
147 def PHI : I<"PHI", 0, Pseudo>; // PHI node...
149 def NOOP : I<"nop", 0x90, RawFrm>; // nop
151 def ADJCALLSTACKDOWN : I<"ADJCALLSTACKDOWN", 0, Pseudo>;
152 def ADJCALLSTACKUP : I<"ADJCALLSTACKUP", 0, Pseudo>;
153 def IMPLICIT_USE : I<"IMPLICIT_USE", 0, Pseudo>;
154 def IMPLICIT_DEF : I<"IMPLICIT_DEF", 0, Pseudo>;
155 let isTerminator = 1 in
156 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
157 def FP_REG_KILL : I<"FP_REG_KILL", 0, Pseudo>;
158 //===----------------------------------------------------------------------===//
159 // Control Flow Instructions...
162 // Return instruction...
163 let isTerminator = 1, isReturn = 1 in
164 def RET : I<"ret", 0xC3, RawFrm>, Pattern<(retvoid)>;
166 // All branches are RawFrm, Void, Branch, and Terminators
167 let isBranch = 1, isTerminator = 1 in
168 class IBr<string name, bits<8> opcode> : I<name, opcode, RawFrm>;
170 def JMP : IBr<"jmp", 0xE9>, Pattern<(br basicblock)>;
171 def JB : IBr<"jb" , 0x82>, TB;
172 def JAE : IBr<"jae", 0x83>, TB;
173 def JE : IBr<"je" , 0x84>, TB, Pattern<(isVoid (unspec1 basicblock))>;
174 def JNE : IBr<"jne", 0x85>, TB;
175 def JBE : IBr<"jbe", 0x86>, TB;
176 def JA : IBr<"ja" , 0x87>, TB;
177 def JS : IBr<"js" , 0x88>, TB;
178 def JNS : IBr<"jns", 0x89>, TB;
179 def JL : IBr<"jl" , 0x8C>, TB;
180 def JGE : IBr<"jge", 0x8D>, TB;
181 def JLE : IBr<"jle", 0x8E>, TB;
182 def JG : IBr<"jg" , 0x8F>, TB;
185 //===----------------------------------------------------------------------===//
186 // Call Instructions...
189 // All calls clobber the non-callee saved registers...
190 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6] in {
191 def CALLpcrel32 : I <"call", 0xE8, RawFrm>;
192 def CALLr32 : I <"call", 0xFF, MRM2r>;
193 def CALLm32 : Im32<"call", 0xFF, MRM2m>;
197 //===----------------------------------------------------------------------===//
198 // Miscellaneous Instructions...
200 def LEAVE : I<"leave", 0xC9, RawFrm>, Imp<[EBP,ESP],[EBP,ESP]>;
201 def POPr32 : I<"pop", 0x58, AddRegFrm>, Imp<[ESP],[ESP]>;
203 let isTwoAddress = 1 in // R32 = bswap R32
204 def BSWAPr32 : I<"bswap", 0xC8, AddRegFrm>, TB;
206 def XCHGrr8 : I <"xchg", 0x86, MRMDestReg>; // xchg R8, R8
207 def XCHGrr16 : I <"xchg", 0x87, MRMDestReg>, OpSize; // xchg R16, R16
208 def XCHGrr32 : I <"xchg", 0x87, MRMDestReg>; // xchg R32, R32
209 def XCHGmr8 : Im8 <"xchg", 0x86, MRMDestMem>; // xchg [mem8], R8
210 def XCHGmr16 : Im16<"xchg", 0x87, MRMDestMem>, OpSize; // xchg [mem16], R16
211 def XCHGmr32 : Im32<"xchg", 0x87, MRMDestMem>; // xchg [mem32], R32
212 def XCHGrm8 : Im8 <"xchg", 0x86, MRMSrcMem >; // xchg R8, [mem8]
213 def XCHGrm16 : Im16<"xchg", 0x87, MRMSrcMem >, OpSize; // xchg R16, [mem16]
214 def XCHGrm32 : Im32<"xchg", 0x87, MRMSrcMem >; // xchg R32, [mem32]
216 def LEAr16 : Im32<"lea", 0x8D, MRMSrcMem>, OpSize; // R16 = lea [mem]
217 def LEAr32 : Im32<"lea", 0x8D, MRMSrcMem>; // R32 = lea [mem]
220 def REP_MOVSB : I<"rep movsb", 0xA4, RawFrm>, REP,
221 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>;
222 def REP_MOVSW : I<"rep movsw", 0xA5, RawFrm>, REP, OpSize,
223 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>;
224 def REP_MOVSD : I<"rep movsd", 0xA5, RawFrm>, REP,
225 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>;
227 def REP_STOSB : I<"rep stosb", 0xAA, RawFrm>, REP,
228 Imp<[AL,ECX,EDI], [ECX,EDI]>;
229 def REP_STOSW : I<"rep stosw", 0xAB, RawFrm>, REP, OpSize,
230 Imp<[AX,ECX,EDI], [ECX,EDI]>;
231 def REP_STOSD : I<"rep stosd", 0xAB, RawFrm>, REP,
232 Imp<[EAX,ECX,EDI], [ECX,EDI]>;
234 //===----------------------------------------------------------------------===//
235 // Move Instructions...
237 def MOVrr8 : I <"mov", 0x88, MRMDestReg>, Pattern<(set R8 , R8 )>;
238 def MOVrr16 : I <"mov", 0x89, MRMDestReg>, OpSize, Pattern<(set R16, R16)>;
239 def MOVrr32 : I <"mov", 0x89, MRMDestReg>, Pattern<(set R32, R32)>;
240 def MOVri8 : Ii8 <"mov", 0xB0, AddRegFrm >, Pattern<(set R8 , imm )>;
241 def MOVri16 : Ii16 <"mov", 0xB8, AddRegFrm >, OpSize, Pattern<(set R16, imm)>;
242 def MOVri32 : Ii32 <"mov", 0xB8, AddRegFrm >, Pattern<(set R32, imm)>;
243 def MOVmi8 : Im8i8 <"mov", 0xC6, MRM0m >; // [mem8] = imm8
244 def MOVmi16 : Im16i16<"mov", 0xC7, MRM0m >, OpSize; // [mem16] = imm16
245 def MOVmi32 : Im32i32<"mov", 0xC7, MRM0m >; // [mem32] = imm32
247 def MOVrm8 : Im8 <"mov", 0x8A, MRMSrcMem>; // R8 = [mem8]
248 def MOVrm16 : Im16 <"mov", 0x8B, MRMSrcMem>, OpSize, // R16 = [mem16]
249 Pattern<(set R16, (load (plus R32, (plus (times imm, R32), imm))))>;
250 def MOVrm32 : Im32 <"mov", 0x8B, MRMSrcMem>, // R32 = [mem32]
251 Pattern<(set R32, (load (plus R32, (plus (times imm, R32), imm))))>;
253 def MOVmr8 : Im8 <"mov", 0x88, MRMDestMem>; // [mem8] = R8
254 def MOVmr16 : Im16 <"mov", 0x89, MRMDestMem>, OpSize; // [mem16] = R16
255 def MOVmr32 : Im32 <"mov", 0x89, MRMDestMem>; // [mem32] = R32
257 //===----------------------------------------------------------------------===//
258 // Fixed-Register Multiplication and Division Instructions...
261 // Extra precision multiplication
262 def MULr8 : I <"mul", 0xF6, MRM4r>, Imp<[AL],[AX]>; // AL,AH = AL*R8
263 def MULr16 : I <"mul", 0xF7, MRM4r>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
264 def MULr32 : I <"mul", 0xF7, MRM4r>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
265 def MULm8 : Im8 <"mul", 0xF6, MRM4m>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
266 def MULm16 : Im16<"mul", 0xF7, MRM4m>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*[mem16]
267 def MULm32 : Im32<"mul", 0xF7, MRM4m>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
269 // unsigned division/remainder
270 def DIVr8 : I <"div", 0xF6, MRM6r>, Imp<[AX],[AX]>; // AX/r8 = AL,AH
271 def DIVr16 : I <"div", 0xF7, MRM6r>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
272 def DIVr32 : I <"div", 0xF7, MRM6r>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
273 def DIVm8 : Im8 <"div", 0xF6, MRM6m>, Imp<[AX],[AX]>; // AX/[mem8] = AL,AH
274 def DIVm16 : Im16<"div", 0xF7, MRM6m>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[mem16] = AX,DX
275 def DIVm32 : Im32<"div", 0xF7, MRM6m>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX
277 // signed division/remainder
278 def IDIVr8 : I <"idiv",0xF6, MRM7r>, Imp<[AX],[AX]>; // AX/r8 = AL,AH
279 def IDIVr16: I <"idiv",0xF7, MRM7r>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
280 def IDIVr32: I <"idiv",0xF7, MRM7r>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
281 def IDIVm8 : Im8 <"idiv",0xF6, MRM7m>, Imp<[AX],[AX]>; // AX/[mem8] = AL,AH
282 def IDIVm16: Im16<"idiv",0xF7, MRM7m>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[mem16] = AX,DX
283 def IDIVm32: Im32<"idiv",0xF7, MRM7m>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX
285 // Sign-extenders for division
286 def CBW : I<"cbw", 0x98, RawFrm >, Imp<[AL],[AH]>; // AX = signext(AL)
287 def CWD : I<"cwd", 0x99, RawFrm >, Imp<[AX],[DX]>; // DX:AX = signext(AX)
288 def CDQ : I<"cdq", 0x99, RawFrm >, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX)
290 //===----------------------------------------------------------------------===//
291 // Two address Instructions...
293 let isTwoAddress = 1 in {
295 // Conditional moves. These are modelled as X = cmovXX Y, Z. Eventually
296 // register allocated to cmovXX XY, Z
297 def CMOVErr16 : I<"cmove", 0x44, MRMSrcReg>, TB, OpSize; // if ==, R16 = R16
298 def CMOVNErr32: I<"cmovne",0x45, MRMSrcReg>, TB; // if !=, R32 = R32
299 def CMOVSrr32 : I<"cmovs", 0x48, MRMSrcReg>, TB; // if signed, R32 = R32
301 // unary instructions
302 def NEGr8 : I <"neg", 0xF6, MRM3r>; // R8 = -R8 = 0-R8
303 def NEGr16 : I <"neg", 0xF7, MRM3r>, OpSize; // R16 = -R16 = 0-R16
304 def NEGr32 : I <"neg", 0xF7, MRM3r>; // R32 = -R32 = 0-R32
305 def NEGm8 : Im8 <"neg", 0xF6, MRM3m>; // [mem8] = -[mem8] = 0-[mem8]
306 def NEGm16 : Im16<"neg", 0xF7, MRM3m>, OpSize; // [mem16] = -[mem16] = 0-[mem16]
307 def NEGm32 : Im32<"neg", 0xF7, MRM3m>; // [mem32] = -[mem32] = 0-[mem32]
309 def NOTr8 : I <"not", 0xF6, MRM2r>; // R8 = ~R8 = R8^-1
310 def NOTr16 : I <"not", 0xF7, MRM2r>, OpSize; // R16 = ~R16 = R16^-1
311 def NOTr32 : I <"not", 0xF7, MRM2r>; // R32 = ~R32 = R32^-1
312 def NOTm8 : Im8 <"not", 0xF6, MRM2m>; // [mem8] = ~[mem8] = [mem8^-1]
313 def NOTm16 : Im16<"not", 0xF7, MRM2m>, OpSize; // [mem16] = ~[mem16] = [mem16^-1]
314 def NOTm32 : Im32<"not", 0xF7, MRM2m>; // [mem32] = ~[mem32] = [mem32^-1]
316 def INCr8 : I <"inc", 0xFE, MRM0r>; // ++R8
317 def INCr16 : I <"inc", 0xFF, MRM0r>, OpSize; // ++R16
318 def INCr32 : I <"inc", 0xFF, MRM0r>; // ++R32
319 def INCm8 : Im8 <"inc", 0xFE, MRM0m>; // ++R8
320 def INCm16 : Im16<"inc", 0xFF, MRM0m>, OpSize; // ++R16
321 def INCm32 : Im32<"inc", 0xFF, MRM0m>; // ++R32
323 def DECr8 : I <"dec", 0xFE, MRM1r>; // --R8
324 def DECr16 : I <"dec", 0xFF, MRM1r>, OpSize; // --R16
325 def DECr32 : I <"dec", 0xFF, MRM1r>; // --R32
326 def DECm8 : Im8 <"dec", 0xFE, MRM1m>; // --[mem8]
327 def DECm16 : Im16<"dec", 0xFF, MRM1m>, OpSize; // --[mem16]
328 def DECm32 : Im32<"dec", 0xFF, MRM1m>; // --[mem32]
330 // Logical operators...
331 def ANDrr8 : I <"and", 0x20, MRMDestReg>, Pattern<(set R8 , (and R8 , R8 ))>;
332 def ANDrr16 : I <"and", 0x21, MRMDestReg>, OpSize, Pattern<(set R16, (and R16, R16))>;
333 def ANDrr32 : I <"and", 0x21, MRMDestReg>, Pattern<(set R32, (and R32, R32))>;
334 def ANDmr8 : Im8 <"and", 0x20, MRMDestMem>; // [mem8] &= R8
335 def ANDmr16 : Im16 <"and", 0x21, MRMDestMem>, OpSize; // [mem16] &= R16
336 def ANDmr32 : Im32 <"and", 0x21, MRMDestMem>; // [mem32] &= R32
337 def ANDrm8 : Im8 <"and", 0x22, MRMSrcMem >; // R8 &= [mem8]
338 def ANDrm16 : Im16 <"and", 0x23, MRMSrcMem >, OpSize; // R16 &= [mem16]
339 def ANDrm32 : Im32 <"and", 0x23, MRMSrcMem >; // R32 &= [mem32]
341 def ANDri8 : Ii8 <"and", 0x80, MRM4r >, Pattern<(set R8 , (and R8 , imm))>;
342 def ANDri16 : Ii16 <"and", 0x81, MRM4r >, OpSize, Pattern<(set R16, (and R16, imm))>;
343 def ANDri32 : Ii32 <"and", 0x81, MRM4r >, Pattern<(set R32, (and R32, imm))>;
344 def ANDmi8 : Im8i8 <"and", 0x80, MRM4m >; // [mem8] &= imm8
345 def ANDmi16 : Im16i16 <"and", 0x81, MRM4m >, OpSize; // [mem16] &= imm16
346 def ANDmi32 : Im32i32 <"and", 0x81, MRM4m >; // [mem32] &= imm32
348 def ANDri16b : Ii8 <"and", 0x83, MRM4r >, OpSize; // R16 &= imm8
349 def ANDri32b : Ii8 <"and", 0x83, MRM4r >; // R32 &= imm8
350 def ANDmi16b : Im16i8<"and", 0x83, MRM4m >, OpSize; // [mem16] &= imm8
351 def ANDmi32b : Im32i8<"and", 0x83, MRM4m >; // [mem32] &= imm8
354 def ORrr8 : I <"or" , 0x08, MRMDestReg>, Pattern<(set R8 , (or R8 , R8 ))>;
355 def ORrr16 : I <"or" , 0x09, MRMDestReg>, OpSize, Pattern<(set R16, (or R16, R16))>;
356 def ORrr32 : I <"or" , 0x09, MRMDestReg>, Pattern<(set R32, (or R32, R32))>;
357 def ORmr8 : Im8 <"or" , 0x08, MRMDestMem>; // [mem8] |= R8
358 def ORmr16 : Im16 <"or" , 0x09, MRMDestMem>, OpSize; // [mem16] |= R16
359 def ORmr32 : Im32 <"or" , 0x09, MRMDestMem>; // [mem32] |= R32
360 def ORrm8 : Im8 <"or" , 0x0A, MRMSrcMem >; // R8 |= [mem8]
361 def ORrm16 : Im16 <"or" , 0x0B, MRMSrcMem >, OpSize; // R16 |= [mem16]
362 def ORrm32 : Im32 <"or" , 0x0B, MRMSrcMem >; // R32 |= [mem32]
364 def ORri8 : Ii8 <"or" , 0x80, MRM1r >, Pattern<(set R8 , (or R8 , imm))>;
365 def ORri16 : Ii16 <"or" , 0x81, MRM1r >, OpSize, Pattern<(set R16, (or R16, imm))>;
366 def ORri32 : Ii32 <"or" , 0x81, MRM1r >, Pattern<(set R32, (or R32, imm))>;
367 def ORmi8 : Im8i8 <"or" , 0x80, MRM1m >; // [mem8] |= imm8
368 def ORmi16 : Im16i16 <"or" , 0x81, MRM1m >, OpSize; // [mem16] |= imm16
369 def ORmi32 : Im32i32 <"or" , 0x81, MRM1m >; // [mem32] |= imm32
371 def ORri16b : Ii8 <"or" , 0x83, MRM1r >, OpSize; // R16 |= imm8
372 def ORri32b : Ii8 <"or" , 0x83, MRM1r >; // R32 |= imm8
373 def ORmi16b : Im16i8<"or" , 0x83, MRM1m >, OpSize; // [mem16] |= imm8
374 def ORmi32b : Im32i8<"or" , 0x83, MRM1m >; // [mem32] |= imm8
377 def XORrr8 : I <"xor", 0x30, MRMDestReg>, Pattern<(set R8 , (xor R8 , R8 ))>;
378 def XORrr16 : I <"xor", 0x31, MRMDestReg>, OpSize, Pattern<(set R16, (xor R16, R16))>;
379 def XORrr32 : I <"xor", 0x31, MRMDestReg>, Pattern<(set R32, (xor R32, R32))>;
380 def XORmr8 : Im8 <"xor", 0x30, MRMDestMem>; // [mem8] ^= R8
381 def XORmr16 : Im16 <"xor", 0x31, MRMDestMem>, OpSize; // [mem16] ^= R16
382 def XORmr32 : Im32 <"xor", 0x31, MRMDestMem>; // [mem32] ^= R32
383 def XORrm8 : Im8 <"xor", 0x32, MRMSrcMem >; // R8 ^= [mem8]
384 def XORrm16 : Im16 <"xor", 0x33, MRMSrcMem >, OpSize; // R16 ^= [mem16]
385 def XORrm32 : Im32 <"xor", 0x33, MRMSrcMem >; // R32 ^= [mem32]
387 def XORri8 : Ii8 <"xor", 0x80, MRM6r >, Pattern<(set R8 , (xor R8 , imm))>;
388 def XORri16 : Ii16 <"xor", 0x81, MRM6r >, OpSize, Pattern<(set R16, (xor R16, imm))>;
389 def XORri32 : Ii32 <"xor", 0x81, MRM6r >, Pattern<(set R32, (xor R32, imm))>;
390 def XORmi8 : Im8i8 <"xor", 0x80, MRM6m >; // [mem8] ^= R8
391 def XORmi16 : Im16i16 <"xor", 0x81, MRM6m >, OpSize; // [mem16] ^= R16
392 def XORmi32 : Im32i32 <"xor", 0x81, MRM6m >; // [mem32] ^= R32
394 def XORri16b : Ii8 <"xor", 0x83, MRM6r >, OpSize; // R16 ^= imm8
395 def XORri32b : Ii8 <"xor", 0x83, MRM6r >; // R32 ^= imm8
396 def XORmi16b : Im16i8<"xor", 0x83, MRM6m >, OpSize; // [mem16] ^= imm8
397 def XORmi32b : Im32i8<"xor", 0x83, MRM6m >; // [mem32] ^= imm8
399 // Shift instructions
400 def SHLrCL8 : I <"shl", 0xD2, MRM4r > , UsesCL; // R8 <<= cl
401 def SHLrCL16 : I <"shl", 0xD3, MRM4r >, OpSize, UsesCL; // R16 <<= cl
402 def SHLrCL32 : I <"shl", 0xD3, MRM4r > , UsesCL; // R32 <<= cl
403 def SHLmCL8 : Im8 <"shl", 0xD2, MRM4m > , UsesCL; // [mem8] <<= cl
404 def SHLmCL16 : Im16 <"shl", 0xD3, MRM4m >, OpSize, UsesCL; // [mem16] <<= cl
405 def SHLmCL32 : Im32 <"shl", 0xD3, MRM4m > , UsesCL; // [mem32] <<= cl
407 def SHLri8 : Ii8 <"shl", 0xC0, MRM4r >; // R8 <<= imm8
408 def SHLri16 : Ii8 <"shl", 0xC1, MRM4r >, OpSize; // R16 <<= imm8
409 def SHLri32 : Ii8 <"shl", 0xC1, MRM4r >; // R32 <<= imm8
410 def SHLmi8 : Im8i8 <"shl", 0xC0, MRM4m >; // [mem8] <<= imm8
411 def SHLmi16 : Im16i8<"shl", 0xC1, MRM4m >, OpSize; // [mem16] <<= imm8
412 def SHLmi32 : Im32i8<"shl", 0xC1, MRM4m >; // [mem32] <<= imm8
414 def SHRrCL8 : I <"shr", 0xD2, MRM5r > , UsesCL; // R8 >>= cl
415 def SHRrCL16 : I <"shr", 0xD3, MRM5r >, OpSize, UsesCL; // R16 >>= cl
416 def SHRrCL32 : I <"shr", 0xD3, MRM5r > , UsesCL; // R32 >>= cl
417 def SHRmCL8 : Im8 <"shr", 0xD2, MRM5m > , UsesCL; // [mem8] >>= cl
418 def SHRmCL16 : Im16 <"shr", 0xD3, MRM5m >, OpSize, UsesCL; // [mem16] >>= cl
419 def SHRmCL32 : Im32 <"shr", 0xD3, MRM5m > , UsesCL; // [mem32] >>= cl
421 def SHRri8 : Ii8 <"shr", 0xC0, MRM5r >; // R8 >>= imm8
422 def SHRri16 : Ii8 <"shr", 0xC1, MRM5r >, OpSize; // R16 >>= imm8
423 def SHRri32 : Ii8 <"shr", 0xC1, MRM5r >; // R32 >>= imm8
424 def SHRmi8 : Im8i8 <"shr", 0xC0, MRM5m >; // [mem8] >>= imm8
425 def SHRmi16 : Im16i8<"shr", 0xC1, MRM5m >, OpSize; // [mem16] >>= imm8
426 def SHRmi32 : Im32i8<"shr", 0xC1, MRM5m >; // [mem32] >>= imm8
428 def SARrCL8 : I <"sar", 0xD2, MRM7r > , UsesCL; // R8 >>>= cl
429 def SARrCL16 : I <"sar", 0xD3, MRM7r >, OpSize, UsesCL; // R16 >>>= cl
430 def SARrCL32 : I <"sar", 0xD3, MRM7r > , UsesCL; // R32 >>>= cl
431 def SARmCL8 : Im8 <"sar", 0xD2, MRM7m > , UsesCL; // [mem8] >>>= cl
432 def SARmCL16 : Im16 <"sar", 0xD3, MRM7m >, OpSize, UsesCL; // [mem16] >>>= cl
433 def SARmCL32 : Im32 <"sar", 0xD3, MRM7m > , UsesCL; // [mem32] >>>= cl
435 def SARri8 : Ii8 <"sar", 0xC0, MRM7r >; // R8 >>>= imm8
436 def SARri16 : Ii8 <"sar", 0xC1, MRM7r >, OpSize; // R16 >>>= imm8
437 def SARri32 : Ii8 <"sar", 0xC1, MRM7r >; // R32 >>>= imm8
438 def SARmi8 : Im8i8 <"sar", 0xC0, MRM7m >; // [mem8] >>>= imm8
439 def SARmi16 : Im16i8<"sar", 0xC1, MRM7m >, OpSize; // [mem16] >>>= imm8
440 def SARmi32 : Im32i8<"sar", 0xC1, MRM7m >; // [mem32] >>>= imm8
442 def SHLDrrCL32 : I <"shld", 0xA5, MRMDestReg>, TB, UsesCL; // R32 <<= R32,R32 cl
443 def SHLDmrCL32 : I <"shld", 0xA5, MRMDestMem>, TB, UsesCL; // [mem32] <<= [mem32],R32 cl
444 def SHLDrr32i8 : Ii8 <"shld", 0xA4, MRMDestReg>, TB; // R32 <<= R32,R32 imm8
445 def SHLDmr32i8 : Ii8 <"shld", 0xA4, MRMDestMem>, TB; // [mem32] <<= [mem32],R32 imm8
447 def SHRDrrCL32 : I <"shrd", 0xAD, MRMDestReg>, TB, UsesCL; // R32 >>= R32,R32 cl
448 def SHRDmrCL32 : I <"shrd", 0xAD, MRMDestMem>, TB, UsesCL; // [mem32] >>= [mem32],R32 cl
449 def SHRDrr32i8 : Ii8 <"shrd", 0xAC, MRMDestReg>, TB; // R32 >>= R32,R32 imm8
450 def SHRDmr32i8 : Ii8 <"shrd", 0xAC, MRMDestMem>, TB; // [mem32] >>= [mem32],R32 imm8
454 def ADDrr8 : I <"add", 0x00, MRMDestReg>, Pattern<(set R8 , (plus R8 , R8 ))>;
455 def ADDrr16 : I <"add", 0x01, MRMDestReg>, OpSize, Pattern<(set R16, (plus R16, R16))>;
456 def ADDrr32 : I <"add", 0x01, MRMDestReg>, Pattern<(set R32, (plus R32, R32))>;
457 def ADDmr8 : Im8 <"add", 0x00, MRMDestMem>; // [mem8] += R8
458 def ADDmr16 : Im16 <"add", 0x01, MRMDestMem>, OpSize; // [mem16] += R16
459 def ADDmr32 : Im32 <"add", 0x01, MRMDestMem>; // [mem32] += R32
460 def ADDrm8 : Im8 <"add", 0x02, MRMSrcMem >; // R8 += [mem8]
461 def ADDrm16 : Im16 <"add", 0x03, MRMSrcMem >, OpSize; // R16 += [mem16]
462 def ADDrm32 : Im32 <"add", 0x03, MRMSrcMem >; // R32 += [mem32]
464 def ADDri8 : Ii8 <"add", 0x80, MRM0r >, Pattern<(set R8 , (plus R8 , imm))>;
465 def ADDri16 : Ii16 <"add", 0x81, MRM0r >, OpSize, Pattern<(set R16, (plus R16, imm))>;
466 def ADDri32 : Ii32 <"add", 0x81, MRM0r >, Pattern<(set R32, (plus R32, imm))>;
467 def ADDmi8 : Im8i8 <"add", 0x80, MRM0m >; // [mem8] += I8
468 def ADDmi16 : Im16i16 <"add", 0x81, MRM0m >, OpSize; // [mem16] += I16
469 def ADDmi32 : Im32i32 <"add", 0x81, MRM0m >; // [mem32] += I32
471 def ADDri16b : Ii8 <"add", 0x83, MRM0r >, OpSize; // ADDri with sign extended 8 bit imm
472 def ADDri32b : Ii8 <"add", 0x83, MRM0r >;
473 def ADDmi16b : Im16i8<"add", 0x83, MRM0m >, OpSize; // [mem16] += I8
474 def ADDmi32b : Im32i8<"add", 0x83, MRM0m >; // [mem32] += I8
476 def ADCrr32 : I <"adc", 0x11, MRMDestReg>; // R32 += R32+Carry
477 def ADCrm32 : Im32 <"adc", 0x11, MRMSrcMem >; // R32 += [mem32]+Carry
478 def ADCmr32 : Im32 <"adc", 0x13, MRMDestMem>; // [mem32] += R32+Carry
481 def SUBrr8 : I <"sub", 0x28, MRMDestReg>, Pattern<(set R8 , (minus R8 , R8 ))>;
482 def SUBrr16 : I <"sub", 0x29, MRMDestReg>, OpSize, Pattern<(set R16, (minus R16, R16))>;
483 def SUBrr32 : I <"sub", 0x29, MRMDestReg>, Pattern<(set R32, (minus R32, R32))>;
484 def SUBmr8 : Im8 <"sub", 0x28, MRMDestMem>; // [mem8] -= R8
485 def SUBmr16 : Im16 <"sub", 0x29, MRMDestMem>, OpSize; // [mem16] -= R16
486 def SUBmr32 : Im32 <"sub", 0x29, MRMDestMem>; // [mem32] -= R32
487 def SUBrm8 : Im8 <"sub", 0x2A, MRMSrcMem >; // R8 -= [mem8]
488 def SUBrm16 : Im16 <"sub", 0x2B, MRMSrcMem >, OpSize; // R16 -= [mem16]
489 def SUBrm32 : Im32 <"sub", 0x2B, MRMSrcMem >; // R32 -= [mem32]
491 def SUBri8 : Ii8 <"sub", 0x80, MRM5r >, Pattern<(set R8 , (minus R8 , imm))>;
492 def SUBri16 : Ii16 <"sub", 0x81, MRM5r >, OpSize, Pattern<(set R16, (minus R16, imm))>;
493 def SUBri32 : Ii32 <"sub", 0x81, MRM5r >, Pattern<(set R32, (minus R32, imm))>;
494 def SUBmi8 : Im8i8 <"sub", 0x80, MRM5m >; // [mem8] -= I8
495 def SUBmi16 : Im16i16 <"sub", 0x81, MRM5m >, OpSize; // [mem16] -= I16
496 def SUBmi32 : Im32i32 <"sub", 0x81, MRM5m >; // [mem32] -= I32
498 def SUBri16b : Ii8 <"sub", 0x83, MRM5r >, OpSize;
499 def SUBri32b : Ii8 <"sub", 0x83, MRM5r >;
500 def SUBmi16b : Im16i8<"sub", 0x83, MRM5m >, OpSize; // [mem16] -= I8
501 def SUBmi32b : Im32i8<"sub", 0x83, MRM5m >; // [mem32] -= I8
503 def SBBrr32 : I <"sbb", 0x19, MRMDestReg>; // R32 -= R32+Borrow
504 def SBBrm32 : Im32 <"sbb", 0x19, MRMSrcMem >; // R32 -= [mem32]+Borrow
505 def SBBmr32 : Im32 <"sbb", 0x1B, MRMDestMem>; // [mem32] -= R32+Borrow
507 def IMULrr16 : I <"imul", 0xAF, MRMSrcReg>, TB, OpSize, Pattern<(set R16, (times R16, R16))>;
508 def IMULrr32 : I <"imul", 0xAF, MRMSrcReg>, TB , Pattern<(set R32, (times R32, R32))>;
509 def IMULrm16 : Im16 <"imul", 0xAF, MRMSrcMem>, TB, OpSize;
510 def IMULrm32 : Im32 <"imul", 0xAF, MRMSrcMem>, TB ;
512 } // end Two Address instructions
514 // These are suprisingly enough not two address instructions!
515 def IMULrri16 : Ii16 <"imul", 0x69, MRMSrcReg>, OpSize; // R16 = R16*I16
516 def IMULrri32 : Ii32 <"imul", 0x69, MRMSrcReg>; // R32 = R32*I32
517 def IMULrri16b : Ii8 <"imul", 0x6B, MRMSrcReg>, OpSize; // R16 = R16*I8
518 def IMULrri32b : Ii8 <"imul", 0x6B, MRMSrcReg>; // R32 = R32*I8
519 def IMULrmi16 : Im16i16 <"imul", 0x69, MRMSrcMem>, OpSize; // R16 = [mem16]*I16
520 def IMULrmi32 : Im32i32 <"imul", 0x69, MRMSrcMem>; // R32 = [mem32]*I32
521 def IMULrmi16b : Im16i8<"imul", 0x6B, MRMSrcMem>, OpSize; // R16 = [mem16]*I8
522 def IMULrmi32b : Im32i8<"imul", 0x6B, MRMSrcMem>; // R32 = [mem32]*I8
524 //===----------------------------------------------------------------------===//
525 // Test instructions are just like AND, except they don't generate a result.
526 def TESTrr8 : I <"test", 0x84, MRMDestReg>; // flags = R8 & R8
527 def TESTrr16 : I <"test", 0x85, MRMDestReg>, OpSize; // flags = R16 & R16
528 def TESTrr32 : I <"test", 0x85, MRMDestReg>; // flags = R32 & R32
529 def TESTmr8 : Im8 <"test", 0x84, MRMDestMem>; // flags = [mem8] & R8
530 def TESTmr16 : Im16 <"test", 0x85, MRMDestMem>, OpSize; // flags = [mem16] & R16
531 def TESTmr32 : Im32 <"test", 0x85, MRMDestMem>; // flags = [mem32] & R32
532 def TESTrm8 : Im8 <"test", 0x84, MRMSrcMem >; // flags = R8 & [mem8]
533 def TESTrm16 : Im16 <"test", 0x85, MRMSrcMem >, OpSize; // flags = R16 & [mem16]
534 def TESTrm32 : Im32 <"test", 0x85, MRMSrcMem >; // flags = R32 & [mem32]
536 def TESTri8 : Ii8 <"test", 0xF6, MRM0r >; // flags = R8 & imm8
537 def TESTri16 : Ii16 <"test", 0xF7, MRM0r >, OpSize; // flags = R16 & imm16
538 def TESTri32 : Ii32 <"test", 0xF7, MRM0r >; // flags = R32 & imm32
539 def TESTmi8 : Im8i8 <"test", 0xF6, MRM0m >; // flags = [mem8] & imm8
540 def TESTmi16 : Im16i16<"test", 0xF7, MRM0m >, OpSize; // flags = [mem16] & imm16
541 def TESTmi32 : Im32i32<"test", 0xF7, MRM0m >; // flags = [mem32] & imm32
545 // Condition code ops, incl. set if equal/not equal/...
546 def SAHF : I <"sahf" , 0x9E, RawFrm>, Imp<[AH],[]>; // flags = AH
548 def SETBr : I <"setb" , 0x92, MRM0r>, TB; // R8 = < unsign
549 def SETBm : Im8<"setb" , 0x92, MRM0m>, TB; // [mem8] = < unsign
550 def SETAEr : I <"setae", 0x93, MRM0r>, TB; // R8 = >= unsign
551 def SETAEm : Im8<"setae", 0x93, MRM0m>, TB; // [mem8] = >= unsign
552 def SETEr : I <"sete" , 0x94, MRM0r>, TB; // R8 = ==
553 def SETEm : Im8<"sete" , 0x94, MRM0m>, TB; // [mem8] = ==
554 def SETNEr : I <"setne", 0x95, MRM0r>, TB; // R8 = !=
555 def SETNEm : Im8<"setne", 0x95, MRM0m>, TB; // [mem8] = !=
556 def SETBEr : I <"setbe", 0x96, MRM0r>, TB; // R8 = <= unsign
557 def SETBEm : Im8<"setbe", 0x96, MRM0m>, TB; // [mem8] = <= unsign
558 def SETAr : I <"seta" , 0x97, MRM0r>, TB; // R8 = > signed
559 def SETAm : Im8<"seta" , 0x97, MRM0m>, TB; // [mem8] = > signed
560 def SETSr : I <"sets" , 0x98, MRM0r>, TB; // R8 = <sign bit>
561 def SETSm : Im8<"sets" , 0x98, MRM0m>, TB; // [mem8] = <sign bit>
562 def SETNSr : I <"setns", 0x99, MRM0r>, TB; // R8 = !<sign bit>
563 def SETNSm : Im8<"setns", 0x99, MRM0m>, TB; // [mem8] = !<sign bit>
564 def SETLr : I <"setl" , 0x9C, MRM0r>, TB; // R8 = < signed
565 def SETLm : Im8<"setl" , 0x9C, MRM0m>, TB; // [mem8] = < signed
566 def SETGEr : I <"setge", 0x9D, MRM0r>, TB; // R8 = >= signed
567 def SETGEm : Im8<"setge", 0x9D, MRM0m>, TB; // [mem8] = >= signed
568 def SETLEr : I <"setle", 0x9E, MRM0r>, TB; // R8 = <= signed
569 def SETLEm : Im8<"setle", 0x9E, MRM0m>, TB; // [mem8] = <= signed
570 def SETGr : I <"setg" , 0x9F, MRM0r>, TB; // R8 = < signed
571 def SETGm : Im8<"setg" , 0x9F, MRM0m>, TB; // [mem8] = < signed
573 // Integer comparisons
574 def CMPrr8 : I <"cmp", 0x38, MRMDestReg>; // compare R8, R8
575 def CMPrr16 : I <"cmp", 0x39, MRMDestReg>, OpSize; // compare R16, R16
576 def CMPrr32 : I <"cmp", 0x39, MRMDestReg>, // compare R32, R32
577 Pattern<(isVoid (unspec2 R32, R32))>;
578 def CMPmr8 : Im8 <"cmp", 0x38, MRMDestMem>; // compare [mem8], R8
579 def CMPmr16 : Im16 <"cmp", 0x39, MRMDestMem>, OpSize; // compare [mem16], R16
580 def CMPmr32 : Im32 <"cmp", 0x39, MRMDestMem>; // compare [mem32], R32
581 def CMPrm8 : Im8 <"cmp", 0x3A, MRMSrcMem >; // compare R8, [mem8]
582 def CMPrm16 : Im16 <"cmp", 0x3B, MRMSrcMem >, OpSize; // compare R16, [mem16]
583 def CMPrm32 : Im32 <"cmp", 0x3B, MRMSrcMem >; // compare R32, [mem32]
584 def CMPri8 : Ii8 <"cmp", 0x80, MRM7r >; // compare R8, imm8
585 def CMPri16 : Ii16 <"cmp", 0x81, MRM7r >, OpSize; // compare R16, imm16
586 def CMPri32 : Ii32 <"cmp", 0x81, MRM7r >; // compare R32, imm32
587 def CMPmi8 : Im8i8 <"cmp", 0x80, MRM7m >; // compare [mem8], imm8
588 def CMPmi16 : Im16i16<"cmp", 0x81, MRM7m >, OpSize; // compare [mem16], imm16
589 def CMPmi32 : Im32i32<"cmp", 0x81, MRM7m >; // compare [mem32], imm32
591 // Sign/Zero extenders
592 def MOVSXr16r8 : I <"movsx", 0xBE, MRMSrcReg>, TB, OpSize; // R16 = signext(R8)
593 def MOVSXr32r8 : I <"movsx", 0xBE, MRMSrcReg>, TB; // R32 = signext(R8)
594 def MOVSXr32r16: I <"movsx", 0xBF, MRMSrcReg>, TB; // R32 = signext(R16)
595 def MOVSXr16m8 : Im8 <"movsx", 0xBE, MRMSrcMem>, TB, OpSize; // R16 = signext([mem8])
596 def MOVSXr32m8 : Im8 <"movsx", 0xBE, MRMSrcMem>, TB; // R32 = signext([mem8])
597 def MOVSXr32m16: Im16<"movsx", 0xBF, MRMSrcMem>, TB; // R32 = signext([mem16])
599 def MOVZXr16r8 : I <"movzx", 0xB6, MRMSrcReg>, TB, OpSize; // R16 = zeroext(R8)
600 def MOVZXr32r8 : I <"movzx", 0xB6, MRMSrcReg>, TB; // R32 = zeroext(R8)
601 def MOVZXr32r16: I <"movzx", 0xB7, MRMSrcReg>, TB; // R32 = zeroext(R16)
602 def MOVZXr16m8 : Im8 <"movzx", 0xB6, MRMSrcMem>, TB, OpSize; // R16 = zeroext([mem8])
603 def MOVZXr32m8 : Im8 <"movzx", 0xB6, MRMSrcMem>, TB; // R32 = zeroext([mem8])
604 def MOVZXr32m16: Im16<"movzx", 0xB7, MRMSrcMem>, TB; // R32 = zeroext([mem16])
607 //===----------------------------------------------------------------------===//
608 // Floating point support
609 //===----------------------------------------------------------------------===//
611 // FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP'
613 // Floating point instruction templates
614 class FPInst<string n, bits<8> o, Format F, FPFormat fp, MemType m, ImmType i>
615 : X86Inst<n, o, F, m, i> { let FPForm = fp; let FPFormBits = FPForm.Value; }
617 class FPI<string n, bits<8> o, Format F, FPFormat fp> : FPInst<n, o, F, fp, NoMem, NoImm>;
619 class FPIM<string n, bits<8> o, Format F, FPFormat fp, MemType m> : FPInst<n, o, F, fp, m, NoImm>;
621 class FPIm16<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem16>;
622 class FPIm32<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem32>;
623 class FPIm64<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem64>;
624 class FPIm80<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem80>;
626 // Pseudo instructions for floating point. We use these pseudo instructions
627 // because they can be expanded by the fp spackifier into one of many different
628 // forms of instructions for doing these operations. Until the stackifier runs,
629 // we prefer to be abstract.
630 def FpMOV : FPI<"FMOV", 0, Pseudo, SpecialFP>; // f1 = fmov f2
631 def FpADD : FPI<"FADD", 0, Pseudo, TwoArgFP>; // f1 = fadd f2, f3
632 def FpSUB : FPI<"FSUB", 0, Pseudo, TwoArgFP>; // f1 = fsub f2, f3
633 def FpMUL : FPI<"FMUL", 0, Pseudo, TwoArgFP>; // f1 = fmul f2, f3
634 def FpDIV : FPI<"FDIV", 0, Pseudo, TwoArgFP>; // f1 = fdiv f2, f3
636 def FpUCOM : FPI<"FUCOM", 0, Pseudo, TwoArgFP>; // FPSW = fucom f1, f2
637 def FpGETRESULT : FPI<"FGETRESULT",0, Pseudo, SpecialFP>; // FPR = ST(0)
638 def FpSETRESULT : FPI<"FSETRESULT",0, Pseudo, SpecialFP>; // ST(0) = FPR
640 // Floating point loads & stores...
641 def FLDrr : FPI <"fld" , 0xC0, AddRegFrm, NotFP>, D9; // push(ST(i))
642 def FLDm32 : FPIm32 <"fld" , 0xD9, MRM0m , ZeroArgFP>; // load float
643 def FLDm64 : FPIm64 <"fld" , 0xDD, MRM0m , ZeroArgFP>; // load double
644 def FLDm80 : FPIm80 <"fld" , 0xDB, MRM5m , ZeroArgFP>; // load extended
645 def FILDm16 : FPIm16 <"fild" , 0xDF, MRM0m , ZeroArgFP>; // load signed short
646 def FILDm32 : FPIm32 <"fild" , 0xDB, MRM0m , ZeroArgFP>; // load signed int
647 def FILDm64 : FPIm64 <"fild" , 0xDF, MRM5m , ZeroArgFP>; // load signed long
649 def FSTrr : FPI <"fst" , 0xD0, AddRegFrm, NotFP >, DD; // ST(i) = ST(0)
650 def FSTPrr : FPI <"fstp", 0xD8, AddRegFrm, NotFP >, DD; // ST(i) = ST(0), pop
651 def FSTm32 : FPIm32 <"fst" , 0xD9, MRM2m , OneArgFP>; // store float
652 def FSTm64 : FPIm64 <"fst" , 0xDD, MRM2m , OneArgFP>; // store double
653 def FSTPm32 : FPIm32 <"fstp", 0xD9, MRM3m , OneArgFP>; // store float, pop
654 def FSTPm64 : FPIm64 <"fstp", 0xDD, MRM3m , OneArgFP>; // store double, pop
655 def FSTPm80 : FPIm80 <"fstp", 0xDB, MRM7m , OneArgFP>; // store extended, pop
657 def FISTm16 : FPIm16 <"fist", 0xDF, MRM2m , OneArgFP>; // store signed short
658 def FISTm32 : FPIm32 <"fist", 0xDB, MRM2m , OneArgFP>; // store signed int
659 def FISTPm16 : FPIm16 <"fistp", 0xDF, MRM3m , NotFP >; // store signed short, pop
660 def FISTPm32 : FPIm32 <"fistp", 0xDB, MRM3m , NotFP >; // store signed int, pop
661 def FISTPm64 : FPIm64 <"fistpll", 0xDF, MRM7m , OneArgFP>; // store signed long, pop
663 def FXCH : FPI <"fxch", 0xC8, AddRegFrm, NotFP>, D9; // fxch ST(i), ST(0)
665 // Floating point constant loads...
666 def FLD0 : FPI<"fldz", 0xEE, RawFrm, ZeroArgFP>, D9;
667 def FLD1 : FPI<"fld1", 0xE8, RawFrm, ZeroArgFP>, D9;
670 // Unary operations...
671 def FCHS : FPI<"fchs", 0xE0, RawFrm, OneArgFPRW>, D9; // f1 = fchs f2
673 def FTST : FPI<"ftst", 0xE4, RawFrm, OneArgFP>, D9; // ftst ST(0)
675 // Binary arithmetic operations...
676 class FPST0rInst<string n, bits<8> o> : I<n, o, AddRegFrm>, D8 {
677 list<Register> Uses = [ST0];
678 list<Register> Defs = [ST0];
680 class FPrST0Inst<string n, bits<8> o> : I<n, o, AddRegFrm>, DC {
681 bit printImplicitUses = 1;
682 list<Register> Uses = [ST0];
684 class FPrST0PInst<string n, bits<8> o> : I<n, o, AddRegFrm>, DE {
685 list<Register> Uses = [ST0];
688 def FADDST0r : FPST0rInst <"fadd", 0xC0>;
689 def FADDrST0 : FPrST0Inst <"fadd", 0xC0>;
690 def FADDPrST0 : FPrST0PInst<"faddp", 0xC0>;
692 def FSUBRST0r : FPST0rInst <"fsubr", 0xE8>;
693 def FSUBrST0 : FPrST0Inst <"fsub", 0xE8>;
694 def FSUBPrST0 : FPrST0PInst<"fsubp", 0xE8>;
696 def FSUBST0r : FPST0rInst <"fsub", 0xE0>;
697 def FSUBRrST0 : FPrST0Inst <"fsubr", 0xE0>;
698 def FSUBRPrST0 : FPrST0PInst<"fsubrp", 0xE0>;
700 def FMULST0r : FPST0rInst <"fmul", 0xC8>;
701 def FMULrST0 : FPrST0Inst <"fmul", 0xC8>;
702 def FMULPrST0 : FPrST0PInst<"fmulp", 0xC8>;
704 def FDIVRST0r : FPST0rInst <"fdivr", 0xF8>;
705 def FDIVrST0 : FPrST0Inst <"fdiv", 0xF8>;
706 def FDIVPrST0 : FPrST0PInst<"fdivp", 0xF8>;
708 def FDIVST0r : FPST0rInst <"fdiv", 0xF0>; // ST(0) = ST(0) / ST(i)
709 def FDIVRrST0 : FPrST0Inst <"fdivr", 0xF0>; // ST(i) = ST(0) / ST(i)
710 def FDIVRPrST0 : FPrST0PInst<"fdivrp", 0xF0>; // ST(i) = ST(0) / ST(i), pop
712 // Floating point compares
713 def FUCOMr : I<"fucom" , 0xE0, AddRegFrm>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i)
714 def FUCOMPr : I<"fucomp" , 0xE8, AddRegFrm>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i), pop
715 def FUCOMPPr : I<"fucompp", 0xE9, RawFrm >, DA, Imp<[ST0],[]>; // compare ST(0) with ST(1), pop, pop
717 // Floating point flag ops
718 def FNSTSWr8 : I <"fnstsw" , 0xE0, RawFrm>, DF, Imp<[],[AX]>; // AX = fp flags
719 def FNSTCWm16 : Im16<"fnstcw" , 0xD9, MRM7m >; // [mem16] = X87 control world
720 def FLDCWm16 : Im16<"fldcw" , 0xD9, MRM5m >; // X87 control world = [mem16]
723 //===----------------------------------------------------------------------===//
724 // Instruction Expanders
727 def RET_R32 : Expander<(ret R32:$reg),
728 [(MOVrr32 EAX, R32:$reg),
731 // FIXME: This should eventually just be implemented by defining a frameidx as a
732 // value address for a load.
733 def LOAD_FI16 : Expander<(set R16:$dest, (load frameidx:$fi)),
734 [(MOVrm16 R16:$dest, frameidx:$fi, 1, 0/*NoReg*/, 0)]>;
736 def LOAD_FI32 : Expander<(set R32:$dest, (load frameidx:$fi)),
737 [(MOVrm32 R32:$dest, frameidx:$fi, 1, 0/*NoReg*/, 0)]>;
740 def LOAD_R16 : Expander<(set R16:$dest, (load R32:$src)),
741 [(MOVrm16 R16:$dest, R32:$src, 1, 0/*NoReg*/, 0)]>;
743 def LOAD_R32 : Expander<(set R32:$dest, (load R32:$src)),
744 [(MOVrm32 R32:$dest, R32:$src, 1, 0/*NoReg*/, 0)]>;
746 def BR_EQ : Expander<(brcond (seteq R32:$a1, R32:$a2),
747 basicblock:$d1, basicblock:$d2),
748 [(CMPrr32 R32:$a1, R32:$a2),
750 (JMP basicblock:$d2)]>;