1 //===----------------------------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
32 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
34 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTX86BrCond : SDTypeProfile<0, 3,
39 [SDTCisVT<0, OtherVT>,
40 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
42 def SDTX86SetCC : SDTypeProfile<1, 2,
44 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86SetCC_C : SDTypeProfile<1, 2,
47 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
49 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
51 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
53 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
54 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
55 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
57 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
58 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
61 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
63 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
67 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
69 def SDTX86Void : SDTypeProfile<0, 0, []>;
71 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
73 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
75 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
77 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
79 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
81 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
83 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
84 def SDT_X86MEMBARRIERNoSSE : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
86 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
88 def X86MemBarrierNoSSE : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIERNoSSE,
90 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
92 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
94 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
98 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
99 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
100 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
101 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
103 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
104 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
106 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
107 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
109 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
110 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
112 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
113 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
114 SDNPMayLoad, SDNPMemOperand]>;
115 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
116 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
117 SDNPMayLoad, SDNPMemOperand]>;
118 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
119 [SDNPHasChain, SDNPMayStore,
120 SDNPMayLoad, SDNPMemOperand]>;
121 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
122 [SDNPHasChain, SDNPMayStore,
123 SDNPMayLoad, SDNPMemOperand]>;
124 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
125 [SDNPHasChain, SDNPMayStore,
126 SDNPMayLoad, SDNPMemOperand]>;
127 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
128 [SDNPHasChain, SDNPMayStore,
129 SDNPMayLoad, SDNPMemOperand]>;
130 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
131 [SDNPHasChain, SDNPMayStore,
132 SDNPMayLoad, SDNPMemOperand]>;
133 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
134 [SDNPHasChain, SDNPMayStore,
135 SDNPMayLoad, SDNPMemOperand]>;
136 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
137 [SDNPHasChain, SDNPMayStore,
138 SDNPMayLoad, SDNPMemOperand]>;
139 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
140 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
142 def X86vastart_save_xmm_regs :
143 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
144 SDT_X86VASTART_SAVE_XMM_REGS,
145 [SDNPHasChain, SDNPVariadic]>;
147 def X86callseq_start :
148 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
149 [SDNPHasChain, SDNPOutFlag]>;
151 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
152 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
154 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
155 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
158 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
159 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
160 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
161 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
164 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
165 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
167 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
168 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
170 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
171 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
172 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
173 SDT_X86SegmentBaseAddress, []>;
175 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
178 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
179 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
181 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
183 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
184 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
186 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
189 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
190 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
191 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
193 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
195 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
198 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
200 def X86MingwAlloca : SDNode<"X86ISD::MINGW_ALLOCA", SDTX86Void,
201 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
203 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
206 //===----------------------------------------------------------------------===//
207 // X86 Operand Definitions.
210 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
211 // the index operand of an address, to conform to x86 encoding restrictions.
212 def ptr_rc_nosp : PointerLikeRegClass<1>;
214 // *mem - Operand definitions for the funky X86 addressing mode operands.
216 def X86MemAsmOperand : AsmOperandClass {
218 let SuperClasses = [];
220 def X86AbsMemAsmOperand : AsmOperandClass {
222 let SuperClasses = [X86MemAsmOperand];
224 class X86MemOperand<string printMethod> : Operand<iPTR> {
225 let PrintMethod = printMethod;
226 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
227 let ParserMatchClass = X86MemAsmOperand;
230 def opaque32mem : X86MemOperand<"printopaquemem">;
231 def opaque48mem : X86MemOperand<"printopaquemem">;
232 def opaque80mem : X86MemOperand<"printopaquemem">;
233 def opaque512mem : X86MemOperand<"printopaquemem">;
235 def i8mem : X86MemOperand<"printi8mem">;
236 def i16mem : X86MemOperand<"printi16mem">;
237 def i32mem : X86MemOperand<"printi32mem">;
238 def i64mem : X86MemOperand<"printi64mem">;
239 def i128mem : X86MemOperand<"printi128mem">;
240 def i256mem : X86MemOperand<"printi256mem">;
241 def f32mem : X86MemOperand<"printf32mem">;
242 def f64mem : X86MemOperand<"printf64mem">;
243 def f80mem : X86MemOperand<"printf80mem">;
244 def f128mem : X86MemOperand<"printf128mem">;
245 def f256mem : X86MemOperand<"printf256mem">;
247 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
248 // plain GR64, so that it doesn't potentially require a REX prefix.
249 def i8mem_NOREX : Operand<i64> {
250 let PrintMethod = "printi8mem";
251 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
252 let ParserMatchClass = X86MemAsmOperand;
255 // Special i32mem for addresses of load folding tail calls. These are not
256 // allowed to use callee-saved registers since they must be scheduled
257 // after callee-saved register are popped.
258 def i32mem_TC : Operand<i32> {
259 let PrintMethod = "printi32mem";
260 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
261 let ParserMatchClass = X86MemAsmOperand;
265 let ParserMatchClass = X86AbsMemAsmOperand,
266 PrintMethod = "print_pcrel_imm" in {
267 def i32imm_pcrel : Operand<i32>;
268 def i16imm_pcrel : Operand<i16>;
270 def offset8 : Operand<i64>;
271 def offset16 : Operand<i64>;
272 def offset32 : Operand<i64>;
273 def offset64 : Operand<i64>;
275 // Branch targets have OtherVT type and print as pc-relative values.
276 def brtarget : Operand<OtherVT>;
277 def brtarget8 : Operand<OtherVT>;
281 def SSECC : Operand<i8> {
282 let PrintMethod = "printSSECC";
285 class ImmSExtAsmOperandClass : AsmOperandClass {
286 let SuperClasses = [ImmAsmOperand];
287 let RenderMethod = "addImmOperands";
290 // Sign-extended immediate classes. We don't need to define the full lattice
291 // here because there is no instruction with an ambiguity between ImmSExti64i32
294 // The strange ranges come from the fact that the assembler always works with
295 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
296 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
299 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
300 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
301 let Name = "ImmSExti64i32";
304 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
305 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
306 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
307 let Name = "ImmSExti16i8";
308 let SuperClasses = [ImmSExti64i32AsmOperand];
311 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
312 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
313 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
314 let Name = "ImmSExti32i8";
318 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
319 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
320 let Name = "ImmSExti64i8";
321 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
322 ImmSExti64i32AsmOperand];
325 // A couple of more descriptive operand definitions.
326 // 16-bits but only 8 bits are significant.
327 def i16i8imm : Operand<i16> {
328 let ParserMatchClass = ImmSExti16i8AsmOperand;
330 // 32-bits but only 8 bits are significant.
331 def i32i8imm : Operand<i32> {
332 let ParserMatchClass = ImmSExti32i8AsmOperand;
335 //===----------------------------------------------------------------------===//
336 // X86 Complex Pattern Definitions.
339 // Define X86 specific addressing mode.
340 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
341 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
342 [add, sub, mul, X86mul_imm, shl, or, frameindex],
344 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
345 [tglobaltlsaddr], []>;
347 //===----------------------------------------------------------------------===//
348 // X86 Instruction Predicate Definitions.
349 def HasCMov : Predicate<"Subtarget->hasCMov()">;
350 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
352 // FIXME: temporary hack to let codegen assert or generate poor code in case
353 // no AVX version of the desired intructions is present, this is better for
354 // incremental dev (without fallbacks it's easier to spot what's missing)
355 def HasMMX : Predicate<"Subtarget->hasMMX() && !Subtarget->hasAVX()">;
356 def HasSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
357 def HasSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
358 def HasSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
359 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
360 def HasSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
361 def HasSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
362 def HasSSE4A : Predicate<"Subtarget->hasSSE4A() && !Subtarget->hasAVX()">;
364 def HasAVX : Predicate<"Subtarget->hasAVX()">;
365 def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">;
366 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
367 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
368 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
369 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
370 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
371 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
372 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
373 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
374 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
375 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
376 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
377 "TM.getCodeModel() != CodeModel::Kernel">;
378 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
379 "TM.getCodeModel() == CodeModel::Kernel">;
380 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
381 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
382 def OptForSize : Predicate<"OptForSize">;
383 def OptForSpeed : Predicate<"!OptForSize">;
384 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
385 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
386 def HasAES : Predicate<"Subtarget->hasAES()">;
388 //===----------------------------------------------------------------------===//
389 // X86 Instruction Format Definitions.
392 include "X86InstrFormats.td"
394 //===----------------------------------------------------------------------===//
395 // Pattern fragments...
398 // X86 specific condition code. These correspond to CondCode in
399 // X86InstrInfo.h. They must be kept in synch.
400 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
401 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
402 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
403 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
404 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
405 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
406 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
407 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
408 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
409 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
410 def X86_COND_NO : PatLeaf<(i8 10)>;
411 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
412 def X86_COND_NS : PatLeaf<(i8 12)>;
413 def X86_COND_O : PatLeaf<(i8 13)>;
414 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
415 def X86_COND_S : PatLeaf<(i8 15)>;
417 def immSext8 : PatLeaf<(imm), [{ return immSext8(N); }]>;
419 def i16immSExt8 : PatLeaf<(i16 immSext8)>;
420 def i32immSExt8 : PatLeaf<(i32 immSext8)>;
422 // Helper fragments for loads.
423 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
424 // known to be 32-bit aligned or better. Ditto for i8 to i16.
425 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
426 LoadSDNode *LD = cast<LoadSDNode>(N);
427 ISD::LoadExtType ExtType = LD->getExtensionType();
428 if (ExtType == ISD::NON_EXTLOAD)
430 if (ExtType == ISD::EXTLOAD)
431 return LD->getAlignment() >= 2 && !LD->isVolatile();
435 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
436 LoadSDNode *LD = cast<LoadSDNode>(N);
437 ISD::LoadExtType ExtType = LD->getExtensionType();
438 if (ExtType == ISD::EXTLOAD)
439 return LD->getAlignment() >= 2 && !LD->isVolatile();
443 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
444 LoadSDNode *LD = cast<LoadSDNode>(N);
445 ISD::LoadExtType ExtType = LD->getExtensionType();
446 if (ExtType == ISD::NON_EXTLOAD)
448 if (ExtType == ISD::EXTLOAD)
449 return LD->getAlignment() >= 4 && !LD->isVolatile();
453 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
454 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
455 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
456 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
457 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
459 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
460 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
461 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
463 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
464 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
465 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
466 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
467 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
468 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
470 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
471 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
472 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
473 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
474 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
475 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
478 // An 'and' node with a single use.
479 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
480 return N->hasOneUse();
482 // An 'srl' node with a single use.
483 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
484 return N->hasOneUse();
486 // An 'trunc' node with a single use.
487 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
488 return N->hasOneUse();
491 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
492 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
493 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
494 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
496 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
497 APInt Mask = APInt::getAllOnesValue(BitWidth);
498 APInt KnownZero0, KnownOne0;
499 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
500 APInt KnownZero1, KnownOne1;
501 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
502 return (~KnownZero0 & ~KnownZero1) == 0;
505 //===----------------------------------------------------------------------===//
506 // Instruction list...
509 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
510 // a stack adjustment and the codegen must know that they may modify the stack
511 // pointer before prolog-epilog rewriting occurs.
512 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
513 // sub / add which can clobber EFLAGS.
514 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
515 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
517 [(X86callseq_start timm:$amt)]>,
518 Requires<[In32BitMode]>;
519 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
521 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
522 Requires<[In32BitMode]>;
525 // x86-64 va_start lowering magic.
526 let usesCustomInserter = 1 in {
527 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
530 i64imm:$regsavefi, i64imm:$offset,
532 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
533 [(X86vastart_save_xmm_regs GR8:$al,
537 // Dynamic stack allocation yields _alloca call for Cygwin/Mingw targets. Calls
538 // to _alloca is needed to probe the stack when allocating more than 4k bytes in
539 // one go. Touching the stack at 4K increments is necessary to ensure that the
540 // guard pages used by the OS virtual memory manager are allocated in correct
542 // The main point of having separate instruction are extra unmodelled effects
543 // (compared to ordinary calls) like stack pointer change.
545 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
546 def MINGW_ALLOCA : I<0, Pseudo, (outs), (ins),
547 "# dynamic stack allocation",
552 let neverHasSideEffects = 1 in {
553 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
554 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
555 "nop{w}\t$zero", []>, TB, OpSize;
556 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
557 "nop{l}\t$zero", []>, TB;
561 let Uses = [EFLAGS] in {
562 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
564 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
565 [(int_x86_int (i8 3))]>;
566 def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
567 [(int_x86_int imm:$trap)]>;
568 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iretw", []>, OpSize;
569 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>;
571 // PIC base construction. This expands to code that looks like this:
574 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
575 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
578 //===----------------------------------------------------------------------===//
579 // Control Flow Instructions.
582 // Return instructions.
583 let isTerminator = 1, isReturn = 1, isBarrier = 1,
584 hasCtrlDep = 1, FPForm = SpecialFP in {
585 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
588 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
590 [(X86retflag timm:$amt)]>;
591 def LRET : I <0xCB, RawFrm, (outs), (ins),
593 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
597 // Unconditional branches.
598 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
599 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
600 "jmp\t$dst", [(br bb:$dst)]>;
601 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
605 // Conditional Branches.
606 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
607 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
608 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
609 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
610 [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
614 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
615 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
616 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
617 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
618 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
619 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
620 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
621 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
622 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
623 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
624 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
625 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
626 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
627 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
628 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
629 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
631 // jcx/jecx/jrcx instructions.
632 let isAsmParserOnly = 1, isBranch = 1, isTerminator = 1 in {
633 // These are the 32-bit versions of this instruction for the asmparser. In
634 // 32-bit mode, the address size prefix is jcxz and the unprefixed version is
637 def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
638 "jcxz\t$dst", []>, AdSize, Requires<[In32BitMode]>;
640 def JECXZ_32 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
641 "jecxz\t$dst", []>, Requires<[In32BitMode]>;
643 // J*CXZ instruction: 64-bit versions of this instruction for the asmparser.
644 // In 64-bit mode, the address size prefix is jecxz and the unprefixed version
647 def JECXZ_64 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
648 "jecxz\t$dst", []>, AdSize, Requires<[In64BitMode]>;
650 def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
651 "jrcxz\t$dst", []>, Requires<[In64BitMode]>;
656 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
657 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
658 [(brind GR32:$dst)]>, Requires<[In32BitMode]>;
659 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
660 [(brind (loadi32 addr:$dst))]>, Requires<[In32BitMode]>;
662 def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
663 (ins i16imm:$off, i16imm:$seg),
664 "ljmp{w}\t{$seg, $off|$off, $seg}", []>, OpSize;
665 def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
666 (ins i32imm:$off, i16imm:$seg),
667 "ljmp{l}\t{$seg, $off|$off, $seg}", []>;
669 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
670 "ljmp{w}\t{*}$dst", []>, OpSize;
671 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
672 "ljmp{l}\t{*}$dst", []>;
678 def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>;
679 def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>;
680 def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>;
682 //===----------------------------------------------------------------------===//
683 // Call Instructions...
686 // All calls clobber the non-callee saved registers. ESP is marked as
687 // a use to prevent stack-pointer assignments that appear immediately
688 // before calls from potentially appearing dead. Uses for argument
689 // registers are added manually.
690 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
691 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
692 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
693 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
695 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
696 (outs), (ins i32imm_pcrel:$dst,variable_ops),
698 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
699 "call\t{*}$dst", [(X86call GR32:$dst)]>;
700 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
701 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
703 def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
704 (ins i16imm:$off, i16imm:$seg),
705 "lcall{w}\t{$seg, $off|$off, $seg}", []>, OpSize;
706 def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
707 (ins i32imm:$off, i16imm:$seg),
708 "lcall{l}\t{$seg, $off|$off, $seg}", []>;
710 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
711 "lcall{w}\t{*}$dst", []>, OpSize;
712 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
713 "lcall{l}\t{*}$dst", []>;
715 // callw for 16 bit code for the assembler.
716 let isAsmParserOnly = 1 in
717 def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
718 (outs), (ins i16imm_pcrel:$dst, variable_ops),
719 "callw\t$dst", []>, OpSize;
722 // Constructing a stack frame.
724 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
725 "enter\t$len, $lvl", []>;
729 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
731 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
732 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
733 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
734 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
736 def TCRETURNdi : I<0, Pseudo, (outs),
737 (ins i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
738 "#TC_RETURN $dst $offset", []>;
739 def TCRETURNri : I<0, Pseudo, (outs),
740 (ins GR32_TC:$dst, i32imm:$offset, variable_ops),
741 "#TC_RETURN $dst $offset", []>;
743 def TCRETURNmi : I<0, Pseudo, (outs),
744 (ins i32mem_TC:$dst, i32imm:$offset, variable_ops),
745 "#TC_RETURN $dst $offset", []>;
747 // FIXME: The should be pseudo instructions that are lowered when going to
749 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
750 (ins i32imm_pcrel:$dst, variable_ops),
751 "jmp\t$dst # TAILCALL",
753 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops),
754 "", []>; // FIXME: Remove encoding when JIT is dead.
756 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops),
757 "jmp{l}\t{*}$dst # TAILCALL", []>;
760 //===----------------------------------------------------------------------===//
761 // Miscellaneous Instructions...
763 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
764 def LEAVE : I<0xC9, RawFrm,
765 (outs), (ins), "leave", []>, Requires<[In32BitMode]>;
767 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
768 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
770 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
771 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
772 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
773 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
775 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
776 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
778 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
780 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
782 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
783 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
785 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
787 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
788 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
791 let mayStore = 1 in {
792 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
794 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
795 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
797 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
799 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
800 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
804 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
805 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
806 "push{l}\t$imm", []>;
807 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
808 "push{w}\t$imm", []>, OpSize;
809 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
810 "push{l}\t$imm", []>;
813 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
814 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
815 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
816 Requires<[In32BitMode]>;
818 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
819 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
820 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
821 Requires<[In32BitMode]>;
824 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
825 mayLoad=1, neverHasSideEffects=1 in {
826 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>,
827 Requires<[In32BitMode]>;
829 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
830 mayStore=1, neverHasSideEffects=1 in {
831 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>,
832 Requires<[In32BitMode]>;
835 let Uses = [EFLAGS], Constraints = "$src = $dst" in // GR32 = bswap GR32
836 def BSWAP32r : I<0xC8, AddRegFrm,
837 (outs GR32:$dst), (ins GR32:$src),
839 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
842 // Bit scan instructions.
843 let Defs = [EFLAGS] in {
844 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
845 "bsf{w}\t{$src, $dst|$dst, $src}",
846 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
847 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
848 "bsf{w}\t{$src, $dst|$dst, $src}",
849 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
851 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
852 "bsf{l}\t{$src, $dst|$dst, $src}",
853 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
854 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
855 "bsf{l}\t{$src, $dst|$dst, $src}",
856 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
858 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
859 "bsr{w}\t{$src, $dst|$dst, $src}",
860 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
861 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
862 "bsr{w}\t{$src, $dst|$dst, $src}",
863 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
865 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
866 "bsr{l}\t{$src, $dst|$dst, $src}",
867 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
868 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
869 "bsr{l}\t{$src, $dst|$dst, $src}",
870 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
873 let neverHasSideEffects = 1 in
874 def LEA16r : I<0x8D, MRMSrcMem,
875 (outs GR16:$dst), (ins i32mem:$src),
876 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
877 let isReMaterializable = 1 in
878 def LEA32r : I<0x8D, MRMSrcMem,
879 (outs GR32:$dst), (ins i32mem:$src),
880 "lea{l}\t{$src|$dst}, {$dst|$src}",
881 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
883 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
884 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
885 [(X86rep_movs i8)]>, REP;
886 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
887 [(X86rep_movs i16)]>, REP, OpSize;
888 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
889 [(X86rep_movs i32)]>, REP;
892 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
893 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
894 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
895 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
896 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
899 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
900 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
901 [(X86rep_stos i8)]>, REP;
902 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
903 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
904 [(X86rep_stos i16)]>, REP, OpSize;
905 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
906 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
907 [(X86rep_stos i32)]>, REP;
909 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
910 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
911 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
912 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
913 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
914 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
915 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
917 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
918 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
919 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
921 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
922 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
923 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
925 let Defs = [RAX, RDX] in
926 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
929 let Defs = [RAX, RCX, RDX] in
930 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
932 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
933 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
936 def SYSCALL : I<0x05, RawFrm,
937 (outs), (ins), "syscall", []>, TB;
938 def SYSRETL : I<0x07, RawFrm,
939 (outs), (ins), "sysretl", []>, TB;
940 def SYSENTER : I<0x34, RawFrm,
941 (outs), (ins), "sysenter", []>, TB;
942 def SYSEXIT : I<0x35, RawFrm,
943 (outs), (ins), "sysexit", []>, TB, Requires<[In32BitMode]>;
945 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
948 //===----------------------------------------------------------------------===//
949 // Input/Output Instructions...
951 let Defs = [AL], Uses = [DX] in
952 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
953 "in{b}\t{%dx, %al|%AL, %DX}", []>;
954 let Defs = [AX], Uses = [DX] in
955 def IN16rr : I<0xED, RawFrm, (outs), (ins),
956 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
957 let Defs = [EAX], Uses = [DX] in
958 def IN32rr : I<0xED, RawFrm, (outs), (ins),
959 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
962 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
963 "in{b}\t{$port, %al|%AL, $port}", []>;
965 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
966 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
968 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
969 "in{l}\t{$port, %eax|%EAX, $port}", []>;
971 let Uses = [DX, AL] in
972 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
973 "out{b}\t{%al, %dx|%DX, %AL}", []>;
974 let Uses = [DX, AX] in
975 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
976 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
977 let Uses = [DX, EAX] in
978 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
979 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
982 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
983 "out{b}\t{%al, $port|$port, %AL}", []>;
985 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
986 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
988 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
989 "out{l}\t{%eax, $port|$port, %EAX}", []>;
991 def IN8 : I<0x6C, RawFrm, (outs), (ins),
993 def IN16 : I<0x6D, RawFrm, (outs), (ins),
994 "ins{w}", []>, OpSize;
995 def IN32 : I<0x6D, RawFrm, (outs), (ins),
998 //===----------------------------------------------------------------------===//
999 // Move Instructions...
1001 let neverHasSideEffects = 1 in {
1002 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1003 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1004 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1005 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1006 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1007 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1009 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1010 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1011 "mov{b}\t{$src, $dst|$dst, $src}",
1012 [(set GR8:$dst, imm:$src)]>;
1013 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1014 "mov{w}\t{$src, $dst|$dst, $src}",
1015 [(set GR16:$dst, imm:$src)]>, OpSize;
1016 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1017 "mov{l}\t{$src, $dst|$dst, $src}",
1018 [(set GR32:$dst, imm:$src)]>;
1021 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1022 "mov{b}\t{$src, $dst|$dst, $src}",
1023 [(store (i8 imm:$src), addr:$dst)]>;
1024 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1025 "mov{w}\t{$src, $dst|$dst, $src}",
1026 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
1027 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1028 "mov{l}\t{$src, $dst|$dst, $src}",
1029 [(store (i32 imm:$src), addr:$dst)]>;
1031 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
1032 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
1033 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
1034 "mov{b}\t{$src, %al|%al, $src}", []>,
1035 Requires<[In32BitMode]>;
1036 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
1037 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize,
1038 Requires<[In32BitMode]>;
1039 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1040 "mov{l}\t{$src, %eax|%eax, $src}", []>,
1041 Requires<[In32BitMode]>;
1042 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1043 "mov{b}\t{%al, $dst|$dst, %al}", []>,
1044 Requires<[In32BitMode]>;
1045 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1046 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize,
1047 Requires<[In32BitMode]>;
1048 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1049 "mov{l}\t{%eax, $dst|$dst, %eax}", []>,
1050 Requires<[In32BitMode]>;
1052 // Moves to and from segment registers
1053 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
1054 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1055 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
1056 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1057 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
1058 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1059 def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
1060 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1061 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
1062 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1063 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
1064 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1065 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
1066 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1067 def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
1068 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1070 let isCodeGenOnly = 1 in {
1071 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1072 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1073 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1074 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1075 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1076 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1079 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1080 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1081 "mov{b}\t{$src, $dst|$dst, $src}",
1082 [(set GR8:$dst, (loadi8 addr:$src))]>;
1083 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1084 "mov{w}\t{$src, $dst|$dst, $src}",
1085 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
1086 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1087 "mov{l}\t{$src, $dst|$dst, $src}",
1088 [(set GR32:$dst, (loadi32 addr:$src))]>;
1091 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1092 "mov{b}\t{$src, $dst|$dst, $src}",
1093 [(store GR8:$src, addr:$dst)]>;
1094 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1095 "mov{w}\t{$src, $dst|$dst, $src}",
1096 [(store GR16:$src, addr:$dst)]>, OpSize;
1097 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1098 "mov{l}\t{$src, $dst|$dst, $src}",
1099 [(store GR32:$src, addr:$dst)]>;
1101 /// Versions of MOV32rr, MOV32rm, and MOV32mr for i32mem_TC and GR32_TC.
1102 let isCodeGenOnly = 1 in {
1103 let neverHasSideEffects = 1 in
1104 def MOV32rr_TC : I<0x89, MRMDestReg, (outs GR32_TC:$dst), (ins GR32_TC:$src),
1105 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1108 canFoldAsLoad = 1, isReMaterializable = 1 in
1109 def MOV32rm_TC : I<0x8B, MRMSrcMem, (outs GR32_TC:$dst), (ins i32mem_TC:$src),
1110 "mov{l}\t{$src, $dst|$dst, $src}",
1114 def MOV32mr_TC : I<0x89, MRMDestMem, (outs), (ins i32mem_TC:$dst, GR32_TC:$src),
1115 "mov{l}\t{$src, $dst|$dst, $src}",
1119 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1120 // that they can be used for copying and storing h registers, which can't be
1121 // encoded when a REX prefix is present.
1122 let isCodeGenOnly = 1 in {
1123 let neverHasSideEffects = 1 in
1124 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1125 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1126 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1128 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1129 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1130 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1132 canFoldAsLoad = 1, isReMaterializable = 1 in
1133 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1134 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1135 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1138 // Moves to and from debug registers
1139 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
1140 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1141 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
1142 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1144 // Moves to and from control registers
1145 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
1146 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1147 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
1148 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1150 //===----------------------------------------------------------------------===//
1151 // Fixed-Register Multiplication and Division Instructions...
1154 // Extra precision multiplication
1156 // AL is really implied by AX, but the registers in Defs must match the
1157 // SDNode results (i8, i32).
1158 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1159 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
1160 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1161 // This probably ought to be moved to a def : Pat<> if the
1162 // syntax can be accepted.
1163 [(set AL, (mul AL, GR8:$src)),
1164 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1166 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1167 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1169 []>, OpSize; // AX,DX = AX*GR16
1171 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1172 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1174 []>; // EAX,EDX = EAX*GR32
1176 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1177 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1179 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1180 // This probably ought to be moved to a def : Pat<> if the
1181 // syntax can be accepted.
1182 [(set AL, (mul AL, (loadi8 addr:$src))),
1183 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1185 let mayLoad = 1, neverHasSideEffects = 1 in {
1186 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1187 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1189 []>, OpSize; // AX,DX = AX*[mem16]
1191 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1192 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1194 []>; // EAX,EDX = EAX*[mem32]
1197 let neverHasSideEffects = 1 in {
1198 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1199 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1201 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1202 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1203 OpSize; // AX,DX = AX*GR16
1204 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1205 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1206 // EAX,EDX = EAX*GR32
1207 let mayLoad = 1 in {
1208 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1209 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1210 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1211 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1212 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1213 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1214 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1215 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1216 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1218 } // neverHasSideEffects
1220 // unsigned division/remainder
1221 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1222 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1223 "div{b}\t$src", []>;
1224 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1225 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1226 "div{w}\t$src", []>, OpSize;
1227 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1228 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1229 "div{l}\t$src", []>;
1230 let mayLoad = 1 in {
1231 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1232 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1233 "div{b}\t$src", []>;
1234 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1235 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1236 "div{w}\t$src", []>, OpSize;
1237 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1238 // EDX:EAX/[mem32] = EAX,EDX
1239 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
1240 "div{l}\t$src", []>;
1243 // Signed division/remainder.
1244 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1245 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1246 "idiv{b}\t$src", []>;
1247 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1248 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1249 "idiv{w}\t$src", []>, OpSize;
1250 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1251 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1252 "idiv{l}\t$src", []>;
1253 let mayLoad = 1, mayLoad = 1 in {
1254 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1255 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1256 "idiv{b}\t$src", []>;
1257 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1258 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1259 "idiv{w}\t$src", []>, OpSize;
1260 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1261 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1262 // EDX:EAX/[mem32] = EAX,EDX
1263 "idiv{l}\t$src", []>;
1266 //===----------------------------------------------------------------------===//
1267 // Two address Instructions.
1269 let Constraints = "$src1 = $dst" in {
1271 // Conditional moves
1272 let Uses = [EFLAGS] in {
1274 let Predicates = [HasCMov] in {
1275 let isCommutable = 1 in {
1276 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1277 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1278 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1279 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1280 X86_COND_B, EFLAGS))]>,
1282 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1283 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1284 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1285 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1286 X86_COND_B, EFLAGS))]>,
1288 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1289 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1290 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1291 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1292 X86_COND_AE, EFLAGS))]>,
1294 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1295 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1296 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1297 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1298 X86_COND_AE, EFLAGS))]>,
1300 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1301 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1302 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1303 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1304 X86_COND_E, EFLAGS))]>,
1306 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1307 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1308 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1309 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1310 X86_COND_E, EFLAGS))]>,
1312 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1313 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1314 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1315 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1316 X86_COND_NE, EFLAGS))]>,
1318 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1319 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1320 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1321 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1322 X86_COND_NE, EFLAGS))]>,
1324 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1325 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1326 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1327 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1328 X86_COND_BE, EFLAGS))]>,
1330 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1331 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1332 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1333 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1334 X86_COND_BE, EFLAGS))]>,
1336 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1337 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1338 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1339 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1340 X86_COND_A, EFLAGS))]>,
1342 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1343 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1344 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1345 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1346 X86_COND_A, EFLAGS))]>,
1348 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1349 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1350 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1351 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1352 X86_COND_L, EFLAGS))]>,
1354 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1355 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1356 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1357 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1358 X86_COND_L, EFLAGS))]>,
1360 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1361 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1362 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1363 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1364 X86_COND_GE, EFLAGS))]>,
1366 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1367 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1368 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1369 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1370 X86_COND_GE, EFLAGS))]>,
1372 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1373 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1374 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1375 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1376 X86_COND_LE, EFLAGS))]>,
1378 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1379 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1380 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1381 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1382 X86_COND_LE, EFLAGS))]>,
1384 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1385 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1386 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1387 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1388 X86_COND_G, EFLAGS))]>,
1390 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1391 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1392 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1393 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1394 X86_COND_G, EFLAGS))]>,
1396 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1397 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1398 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1399 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1400 X86_COND_S, EFLAGS))]>,
1402 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1403 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1404 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1405 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1406 X86_COND_S, EFLAGS))]>,
1408 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1409 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1410 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1411 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1412 X86_COND_NS, EFLAGS))]>,
1414 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1415 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1416 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1417 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1418 X86_COND_NS, EFLAGS))]>,
1420 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1421 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1422 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1423 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1424 X86_COND_P, EFLAGS))]>,
1426 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1427 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1428 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1429 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1430 X86_COND_P, EFLAGS))]>,
1432 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1433 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1434 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1435 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1436 X86_COND_NP, EFLAGS))]>,
1438 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1439 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1440 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1441 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1442 X86_COND_NP, EFLAGS))]>,
1444 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1445 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1446 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1447 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1448 X86_COND_O, EFLAGS))]>,
1450 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1451 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1452 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1453 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1454 X86_COND_O, EFLAGS))]>,
1456 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1457 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1458 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1459 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1460 X86_COND_NO, EFLAGS))]>,
1462 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1463 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1464 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1465 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1466 X86_COND_NO, EFLAGS))]>,
1468 } // isCommutable = 1
1470 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1471 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1472 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1473 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1474 X86_COND_B, EFLAGS))]>,
1476 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1477 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1478 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1479 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1480 X86_COND_B, EFLAGS))]>,
1482 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1483 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1484 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1485 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1486 X86_COND_AE, EFLAGS))]>,
1488 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1489 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1490 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1491 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1492 X86_COND_AE, EFLAGS))]>,
1494 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1495 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1496 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1497 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1498 X86_COND_E, EFLAGS))]>,
1500 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1501 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1502 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1503 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1504 X86_COND_E, EFLAGS))]>,
1506 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1507 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1508 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1509 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1510 X86_COND_NE, EFLAGS))]>,
1512 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1513 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1514 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1515 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1516 X86_COND_NE, EFLAGS))]>,
1518 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1519 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1520 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1521 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1522 X86_COND_BE, EFLAGS))]>,
1524 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1525 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1526 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1527 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1528 X86_COND_BE, EFLAGS))]>,
1530 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1531 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1532 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1533 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1534 X86_COND_A, EFLAGS))]>,
1536 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1537 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1538 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1539 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1540 X86_COND_A, EFLAGS))]>,
1542 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1543 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1544 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1545 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1546 X86_COND_L, EFLAGS))]>,
1548 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1549 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1550 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1551 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1552 X86_COND_L, EFLAGS))]>,
1554 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1555 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1556 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1557 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1558 X86_COND_GE, EFLAGS))]>,
1560 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1561 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1562 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1563 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1564 X86_COND_GE, EFLAGS))]>,
1566 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1567 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1568 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1569 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1570 X86_COND_LE, EFLAGS))]>,
1572 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1573 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1574 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1575 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1576 X86_COND_LE, EFLAGS))]>,
1578 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1579 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1580 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1581 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1582 X86_COND_G, EFLAGS))]>,
1584 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1585 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1586 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1587 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1588 X86_COND_G, EFLAGS))]>,
1590 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1591 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1592 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1593 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1594 X86_COND_S, EFLAGS))]>,
1596 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1597 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1598 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1599 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1600 X86_COND_S, EFLAGS))]>,
1602 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1603 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1604 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1605 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1606 X86_COND_NS, EFLAGS))]>,
1608 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1609 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1610 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1611 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1612 X86_COND_NS, EFLAGS))]>,
1614 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1615 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1616 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1617 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1618 X86_COND_P, EFLAGS))]>,
1620 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1621 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1622 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1623 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1624 X86_COND_P, EFLAGS))]>,
1626 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1627 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1628 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1629 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1630 X86_COND_NP, EFLAGS))]>,
1632 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1633 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1634 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1635 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1636 X86_COND_NP, EFLAGS))]>,
1638 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1639 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1640 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1641 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1642 X86_COND_O, EFLAGS))]>,
1644 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1645 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1646 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1647 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1648 X86_COND_O, EFLAGS))]>,
1650 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1651 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1652 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1653 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1654 X86_COND_NO, EFLAGS))]>,
1656 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1657 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1658 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1659 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1660 X86_COND_NO, EFLAGS))]>,
1662 } // Predicates = [HasCMov]
1664 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1665 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1666 // however that requires promoting the operands, and can induce additional
1667 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1668 // clobber EFLAGS, because if one of the operands is zero, the expansion
1669 // could involve an xor.
1670 let usesCustomInserter = 1, Constraints = "", Defs = [EFLAGS] in {
1671 def CMOV_GR8 : I<0, Pseudo,
1672 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1673 "#CMOV_GR8 PSEUDO!",
1674 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1675 imm:$cond, EFLAGS))]>;
1677 let Predicates = [NoCMov] in {
1678 def CMOV_GR32 : I<0, Pseudo,
1679 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
1680 "#CMOV_GR32* PSEUDO!",
1682 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
1683 def CMOV_GR16 : I<0, Pseudo,
1684 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
1685 "#CMOV_GR16* PSEUDO!",
1687 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
1688 def CMOV_RFP32 : I<0, Pseudo,
1690 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
1691 "#CMOV_RFP32 PSEUDO!",
1693 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
1695 def CMOV_RFP64 : I<0, Pseudo,
1697 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
1698 "#CMOV_RFP64 PSEUDO!",
1700 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
1702 def CMOV_RFP80 : I<0, Pseudo,
1704 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
1705 "#CMOV_RFP80 PSEUDO!",
1707 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
1709 } // Predicates = [NoCMov]
1710 } // UsesCustomInserter = 1, Constraints = "", Defs = [EFLAGS]
1711 } // Uses = [EFLAGS]
1714 // unary instructions
1715 let CodeSize = 2 in {
1716 let Defs = [EFLAGS] in {
1717 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
1719 [(set GR8:$dst, (ineg GR8:$src1)),
1720 (implicit EFLAGS)]>;
1721 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
1723 [(set GR16:$dst, (ineg GR16:$src1)),
1724 (implicit EFLAGS)]>, OpSize;
1725 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
1727 [(set GR32:$dst, (ineg GR32:$src1)),
1728 (implicit EFLAGS)]>;
1730 let Constraints = "" in {
1731 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
1733 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1734 (implicit EFLAGS)]>;
1735 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
1737 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1738 (implicit EFLAGS)]>, OpSize;
1739 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
1741 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1742 (implicit EFLAGS)]>;
1743 } // Constraints = ""
1744 } // Defs = [EFLAGS]
1746 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1747 let AddedComplexity = 15 in {
1748 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
1750 [(set GR8:$dst, (not GR8:$src1))]>;
1751 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
1753 [(set GR16:$dst, (not GR16:$src1))]>, OpSize;
1754 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
1756 [(set GR32:$dst, (not GR32:$src1))]>;
1758 let Constraints = "" in {
1759 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
1761 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1762 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
1764 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1765 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
1767 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1768 } // Constraints = ""
1771 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1772 let Defs = [EFLAGS] in {
1774 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1776 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>;
1778 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1779 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
1781 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
1782 OpSize, Requires<[In32BitMode]>;
1783 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
1785 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
1786 Requires<[In32BitMode]>;
1788 let Constraints = "", CodeSize = 2 in {
1789 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1790 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1791 (implicit EFLAGS)]>;
1792 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1793 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1794 (implicit EFLAGS)]>,
1795 OpSize, Requires<[In32BitMode]>;
1796 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1797 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1798 (implicit EFLAGS)]>,
1799 Requires<[In32BitMode]>;
1800 } // Constraints = "", CodeSize = 2
1803 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1805 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>;
1806 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1807 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
1809 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
1810 OpSize, Requires<[In32BitMode]>;
1811 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
1813 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
1814 Requires<[In32BitMode]>;
1817 let Constraints = "", CodeSize = 2 in {
1818 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1819 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1820 (implicit EFLAGS)]>;
1821 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1822 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1823 (implicit EFLAGS)]>,
1824 OpSize, Requires<[In32BitMode]>;
1825 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1826 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1827 (implicit EFLAGS)]>,
1828 Requires<[In32BitMode]>;
1829 } // Constraints = "", CodeSize = 2
1830 } // Defs = [EFLAGS]
1832 // Logical operators...
1833 let Defs = [EFLAGS] in {
1834 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1835 def AND8rr : I<0x20, MRMDestReg,
1836 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1837 "and{b}\t{$src2, $dst|$dst, $src2}",
1838 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, GR8:$src2))]>;
1839 def AND16rr : I<0x21, MRMDestReg,
1840 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1841 "and{w}\t{$src2, $dst|$dst, $src2}",
1842 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1843 GR16:$src2))]>, OpSize;
1844 def AND32rr : I<0x21, MRMDestReg,
1845 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1846 "and{l}\t{$src2, $dst|$dst, $src2}",
1847 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1851 // AND instructions with the destination register in REG and the source register
1852 // in R/M. Included for the disassembler.
1853 let isCodeGenOnly = 1 in {
1854 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1855 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1856 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1857 (ins GR16:$src1, GR16:$src2),
1858 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1859 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1860 (ins GR32:$src1, GR32:$src2),
1861 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1864 def AND8rm : I<0x22, MRMSrcMem,
1865 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1866 "and{b}\t{$src2, $dst|$dst, $src2}",
1867 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1868 (loadi8 addr:$src2)))]>;
1869 def AND16rm : I<0x23, MRMSrcMem,
1870 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1871 "and{w}\t{$src2, $dst|$dst, $src2}",
1872 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1873 (loadi16 addr:$src2)))]>,
1875 def AND32rm : I<0x23, MRMSrcMem,
1876 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1877 "and{l}\t{$src2, $dst|$dst, $src2}",
1878 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1879 (loadi32 addr:$src2)))]>;
1881 def AND8ri : Ii8<0x80, MRM4r,
1882 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1883 "and{b}\t{$src2, $dst|$dst, $src2}",
1884 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1886 def AND16ri : Ii16<0x81, MRM4r,
1887 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1888 "and{w}\t{$src2, $dst|$dst, $src2}",
1889 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1890 imm:$src2))]>, OpSize;
1891 def AND32ri : Ii32<0x81, MRM4r,
1892 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1893 "and{l}\t{$src2, $dst|$dst, $src2}",
1894 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1896 def AND16ri8 : Ii8<0x83, MRM4r,
1897 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1898 "and{w}\t{$src2, $dst|$dst, $src2}",
1899 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1900 i16immSExt8:$src2))]>,
1902 def AND32ri8 : Ii8<0x83, MRM4r,
1903 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1904 "and{l}\t{$src2, $dst|$dst, $src2}",
1905 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1906 i32immSExt8:$src2))]>;
1908 let Constraints = "" in {
1909 def AND8mr : I<0x20, MRMDestMem,
1910 (outs), (ins i8mem :$dst, GR8 :$src),
1911 "and{b}\t{$src, $dst|$dst, $src}",
1912 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1913 (implicit EFLAGS)]>;
1914 def AND16mr : I<0x21, MRMDestMem,
1915 (outs), (ins i16mem:$dst, GR16:$src),
1916 "and{w}\t{$src, $dst|$dst, $src}",
1917 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1918 (implicit EFLAGS)]>,
1920 def AND32mr : I<0x21, MRMDestMem,
1921 (outs), (ins i32mem:$dst, GR32:$src),
1922 "and{l}\t{$src, $dst|$dst, $src}",
1923 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1924 (implicit EFLAGS)]>;
1925 def AND8mi : Ii8<0x80, MRM4m,
1926 (outs), (ins i8mem :$dst, i8imm :$src),
1927 "and{b}\t{$src, $dst|$dst, $src}",
1928 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1929 (implicit EFLAGS)]>;
1930 def AND16mi : Ii16<0x81, MRM4m,
1931 (outs), (ins i16mem:$dst, i16imm:$src),
1932 "and{w}\t{$src, $dst|$dst, $src}",
1933 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1934 (implicit EFLAGS)]>,
1936 def AND32mi : Ii32<0x81, MRM4m,
1937 (outs), (ins i32mem:$dst, i32imm:$src),
1938 "and{l}\t{$src, $dst|$dst, $src}",
1939 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1940 (implicit EFLAGS)]>;
1941 def AND16mi8 : Ii8<0x83, MRM4m,
1942 (outs), (ins i16mem:$dst, i16i8imm :$src),
1943 "and{w}\t{$src, $dst|$dst, $src}",
1944 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1945 (implicit EFLAGS)]>,
1947 def AND32mi8 : Ii8<0x83, MRM4m,
1948 (outs), (ins i32mem:$dst, i32i8imm :$src),
1949 "and{l}\t{$src, $dst|$dst, $src}",
1950 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1951 (implicit EFLAGS)]>;
1953 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1954 "and{b}\t{$src, %al|%al, $src}", []>;
1955 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1956 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1957 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1958 "and{l}\t{$src, %eax|%eax, $src}", []>;
1960 } // Constraints = ""
1963 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1964 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1965 (ins GR8 :$src1, GR8 :$src2),
1966 "or{b}\t{$src2, $dst|$dst, $src2}",
1967 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
1968 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1969 (ins GR16:$src1, GR16:$src2),
1970 "or{w}\t{$src2, $dst|$dst, $src2}",
1971 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
1973 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1974 (ins GR32:$src1, GR32:$src2),
1975 "or{l}\t{$src2, $dst|$dst, $src2}",
1976 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
1979 // OR instructions with the destination register in REG and the source register
1980 // in R/M. Included for the disassembler.
1981 let isCodeGenOnly = 1 in {
1982 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1983 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1984 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1985 (ins GR16:$src1, GR16:$src2),
1986 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1987 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1988 (ins GR32:$src1, GR32:$src2),
1989 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
1992 def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst),
1993 (ins GR8 :$src1, i8mem :$src2),
1994 "or{b}\t{$src2, $dst|$dst, $src2}",
1995 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
1996 (load addr:$src2)))]>;
1997 def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst),
1998 (ins GR16:$src1, i16mem:$src2),
1999 "or{w}\t{$src2, $dst|$dst, $src2}",
2000 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
2001 (load addr:$src2)))]>,
2003 def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst),
2004 (ins GR32:$src1, i32mem:$src2),
2005 "or{l}\t{$src2, $dst|$dst, $src2}",
2006 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
2007 (load addr:$src2)))]>;
2009 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
2010 (ins GR8 :$src1, i8imm:$src2),
2011 "or{b}\t{$src2, $dst|$dst, $src2}",
2012 [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
2013 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
2014 (ins GR16:$src1, i16imm:$src2),
2015 "or{w}\t{$src2, $dst|$dst, $src2}",
2016 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
2017 imm:$src2))]>, OpSize;
2018 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
2019 (ins GR32:$src1, i32imm:$src2),
2020 "or{l}\t{$src2, $dst|$dst, $src2}",
2021 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
2024 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
2025 (ins GR16:$src1, i16i8imm:$src2),
2026 "or{w}\t{$src2, $dst|$dst, $src2}",
2027 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
2028 i16immSExt8:$src2))]>, OpSize;
2029 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
2030 (ins GR32:$src1, i32i8imm:$src2),
2031 "or{l}\t{$src2, $dst|$dst, $src2}",
2032 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
2033 i32immSExt8:$src2))]>;
2034 let Constraints = "" in {
2035 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
2036 "or{b}\t{$src, $dst|$dst, $src}",
2037 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
2038 (implicit EFLAGS)]>;
2039 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
2040 "or{w}\t{$src, $dst|$dst, $src}",
2041 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
2042 (implicit EFLAGS)]>, OpSize;
2043 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2044 "or{l}\t{$src, $dst|$dst, $src}",
2045 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
2046 (implicit EFLAGS)]>;
2047 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2048 "or{b}\t{$src, $dst|$dst, $src}",
2049 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
2050 (implicit EFLAGS)]>;
2051 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
2052 "or{w}\t{$src, $dst|$dst, $src}",
2053 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
2054 (implicit EFLAGS)]>,
2056 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
2057 "or{l}\t{$src, $dst|$dst, $src}",
2058 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
2059 (implicit EFLAGS)]>;
2060 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
2061 "or{w}\t{$src, $dst|$dst, $src}",
2062 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
2063 (implicit EFLAGS)]>,
2065 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
2066 "or{l}\t{$src, $dst|$dst, $src}",
2067 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
2068 (implicit EFLAGS)]>;
2070 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
2071 "or{b}\t{$src, %al|%al, $src}", []>;
2072 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
2073 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2074 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
2075 "or{l}\t{$src, %eax|%eax, $src}", []>;
2076 } // Constraints = ""
2079 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
2080 def XOR8rr : I<0x30, MRMDestReg,
2081 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
2082 "xor{b}\t{$src2, $dst|$dst, $src2}",
2083 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2085 def XOR16rr : I<0x31, MRMDestReg,
2086 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2087 "xor{w}\t{$src2, $dst|$dst, $src2}",
2088 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2089 GR16:$src2))]>, OpSize;
2090 def XOR32rr : I<0x31, MRMDestReg,
2091 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2092 "xor{l}\t{$src2, $dst|$dst, $src2}",
2093 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2095 } // isCommutable = 1
2097 // XOR instructions with the destination register in REG and the source register
2098 // in R/M. Included for the disassembler.
2099 let isCodeGenOnly = 1 in {
2100 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2101 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
2102 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
2103 (ins GR16:$src1, GR16:$src2),
2104 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2105 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
2106 (ins GR32:$src1, GR32:$src2),
2107 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
2110 def XOR8rm : I<0x32, MRMSrcMem,
2111 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
2112 "xor{b}\t{$src2, $dst|$dst, $src2}",
2113 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2114 (load addr:$src2)))]>;
2115 def XOR16rm : I<0x33, MRMSrcMem,
2116 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2117 "xor{w}\t{$src2, $dst|$dst, $src2}",
2118 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2119 (load addr:$src2)))]>,
2121 def XOR32rm : I<0x33, MRMSrcMem,
2122 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2123 "xor{l}\t{$src2, $dst|$dst, $src2}",
2124 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2125 (load addr:$src2)))]>;
2127 def XOR8ri : Ii8<0x80, MRM6r,
2128 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2129 "xor{b}\t{$src2, $dst|$dst, $src2}",
2130 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
2131 def XOR16ri : Ii16<0x81, MRM6r,
2132 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2133 "xor{w}\t{$src2, $dst|$dst, $src2}",
2134 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2135 imm:$src2))]>, OpSize;
2136 def XOR32ri : Ii32<0x81, MRM6r,
2137 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2138 "xor{l}\t{$src2, $dst|$dst, $src2}",
2139 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2141 def XOR16ri8 : Ii8<0x83, MRM6r,
2142 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2143 "xor{w}\t{$src2, $dst|$dst, $src2}",
2144 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2145 i16immSExt8:$src2))]>,
2147 def XOR32ri8 : Ii8<0x83, MRM6r,
2148 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2149 "xor{l}\t{$src2, $dst|$dst, $src2}",
2150 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2151 i32immSExt8:$src2))]>;
2153 let Constraints = "" in {
2154 def XOR8mr : I<0x30, MRMDestMem,
2155 (outs), (ins i8mem :$dst, GR8 :$src),
2156 "xor{b}\t{$src, $dst|$dst, $src}",
2157 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
2158 (implicit EFLAGS)]>;
2159 def XOR16mr : I<0x31, MRMDestMem,
2160 (outs), (ins i16mem:$dst, GR16:$src),
2161 "xor{w}\t{$src, $dst|$dst, $src}",
2162 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
2163 (implicit EFLAGS)]>,
2165 def XOR32mr : I<0x31, MRMDestMem,
2166 (outs), (ins i32mem:$dst, GR32:$src),
2167 "xor{l}\t{$src, $dst|$dst, $src}",
2168 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
2169 (implicit EFLAGS)]>;
2170 def XOR8mi : Ii8<0x80, MRM6m,
2171 (outs), (ins i8mem :$dst, i8imm :$src),
2172 "xor{b}\t{$src, $dst|$dst, $src}",
2173 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
2174 (implicit EFLAGS)]>;
2175 def XOR16mi : Ii16<0x81, MRM6m,
2176 (outs), (ins i16mem:$dst, i16imm:$src),
2177 "xor{w}\t{$src, $dst|$dst, $src}",
2178 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
2179 (implicit EFLAGS)]>,
2181 def XOR32mi : Ii32<0x81, MRM6m,
2182 (outs), (ins i32mem:$dst, i32imm:$src),
2183 "xor{l}\t{$src, $dst|$dst, $src}",
2184 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
2185 (implicit EFLAGS)]>;
2186 def XOR16mi8 : Ii8<0x83, MRM6m,
2187 (outs), (ins i16mem:$dst, i16i8imm :$src),
2188 "xor{w}\t{$src, $dst|$dst, $src}",
2189 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
2190 (implicit EFLAGS)]>,
2192 def XOR32mi8 : Ii8<0x83, MRM6m,
2193 (outs), (ins i32mem:$dst, i32i8imm :$src),
2194 "xor{l}\t{$src, $dst|$dst, $src}",
2195 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
2196 (implicit EFLAGS)]>;
2198 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
2199 "xor{b}\t{$src, %al|%al, $src}", []>;
2200 def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
2201 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2202 def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
2203 "xor{l}\t{$src, %eax|%eax, $src}", []>;
2204 } // Constraints = ""
2205 } // Defs = [EFLAGS]
2207 // Shift instructions
2208 let Defs = [EFLAGS] in {
2209 let Uses = [CL] in {
2210 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
2211 "shl{b}\t{%cl, $dst|$dst, CL}",
2212 [(set GR8:$dst, (shl GR8:$src1, CL))]>;
2213 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2214 "shl{w}\t{%cl, $dst|$dst, CL}",
2215 [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize;
2216 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2217 "shl{l}\t{%cl, $dst|$dst, CL}",
2218 [(set GR32:$dst, (shl GR32:$src1, CL))]>;
2221 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2222 "shl{b}\t{$src2, $dst|$dst, $src2}",
2223 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
2225 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2226 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2227 "shl{w}\t{$src2, $dst|$dst, $src2}",
2228 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2229 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2230 "shl{l}\t{$src2, $dst|$dst, $src2}",
2231 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
2233 // NOTE: We don't include patterns for shifts of a register by one, because
2234 // 'add reg,reg' is cheaper.
2236 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
2237 "shl{b}\t$dst", []>;
2238 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2239 "shl{w}\t$dst", []>, OpSize;
2240 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2241 "shl{l}\t$dst", []>;
2243 } // isConvertibleToThreeAddress = 1
2245 let Constraints = "" in {
2246 let Uses = [CL] in {
2247 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
2248 "shl{b}\t{%cl, $dst|$dst, CL}",
2249 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
2250 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
2251 "shl{w}\t{%cl, $dst|$dst, CL}",
2252 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2253 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
2254 "shl{l}\t{%cl, $dst|$dst, CL}",
2255 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
2257 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
2258 "shl{b}\t{$src, $dst|$dst, $src}",
2259 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2260 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
2261 "shl{w}\t{$src, $dst|$dst, $src}",
2262 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2264 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
2265 "shl{l}\t{$src, $dst|$dst, $src}",
2266 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2269 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
2271 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2272 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
2274 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2276 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2278 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2279 } // Constraints = ""
2281 let Uses = [CL] in {
2282 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
2283 "shr{b}\t{%cl, $dst|$dst, CL}",
2284 [(set GR8:$dst, (srl GR8:$src1, CL))]>;
2285 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2286 "shr{w}\t{%cl, $dst|$dst, CL}",
2287 [(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize;
2288 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2289 "shr{l}\t{%cl, $dst|$dst, CL}",
2290 [(set GR32:$dst, (srl GR32:$src1, CL))]>;
2293 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2294 "shr{b}\t{$src2, $dst|$dst, $src2}",
2295 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2296 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2297 "shr{w}\t{$src2, $dst|$dst, $src2}",
2298 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2299 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2300 "shr{l}\t{$src2, $dst|$dst, $src2}",
2301 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2304 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2306 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2307 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2309 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2310 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2312 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2314 let Constraints = "" in {
2315 let Uses = [CL] in {
2316 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2317 "shr{b}\t{%cl, $dst|$dst, CL}",
2318 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2319 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2320 "shr{w}\t{%cl, $dst|$dst, CL}",
2321 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2323 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2324 "shr{l}\t{%cl, $dst|$dst, CL}",
2325 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2327 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2328 "shr{b}\t{$src, $dst|$dst, $src}",
2329 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2330 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2331 "shr{w}\t{$src, $dst|$dst, $src}",
2332 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2334 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2335 "shr{l}\t{$src, $dst|$dst, $src}",
2336 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2339 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2341 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2342 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2344 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2345 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2347 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2348 } // Constraints = ""
2350 let Uses = [CL] in {
2351 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2352 "sar{b}\t{%cl, $dst|$dst, CL}",
2353 [(set GR8:$dst, (sra GR8:$src1, CL))]>;
2354 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2355 "sar{w}\t{%cl, $dst|$dst, CL}",
2356 [(set GR16:$dst, (sra GR16:$src1, CL))]>, OpSize;
2357 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2358 "sar{l}\t{%cl, $dst|$dst, CL}",
2359 [(set GR32:$dst, (sra GR32:$src1, CL))]>;
2362 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2363 "sar{b}\t{$src2, $dst|$dst, $src2}",
2364 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2365 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2366 "sar{w}\t{$src2, $dst|$dst, $src2}",
2367 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2369 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2370 "sar{l}\t{$src2, $dst|$dst, $src2}",
2371 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2374 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2376 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2377 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2379 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2380 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2382 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2384 let Constraints = "" in {
2385 let Uses = [CL] in {
2386 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2387 "sar{b}\t{%cl, $dst|$dst, CL}",
2388 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2389 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2390 "sar{w}\t{%cl, $dst|$dst, CL}",
2391 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2392 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2393 "sar{l}\t{%cl, $dst|$dst, CL}",
2394 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2396 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2397 "sar{b}\t{$src, $dst|$dst, $src}",
2398 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2399 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2400 "sar{w}\t{$src, $dst|$dst, $src}",
2401 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2403 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2404 "sar{l}\t{$src, $dst|$dst, $src}",
2405 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2408 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2410 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2411 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2413 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2415 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2417 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2418 } // Constraints = ""
2420 // Rotate instructions
2422 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
2423 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2424 let Uses = [CL] in {
2425 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
2426 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2428 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
2429 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2431 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
2432 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2433 let Uses = [CL] in {
2434 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
2435 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2437 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
2438 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2440 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
2441 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2442 let Uses = [CL] in {
2443 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
2444 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2446 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
2447 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2449 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
2450 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2451 let Uses = [CL] in {
2452 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
2453 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2455 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
2456 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2458 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
2459 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2460 let Uses = [CL] in {
2461 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
2462 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2464 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
2465 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2467 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
2468 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2469 let Uses = [CL] in {
2470 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
2471 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2473 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
2474 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2476 let Constraints = "" in {
2477 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
2478 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2479 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2480 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2481 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
2482 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2483 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2484 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2485 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
2486 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2487 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2488 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2489 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
2490 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2491 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2492 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2493 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
2494 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2495 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2496 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2497 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
2498 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2499 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2500 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2502 let Uses = [CL] in {
2503 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
2504 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2505 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
2506 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2507 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
2508 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2509 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
2510 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2511 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
2512 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2513 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
2514 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2516 } // Constraints = ""
2518 // FIXME: provide shorter instructions when imm8 == 1
2519 let Uses = [CL] in {
2520 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2521 "rol{b}\t{%cl, $dst|$dst, CL}",
2522 [(set GR8:$dst, (rotl GR8:$src1, CL))]>;
2523 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2524 "rol{w}\t{%cl, $dst|$dst, CL}",
2525 [(set GR16:$dst, (rotl GR16:$src1, CL))]>, OpSize;
2526 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2527 "rol{l}\t{%cl, $dst|$dst, CL}",
2528 [(set GR32:$dst, (rotl GR32:$src1, CL))]>;
2531 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2532 "rol{b}\t{$src2, $dst|$dst, $src2}",
2533 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2534 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2535 "rol{w}\t{$src2, $dst|$dst, $src2}",
2536 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2538 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2539 "rol{l}\t{$src2, $dst|$dst, $src2}",
2540 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2543 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2545 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2546 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2548 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2549 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2551 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2553 let Constraints = "" in {
2554 let Uses = [CL] in {
2555 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2556 "rol{b}\t{%cl, $dst|$dst, CL}",
2557 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2558 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2559 "rol{w}\t{%cl, $dst|$dst, CL}",
2560 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2561 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2562 "rol{l}\t{%cl, $dst|$dst, CL}",
2563 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2565 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2566 "rol{b}\t{$src, $dst|$dst, $src}",
2567 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2568 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2569 "rol{w}\t{$src, $dst|$dst, $src}",
2570 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2572 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2573 "rol{l}\t{$src, $dst|$dst, $src}",
2574 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2577 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2579 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2580 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2582 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2584 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2586 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2587 } // Constraints = ""
2589 let Uses = [CL] in {
2590 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2591 "ror{b}\t{%cl, $dst|$dst, CL}",
2592 [(set GR8:$dst, (rotr GR8:$src1, CL))]>;
2593 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2594 "ror{w}\t{%cl, $dst|$dst, CL}",
2595 [(set GR16:$dst, (rotr GR16:$src1, CL))]>, OpSize;
2596 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2597 "ror{l}\t{%cl, $dst|$dst, CL}",
2598 [(set GR32:$dst, (rotr GR32:$src1, CL))]>;
2601 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2602 "ror{b}\t{$src2, $dst|$dst, $src2}",
2603 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2604 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2605 "ror{w}\t{$src2, $dst|$dst, $src2}",
2606 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2608 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2609 "ror{l}\t{$src2, $dst|$dst, $src2}",
2610 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2613 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2615 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2616 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2618 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2619 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2621 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2623 let Constraints = "" in {
2624 let Uses = [CL] in {
2625 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2626 "ror{b}\t{%cl, $dst|$dst, CL}",
2627 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2628 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2629 "ror{w}\t{%cl, $dst|$dst, CL}",
2630 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2631 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2632 "ror{l}\t{%cl, $dst|$dst, CL}",
2633 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2635 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2636 "ror{b}\t{$src, $dst|$dst, $src}",
2637 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2638 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2639 "ror{w}\t{$src, $dst|$dst, $src}",
2640 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2642 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2643 "ror{l}\t{$src, $dst|$dst, $src}",
2644 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2647 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2649 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2650 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2652 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2654 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2656 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2657 } // Constraints = ""
2660 // Double shift instructions (generalizations of rotate)
2661 let Uses = [CL] in {
2662 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2663 (ins GR32:$src1, GR32:$src2),
2664 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2665 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2666 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2667 (ins GR32:$src1, GR32:$src2),
2668 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2669 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2670 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2671 (ins GR16:$src1, GR16:$src2),
2672 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2673 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2675 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2676 (ins GR16:$src1, GR16:$src2),
2677 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2678 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2682 let isCommutable = 1 in { // These instructions commute to each other.
2683 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2685 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2686 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2687 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2690 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2692 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2693 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2694 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2697 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2699 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2700 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2701 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2704 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2706 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2707 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2708 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2713 let Constraints = "" in {
2714 let Uses = [CL] in {
2715 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2716 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2717 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2719 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2720 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2721 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2724 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2725 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2726 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2727 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2728 (i8 imm:$src3)), addr:$dst)]>,
2730 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2731 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2732 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2733 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2734 (i8 imm:$src3)), addr:$dst)]>,
2737 let Uses = [CL] in {
2738 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2739 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2740 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2741 addr:$dst)]>, TB, OpSize;
2742 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2743 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2744 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2745 addr:$dst)]>, TB, OpSize;
2747 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2748 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2749 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2750 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2751 (i8 imm:$src3)), addr:$dst)]>,
2753 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2754 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2755 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2756 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2757 (i8 imm:$src3)), addr:$dst)]>,
2759 } // Constraints = ""
2760 } // Defs = [EFLAGS]
2764 let Defs = [EFLAGS] in {
2765 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2766 // Register-Register Addition
2767 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2768 (ins GR8 :$src1, GR8 :$src2),
2769 "add{b}\t{$src2, $dst|$dst, $src2}",
2770 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
2772 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2773 // Register-Register Addition
2774 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2775 (ins GR16:$src1, GR16:$src2),
2776 "add{w}\t{$src2, $dst|$dst, $src2}",
2777 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2778 GR16:$src2))]>, OpSize;
2779 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2780 (ins GR32:$src1, GR32:$src2),
2781 "add{l}\t{$src2, $dst|$dst, $src2}",
2782 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2784 } // end isConvertibleToThreeAddress
2785 } // end isCommutable
2787 // These are alternate spellings for use by the disassembler, we mark them as
2788 // code gen only to ensure they aren't matched by the assembler.
2789 let isCodeGenOnly = 1 in {
2790 def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2791 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2792 def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2793 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2794 def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR32:$dst),(ins GR32:$src1, GR32:$src2),
2795 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2798 // Register-Memory Addition
2799 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2800 (ins GR8 :$src1, i8mem :$src2),
2801 "add{b}\t{$src2, $dst|$dst, $src2}",
2802 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
2803 (load addr:$src2)))]>;
2804 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2805 (ins GR16:$src1, i16mem:$src2),
2806 "add{w}\t{$src2, $dst|$dst, $src2}",
2807 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2808 (load addr:$src2)))]>, OpSize;
2809 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2810 (ins GR32:$src1, i32mem:$src2),
2811 "add{l}\t{$src2, $dst|$dst, $src2}",
2812 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2813 (load addr:$src2)))]>;
2815 // Register-Integer Addition
2816 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2817 "add{b}\t{$src2, $dst|$dst, $src2}",
2818 [(set GR8:$dst, EFLAGS,
2819 (X86add_flag GR8:$src1, imm:$src2))]>;
2821 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2822 // Register-Integer Addition
2823 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2824 (ins GR16:$src1, i16imm:$src2),
2825 "add{w}\t{$src2, $dst|$dst, $src2}",
2826 [(set GR16:$dst, EFLAGS,
2827 (X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
2828 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2829 (ins GR32:$src1, i32imm:$src2),
2830 "add{l}\t{$src2, $dst|$dst, $src2}",
2831 [(set GR32:$dst, EFLAGS,
2832 (X86add_flag GR32:$src1, imm:$src2))]>;
2833 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2834 (ins GR16:$src1, i16i8imm:$src2),
2835 "add{w}\t{$src2, $dst|$dst, $src2}",
2836 [(set GR16:$dst, EFLAGS,
2837 (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2838 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2839 (ins GR32:$src1, i32i8imm:$src2),
2840 "add{l}\t{$src2, $dst|$dst, $src2}",
2841 [(set GR32:$dst, EFLAGS,
2842 (X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
2845 let Constraints = "" in {
2846 // Memory-Register Addition
2847 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2848 "add{b}\t{$src2, $dst|$dst, $src2}",
2849 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2850 (implicit EFLAGS)]>;
2851 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2852 "add{w}\t{$src2, $dst|$dst, $src2}",
2853 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2854 (implicit EFLAGS)]>, OpSize;
2855 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2856 "add{l}\t{$src2, $dst|$dst, $src2}",
2857 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2858 (implicit EFLAGS)]>;
2859 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2860 "add{b}\t{$src2, $dst|$dst, $src2}",
2861 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2862 (implicit EFLAGS)]>;
2863 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2864 "add{w}\t{$src2, $dst|$dst, $src2}",
2865 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2866 (implicit EFLAGS)]>, OpSize;
2867 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2868 "add{l}\t{$src2, $dst|$dst, $src2}",
2869 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2870 (implicit EFLAGS)]>;
2871 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2872 "add{w}\t{$src2, $dst|$dst, $src2}",
2873 [(store (add (load addr:$dst), i16immSExt8:$src2),
2875 (implicit EFLAGS)]>, OpSize;
2876 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2877 "add{l}\t{$src2, $dst|$dst, $src2}",
2878 [(store (add (load addr:$dst), i32immSExt8:$src2),
2880 (implicit EFLAGS)]>;
2883 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2884 "add{b}\t{$src, %al|%al, $src}", []>;
2885 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2886 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2887 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2888 "add{l}\t{$src, %eax|%eax, $src}", []>;
2889 } // Constraints = ""
2891 let Uses = [EFLAGS] in {
2892 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2893 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2894 "adc{b}\t{$src2, $dst|$dst, $src2}",
2895 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2896 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2897 (ins GR16:$src1, GR16:$src2),
2898 "adc{w}\t{$src2, $dst|$dst, $src2}",
2899 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2900 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2901 (ins GR32:$src1, GR32:$src2),
2902 "adc{l}\t{$src2, $dst|$dst, $src2}",
2903 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2906 let isCodeGenOnly = 1 in {
2907 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2908 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2909 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2910 (ins GR16:$src1, GR16:$src2),
2911 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2912 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2913 (ins GR32:$src1, GR32:$src2),
2914 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2917 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2918 (ins GR8:$src1, i8mem:$src2),
2919 "adc{b}\t{$src2, $dst|$dst, $src2}",
2920 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2921 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2922 (ins GR16:$src1, i16mem:$src2),
2923 "adc{w}\t{$src2, $dst|$dst, $src2}",
2924 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2926 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2927 (ins GR32:$src1, i32mem:$src2),
2928 "adc{l}\t{$src2, $dst|$dst, $src2}",
2929 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2930 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2931 "adc{b}\t{$src2, $dst|$dst, $src2}",
2932 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2933 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2934 (ins GR16:$src1, i16imm:$src2),
2935 "adc{w}\t{$src2, $dst|$dst, $src2}",
2936 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2937 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2938 (ins GR16:$src1, i16i8imm:$src2),
2939 "adc{w}\t{$src2, $dst|$dst, $src2}",
2940 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2942 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2943 (ins GR32:$src1, i32imm:$src2),
2944 "adc{l}\t{$src2, $dst|$dst, $src2}",
2945 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2946 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2947 (ins GR32:$src1, i32i8imm:$src2),
2948 "adc{l}\t{$src2, $dst|$dst, $src2}",
2949 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2951 let Constraints = "" in {
2952 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2953 "adc{b}\t{$src2, $dst|$dst, $src2}",
2954 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2955 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2956 "adc{w}\t{$src2, $dst|$dst, $src2}",
2957 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2959 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2960 "adc{l}\t{$src2, $dst|$dst, $src2}",
2961 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2962 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2963 "adc{b}\t{$src2, $dst|$dst, $src2}",
2964 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2965 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2966 "adc{w}\t{$src2, $dst|$dst, $src2}",
2967 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2969 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2970 "adc{w}\t{$src2, $dst|$dst, $src2}",
2971 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2973 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2974 "adc{l}\t{$src2, $dst|$dst, $src2}",
2975 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2976 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2977 "adc{l}\t{$src2, $dst|$dst, $src2}",
2978 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2980 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2981 "adc{b}\t{$src, %al|%al, $src}", []>;
2982 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2983 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2984 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2985 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2986 } // Constraints = ""
2987 } // Uses = [EFLAGS]
2989 // Register-Register Subtraction
2990 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2991 "sub{b}\t{$src2, $dst|$dst, $src2}",
2992 [(set GR8:$dst, EFLAGS,
2993 (X86sub_flag GR8:$src1, GR8:$src2))]>;
2994 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2995 "sub{w}\t{$src2, $dst|$dst, $src2}",
2996 [(set GR16:$dst, EFLAGS,
2997 (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
2998 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2999 "sub{l}\t{$src2, $dst|$dst, $src2}",
3000 [(set GR32:$dst, EFLAGS,
3001 (X86sub_flag GR32:$src1, GR32:$src2))]>;
3003 let isCodeGenOnly = 1 in {
3004 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3005 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
3006 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
3007 (ins GR16:$src1, GR16:$src2),
3008 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3009 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
3010 (ins GR32:$src1, GR32:$src2),
3011 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
3014 // Register-Memory Subtraction
3015 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
3016 (ins GR8 :$src1, i8mem :$src2),
3017 "sub{b}\t{$src2, $dst|$dst, $src2}",
3018 [(set GR8:$dst, EFLAGS,
3019 (X86sub_flag GR8:$src1, (load addr:$src2)))]>;
3020 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
3021 (ins GR16:$src1, i16mem:$src2),
3022 "sub{w}\t{$src2, $dst|$dst, $src2}",
3023 [(set GR16:$dst, EFLAGS,
3024 (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
3025 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
3026 (ins GR32:$src1, i32mem:$src2),
3027 "sub{l}\t{$src2, $dst|$dst, $src2}",
3028 [(set GR32:$dst, EFLAGS,
3029 (X86sub_flag GR32:$src1, (load addr:$src2)))]>;
3031 // Register-Integer Subtraction
3032 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
3033 (ins GR8:$src1, i8imm:$src2),
3034 "sub{b}\t{$src2, $dst|$dst, $src2}",
3035 [(set GR8:$dst, EFLAGS,
3036 (X86sub_flag GR8:$src1, imm:$src2))]>;
3037 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
3038 (ins GR16:$src1, i16imm:$src2),
3039 "sub{w}\t{$src2, $dst|$dst, $src2}",
3040 [(set GR16:$dst, EFLAGS,
3041 (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
3042 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
3043 (ins GR32:$src1, i32imm:$src2),
3044 "sub{l}\t{$src2, $dst|$dst, $src2}",
3045 [(set GR32:$dst, EFLAGS,
3046 (X86sub_flag GR32:$src1, imm:$src2))]>;
3047 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
3048 (ins GR16:$src1, i16i8imm:$src2),
3049 "sub{w}\t{$src2, $dst|$dst, $src2}",
3050 [(set GR16:$dst, EFLAGS,
3051 (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
3052 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
3053 (ins GR32:$src1, i32i8imm:$src2),
3054 "sub{l}\t{$src2, $dst|$dst, $src2}",
3055 [(set GR32:$dst, EFLAGS,
3056 (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
3058 let Constraints = "" in {
3059 // Memory-Register Subtraction
3060 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3061 "sub{b}\t{$src2, $dst|$dst, $src2}",
3062 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
3063 (implicit EFLAGS)]>;
3064 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3065 "sub{w}\t{$src2, $dst|$dst, $src2}",
3066 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
3067 (implicit EFLAGS)]>, OpSize;
3068 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3069 "sub{l}\t{$src2, $dst|$dst, $src2}",
3070 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
3071 (implicit EFLAGS)]>;
3073 // Memory-Integer Subtraction
3074 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3075 "sub{b}\t{$src2, $dst|$dst, $src2}",
3076 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
3077 (implicit EFLAGS)]>;
3078 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3079 "sub{w}\t{$src2, $dst|$dst, $src2}",
3080 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
3081 (implicit EFLAGS)]>, OpSize;
3082 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3083 "sub{l}\t{$src2, $dst|$dst, $src2}",
3084 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
3085 (implicit EFLAGS)]>;
3086 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3087 "sub{w}\t{$src2, $dst|$dst, $src2}",
3088 [(store (sub (load addr:$dst), i16immSExt8:$src2),
3090 (implicit EFLAGS)]>, OpSize;
3091 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3092 "sub{l}\t{$src2, $dst|$dst, $src2}",
3093 [(store (sub (load addr:$dst), i32immSExt8:$src2),
3095 (implicit EFLAGS)]>;
3097 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
3098 "sub{b}\t{$src, %al|%al, $src}", []>;
3099 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
3100 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3101 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
3102 "sub{l}\t{$src, %eax|%eax, $src}", []>;
3103 } // Constraints = ""
3105 let Uses = [EFLAGS] in {
3106 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
3107 (ins GR8:$src1, GR8:$src2),
3108 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3109 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
3110 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
3111 (ins GR16:$src1, GR16:$src2),
3112 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3113 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
3114 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
3115 (ins GR32:$src1, GR32:$src2),
3116 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3117 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
3119 let Constraints = "" in {
3120 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3121 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3122 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
3123 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3124 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3125 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
3127 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3128 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3129 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
3130 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
3131 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3132 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
3133 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
3134 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3135 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
3137 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3138 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3139 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
3141 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
3142 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3143 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
3144 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3145 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3146 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
3148 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
3149 "sbb{b}\t{$src, %al|%al, $src}", []>;
3150 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
3151 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3152 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
3153 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
3154 } // Constraints = ""
3156 let isCodeGenOnly = 1 in {
3157 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3158 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
3159 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
3160 (ins GR16:$src1, GR16:$src2),
3161 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3162 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
3163 (ins GR32:$src1, GR32:$src2),
3164 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
3167 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
3168 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3169 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
3170 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
3171 (ins GR16:$src1, i16mem:$src2),
3172 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3173 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
3175 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
3176 (ins GR32:$src1, i32mem:$src2),
3177 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3178 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
3179 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
3180 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3181 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
3182 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
3183 (ins GR16:$src1, i16imm:$src2),
3184 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3185 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
3186 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
3187 (ins GR16:$src1, i16i8imm:$src2),
3188 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3189 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
3191 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
3192 (ins GR32:$src1, i32imm:$src2),
3193 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3194 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
3195 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
3196 (ins GR32:$src1, i32i8imm:$src2),
3197 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3198 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
3199 } // Uses = [EFLAGS]
3200 } // Defs = [EFLAGS]
3202 let Defs = [EFLAGS] in {
3203 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
3204 // Register-Register Signed Integer Multiply
3205 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3206 "imul{w}\t{$src2, $dst|$dst, $src2}",
3207 [(set GR16:$dst, EFLAGS,
3208 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
3209 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3210 "imul{l}\t{$src2, $dst|$dst, $src2}",
3211 [(set GR32:$dst, EFLAGS,
3212 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
3215 // Register-Memory Signed Integer Multiply
3216 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
3217 (ins GR16:$src1, i16mem:$src2),
3218 "imul{w}\t{$src2, $dst|$dst, $src2}",
3219 [(set GR16:$dst, EFLAGS,
3220 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
3222 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
3223 (ins GR32:$src1, i32mem:$src2),
3224 "imul{l}\t{$src2, $dst|$dst, $src2}",
3225 [(set GR32:$dst, EFLAGS,
3226 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
3227 } // Defs = [EFLAGS]
3228 } // end Two Address instructions
3230 // Suprisingly enough, these are not two address instructions!
3231 let Defs = [EFLAGS] in {
3232 // Register-Integer Signed Integer Multiply
3233 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
3234 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
3235 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3236 [(set GR16:$dst, EFLAGS,
3237 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
3238 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
3239 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
3240 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3241 [(set GR32:$dst, EFLAGS,
3242 (X86smul_flag GR32:$src1, imm:$src2))]>;
3243 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
3244 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
3245 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3246 [(set GR16:$dst, EFLAGS,
3247 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
3249 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
3250 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
3251 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3252 [(set GR32:$dst, EFLAGS,
3253 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
3255 // Memory-Integer Signed Integer Multiply
3256 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
3257 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
3258 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3259 [(set GR16:$dst, EFLAGS,
3260 (X86smul_flag (load addr:$src1), imm:$src2))]>,
3262 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
3263 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
3264 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3265 [(set GR32:$dst, EFLAGS,
3266 (X86smul_flag (load addr:$src1), imm:$src2))]>;
3267 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
3268 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
3269 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3270 [(set GR16:$dst, EFLAGS,
3271 (X86smul_flag (load addr:$src1),
3272 i16immSExt8:$src2))]>, OpSize;
3273 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
3274 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
3275 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3276 [(set GR32:$dst, EFLAGS,
3277 (X86smul_flag (load addr:$src1),
3278 i32immSExt8:$src2))]>;
3279 } // Defs = [EFLAGS]
3281 //===----------------------------------------------------------------------===//
3282 // Test instructions are just like AND, except they don't generate a result.
3284 let Defs = [EFLAGS] in {
3285 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
3286 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3287 "test{b}\t{$src2, $src1|$src1, $src2}",
3288 [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
3289 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3290 "test{w}\t{$src2, $src1|$src1, $src2}",
3291 [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
3294 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3295 "test{l}\t{$src2, $src1|$src1, $src2}",
3296 [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
3300 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
3301 "test{b}\t{$src, %al|%al, $src}", []>;
3302 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
3303 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3304 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
3305 "test{l}\t{$src, %eax|%eax, $src}", []>;
3307 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
3308 "test{b}\t{$src2, $src1|$src1, $src2}",
3309 [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
3311 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
3312 "test{w}\t{$src2, $src1|$src1, $src2}",
3313 [(set EFLAGS, (X86cmp (and GR16:$src1,
3314 (loadi16 addr:$src2)), 0))]>, OpSize;
3315 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
3316 "test{l}\t{$src2, $src1|$src1, $src2}",
3317 [(set EFLAGS, (X86cmp (and GR32:$src1,
3318 (loadi32 addr:$src2)), 0))]>;
3320 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
3321 (outs), (ins GR8:$src1, i8imm:$src2),
3322 "test{b}\t{$src2, $src1|$src1, $src2}",
3323 [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
3324 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
3325 (outs), (ins GR16:$src1, i16imm:$src2),
3326 "test{w}\t{$src2, $src1|$src1, $src2}",
3327 [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
3329 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
3330 (outs), (ins GR32:$src1, i32imm:$src2),
3331 "test{l}\t{$src2, $src1|$src1, $src2}",
3332 [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
3334 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
3335 (outs), (ins i8mem:$src1, i8imm:$src2),
3336 "test{b}\t{$src2, $src1|$src1, $src2}",
3337 [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
3339 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3340 (outs), (ins i16mem:$src1, i16imm:$src2),
3341 "test{w}\t{$src2, $src1|$src1, $src2}",
3342 [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
3344 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3345 (outs), (ins i32mem:$src1, i32imm:$src2),
3346 "test{l}\t{$src2, $src1|$src1, $src2}",
3347 [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
3349 } // Defs = [EFLAGS]
3352 // Condition code ops, incl. set if equal/not equal/...
3353 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3354 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3355 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3356 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3358 let Uses = [EFLAGS] in {
3359 // Use sbb to materialize carry bit.
3360 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
3361 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
3362 // However, Pat<> can't replicate the destination reg into the inputs of the
3364 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
3366 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
3367 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3368 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
3369 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
3371 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
3372 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3375 def SETEr : I<0x94, MRM0r,
3376 (outs GR8 :$dst), (ins),
3378 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3380 def SETEm : I<0x94, MRM0m,
3381 (outs), (ins i8mem:$dst),
3383 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3386 def SETNEr : I<0x95, MRM0r,
3387 (outs GR8 :$dst), (ins),
3389 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3391 def SETNEm : I<0x95, MRM0m,
3392 (outs), (ins i8mem:$dst),
3394 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3397 def SETLr : I<0x9C, MRM0r,
3398 (outs GR8 :$dst), (ins),
3400 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3401 TB; // GR8 = < signed
3402 def SETLm : I<0x9C, MRM0m,
3403 (outs), (ins i8mem:$dst),
3405 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3406 TB; // [mem8] = < signed
3408 def SETGEr : I<0x9D, MRM0r,
3409 (outs GR8 :$dst), (ins),
3411 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3412 TB; // GR8 = >= signed
3413 def SETGEm : I<0x9D, MRM0m,
3414 (outs), (ins i8mem:$dst),
3416 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3417 TB; // [mem8] = >= signed
3419 def SETLEr : I<0x9E, MRM0r,
3420 (outs GR8 :$dst), (ins),
3422 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3423 TB; // GR8 = <= signed
3424 def SETLEm : I<0x9E, MRM0m,
3425 (outs), (ins i8mem:$dst),
3427 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3428 TB; // [mem8] = <= signed
3430 def SETGr : I<0x9F, MRM0r,
3431 (outs GR8 :$dst), (ins),
3433 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3434 TB; // GR8 = > signed
3435 def SETGm : I<0x9F, MRM0m,
3436 (outs), (ins i8mem:$dst),
3438 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3439 TB; // [mem8] = > signed
3441 def SETBr : I<0x92, MRM0r,
3442 (outs GR8 :$dst), (ins),
3444 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3445 TB; // GR8 = < unsign
3446 def SETBm : I<0x92, MRM0m,
3447 (outs), (ins i8mem:$dst),
3449 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3450 TB; // [mem8] = < unsign
3452 def SETAEr : I<0x93, MRM0r,
3453 (outs GR8 :$dst), (ins),
3455 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3456 TB; // GR8 = >= unsign
3457 def SETAEm : I<0x93, MRM0m,
3458 (outs), (ins i8mem:$dst),
3460 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3461 TB; // [mem8] = >= unsign
3463 def SETBEr : I<0x96, MRM0r,
3464 (outs GR8 :$dst), (ins),
3466 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3467 TB; // GR8 = <= unsign
3468 def SETBEm : I<0x96, MRM0m,
3469 (outs), (ins i8mem:$dst),
3471 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3472 TB; // [mem8] = <= unsign
3474 def SETAr : I<0x97, MRM0r,
3475 (outs GR8 :$dst), (ins),
3477 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3478 TB; // GR8 = > signed
3479 def SETAm : I<0x97, MRM0m,
3480 (outs), (ins i8mem:$dst),
3482 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3483 TB; // [mem8] = > signed
3485 def SETSr : I<0x98, MRM0r,
3486 (outs GR8 :$dst), (ins),
3488 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3489 TB; // GR8 = <sign bit>
3490 def SETSm : I<0x98, MRM0m,
3491 (outs), (ins i8mem:$dst),
3493 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3494 TB; // [mem8] = <sign bit>
3495 def SETNSr : I<0x99, MRM0r,
3496 (outs GR8 :$dst), (ins),
3498 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3499 TB; // GR8 = !<sign bit>
3500 def SETNSm : I<0x99, MRM0m,
3501 (outs), (ins i8mem:$dst),
3503 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3504 TB; // [mem8] = !<sign bit>
3506 def SETPr : I<0x9A, MRM0r,
3507 (outs GR8 :$dst), (ins),
3509 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3511 def SETPm : I<0x9A, MRM0m,
3512 (outs), (ins i8mem:$dst),
3514 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3515 TB; // [mem8] = parity
3516 def SETNPr : I<0x9B, MRM0r,
3517 (outs GR8 :$dst), (ins),
3519 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3520 TB; // GR8 = not parity
3521 def SETNPm : I<0x9B, MRM0m,
3522 (outs), (ins i8mem:$dst),
3524 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3525 TB; // [mem8] = not parity
3527 def SETOr : I<0x90, MRM0r,
3528 (outs GR8 :$dst), (ins),
3530 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3531 TB; // GR8 = overflow
3532 def SETOm : I<0x90, MRM0m,
3533 (outs), (ins i8mem:$dst),
3535 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3536 TB; // [mem8] = overflow
3537 def SETNOr : I<0x91, MRM0r,
3538 (outs GR8 :$dst), (ins),
3540 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3541 TB; // GR8 = not overflow
3542 def SETNOm : I<0x91, MRM0m,
3543 (outs), (ins i8mem:$dst),
3545 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3546 TB; // [mem8] = not overflow
3547 } // Uses = [EFLAGS]
3550 // Integer comparisons
3551 let Defs = [EFLAGS] in {
3552 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3553 "cmp{b}\t{$src, %al|%al, $src}", []>;
3554 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3555 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3556 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3557 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3559 def CMP8rr : I<0x38, MRMDestReg,
3560 (outs), (ins GR8 :$src1, GR8 :$src2),
3561 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3562 [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
3563 def CMP16rr : I<0x39, MRMDestReg,
3564 (outs), (ins GR16:$src1, GR16:$src2),
3565 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3566 [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
3567 def CMP32rr : I<0x39, MRMDestReg,
3568 (outs), (ins GR32:$src1, GR32:$src2),
3569 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3570 [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
3571 def CMP8mr : I<0x38, MRMDestMem,
3572 (outs), (ins i8mem :$src1, GR8 :$src2),
3573 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3574 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
3575 def CMP16mr : I<0x39, MRMDestMem,
3576 (outs), (ins i16mem:$src1, GR16:$src2),
3577 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3578 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
3580 def CMP32mr : I<0x39, MRMDestMem,
3581 (outs), (ins i32mem:$src1, GR32:$src2),
3582 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3583 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
3584 def CMP8rm : I<0x3A, MRMSrcMem,
3585 (outs), (ins GR8 :$src1, i8mem :$src2),
3586 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3587 [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
3588 def CMP16rm : I<0x3B, MRMSrcMem,
3589 (outs), (ins GR16:$src1, i16mem:$src2),
3590 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3591 [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
3593 def CMP32rm : I<0x3B, MRMSrcMem,
3594 (outs), (ins GR32:$src1, i32mem:$src2),
3595 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3596 [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
3598 // These are alternate spellings for use by the disassembler, we mark them as
3599 // code gen only to ensure they aren't matched by the assembler.
3600 let isCodeGenOnly = 1 in {
3601 def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3602 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3603 def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3604 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3605 def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3606 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3609 def CMP8ri : Ii8<0x80, MRM7r,
3610 (outs), (ins GR8:$src1, i8imm:$src2),
3611 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3612 [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
3613 def CMP16ri : Ii16<0x81, MRM7r,
3614 (outs), (ins GR16:$src1, i16imm:$src2),
3615 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3616 [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
3617 def CMP32ri : Ii32<0x81, MRM7r,
3618 (outs), (ins GR32:$src1, i32imm:$src2),
3619 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3620 [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
3621 def CMP8mi : Ii8 <0x80, MRM7m,
3622 (outs), (ins i8mem :$src1, i8imm :$src2),
3623 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3624 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
3625 def CMP16mi : Ii16<0x81, MRM7m,
3626 (outs), (ins i16mem:$src1, i16imm:$src2),
3627 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3628 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
3630 def CMP32mi : Ii32<0x81, MRM7m,
3631 (outs), (ins i32mem:$src1, i32imm:$src2),
3632 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3633 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
3634 def CMP16ri8 : Ii8<0x83, MRM7r,
3635 (outs), (ins GR16:$src1, i16i8imm:$src2),
3636 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3637 [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
3639 def CMP16mi8 : Ii8<0x83, MRM7m,
3640 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3641 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3642 [(set EFLAGS, (X86cmp (loadi16 addr:$src1),
3643 i16immSExt8:$src2))]>, OpSize;
3644 def CMP32mi8 : Ii8<0x83, MRM7m,
3645 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3646 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3647 [(set EFLAGS, (X86cmp (loadi32 addr:$src1),
3648 i32immSExt8:$src2))]>;
3649 def CMP32ri8 : Ii8<0x83, MRM7r,
3650 (outs), (ins GR32:$src1, i32i8imm:$src2),
3651 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3652 [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
3653 } // Defs = [EFLAGS]
3656 // TODO: BTC, BTR, and BTS
3657 let Defs = [EFLAGS] in {
3658 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3659 "bt{w}\t{$src2, $src1|$src1, $src2}",
3660 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
3661 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3662 "bt{l}\t{$src2, $src1|$src1, $src2}",
3663 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
3665 // Unlike with the register+register form, the memory+register form of the
3666 // bt instruction does not ignore the high bits of the index. From ISel's
3667 // perspective, this is pretty bizarre. Make these instructions disassembly
3670 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3671 "bt{w}\t{$src2, $src1|$src1, $src2}",
3672 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3673 // (implicit EFLAGS)]
3675 >, OpSize, TB, Requires<[FastBTMem]>;
3676 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3677 "bt{l}\t{$src2, $src1|$src1, $src2}",
3678 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3679 // (implicit EFLAGS)]
3681 >, TB, Requires<[FastBTMem]>;
3683 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3684 "bt{w}\t{$src2, $src1|$src1, $src2}",
3685 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
3687 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3688 "bt{l}\t{$src2, $src1|$src1, $src2}",
3689 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
3690 // Note that these instructions don't need FastBTMem because that
3691 // only applies when the other operand is in a register. When it's
3692 // an immediate, bt is still fast.
3693 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3694 "bt{w}\t{$src2, $src1|$src1, $src2}",
3695 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
3697 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3698 "bt{l}\t{$src2, $src1|$src1, $src2}",
3699 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
3702 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3703 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3704 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3705 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3706 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3707 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3708 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3709 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3710 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3711 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3712 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3713 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3714 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3715 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3716 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3717 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3719 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3720 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3721 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3722 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3723 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3724 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3725 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3726 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3727 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3728 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3729 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3730 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3731 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3732 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3733 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3734 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3736 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3737 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3738 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3739 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3740 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3741 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3742 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3743 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3744 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3745 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3746 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3747 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3748 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3749 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3750 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3751 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3752 } // Defs = [EFLAGS]
3754 // Sign/Zero extenders
3755 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3756 // of the register here. This has a smaller encoding and avoids a
3757 // partial-register update. Actual movsbw included for the disassembler.
3758 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3759 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3760 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3761 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3762 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3763 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3764 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3765 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3766 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3767 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3768 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3769 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3770 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3771 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3772 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3773 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3774 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3775 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3776 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3777 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3779 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3780 // of the register here. This has a smaller encoding and avoids a
3781 // partial-register update. Actual movzbw included for the disassembler.
3782 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3783 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3784 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3785 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3786 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3787 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3788 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3789 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3790 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3791 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3792 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3793 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3794 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3795 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3796 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3797 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3798 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3799 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3800 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3801 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3803 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
3804 // except that they use GR32_NOREX for the output operand register class
3805 // instead of GR32. This allows them to operate on h registers on x86-64.
3806 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3807 (outs GR32_NOREX:$dst), (ins GR8:$src),
3808 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3811 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3812 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3813 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3816 let neverHasSideEffects = 1 in {
3817 let Defs = [AX], Uses = [AL] in
3818 def CBW : I<0x98, RawFrm, (outs), (ins),
3819 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3820 let Defs = [EAX], Uses = [AX] in
3821 def CWDE : I<0x98, RawFrm, (outs), (ins),
3822 "{cwtl|cwde}", []>; // EAX = signext(AX)
3824 let Defs = [AX,DX], Uses = [AX] in
3825 def CWD : I<0x99, RawFrm, (outs), (ins),
3826 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3827 let Defs = [EAX,EDX], Uses = [EAX] in
3828 def CDQ : I<0x99, RawFrm, (outs), (ins),
3829 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3832 //===----------------------------------------------------------------------===//
3833 // Alias Instructions
3834 //===----------------------------------------------------------------------===//
3836 // Alias instructions that map movr0 to xor.
3837 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3838 // FIXME: Set encoding to pseudo.
3839 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3840 isCodeGenOnly = 1 in {
3841 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
3842 [(set GR8:$dst, 0)]>;
3844 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
3845 // encoding and avoids a partial-register update sometimes, but doing so
3846 // at isel time interferes with rematerialization in the current register
3847 // allocator. For now, this is rewritten when the instruction is lowered
3849 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3851 [(set GR16:$dst, 0)]>, OpSize;
3853 // FIXME: Set encoding to pseudo.
3854 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
3855 [(set GR32:$dst, 0)]>;
3858 //===----------------------------------------------------------------------===//
3859 // Thread Local Storage Instructions
3863 // All calls clobber the non-callee saved registers. ESP is marked as
3864 // a use to prevent stack-pointer assignments that appear immediately
3865 // before calls from potentially appearing dead.
3866 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3867 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3868 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3869 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3871 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
3872 "leal\t$sym, %eax; "
3873 "call\t___tls_get_addr@PLT",
3874 [(X86tlsaddr tls32addr:$sym)]>,
3875 Requires<[In32BitMode]>;
3877 // Darwin TLS Support
3878 // For i386, the address of the thunk is passed on the stack, on return the
3879 // address of the variable is in %eax. %ecx is trashed during the function
3880 // call. All other registers are preserved.
3881 let Defs = [EAX, ECX],
3883 usesCustomInserter = 1 in
3884 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
3886 [(X86TLSCall addr:$sym)]>,
3887 Requires<[In32BitMode]>;
3889 //===----------------------------------------------------------------------===//
3890 // EH Pseudo Instructions
3892 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3893 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3894 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3895 "ret\t#eh_return, addr: $addr",
3896 [(X86ehret GR32:$addr)]>;
3900 //===----------------------------------------------------------------------===//
3906 // TODO: Get this to fold the constant into the instruction.
3907 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
3909 "or{l}\t{$zero, $dst|$dst, $zero}",
3910 []>, Requires<[In32BitMode]>, LOCK;
3912 let hasSideEffects = 1 in {
3913 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
3915 [(X86MemBarrier)]>, Requires<[HasSSE2]>;
3918 // Atomic swap. These are just normal xchg instructions. But since a memory
3919 // operand is referenced, the atomicity is ensured.
3920 let Constraints = "$val = $dst" in {
3921 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3922 (ins GR32:$val, i32mem:$ptr),
3923 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3924 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3925 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3926 (ins GR16:$val, i16mem:$ptr),
3927 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3928 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3930 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3931 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3932 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3934 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3935 "xchg{l}\t{$val, $src|$src, $val}", []>;
3936 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3937 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3938 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3939 "xchg{b}\t{$val, $src|$src, $val}", []>;
3942 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3943 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3944 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3945 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
3947 // Atomic compare and swap.
3948 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3949 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3951 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3952 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3954 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3955 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
3958 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3961 let Defs = [AX, EFLAGS], Uses = [AX] in {
3962 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3964 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3965 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3967 let Defs = [AL, EFLAGS], Uses = [AL] in {
3968 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3970 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3971 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3974 // Atomic exchange and add
3975 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3976 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
3978 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3979 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3981 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
3983 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3984 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3986 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3988 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3989 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3993 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3994 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3995 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3996 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3997 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3998 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
4000 let mayLoad = 1, mayStore = 1 in {
4001 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
4002 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
4003 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
4004 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4005 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
4006 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
4009 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
4010 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
4011 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
4012 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4013 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4014 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
4016 let mayLoad = 1, mayStore = 1 in {
4017 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
4018 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
4019 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
4020 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4021 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
4022 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
4025 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
4026 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
4027 "cmpxchg8b\t$dst", []>, TB;
4029 // Optimized codegen when the non-memory output is not used.
4030 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
4031 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1 in {
4032 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
4034 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4035 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
4037 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4038 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
4040 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4041 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
4043 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4044 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
4046 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4047 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
4049 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4050 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
4052 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4053 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
4055 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4057 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
4059 "inc{b}\t$dst", []>, LOCK;
4060 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
4062 "inc{w}\t$dst", []>, OpSize, LOCK;
4063 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
4065 "inc{l}\t$dst", []>, LOCK;
4067 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
4069 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4070 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
4072 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4073 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
4075 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4076 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
4078 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4079 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
4081 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4082 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
4084 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4085 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
4087 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4088 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
4090 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4092 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
4094 "dec{b}\t$dst", []>, LOCK;
4095 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
4097 "dec{w}\t$dst", []>, OpSize, LOCK;
4098 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
4100 "dec{l}\t$dst", []>, LOCK;
4103 // Atomic exchange, and, or, xor
4104 let Constraints = "$val = $dst", Defs = [EFLAGS],
4105 usesCustomInserter = 1 in {
4106 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4107 "#ATOMAND32 PSEUDO!",
4108 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
4109 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4110 "#ATOMOR32 PSEUDO!",
4111 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
4112 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4113 "#ATOMXOR32 PSEUDO!",
4114 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
4115 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4116 "#ATOMNAND32 PSEUDO!",
4117 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
4118 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
4119 "#ATOMMIN32 PSEUDO!",
4120 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
4121 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4122 "#ATOMMAX32 PSEUDO!",
4123 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
4124 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4125 "#ATOMUMIN32 PSEUDO!",
4126 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
4127 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4128 "#ATOMUMAX32 PSEUDO!",
4129 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
4131 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4132 "#ATOMAND16 PSEUDO!",
4133 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
4134 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4135 "#ATOMOR16 PSEUDO!",
4136 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
4137 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4138 "#ATOMXOR16 PSEUDO!",
4139 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
4140 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4141 "#ATOMNAND16 PSEUDO!",
4142 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
4143 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
4144 "#ATOMMIN16 PSEUDO!",
4145 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
4146 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4147 "#ATOMMAX16 PSEUDO!",
4148 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
4149 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4150 "#ATOMUMIN16 PSEUDO!",
4151 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
4152 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4153 "#ATOMUMAX16 PSEUDO!",
4154 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
4156 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4157 "#ATOMAND8 PSEUDO!",
4158 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
4159 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4161 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
4162 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4163 "#ATOMXOR8 PSEUDO!",
4164 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
4165 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4166 "#ATOMNAND8 PSEUDO!",
4167 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
4170 let Constraints = "$val1 = $dst1, $val2 = $dst2",
4171 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
4172 Uses = [EAX, EBX, ECX, EDX],
4173 mayLoad = 1, mayStore = 1,
4174 usesCustomInserter = 1 in {
4175 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4176 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4177 "#ATOMAND6432 PSEUDO!", []>;
4178 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4179 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4180 "#ATOMOR6432 PSEUDO!", []>;
4181 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4182 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4183 "#ATOMXOR6432 PSEUDO!", []>;
4184 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4185 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4186 "#ATOMNAND6432 PSEUDO!", []>;
4187 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4188 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4189 "#ATOMADD6432 PSEUDO!", []>;
4190 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4191 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4192 "#ATOMSUB6432 PSEUDO!", []>;
4193 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4194 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4195 "#ATOMSWAP6432 PSEUDO!", []>;
4198 // Segmentation support instructions.
4200 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4201 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4202 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4203 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4205 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
4206 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
4207 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4208 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4209 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4211 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4212 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4213 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4214 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4215 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4216 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4217 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4218 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4220 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
4222 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
4223 "str{w}\t{$dst}", []>, TB;
4224 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
4225 "str{w}\t{$dst}", []>, TB;
4226 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
4227 "ltr{w}\t{$src}", []>, TB;
4228 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
4229 "ltr{w}\t{$src}", []>, TB;
4231 def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
4232 "push{w}\t%cs", []>, Requires<[In32BitMode]>, OpSize;
4233 def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
4234 "push{l}\t%cs", []>, Requires<[In32BitMode]>;
4235 def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
4236 "push{w}\t%ss", []>, Requires<[In32BitMode]>, OpSize;
4237 def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
4238 "push{l}\t%ss", []>, Requires<[In32BitMode]>;
4239 def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
4240 "push{w}\t%ds", []>, Requires<[In32BitMode]>, OpSize;
4241 def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
4242 "push{l}\t%ds", []>, Requires<[In32BitMode]>;
4243 def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
4244 "push{w}\t%es", []>, Requires<[In32BitMode]>, OpSize;
4245 def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
4246 "push{l}\t%es", []>, Requires<[In32BitMode]>;
4248 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
4249 "push{w}\t%fs", []>, OpSize, TB;
4250 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
4251 "push{l}\t%fs", []>, TB, Requires<[In32BitMode]>;
4252 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
4253 "push{w}\t%gs", []>, OpSize, TB;
4254 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
4255 "push{l}\t%gs", []>, TB, Requires<[In32BitMode]>;
4257 // No "pop cs" instruction.
4258 def POPSS16 : I<0x17, RawFrm, (outs), (ins),
4259 "pop{w}\t%ss", []>, OpSize, Requires<[In32BitMode]>;
4260 def POPSS32 : I<0x17, RawFrm, (outs), (ins),
4261 "pop{l}\t%ss", []> , Requires<[In32BitMode]>;
4262 def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
4263 "pop{w}\t%ds", []>, OpSize, Requires<[In32BitMode]>;
4264 def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
4265 "pop{l}\t%ds", []> , Requires<[In32BitMode]>;
4266 def POPES16 : I<0x07, RawFrm, (outs), (ins),
4267 "pop{w}\t%es", []>, OpSize, Requires<[In32BitMode]>;
4268 def POPES32 : I<0x07, RawFrm, (outs), (ins),
4269 "pop{l}\t%es", []> , Requires<[In32BitMode]>;
4270 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
4271 "pop{w}\t%fs", []>, OpSize, TB;
4272 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
4273 "pop{l}\t%fs", []>, TB , Requires<[In32BitMode]>;
4274 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
4275 "pop{w}\t%gs", []>, OpSize, TB;
4276 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
4277 "pop{l}\t%gs", []>, TB , Requires<[In32BitMode]>;
4279 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4280 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4281 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4282 "lds{l}\t{$src, $dst|$dst, $src}", []>;
4283 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4284 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4285 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4286 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
4287 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4288 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4289 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4290 "les{l}\t{$src, $dst|$dst, $src}", []>;
4291 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4292 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4293 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4294 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4295 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4296 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4297 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4298 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4300 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
4301 "verr\t$seg", []>, TB;
4302 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
4303 "verr\t$seg", []>, TB;
4304 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
4305 "verw\t$seg", []>, TB;
4306 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
4307 "verw\t$seg", []>, TB;
4309 // Descriptor-table support instructions
4311 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
4312 "sgdt\t$dst", []>, TB;
4313 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
4314 "sidt\t$dst", []>, TB;
4315 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
4316 "sldt{w}\t$dst", []>, TB, OpSize;
4317 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
4318 "sldt{w}\t$dst", []>, TB;
4319 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
4320 "sldt{l}\t$dst", []>, TB;
4321 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
4322 "lgdt\t$src", []>, TB;
4323 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
4324 "lidt\t$src", []>, TB;
4325 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
4326 "lldt{w}\t$src", []>, TB;
4327 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
4328 "lldt{w}\t$src", []>, TB;
4330 // Lock instruction prefix
4331 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
4333 // Repeat string operation instruction prefixes
4334 // These uses the DF flag in the EFLAGS register to inc or dec ECX
4335 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
4336 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
4337 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
4338 // Repeat while not equal (used with CMPS and SCAS)
4339 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
4342 // Segment override instruction prefixes
4343 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
4344 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
4345 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
4346 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
4347 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
4348 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
4350 // String manipulation instructions
4352 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
4353 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
4354 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
4356 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
4357 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
4358 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
4360 // CPU flow control instructions
4362 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
4363 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
4365 // FPU control instructions
4367 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
4369 // Flag instructions
4371 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
4372 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
4373 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
4374 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
4375 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
4376 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
4377 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
4379 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
4381 // Table lookup instructions
4383 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
4385 // Specialized register support
4387 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
4388 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
4389 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
4391 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
4392 "smsw{w}\t$dst", []>, OpSize, TB;
4393 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
4394 "smsw{l}\t$dst", []>, TB;
4395 // For memory operands, there is only a 16-bit form
4396 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
4397 "smsw{w}\t$dst", []>, TB;
4399 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
4400 "lmsw{w}\t$src", []>, TB;
4401 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
4402 "lmsw{w}\t$src", []>, TB;
4404 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
4406 // Cache instructions
4408 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
4409 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
4414 def INVEPT : I<0x80, RawFrm, (outs), (ins), "invept", []>, OpSize, T8;
4416 def INVVPID : I<0x81, RawFrm, (outs), (ins), "invvpid", []>, OpSize, T8;
4418 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
4419 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4420 "vmclear\t$vmcs", []>, OpSize, TB;
4422 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
4424 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
4425 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4426 "vmptrld\t$vmcs", []>, TB;
4427 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4428 "vmptrst\t$vmcs", []>, TB;
4429 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
4430 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4431 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
4432 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4433 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
4434 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4435 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4436 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4437 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4438 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4439 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4440 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4441 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4442 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4443 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4444 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4446 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
4447 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
4448 "vmxon\t{$vmxon}", []>, XS;
4450 //===----------------------------------------------------------------------===//
4451 // Non-Instruction Patterns
4452 //===----------------------------------------------------------------------===//
4454 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
4455 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
4456 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
4457 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
4458 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
4459 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
4460 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
4462 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
4463 (ADD32ri GR32:$src1, tconstpool:$src2)>;
4464 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
4465 (ADD32ri GR32:$src1, tjumptable:$src2)>;
4466 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
4467 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
4468 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
4469 (ADD32ri GR32:$src1, texternalsym:$src2)>;
4470 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
4471 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
4473 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
4474 (MOV32mi addr:$dst, tglobaladdr:$src)>;
4475 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
4476 (MOV32mi addr:$dst, texternalsym:$src)>;
4477 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
4478 (MOV32mi addr:$dst, tblockaddress:$src)>;
4482 def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
4483 (TCRETURNri GR32_TC:$dst, imm:$off)>,
4484 Requires<[In32BitMode]>;
4486 // FIXME: This is disabled for 32-bit PIC mode because the global base
4487 // register which is part of the address mode may be assigned a
4488 // callee-saved register.
4489 def : Pat<(X86tcret (load addr:$dst), imm:$off),
4490 (TCRETURNmi addr:$dst, imm:$off)>,
4491 Requires<[In32BitMode, IsNotPIC]>;
4493 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
4494 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4495 Requires<[In32BitMode]>;
4497 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
4498 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4499 Requires<[In32BitMode]>;
4501 // Normal calls, with various flavors of addresses.
4502 def : Pat<(X86call (i32 tglobaladdr:$dst)),
4503 (CALLpcrel32 tglobaladdr:$dst)>;
4504 def : Pat<(X86call (i32 texternalsym:$dst)),
4505 (CALLpcrel32 texternalsym:$dst)>;
4506 def : Pat<(X86call (i32 imm:$dst)),
4507 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
4509 // X86 specific add which produces a flag.
4510 def : Pat<(addc GR32:$src1, GR32:$src2),
4511 (ADD32rr GR32:$src1, GR32:$src2)>;
4512 def : Pat<(addc GR32:$src1, (load addr:$src2)),
4513 (ADD32rm GR32:$src1, addr:$src2)>;
4514 def : Pat<(addc GR32:$src1, imm:$src2),
4515 (ADD32ri GR32:$src1, imm:$src2)>;
4516 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
4517 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4519 def : Pat<(subc GR32:$src1, GR32:$src2),
4520 (SUB32rr GR32:$src1, GR32:$src2)>;
4521 def : Pat<(subc GR32:$src1, (load addr:$src2)),
4522 (SUB32rm GR32:$src1, addr:$src2)>;
4523 def : Pat<(subc GR32:$src1, imm:$src2),
4524 (SUB32ri GR32:$src1, imm:$src2)>;
4525 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
4526 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4530 // TEST R,R is smaller than CMP R,0
4531 def : Pat<(X86cmp GR8:$src1, 0),
4532 (TEST8rr GR8:$src1, GR8:$src1)>;
4533 def : Pat<(X86cmp GR16:$src1, 0),
4534 (TEST16rr GR16:$src1, GR16:$src1)>;
4535 def : Pat<(X86cmp GR32:$src1, 0),
4536 (TEST32rr GR32:$src1, GR32:$src1)>;
4538 // Conditional moves with folded loads with operands swapped and conditions
4540 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
4541 (CMOVAE16rm GR16:$src2, addr:$src1)>;
4542 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
4543 (CMOVAE32rm GR32:$src2, addr:$src1)>;
4544 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
4545 (CMOVB16rm GR16:$src2, addr:$src1)>;
4546 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
4547 (CMOVB32rm GR32:$src2, addr:$src1)>;
4548 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
4549 (CMOVNE16rm GR16:$src2, addr:$src1)>;
4550 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
4551 (CMOVNE32rm GR32:$src2, addr:$src1)>;
4552 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
4553 (CMOVE16rm GR16:$src2, addr:$src1)>;
4554 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
4555 (CMOVE32rm GR32:$src2, addr:$src1)>;
4556 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
4557 (CMOVA16rm GR16:$src2, addr:$src1)>;
4558 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
4559 (CMOVA32rm GR32:$src2, addr:$src1)>;
4560 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
4561 (CMOVBE16rm GR16:$src2, addr:$src1)>;
4562 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
4563 (CMOVBE32rm GR32:$src2, addr:$src1)>;
4564 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
4565 (CMOVGE16rm GR16:$src2, addr:$src1)>;
4566 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
4567 (CMOVGE32rm GR32:$src2, addr:$src1)>;
4568 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
4569 (CMOVL16rm GR16:$src2, addr:$src1)>;
4570 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
4571 (CMOVL32rm GR32:$src2, addr:$src1)>;
4572 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
4573 (CMOVG16rm GR16:$src2, addr:$src1)>;
4574 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
4575 (CMOVG32rm GR32:$src2, addr:$src1)>;
4576 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
4577 (CMOVLE16rm GR16:$src2, addr:$src1)>;
4578 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
4579 (CMOVLE32rm GR32:$src2, addr:$src1)>;
4580 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
4581 (CMOVNP16rm GR16:$src2, addr:$src1)>;
4582 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
4583 (CMOVNP32rm GR32:$src2, addr:$src1)>;
4584 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
4585 (CMOVP16rm GR16:$src2, addr:$src1)>;
4586 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
4587 (CMOVP32rm GR32:$src2, addr:$src1)>;
4588 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
4589 (CMOVNS16rm GR16:$src2, addr:$src1)>;
4590 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
4591 (CMOVNS32rm GR32:$src2, addr:$src1)>;
4592 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
4593 (CMOVS16rm GR16:$src2, addr:$src1)>;
4594 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
4595 (CMOVS32rm GR32:$src2, addr:$src1)>;
4596 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
4597 (CMOVNO16rm GR16:$src2, addr:$src1)>;
4598 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
4599 (CMOVNO32rm GR32:$src2, addr:$src1)>;
4600 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
4601 (CMOVO16rm GR16:$src2, addr:$src1)>;
4602 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
4603 (CMOVO32rm GR32:$src2, addr:$src1)>;
4605 // zextload bool -> zextload byte
4606 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4607 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4608 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4610 // extload bool -> extload byte
4611 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4612 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4613 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4614 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
4615 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
4616 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
4618 // anyext. Define these to do an explicit zero-extend to
4619 // avoid partial-register updates.
4620 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
4621 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
4623 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
4624 def : Pat<(i32 (anyext GR16:$src)),
4625 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
4628 //===----------------------------------------------------------------------===//
4630 //===----------------------------------------------------------------------===//
4632 // Odd encoding trick: -128 fits into an 8-bit immediate field while
4633 // +128 doesn't, so in this special case use a sub instead of an add.
4634 def : Pat<(add GR16:$src1, 128),
4635 (SUB16ri8 GR16:$src1, -128)>;
4636 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
4637 (SUB16mi8 addr:$dst, -128)>;
4638 def : Pat<(add GR32:$src1, 128),
4639 (SUB32ri8 GR32:$src1, -128)>;
4640 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
4641 (SUB32mi8 addr:$dst, -128)>;
4643 // r & (2^16-1) ==> movz
4644 def : Pat<(and GR32:$src1, 0xffff),
4645 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
4646 // r & (2^8-1) ==> movz
4647 def : Pat<(and GR32:$src1, 0xff),
4648 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
4651 Requires<[In32BitMode]>;
4652 // r & (2^8-1) ==> movz
4653 def : Pat<(and GR16:$src1, 0xff),
4654 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
4657 Requires<[In32BitMode]>;
4659 // sext_inreg patterns
4660 def : Pat<(sext_inreg GR32:$src, i16),
4661 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
4662 def : Pat<(sext_inreg GR32:$src, i8),
4663 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4666 Requires<[In32BitMode]>;
4667 def : Pat<(sext_inreg GR16:$src, i8),
4668 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4671 Requires<[In32BitMode]>;
4674 def : Pat<(i16 (trunc GR32:$src)),
4675 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
4676 def : Pat<(i8 (trunc GR32:$src)),
4677 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4679 Requires<[In32BitMode]>;
4680 def : Pat<(i8 (trunc GR16:$src)),
4681 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4683 Requires<[In32BitMode]>;
4685 // h-register tricks
4686 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
4687 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4689 Requires<[In32BitMode]>;
4690 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
4691 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4693 Requires<[In32BitMode]>;
4694 def : Pat<(srl GR16:$src, (i8 8)),
4697 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4700 Requires<[In32BitMode]>;
4701 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4702 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4705 Requires<[In32BitMode]>;
4706 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4707 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4710 Requires<[In32BitMode]>;
4711 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4712 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4715 Requires<[In32BitMode]>;
4716 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
4717 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4720 Requires<[In32BitMode]>;
4722 // (shl x, 1) ==> (add x, x)
4723 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
4724 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
4725 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
4727 // (shl x (and y, 31)) ==> (shl x, y)
4728 def : Pat<(shl GR8:$src1, (and CL, 31)),
4729 (SHL8rCL GR8:$src1)>;
4730 def : Pat<(shl GR16:$src1, (and CL, 31)),
4731 (SHL16rCL GR16:$src1)>;
4732 def : Pat<(shl GR32:$src1, (and CL, 31)),
4733 (SHL32rCL GR32:$src1)>;
4734 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4735 (SHL8mCL addr:$dst)>;
4736 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4737 (SHL16mCL addr:$dst)>;
4738 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4739 (SHL32mCL addr:$dst)>;
4741 def : Pat<(srl GR8:$src1, (and CL, 31)),
4742 (SHR8rCL GR8:$src1)>;
4743 def : Pat<(srl GR16:$src1, (and CL, 31)),
4744 (SHR16rCL GR16:$src1)>;
4745 def : Pat<(srl GR32:$src1, (and CL, 31)),
4746 (SHR32rCL GR32:$src1)>;
4747 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4748 (SHR8mCL addr:$dst)>;
4749 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4750 (SHR16mCL addr:$dst)>;
4751 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4752 (SHR32mCL addr:$dst)>;
4754 def : Pat<(sra GR8:$src1, (and CL, 31)),
4755 (SAR8rCL GR8:$src1)>;
4756 def : Pat<(sra GR16:$src1, (and CL, 31)),
4757 (SAR16rCL GR16:$src1)>;
4758 def : Pat<(sra GR32:$src1, (and CL, 31)),
4759 (SAR32rCL GR32:$src1)>;
4760 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4761 (SAR8mCL addr:$dst)>;
4762 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4763 (SAR16mCL addr:$dst)>;
4764 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4765 (SAR32mCL addr:$dst)>;
4767 // (anyext (setcc_carry)) -> (setcc_carry)
4768 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4770 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4772 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
4775 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
4776 let AddedComplexity = 5 in { // Try this before the selecting to OR
4777 def : Pat<(or_is_add GR16:$src1, imm:$src2),
4778 (ADD16ri GR16:$src1, imm:$src2)>;
4779 def : Pat<(or_is_add GR32:$src1, imm:$src2),
4780 (ADD32ri GR32:$src1, imm:$src2)>;
4781 def : Pat<(or_is_add GR16:$src1, i16immSExt8:$src2),
4782 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4783 def : Pat<(or_is_add GR32:$src1, i32immSExt8:$src2),
4784 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4785 def : Pat<(or_is_add GR16:$src1, GR16:$src2),
4786 (ADD16rr GR16:$src1, GR16:$src2)>;
4787 def : Pat<(or_is_add GR32:$src1, GR32:$src2),
4788 (ADD32rr GR32:$src1, GR32:$src2)>;
4789 } // AddedComplexity
4791 //===----------------------------------------------------------------------===//
4792 // EFLAGS-defining Patterns
4793 //===----------------------------------------------------------------------===//
4796 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
4797 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
4798 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
4801 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
4802 (ADD8rm GR8:$src1, addr:$src2)>;
4803 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
4804 (ADD16rm GR16:$src1, addr:$src2)>;
4805 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
4806 (ADD32rm GR32:$src1, addr:$src2)>;
4809 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
4810 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
4811 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
4812 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
4813 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4814 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
4815 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4818 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
4819 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
4820 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
4823 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
4824 (SUB8rm GR8:$src1, addr:$src2)>;
4825 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
4826 (SUB16rm GR16:$src1, addr:$src2)>;
4827 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
4828 (SUB32rm GR32:$src1, addr:$src2)>;
4831 def : Pat<(sub GR8:$src1, imm:$src2),
4832 (SUB8ri GR8:$src1, imm:$src2)>;
4833 def : Pat<(sub GR16:$src1, imm:$src2),
4834 (SUB16ri GR16:$src1, imm:$src2)>;
4835 def : Pat<(sub GR32:$src1, imm:$src2),
4836 (SUB32ri GR32:$src1, imm:$src2)>;
4837 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
4838 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4839 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
4840 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4843 def : Pat<(mul GR16:$src1, GR16:$src2),
4844 (IMUL16rr GR16:$src1, GR16:$src2)>;
4845 def : Pat<(mul GR32:$src1, GR32:$src2),
4846 (IMUL32rr GR32:$src1, GR32:$src2)>;
4849 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
4850 (IMUL16rm GR16:$src1, addr:$src2)>;
4851 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
4852 (IMUL32rm GR32:$src1, addr:$src2)>;
4855 def : Pat<(mul GR16:$src1, imm:$src2),
4856 (IMUL16rri GR16:$src1, imm:$src2)>;
4857 def : Pat<(mul GR32:$src1, imm:$src2),
4858 (IMUL32rri GR32:$src1, imm:$src2)>;
4859 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
4860 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4861 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
4862 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4864 // reg = mul mem, imm
4865 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
4866 (IMUL16rmi addr:$src1, imm:$src2)>;
4867 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
4868 (IMUL32rmi addr:$src1, imm:$src2)>;
4869 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
4870 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4871 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
4872 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4874 // Optimize multiply by 2 with EFLAGS result.
4875 let AddedComplexity = 2 in {
4876 def : Pat<(X86smul_flag GR16:$src1, 2), (ADD16rr GR16:$src1, GR16:$src1)>;
4877 def : Pat<(X86smul_flag GR32:$src1, 2), (ADD32rr GR32:$src1, GR32:$src1)>;
4880 // Patterns for nodes that do not produce flags, for instructions that do.
4883 def : Pat<(add GR8:$src1 , 1), (INC8r GR8:$src1)>;
4884 def : Pat<(add GR16:$src1, 1), (INC16r GR16:$src1)>, Requires<[In32BitMode]>;
4885 def : Pat<(add GR32:$src1, 1), (INC32r GR32:$src1)>, Requires<[In32BitMode]>;
4888 def : Pat<(add GR8:$src1 , -1), (DEC8r GR8:$src1)>;
4889 def : Pat<(add GR16:$src1, -1), (DEC16r GR16:$src1)>, Requires<[In32BitMode]>;
4890 def : Pat<(add GR32:$src1, -1), (DEC32r GR32:$src1)>, Requires<[In32BitMode]>;
4893 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
4894 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
4895 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
4898 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
4899 (OR8rm GR8:$src1, addr:$src2)>;
4900 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
4901 (OR16rm GR16:$src1, addr:$src2)>;
4902 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
4903 (OR32rm GR32:$src1, addr:$src2)>;
4906 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
4907 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
4908 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
4909 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
4910 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4911 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
4912 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4915 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
4916 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
4917 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
4920 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
4921 (XOR8rm GR8:$src1, addr:$src2)>;
4922 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
4923 (XOR16rm GR16:$src1, addr:$src2)>;
4924 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
4925 (XOR32rm GR32:$src1, addr:$src2)>;
4928 def : Pat<(xor GR8:$src1, imm:$src2),
4929 (XOR8ri GR8:$src1, imm:$src2)>;
4930 def : Pat<(xor GR16:$src1, imm:$src2),
4931 (XOR16ri GR16:$src1, imm:$src2)>;
4932 def : Pat<(xor GR32:$src1, imm:$src2),
4933 (XOR32ri GR32:$src1, imm:$src2)>;
4934 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
4935 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4936 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
4937 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4940 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
4941 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
4942 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
4945 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
4946 (AND8rm GR8:$src1, addr:$src2)>;
4947 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
4948 (AND16rm GR16:$src1, addr:$src2)>;
4949 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
4950 (AND32rm GR32:$src1, addr:$src2)>;
4953 def : Pat<(and GR8:$src1, imm:$src2),
4954 (AND8ri GR8:$src1, imm:$src2)>;
4955 def : Pat<(and GR16:$src1, imm:$src2),
4956 (AND16ri GR16:$src1, imm:$src2)>;
4957 def : Pat<(and GR32:$src1, imm:$src2),
4958 (AND32ri GR32:$src1, imm:$src2)>;
4959 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
4960 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
4961 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
4962 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
4964 //===----------------------------------------------------------------------===//
4965 // Floating Point Stack Support
4966 //===----------------------------------------------------------------------===//
4968 include "X86InstrFPStack.td"
4970 //===----------------------------------------------------------------------===//
4972 //===----------------------------------------------------------------------===//
4974 include "X86Instr64bit.td"
4976 //===----------------------------------------------------------------------===//
4977 // SIMD support (SSE, MMX and AVX)
4978 //===----------------------------------------------------------------------===//
4980 include "X86InstrFragmentsSIMD.td"
4982 //===----------------------------------------------------------------------===//
4983 // FMA - Fused Multiply-Add support (requires FMA)
4984 //===----------------------------------------------------------------------===//
4986 include "X86InstrFMA.td"
4988 //===----------------------------------------------------------------------===//
4989 // XMM Floating point support (requires SSE / SSE2)
4990 //===----------------------------------------------------------------------===//
4992 include "X86InstrSSE.td"
4994 //===----------------------------------------------------------------------===//
4995 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
4996 //===----------------------------------------------------------------------===//
4998 include "X86InstrMMX.td"