1 //===- X86InstrInfo.td - Main X86 Instruction Definition ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
32 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
34 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTX86BrCond : SDTypeProfile<0, 3,
39 [SDTCisVT<0, OtherVT>,
40 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
42 def SDTX86SetCC : SDTypeProfile<1, 2,
44 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86SetCC_C : SDTypeProfile<1, 2,
47 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
49 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
51 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
53 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
54 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
55 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
57 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
58 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
61 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
63 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
67 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
69 def SDTX86Void : SDTypeProfile<0, 0, []>;
71 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
73 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
75 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
77 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
79 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
81 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
82 def SDT_X86MEMBARRIERNoSSE : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
84 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
86 def X86MemBarrierNoSSE : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIERNoSSE,
88 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
90 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
92 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
96 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
97 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
98 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
99 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
101 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
102 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
104 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
105 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
107 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
108 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
110 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
111 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
112 SDNPMayLoad, SDNPMemOperand]>;
113 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
114 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
115 SDNPMayLoad, SDNPMemOperand]>;
116 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
117 [SDNPHasChain, SDNPMayStore,
118 SDNPMayLoad, SDNPMemOperand]>;
119 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
120 [SDNPHasChain, SDNPMayStore,
121 SDNPMayLoad, SDNPMemOperand]>;
122 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
123 [SDNPHasChain, SDNPMayStore,
124 SDNPMayLoad, SDNPMemOperand]>;
125 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
126 [SDNPHasChain, SDNPMayStore,
127 SDNPMayLoad, SDNPMemOperand]>;
128 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
129 [SDNPHasChain, SDNPMayStore,
130 SDNPMayLoad, SDNPMemOperand]>;
131 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
132 [SDNPHasChain, SDNPMayStore,
133 SDNPMayLoad, SDNPMemOperand]>;
134 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
135 [SDNPHasChain, SDNPMayStore,
136 SDNPMayLoad, SDNPMemOperand]>;
137 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
138 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
140 def X86vastart_save_xmm_regs :
141 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
142 SDT_X86VASTART_SAVE_XMM_REGS,
143 [SDNPHasChain, SDNPVariadic]>;
145 def X86callseq_start :
146 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
147 [SDNPHasChain, SDNPOutFlag]>;
149 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
150 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
152 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
153 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
156 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
157 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
158 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
159 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
162 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
163 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
165 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
166 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
168 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
169 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
171 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
174 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
175 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
177 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
179 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
180 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
182 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
185 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
186 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
187 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
189 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
191 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
194 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
196 def X86MingwAlloca : SDNode<"X86ISD::MINGW_ALLOCA", SDTX86Void,
197 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
199 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
202 //===----------------------------------------------------------------------===//
203 // X86 Operand Definitions.
206 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
207 // the index operand of an address, to conform to x86 encoding restrictions.
208 def ptr_rc_nosp : PointerLikeRegClass<1>;
210 // *mem - Operand definitions for the funky X86 addressing mode operands.
212 def X86MemAsmOperand : AsmOperandClass {
214 let SuperClasses = [];
216 def X86AbsMemAsmOperand : AsmOperandClass {
218 let SuperClasses = [X86MemAsmOperand];
220 class X86MemOperand<string printMethod> : Operand<iPTR> {
221 let PrintMethod = printMethod;
222 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
223 let ParserMatchClass = X86MemAsmOperand;
226 def opaque32mem : X86MemOperand<"printopaquemem">;
227 def opaque48mem : X86MemOperand<"printopaquemem">;
228 def opaque80mem : X86MemOperand<"printopaquemem">;
229 def opaque512mem : X86MemOperand<"printopaquemem">;
231 def i8mem : X86MemOperand<"printi8mem">;
232 def i16mem : X86MemOperand<"printi16mem">;
233 def i32mem : X86MemOperand<"printi32mem">;
234 def i64mem : X86MemOperand<"printi64mem">;
235 def i128mem : X86MemOperand<"printi128mem">;
236 def i256mem : X86MemOperand<"printi256mem">;
237 def f32mem : X86MemOperand<"printf32mem">;
238 def f64mem : X86MemOperand<"printf64mem">;
239 def f80mem : X86MemOperand<"printf80mem">;
240 def f128mem : X86MemOperand<"printf128mem">;
241 def f256mem : X86MemOperand<"printf256mem">;
243 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
244 // plain GR64, so that it doesn't potentially require a REX prefix.
245 def i8mem_NOREX : Operand<i64> {
246 let PrintMethod = "printi8mem";
247 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
248 let ParserMatchClass = X86MemAsmOperand;
251 // Special i32mem for addresses of load folding tail calls. These are not
252 // allowed to use callee-saved registers since they must be scheduled
253 // after callee-saved register are popped.
254 def i32mem_TC : Operand<i32> {
255 let PrintMethod = "printi32mem";
256 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
257 let ParserMatchClass = X86MemAsmOperand;
260 // Special i64mem for addresses of load folding tail calls. These are not
261 // allowed to use callee-saved registers since they must be scheduled
262 // after callee-saved register are popped.
263 def i64mem_TC : Operand<i64> {
264 let PrintMethod = "printi64mem";
265 let MIOperandInfo = (ops GR64_TC, i8imm, GR64_TC, i32imm, i8imm);
266 let ParserMatchClass = X86MemAsmOperand;
269 let ParserMatchClass = X86AbsMemAsmOperand,
270 PrintMethod = "print_pcrel_imm" in {
271 def i32imm_pcrel : Operand<i32>;
272 def i16imm_pcrel : Operand<i16>;
274 def offset8 : Operand<i64>;
275 def offset16 : Operand<i64>;
276 def offset32 : Operand<i64>;
277 def offset64 : Operand<i64>;
279 // Branch targets have OtherVT type and print as pc-relative values.
280 def brtarget : Operand<OtherVT>;
281 def brtarget8 : Operand<OtherVT>;
285 def SSECC : Operand<i8> {
286 let PrintMethod = "printSSECC";
289 class ImmSExtAsmOperandClass : AsmOperandClass {
290 let SuperClasses = [ImmAsmOperand];
291 let RenderMethod = "addImmOperands";
294 // Sign-extended immediate classes. We don't need to define the full lattice
295 // here because there is no instruction with an ambiguity between ImmSExti64i32
298 // The strange ranges come from the fact that the assembler always works with
299 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
300 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
303 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
304 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
305 let Name = "ImmSExti64i32";
308 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
309 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
310 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
311 let Name = "ImmSExti16i8";
312 let SuperClasses = [ImmSExti64i32AsmOperand];
315 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
316 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
317 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
318 let Name = "ImmSExti32i8";
322 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
323 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
324 let Name = "ImmSExti64i8";
325 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
326 ImmSExti64i32AsmOperand];
329 // A couple of more descriptive operand definitions.
330 // 16-bits but only 8 bits are significant.
331 def i16i8imm : Operand<i16> {
332 let ParserMatchClass = ImmSExti16i8AsmOperand;
334 // 32-bits but only 8 bits are significant.
335 def i32i8imm : Operand<i32> {
336 let ParserMatchClass = ImmSExti32i8AsmOperand;
339 // 64-bits but only 32 bits are significant.
340 def i64i32imm : Operand<i64> {
341 let ParserMatchClass = ImmSExti64i32AsmOperand;
344 // 64-bits but only 32 bits are significant, and those bits are treated as being
346 def i64i32imm_pcrel : Operand<i64> {
347 let PrintMethod = "print_pcrel_imm";
348 let ParserMatchClass = X86AbsMemAsmOperand;
351 // 64-bits but only 8 bits are significant.
352 def i64i8imm : Operand<i64> {
353 let ParserMatchClass = ImmSExti64i8AsmOperand;
356 def lea64_32mem : Operand<i32> {
357 let PrintMethod = "printi32mem";
358 let AsmOperandLowerMethod = "lower_lea64_32mem";
359 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm);
360 let ParserMatchClass = X86MemAsmOperand;
364 //===----------------------------------------------------------------------===//
365 // X86 Complex Pattern Definitions.
368 // Define X86 specific addressing mode.
369 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
370 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
371 [add, sub, mul, X86mul_imm, shl, or, frameindex],
373 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
374 [tglobaltlsaddr], []>;
376 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
377 [add, sub, mul, X86mul_imm, shl, or, frameindex,
380 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
381 [tglobaltlsaddr], []>;
383 //===----------------------------------------------------------------------===//
384 // X86 Instruction Predicate Definitions.
385 def HasCMov : Predicate<"Subtarget->hasCMov()">;
386 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
388 // FIXME: temporary hack to let codegen assert or generate poor code in case
389 // no AVX version of the desired intructions is present, this is better for
390 // incremental dev (without fallbacks it's easier to spot what's missing)
391 def HasMMX : Predicate<"Subtarget->hasMMX() && !Subtarget->hasAVX()">;
392 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
393 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
394 def HasSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
395 def HasSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
396 def HasSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
397 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
398 def HasSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
399 def HasSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
400 def HasSSE4A : Predicate<"Subtarget->hasSSE4A() && !Subtarget->hasAVX()">;
402 def HasAVX : Predicate<"Subtarget->hasAVX()">;
403 def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">;
404 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
405 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
406 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
407 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
408 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
409 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
410 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
411 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
412 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
413 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
414 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
415 "TM.getCodeModel() != CodeModel::Kernel">;
416 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
417 "TM.getCodeModel() == CodeModel::Kernel">;
418 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
419 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
420 def OptForSize : Predicate<"OptForSize">;
421 def OptForSpeed : Predicate<"!OptForSize">;
422 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
423 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
424 def HasAES : Predicate<"Subtarget->hasAES()">;
426 //===----------------------------------------------------------------------===//
427 // X86 Instruction Format Definitions.
430 include "X86InstrFormats.td"
432 //===----------------------------------------------------------------------===//
433 // Pattern fragments...
436 // X86 specific condition code. These correspond to CondCode in
437 // X86InstrInfo.h. They must be kept in synch.
438 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
439 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
440 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
441 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
442 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
443 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
444 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
445 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
446 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
447 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
448 def X86_COND_NO : PatLeaf<(i8 10)>;
449 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
450 def X86_COND_NS : PatLeaf<(i8 12)>;
451 def X86_COND_O : PatLeaf<(i8 13)>;
452 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
453 def X86_COND_S : PatLeaf<(i8 15)>;
455 def immSext8 : PatLeaf<(imm), [{ return immSext8(N); }]>;
457 def i16immSExt8 : PatLeaf<(i16 immSext8)>;
458 def i32immSExt8 : PatLeaf<(i32 immSext8)>;
459 def i64immSExt8 : PatLeaf<(i64 immSext8)>;
460 def i64immSExt32 : PatLeaf<(i64 imm), [{ return i64immSExt32(N); }]>;
461 def i64immZExt32 : PatLeaf<(i64 imm), [{
462 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
463 // unsignedsign extended field.
464 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
467 // Helper fragments for loads.
468 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
469 // known to be 32-bit aligned or better. Ditto for i8 to i16.
470 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
471 LoadSDNode *LD = cast<LoadSDNode>(N);
472 ISD::LoadExtType ExtType = LD->getExtensionType();
473 if (ExtType == ISD::NON_EXTLOAD)
475 if (ExtType == ISD::EXTLOAD)
476 return LD->getAlignment() >= 2 && !LD->isVolatile();
480 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
481 LoadSDNode *LD = cast<LoadSDNode>(N);
482 ISD::LoadExtType ExtType = LD->getExtensionType();
483 if (ExtType == ISD::EXTLOAD)
484 return LD->getAlignment() >= 2 && !LD->isVolatile();
488 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
489 LoadSDNode *LD = cast<LoadSDNode>(N);
490 ISD::LoadExtType ExtType = LD->getExtensionType();
491 if (ExtType == ISD::NON_EXTLOAD)
493 if (ExtType == ISD::EXTLOAD)
494 return LD->getAlignment() >= 4 && !LD->isVolatile();
498 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
499 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
500 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
501 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
502 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
504 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
505 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
506 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
507 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
508 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
509 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
511 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
512 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
513 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
514 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
515 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
516 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
517 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
518 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
519 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
520 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
522 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
523 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
524 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
525 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
526 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
527 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
528 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
529 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
530 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
531 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
534 // An 'and' node with a single use.
535 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
536 return N->hasOneUse();
538 // An 'srl' node with a single use.
539 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
540 return N->hasOneUse();
542 // An 'trunc' node with a single use.
543 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
544 return N->hasOneUse();
547 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
548 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
549 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
550 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
552 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
553 APInt Mask = APInt::getAllOnesValue(BitWidth);
554 APInt KnownZero0, KnownOne0;
555 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
556 APInt KnownZero1, KnownOne1;
557 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
558 return (~KnownZero0 & ~KnownZero1) == 0;
561 //===----------------------------------------------------------------------===//
566 let neverHasSideEffects = 1 in {
567 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
568 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
569 "nop{w}\t$zero", []>, TB, OpSize;
570 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
571 "nop{l}\t$zero", []>, TB;
575 // Constructing a stack frame.
576 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
577 "enter\t$len, $lvl", []>;
579 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
580 def LEAVE : I<0xC9, RawFrm,
581 (outs), (ins), "leave", []>, Requires<[In32BitMode]>;
583 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
584 def LEAVE64 : I<0xC9, RawFrm,
585 (outs), (ins), "leave", []>, Requires<[In64BitMode]>;
587 //===----------------------------------------------------------------------===//
588 // Miscellaneous Instructions.
591 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
593 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
595 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
596 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
598 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
600 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
601 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
603 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
604 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
605 Requires<[In32BitMode]>;
608 let mayStore = 1 in {
609 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
611 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
612 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
614 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
616 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
617 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
619 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
620 "push{l}\t$imm", []>;
621 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
622 "push{w}\t$imm", []>, OpSize;
623 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
624 "push{l}\t$imm", []>;
626 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
627 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
628 Requires<[In32BitMode]>;
633 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
635 def POP64r : I<0x58, AddRegFrm,
636 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
637 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
638 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
640 let mayStore = 1 in {
641 def PUSH64r : I<0x50, AddRegFrm,
642 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
643 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
644 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
648 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
649 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
650 "push{q}\t$imm", []>;
651 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
652 "push{q}\t$imm", []>;
653 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
654 "push{q}\t$imm", []>;
657 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
658 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>,
659 Requires<[In64BitMode]>;
660 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
661 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>,
662 Requires<[In64BitMode]>;
666 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
667 mayLoad=1, neverHasSideEffects=1 in {
668 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>,
669 Requires<[In32BitMode]>;
671 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
672 mayStore=1, neverHasSideEffects=1 in {
673 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>,
674 Requires<[In32BitMode]>;
677 let Constraints = "$src = $dst" in { // GR32 = bswap GR32
678 def BSWAP32r : I<0xC8, AddRegFrm,
679 (outs GR32:$dst), (ins GR32:$src),
681 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
683 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
685 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
686 } // Constraints = "$src = $dst"
688 // Bit scan instructions.
689 let Defs = [EFLAGS] in {
690 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
691 "bsf{w}\t{$src, $dst|$dst, $src}",
692 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
693 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
694 "bsf{w}\t{$src, $dst|$dst, $src}",
695 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
697 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
698 "bsf{l}\t{$src, $dst|$dst, $src}",
699 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
700 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
701 "bsf{l}\t{$src, $dst|$dst, $src}",
702 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
703 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
704 "bsf{q}\t{$src, $dst|$dst, $src}",
705 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, TB;
706 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
707 "bsf{q}\t{$src, $dst|$dst, $src}",
708 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, TB;
710 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
711 "bsr{w}\t{$src, $dst|$dst, $src}",
712 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
713 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
714 "bsr{w}\t{$src, $dst|$dst, $src}",
715 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
717 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
718 "bsr{l}\t{$src, $dst|$dst, $src}",
719 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
720 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
721 "bsr{l}\t{$src, $dst|$dst, $src}",
722 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
723 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
724 "bsr{q}\t{$src, $dst|$dst, $src}",
725 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, TB;
726 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
727 "bsr{q}\t{$src, $dst|$dst, $src}",
728 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, TB;
731 let neverHasSideEffects = 1 in
732 def LEA16r : I<0x8D, MRMSrcMem,
733 (outs GR16:$dst), (ins i32mem:$src),
734 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
735 let isReMaterializable = 1 in
736 def LEA32r : I<0x8D, MRMSrcMem,
737 (outs GR32:$dst), (ins i32mem:$src),
738 "lea{l}\t{$src|$dst}, {$dst|$src}",
739 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
741 def LEA64_32r : I<0x8D, MRMSrcMem,
742 (outs GR32:$dst), (ins lea64_32mem:$src),
743 "lea{l}\t{$src|$dst}, {$dst|$src}",
744 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
746 let isReMaterializable = 1 in
747 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
748 "lea{q}\t{$src|$dst}, {$dst|$src}",
749 [(set GR64:$dst, lea64addr:$src)]>;
753 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
754 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
755 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
756 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
757 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
758 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", []>;
761 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
762 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
763 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
764 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
765 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
766 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
767 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
768 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
769 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", []>;
771 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
772 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
773 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
774 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", []>;
776 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
777 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
778 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
779 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", []>;
782 //===----------------------------------------------------------------------===//
783 // Move Instructions.
785 let neverHasSideEffects = 1 in {
786 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
787 "mov{b}\t{$src, $dst|$dst, $src}", []>;
788 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
789 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
790 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
791 "mov{l}\t{$src, $dst|$dst, $src}", []>;
793 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
794 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
795 "mov{b}\t{$src, $dst|$dst, $src}",
796 [(set GR8:$dst, imm:$src)]>;
797 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
798 "mov{w}\t{$src, $dst|$dst, $src}",
799 [(set GR16:$dst, imm:$src)]>, OpSize;
800 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
801 "mov{l}\t{$src, $dst|$dst, $src}",
802 [(set GR32:$dst, imm:$src)]>;
805 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
806 "mov{b}\t{$src, $dst|$dst, $src}",
807 [(store (i8 imm:$src), addr:$dst)]>;
808 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
809 "mov{w}\t{$src, $dst|$dst, $src}",
810 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
811 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
812 "mov{l}\t{$src, $dst|$dst, $src}",
813 [(store (i32 imm:$src), addr:$dst)]>;
815 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
816 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
817 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
818 "mov{b}\t{$src, %al|%al, $src}", []>,
819 Requires<[In32BitMode]>;
820 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
821 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize,
822 Requires<[In32BitMode]>;
823 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
824 "mov{l}\t{$src, %eax|%eax, $src}", []>,
825 Requires<[In32BitMode]>;
826 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
827 "mov{b}\t{%al, $dst|$dst, %al}", []>,
828 Requires<[In32BitMode]>;
829 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
830 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize,
831 Requires<[In32BitMode]>;
832 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
833 "mov{l}\t{%eax, $dst|$dst, %eax}", []>,
834 Requires<[In32BitMode]>;
837 let isCodeGenOnly = 1 in {
838 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
839 "mov{b}\t{$src, $dst|$dst, $src}", []>;
840 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
841 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
842 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
843 "mov{l}\t{$src, $dst|$dst, $src}", []>;
846 let canFoldAsLoad = 1, isReMaterializable = 1 in {
847 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
848 "mov{b}\t{$src, $dst|$dst, $src}",
849 [(set GR8:$dst, (loadi8 addr:$src))]>;
850 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
851 "mov{w}\t{$src, $dst|$dst, $src}",
852 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
853 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
854 "mov{l}\t{$src, $dst|$dst, $src}",
855 [(set GR32:$dst, (loadi32 addr:$src))]>;
858 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
859 "mov{b}\t{$src, $dst|$dst, $src}",
860 [(store GR8:$src, addr:$dst)]>;
861 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
862 "mov{w}\t{$src, $dst|$dst, $src}",
863 [(store GR16:$src, addr:$dst)]>, OpSize;
864 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
865 "mov{l}\t{$src, $dst|$dst, $src}",
866 [(store GR32:$src, addr:$dst)]>;
868 /// Versions of MOV32rr, MOV32rm, and MOV32mr for i32mem_TC and GR32_TC.
869 let isCodeGenOnly = 1 in {
870 let neverHasSideEffects = 1 in
871 def MOV32rr_TC : I<0x89, MRMDestReg, (outs GR32_TC:$dst), (ins GR32_TC:$src),
872 "mov{l}\t{$src, $dst|$dst, $src}", []>;
875 canFoldAsLoad = 1, isReMaterializable = 1 in
876 def MOV32rm_TC : I<0x8B, MRMSrcMem, (outs GR32_TC:$dst), (ins i32mem_TC:$src),
877 "mov{l}\t{$src, $dst|$dst, $src}",
881 def MOV32mr_TC : I<0x89, MRMDestMem, (outs), (ins i32mem_TC:$dst, GR32_TC:$src),
882 "mov{l}\t{$src, $dst|$dst, $src}",
886 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
887 // that they can be used for copying and storing h registers, which can't be
888 // encoded when a REX prefix is present.
889 let isCodeGenOnly = 1 in {
890 let neverHasSideEffects = 1 in
891 def MOV8rr_NOREX : I<0x88, MRMDestReg,
892 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
893 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
895 def MOV8mr_NOREX : I<0x88, MRMDestMem,
896 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
897 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
899 canFoldAsLoad = 1, isReMaterializable = 1 in
900 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
901 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
902 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
905 //===----------------------------------------------------------------------===//
906 // Fixed-Register Multiplication and Division Instructions...
909 // Extra precision multiplication
911 // AL is really implied by AX, but the registers in Defs must match the
912 // SDNode results (i8, i32).
913 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
914 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
915 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
916 // This probably ought to be moved to a def : Pat<> if the
917 // syntax can be accepted.
918 [(set AL, (mul AL, GR8:$src)),
919 (implicit EFLAGS)]>; // AL,AH = AL*GR8
921 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
922 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
924 []>, OpSize; // AX,DX = AX*GR16
926 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
927 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
929 []>; // EAX,EDX = EAX*GR32
931 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
932 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
934 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
935 // This probably ought to be moved to a def : Pat<> if the
936 // syntax can be accepted.
937 [(set AL, (mul AL, (loadi8 addr:$src))),
938 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
940 let mayLoad = 1, neverHasSideEffects = 1 in {
941 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
942 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
944 []>, OpSize; // AX,DX = AX*[mem16]
946 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
947 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
949 []>; // EAX,EDX = EAX*[mem32]
952 let neverHasSideEffects = 1 in {
953 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
954 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
956 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
957 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
958 OpSize; // AX,DX = AX*GR16
959 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
960 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
961 // EAX,EDX = EAX*GR32
963 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
964 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
965 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
966 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
967 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
968 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
969 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
970 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
971 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
973 } // neverHasSideEffects
975 // unsigned division/remainder
976 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
977 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
979 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
980 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
981 "div{w}\t$src", []>, OpSize;
982 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
983 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
986 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
987 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
989 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
990 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
991 "div{w}\t$src", []>, OpSize;
992 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
993 // EDX:EAX/[mem32] = EAX,EDX
994 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
998 // Signed division/remainder.
999 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1000 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1001 "idiv{b}\t$src", []>;
1002 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1003 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1004 "idiv{w}\t$src", []>, OpSize;
1005 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1006 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1007 "idiv{l}\t$src", []>;
1008 let mayLoad = 1, mayLoad = 1 in {
1009 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1010 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1011 "idiv{b}\t$src", []>;
1012 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1013 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1014 "idiv{w}\t$src", []>, OpSize;
1015 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1016 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1017 // EDX:EAX/[mem32] = EAX,EDX
1018 "idiv{l}\t$src", []>;
1021 //===----------------------------------------------------------------------===//
1022 // Two address Instructions.
1024 let Constraints = "$src1 = $dst" in {
1026 // unary instructions
1027 let CodeSize = 2 in {
1028 let Defs = [EFLAGS] in {
1029 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
1031 [(set GR8:$dst, (ineg GR8:$src1)),
1032 (implicit EFLAGS)]>;
1033 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
1035 [(set GR16:$dst, (ineg GR16:$src1)),
1036 (implicit EFLAGS)]>, OpSize;
1037 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
1039 [(set GR32:$dst, (ineg GR32:$src1)),
1040 (implicit EFLAGS)]>;
1042 let Constraints = "" in {
1043 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
1045 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1046 (implicit EFLAGS)]>;
1047 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
1049 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1050 (implicit EFLAGS)]>, OpSize;
1051 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
1053 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1054 (implicit EFLAGS)]>;
1055 } // Constraints = ""
1056 } // Defs = [EFLAGS]
1058 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1059 let AddedComplexity = 15 in {
1060 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
1062 [(set GR8:$dst, (not GR8:$src1))]>;
1063 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
1065 [(set GR16:$dst, (not GR16:$src1))]>, OpSize;
1066 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
1068 [(set GR32:$dst, (not GR32:$src1))]>;
1070 let Constraints = "" in {
1071 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
1073 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1074 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
1076 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1077 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
1079 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1080 } // Constraints = ""
1083 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1084 let Defs = [EFLAGS] in {
1086 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1088 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>;
1090 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1091 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
1093 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
1094 OpSize, Requires<[In32BitMode]>;
1095 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
1097 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
1098 Requires<[In32BitMode]>;
1100 let Constraints = "", CodeSize = 2 in {
1101 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1102 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1103 (implicit EFLAGS)]>;
1104 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1105 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1106 (implicit EFLAGS)]>,
1107 OpSize, Requires<[In32BitMode]>;
1108 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1109 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1110 (implicit EFLAGS)]>,
1111 Requires<[In32BitMode]>;
1112 } // Constraints = "", CodeSize = 2
1115 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1117 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>;
1118 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1119 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
1121 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
1122 OpSize, Requires<[In32BitMode]>;
1123 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
1125 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
1126 Requires<[In32BitMode]>;
1129 let Constraints = "", CodeSize = 2 in {
1130 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1131 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1132 (implicit EFLAGS)]>;
1133 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1134 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1135 (implicit EFLAGS)]>,
1136 OpSize, Requires<[In32BitMode]>;
1137 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1138 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1139 (implicit EFLAGS)]>,
1140 Requires<[In32BitMode]>;
1141 } // Constraints = "", CodeSize = 2
1142 } // Defs = [EFLAGS]
1144 // Logical operators...
1145 let Defs = [EFLAGS] in {
1146 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1147 def AND8rr : I<0x20, MRMDestReg,
1148 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1149 "and{b}\t{$src2, $dst|$dst, $src2}",
1150 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, GR8:$src2))]>;
1151 def AND16rr : I<0x21, MRMDestReg,
1152 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1153 "and{w}\t{$src2, $dst|$dst, $src2}",
1154 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1155 GR16:$src2))]>, OpSize;
1156 def AND32rr : I<0x21, MRMDestReg,
1157 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1158 "and{l}\t{$src2, $dst|$dst, $src2}",
1159 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1163 // AND instructions with the destination register in REG and the source register
1164 // in R/M. Included for the disassembler.
1165 let isCodeGenOnly = 1 in {
1166 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1167 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1168 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1169 (ins GR16:$src1, GR16:$src2),
1170 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1171 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1172 (ins GR32:$src1, GR32:$src2),
1173 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1176 def AND8rm : I<0x22, MRMSrcMem,
1177 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1178 "and{b}\t{$src2, $dst|$dst, $src2}",
1179 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1180 (loadi8 addr:$src2)))]>;
1181 def AND16rm : I<0x23, MRMSrcMem,
1182 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1183 "and{w}\t{$src2, $dst|$dst, $src2}",
1184 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1185 (loadi16 addr:$src2)))]>,
1187 def AND32rm : I<0x23, MRMSrcMem,
1188 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1189 "and{l}\t{$src2, $dst|$dst, $src2}",
1190 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1191 (loadi32 addr:$src2)))]>;
1193 def AND8ri : Ii8<0x80, MRM4r,
1194 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1195 "and{b}\t{$src2, $dst|$dst, $src2}",
1196 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1198 def AND16ri : Ii16<0x81, MRM4r,
1199 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1200 "and{w}\t{$src2, $dst|$dst, $src2}",
1201 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1202 imm:$src2))]>, OpSize;
1203 def AND32ri : Ii32<0x81, MRM4r,
1204 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1205 "and{l}\t{$src2, $dst|$dst, $src2}",
1206 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1208 def AND16ri8 : Ii8<0x83, MRM4r,
1209 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1210 "and{w}\t{$src2, $dst|$dst, $src2}",
1211 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1212 i16immSExt8:$src2))]>,
1214 def AND32ri8 : Ii8<0x83, MRM4r,
1215 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1216 "and{l}\t{$src2, $dst|$dst, $src2}",
1217 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1218 i32immSExt8:$src2))]>;
1220 let Constraints = "" in {
1221 def AND8mr : I<0x20, MRMDestMem,
1222 (outs), (ins i8mem :$dst, GR8 :$src),
1223 "and{b}\t{$src, $dst|$dst, $src}",
1224 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1225 (implicit EFLAGS)]>;
1226 def AND16mr : I<0x21, MRMDestMem,
1227 (outs), (ins i16mem:$dst, GR16:$src),
1228 "and{w}\t{$src, $dst|$dst, $src}",
1229 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1230 (implicit EFLAGS)]>,
1232 def AND32mr : I<0x21, MRMDestMem,
1233 (outs), (ins i32mem:$dst, GR32:$src),
1234 "and{l}\t{$src, $dst|$dst, $src}",
1235 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1236 (implicit EFLAGS)]>;
1237 def AND8mi : Ii8<0x80, MRM4m,
1238 (outs), (ins i8mem :$dst, i8imm :$src),
1239 "and{b}\t{$src, $dst|$dst, $src}",
1240 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1241 (implicit EFLAGS)]>;
1242 def AND16mi : Ii16<0x81, MRM4m,
1243 (outs), (ins i16mem:$dst, i16imm:$src),
1244 "and{w}\t{$src, $dst|$dst, $src}",
1245 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1246 (implicit EFLAGS)]>,
1248 def AND32mi : Ii32<0x81, MRM4m,
1249 (outs), (ins i32mem:$dst, i32imm:$src),
1250 "and{l}\t{$src, $dst|$dst, $src}",
1251 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1252 (implicit EFLAGS)]>;
1253 def AND16mi8 : Ii8<0x83, MRM4m,
1254 (outs), (ins i16mem:$dst, i16i8imm :$src),
1255 "and{w}\t{$src, $dst|$dst, $src}",
1256 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1257 (implicit EFLAGS)]>,
1259 def AND32mi8 : Ii8<0x83, MRM4m,
1260 (outs), (ins i32mem:$dst, i32i8imm :$src),
1261 "and{l}\t{$src, $dst|$dst, $src}",
1262 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1263 (implicit EFLAGS)]>;
1265 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1266 "and{b}\t{$src, %al|%al, $src}", []>;
1267 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1268 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1269 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1270 "and{l}\t{$src, %eax|%eax, $src}", []>;
1272 } // Constraints = ""
1275 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1276 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1277 (ins GR8 :$src1, GR8 :$src2),
1278 "or{b}\t{$src2, $dst|$dst, $src2}",
1279 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
1280 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1281 (ins GR16:$src1, GR16:$src2),
1282 "or{w}\t{$src2, $dst|$dst, $src2}",
1283 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
1285 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1286 (ins GR32:$src1, GR32:$src2),
1287 "or{l}\t{$src2, $dst|$dst, $src2}",
1288 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
1291 // OR instructions with the destination register in REG and the source register
1292 // in R/M. Included for the disassembler.
1293 let isCodeGenOnly = 1 in {
1294 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1295 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1296 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1297 (ins GR16:$src1, GR16:$src2),
1298 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1299 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1300 (ins GR32:$src1, GR32:$src2),
1301 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
1304 def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst),
1305 (ins GR8 :$src1, i8mem :$src2),
1306 "or{b}\t{$src2, $dst|$dst, $src2}",
1307 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
1308 (load addr:$src2)))]>;
1309 def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst),
1310 (ins GR16:$src1, i16mem:$src2),
1311 "or{w}\t{$src2, $dst|$dst, $src2}",
1312 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1313 (load addr:$src2)))]>,
1315 def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst),
1316 (ins GR32:$src1, i32mem:$src2),
1317 "or{l}\t{$src2, $dst|$dst, $src2}",
1318 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1319 (load addr:$src2)))]>;
1321 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
1322 (ins GR8 :$src1, i8imm:$src2),
1323 "or{b}\t{$src2, $dst|$dst, $src2}",
1324 [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
1325 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
1326 (ins GR16:$src1, i16imm:$src2),
1327 "or{w}\t{$src2, $dst|$dst, $src2}",
1328 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1329 imm:$src2))]>, OpSize;
1330 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
1331 (ins GR32:$src1, i32imm:$src2),
1332 "or{l}\t{$src2, $dst|$dst, $src2}",
1333 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1336 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
1337 (ins GR16:$src1, i16i8imm:$src2),
1338 "or{w}\t{$src2, $dst|$dst, $src2}",
1339 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1340 i16immSExt8:$src2))]>, OpSize;
1341 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
1342 (ins GR32:$src1, i32i8imm:$src2),
1343 "or{l}\t{$src2, $dst|$dst, $src2}",
1344 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1345 i32immSExt8:$src2))]>;
1346 let Constraints = "" in {
1347 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1348 "or{b}\t{$src, $dst|$dst, $src}",
1349 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1350 (implicit EFLAGS)]>;
1351 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1352 "or{w}\t{$src, $dst|$dst, $src}",
1353 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1354 (implicit EFLAGS)]>, OpSize;
1355 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1356 "or{l}\t{$src, $dst|$dst, $src}",
1357 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1358 (implicit EFLAGS)]>;
1359 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1360 "or{b}\t{$src, $dst|$dst, $src}",
1361 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1362 (implicit EFLAGS)]>;
1363 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1364 "or{w}\t{$src, $dst|$dst, $src}",
1365 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1366 (implicit EFLAGS)]>,
1368 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1369 "or{l}\t{$src, $dst|$dst, $src}",
1370 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1371 (implicit EFLAGS)]>;
1372 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1373 "or{w}\t{$src, $dst|$dst, $src}",
1374 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1375 (implicit EFLAGS)]>,
1377 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1378 "or{l}\t{$src, $dst|$dst, $src}",
1379 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1380 (implicit EFLAGS)]>;
1382 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
1383 "or{b}\t{$src, %al|%al, $src}", []>;
1384 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
1385 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1386 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
1387 "or{l}\t{$src, %eax|%eax, $src}", []>;
1388 } // Constraints = ""
1391 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1392 def XOR8rr : I<0x30, MRMDestReg,
1393 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1394 "xor{b}\t{$src2, $dst|$dst, $src2}",
1395 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
1397 def XOR16rr : I<0x31, MRMDestReg,
1398 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1399 "xor{w}\t{$src2, $dst|$dst, $src2}",
1400 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
1401 GR16:$src2))]>, OpSize;
1402 def XOR32rr : I<0x31, MRMDestReg,
1403 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1404 "xor{l}\t{$src2, $dst|$dst, $src2}",
1405 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
1407 } // isCommutable = 1
1409 // XOR instructions with the destination register in REG and the source register
1410 // in R/M. Included for the disassembler.
1411 let isCodeGenOnly = 1 in {
1412 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1413 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
1414 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
1415 (ins GR16:$src1, GR16:$src2),
1416 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1417 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
1418 (ins GR32:$src1, GR32:$src2),
1419 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
1422 def XOR8rm : I<0x32, MRMSrcMem,
1423 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1424 "xor{b}\t{$src2, $dst|$dst, $src2}",
1425 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
1426 (load addr:$src2)))]>;
1427 def XOR16rm : I<0x33, MRMSrcMem,
1428 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1429 "xor{w}\t{$src2, $dst|$dst, $src2}",
1430 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
1431 (load addr:$src2)))]>,
1433 def XOR32rm : I<0x33, MRMSrcMem,
1434 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1435 "xor{l}\t{$src2, $dst|$dst, $src2}",
1436 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
1437 (load addr:$src2)))]>;
1439 def XOR8ri : Ii8<0x80, MRM6r,
1440 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1441 "xor{b}\t{$src2, $dst|$dst, $src2}",
1442 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
1443 def XOR16ri : Ii16<0x81, MRM6r,
1444 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1445 "xor{w}\t{$src2, $dst|$dst, $src2}",
1446 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
1447 imm:$src2))]>, OpSize;
1448 def XOR32ri : Ii32<0x81, MRM6r,
1449 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1450 "xor{l}\t{$src2, $dst|$dst, $src2}",
1451 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
1453 def XOR16ri8 : Ii8<0x83, MRM6r,
1454 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1455 "xor{w}\t{$src2, $dst|$dst, $src2}",
1456 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
1457 i16immSExt8:$src2))]>,
1459 def XOR32ri8 : Ii8<0x83, MRM6r,
1460 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1461 "xor{l}\t{$src2, $dst|$dst, $src2}",
1462 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
1463 i32immSExt8:$src2))]>;
1465 let Constraints = "" in {
1466 def XOR8mr : I<0x30, MRMDestMem,
1467 (outs), (ins i8mem :$dst, GR8 :$src),
1468 "xor{b}\t{$src, $dst|$dst, $src}",
1469 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
1470 (implicit EFLAGS)]>;
1471 def XOR16mr : I<0x31, MRMDestMem,
1472 (outs), (ins i16mem:$dst, GR16:$src),
1473 "xor{w}\t{$src, $dst|$dst, $src}",
1474 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
1475 (implicit EFLAGS)]>,
1477 def XOR32mr : I<0x31, MRMDestMem,
1478 (outs), (ins i32mem:$dst, GR32:$src),
1479 "xor{l}\t{$src, $dst|$dst, $src}",
1480 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
1481 (implicit EFLAGS)]>;
1482 def XOR8mi : Ii8<0x80, MRM6m,
1483 (outs), (ins i8mem :$dst, i8imm :$src),
1484 "xor{b}\t{$src, $dst|$dst, $src}",
1485 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
1486 (implicit EFLAGS)]>;
1487 def XOR16mi : Ii16<0x81, MRM6m,
1488 (outs), (ins i16mem:$dst, i16imm:$src),
1489 "xor{w}\t{$src, $dst|$dst, $src}",
1490 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
1491 (implicit EFLAGS)]>,
1493 def XOR32mi : Ii32<0x81, MRM6m,
1494 (outs), (ins i32mem:$dst, i32imm:$src),
1495 "xor{l}\t{$src, $dst|$dst, $src}",
1496 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
1497 (implicit EFLAGS)]>;
1498 def XOR16mi8 : Ii8<0x83, MRM6m,
1499 (outs), (ins i16mem:$dst, i16i8imm :$src),
1500 "xor{w}\t{$src, $dst|$dst, $src}",
1501 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
1502 (implicit EFLAGS)]>,
1504 def XOR32mi8 : Ii8<0x83, MRM6m,
1505 (outs), (ins i32mem:$dst, i32i8imm :$src),
1506 "xor{l}\t{$src, $dst|$dst, $src}",
1507 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
1508 (implicit EFLAGS)]>;
1510 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
1511 "xor{b}\t{$src, %al|%al, $src}", []>;
1512 def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
1513 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1514 def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
1515 "xor{l}\t{$src, %eax|%eax, $src}", []>;
1516 } // Constraints = ""
1517 } // Defs = [EFLAGS]
1519 // Shift instructions
1520 let Defs = [EFLAGS] in {
1521 let Uses = [CL] in {
1522 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
1523 "shl{b}\t{%cl, $dst|$dst, CL}",
1524 [(set GR8:$dst, (shl GR8:$src1, CL))]>;
1525 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
1526 "shl{w}\t{%cl, $dst|$dst, CL}",
1527 [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize;
1528 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
1529 "shl{l}\t{%cl, $dst|$dst, CL}",
1530 [(set GR32:$dst, (shl GR32:$src1, CL))]>;
1533 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1534 "shl{b}\t{$src2, $dst|$dst, $src2}",
1535 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1537 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1538 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1539 "shl{w}\t{$src2, $dst|$dst, $src2}",
1540 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1541 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1542 "shl{l}\t{$src2, $dst|$dst, $src2}",
1543 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1545 // NOTE: We don't include patterns for shifts of a register by one, because
1546 // 'add reg,reg' is cheaper.
1548 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
1549 "shl{b}\t$dst", []>;
1550 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
1551 "shl{w}\t$dst", []>, OpSize;
1552 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
1553 "shl{l}\t$dst", []>;
1555 } // isConvertibleToThreeAddress = 1
1557 let Constraints = "" in {
1558 let Uses = [CL] in {
1559 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1560 "shl{b}\t{%cl, $dst|$dst, CL}",
1561 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1562 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1563 "shl{w}\t{%cl, $dst|$dst, CL}",
1564 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1565 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1566 "shl{l}\t{%cl, $dst|$dst, CL}",
1567 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1569 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1570 "shl{b}\t{$src, $dst|$dst, $src}",
1571 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1572 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1573 "shl{w}\t{$src, $dst|$dst, $src}",
1574 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1576 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1577 "shl{l}\t{$src, $dst|$dst, $src}",
1578 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1581 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1583 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1584 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1586 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1588 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1590 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1591 } // Constraints = ""
1593 let Uses = [CL] in {
1594 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
1595 "shr{b}\t{%cl, $dst|$dst, CL}",
1596 [(set GR8:$dst, (srl GR8:$src1, CL))]>;
1597 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1598 "shr{w}\t{%cl, $dst|$dst, CL}",
1599 [(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize;
1600 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1601 "shr{l}\t{%cl, $dst|$dst, CL}",
1602 [(set GR32:$dst, (srl GR32:$src1, CL))]>;
1605 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1606 "shr{b}\t{$src2, $dst|$dst, $src2}",
1607 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1608 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1609 "shr{w}\t{$src2, $dst|$dst, $src2}",
1610 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1611 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1612 "shr{l}\t{$src2, $dst|$dst, $src2}",
1613 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1616 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1618 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1619 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1621 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1622 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1624 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1626 let Constraints = "" in {
1627 let Uses = [CL] in {
1628 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1629 "shr{b}\t{%cl, $dst|$dst, CL}",
1630 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1631 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1632 "shr{w}\t{%cl, $dst|$dst, CL}",
1633 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1635 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1636 "shr{l}\t{%cl, $dst|$dst, CL}",
1637 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1639 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1640 "shr{b}\t{$src, $dst|$dst, $src}",
1641 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1642 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1643 "shr{w}\t{$src, $dst|$dst, $src}",
1644 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1646 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1647 "shr{l}\t{$src, $dst|$dst, $src}",
1648 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1651 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1653 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1654 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1656 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1657 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1659 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1660 } // Constraints = ""
1662 let Uses = [CL] in {
1663 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1664 "sar{b}\t{%cl, $dst|$dst, CL}",
1665 [(set GR8:$dst, (sra GR8:$src1, CL))]>;
1666 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1667 "sar{w}\t{%cl, $dst|$dst, CL}",
1668 [(set GR16:$dst, (sra GR16:$src1, CL))]>, OpSize;
1669 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1670 "sar{l}\t{%cl, $dst|$dst, CL}",
1671 [(set GR32:$dst, (sra GR32:$src1, CL))]>;
1674 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1675 "sar{b}\t{$src2, $dst|$dst, $src2}",
1676 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1677 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1678 "sar{w}\t{$src2, $dst|$dst, $src2}",
1679 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1681 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1682 "sar{l}\t{$src2, $dst|$dst, $src2}",
1683 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1686 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1688 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1689 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1691 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1692 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1694 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1696 let Constraints = "" in {
1697 let Uses = [CL] in {
1698 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1699 "sar{b}\t{%cl, $dst|$dst, CL}",
1700 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
1701 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1702 "sar{w}\t{%cl, $dst|$dst, CL}",
1703 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1704 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1705 "sar{l}\t{%cl, $dst|$dst, CL}",
1706 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1708 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1709 "sar{b}\t{$src, $dst|$dst, $src}",
1710 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1711 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1712 "sar{w}\t{$src, $dst|$dst, $src}",
1713 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1715 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1716 "sar{l}\t{$src, $dst|$dst, $src}",
1717 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1720 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1722 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1723 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1725 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1727 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
1729 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1730 } // Constraints = ""
1732 // Rotate instructions
1734 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
1735 "rcl{b}\t{1, $dst|$dst, 1}", []>;
1736 let Uses = [CL] in {
1737 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
1738 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
1740 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
1741 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
1743 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
1744 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
1745 let Uses = [CL] in {
1746 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
1747 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
1749 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
1750 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
1752 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
1753 "rcl{l}\t{1, $dst|$dst, 1}", []>;
1754 let Uses = [CL] in {
1755 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
1756 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
1758 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
1759 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
1761 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
1762 "rcr{b}\t{1, $dst|$dst, 1}", []>;
1763 let Uses = [CL] in {
1764 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
1765 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
1767 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
1768 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
1770 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
1771 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
1772 let Uses = [CL] in {
1773 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
1774 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
1776 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
1777 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
1779 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
1780 "rcr{l}\t{1, $dst|$dst, 1}", []>;
1781 let Uses = [CL] in {
1782 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
1783 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
1785 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
1786 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
1788 let Constraints = "" in {
1789 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
1790 "rcl{b}\t{1, $dst|$dst, 1}", []>;
1791 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
1792 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
1793 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
1794 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
1795 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
1796 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
1797 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
1798 "rcl{l}\t{1, $dst|$dst, 1}", []>;
1799 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
1800 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
1801 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
1802 "rcr{b}\t{1, $dst|$dst, 1}", []>;
1803 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
1804 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
1805 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
1806 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
1807 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
1808 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
1809 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
1810 "rcr{l}\t{1, $dst|$dst, 1}", []>;
1811 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
1812 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
1814 let Uses = [CL] in {
1815 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
1816 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
1817 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
1818 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
1819 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
1820 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
1821 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
1822 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
1823 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
1824 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
1825 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
1826 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
1828 } // Constraints = ""
1830 // FIXME: provide shorter instructions when imm8 == 1
1831 let Uses = [CL] in {
1832 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1833 "rol{b}\t{%cl, $dst|$dst, CL}",
1834 [(set GR8:$dst, (rotl GR8:$src1, CL))]>;
1835 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
1836 "rol{w}\t{%cl, $dst|$dst, CL}",
1837 [(set GR16:$dst, (rotl GR16:$src1, CL))]>, OpSize;
1838 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1839 "rol{l}\t{%cl, $dst|$dst, CL}",
1840 [(set GR32:$dst, (rotl GR32:$src1, CL))]>;
1843 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1844 "rol{b}\t{$src2, $dst|$dst, $src2}",
1845 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1846 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1847 "rol{w}\t{$src2, $dst|$dst, $src2}",
1848 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
1850 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1851 "rol{l}\t{$src2, $dst|$dst, $src2}",
1852 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1855 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1857 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1858 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
1860 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1861 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1863 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1865 let Constraints = "" in {
1866 let Uses = [CL] in {
1867 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
1868 "rol{b}\t{%cl, $dst|$dst, CL}",
1869 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
1870 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
1871 "rol{w}\t{%cl, $dst|$dst, CL}",
1872 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1873 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
1874 "rol{l}\t{%cl, $dst|$dst, CL}",
1875 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
1877 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
1878 "rol{b}\t{$src, $dst|$dst, $src}",
1879 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1880 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
1881 "rol{w}\t{$src, $dst|$dst, $src}",
1882 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1884 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
1885 "rol{l}\t{$src, $dst|$dst, $src}",
1886 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1889 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
1891 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1892 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
1894 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1896 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
1898 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1899 } // Constraints = ""
1901 let Uses = [CL] in {
1902 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1903 "ror{b}\t{%cl, $dst|$dst, CL}",
1904 [(set GR8:$dst, (rotr GR8:$src1, CL))]>;
1905 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
1906 "ror{w}\t{%cl, $dst|$dst, CL}",
1907 [(set GR16:$dst, (rotr GR16:$src1, CL))]>, OpSize;
1908 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
1909 "ror{l}\t{%cl, $dst|$dst, CL}",
1910 [(set GR32:$dst, (rotr GR32:$src1, CL))]>;
1913 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1914 "ror{b}\t{$src2, $dst|$dst, $src2}",
1915 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
1916 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1917 "ror{w}\t{$src2, $dst|$dst, $src2}",
1918 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
1920 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1921 "ror{l}\t{$src2, $dst|$dst, $src2}",
1922 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
1925 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1927 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
1928 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
1930 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
1931 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
1933 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
1935 let Constraints = "" in {
1936 let Uses = [CL] in {
1937 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
1938 "ror{b}\t{%cl, $dst|$dst, CL}",
1939 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
1940 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
1941 "ror{w}\t{%cl, $dst|$dst, CL}",
1942 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1943 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
1944 "ror{l}\t{%cl, $dst|$dst, CL}",
1945 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
1947 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1948 "ror{b}\t{$src, $dst|$dst, $src}",
1949 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1950 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
1951 "ror{w}\t{$src, $dst|$dst, $src}",
1952 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1954 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
1955 "ror{l}\t{$src, $dst|$dst, $src}",
1956 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1959 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
1961 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1962 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
1964 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1966 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
1968 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1969 } // Constraints = ""
1972 // Double shift instructions (generalizations of rotate)
1973 let Uses = [CL] in {
1974 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
1975 (ins GR32:$src1, GR32:$src2),
1976 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
1977 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
1978 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
1979 (ins GR32:$src1, GR32:$src2),
1980 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
1981 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
1982 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
1983 (ins GR16:$src1, GR16:$src2),
1984 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
1985 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
1987 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
1988 (ins GR16:$src1, GR16:$src2),
1989 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
1990 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
1994 let isCommutable = 1 in { // These instructions commute to each other.
1995 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
1997 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1998 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1999 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2002 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2004 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2005 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2006 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2009 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2011 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2012 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2013 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2016 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2018 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2019 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2020 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2025 let Constraints = "" in {
2026 let Uses = [CL] in {
2027 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2028 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2029 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2031 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2032 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2033 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2036 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2037 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2038 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2039 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2040 (i8 imm:$src3)), addr:$dst)]>,
2042 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2043 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2044 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2045 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2046 (i8 imm:$src3)), addr:$dst)]>,
2049 let Uses = [CL] in {
2050 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2051 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2052 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2053 addr:$dst)]>, TB, OpSize;
2054 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2055 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2056 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2057 addr:$dst)]>, TB, OpSize;
2059 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2060 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2061 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2062 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2063 (i8 imm:$src3)), addr:$dst)]>,
2065 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2066 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2067 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2068 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2069 (i8 imm:$src3)), addr:$dst)]>,
2071 } // Constraints = ""
2072 } // Defs = [EFLAGS]
2076 let Defs = [EFLAGS] in {
2077 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2078 // Register-Register Addition
2079 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2080 (ins GR8 :$src1, GR8 :$src2),
2081 "add{b}\t{$src2, $dst|$dst, $src2}",
2082 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
2084 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2085 // Register-Register Addition
2086 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2087 (ins GR16:$src1, GR16:$src2),
2088 "add{w}\t{$src2, $dst|$dst, $src2}",
2089 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2090 GR16:$src2))]>, OpSize;
2091 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2092 (ins GR32:$src1, GR32:$src2),
2093 "add{l}\t{$src2, $dst|$dst, $src2}",
2094 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2096 } // end isConvertibleToThreeAddress
2097 } // end isCommutable
2099 // These are alternate spellings for use by the disassembler, we mark them as
2100 // code gen only to ensure they aren't matched by the assembler.
2101 let isCodeGenOnly = 1 in {
2102 def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2103 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2104 def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2105 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2106 def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR32:$dst),(ins GR32:$src1, GR32:$src2),
2107 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2110 // Register-Memory Addition
2111 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2112 (ins GR8 :$src1, i8mem :$src2),
2113 "add{b}\t{$src2, $dst|$dst, $src2}",
2114 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
2115 (load addr:$src2)))]>;
2116 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2117 (ins GR16:$src1, i16mem:$src2),
2118 "add{w}\t{$src2, $dst|$dst, $src2}",
2119 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2120 (load addr:$src2)))]>, OpSize;
2121 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2122 (ins GR32:$src1, i32mem:$src2),
2123 "add{l}\t{$src2, $dst|$dst, $src2}",
2124 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2125 (load addr:$src2)))]>;
2127 // Register-Integer Addition
2128 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2129 "add{b}\t{$src2, $dst|$dst, $src2}",
2130 [(set GR8:$dst, EFLAGS,
2131 (X86add_flag GR8:$src1, imm:$src2))]>;
2133 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2134 // Register-Integer Addition
2135 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2136 (ins GR16:$src1, i16imm:$src2),
2137 "add{w}\t{$src2, $dst|$dst, $src2}",
2138 [(set GR16:$dst, EFLAGS,
2139 (X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
2140 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2141 (ins GR32:$src1, i32imm:$src2),
2142 "add{l}\t{$src2, $dst|$dst, $src2}",
2143 [(set GR32:$dst, EFLAGS,
2144 (X86add_flag GR32:$src1, imm:$src2))]>;
2145 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2146 (ins GR16:$src1, i16i8imm:$src2),
2147 "add{w}\t{$src2, $dst|$dst, $src2}",
2148 [(set GR16:$dst, EFLAGS,
2149 (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2150 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2151 (ins GR32:$src1, i32i8imm:$src2),
2152 "add{l}\t{$src2, $dst|$dst, $src2}",
2153 [(set GR32:$dst, EFLAGS,
2154 (X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
2157 let Constraints = "" in {
2158 // Memory-Register Addition
2159 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2160 "add{b}\t{$src2, $dst|$dst, $src2}",
2161 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2162 (implicit EFLAGS)]>;
2163 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2164 "add{w}\t{$src2, $dst|$dst, $src2}",
2165 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2166 (implicit EFLAGS)]>, OpSize;
2167 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2168 "add{l}\t{$src2, $dst|$dst, $src2}",
2169 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2170 (implicit EFLAGS)]>;
2171 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2172 "add{b}\t{$src2, $dst|$dst, $src2}",
2173 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2174 (implicit EFLAGS)]>;
2175 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2176 "add{w}\t{$src2, $dst|$dst, $src2}",
2177 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2178 (implicit EFLAGS)]>, OpSize;
2179 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2180 "add{l}\t{$src2, $dst|$dst, $src2}",
2181 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2182 (implicit EFLAGS)]>;
2183 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2184 "add{w}\t{$src2, $dst|$dst, $src2}",
2185 [(store (add (load addr:$dst), i16immSExt8:$src2),
2187 (implicit EFLAGS)]>, OpSize;
2188 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2189 "add{l}\t{$src2, $dst|$dst, $src2}",
2190 [(store (add (load addr:$dst), i32immSExt8:$src2),
2192 (implicit EFLAGS)]>;
2195 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2196 "add{b}\t{$src, %al|%al, $src}", []>;
2197 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2198 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2199 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2200 "add{l}\t{$src, %eax|%eax, $src}", []>;
2201 } // Constraints = ""
2203 let Uses = [EFLAGS] in {
2204 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2205 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2206 "adc{b}\t{$src2, $dst|$dst, $src2}",
2207 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2208 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2209 (ins GR16:$src1, GR16:$src2),
2210 "adc{w}\t{$src2, $dst|$dst, $src2}",
2211 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2212 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2213 (ins GR32:$src1, GR32:$src2),
2214 "adc{l}\t{$src2, $dst|$dst, $src2}",
2215 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2218 let isCodeGenOnly = 1 in {
2219 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2220 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2221 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2222 (ins GR16:$src1, GR16:$src2),
2223 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2224 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2225 (ins GR32:$src1, GR32:$src2),
2226 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2229 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2230 (ins GR8:$src1, i8mem:$src2),
2231 "adc{b}\t{$src2, $dst|$dst, $src2}",
2232 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2233 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2234 (ins GR16:$src1, i16mem:$src2),
2235 "adc{w}\t{$src2, $dst|$dst, $src2}",
2236 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2238 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2239 (ins GR32:$src1, i32mem:$src2),
2240 "adc{l}\t{$src2, $dst|$dst, $src2}",
2241 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2242 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2243 "adc{b}\t{$src2, $dst|$dst, $src2}",
2244 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2245 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2246 (ins GR16:$src1, i16imm:$src2),
2247 "adc{w}\t{$src2, $dst|$dst, $src2}",
2248 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2249 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2250 (ins GR16:$src1, i16i8imm:$src2),
2251 "adc{w}\t{$src2, $dst|$dst, $src2}",
2252 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2254 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2255 (ins GR32:$src1, i32imm:$src2),
2256 "adc{l}\t{$src2, $dst|$dst, $src2}",
2257 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2258 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2259 (ins GR32:$src1, i32i8imm:$src2),
2260 "adc{l}\t{$src2, $dst|$dst, $src2}",
2261 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2263 let Constraints = "" in {
2264 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2265 "adc{b}\t{$src2, $dst|$dst, $src2}",
2266 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2267 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2268 "adc{w}\t{$src2, $dst|$dst, $src2}",
2269 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2271 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2272 "adc{l}\t{$src2, $dst|$dst, $src2}",
2273 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2274 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2275 "adc{b}\t{$src2, $dst|$dst, $src2}",
2276 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2277 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2278 "adc{w}\t{$src2, $dst|$dst, $src2}",
2279 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2281 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2282 "adc{w}\t{$src2, $dst|$dst, $src2}",
2283 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2285 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2286 "adc{l}\t{$src2, $dst|$dst, $src2}",
2287 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2288 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2289 "adc{l}\t{$src2, $dst|$dst, $src2}",
2290 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2292 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2293 "adc{b}\t{$src, %al|%al, $src}", []>;
2294 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2295 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2296 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2297 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2298 } // Constraints = ""
2299 } // Uses = [EFLAGS]
2301 // Register-Register Subtraction
2302 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2303 "sub{b}\t{$src2, $dst|$dst, $src2}",
2304 [(set GR8:$dst, EFLAGS,
2305 (X86sub_flag GR8:$src1, GR8:$src2))]>;
2306 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2307 "sub{w}\t{$src2, $dst|$dst, $src2}",
2308 [(set GR16:$dst, EFLAGS,
2309 (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
2310 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2311 "sub{l}\t{$src2, $dst|$dst, $src2}",
2312 [(set GR32:$dst, EFLAGS,
2313 (X86sub_flag GR32:$src1, GR32:$src2))]>;
2315 let isCodeGenOnly = 1 in {
2316 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2317 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
2318 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
2319 (ins GR16:$src1, GR16:$src2),
2320 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2321 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
2322 (ins GR32:$src1, GR32:$src2),
2323 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
2326 // Register-Memory Subtraction
2327 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2328 (ins GR8 :$src1, i8mem :$src2),
2329 "sub{b}\t{$src2, $dst|$dst, $src2}",
2330 [(set GR8:$dst, EFLAGS,
2331 (X86sub_flag GR8:$src1, (load addr:$src2)))]>;
2332 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2333 (ins GR16:$src1, i16mem:$src2),
2334 "sub{w}\t{$src2, $dst|$dst, $src2}",
2335 [(set GR16:$dst, EFLAGS,
2336 (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
2337 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2338 (ins GR32:$src1, i32mem:$src2),
2339 "sub{l}\t{$src2, $dst|$dst, $src2}",
2340 [(set GR32:$dst, EFLAGS,
2341 (X86sub_flag GR32:$src1, (load addr:$src2)))]>;
2343 // Register-Integer Subtraction
2344 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2345 (ins GR8:$src1, i8imm:$src2),
2346 "sub{b}\t{$src2, $dst|$dst, $src2}",
2347 [(set GR8:$dst, EFLAGS,
2348 (X86sub_flag GR8:$src1, imm:$src2))]>;
2349 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2350 (ins GR16:$src1, i16imm:$src2),
2351 "sub{w}\t{$src2, $dst|$dst, $src2}",
2352 [(set GR16:$dst, EFLAGS,
2353 (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
2354 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2355 (ins GR32:$src1, i32imm:$src2),
2356 "sub{l}\t{$src2, $dst|$dst, $src2}",
2357 [(set GR32:$dst, EFLAGS,
2358 (X86sub_flag GR32:$src1, imm:$src2))]>;
2359 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2360 (ins GR16:$src1, i16i8imm:$src2),
2361 "sub{w}\t{$src2, $dst|$dst, $src2}",
2362 [(set GR16:$dst, EFLAGS,
2363 (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2364 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2365 (ins GR32:$src1, i32i8imm:$src2),
2366 "sub{l}\t{$src2, $dst|$dst, $src2}",
2367 [(set GR32:$dst, EFLAGS,
2368 (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
2370 let Constraints = "" in {
2371 // Memory-Register Subtraction
2372 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2373 "sub{b}\t{$src2, $dst|$dst, $src2}",
2374 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2375 (implicit EFLAGS)]>;
2376 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2377 "sub{w}\t{$src2, $dst|$dst, $src2}",
2378 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2379 (implicit EFLAGS)]>, OpSize;
2380 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2381 "sub{l}\t{$src2, $dst|$dst, $src2}",
2382 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2383 (implicit EFLAGS)]>;
2385 // Memory-Integer Subtraction
2386 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2387 "sub{b}\t{$src2, $dst|$dst, $src2}",
2388 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2389 (implicit EFLAGS)]>;
2390 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2391 "sub{w}\t{$src2, $dst|$dst, $src2}",
2392 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2393 (implicit EFLAGS)]>, OpSize;
2394 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2395 "sub{l}\t{$src2, $dst|$dst, $src2}",
2396 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2397 (implicit EFLAGS)]>;
2398 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2399 "sub{w}\t{$src2, $dst|$dst, $src2}",
2400 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2402 (implicit EFLAGS)]>, OpSize;
2403 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2404 "sub{l}\t{$src2, $dst|$dst, $src2}",
2405 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2407 (implicit EFLAGS)]>;
2409 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
2410 "sub{b}\t{$src, %al|%al, $src}", []>;
2411 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
2412 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2413 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
2414 "sub{l}\t{$src, %eax|%eax, $src}", []>;
2415 } // Constraints = ""
2417 let Uses = [EFLAGS] in {
2418 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
2419 (ins GR8:$src1, GR8:$src2),
2420 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2421 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
2422 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
2423 (ins GR16:$src1, GR16:$src2),
2424 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2425 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
2426 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
2427 (ins GR32:$src1, GR32:$src2),
2428 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2429 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2431 let Constraints = "" in {
2432 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2433 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2434 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
2435 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2436 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2437 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
2439 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2440 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2441 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2442 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2443 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2444 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2445 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
2446 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2447 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2449 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2450 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2451 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2453 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2454 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2455 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2456 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2457 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2458 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2460 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
2461 "sbb{b}\t{$src, %al|%al, $src}", []>;
2462 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
2463 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2464 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
2465 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
2466 } // Constraints = ""
2468 let isCodeGenOnly = 1 in {
2469 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2470 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
2471 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
2472 (ins GR16:$src1, GR16:$src2),
2473 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2474 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
2475 (ins GR32:$src1, GR32:$src2),
2476 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
2479 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
2480 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2481 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
2482 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
2483 (ins GR16:$src1, i16mem:$src2),
2484 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2485 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
2487 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
2488 (ins GR32:$src1, i32mem:$src2),
2489 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2490 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2491 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2492 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2493 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
2494 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
2495 (ins GR16:$src1, i16imm:$src2),
2496 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2497 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
2498 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
2499 (ins GR16:$src1, i16i8imm:$src2),
2500 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2501 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
2503 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
2504 (ins GR32:$src1, i32imm:$src2),
2505 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2506 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2507 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
2508 (ins GR32:$src1, i32i8imm:$src2),
2509 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2510 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2511 } // Uses = [EFLAGS]
2512 } // Defs = [EFLAGS]
2514 let Defs = [EFLAGS] in {
2515 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2516 // Register-Register Signed Integer Multiply
2517 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2518 "imul{w}\t{$src2, $dst|$dst, $src2}",
2519 [(set GR16:$dst, EFLAGS,
2520 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
2521 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2522 "imul{l}\t{$src2, $dst|$dst, $src2}",
2523 [(set GR32:$dst, EFLAGS,
2524 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
2527 // Register-Memory Signed Integer Multiply
2528 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
2529 (ins GR16:$src1, i16mem:$src2),
2530 "imul{w}\t{$src2, $dst|$dst, $src2}",
2531 [(set GR16:$dst, EFLAGS,
2532 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
2534 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
2535 (ins GR32:$src1, i32mem:$src2),
2536 "imul{l}\t{$src2, $dst|$dst, $src2}",
2537 [(set GR32:$dst, EFLAGS,
2538 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
2539 } // Defs = [EFLAGS]
2540 } // end Two Address instructions
2542 // Suprisingly enough, these are not two address instructions!
2543 let Defs = [EFLAGS] in {
2544 // Register-Integer Signed Integer Multiply
2545 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2546 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2547 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2548 [(set GR16:$dst, EFLAGS,
2549 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
2550 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2551 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2552 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2553 [(set GR32:$dst, EFLAGS,
2554 (X86smul_flag GR32:$src1, imm:$src2))]>;
2555 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2556 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2557 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2558 [(set GR16:$dst, EFLAGS,
2559 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
2561 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2562 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2563 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2564 [(set GR32:$dst, EFLAGS,
2565 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
2567 // Memory-Integer Signed Integer Multiply
2568 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2569 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2570 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2571 [(set GR16:$dst, EFLAGS,
2572 (X86smul_flag (load addr:$src1), imm:$src2))]>,
2574 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2575 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2576 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2577 [(set GR32:$dst, EFLAGS,
2578 (X86smul_flag (load addr:$src1), imm:$src2))]>;
2579 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2580 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2581 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2582 [(set GR16:$dst, EFLAGS,
2583 (X86smul_flag (load addr:$src1),
2584 i16immSExt8:$src2))]>, OpSize;
2585 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2586 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2587 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2588 [(set GR32:$dst, EFLAGS,
2589 (X86smul_flag (load addr:$src1),
2590 i32immSExt8:$src2))]>;
2591 } // Defs = [EFLAGS]
2593 //===----------------------------------------------------------------------===//
2594 // Test instructions are just like AND, except they don't generate a result.
2596 let Defs = [EFLAGS] in {
2597 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2598 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
2599 "test{b}\t{$src2, $src1|$src1, $src2}",
2600 [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
2601 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
2602 "test{w}\t{$src2, $src1|$src1, $src2}",
2603 [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
2606 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
2607 "test{l}\t{$src2, $src1|$src1, $src2}",
2608 [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
2612 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
2613 "test{b}\t{$src, %al|%al, $src}", []>;
2614 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
2615 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2616 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
2617 "test{l}\t{$src, %eax|%eax, $src}", []>;
2619 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2620 "test{b}\t{$src2, $src1|$src1, $src2}",
2621 [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
2623 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2624 "test{w}\t{$src2, $src1|$src1, $src2}",
2625 [(set EFLAGS, (X86cmp (and GR16:$src1,
2626 (loadi16 addr:$src2)), 0))]>, OpSize;
2627 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2628 "test{l}\t{$src2, $src1|$src1, $src2}",
2629 [(set EFLAGS, (X86cmp (and GR32:$src1,
2630 (loadi32 addr:$src2)), 0))]>;
2632 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2633 (outs), (ins GR8:$src1, i8imm:$src2),
2634 "test{b}\t{$src2, $src1|$src1, $src2}",
2635 [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
2636 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2637 (outs), (ins GR16:$src1, i16imm:$src2),
2638 "test{w}\t{$src2, $src1|$src1, $src2}",
2639 [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
2641 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2642 (outs), (ins GR32:$src1, i32imm:$src2),
2643 "test{l}\t{$src2, $src1|$src1, $src2}",
2644 [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
2646 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2647 (outs), (ins i8mem:$src1, i8imm:$src2),
2648 "test{b}\t{$src2, $src1|$src1, $src2}",
2649 [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
2651 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2652 (outs), (ins i16mem:$src1, i16imm:$src2),
2653 "test{w}\t{$src2, $src1|$src1, $src2}",
2654 [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
2656 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2657 (outs), (ins i32mem:$src1, i32imm:$src2),
2658 "test{l}\t{$src2, $src1|$src1, $src2}",
2659 [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
2661 } // Defs = [EFLAGS]
2664 // Condition code ops, incl. set if equal/not equal/...
2665 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2666 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2667 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2668 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2670 // Integer comparisons
2671 let Defs = [EFLAGS] in {
2672 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
2673 "cmp{b}\t{$src, %al|%al, $src}", []>;
2674 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
2675 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2676 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
2677 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
2679 def CMP8rr : I<0x38, MRMDestReg,
2680 (outs), (ins GR8 :$src1, GR8 :$src2),
2681 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2682 [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
2683 def CMP16rr : I<0x39, MRMDestReg,
2684 (outs), (ins GR16:$src1, GR16:$src2),
2685 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2686 [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
2687 def CMP32rr : I<0x39, MRMDestReg,
2688 (outs), (ins GR32:$src1, GR32:$src2),
2689 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2690 [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
2691 def CMP8mr : I<0x38, MRMDestMem,
2692 (outs), (ins i8mem :$src1, GR8 :$src2),
2693 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2694 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
2695 def CMP16mr : I<0x39, MRMDestMem,
2696 (outs), (ins i16mem:$src1, GR16:$src2),
2697 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2698 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
2700 def CMP32mr : I<0x39, MRMDestMem,
2701 (outs), (ins i32mem:$src1, GR32:$src2),
2702 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2703 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
2704 def CMP8rm : I<0x3A, MRMSrcMem,
2705 (outs), (ins GR8 :$src1, i8mem :$src2),
2706 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2707 [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
2708 def CMP16rm : I<0x3B, MRMSrcMem,
2709 (outs), (ins GR16:$src1, i16mem:$src2),
2710 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2711 [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
2713 def CMP32rm : I<0x3B, MRMSrcMem,
2714 (outs), (ins GR32:$src1, i32mem:$src2),
2715 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2716 [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
2718 // These are alternate spellings for use by the disassembler, we mark them as
2719 // code gen only to ensure they aren't matched by the assembler.
2720 let isCodeGenOnly = 1 in {
2721 def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
2722 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
2723 def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
2724 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
2725 def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
2726 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
2729 def CMP8ri : Ii8<0x80, MRM7r,
2730 (outs), (ins GR8:$src1, i8imm:$src2),
2731 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2732 [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
2733 def CMP16ri : Ii16<0x81, MRM7r,
2734 (outs), (ins GR16:$src1, i16imm:$src2),
2735 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2736 [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
2737 def CMP32ri : Ii32<0x81, MRM7r,
2738 (outs), (ins GR32:$src1, i32imm:$src2),
2739 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2740 [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
2741 def CMP8mi : Ii8 <0x80, MRM7m,
2742 (outs), (ins i8mem :$src1, i8imm :$src2),
2743 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2744 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
2745 def CMP16mi : Ii16<0x81, MRM7m,
2746 (outs), (ins i16mem:$src1, i16imm:$src2),
2747 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2748 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
2750 def CMP32mi : Ii32<0x81, MRM7m,
2751 (outs), (ins i32mem:$src1, i32imm:$src2),
2752 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2753 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
2754 def CMP16ri8 : Ii8<0x83, MRM7r,
2755 (outs), (ins GR16:$src1, i16i8imm:$src2),
2756 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2757 [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
2759 def CMP16mi8 : Ii8<0x83, MRM7m,
2760 (outs), (ins i16mem:$src1, i16i8imm:$src2),
2761 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2762 [(set EFLAGS, (X86cmp (loadi16 addr:$src1),
2763 i16immSExt8:$src2))]>, OpSize;
2764 def CMP32mi8 : Ii8<0x83, MRM7m,
2765 (outs), (ins i32mem:$src1, i32i8imm:$src2),
2766 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2767 [(set EFLAGS, (X86cmp (loadi32 addr:$src1),
2768 i32immSExt8:$src2))]>;
2769 def CMP32ri8 : Ii8<0x83, MRM7r,
2770 (outs), (ins GR32:$src1, i32i8imm:$src2),
2771 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2772 [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
2773 } // Defs = [EFLAGS]
2776 // TODO: BTC, BTR, and BTS
2777 let Defs = [EFLAGS] in {
2778 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2779 "bt{w}\t{$src2, $src1|$src1, $src2}",
2780 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
2781 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2782 "bt{l}\t{$src2, $src1|$src1, $src2}",
2783 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
2785 // Unlike with the register+register form, the memory+register form of the
2786 // bt instruction does not ignore the high bits of the index. From ISel's
2787 // perspective, this is pretty bizarre. Make these instructions disassembly
2790 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
2791 "bt{w}\t{$src2, $src1|$src1, $src2}",
2792 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
2793 // (implicit EFLAGS)]
2795 >, OpSize, TB, Requires<[FastBTMem]>;
2796 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
2797 "bt{l}\t{$src2, $src1|$src1, $src2}",
2798 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
2799 // (implicit EFLAGS)]
2801 >, TB, Requires<[FastBTMem]>;
2803 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
2804 "bt{w}\t{$src2, $src1|$src1, $src2}",
2805 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
2807 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
2808 "bt{l}\t{$src2, $src1|$src1, $src2}",
2809 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
2810 // Note that these instructions don't need FastBTMem because that
2811 // only applies when the other operand is in a register. When it's
2812 // an immediate, bt is still fast.
2813 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
2814 "bt{w}\t{$src2, $src1|$src1, $src2}",
2815 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
2817 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
2818 "bt{l}\t{$src2, $src1|$src1, $src2}",
2819 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
2822 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2823 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
2824 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2825 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
2826 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
2827 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
2828 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
2829 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
2830 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
2831 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
2832 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
2833 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
2834 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
2835 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
2836 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
2837 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
2839 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2840 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
2841 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2842 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
2843 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
2844 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
2845 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
2846 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
2847 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
2848 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
2849 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
2850 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
2851 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
2852 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
2853 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
2854 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
2856 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2857 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
2858 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2859 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
2860 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
2861 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
2862 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
2863 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
2864 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
2865 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
2866 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
2867 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
2868 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
2869 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
2870 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
2871 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
2872 } // Defs = [EFLAGS]
2875 //===----------------------------------------------------------------------===//
2880 // Atomic swap. These are just normal xchg instructions. But since a memory
2881 // operand is referenced, the atomicity is ensured.
2882 let Constraints = "$val = $dst" in {
2883 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
2884 "xchg{b}\t{$val, $ptr|$ptr, $val}",
2885 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
2886 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
2887 (ins GR16:$val, i16mem:$ptr),
2888 "xchg{w}\t{$val, $ptr|$ptr, $val}",
2889 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
2891 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
2892 (ins GR32:$val, i32mem:$ptr),
2893 "xchg{l}\t{$val, $ptr|$ptr, $val}",
2894 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
2895 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),
2896 (ins GR64:$val,i64mem:$ptr),
2897 "xchg{q}\t{$val, $ptr|$ptr, $val}",
2898 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
2900 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
2901 "xchg{b}\t{$val, $src|$src, $val}", []>;
2902 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
2903 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
2904 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
2905 "xchg{l}\t{$val, $src|$src, $val}", []>;
2906 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
2907 "xchg{q}\t{$val, $src|$src, $val}", []>;
2910 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
2911 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2912 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
2913 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
2914 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
2915 "xchg{q}\t{$src, %rax|%rax, $src}", []>;
2919 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
2920 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
2921 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
2922 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
2923 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
2924 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
2925 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
2926 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
2928 let mayLoad = 1, mayStore = 1 in {
2929 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
2930 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
2931 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
2932 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
2933 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2934 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
2935 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2936 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
2940 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
2941 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
2942 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
2943 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
2944 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
2945 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
2946 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
2947 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
2949 let mayLoad = 1, mayStore = 1 in {
2950 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
2951 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
2952 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
2953 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
2954 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2955 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
2956 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2957 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
2960 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
2961 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
2962 "cmpxchg8b\t$dst", []>, TB;
2964 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
2965 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
2966 "cmpxchg16b\t$dst", []>, TB;
2970 // Lock instruction prefix
2971 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
2973 // Repeat string operation instruction prefixes
2974 // These uses the DF flag in the EFLAGS register to inc or dec ECX
2975 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
2976 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
2977 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
2978 // Repeat while not equal (used with CMPS and SCAS)
2979 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
2983 // String manipulation instructions
2985 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
2986 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
2987 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
2988 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
2990 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
2991 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
2992 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
2995 // Flag instructions
2996 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
2997 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
2998 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
2999 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
3000 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
3001 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
3002 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
3004 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
3006 // Table lookup instructions
3007 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
3011 //===----------------------------------------------------------------------===//
3013 //===----------------------------------------------------------------------===//
3015 // Floating Point Stack Support
3016 include "X86InstrFPStack.td"
3017 include "X86Instr64bit.td"
3019 include "X86InstrCMovSetCC.td"
3020 include "X86InstrExtension.td"
3021 include "X86InstrControl.td"
3023 // SIMD support (SSE, MMX and AVX)
3024 include "X86InstrFragmentsSIMD.td"
3026 // FMA - Fused Multiply-Add support (requires FMA)
3027 include "X86InstrFMA.td"
3029 // SSE, MMX and 3DNow! vector support.
3030 include "X86InstrSSE.td"
3031 include "X86InstrMMX.td"
3032 include "X86Instr3DNow.td"
3034 include "X86InstrVMX.td"
3036 // System instructions.
3037 include "X86InstrSystem.td"
3039 // Compiler Pseudo Instructions and Pat Patterns
3040 include "X86InstrCompiler.td"