1 //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
29 def SDTX86Cmov_NEW : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 def SDTX86BrCond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>;
35 def SDTX86BrCond_NEW : SDTypeProfile<0, 3,
36 [SDTCisVT<0, OtherVT>,
37 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
39 def SDTX86SetCC : SDTypeProfile<1, 1,
40 [SDTCisVT<0, i8>, SDTCisVT<1, i8>]>;
41 def SDTX86SetCC_NEW : SDTypeProfile<1, 2,
43 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86Ret : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>;
47 def SDT_X86CallSeqStart : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
48 def SDT_X86CallSeqEnd : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>,
51 def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
53 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
55 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
57 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
59 def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
63 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
66 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
68 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest,
69 [SDNPHasChain, SDNPOutFlag]>;
70 def X86cmp_new : SDNode<"X86ISD::CMP_NEW" , SDTX86CmpTest>;
72 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov,
73 [SDNPInFlag, SDNPOutFlag]>;
74 def X86cmov_new: SDNode<"X86ISD::CMOV_NEW", SDTX86Cmov_NEW>;
75 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
76 [SDNPHasChain, SDNPInFlag]>;
77 def X86brcond_new : SDNode<"X86ISD::BRCOND_NEW", SDTX86BrCond_NEW,
79 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC,
80 [SDNPInFlag, SDNPOutFlag]>;
81 def X86setcc_new : SDNode<"X86ISD::SETCC_NEW", SDTX86SetCC_NEW>;
83 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
84 [SDNPHasChain, SDNPOptInFlag]>;
86 def X86callseq_start :
87 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
88 [SDNPHasChain, SDNPOutFlag]>;
90 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
91 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
93 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
94 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
96 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
97 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
99 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
100 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
101 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
102 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
104 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
105 [SDNPHasChain, SDNPOutFlag]>;
107 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
108 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
110 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
111 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
112 def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
114 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
118 //===----------------------------------------------------------------------===//
119 // X86 Operand Definitions.
122 // *mem - Operand definitions for the funky X86 addressing mode operands.
124 class X86MemOperand<string printMethod> : Operand<iPTR> {
125 let PrintMethod = printMethod;
126 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
129 def i8mem : X86MemOperand<"printi8mem">;
130 def i16mem : X86MemOperand<"printi16mem">;
131 def i32mem : X86MemOperand<"printi32mem">;
132 def i64mem : X86MemOperand<"printi64mem">;
133 def i128mem : X86MemOperand<"printi128mem">;
134 def f32mem : X86MemOperand<"printf32mem">;
135 def f64mem : X86MemOperand<"printf64mem">;
136 def f80mem : X86MemOperand<"printf80mem">;
137 def f128mem : X86MemOperand<"printf128mem">;
139 def lea32mem : Operand<i32> {
140 let PrintMethod = "printi32mem";
141 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
144 def SSECC : Operand<i8> {
145 let PrintMethod = "printSSECC";
148 def piclabel: Operand<i32> {
149 let PrintMethod = "printPICLabel";
152 // A couple of more descriptive operand definitions.
153 // 16-bits but only 8 bits are significant.
154 def i16i8imm : Operand<i16>;
155 // 32-bits but only 8 bits are significant.
156 def i32i8imm : Operand<i32>;
158 // Branch targets have OtherVT type.
159 def brtarget : Operand<OtherVT>;
161 //===----------------------------------------------------------------------===//
162 // X86 Complex Pattern Definitions.
165 // Define X86 specific addressing mode.
166 def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
167 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
168 [add, mul, shl, or, frameindex], []>;
170 //===----------------------------------------------------------------------===//
171 // X86 Instruction Predicate Definitions.
172 def HasMMX : Predicate<"Subtarget->hasMMX()">;
173 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
174 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
175 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
176 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
177 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
178 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
179 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
180 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
181 def HasLow4G : Predicate<"Subtarget->hasLow4GUserSpaceAddress()">;
182 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
183 def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
184 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
186 //===----------------------------------------------------------------------===//
187 // X86 Instruction Format Definitions.
190 include "X86InstrFormats.td"
192 //===----------------------------------------------------------------------===//
193 // Pattern fragments...
196 // X86 specific condition code. These correspond to CondCode in
197 // X86InstrInfo.h. They must be kept in synch.
198 def X86_COND_A : PatLeaf<(i8 0)>;
199 def X86_COND_AE : PatLeaf<(i8 1)>;
200 def X86_COND_B : PatLeaf<(i8 2)>;
201 def X86_COND_BE : PatLeaf<(i8 3)>;
202 def X86_COND_E : PatLeaf<(i8 4)>;
203 def X86_COND_G : PatLeaf<(i8 5)>;
204 def X86_COND_GE : PatLeaf<(i8 6)>;
205 def X86_COND_L : PatLeaf<(i8 7)>;
206 def X86_COND_LE : PatLeaf<(i8 8)>;
207 def X86_COND_NE : PatLeaf<(i8 9)>;
208 def X86_COND_NO : PatLeaf<(i8 10)>;
209 def X86_COND_NP : PatLeaf<(i8 11)>;
210 def X86_COND_NS : PatLeaf<(i8 12)>;
211 def X86_COND_O : PatLeaf<(i8 13)>;
212 def X86_COND_P : PatLeaf<(i8 14)>;
213 def X86_COND_S : PatLeaf<(i8 15)>;
215 def i16immSExt8 : PatLeaf<(i16 imm), [{
216 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
217 // sign extended field.
218 return (int16_t)N->getValue() == (int8_t)N->getValue();
221 def i32immSExt8 : PatLeaf<(i32 imm), [{
222 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
223 // sign extended field.
224 return (int32_t)N->getValue() == (int8_t)N->getValue();
227 // Helper fragments for loads.
228 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
229 def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>;
230 def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>;
231 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
233 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
234 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
235 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
237 def sextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (sextloadi1 node:$ptr))>;
238 def sextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (sextloadi1 node:$ptr))>;
239 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
240 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
241 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
243 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
244 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
245 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
246 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
247 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
248 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
250 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
251 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
252 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
253 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
254 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
255 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
257 //===----------------------------------------------------------------------===//
258 // Instruction list...
261 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
262 // a stack adjustment and the codegen must know that they may modify the stack
263 // pointer before prolog-epilog rewriting occurs.
264 // Pessimisively assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become sub / add
265 // which can clobber EFLAGS.
266 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
267 def ADJCALLSTACKDOWN : I<0, Pseudo, (outs), (ins i32imm:$amt), "#ADJCALLSTACKDOWN",
268 [(X86callseq_start imm:$amt)]>;
269 def ADJCALLSTACKUP : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
271 [(X86callseq_end imm:$amt1, imm:$amt2)]>;
273 def IMPLICIT_USE : I<0, Pseudo, (outs), (ins variable_ops),
274 "#IMPLICIT_USE", []>;
275 def IMPLICIT_DEF : I<0, Pseudo, (outs variable_ops), (ins),
276 "#IMPLICIT_DEF", []>;
277 def IMPLICIT_DEF_GR8 : I<0, Pseudo, (outs GR8:$dst), (ins),
278 "#IMPLICIT_DEF $dst",
279 [(set GR8:$dst, (undef))]>;
280 def IMPLICIT_DEF_GR16 : I<0, Pseudo, (outs GR16:$dst), (ins),
281 "#IMPLICIT_DEF $dst",
282 [(set GR16:$dst, (undef))]>;
283 def IMPLICIT_DEF_GR32 : I<0, Pseudo, (outs GR32:$dst), (ins),
284 "#IMPLICIT_DEF $dst",
285 [(set GR32:$dst, (undef))]>;
288 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
291 //===----------------------------------------------------------------------===//
292 // Control Flow Instructions...
295 // Return instructions.
296 let isTerminator = 1, isReturn = 1, isBarrier = 1,
298 def RET : I<0xC3, RawFrm, (outs), (ins), "ret", [(X86retflag 0)]>;
299 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), "ret\t$amt",
300 [(X86retflag imm:$amt)]>;
303 // All branches are RawFrm, Void, Branch, and Terminators
304 let isBranch = 1, isTerminator = 1 in
305 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
306 I<opcode, RawFrm, (outs), ins, asm, pattern>;
309 let isBranch = 1, isBarrier = 1 in
310 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
312 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
313 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
314 [(brind GR32:$dst)]>;
315 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
316 [(brind (loadi32 addr:$dst))]>;
319 // Conditional branches
320 let Uses = [EFLAGS] in {
321 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
322 [(X86brcond bb:$dst, X86_COND_E)]>, TB;
323 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
324 [(X86brcond bb:$dst, X86_COND_NE)]>, TB;
325 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
326 [(X86brcond bb:$dst, X86_COND_L)]>, TB;
327 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
328 [(X86brcond bb:$dst, X86_COND_LE)]>, TB;
329 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
330 [(X86brcond bb:$dst, X86_COND_G)]>, TB;
331 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
332 [(X86brcond bb:$dst, X86_COND_GE)]>, TB;
334 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
335 [(X86brcond bb:$dst, X86_COND_B)]>, TB;
336 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
337 [(X86brcond bb:$dst, X86_COND_BE)]>, TB;
338 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
339 [(X86brcond bb:$dst, X86_COND_A)]>, TB;
340 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
341 [(X86brcond bb:$dst, X86_COND_AE)]>, TB;
343 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
344 [(X86brcond bb:$dst, X86_COND_S)]>, TB;
345 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
346 [(X86brcond bb:$dst, X86_COND_NS)]>, TB;
347 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
348 [(X86brcond bb:$dst, X86_COND_P)]>, TB;
349 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
350 [(X86brcond bb:$dst, X86_COND_NP)]>, TB;
351 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
352 [(X86brcond bb:$dst, X86_COND_O)]>, TB;
353 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
354 [(X86brcond bb:$dst, X86_COND_NO)]>, TB;
357 let Uses = [EFLAGS] in {
358 def NEW_JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
359 [(X86brcond_new bb:$dst, X86_COND_E, EFLAGS)]>, TB;
360 def NEW_JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
361 [(X86brcond_new bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
362 def NEW_JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
363 [(X86brcond_new bb:$dst, X86_COND_L, EFLAGS)]>, TB;
364 def NEW_JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
365 [(X86brcond_new bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
366 def NEW_JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
367 [(X86brcond_new bb:$dst, X86_COND_G, EFLAGS)]>, TB;
368 def NEW_JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
369 [(X86brcond_new bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
371 def NEW_JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
372 [(X86brcond_new bb:$dst, X86_COND_B, EFLAGS)]>, TB;
373 def NEW_JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
374 [(X86brcond_new bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
375 def NEW_JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
376 [(X86brcond_new bb:$dst, X86_COND_A, EFLAGS)]>, TB;
377 def NEW_JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
378 [(X86brcond_new bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
380 def NEW_JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
381 [(X86brcond_new bb:$dst, X86_COND_S, EFLAGS)]>, TB;
382 def NEW_JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
383 [(X86brcond_new bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
384 def NEW_JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
385 [(X86brcond_new bb:$dst, X86_COND_P, EFLAGS)]>, TB;
386 def NEW_JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
387 [(X86brcond_new bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
388 def NEW_JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
389 [(X86brcond_new bb:$dst, X86_COND_O, EFLAGS)]>, TB;
390 def NEW_JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
391 [(X86brcond_new bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
394 //===----------------------------------------------------------------------===//
395 // Call Instructions...
398 // All calls clobber the non-callee saved registers...
399 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
400 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
401 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, EFLAGS] in {
402 def CALLpcrel32 : I<0xE8, RawFrm, (outs), (ins i32imm:$dst, variable_ops),
403 "call\t${dst:call}", []>;
404 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
405 "call\t{*}$dst", [(X86call GR32:$dst)]>;
406 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
407 "call\t{*}$dst", []>;
411 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
412 def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAIL CALL",
414 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
415 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp\t{*}$dst # TAIL CALL",
417 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
418 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
419 "jmp\t{*}$dst # TAIL CALL", []>;
421 //===----------------------------------------------------------------------===//
422 // Miscellaneous Instructions...
424 let Defs = [EBP, ESP], Uses = [EBP, ESP] in
425 def LEAVE : I<0xC9, RawFrm,
426 (outs), (ins), "leave", []>;
428 let Defs = [ESP], Uses = [ESP] in {
429 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
431 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
434 let Defs = [ESP, EFLAGS], Uses = [ESP] in
435 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
436 let Defs = [ESP], Uses = [ESP, EFLAGS] in
437 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
439 def MovePCtoStack : I<0, Pseudo, (outs), (ins piclabel:$label),
442 let isTwoAddress = 1 in // GR32 = bswap GR32
443 def BSWAP32r : I<0xC8, AddRegFrm,
444 (outs GR32:$dst), (ins GR32:$src),
446 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
448 // FIXME: Model xchg* as two address instructions?
449 def XCHG8rr : I<0x86, MRMDestReg, // xchg GR8, GR8
450 (outs), (ins GR8:$src1, GR8:$src2),
451 "xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
452 def XCHG16rr : I<0x87, MRMDestReg, // xchg GR16, GR16
453 (outs), (ins GR16:$src1, GR16:$src2),
454 "xchg{w}\t{$src2|$src1}, {$src1|$src2}", []>, OpSize;
455 def XCHG32rr : I<0x87, MRMDestReg, // xchg GR32, GR32
456 (outs), (ins GR32:$src1, GR32:$src2),
457 "xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
459 def XCHG8mr : I<0x86, MRMDestMem,
460 (outs), (ins i8mem:$src1, GR8:$src2),
461 "xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
462 def XCHG16mr : I<0x87, MRMDestMem,
463 (outs), (ins i16mem:$src1, GR16:$src2),
464 "xchg{w}\t{$src2|$src1}, {$src1|$src2}", []>, OpSize;
465 def XCHG32mr : I<0x87, MRMDestMem,
466 (outs), (ins i32mem:$src1, GR32:$src2),
467 "xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
468 def XCHG8rm : I<0x86, MRMSrcMem,
469 (outs), (ins GR8:$src1, i8mem:$src2),
470 "xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
471 def XCHG16rm : I<0x87, MRMSrcMem,
472 (outs), (ins GR16:$src1, i16mem:$src2),
473 "xchg{w}\t{$src2|$src1}, {$src1|$src2}", []>, OpSize;
474 def XCHG32rm : I<0x87, MRMSrcMem,
475 (outs), (ins GR32:$src1, i32mem:$src2),
476 "xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
478 def LEA16r : I<0x8D, MRMSrcMem,
479 (outs GR16:$dst), (ins i32mem:$src),
480 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
481 def LEA32r : I<0x8D, MRMSrcMem,
482 (outs GR32:$dst), (ins lea32mem:$src),
483 "lea{l}\t{$src|$dst}, {$dst|$src}",
484 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
486 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
487 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
488 [(X86rep_movs i8)]>, REP;
489 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
490 [(X86rep_movs i16)]>, REP, OpSize;
491 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
492 [(X86rep_movs i32)]>, REP;
495 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
496 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
497 [(X86rep_stos i8)]>, REP;
498 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
499 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
500 [(X86rep_stos i16)]>, REP, OpSize;
501 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
502 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
503 [(X86rep_stos i32)]>, REP;
505 let Defs = [RAX, RDX] in
506 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
509 //===----------------------------------------------------------------------===//
510 // Input/Output Instructions...
512 let Defs = [AL], Uses = [DX] in
513 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
514 "in{b}\t{%dx, %al|%AL, %DX}", []>;
515 let Defs = [AX], Uses = [DX] in
516 def IN16rr : I<0xED, RawFrm, (outs), (ins),
517 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
518 let Defs = [EAX], Uses = [DX] in
519 def IN32rr : I<0xED, RawFrm, (outs), (ins),
520 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
523 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
524 "in{b}\t{$port, %al|%AL, $port}", []>;
526 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
527 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
529 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
530 "in{l}\t{$port, %eax|%EAX, $port}", []>;
532 let Uses = [DX, AL] in
533 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
534 "out{b}\t{%al, %dx|%DX, %AL}", []>;
535 let Uses = [DX, AX] in
536 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
537 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
538 let Uses = [DX, EAX] in
539 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
540 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
543 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
544 "out{b}\t{%al, $port|$port, %AL}", []>;
546 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
547 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
549 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
550 "out{l}\t{%eax, $port|$port, %EAX}", []>;
552 //===----------------------------------------------------------------------===//
553 // Move Instructions...
555 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
556 "mov{b}\t{$src, $dst|$dst, $src}", []>;
557 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
558 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
559 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
560 "mov{l}\t{$src, $dst|$dst, $src}", []>;
561 let isReMaterializable = 1 in {
562 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
563 "mov{b}\t{$src, $dst|$dst, $src}",
564 [(set GR8:$dst, imm:$src)]>;
565 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
566 "mov{w}\t{$src, $dst|$dst, $src}",
567 [(set GR16:$dst, imm:$src)]>, OpSize;
568 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
569 "mov{l}\t{$src, $dst|$dst, $src}",
570 [(set GR32:$dst, imm:$src)]>;
572 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
573 "mov{b}\t{$src, $dst|$dst, $src}",
574 [(store (i8 imm:$src), addr:$dst)]>;
575 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
576 "mov{w}\t{$src, $dst|$dst, $src}",
577 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
578 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
579 "mov{l}\t{$src, $dst|$dst, $src}",
580 [(store (i32 imm:$src), addr:$dst)]>;
583 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
584 "mov{b}\t{$src, $dst|$dst, $src}",
585 [(set GR8:$dst, (load addr:$src))]>;
586 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
587 "mov{w}\t{$src, $dst|$dst, $src}",
588 [(set GR16:$dst, (load addr:$src))]>, OpSize;
589 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
590 "mov{l}\t{$src, $dst|$dst, $src}",
591 [(set GR32:$dst, (load addr:$src))]>;
594 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
595 "mov{b}\t{$src, $dst|$dst, $src}",
596 [(store GR8:$src, addr:$dst)]>;
597 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
598 "mov{w}\t{$src, $dst|$dst, $src}",
599 [(store GR16:$src, addr:$dst)]>, OpSize;
600 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
601 "mov{l}\t{$src, $dst|$dst, $src}",
602 [(store GR32:$src, addr:$dst)]>;
604 //===----------------------------------------------------------------------===//
605 // Fixed-Register Multiplication and Division Instructions...
608 // Extra precision multiplication
609 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
610 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
611 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
612 // This probably ought to be moved to a def : Pat<> if the
613 // syntax can be accepted.
614 [(set AL, (mul AL, GR8:$src))]>; // AL,AH = AL*GR8
615 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
616 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>,
617 OpSize; // AX,DX = AX*GR16
618 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
619 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l}\t$src", []>;
620 // EAX,EDX = EAX*GR32
621 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
622 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
624 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
625 // This probably ought to be moved to a def : Pat<> if the
626 // syntax can be accepted.
627 [(set AL, (mul AL, (loadi8 addr:$src)))]>; // AL,AH = AL*[mem8]
628 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
629 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
630 "mul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
631 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
632 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
633 "mul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
635 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
636 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
638 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
639 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
640 OpSize; // AX,DX = AX*GR16
641 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
642 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
643 // EAX,EDX = EAX*GR32
644 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
645 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
646 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
647 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
648 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
649 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
650 let Defs = [EAX,EDX], Uses = [EAX] in
651 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
652 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
654 // unsigned division/remainder
655 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
656 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
658 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
659 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
660 "div{w}\t$src", []>, OpSize;
661 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
662 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
664 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
665 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
667 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
668 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
669 "div{w}\t$src", []>, OpSize;
670 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
671 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
674 // Signed division/remainder.
675 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
676 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
677 "idiv{b}\t$src", []>;
678 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
679 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
680 "idiv{w}\t$src", []>, OpSize;
681 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
682 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
683 "idiv{l}\t$src", []>;
684 let Defs = [AX,EFLAGS], Uses = [AL,AH] in
685 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
686 "idiv{b}\t$src", []>;
687 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
688 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
689 "idiv{w}\t$src", []>, OpSize;
690 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
691 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
692 "idiv{l}\t$src", []>;
695 //===----------------------------------------------------------------------===//
696 // Two address Instructions...
698 let isTwoAddress = 1 in {
701 let Uses = [EFLAGS] in {
702 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
703 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
704 "cmovb\t{$src2, $dst|$dst, $src2}",
705 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
708 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
709 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
710 "cmovb\t{$src2, $dst|$dst, $src2}",
711 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
714 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
715 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
716 "cmovb\t{$src2, $dst|$dst, $src2}",
717 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
720 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
721 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
722 "cmovb\t{$src2, $dst|$dst, $src2}",
723 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
727 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
728 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
729 "cmovae\t{$src2, $dst|$dst, $src2}",
730 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
733 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
734 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
735 "cmovae\t{$src2, $dst|$dst, $src2}",
736 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
739 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
740 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
741 "cmovae\t{$src2, $dst|$dst, $src2}",
742 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
745 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
746 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
747 "cmovae\t{$src2, $dst|$dst, $src2}",
748 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
752 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
753 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
754 "cmove\t{$src2, $dst|$dst, $src2}",
755 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
758 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
759 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
760 "cmove\t{$src2, $dst|$dst, $src2}",
761 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
764 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
765 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
766 "cmove\t{$src2, $dst|$dst, $src2}",
767 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
770 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
771 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
772 "cmove\t{$src2, $dst|$dst, $src2}",
773 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
777 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
778 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
779 "cmovne\t{$src2, $dst|$dst, $src2}",
780 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
783 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
784 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
785 "cmovne\t{$src2, $dst|$dst, $src2}",
786 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
789 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
790 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
791 "cmovne\t{$src2, $dst|$dst, $src2}",
792 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
795 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
796 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
797 "cmovne\t{$src2, $dst|$dst, $src2}",
798 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
802 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
803 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
804 "cmovbe\t{$src2, $dst|$dst, $src2}",
805 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
808 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
809 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
810 "cmovbe\t{$src2, $dst|$dst, $src2}",
811 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
814 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
815 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
816 "cmovbe\t{$src2, $dst|$dst, $src2}",
817 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
820 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
821 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
822 "cmovbe\t{$src2, $dst|$dst, $src2}",
823 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
827 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
828 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
829 "cmova\t{$src2, $dst|$dst, $src2}",
830 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
833 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
834 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
835 "cmova\t{$src2, $dst|$dst, $src2}",
836 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
839 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
840 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
841 "cmova\t{$src2, $dst|$dst, $src2}",
842 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
845 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
846 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
847 "cmova\t{$src2, $dst|$dst, $src2}",
848 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
852 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
853 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
854 "cmovl\t{$src2, $dst|$dst, $src2}",
855 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
858 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
859 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
860 "cmovl\t{$src2, $dst|$dst, $src2}",
861 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
864 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
865 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
866 "cmovl\t{$src2, $dst|$dst, $src2}",
867 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
870 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
871 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
872 "cmovl\t{$src2, $dst|$dst, $src2}",
873 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
877 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
878 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
879 "cmovge\t{$src2, $dst|$dst, $src2}",
880 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
883 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
884 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
885 "cmovge\t{$src2, $dst|$dst, $src2}",
886 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
889 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
890 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
891 "cmovge\t{$src2, $dst|$dst, $src2}",
892 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
895 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
896 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
897 "cmovge\t{$src2, $dst|$dst, $src2}",
898 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
902 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
903 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
904 "cmovle\t{$src2, $dst|$dst, $src2}",
905 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
908 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
909 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
910 "cmovle\t{$src2, $dst|$dst, $src2}",
911 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
914 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
915 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
916 "cmovle\t{$src2, $dst|$dst, $src2}",
917 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
920 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
921 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
922 "cmovle\t{$src2, $dst|$dst, $src2}",
923 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
927 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
928 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
929 "cmovg\t{$src2, $dst|$dst, $src2}",
930 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
933 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
934 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
935 "cmovg\t{$src2, $dst|$dst, $src2}",
936 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
939 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
940 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
941 "cmovg\t{$src2, $dst|$dst, $src2}",
942 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
945 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
946 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
947 "cmovg\t{$src2, $dst|$dst, $src2}",
948 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
952 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
953 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
954 "cmovs\t{$src2, $dst|$dst, $src2}",
955 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
958 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
959 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
960 "cmovs\t{$src2, $dst|$dst, $src2}",
961 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
964 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
965 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
966 "cmovs\t{$src2, $dst|$dst, $src2}",
967 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
970 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
971 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
972 "cmovs\t{$src2, $dst|$dst, $src2}",
973 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
977 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
978 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
979 "cmovns\t{$src2, $dst|$dst, $src2}",
980 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
983 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
984 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
985 "cmovns\t{$src2, $dst|$dst, $src2}",
986 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
989 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
990 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
991 "cmovns\t{$src2, $dst|$dst, $src2}",
992 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
995 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
996 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
997 "cmovns\t{$src2, $dst|$dst, $src2}",
998 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1002 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1003 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1004 "cmovp\t{$src2, $dst|$dst, $src2}",
1005 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1008 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1009 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1010 "cmovp\t{$src2, $dst|$dst, $src2}",
1011 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1014 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1015 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1016 "cmovp\t{$src2, $dst|$dst, $src2}",
1017 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1020 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1021 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1022 "cmovp\t{$src2, $dst|$dst, $src2}",
1023 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1027 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1028 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1029 "cmovnp\t{$src2, $dst|$dst, $src2}",
1030 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1033 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1034 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1035 "cmovnp\t{$src2, $dst|$dst, $src2}",
1036 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1039 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1040 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1041 "cmovnp\t{$src2, $dst|$dst, $src2}",
1042 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1045 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1046 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1047 "cmovnp\t{$src2, $dst|$dst, $src2}",
1048 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1053 def NEW_CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1054 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1055 "cmovb\t{$src2, $dst|$dst, $src2}",
1056 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1057 X86_COND_B, EFLAGS))]>,
1059 def NEW_CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1060 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1061 "cmovb\t{$src2, $dst|$dst, $src2}",
1062 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1063 X86_COND_B, EFLAGS))]>,
1065 def NEW_CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1066 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1067 "cmovb\t{$src2, $dst|$dst, $src2}",
1068 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1069 X86_COND_B, EFLAGS))]>,
1071 def NEW_CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1072 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1073 "cmovb\t{$src2, $dst|$dst, $src2}",
1074 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1075 X86_COND_B, EFLAGS))]>,
1078 def NEW_CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1079 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1080 "cmovae\t{$src2, $dst|$dst, $src2}",
1081 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1082 X86_COND_AE, EFLAGS))]>,
1084 def NEW_CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1085 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1086 "cmovae\t{$src2, $dst|$dst, $src2}",
1087 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1088 X86_COND_AE, EFLAGS))]>,
1090 def NEW_CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1091 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1092 "cmovae\t{$src2, $dst|$dst, $src2}",
1093 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1094 X86_COND_AE, EFLAGS))]>,
1096 def NEW_CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1097 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1098 "cmovae\t{$src2, $dst|$dst, $src2}",
1099 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1100 X86_COND_AE, EFLAGS))]>,
1103 def NEW_CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1104 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1105 "cmove\t{$src2, $dst|$dst, $src2}",
1106 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1107 X86_COND_E, EFLAGS))]>,
1109 def NEW_CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1110 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1111 "cmove\t{$src2, $dst|$dst, $src2}",
1112 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1113 X86_COND_E, EFLAGS))]>,
1115 def NEW_CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1116 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1117 "cmove\t{$src2, $dst|$dst, $src2}",
1118 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1119 X86_COND_E, EFLAGS))]>,
1121 def NEW_CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1122 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1123 "cmove\t{$src2, $dst|$dst, $src2}",
1124 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1125 X86_COND_E, EFLAGS))]>,
1128 def NEW_CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1129 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1130 "cmovne\t{$src2, $dst|$dst, $src2}",
1131 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1132 X86_COND_NE, EFLAGS))]>,
1134 def NEW_CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1135 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1136 "cmovne\t{$src2, $dst|$dst, $src2}",
1137 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1138 X86_COND_NE, EFLAGS))]>,
1140 def NEW_CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1141 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1142 "cmovne\t{$src2, $dst|$dst, $src2}",
1143 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1144 X86_COND_NE, EFLAGS))]>,
1146 def NEW_CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1147 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1148 "cmovne\t{$src2, $dst|$dst, $src2}",
1149 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1150 X86_COND_NE, EFLAGS))]>,
1153 def NEW_CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1154 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1155 "cmovbe\t{$src2, $dst|$dst, $src2}",
1156 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1157 X86_COND_BE, EFLAGS))]>,
1159 def NEW_CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1160 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1161 "cmovbe\t{$src2, $dst|$dst, $src2}",
1162 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1163 X86_COND_BE, EFLAGS))]>,
1165 def NEW_CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1166 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1167 "cmovbe\t{$src2, $dst|$dst, $src2}",
1168 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1169 X86_COND_BE, EFLAGS))]>,
1171 def NEW_CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1172 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1173 "cmovbe\t{$src2, $dst|$dst, $src2}",
1174 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1175 X86_COND_BE, EFLAGS))]>,
1178 def NEW_CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1179 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1180 "cmova\t{$src2, $dst|$dst, $src2}",
1181 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1182 X86_COND_A, EFLAGS))]>,
1184 def NEW_CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1185 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1186 "cmova\t{$src2, $dst|$dst, $src2}",
1187 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1188 X86_COND_A, EFLAGS))]>,
1190 def NEW_CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1191 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1192 "cmova\t{$src2, $dst|$dst, $src2}",
1193 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1194 X86_COND_A, EFLAGS))]>,
1196 def NEW_CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1197 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1198 "cmova\t{$src2, $dst|$dst, $src2}",
1199 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1200 X86_COND_A, EFLAGS))]>,
1203 def NEW_CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1204 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1205 "cmovl\t{$src2, $dst|$dst, $src2}",
1206 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1207 X86_COND_L, EFLAGS))]>,
1209 def NEW_CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1210 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1211 "cmovl\t{$src2, $dst|$dst, $src2}",
1212 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1213 X86_COND_L, EFLAGS))]>,
1215 def NEW_CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1216 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1217 "cmovl\t{$src2, $dst|$dst, $src2}",
1218 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1219 X86_COND_L, EFLAGS))]>,
1221 def NEW_CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1222 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1223 "cmovl\t{$src2, $dst|$dst, $src2}",
1224 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1225 X86_COND_L, EFLAGS))]>,
1228 def NEW_CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1229 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1230 "cmovge\t{$src2, $dst|$dst, $src2}",
1231 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1232 X86_COND_GE, EFLAGS))]>,
1234 def NEW_CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1235 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1236 "cmovge\t{$src2, $dst|$dst, $src2}",
1237 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1238 X86_COND_GE, EFLAGS))]>,
1240 def NEW_CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1241 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1242 "cmovge\t{$src2, $dst|$dst, $src2}",
1243 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1244 X86_COND_GE, EFLAGS))]>,
1246 def NEW_CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1247 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1248 "cmovge\t{$src2, $dst|$dst, $src2}",
1249 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1250 X86_COND_GE, EFLAGS))]>,
1253 def NEW_CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1254 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1255 "cmovle\t{$src2, $dst|$dst, $src2}",
1256 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1257 X86_COND_LE, EFLAGS))]>,
1259 def NEW_CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1260 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1261 "cmovle\t{$src2, $dst|$dst, $src2}",
1262 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1263 X86_COND_LE, EFLAGS))]>,
1265 def NEW_CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1266 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1267 "cmovle\t{$src2, $dst|$dst, $src2}",
1268 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1269 X86_COND_LE, EFLAGS))]>,
1271 def NEW_CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1272 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1273 "cmovle\t{$src2, $dst|$dst, $src2}",
1274 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1275 X86_COND_LE, EFLAGS))]>,
1278 def NEW_CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1279 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1280 "cmovg\t{$src2, $dst|$dst, $src2}",
1281 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1282 X86_COND_G, EFLAGS))]>,
1284 def NEW_CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1285 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1286 "cmovg\t{$src2, $dst|$dst, $src2}",
1287 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1288 X86_COND_G, EFLAGS))]>,
1290 def NEW_CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1291 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1292 "cmovg\t{$src2, $dst|$dst, $src2}",
1293 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1294 X86_COND_G, EFLAGS))]>,
1296 def NEW_CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1297 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1298 "cmovg\t{$src2, $dst|$dst, $src2}",
1299 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1300 X86_COND_G, EFLAGS))]>,
1303 def NEW_CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1304 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1305 "cmovs\t{$src2, $dst|$dst, $src2}",
1306 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1307 X86_COND_S, EFLAGS))]>,
1309 def NEW_CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1310 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1311 "cmovs\t{$src2, $dst|$dst, $src2}",
1312 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1313 X86_COND_S, EFLAGS))]>,
1315 def NEW_CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1316 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1317 "cmovs\t{$src2, $dst|$dst, $src2}",
1318 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1319 X86_COND_S, EFLAGS))]>,
1321 def NEW_CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1322 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1323 "cmovs\t{$src2, $dst|$dst, $src2}",
1324 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1325 X86_COND_S, EFLAGS))]>,
1328 def NEW_CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1329 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1330 "cmovns\t{$src2, $dst|$dst, $src2}",
1331 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1332 X86_COND_NS, EFLAGS))]>,
1334 def NEW_CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1335 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1336 "cmovns\t{$src2, $dst|$dst, $src2}",
1337 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1338 X86_COND_NS, EFLAGS))]>,
1340 def NEW_CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1341 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1342 "cmovns\t{$src2, $dst|$dst, $src2}",
1343 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1344 X86_COND_NS, EFLAGS))]>,
1346 def NEW_CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1347 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1348 "cmovns\t{$src2, $dst|$dst, $src2}",
1349 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1350 X86_COND_NS, EFLAGS))]>,
1353 def NEW_CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1354 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1355 "cmovp\t{$src2, $dst|$dst, $src2}",
1356 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1357 X86_COND_P, EFLAGS))]>,
1359 def NEW_CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1360 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1361 "cmovp\t{$src2, $dst|$dst, $src2}",
1362 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1363 X86_COND_P, EFLAGS))]>,
1365 def NEW_CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1366 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1367 "cmovp\t{$src2, $dst|$dst, $src2}",
1368 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1369 X86_COND_P, EFLAGS))]>,
1371 def NEW_CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1372 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1373 "cmovp\t{$src2, $dst|$dst, $src2}",
1374 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1375 X86_COND_P, EFLAGS))]>,
1378 def NEW_CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1379 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1380 "cmovnp\t{$src2, $dst|$dst, $src2}",
1381 [(set GR16:$dst, (X86cmov_new GR16:$src1, GR16:$src2,
1382 X86_COND_NP, EFLAGS))]>,
1384 def NEW_CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1385 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1386 "cmovnp\t{$src2, $dst|$dst, $src2}",
1387 [(set GR16:$dst, (X86cmov_new GR16:$src1, (loadi16 addr:$src2),
1388 X86_COND_NP, EFLAGS))]>,
1390 def NEW_CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1391 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1392 "cmovnp\t{$src2, $dst|$dst, $src2}",
1393 [(set GR32:$dst, (X86cmov_new GR32:$src1, GR32:$src2,
1394 X86_COND_NP, EFLAGS))]>,
1396 def NEW_CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1397 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1398 "cmovnp\t{$src2, $dst|$dst, $src2}",
1399 [(set GR32:$dst, (X86cmov_new GR32:$src1, (loadi32 addr:$src2),
1400 X86_COND_NP, EFLAGS))]>,
1402 } // Uses = [EFLAGS]
1405 // unary instructions
1406 let CodeSize = 2 in {
1407 let Defs = [EFLAGS] in {
1408 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1409 [(set GR8:$dst, (ineg GR8:$src))]>;
1410 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1411 [(set GR16:$dst, (ineg GR16:$src))]>, OpSize;
1412 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1413 [(set GR32:$dst, (ineg GR32:$src))]>;
1414 let isTwoAddress = 0 in {
1415 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1416 [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
1417 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1418 [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1419 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1420 [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
1423 } // Defs = [EFLAGS]
1425 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1426 [(set GR8:$dst, (not GR8:$src))]>;
1427 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1428 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1429 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1430 [(set GR32:$dst, (not GR32:$src))]>;
1431 let isTwoAddress = 0 in {
1432 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1433 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1434 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1435 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1436 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1437 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1441 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1442 let Defs = [EFLAGS] in {
1444 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1445 [(set GR8:$dst, (add GR8:$src, 1))]>;
1446 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1447 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1448 [(set GR16:$dst, (add GR16:$src, 1))]>,
1449 OpSize, Requires<[In32BitMode]>;
1450 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1451 [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>;
1453 let isTwoAddress = 0, CodeSize = 2 in {
1454 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1455 [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
1456 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1457 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>, OpSize;
1458 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1459 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>;
1463 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1464 [(set GR8:$dst, (add GR8:$src, -1))]>;
1465 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1466 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1467 [(set GR16:$dst, (add GR16:$src, -1))]>,
1468 OpSize, Requires<[In32BitMode]>;
1469 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1470 [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>;
1473 let isTwoAddress = 0, CodeSize = 2 in {
1474 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1475 [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
1476 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1477 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>, OpSize;
1478 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1479 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>;
1481 } // Defs = [EFLAGS]
1483 // Logical operators...
1484 let Defs = [EFLAGS] in {
1485 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1486 def AND8rr : I<0x20, MRMDestReg,
1487 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1488 "and{b}\t{$src2, $dst|$dst, $src2}",
1489 [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>;
1490 def AND16rr : I<0x21, MRMDestReg,
1491 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1492 "and{w}\t{$src2, $dst|$dst, $src2}",
1493 [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize;
1494 def AND32rr : I<0x21, MRMDestReg,
1495 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1496 "and{l}\t{$src2, $dst|$dst, $src2}",
1497 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
1500 def AND8rm : I<0x22, MRMSrcMem,
1501 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1502 "and{b}\t{$src2, $dst|$dst, $src2}",
1503 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>;
1504 def AND16rm : I<0x23, MRMSrcMem,
1505 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1506 "and{w}\t{$src2, $dst|$dst, $src2}",
1507 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize;
1508 def AND32rm : I<0x23, MRMSrcMem,
1509 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1510 "and{l}\t{$src2, $dst|$dst, $src2}",
1511 [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>;
1513 def AND8ri : Ii8<0x80, MRM4r,
1514 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1515 "and{b}\t{$src2, $dst|$dst, $src2}",
1516 [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>;
1517 def AND16ri : Ii16<0x81, MRM4r,
1518 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1519 "and{w}\t{$src2, $dst|$dst, $src2}",
1520 [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize;
1521 def AND32ri : Ii32<0x81, MRM4r,
1522 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1523 "and{l}\t{$src2, $dst|$dst, $src2}",
1524 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
1525 def AND16ri8 : Ii8<0x83, MRM4r,
1526 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1527 "and{w}\t{$src2, $dst|$dst, $src2}",
1528 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>,
1530 def AND32ri8 : Ii8<0x83, MRM4r,
1531 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1532 "and{l}\t{$src2, $dst|$dst, $src2}",
1533 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>;
1535 let isTwoAddress = 0 in {
1536 def AND8mr : I<0x20, MRMDestMem,
1537 (outs), (ins i8mem :$dst, GR8 :$src),
1538 "and{b}\t{$src, $dst|$dst, $src}",
1539 [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>;
1540 def AND16mr : I<0x21, MRMDestMem,
1541 (outs), (ins i16mem:$dst, GR16:$src),
1542 "and{w}\t{$src, $dst|$dst, $src}",
1543 [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>,
1545 def AND32mr : I<0x21, MRMDestMem,
1546 (outs), (ins i32mem:$dst, GR32:$src),
1547 "and{l}\t{$src, $dst|$dst, $src}",
1548 [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>;
1549 def AND8mi : Ii8<0x80, MRM4m,
1550 (outs), (ins i8mem :$dst, i8imm :$src),
1551 "and{b}\t{$src, $dst|$dst, $src}",
1552 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1553 def AND16mi : Ii16<0x81, MRM4m,
1554 (outs), (ins i16mem:$dst, i16imm:$src),
1555 "and{w}\t{$src, $dst|$dst, $src}",
1556 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1558 def AND32mi : Ii32<0x81, MRM4m,
1559 (outs), (ins i32mem:$dst, i32imm:$src),
1560 "and{l}\t{$src, $dst|$dst, $src}",
1561 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1562 def AND16mi8 : Ii8<0x83, MRM4m,
1563 (outs), (ins i16mem:$dst, i16i8imm :$src),
1564 "and{w}\t{$src, $dst|$dst, $src}",
1565 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1567 def AND32mi8 : Ii8<0x83, MRM4m,
1568 (outs), (ins i32mem:$dst, i32i8imm :$src),
1569 "and{l}\t{$src, $dst|$dst, $src}",
1570 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1574 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1575 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1576 "or{b}\t{$src2, $dst|$dst, $src2}",
1577 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
1578 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1579 "or{w}\t{$src2, $dst|$dst, $src2}",
1580 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize;
1581 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1582 "or{l}\t{$src2, $dst|$dst, $src2}",
1583 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
1585 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1586 "or{b}\t{$src2, $dst|$dst, $src2}",
1587 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
1588 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1589 "or{w}\t{$src2, $dst|$dst, $src2}",
1590 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize;
1591 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1592 "or{l}\t{$src2, $dst|$dst, $src2}",
1593 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>;
1595 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1596 "or{b}\t{$src2, $dst|$dst, $src2}",
1597 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
1598 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1599 "or{w}\t{$src2, $dst|$dst, $src2}",
1600 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize;
1601 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1602 "or{l}\t{$src2, $dst|$dst, $src2}",
1603 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
1605 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1606 "or{w}\t{$src2, $dst|$dst, $src2}",
1607 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1608 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1609 "or{l}\t{$src2, $dst|$dst, $src2}",
1610 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>;
1611 let isTwoAddress = 0 in {
1612 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1613 "or{b}\t{$src, $dst|$dst, $src}",
1614 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
1615 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1616 "or{w}\t{$src, $dst|$dst, $src}",
1617 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize;
1618 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1619 "or{l}\t{$src, $dst|$dst, $src}",
1620 [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>;
1621 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1622 "or{b}\t{$src, $dst|$dst, $src}",
1623 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1624 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1625 "or{w}\t{$src, $dst|$dst, $src}",
1626 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1628 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1629 "or{l}\t{$src, $dst|$dst, $src}",
1630 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1631 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1632 "or{w}\t{$src, $dst|$dst, $src}",
1633 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1635 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1636 "or{l}\t{$src, $dst|$dst, $src}",
1637 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1641 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1642 def XOR8rr : I<0x30, MRMDestReg,
1643 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1644 "xor{b}\t{$src2, $dst|$dst, $src2}",
1645 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>;
1646 def XOR16rr : I<0x31, MRMDestReg,
1647 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1648 "xor{w}\t{$src2, $dst|$dst, $src2}",
1649 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize;
1650 def XOR32rr : I<0x31, MRMDestReg,
1651 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1652 "xor{l}\t{$src2, $dst|$dst, $src2}",
1653 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
1656 def XOR8rm : I<0x32, MRMSrcMem ,
1657 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1658 "xor{b}\t{$src2, $dst|$dst, $src2}",
1659 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>;
1660 def XOR16rm : I<0x33, MRMSrcMem ,
1661 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1662 "xor{w}\t{$src2, $dst|$dst, $src2}",
1663 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>, OpSize;
1664 def XOR32rm : I<0x33, MRMSrcMem ,
1665 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1666 "xor{l}\t{$src2, $dst|$dst, $src2}",
1667 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>;
1669 def XOR8ri : Ii8<0x80, MRM6r,
1670 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1671 "xor{b}\t{$src2, $dst|$dst, $src2}",
1672 [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>;
1673 def XOR16ri : Ii16<0x81, MRM6r,
1674 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1675 "xor{w}\t{$src2, $dst|$dst, $src2}",
1676 [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize;
1677 def XOR32ri : Ii32<0x81, MRM6r,
1678 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1679 "xor{l}\t{$src2, $dst|$dst, $src2}",
1680 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
1681 def XOR16ri8 : Ii8<0x83, MRM6r,
1682 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1683 "xor{w}\t{$src2, $dst|$dst, $src2}",
1684 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>,
1686 def XOR32ri8 : Ii8<0x83, MRM6r,
1687 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1688 "xor{l}\t{$src2, $dst|$dst, $src2}",
1689 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>;
1690 let isTwoAddress = 0 in {
1691 def XOR8mr : I<0x30, MRMDestMem,
1692 (outs), (ins i8mem :$dst, GR8 :$src),
1693 "xor{b}\t{$src, $dst|$dst, $src}",
1694 [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>;
1695 def XOR16mr : I<0x31, MRMDestMem,
1696 (outs), (ins i16mem:$dst, GR16:$src),
1697 "xor{w}\t{$src, $dst|$dst, $src}",
1698 [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>,
1700 def XOR32mr : I<0x31, MRMDestMem,
1701 (outs), (ins i32mem:$dst, GR32:$src),
1702 "xor{l}\t{$src, $dst|$dst, $src}",
1703 [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>;
1704 def XOR8mi : Ii8<0x80, MRM6m,
1705 (outs), (ins i8mem :$dst, i8imm :$src),
1706 "xor{b}\t{$src, $dst|$dst, $src}",
1707 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1708 def XOR16mi : Ii16<0x81, MRM6m,
1709 (outs), (ins i16mem:$dst, i16imm:$src),
1710 "xor{w}\t{$src, $dst|$dst, $src}",
1711 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1713 def XOR32mi : Ii32<0x81, MRM6m,
1714 (outs), (ins i32mem:$dst, i32imm:$src),
1715 "xor{l}\t{$src, $dst|$dst, $src}",
1716 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1717 def XOR16mi8 : Ii8<0x83, MRM6m,
1718 (outs), (ins i16mem:$dst, i16i8imm :$src),
1719 "xor{w}\t{$src, $dst|$dst, $src}",
1720 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1722 def XOR32mi8 : Ii8<0x83, MRM6m,
1723 (outs), (ins i32mem:$dst, i32i8imm :$src),
1724 "xor{l}\t{$src, $dst|$dst, $src}",
1725 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1727 } // Defs = [EFLAGS]
1729 // Shift instructions
1730 let Defs = [EFLAGS] in {
1731 let Uses = [CL] in {
1732 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1733 "shl{b}\t{%cl, $dst|$dst, %CL}",
1734 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1735 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1736 "shl{w}\t{%cl, $dst|$dst, %CL}",
1737 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1738 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1739 "shl{l}\t{%cl, $dst|$dst, %CL}",
1740 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1743 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1744 "shl{b}\t{$src2, $dst|$dst, $src2}",
1745 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1746 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1747 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1748 "shl{w}\t{$src2, $dst|$dst, $src2}",
1749 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1750 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1751 "shl{l}\t{$src2, $dst|$dst, $src2}",
1752 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1755 // Shift left by one. Not used because (add x, x) is slightly cheaper.
1756 def SHL8r1 : I<0xD0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
1757 "shl{b}\t$dst", []>;
1758 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
1759 "shl{w}\t$dst", []>, OpSize;
1760 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
1761 "shl{l}\t$dst", []>;
1763 let isTwoAddress = 0 in {
1764 let Uses = [CL] in {
1765 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1766 "shl{b}\t{%cl, $dst|$dst, %CL}",
1767 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1768 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1769 "shl{w}\t{%cl, $dst|$dst, %CL}",
1770 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1771 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1772 "shl{l}\t{%cl, $dst|$dst, %CL}",
1773 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1775 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1776 "shl{b}\t{$src, $dst|$dst, $src}",
1777 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1778 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1779 "shl{w}\t{$src, $dst|$dst, $src}",
1780 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1782 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1783 "shl{l}\t{$src, $dst|$dst, $src}",
1784 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1787 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1789 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1790 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1792 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1794 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1796 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1799 let Uses = [CL] in {
1800 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1801 "shr{b}\t{%cl, $dst|$dst, %CL}",
1802 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1803 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1804 "shr{w}\t{%cl, $dst|$dst, %CL}",
1805 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1806 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1807 "shr{l}\t{%cl, $dst|$dst, %CL}",
1808 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1811 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1812 "shr{b}\t{$src2, $dst|$dst, $src2}",
1813 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1814 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1815 "shr{w}\t{$src2, $dst|$dst, $src2}",
1816 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1817 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1818 "shr{l}\t{$src2, $dst|$dst, $src2}",
1819 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1822 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1824 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1825 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1827 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1828 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1830 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1832 let isTwoAddress = 0 in {
1833 let Uses = [CL] in {
1834 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1835 "shr{b}\t{%cl, $dst|$dst, %CL}",
1836 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1837 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1838 "shr{w}\t{%cl, $dst|$dst, %CL}",
1839 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1841 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1842 "shr{l}\t{%cl, $dst|$dst, %CL}",
1843 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1845 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1846 "shr{b}\t{$src, $dst|$dst, $src}",
1847 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1848 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1849 "shr{w}\t{$src, $dst|$dst, $src}",
1850 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1852 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1853 "shr{l}\t{$src, $dst|$dst, $src}",
1854 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1857 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1859 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1860 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1862 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1863 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1865 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1868 let Uses = [CL] in {
1869 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1870 "sar{b}\t{%cl, $dst|$dst, %CL}",
1871 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1872 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1873 "sar{w}\t{%cl, $dst|$dst, %CL}",
1874 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1875 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1876 "sar{l}\t{%cl, $dst|$dst, %CL}",
1877 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1880 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1881 "sar{b}\t{$src2, $dst|$dst, $src2}",
1882 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1883 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1884 "sar{w}\t{$src2, $dst|$dst, $src2}",
1885 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1887 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1888 "sar{l}\t{$src2, $dst|$dst, $src2}",
1889 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1892 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1894 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1895 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1897 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1898 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1900 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1902 let isTwoAddress = 0 in {
1903 let Uses = [CL] in {
1904 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1905 "sar{b}\t{%cl, $dst|$dst, %CL}",
1906 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
1907 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1908 "sar{w}\t{%cl, $dst|$dst, %CL}",
1909 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1910 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1911 "sar{l}\t{%cl, $dst|$dst, %CL}",
1912 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1914 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1915 "sar{b}\t{$src, $dst|$dst, $src}",
1916 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1917 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1918 "sar{w}\t{$src, $dst|$dst, $src}",
1919 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1921 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1922 "sar{l}\t{$src, $dst|$dst, $src}",
1923 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1926 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1928 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1929 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1931 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1933 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
1935 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1938 // Rotate instructions
1939 // FIXME: provide shorter instructions when imm8 == 1
1940 let Uses = [CL] in {
1941 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
1942 "rol{b}\t{%cl, $dst|$dst, %CL}",
1943 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
1944 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
1945 "rol{w}\t{%cl, $dst|$dst, %CL}",
1946 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
1947 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
1948 "rol{l}\t{%cl, $dst|$dst, %CL}",
1949 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
1952 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1953 "rol{b}\t{$src2, $dst|$dst, $src2}",
1954 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1955 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1956 "rol{w}\t{$src2, $dst|$dst, $src2}",
1957 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1958 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1959 "rol{l}\t{$src2, $dst|$dst, $src2}",
1960 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1963 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1965 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1966 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
1968 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1969 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1971 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1973 let isTwoAddress = 0 in {
1974 let Uses = [CL] in {
1975 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
1976 "rol{b}\t{%cl, $dst|$dst, %CL}",
1977 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
1978 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
1979 "rol{w}\t{%cl, $dst|$dst, %CL}",
1980 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1981 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
1982 "rol{l}\t{%cl, $dst|$dst, %CL}",
1983 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
1985 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
1986 "rol{b}\t{$src, $dst|$dst, $src}",
1987 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1988 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
1989 "rol{w}\t{$src, $dst|$dst, $src}",
1990 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1992 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
1993 "rol{l}\t{$src, $dst|$dst, $src}",
1994 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1997 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
1999 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2000 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2002 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2004 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2006 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2009 let Uses = [CL] in {
2010 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2011 "ror{b}\t{%cl, $dst|$dst, %CL}",
2012 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2013 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2014 "ror{w}\t{%cl, $dst|$dst, %CL}",
2015 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2016 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2017 "ror{l}\t{%cl, $dst|$dst, %CL}",
2018 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2021 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2022 "ror{b}\t{$src2, $dst|$dst, $src2}",
2023 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2024 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2025 "ror{w}\t{$src2, $dst|$dst, $src2}",
2026 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2027 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2028 "ror{l}\t{$src2, $dst|$dst, $src2}",
2029 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2032 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2034 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2035 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2037 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2038 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2040 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2042 let isTwoAddress = 0 in {
2043 let Uses = [CL] in {
2044 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2045 "ror{b}\t{%cl, $dst|$dst, %CL}",
2046 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2047 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2048 "ror{w}\t{%cl, $dst|$dst, %CL}",
2049 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2050 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2051 "ror{l}\t{%cl, $dst|$dst, %CL}",
2052 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2054 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2055 "ror{b}\t{$src, $dst|$dst, $src}",
2056 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2057 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2058 "ror{w}\t{$src, $dst|$dst, $src}",
2059 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2061 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2062 "ror{l}\t{$src, $dst|$dst, $src}",
2063 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2066 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2068 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2069 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2071 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2073 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2075 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2080 // Double shift instructions (generalizations of rotate)
2081 let Uses = [CL] in {
2082 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2083 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2084 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2085 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2086 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2087 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2088 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2089 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2090 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2092 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2093 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2094 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2098 let isCommutable = 1 in { // These instructions commute to each other.
2099 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2100 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2101 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2102 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2105 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2106 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2107 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2108 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2111 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2112 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2113 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2114 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2117 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2118 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2119 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2120 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2125 let isTwoAddress = 0 in {
2126 let Uses = [CL] in {
2127 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2128 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2129 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2131 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2132 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2133 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2136 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2137 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2138 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2139 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2140 (i8 imm:$src3)), addr:$dst)]>,
2142 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2143 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2144 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2145 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2146 (i8 imm:$src3)), addr:$dst)]>,
2149 let Uses = [CL] in {
2150 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2151 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2152 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2153 addr:$dst)]>, TB, OpSize;
2154 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2155 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
2156 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2157 addr:$dst)]>, TB, OpSize;
2159 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2160 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2161 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2162 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2163 (i8 imm:$src3)), addr:$dst)]>,
2165 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2166 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2167 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2168 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2169 (i8 imm:$src3)), addr:$dst)]>,
2172 } // Defs = [EFLAGS]
2176 let Defs = [EFLAGS] in {
2177 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2178 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2179 (ins GR8 :$src1, GR8 :$src2),
2180 "add{b}\t{$src2, $dst|$dst, $src2}",
2181 [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>;
2182 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2183 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2184 (ins GR16:$src1, GR16:$src2),
2185 "add{w}\t{$src2, $dst|$dst, $src2}",
2186 [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize;
2187 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2188 (ins GR32:$src1, GR32:$src2),
2189 "add{l}\t{$src2, $dst|$dst, $src2}",
2190 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
2191 } // end isConvertibleToThreeAddress
2192 } // end isCommutable
2193 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2194 (ins GR8 :$src1, i8mem :$src2),
2195 "add{b}\t{$src2, $dst|$dst, $src2}",
2196 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>;
2197 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2198 (ins GR16:$src1, i16mem:$src2),
2199 "add{w}\t{$src2, $dst|$dst, $src2}",
2200 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>,OpSize;
2201 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2202 (ins GR32:$src1, i32mem:$src2),
2203 "add{l}\t{$src2, $dst|$dst, $src2}",
2204 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>;
2206 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2207 "add{b}\t{$src2, $dst|$dst, $src2}",
2208 [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>;
2210 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2211 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2212 (ins GR16:$src1, i16imm:$src2),
2213 "add{w}\t{$src2, $dst|$dst, $src2}",
2214 [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize;
2215 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2216 (ins GR32:$src1, i32imm:$src2),
2217 "add{l}\t{$src2, $dst|$dst, $src2}",
2218 [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>;
2219 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2220 (ins GR16:$src1, i16i8imm:$src2),
2221 "add{w}\t{$src2, $dst|$dst, $src2}",
2222 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2223 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2224 (ins GR32:$src1, i32i8imm:$src2),
2225 "add{l}\t{$src2, $dst|$dst, $src2}",
2226 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>;
2229 let isTwoAddress = 0 in {
2230 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2231 "add{b}\t{$src2, $dst|$dst, $src2}",
2232 [(store (add (load addr:$dst), GR8:$src2), addr:$dst)]>;
2233 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2234 "add{w}\t{$src2, $dst|$dst, $src2}",
2235 [(store (add (load addr:$dst), GR16:$src2), addr:$dst)]>,
2237 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2238 "add{l}\t{$src2, $dst|$dst, $src2}",
2239 [(store (add (load addr:$dst), GR32:$src2), addr:$dst)]>;
2240 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2241 "add{b}\t{$src2, $dst|$dst, $src2}",
2242 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2243 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2244 "add{w}\t{$src2, $dst|$dst, $src2}",
2245 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2247 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2248 "add{l}\t{$src2, $dst|$dst, $src2}",
2249 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2250 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2251 "add{w}\t{$src2, $dst|$dst, $src2}",
2252 [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2254 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2255 "add{l}\t{$src2, $dst|$dst, $src2}",
2256 [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2259 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2260 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2261 "adc{l}\t{$src2, $dst|$dst, $src2}",
2262 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2264 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2265 "adc{l}\t{$src2, $dst|$dst, $src2}",
2266 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2267 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2268 "adc{l}\t{$src2, $dst|$dst, $src2}",
2269 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2270 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2271 "adc{l}\t{$src2, $dst|$dst, $src2}",
2272 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2274 let isTwoAddress = 0 in {
2275 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2276 "adc{l}\t{$src2, $dst|$dst, $src2}",
2277 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2278 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2279 "adc{l}\t{$src2, $dst|$dst, $src2}",
2280 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2281 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2282 "adc{l}\t{$src2, $dst|$dst, $src2}",
2283 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2286 def SUB8rr : I<0x28, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
2287 "sub{b}\t{$src2, $dst|$dst, $src2}",
2288 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2))]>;
2289 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2290 "sub{w}\t{$src2, $dst|$dst, $src2}",
2291 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2))]>, OpSize;
2292 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2293 "sub{l}\t{$src2, $dst|$dst, $src2}",
2294 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
2295 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
2296 "sub{b}\t{$src2, $dst|$dst, $src2}",
2297 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2)))]>;
2298 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2299 "sub{w}\t{$src2, $dst|$dst, $src2}",
2300 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2)))]>, OpSize;
2301 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2302 "sub{l}\t{$src2, $dst|$dst, $src2}",
2303 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2)))]>;
2305 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2306 "sub{b}\t{$src2, $dst|$dst, $src2}",
2307 [(set GR8:$dst, (sub GR8:$src1, imm:$src2))]>;
2308 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2309 "sub{w}\t{$src2, $dst|$dst, $src2}",
2310 [(set GR16:$dst, (sub GR16:$src1, imm:$src2))]>, OpSize;
2311 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2312 "sub{l}\t{$src2, $dst|$dst, $src2}",
2313 [(set GR32:$dst, (sub GR32:$src1, imm:$src2))]>;
2314 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2315 "sub{w}\t{$src2, $dst|$dst, $src2}",
2316 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2))]>,
2318 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2319 "sub{l}\t{$src2, $dst|$dst, $src2}",
2320 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2))]>;
2321 let isTwoAddress = 0 in {
2322 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2323 "sub{b}\t{$src2, $dst|$dst, $src2}",
2324 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst)]>;
2325 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2326 "sub{w}\t{$src2, $dst|$dst, $src2}",
2327 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst)]>,
2329 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2330 "sub{l}\t{$src2, $dst|$dst, $src2}",
2331 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst)]>;
2332 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2333 "sub{b}\t{$src2, $dst|$dst, $src2}",
2334 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2335 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2336 "sub{w}\t{$src2, $dst|$dst, $src2}",
2337 [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2339 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2340 "sub{l}\t{$src2, $dst|$dst, $src2}",
2341 [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2342 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2343 "sub{w}\t{$src2, $dst|$dst, $src2}",
2344 [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2346 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2347 "sub{l}\t{$src2, $dst|$dst, $src2}",
2348 [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2351 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2352 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2353 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2355 let isTwoAddress = 0 in {
2356 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2357 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2358 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2359 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2360 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2361 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2362 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2363 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2364 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2365 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2366 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2367 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2369 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2370 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2371 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2372 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2373 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2374 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2375 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2376 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2377 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2378 } // Defs = [EFLAGS]
2380 let Defs = [EFLAGS] in {
2381 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2382 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2383 "imul{w}\t{$src2, $dst|$dst, $src2}",
2384 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2))]>, TB, OpSize;
2385 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2386 "imul{l}\t{$src2, $dst|$dst, $src2}",
2387 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>, TB;
2389 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2390 "imul{w}\t{$src2, $dst|$dst, $src2}",
2391 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2)))]>,
2393 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2394 "imul{l}\t{$src2, $dst|$dst, $src2}",
2395 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2)))]>, TB;
2396 } // Defs = [EFLAGS]
2397 } // end Two Address instructions
2399 // Suprisingly enough, these are not two address instructions!
2400 let Defs = [EFLAGS] in {
2401 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2402 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2403 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2404 [(set GR16:$dst, (mul GR16:$src1, imm:$src2))]>, OpSize;
2405 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2406 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2407 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2408 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
2409 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2410 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2411 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2412 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2))]>,
2414 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2415 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2416 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2417 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2))]>;
2419 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2420 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2421 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2422 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2))]>,
2424 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2425 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2426 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2427 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2))]>;
2428 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2429 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2430 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2431 [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>,
2433 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2434 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2435 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2436 [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>;
2437 } // Defs = [EFLAGS]
2439 //===----------------------------------------------------------------------===//
2440 // Test instructions are just like AND, except they don't generate a result.
2442 let Defs = [EFLAGS] in {
2443 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2444 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2445 "test{b}\t{$src2, $src1|$src1, $src2}",
2446 [(X86cmp (and GR8:$src1, GR8:$src2), 0)]>;
2447 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2448 "test{w}\t{$src2, $src1|$src1, $src2}",
2449 [(X86cmp (and GR16:$src1, GR16:$src2), 0)]>, OpSize;
2450 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2451 "test{l}\t{$src2, $src1|$src1, $src2}",
2452 [(X86cmp (and GR32:$src1, GR32:$src2), 0)]>;
2455 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2456 "test{b}\t{$src2, $src1|$src1, $src2}",
2457 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0)]>;
2458 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2459 "test{w}\t{$src2, $src1|$src1, $src2}",
2460 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0)]>,
2462 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2463 "test{l}\t{$src2, $src1|$src1, $src2}",
2464 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0)]>;
2466 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2467 (outs), (ins GR8:$src1, i8imm:$src2),
2468 "test{b}\t{$src2, $src1|$src1, $src2}",
2469 [(X86cmp (and GR8:$src1, imm:$src2), 0)]>;
2470 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2471 (outs), (ins GR16:$src1, i16imm:$src2),
2472 "test{w}\t{$src2, $src1|$src1, $src2}",
2473 [(X86cmp (and GR16:$src1, imm:$src2), 0)]>, OpSize;
2474 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2475 (outs), (ins GR32:$src1, i32imm:$src2),
2476 "test{l}\t{$src2, $src1|$src1, $src2}",
2477 [(X86cmp (and GR32:$src1, imm:$src2), 0)]>;
2479 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2480 (outs), (ins i8mem:$src1, i8imm:$src2),
2481 "test{b}\t{$src2, $src1|$src1, $src2}",
2482 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0)]>;
2483 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2484 (outs), (ins i16mem:$src1, i16imm:$src2),
2485 "test{w}\t{$src2, $src1|$src1, $src2}",
2486 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0)]>,
2488 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2489 (outs), (ins i32mem:$src1, i32imm:$src2),
2490 "test{l}\t{$src2, $src1|$src1, $src2}",
2491 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0)]>;
2492 } // Defs = [EFLAGS]
2495 let Defs = [EFLAGS] in {
2496 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2497 def NEW_TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2498 "test{b}\t{$src2, $src1|$src1, $src2}",
2499 [(X86cmp_new (and GR8:$src1, GR8:$src2), 0),
2500 (implicit EFLAGS)]>;
2501 def NEW_TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2502 "test{w}\t{$src2, $src1|$src1, $src2}",
2503 [(X86cmp_new (and GR16:$src1, GR16:$src2), 0),
2504 (implicit EFLAGS)]>,
2506 def NEW_TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2507 "test{l}\t{$src2, $src1|$src1, $src2}",
2508 [(X86cmp_new (and GR32:$src1, GR32:$src2), 0),
2509 (implicit EFLAGS)]>;
2512 def NEW_TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2513 "test{b}\t{$src2, $src1|$src1, $src2}",
2514 [(X86cmp_new (and GR8:$src1, (loadi8 addr:$src2)), 0),
2515 (implicit EFLAGS)]>;
2516 def NEW_TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2517 "test{w}\t{$src2, $src1|$src1, $src2}",
2518 [(X86cmp_new (and GR16:$src1, (loadi16 addr:$src2)), 0),
2519 (implicit EFLAGS)]>, OpSize;
2520 def NEW_TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2521 "test{l}\t{$src2, $src1|$src1, $src2}",
2522 [(X86cmp_new (and GR32:$src1, (loadi32 addr:$src2)), 0),
2523 (implicit EFLAGS)]>;
2525 def NEW_TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2526 (outs), (ins GR8:$src1, i8imm:$src2),
2527 "test{b}\t{$src2, $src1|$src1, $src2}",
2528 [(X86cmp_new (and GR8:$src1, imm:$src2), 0),
2529 (implicit EFLAGS)]>;
2530 def NEW_TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2531 (outs), (ins GR16:$src1, i16imm:$src2),
2532 "test{w}\t{$src2, $src1|$src1, $src2}",
2533 [(X86cmp_new (and GR16:$src1, imm:$src2), 0),
2534 (implicit EFLAGS)]>, OpSize;
2535 def NEW_TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2536 (outs), (ins GR32:$src1, i32imm:$src2),
2537 "test{l}\t{$src2, $src1|$src1, $src2}",
2538 [(X86cmp_new (and GR32:$src1, imm:$src2), 0),
2539 (implicit EFLAGS)]>;
2541 def NEW_TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2542 (outs), (ins i8mem:$src1, i8imm:$src2),
2543 "test{b}\t{$src2, $src1|$src1, $src2}",
2544 [(X86cmp_new (and (loadi8 addr:$src1), imm:$src2), 0),
2545 (implicit EFLAGS)]>;
2546 def NEW_TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2547 (outs), (ins i16mem:$src1, i16imm:$src2),
2548 "test{w}\t{$src2, $src1|$src1, $src2}",
2549 [(X86cmp_new (and (loadi16 addr:$src1), imm:$src2), 0),
2550 (implicit EFLAGS)]>, OpSize;
2551 def NEW_TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2552 (outs), (ins i32mem:$src1, i32imm:$src2),
2553 "test{l}\t{$src2, $src1|$src1, $src2}",
2554 [(X86cmp_new (and (loadi32 addr:$src1), imm:$src2), 0),
2555 (implicit EFLAGS)]>;
2556 } // Defs = [EFLAGS]
2559 // Condition code ops, incl. set if equal/not equal/...
2560 let Defs = [EFLAGS], Uses = [AH] in
2561 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2562 let Defs = [AH], Uses = [EFLAGS] in
2563 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2565 let Uses = [EFLAGS] in {
2566 def SETEr : I<0x94, MRM0r,
2567 (outs GR8 :$dst), (ins),
2569 [(set GR8:$dst, (X86setcc X86_COND_E))]>,
2571 def SETEm : I<0x94, MRM0m,
2572 (outs), (ins i8mem:$dst),
2574 [(store (X86setcc X86_COND_E), addr:$dst)]>,
2576 def SETNEr : I<0x95, MRM0r,
2577 (outs GR8 :$dst), (ins),
2579 [(set GR8:$dst, (X86setcc X86_COND_NE))]>,
2581 def SETNEm : I<0x95, MRM0m,
2582 (outs), (ins i8mem:$dst),
2584 [(store (X86setcc X86_COND_NE), addr:$dst)]>,
2586 def SETLr : I<0x9C, MRM0r,
2587 (outs GR8 :$dst), (ins),
2589 [(set GR8:$dst, (X86setcc X86_COND_L))]>,
2590 TB; // GR8 = < signed
2591 def SETLm : I<0x9C, MRM0m,
2592 (outs), (ins i8mem:$dst),
2594 [(store (X86setcc X86_COND_L), addr:$dst)]>,
2595 TB; // [mem8] = < signed
2596 def SETGEr : I<0x9D, MRM0r,
2597 (outs GR8 :$dst), (ins),
2599 [(set GR8:$dst, (X86setcc X86_COND_GE))]>,
2600 TB; // GR8 = >= signed
2601 def SETGEm : I<0x9D, MRM0m,
2602 (outs), (ins i8mem:$dst),
2604 [(store (X86setcc X86_COND_GE), addr:$dst)]>,
2605 TB; // [mem8] = >= signed
2606 def SETLEr : I<0x9E, MRM0r,
2607 (outs GR8 :$dst), (ins),
2609 [(set GR8:$dst, (X86setcc X86_COND_LE))]>,
2610 TB; // GR8 = <= signed
2611 def SETLEm : I<0x9E, MRM0m,
2612 (outs), (ins i8mem:$dst),
2614 [(store (X86setcc X86_COND_LE), addr:$dst)]>,
2615 TB; // [mem8] = <= signed
2616 def SETGr : I<0x9F, MRM0r,
2617 (outs GR8 :$dst), (ins),
2619 [(set GR8:$dst, (X86setcc X86_COND_G))]>,
2620 TB; // GR8 = > signed
2621 def SETGm : I<0x9F, MRM0m,
2622 (outs), (ins i8mem:$dst),
2624 [(store (X86setcc X86_COND_G), addr:$dst)]>,
2625 TB; // [mem8] = > signed
2627 def SETBr : I<0x92, MRM0r,
2628 (outs GR8 :$dst), (ins),
2630 [(set GR8:$dst, (X86setcc X86_COND_B))]>,
2631 TB; // GR8 = < unsign
2632 def SETBm : I<0x92, MRM0m,
2633 (outs), (ins i8mem:$dst),
2635 [(store (X86setcc X86_COND_B), addr:$dst)]>,
2636 TB; // [mem8] = < unsign
2637 def SETAEr : I<0x93, MRM0r,
2638 (outs GR8 :$dst), (ins),
2640 [(set GR8:$dst, (X86setcc X86_COND_AE))]>,
2641 TB; // GR8 = >= unsign
2642 def SETAEm : I<0x93, MRM0m,
2643 (outs), (ins i8mem:$dst),
2645 [(store (X86setcc X86_COND_AE), addr:$dst)]>,
2646 TB; // [mem8] = >= unsign
2647 def SETBEr : I<0x96, MRM0r,
2648 (outs GR8 :$dst), (ins),
2650 [(set GR8:$dst, (X86setcc X86_COND_BE))]>,
2651 TB; // GR8 = <= unsign
2652 def SETBEm : I<0x96, MRM0m,
2653 (outs), (ins i8mem:$dst),
2655 [(store (X86setcc X86_COND_BE), addr:$dst)]>,
2656 TB; // [mem8] = <= unsign
2657 def SETAr : I<0x97, MRM0r,
2658 (outs GR8 :$dst), (ins),
2660 [(set GR8:$dst, (X86setcc X86_COND_A))]>,
2661 TB; // GR8 = > signed
2662 def SETAm : I<0x97, MRM0m,
2663 (outs), (ins i8mem:$dst),
2665 [(store (X86setcc X86_COND_A), addr:$dst)]>,
2666 TB; // [mem8] = > signed
2668 def SETSr : I<0x98, MRM0r,
2669 (outs GR8 :$dst), (ins),
2671 [(set GR8:$dst, (X86setcc X86_COND_S))]>,
2672 TB; // GR8 = <sign bit>
2673 def SETSm : I<0x98, MRM0m,
2674 (outs), (ins i8mem:$dst),
2676 [(store (X86setcc X86_COND_S), addr:$dst)]>,
2677 TB; // [mem8] = <sign bit>
2678 def SETNSr : I<0x99, MRM0r,
2679 (outs GR8 :$dst), (ins),
2681 [(set GR8:$dst, (X86setcc X86_COND_NS))]>,
2682 TB; // GR8 = !<sign bit>
2683 def SETNSm : I<0x99, MRM0m,
2684 (outs), (ins i8mem:$dst),
2686 [(store (X86setcc X86_COND_NS), addr:$dst)]>,
2687 TB; // [mem8] = !<sign bit>
2688 def SETPr : I<0x9A, MRM0r,
2689 (outs GR8 :$dst), (ins),
2691 [(set GR8:$dst, (X86setcc X86_COND_P))]>,
2693 def SETPm : I<0x9A, MRM0m,
2694 (outs), (ins i8mem:$dst),
2696 [(store (X86setcc X86_COND_P), addr:$dst)]>,
2697 TB; // [mem8] = parity
2698 def SETNPr : I<0x9B, MRM0r,
2699 (outs GR8 :$dst), (ins),
2701 [(set GR8:$dst, (X86setcc X86_COND_NP))]>,
2702 TB; // GR8 = not parity
2703 def SETNPm : I<0x9B, MRM0m,
2704 (outs), (ins i8mem:$dst),
2706 [(store (X86setcc X86_COND_NP), addr:$dst)]>,
2707 TB; // [mem8] = not parity
2708 } // Uses = [EFLAGS]
2710 let Uses = [EFLAGS] in {
2711 def NEW_SETEr : I<0x94, MRM0r,
2712 (outs GR8 :$dst), (ins),
2714 [(set GR8:$dst, (X86setcc_new X86_COND_E, EFLAGS))]>,
2716 def NEW_SETEm : I<0x94, MRM0m,
2717 (outs), (ins i8mem:$dst),
2719 [(store (X86setcc_new X86_COND_E, EFLAGS), addr:$dst)]>,
2721 def NEW_SETNEr : I<0x95, MRM0r,
2722 (outs GR8 :$dst), (ins),
2724 [(set GR8:$dst, (X86setcc_new X86_COND_NE, EFLAGS))]>,
2726 def NEW_SETNEm : I<0x95, MRM0m,
2727 (outs), (ins i8mem:$dst),
2729 [(store (X86setcc_new X86_COND_NE, EFLAGS), addr:$dst)]>,
2731 def NEW_SETLr : I<0x9C, MRM0r,
2732 (outs GR8 :$dst), (ins),
2734 [(set GR8:$dst, (X86setcc_new X86_COND_L, EFLAGS))]>,
2735 TB; // GR8 = < signed
2736 def NEW_SETLm : I<0x9C, MRM0m,
2737 (outs), (ins i8mem:$dst),
2739 [(store (X86setcc_new X86_COND_L, EFLAGS), addr:$dst)]>,
2740 TB; // [mem8] = < signed
2741 def NEW_SETGEr : I<0x9D, MRM0r,
2742 (outs GR8 :$dst), (ins),
2744 [(set GR8:$dst, (X86setcc_new X86_COND_GE, EFLAGS))]>,
2745 TB; // GR8 = >= signed
2746 def NEW_SETGEm : I<0x9D, MRM0m,
2747 (outs), (ins i8mem:$dst),
2749 [(store (X86setcc_new X86_COND_GE, EFLAGS), addr:$dst)]>,
2750 TB; // [mem8] = >= signed
2751 def NEW_SETLEr : I<0x9E, MRM0r,
2752 (outs GR8 :$dst), (ins),
2754 [(set GR8:$dst, (X86setcc_new X86_COND_LE, EFLAGS))]>,
2755 TB; // GR8 = <= signed
2756 def NEW_SETLEm : I<0x9E, MRM0m,
2757 (outs), (ins i8mem:$dst),
2759 [(store (X86setcc_new X86_COND_LE, EFLAGS), addr:$dst)]>,
2760 TB; // [mem8] = <= signed
2761 def NEW_SETGr : I<0x9F, MRM0r,
2762 (outs GR8 :$dst), (ins),
2764 [(set GR8:$dst, (X86setcc_new X86_COND_G, EFLAGS))]>,
2765 TB; // GR8 = > signed
2766 def NEW_SETGm : I<0x9F, MRM0m,
2767 (outs), (ins i8mem:$dst),
2769 [(store (X86setcc_new X86_COND_G, EFLAGS), addr:$dst)]>,
2770 TB; // [mem8] = > signed
2772 def NEW_SETBr : I<0x92, MRM0r,
2773 (outs GR8 :$dst), (ins),
2775 [(set GR8:$dst, (X86setcc_new X86_COND_B, EFLAGS))]>,
2776 TB; // GR8 = < unsign
2777 def NEW_SETBm : I<0x92, MRM0m,
2778 (outs), (ins i8mem:$dst),
2780 [(store (X86setcc_new X86_COND_B, EFLAGS), addr:$dst)]>,
2781 TB; // [mem8] = < unsign
2782 def NEW_SETAEr : I<0x93, MRM0r,
2783 (outs GR8 :$dst), (ins),
2785 [(set GR8:$dst, (X86setcc_new X86_COND_AE, EFLAGS))]>,
2786 TB; // GR8 = >= unsign
2787 def NEW_SETAEm : I<0x93, MRM0m,
2788 (outs), (ins i8mem:$dst),
2790 [(store (X86setcc_new X86_COND_AE, EFLAGS), addr:$dst)]>,
2791 TB; // [mem8] = >= unsign
2792 def NEW_SETBEr : I<0x96, MRM0r,
2793 (outs GR8 :$dst), (ins),
2795 [(set GR8:$dst, (X86setcc_new X86_COND_BE, EFLAGS))]>,
2796 TB; // GR8 = <= unsign
2797 def NEW_SETBEm : I<0x96, MRM0m,
2798 (outs), (ins i8mem:$dst),
2800 [(store (X86setcc_new X86_COND_BE, EFLAGS), addr:$dst)]>,
2801 TB; // [mem8] = <= unsign
2802 def NEW_SETAr : I<0x97, MRM0r,
2803 (outs GR8 :$dst), (ins),
2805 [(set GR8:$dst, (X86setcc_new X86_COND_A, EFLAGS))]>,
2806 TB; // GR8 = > signed
2807 def NEW_SETAm : I<0x97, MRM0m,
2808 (outs), (ins i8mem:$dst),
2810 [(store (X86setcc_new X86_COND_A, EFLAGS), addr:$dst)]>,
2811 TB; // [mem8] = > signed
2813 def NEW_SETSr : I<0x98, MRM0r,
2814 (outs GR8 :$dst), (ins),
2816 [(set GR8:$dst, (X86setcc_new X86_COND_S, EFLAGS))]>,
2817 TB; // GR8 = <sign bit>
2818 def NEW_SETSm : I<0x98, MRM0m,
2819 (outs), (ins i8mem:$dst),
2821 [(store (X86setcc_new X86_COND_S, EFLAGS), addr:$dst)]>,
2822 TB; // [mem8] = <sign bit>
2823 def NEW_SETNSr : I<0x99, MRM0r,
2824 (outs GR8 :$dst), (ins),
2826 [(set GR8:$dst, (X86setcc_new X86_COND_NS, EFLAGS))]>,
2827 TB; // GR8 = !<sign bit>
2828 def NEW_SETNSm : I<0x99, MRM0m,
2829 (outs), (ins i8mem:$dst),
2831 [(store (X86setcc_new X86_COND_NS, EFLAGS), addr:$dst)]>,
2832 TB; // [mem8] = !<sign bit>
2833 def NEW_SETPr : I<0x9A, MRM0r,
2834 (outs GR8 :$dst), (ins),
2836 [(set GR8:$dst, (X86setcc_new X86_COND_P, EFLAGS))]>,
2838 def NEW_SETPm : I<0x9A, MRM0m,
2839 (outs), (ins i8mem:$dst),
2841 [(store (X86setcc_new X86_COND_P, EFLAGS), addr:$dst)]>,
2842 TB; // [mem8] = parity
2843 def NEW_SETNPr : I<0x9B, MRM0r,
2844 (outs GR8 :$dst), (ins),
2846 [(set GR8:$dst, (X86setcc_new X86_COND_NP, EFLAGS))]>,
2847 TB; // GR8 = not parity
2848 def NEW_SETNPm : I<0x9B, MRM0m,
2849 (outs), (ins i8mem:$dst),
2851 [(store (X86setcc_new X86_COND_NP, EFLAGS), addr:$dst)]>,
2852 TB; // [mem8] = not parity
2853 } // Uses = [EFLAGS]
2856 //def : Pat<(X86setcc_new X86_COND_E, EFLAGS), (SETEr)>;
2858 // Integer comparisons
2859 let Defs = [EFLAGS] in {
2860 def CMP8rr : I<0x38, MRMDestReg,
2861 (outs), (ins GR8 :$src1, GR8 :$src2),
2862 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2863 [(X86cmp GR8:$src1, GR8:$src2)]>;
2864 def CMP16rr : I<0x39, MRMDestReg,
2865 (outs), (ins GR16:$src1, GR16:$src2),
2866 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2867 [(X86cmp GR16:$src1, GR16:$src2)]>, OpSize;
2868 def CMP32rr : I<0x39, MRMDestReg,
2869 (outs), (ins GR32:$src1, GR32:$src2),
2870 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2871 [(X86cmp GR32:$src1, GR32:$src2)]>;
2872 def CMP8mr : I<0x38, MRMDestMem,
2873 (outs), (ins i8mem :$src1, GR8 :$src2),
2874 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2875 [(X86cmp (loadi8 addr:$src1), GR8:$src2)]>;
2876 def CMP16mr : I<0x39, MRMDestMem,
2877 (outs), (ins i16mem:$src1, GR16:$src2),
2878 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2879 [(X86cmp (loadi16 addr:$src1), GR16:$src2)]>, OpSize;
2880 def CMP32mr : I<0x39, MRMDestMem,
2881 (outs), (ins i32mem:$src1, GR32:$src2),
2882 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2883 [(X86cmp (loadi32 addr:$src1), GR32:$src2)]>;
2884 def CMP8rm : I<0x3A, MRMSrcMem,
2885 (outs), (ins GR8 :$src1, i8mem :$src2),
2886 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2887 [(X86cmp GR8:$src1, (loadi8 addr:$src2))]>;
2888 def CMP16rm : I<0x3B, MRMSrcMem,
2889 (outs), (ins GR16:$src1, i16mem:$src2),
2890 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2891 [(X86cmp GR16:$src1, (loadi16 addr:$src2))]>, OpSize;
2892 def CMP32rm : I<0x3B, MRMSrcMem,
2893 (outs), (ins GR32:$src1, i32mem:$src2),
2894 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2895 [(X86cmp GR32:$src1, (loadi32 addr:$src2))]>;
2896 def CMP8ri : Ii8<0x80, MRM7r,
2897 (outs), (ins GR8:$src1, i8imm:$src2),
2898 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2899 [(X86cmp GR8:$src1, imm:$src2)]>;
2900 def CMP16ri : Ii16<0x81, MRM7r,
2901 (outs), (ins GR16:$src1, i16imm:$src2),
2902 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2903 [(X86cmp GR16:$src1, imm:$src2)]>, OpSize;
2904 def CMP32ri : Ii32<0x81, MRM7r,
2905 (outs), (ins GR32:$src1, i32imm:$src2),
2906 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2907 [(X86cmp GR32:$src1, imm:$src2)]>;
2908 def CMP8mi : Ii8 <0x80, MRM7m,
2909 (outs), (ins i8mem :$src1, i8imm :$src2),
2910 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2911 [(X86cmp (loadi8 addr:$src1), imm:$src2)]>;
2912 def CMP16mi : Ii16<0x81, MRM7m,
2913 (outs), (ins i16mem:$src1, i16imm:$src2),
2914 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2915 [(X86cmp (loadi16 addr:$src1), imm:$src2)]>, OpSize;
2916 def CMP32mi : Ii32<0x81, MRM7m,
2917 (outs), (ins i32mem:$src1, i32imm:$src2),
2918 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2919 [(X86cmp (loadi32 addr:$src1), imm:$src2)]>;
2920 def CMP16ri8 : Ii8<0x83, MRM7r,
2921 (outs), (ins GR16:$src1, i16i8imm:$src2),
2922 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2923 [(X86cmp GR16:$src1, i16immSExt8:$src2)]>, OpSize;
2924 def CMP16mi8 : Ii8<0x83, MRM7m,
2925 (outs), (ins i16mem:$src1, i16i8imm:$src2),
2926 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2927 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2)]>, OpSize;
2928 def CMP32mi8 : Ii8<0x83, MRM7m,
2929 (outs), (ins i32mem:$src1, i32i8imm:$src2),
2930 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2931 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2)]>;
2932 def CMP32ri8 : Ii8<0x83, MRM7r,
2933 (outs), (ins GR32:$src1, i32i8imm:$src2),
2934 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2935 [(X86cmp GR32:$src1, i32immSExt8:$src2)]>;
2936 } // Defs = [EFLAGS]
2938 let Defs = [EFLAGS] in {
2939 def NEW_CMP8rr : I<0x38, MRMDestReg,
2940 (outs), (ins GR8 :$src1, GR8 :$src2),
2941 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2942 [(X86cmp_new GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2943 def NEW_CMP16rr : I<0x39, MRMDestReg,
2944 (outs), (ins GR16:$src1, GR16:$src2),
2945 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2946 [(X86cmp_new GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
2947 def NEW_CMP32rr : I<0x39, MRMDestReg,
2948 (outs), (ins GR32:$src1, GR32:$src2),
2949 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2950 [(X86cmp_new GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
2951 def NEW_CMP8mr : I<0x38, MRMDestMem,
2952 (outs), (ins i8mem :$src1, GR8 :$src2),
2953 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2954 [(X86cmp_new (loadi8 addr:$src1), GR8:$src2),
2955 (implicit EFLAGS)]>;
2956 def NEW_CMP16mr : I<0x39, MRMDestMem,
2957 (outs), (ins i16mem:$src1, GR16:$src2),
2958 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2959 [(X86cmp_new (loadi16 addr:$src1), GR16:$src2),
2960 (implicit EFLAGS)]>, OpSize;
2961 def NEW_CMP32mr : I<0x39, MRMDestMem,
2962 (outs), (ins i32mem:$src1, GR32:$src2),
2963 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2964 [(X86cmp_new (loadi32 addr:$src1), GR32:$src2),
2965 (implicit EFLAGS)]>;
2966 def NEW_CMP8rm : I<0x3A, MRMSrcMem,
2967 (outs), (ins GR8 :$src1, i8mem :$src2),
2968 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2969 [(X86cmp_new GR8:$src1, (loadi8 addr:$src2)),
2970 (implicit EFLAGS)]>;
2971 def NEW_CMP16rm : I<0x3B, MRMSrcMem,
2972 (outs), (ins GR16:$src1, i16mem:$src2),
2973 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2974 [(X86cmp_new GR16:$src1, (loadi16 addr:$src2)),
2975 (implicit EFLAGS)]>, OpSize;
2976 def NEW_CMP32rm : I<0x3B, MRMSrcMem,
2977 (outs), (ins GR32:$src1, i32mem:$src2),
2978 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2979 [(X86cmp_new GR32:$src1, (loadi32 addr:$src2)),
2980 (implicit EFLAGS)]>;
2981 def NEW_CMP8ri : Ii8<0x80, MRM7r,
2982 (outs), (ins GR8:$src1, i8imm:$src2),
2983 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2984 [(X86cmp_new GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
2985 def NEW_CMP16ri : Ii16<0x81, MRM7r,
2986 (outs), (ins GR16:$src1, i16imm:$src2),
2987 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2988 [(X86cmp_new GR16:$src1, imm:$src2),
2989 (implicit EFLAGS)]>, OpSize;
2990 def NEW_CMP32ri : Ii32<0x81, MRM7r,
2991 (outs), (ins GR32:$src1, i32imm:$src2),
2992 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2993 [(X86cmp_new GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
2994 def NEW_CMP8mi : Ii8 <0x80, MRM7m,
2995 (outs), (ins i8mem :$src1, i8imm :$src2),
2996 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2997 [(X86cmp_new (loadi8 addr:$src1), imm:$src2),
2998 (implicit EFLAGS)]>;
2999 def NEW_CMP16mi : Ii16<0x81, MRM7m,
3000 (outs), (ins i16mem:$src1, i16imm:$src2),
3001 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3002 [(X86cmp_new (loadi16 addr:$src1), imm:$src2),
3003 (implicit EFLAGS)]>, OpSize;
3004 def NEW_CMP32mi : Ii32<0x81, MRM7m,
3005 (outs), (ins i32mem:$src1, i32imm:$src2),
3006 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3007 [(X86cmp_new (loadi32 addr:$src1), imm:$src2),
3008 (implicit EFLAGS)]>;
3009 def NEW_CMP16ri8 : Ii8<0x83, MRM7r,
3010 (outs), (ins GR16:$src1, i16i8imm:$src2),
3011 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3012 [(X86cmp_new GR16:$src1, i16immSExt8:$src2),
3013 (implicit EFLAGS)]>, OpSize;
3014 def NEW_CMP16mi8 : Ii8<0x83, MRM7m,
3015 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3016 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3017 [(X86cmp_new (loadi16 addr:$src1), i16immSExt8:$src2),
3018 (implicit EFLAGS)]>, OpSize;
3019 def NEW_CMP32mi8 : Ii8<0x83, MRM7m,
3020 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3021 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3022 [(X86cmp_new (loadi32 addr:$src1), i32immSExt8:$src2),
3023 (implicit EFLAGS)]>;
3024 def NEW_CMP32ri8 : Ii8<0x83, MRM7r,
3025 (outs), (ins GR32:$src1, i32i8imm:$src2),
3026 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3027 [(X86cmp_new GR32:$src1, i32immSExt8:$src2),
3028 (implicit EFLAGS)]>;
3029 } // Defs = [EFLAGS]
3031 // Sign/Zero extenders
3032 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3033 "movs{bw|x}\t{$src, $dst|$dst, $src}",
3034 [(set GR16:$dst, (sext GR8:$src))]>, TB, OpSize;
3035 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3036 "movs{bw|x}\t{$src, $dst|$dst, $src}",
3037 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize;
3038 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3039 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3040 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3041 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3042 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3043 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3044 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3045 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3046 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3047 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3048 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3049 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3051 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3052 "movz{bw|x}\t{$src, $dst|$dst, $src}",
3053 [(set GR16:$dst, (zext GR8:$src))]>, TB, OpSize;
3054 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3055 "movz{bw|x}\t{$src, $dst|$dst, $src}",
3056 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize;
3057 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3058 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3059 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3060 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3061 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3062 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3063 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3064 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3065 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3066 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3067 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3068 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3070 let Defs = [AX], Uses = [AL] in
3071 def CBW : I<0x98, RawFrm, (outs), (ins),
3072 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3073 let Defs = [EAX], Uses = [AX] in
3074 def CWDE : I<0x98, RawFrm, (outs), (ins),
3075 "{cwtl|cwde}", []>; // EAX = signext(AX)
3077 let Defs = [AX,DX], Uses = [AX] in
3078 def CWD : I<0x99, RawFrm, (outs), (ins),
3079 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3080 let Defs = [EAX,EDX], Uses = [EAX] in
3081 def CDQ : I<0x99, RawFrm, (outs), (ins),
3082 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3085 //===----------------------------------------------------------------------===//
3086 // Alias Instructions
3087 //===----------------------------------------------------------------------===//
3089 // Alias instructions that map movr0 to xor.
3090 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3091 let Defs = [EFLAGS], isReMaterializable = 1 in {
3092 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
3093 "xor{b}\t$dst, $dst",
3094 [(set GR8:$dst, 0)]>;
3095 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3096 "xor{w}\t$dst, $dst",
3097 [(set GR16:$dst, 0)]>, OpSize;
3098 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
3099 "xor{l}\t$dst, $dst",
3100 [(set GR32:$dst, 0)]>;
3103 // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
3104 // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
3105 def MOV16to16_ : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16:$src),
3106 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
3107 def MOV32to32_ : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32:$src),
3108 "mov{l}\t{$src, $dst|$dst, $src}", []>;
3110 def MOV16_rr : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16_:$src),
3111 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
3112 def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src),
3113 "mov{l}\t{$src, $dst|$dst, $src}", []>;
3115 def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src),
3116 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
3117 def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src),
3118 "mov{l}\t{$src, $dst|$dst, $src}", []>;
3120 def MOV16_mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16_:$src),
3121 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
3122 def MOV32_mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32_:$src),
3123 "mov{l}\t{$src, $dst|$dst, $src}", []>;
3125 //===----------------------------------------------------------------------===//
3126 // Thread Local Storage Instructions
3130 def TLS_addr : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
3131 "leal\t${sym:mem}(,%ebx,1), $dst",
3132 [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
3134 let AddedComplexity = 10 in
3135 def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
3136 "movl\t%gs:($src), $dst",
3137 [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
3139 let AddedComplexity = 15 in
3140 def TLS_gs_ri : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
3141 "movl\t%gs:${src:mem}, $dst",
3143 (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>;
3145 def TLS_tp : I<0, Pseudo, (outs GR32:$dst), (ins),
3146 "movl\t%gs:0, $dst",
3147 [(set GR32:$dst, X86TLStp)]>;
3149 //===----------------------------------------------------------------------===//
3150 // DWARF Pseudo Instructions
3153 def DWARF_LOC : I<0, Pseudo, (outs),
3154 (ins i32imm:$line, i32imm:$col, i32imm:$file),
3155 ".loc\t${file:debug} ${line:debug} ${col:debug}",
3156 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
3159 //===----------------------------------------------------------------------===//
3160 // EH Pseudo Instructions
3162 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3164 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3165 "ret\t#eh_return, addr: $addr",
3166 [(X86ehret GR32:$addr)]>;
3170 //===----------------------------------------------------------------------===//
3171 // Non-Instruction Patterns
3172 //===----------------------------------------------------------------------===//
3174 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
3175 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
3176 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
3177 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)), (MOV32ri tglobaltlsaddr:$dst)>;
3178 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
3179 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
3181 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
3182 (ADD32ri GR32:$src1, tconstpool:$src2)>;
3183 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
3184 (ADD32ri GR32:$src1, tjumptable:$src2)>;
3185 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
3186 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
3187 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
3188 (ADD32ri GR32:$src1, texternalsym:$src2)>;
3190 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
3191 (MOV32mi addr:$dst, tglobaladdr:$src)>;
3192 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
3193 (MOV32mi addr:$dst, texternalsym:$src)>;
3196 def : Pat<(X86tailcall GR32:$dst),
3197 (CALL32r GR32:$dst)>;
3199 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
3200 (CALLpcrel32 tglobaladdr:$dst)>;
3201 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
3202 (CALLpcrel32 texternalsym:$dst)>;
3204 def : Pat<(X86call (i32 tglobaladdr:$dst)),
3205 (CALLpcrel32 tglobaladdr:$dst)>;
3206 def : Pat<(X86call (i32 texternalsym:$dst)),
3207 (CALLpcrel32 texternalsym:$dst)>;
3209 // X86 specific add which produces a flag.
3210 def : Pat<(addc GR32:$src1, GR32:$src2),
3211 (ADD32rr GR32:$src1, GR32:$src2)>;
3212 def : Pat<(addc GR32:$src1, (load addr:$src2)),
3213 (ADD32rm GR32:$src1, addr:$src2)>;
3214 def : Pat<(addc GR32:$src1, imm:$src2),
3215 (ADD32ri GR32:$src1, imm:$src2)>;
3216 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
3217 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3219 def : Pat<(subc GR32:$src1, GR32:$src2),
3220 (SUB32rr GR32:$src1, GR32:$src2)>;
3221 def : Pat<(subc GR32:$src1, (load addr:$src2)),
3222 (SUB32rm GR32:$src1, addr:$src2)>;
3223 def : Pat<(subc GR32:$src1, imm:$src2),
3224 (SUB32ri GR32:$src1, imm:$src2)>;
3225 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
3226 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3228 def : Pat<(truncstorei1 (i8 imm:$src), addr:$dst),
3229 (MOV8mi addr:$dst, imm:$src)>;
3230 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
3231 (MOV8mr addr:$dst, GR8:$src)>;
3235 // TEST R,R is smaller than CMP R,0
3236 def : Pat<(X86cmp GR8:$src1, 0),
3237 (TEST8rr GR8:$src1, GR8:$src1)>;
3238 def : Pat<(X86cmp GR16:$src1, 0),
3239 (TEST16rr GR16:$src1, GR16:$src1)>;
3240 def : Pat<(X86cmp GR32:$src1, 0),
3241 (TEST32rr GR32:$src1, GR32:$src1)>;
3243 def : Pat<(parallel (X86cmp_new GR8:$src1, 0), (implicit EFLAGS)),
3244 (NEW_TEST8rr GR8:$src1, GR8:$src1)>;
3245 def : Pat<(parallel (X86cmp_new GR16:$src1, 0), (implicit EFLAGS)),
3246 (NEW_TEST16rr GR16:$src1, GR16:$src1)>;
3247 def : Pat<(parallel (X86cmp_new GR32:$src1, 0), (implicit EFLAGS)),
3248 (NEW_TEST32rr GR32:$src1, GR32:$src1)>;
3250 // {s|z}extload bool -> {s|z}extload byte
3251 def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>;
3252 def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>;
3253 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3254 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3255 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3257 // extload bool -> extload byte
3258 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3259 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3260 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3261 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
3262 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
3263 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
3266 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
3267 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
3268 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
3269 def : Pat<(i16 (anyext (loadi8 addr:$src))), (MOVZX16rm8 addr:$src)>;
3270 def : Pat<(i32 (anyext (loadi8 addr:$src))), (MOVZX32rm8 addr:$src)>;
3271 def : Pat<(i32 (anyext (loadi16 addr:$src))), (MOVZX32rm16 addr:$src)>;
3273 //===----------------------------------------------------------------------===//
3275 //===----------------------------------------------------------------------===//
3277 // (shl x, 1) ==> (add x, x)
3278 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
3279 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
3280 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
3282 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
3283 def : Pat<(or (srl GR32:$src1, CL:$amt),
3284 (shl GR32:$src2, (sub 32, CL:$amt))),
3285 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3287 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
3288 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3289 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3291 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
3292 def : Pat<(or (shl GR32:$src1, CL:$amt),
3293 (srl GR32:$src2, (sub 32, CL:$amt))),
3294 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3296 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
3297 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3298 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3300 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
3301 def : Pat<(or (srl GR16:$src1, CL:$amt),
3302 (shl GR16:$src2, (sub 16, CL:$amt))),
3303 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3305 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
3306 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3307 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3309 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
3310 def : Pat<(or (shl GR16:$src1, CL:$amt),
3311 (srl GR16:$src2, (sub 16, CL:$amt))),
3312 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3314 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
3315 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3316 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3319 //===----------------------------------------------------------------------===//
3320 // Floating Point Stack Support
3321 //===----------------------------------------------------------------------===//
3323 include "X86InstrFPStack.td"
3325 //===----------------------------------------------------------------------===//
3327 //===----------------------------------------------------------------------===//
3329 include "X86InstrX86-64.td"
3331 //===----------------------------------------------------------------------===//
3332 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
3333 //===----------------------------------------------------------------------===//
3335 include "X86InstrMMX.td"
3337 //===----------------------------------------------------------------------===//
3338 // XMM Floating point support (requires SSE / SSE2)
3339 //===----------------------------------------------------------------------===//
3341 include "X86InstrSSE.td"