1 //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Format specifies the encoding used by the instruction. This is part of the
17 // ad-hoc solution used to emit machine instruction encodings by our machine
19 class Format<bits<5> val> {
23 def Pseudo : Format<0>; def RawFrm : Format<1>;
24 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
25 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
26 def MRMSrcMem : Format<6>;
27 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
28 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
29 def MRM6r : Format<22>; def MRM7r : Format<23>;
30 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
31 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
32 def MRM6m : Format<30>; def MRM7m : Format<31>;
34 // ImmType - This specifies the immediate type used by an instruction. This is
35 // part of the ad-hoc solution used to emit machine instruction encodings by our
36 // machine code emitter.
37 class ImmType<bits<2> val> {
40 def NoImm : ImmType<0>;
41 def Imm8 : ImmType<1>;
42 def Imm16 : ImmType<2>;
43 def Imm32 : ImmType<3>;
45 // MemType - This specifies the immediate type used by an instruction. This is
46 // part of the ad-hoc solution used to emit machine instruction encodings by our
47 // machine code emitter.
48 class MemType<bits<3> val> {
51 def NoMem : MemType<0>;
52 def Mem8 : MemType<1>;
53 def Mem16 : MemType<2>;
54 def Mem32 : MemType<3>;
55 def Mem64 : MemType<4>;
56 def Mem80 : MemType<5>;
57 def Mem128 : MemType<6>;
59 // FPFormat - This specifies what form this FP instruction has. This is used by
60 // the Floating-Point stackifier pass.
61 class FPFormat<bits<3> val> {
64 def NotFP : FPFormat<0>;
65 def ZeroArgFP : FPFormat<1>;
66 def OneArgFP : FPFormat<2>;
67 def OneArgFPRW : FPFormat<3>;
68 def TwoArgFP : FPFormat<4>;
69 def CompareFP : FPFormat<5>;
70 def CondMovFP : FPFormat<6>;
71 def SpecialFP : FPFormat<7>;
74 class X86Inst<string nam, bits<8> opcod, Format f, MemType m, ImmType i> : Instruction {
75 let Namespace = "X86";
78 bits<8> Opcode = opcod;
80 bits<5> FormBits = Form.Value;
82 bits<3> MemTypeBits = MemT.Value;
84 bits<2> ImmTypeBits = ImmT.Value;
87 // Attributes specific to X86 instructions...
89 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
91 // Flag whether implicit register usage is printed before/after the
93 bit printImplicitUsesBefore = 0;
94 bit printImplicitUsesAfter = 0;
96 // Flag whether implicit register definitions are printed before/after the
98 bit printImplicitDefsBefore = 0;
99 bit printImplicitDefsAfter = 0;
101 bits<4> Prefix = 0; // Which prefix byte does this inst have?
102 FPFormat FPForm; // What flavor of FP instruction is this?
103 bits<3> FPFormBits = 0;
106 class Imp<list<Register> uses, list<Register> defs> {
107 list<Register> Uses = uses;
108 list<Register> Defs = defs;
111 // II - InstructionInfo - this will eventually replace the I class.
112 class II<dag ops, string AsmStr> {
113 dag OperandList = ops;
114 string AsmString = AsmStr;
118 // Prefix byte classes which are used to indicate to the ad-hoc machine code
119 // emitter that various prefix bytes are required.
120 class OpSize { bit hasOpSizePrefix = 1; }
121 class TB { bits<4> Prefix = 1; }
122 class REP { bits<4> Prefix = 2; }
123 class D8 { bits<4> Prefix = 3; }
124 class D9 { bits<4> Prefix = 4; }
125 class DA { bits<4> Prefix = 5; }
126 class DB { bits<4> Prefix = 6; }
127 class DC { bits<4> Prefix = 7; }
128 class DD { bits<4> Prefix = 8; }
129 class DE { bits<4> Prefix = 9; }
130 class DF { bits<4> Prefix = 10; }
133 //===----------------------------------------------------------------------===//
134 // Instruction templates...
136 class I<string n, bits<8> o, Format f> : X86Inst<n, o, f, NoMem, NoImm>;
138 class Im<string n, bits<8> o, Format f, MemType m> : X86Inst<n, o, f, m, NoImm>;
139 class Im8 <string n, bits<8> o, Format f> : Im<n, o, f, Mem8 >;
140 class Im16<string n, bits<8> o, Format f> : Im<n, o, f, Mem16>;
141 class Im32<string n, bits<8> o, Format f> : Im<n, o, f, Mem32>;
143 class Ii<string n, bits<8> o, Format f, ImmType i> : X86Inst<n, o, f, NoMem, i>;
144 class Ii8 <string n, bits<8> o, Format f> : Ii<n, o, f, Imm8 >;
145 class Ii16<string n, bits<8> o, Format f> : Ii<n, o, f, Imm16>;
146 class Ii32<string n, bits<8> o, Format f> : Ii<n, o, f, Imm32>;
148 class Im8i8 <string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem8 , Imm8 >;
149 class Im16i16<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem16, Imm16>;
150 class Im32i32<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem32, Imm32>;
152 class Im16i8<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem16, Imm8>;
153 class Im32i8<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem32, Imm8>;
155 // Helper for shift instructions
156 class UsesCL { list<Register> Uses = [CL]; bit printImplicitUsesAfter = 1; }
158 //===----------------------------------------------------------------------===//
159 // Instruction list...
162 def PHI : I<"PHI", 0, Pseudo>; // PHI node...
163 def NOOP : I<"nop", 0x90, RawFrm>, // nop
166 def ADJCALLSTACKDOWN : I<"ADJCALLSTACKDOWN", 0, Pseudo>;
167 def ADJCALLSTACKUP : I<"ADJCALLSTACKUP", 0, Pseudo>;
168 def IMPLICIT_USE : I<"IMPLICIT_USE", 0, Pseudo>;
169 def IMPLICIT_DEF : I<"IMPLICIT_DEF", 0, Pseudo>;
170 let isTerminator = 1 in
171 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
172 def FP_REG_KILL : I<"FP_REG_KILL", 0, Pseudo>;
174 //===----------------------------------------------------------------------===//
175 // Control Flow Instructions...
178 // Return instruction...
179 let isTerminator = 1, isReturn = 1, isBarrier = 1 in
180 def RET : I<"ret", 0xC3, RawFrm>,
183 // All branches are RawFrm, Void, Branch, and Terminators
184 let isBranch = 1, isTerminator = 1 in
185 class IBr<string name, bits<8> opcode> : I<name, opcode, RawFrm>;
188 def JMP : IBr<"jmp", 0xE9>;
189 def JB : IBr<"jb" , 0x82>, TB;
190 def JAE : IBr<"jae", 0x83>, TB;
191 def JE : IBr<"je" , 0x84>, TB;
192 def JNE : IBr<"jne", 0x85>, TB;
193 def JBE : IBr<"jbe", 0x86>, TB;
194 def JA : IBr<"ja" , 0x87>, TB;
195 def JS : IBr<"js" , 0x88>, TB;
196 def JNS : IBr<"jns", 0x89>, TB;
197 def JL : IBr<"jl" , 0x8C>, TB;
198 def JGE : IBr<"jge", 0x8D>, TB;
199 def JLE : IBr<"jle", 0x8E>, TB;
200 def JG : IBr<"jg" , 0x8F>, TB;
203 //===----------------------------------------------------------------------===//
204 // Call Instructions...
207 // All calls clobber the non-callee saved registers...
208 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6] in {
209 def CALLpcrel32 : I <"call", 0xE8, RawFrm>;
210 def CALL32r : I <"call", 0xFF, MRM2r>;
211 def CALL32m : Im32<"call", 0xFF, MRM2m>;
215 //===----------------------------------------------------------------------===//
216 // Miscellaneous Instructions...
218 def LEAVE : I<"leave", 0xC9, RawFrm>, Imp<[EBP,ESP],[EBP,ESP]>,
220 def POP32r : I<"pop", 0x58, AddRegFrm>, Imp<[ESP],[ESP]>;
222 let isTwoAddress = 1 in // R32 = bswap R32
223 def BSWAP32r : I<"bswap", 0xC8, AddRegFrm>, TB;
225 def XCHG8rr : I <"xchg", 0x86, MRMDestReg>; // xchg R8, R8
226 def XCHG16rr : I <"xchg", 0x87, MRMDestReg>, OpSize; // xchg R16, R16
227 def XCHG32rr : I <"xchg", 0x87, MRMDestReg>; // xchg R32, R32
228 def XCHG8mr : Im8 <"xchg", 0x86, MRMDestMem>; // xchg [mem8], R8
229 def XCHG16mr : Im16<"xchg", 0x87, MRMDestMem>, OpSize; // xchg [mem16], R16
230 def XCHG32mr : Im32<"xchg", 0x87, MRMDestMem>; // xchg [mem32], R32
231 def XCHG8rm : Im8 <"xchg", 0x86, MRMSrcMem >; // xchg R8, [mem8]
232 def XCHG16rm : Im16<"xchg", 0x87, MRMSrcMem >, OpSize; // xchg R16, [mem16]
233 def XCHG32rm : Im32<"xchg", 0x87, MRMSrcMem >; // xchg R32, [mem32]
235 def LEA16r : Im32<"lea", 0x8D, MRMSrcMem>, OpSize; // R16 = lea [mem]
236 def LEA32r : Im32<"lea", 0x8D, MRMSrcMem>; // R32 = lea [mem]
239 def REP_MOVSB : I<"rep movsb", 0xA4, RawFrm>, REP,
240 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>,
241 II<(ops), "rep movsb">;
242 def REP_MOVSW : I<"rep movsw", 0xA5, RawFrm>, REP, OpSize,
243 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>,
244 II<(ops), "rep movsw">;
245 def REP_MOVSD : I<"rep movsd", 0xA5, RawFrm>, REP,
246 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>,
247 II<(ops), "rep movsd">;
249 def REP_STOSB : I<"rep stosb", 0xAA, RawFrm>, REP,
250 Imp<[AL,ECX,EDI], [ECX,EDI]>,
251 II<(ops), "rep stosb">;
252 def REP_STOSW : I<"rep stosw", 0xAB, RawFrm>, REP, OpSize,
253 Imp<[AX,ECX,EDI], [ECX,EDI]>,
254 II<(ops), "rep stosw">;
255 def REP_STOSD : I<"rep stosd", 0xAB, RawFrm>, REP,
256 Imp<[EAX,ECX,EDI], [ECX,EDI]>,
257 II<(ops), "rep stosd">;
259 //===----------------------------------------------------------------------===//
260 // Input/Output Instructions...
262 def IN8rr : I<"in", 0xEC, RawFrm>, Imp<[DX], [AL]>, // AL = in I/O address DX
263 II<(ops), "in AL, DX">;
264 def IN16rr : I<"in", 0xED, RawFrm>, Imp<[DX], [AX]>, OpSize, // AX = in I/O address DX
265 II<(ops), "in AX, DX">;
266 def IN32rr : I<"in", 0xED, RawFrm>, Imp<[DX],[EAX]>, // EAX = in I/O address DX
267 II<(ops), "in EAX, DX">;
269 let printImplicitDefsBefore = 1 in {
270 def IN8ri : Ii16<"in", 0xE4, RawFrm>, Imp<[], [AL]>; // AL = in [I/O address]
271 def IN16ri : Ii16<"in", 0xE5, RawFrm>, Imp<[], [AX]>, OpSize; // AX = in [I/O address]
272 def IN32ri : Ii16<"in", 0xE5, RawFrm>, Imp<[],[EAX]>; // EAX = in [I/O address]
275 let printImplicitUsesAfter = 1 in {
276 def OUT8rr : I<"out", 0xEE, RawFrm>, Imp<[DX, AL], []>,
277 II<(ops), "out DX, AL">;
278 def OUT16rr : I<"out", 0xEF, RawFrm>, Imp<[DX, AX], []>, OpSize,
279 II<(ops), "out DX, AX">;
280 def OUT32rr : I<"out", 0xEF, RawFrm>, Imp<[DX, EAX], []>,
281 II<(ops), "out DX, EAX">;
282 def OUT8ir : Ii16<"out", 0xE6, RawFrm>, Imp<[AL], []>;
283 def OUT16ir : Ii16<"out", 0xE7, RawFrm>, Imp<[AX], []>, OpSize;
284 def OUT32ir : Ii16<"out", 0xE7, RawFrm>, Imp<[EAX], []>;
287 //===----------------------------------------------------------------------===//
288 // Move Instructions...
290 def MOV8rr : I <"mov", 0x88, MRMDestReg>;
291 def MOV16rr : I <"mov", 0x89, MRMDestReg>, OpSize;
292 def MOV32rr : I <"mov", 0x89, MRMDestReg>;
293 def MOV8ri : Ii8 <"mov", 0xB0, AddRegFrm >;
294 def MOV16ri : Ii16 <"mov", 0xB8, AddRegFrm >, OpSize;
295 def MOV32ri : Ii32 <"mov", 0xB8, AddRegFrm >;
296 def MOV8mi : Im8i8 <"mov", 0xC6, MRM0m >; // [mem8] = imm8
297 def MOV16mi : Im16i16<"mov", 0xC7, MRM0m >, OpSize; // [mem16] = imm16
298 def MOV32mi : Im32i32<"mov", 0xC7, MRM0m >; // [mem32] = imm32
300 def MOV8rm : Im8 <"mov", 0x8A, MRMSrcMem>; // R8 = [mem8]
301 def MOV16rm : Im16 <"mov", 0x8B, MRMSrcMem>, OpSize; // R16 = [mem16]
302 def MOV32rm : Im32 <"mov", 0x8B, MRMSrcMem>; // R32 = [mem32]
304 def MOV8mr : Im8 <"mov", 0x88, MRMDestMem>; // [mem8] = R8
305 def MOV16mr : Im16 <"mov", 0x89, MRMDestMem>, OpSize; // [mem16] = R16
306 def MOV32mr : Im32 <"mov", 0x89, MRMDestMem>; // [mem32] = R32
308 //===----------------------------------------------------------------------===//
309 // Fixed-Register Multiplication and Division Instructions...
312 // Extra precision multiplication
313 def MUL8r : I <"mul", 0xF6, MRM4r>, Imp<[AL],[AX]>; // AL,AH = AL*R8
314 def MUL16r : I <"mul", 0xF7, MRM4r>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
315 def MUL32r : I <"mul", 0xF7, MRM4r>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
316 def MUL8m : Im8 <"mul", 0xF6, MRM4m>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
317 def MUL16m : Im16<"mul", 0xF7, MRM4m>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*[mem16]
318 def MUL32m : Im32<"mul", 0xF7, MRM4m>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
320 // unsigned division/remainder
321 def DIV8r : I <"div", 0xF6, MRM6r>, Imp<[AX],[AX]>; // AX/r8 = AL,AH
322 def DIV16r : I <"div", 0xF7, MRM6r>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
323 def DIV32r : I <"div", 0xF7, MRM6r>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
324 def DIV8m : Im8 <"div", 0xF6, MRM6m>, Imp<[AX],[AX]>; // AX/[mem8] = AL,AH
325 def DIV16m : Im16<"div", 0xF7, MRM6m>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[mem16] = AX,DX
326 def DIV32m : Im32<"div", 0xF7, MRM6m>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX
328 // signed division/remainder
329 def IDIV8r : I <"idiv",0xF6, MRM7r>, Imp<[AX],[AX]>; // AX/r8 = AL,AH
330 def IDIV16r: I <"idiv",0xF7, MRM7r>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
331 def IDIV32r: I <"idiv",0xF7, MRM7r>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
332 def IDIV8m : Im8 <"idiv",0xF6, MRM7m>, Imp<[AX],[AX]>; // AX/[mem8] = AL,AH
333 def IDIV16m: Im16<"idiv",0xF7, MRM7m>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[mem16] = AX,DX
334 def IDIV32m: Im32<"idiv",0xF7, MRM7m>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX
336 // Sign-extenders for division
337 def CBW : I<"cbw", 0x98, RawFrm >, Imp<[AL],[AH]>, // AX = signext(AL)
339 def CWD : I<"cwd", 0x99, RawFrm >, Imp<[AX],[DX]>, // DX:AX = signext(AX)
341 def CDQ : I<"cdq", 0x99, RawFrm >, Imp<[EAX],[EDX]>, // EDX:EAX = signext(EAX)
344 //===----------------------------------------------------------------------===//
345 // Two address Instructions...
347 let isTwoAddress = 1 in {
350 def CMOVB16rr : I <"cmovb", 0x42, MRMSrcReg>, TB, OpSize; // if <u, R16 = R16
351 def CMOVB16rm : Im16<"cmovb", 0x42, MRMSrcMem>, TB, OpSize; // if <u, R16 = [mem16]
352 def CMOVB32rr : I <"cmovb", 0x42, MRMSrcReg>, TB; // if <u, R32 = R32
353 def CMOVB32rm : Im32<"cmovb", 0x42, MRMSrcMem>, TB; // if <u, R32 = [mem32]
355 def CMOVAE16rr: I <"cmovae", 0x43, MRMSrcReg>, TB, OpSize; // if >=u, R16 = R16
356 def CMOVAE16rm: Im16<"cmovae", 0x43, MRMSrcMem>, TB, OpSize; // if >=u, R16 = [mem16]
357 def CMOVAE32rr: I <"cmovae", 0x43, MRMSrcReg>, TB; // if >=u, R32 = R32
358 def CMOVAE32rm: Im32<"cmovae", 0x43, MRMSrcMem>, TB; // if >=u, R32 = [mem32]
360 def CMOVE16rr : I <"cmove", 0x44, MRMSrcReg>, TB, OpSize; // if ==, R16 = R16
361 def CMOVE16rm : Im16<"cmove", 0x44, MRMSrcMem>, TB, OpSize; // if ==, R16 = [mem16]
362 def CMOVE32rr : I <"cmove", 0x44, MRMSrcReg>, TB; // if ==, R32 = R32
363 def CMOVE32rm : Im32<"cmove", 0x44, MRMSrcMem>, TB; // if ==, R32 = [mem32]
365 def CMOVNE16rr: I <"cmovne",0x45, MRMSrcReg>, TB, OpSize; // if !=, R16 = R16
366 def CMOVNE16rm: Im16<"cmovne",0x45, MRMSrcMem>, TB, OpSize; // if !=, R16 = [mem16]
367 def CMOVNE32rr: I <"cmovne",0x45, MRMSrcReg>, TB; // if !=, R32 = R32
368 def CMOVNE32rm: Im32<"cmovne",0x45, MRMSrcMem>, TB; // if !=, R32 = [mem32]
370 def CMOVBE16rr: I <"cmovbe",0x46, MRMSrcReg>, TB, OpSize; // if <=u, R16 = R16
371 def CMOVBE16rm: Im16<"cmovbe",0x46, MRMSrcMem>, TB, OpSize; // if <=u, R16 = [mem16]
372 def CMOVBE32rr: I <"cmovbe",0x46, MRMSrcReg>, TB; // if <=u, R32 = R32
373 def CMOVBE32rm: Im32<"cmovbe",0x46, MRMSrcMem>, TB; // if <=u, R32 = [mem32]
375 def CMOVA16rr : I <"cmova", 0x47, MRMSrcReg>, TB, OpSize; // if >u, R16 = R16
376 def CMOVA16rm : Im16<"cmova", 0x47, MRMSrcMem>, TB, OpSize; // if >u, R16 = [mem16]
377 def CMOVA32rr : I <"cmova", 0x47, MRMSrcReg>, TB; // if >u, R32 = R32
378 def CMOVA32rm : Im32<"cmova", 0x47, MRMSrcMem>, TB; // if >u, R32 = [mem32]
380 def CMOVS16rr : I <"cmovs", 0x48, MRMSrcReg>, TB, OpSize; // if signed, R16 = R16
381 def CMOVS16rm : Im16<"cmovs", 0x48, MRMSrcMem>, TB, OpSize; // if signed, R16 = [mem16]
382 def CMOVS32rr : I <"cmovs", 0x48, MRMSrcReg>, TB; // if signed, R32 = R32
383 def CMOVS32rm : Im32<"cmovs", 0x48, MRMSrcMem>, TB; // if signed, R32 = [mem32]
385 def CMOVNS16rr: I <"cmovns",0x49, MRMSrcReg>, TB, OpSize; // if !signed, R16 = R16
386 def CMOVNS16rm: Im16<"cmovns",0x49, MRMSrcMem>, TB, OpSize; // if !signed, R16 = [mem16]
387 def CMOVNS32rr: I <"cmovns",0x49, MRMSrcReg>, TB; // if !signed, R32 = R32
388 def CMOVNS32rm: Im32<"cmovns",0x49, MRMSrcMem>, TB; // if !signed, R32 = [mem32]
390 def CMOVL16rr : I <"cmovl", 0x4C, MRMSrcReg>, TB, OpSize; // if <s, R16 = R16
391 def CMOVL16rm : Im16<"cmovl", 0x4C, MRMSrcMem>, TB, OpSize; // if <s, R16 = [mem16]
392 def CMOVL32rr : I <"cmovl", 0x4C, MRMSrcReg>, TB; // if <s, R32 = R32
393 def CMOVL32rm : Im32<"cmovl", 0x4C, MRMSrcMem>, TB; // if <s, R32 = [mem32]
395 def CMOVGE16rr: I <"cmovge",0x4D, MRMSrcReg>, TB, OpSize; // if >=s, R16 = R16
396 def CMOVGE16rm: Im16<"cmovge",0x4D, MRMSrcMem>, TB, OpSize; // if >=s, R16 = [mem16]
397 def CMOVGE32rr: I <"cmovge",0x4D, MRMSrcReg>, TB; // if >=s, R32 = R32
398 def CMOVGE32rm: Im32<"cmovge",0x4D, MRMSrcMem>, TB; // if >=s, R32 = [mem32]
400 def CMOVLE16rr: I <"cmovle",0x4E, MRMSrcReg>, TB, OpSize; // if <=s, R16 = R16
401 def CMOVLE16rm: Im16<"cmovle",0x4E, MRMSrcMem>, TB, OpSize; // if <=s, R16 = [mem16]
402 def CMOVLE32rr: I <"cmovle",0x4E, MRMSrcReg>, TB; // if <=s, R32 = R32
403 def CMOVLE32rm: Im32<"cmovle",0x4E, MRMSrcMem>, TB; // if <=s, R32 = [mem32]
405 def CMOVG16rr : I <"cmovg", 0x4F, MRMSrcReg>, TB, OpSize; // if >s, R16 = R16
406 def CMOVG16rm : Im16<"cmovg", 0x4F, MRMSrcMem>, TB, OpSize; // if >s, R16 = [mem16]
407 def CMOVG32rr : I <"cmovg", 0x4F, MRMSrcReg>, TB; // if >s, R32 = R32
408 def CMOVG32rm : Im32<"cmovg", 0x4F, MRMSrcMem>, TB; // if >s, R32 = [mem32]
410 // unary instructions
411 def NEG8r : I <"neg", 0xF6, MRM3r>; // R8 = -R8 = 0-R8
412 def NEG16r : I <"neg", 0xF7, MRM3r>, OpSize; // R16 = -R16 = 0-R16
413 def NEG32r : I <"neg", 0xF7, MRM3r>; // R32 = -R32 = 0-R32
414 def NEG8m : Im8 <"neg", 0xF6, MRM3m>; // [mem8] = -[mem8] = 0-[mem8]
415 def NEG16m : Im16<"neg", 0xF7, MRM3m>, OpSize; // [mem16] = -[mem16] = 0-[mem16]
416 def NEG32m : Im32<"neg", 0xF7, MRM3m>; // [mem32] = -[mem32] = 0-[mem32]
418 def NOT8r : I <"not", 0xF6, MRM2r>; // R8 = ~R8 = R8^-1
419 def NOT16r : I <"not", 0xF7, MRM2r>, OpSize; // R16 = ~R16 = R16^-1
420 def NOT32r : I <"not", 0xF7, MRM2r>; // R32 = ~R32 = R32^-1
421 def NOT8m : Im8 <"not", 0xF6, MRM2m>; // [mem8] = ~[mem8] = [mem8^-1]
422 def NOT16m : Im16<"not", 0xF7, MRM2m>, OpSize; // [mem16] = ~[mem16] = [mem16^-1]
423 def NOT32m : Im32<"not", 0xF7, MRM2m>; // [mem32] = ~[mem32] = [mem32^-1]
425 def INC8r : I <"inc", 0xFE, MRM0r>; // ++R8
426 def INC16r : I <"inc", 0xFF, MRM0r>, OpSize; // ++R16
427 def INC32r : I <"inc", 0xFF, MRM0r>; // ++R32
428 def INC8m : Im8 <"inc", 0xFE, MRM0m>; // ++R8
429 def INC16m : Im16<"inc", 0xFF, MRM0m>, OpSize; // ++R16
430 def INC32m : Im32<"inc", 0xFF, MRM0m>; // ++R32
432 def DEC8r : I <"dec", 0xFE, MRM1r>; // --R8
433 def DEC16r : I <"dec", 0xFF, MRM1r>, OpSize; // --R16
434 def DEC32r : I <"dec", 0xFF, MRM1r>; // --R32
435 def DEC8m : Im8 <"dec", 0xFE, MRM1m>; // --[mem8]
436 def DEC16m : Im16<"dec", 0xFF, MRM1m>, OpSize; // --[mem16]
437 def DEC32m : Im32<"dec", 0xFF, MRM1m>; // --[mem32]
439 // Logical operators...
440 def AND8rr : I <"and", 0x20, MRMDestReg>,
441 II<(ops R8:$dst, R8:$src1, R8:$src2), "and $dst, $src2">;
442 def AND16rr : I <"and", 0x21, MRMDestReg>, OpSize;
443 def AND32rr : I <"and", 0x21, MRMDestReg>;
444 def AND8mr : Im8 <"and", 0x20, MRMDestMem>; // [mem8] &= R8
445 def AND16mr : Im16 <"and", 0x21, MRMDestMem>, OpSize; // [mem16] &= R16
446 def AND32mr : Im32 <"and", 0x21, MRMDestMem>; // [mem32] &= R32
447 def AND8rm : Im8 <"and", 0x22, MRMSrcMem >; // R8 &= [mem8]
448 def AND16rm : Im16 <"and", 0x23, MRMSrcMem >, OpSize; // R16 &= [mem16]
449 def AND32rm : Im32 <"and", 0x23, MRMSrcMem >; // R32 &= [mem32]
451 def AND8ri : Ii8 <"and", 0x80, MRM4r >;
452 def AND16ri : Ii16 <"and", 0x81, MRM4r >, OpSize;
453 def AND32ri : Ii32 <"and", 0x81, MRM4r >;
454 def AND8mi : Im8i8 <"and", 0x80, MRM4m >; // [mem8] &= imm8
455 def AND16mi : Im16i16<"and", 0x81, MRM4m >, OpSize; // [mem16] &= imm16
456 def AND32mi : Im32i32<"and", 0x81, MRM4m >; // [mem32] &= imm32
458 def AND16ri8 : Ii8 <"and", 0x83, MRM4r >, OpSize; // R16 &= imm8
459 def AND32ri8 : Ii8 <"and", 0x83, MRM4r >; // R32 &= imm8
460 def AND16mi8 : Im16i8<"and", 0x83, MRM4m >, OpSize; // [mem16] &= imm8
461 def AND32mi8 : Im32i8<"and", 0x83, MRM4m >; // [mem32] &= imm8
464 def OR8rr : I <"or" , 0x08, MRMDestReg>;
465 def OR16rr : I <"or" , 0x09, MRMDestReg>, OpSize;
466 def OR32rr : I <"or" , 0x09, MRMDestReg>;
467 def OR8mr : Im8 <"or" , 0x08, MRMDestMem>; // [mem8] |= R8
468 def OR16mr : Im16 <"or" , 0x09, MRMDestMem>, OpSize; // [mem16] |= R16
469 def OR32mr : Im32 <"or" , 0x09, MRMDestMem>; // [mem32] |= R32
470 def OR8rm : Im8 <"or" , 0x0A, MRMSrcMem >; // R8 |= [mem8]
471 def OR16rm : Im16 <"or" , 0x0B, MRMSrcMem >, OpSize; // R16 |= [mem16]
472 def OR32rm : Im32 <"or" , 0x0B, MRMSrcMem >; // R32 |= [mem32]
474 def OR8ri : Ii8 <"or" , 0x80, MRM1r >;
475 def OR16ri : Ii16 <"or" , 0x81, MRM1r >, OpSize;
476 def OR32ri : Ii32 <"or" , 0x81, MRM1r >;
477 def OR8mi : Im8i8 <"or" , 0x80, MRM1m >; // [mem8] |= imm8
478 def OR16mi : Im16i16<"or" , 0x81, MRM1m >, OpSize; // [mem16] |= imm16
479 def OR32mi : Im32i32<"or" , 0x81, MRM1m >; // [mem32] |= imm32
481 def OR16ri8 : Ii8 <"or" , 0x83, MRM1r >, OpSize; // R16 |= imm8
482 def OR32ri8 : Ii8 <"or" , 0x83, MRM1r >; // R32 |= imm8
483 def OR16mi8 : Im16i8<"or" , 0x83, MRM1m >, OpSize; // [mem16] |= imm8
484 def OR32mi8 : Im32i8<"or" , 0x83, MRM1m >; // [mem32] |= imm8
487 def XOR8rr : I <"xor", 0x30, MRMDestReg>;
488 def XOR16rr : I <"xor", 0x31, MRMDestReg>, OpSize;
489 def XOR32rr : I <"xor", 0x31, MRMDestReg>;
490 def XOR8mr : Im8 <"xor", 0x30, MRMDestMem>; // [mem8] ^= R8
491 def XOR16mr : Im16 <"xor", 0x31, MRMDestMem>, OpSize; // [mem16] ^= R16
492 def XOR32mr : Im32 <"xor", 0x31, MRMDestMem>; // [mem32] ^= R32
493 def XOR8rm : Im8 <"xor", 0x32, MRMSrcMem >; // R8 ^= [mem8]
494 def XOR16rm : Im16 <"xor", 0x33, MRMSrcMem >, OpSize; // R16 ^= [mem16]
495 def XOR32rm : Im32 <"xor", 0x33, MRMSrcMem >; // R32 ^= [mem32]
497 def XOR8ri : Ii8 <"xor", 0x80, MRM6r >;
498 def XOR16ri : Ii16 <"xor", 0x81, MRM6r >, OpSize;
499 def XOR32ri : Ii32 <"xor", 0x81, MRM6r >;
500 def XOR8mi : Im8i8 <"xor", 0x80, MRM6m >; // [mem8] ^= R8
501 def XOR16mi : Im16i16<"xor", 0x81, MRM6m >, OpSize; // [mem16] ^= R16
502 def XOR32mi : Im32i32<"xor", 0x81, MRM6m >; // [mem32] ^= R32
504 def XOR16ri8 : Ii8 <"xor", 0x83, MRM6r >, OpSize; // R16 ^= imm8
505 def XOR32ri8 : Ii8 <"xor", 0x83, MRM6r >; // R32 ^= imm8
506 def XOR16mi8 : Im16i8<"xor", 0x83, MRM6m >, OpSize; // [mem16] ^= imm8
507 def XOR32mi8 : Im32i8<"xor", 0x83, MRM6m >; // [mem32] ^= imm8
509 // Shift instructions
510 // FIXME: provide shorter instructions when imm8 == 1
511 def SHL8rCL : I <"shl", 0xD2, MRM4r > , UsesCL, // R8 <<= cl
512 II<(ops R8:$dst, R8:$src), "shl $dst, CL">;
513 def SHL16rCL : I <"shl", 0xD3, MRM4r >, OpSize, UsesCL, // R16 <<= cl
514 II<(ops R16:$dst, R16:$src), "shl $dst, CL">;
515 def SHL32rCL : I <"shl", 0xD3, MRM4r > , UsesCL, // R32 <<= cl
516 II<(ops R32:$dst, R32:$src), "shl $dst, CL">;
517 def SHL8mCL : Im8 <"shl", 0xD2, MRM4m > , UsesCL; // [mem8] <<= cl
518 def SHL16mCL : Im16 <"shl", 0xD3, MRM4m >, OpSize, UsesCL; // [mem16] <<= cl
519 def SHL32mCL : Im32 <"shl", 0xD3, MRM4m > , UsesCL; // [mem32] <<= cl
521 def SHL8ri : Ii8 <"shl", 0xC0, MRM4r >; // R8 <<= imm8
522 def SHL16ri : Ii8 <"shl", 0xC1, MRM4r >, OpSize; // R16 <<= imm8
523 def SHL32ri : Ii8 <"shl", 0xC1, MRM4r >; // R32 <<= imm8
524 def SHL8mi : Im8i8 <"shl", 0xC0, MRM4m >; // [mem8] <<= imm8
525 def SHL16mi : Im16i8<"shl", 0xC1, MRM4m >, OpSize; // [mem16] <<= imm8
526 def SHL32mi : Im32i8<"shl", 0xC1, MRM4m >; // [mem32] <<= imm8
528 def SHR8rCL : I <"shr", 0xD2, MRM5r > , UsesCL, // R8 >>= cl
529 II<(ops R8:$dst, R8:$src), "shr $dst, CL">;
530 def SHR16rCL : I <"shr", 0xD3, MRM5r >, OpSize, UsesCL, // R16 >>= cl
531 II<(ops R16:$dst, R16:$src), "shr $dst, CL">;
532 def SHR32rCL : I <"shr", 0xD3, MRM5r > , UsesCL, // R32 >>= cl
533 II<(ops R32:$dst, R32:$src), "shr $dst, CL">;
534 def SHR8mCL : Im8 <"shr", 0xD2, MRM5m > , UsesCL; // [mem8] >>= cl
535 def SHR16mCL : Im16 <"shr", 0xD3, MRM5m >, OpSize, UsesCL; // [mem16] >>= cl
536 def SHR32mCL : Im32 <"shr", 0xD3, MRM5m > , UsesCL; // [mem32] >>= cl
538 def SHR8ri : Ii8 <"shr", 0xC0, MRM5r >; // R8 >>= imm8
539 def SHR16ri : Ii8 <"shr", 0xC1, MRM5r >, OpSize; // R16 >>= imm8
540 def SHR32ri : Ii8 <"shr", 0xC1, MRM5r >; // R32 >>= imm8
541 def SHR8mi : Im8i8 <"shr", 0xC0, MRM5m >; // [mem8] >>= imm8
542 def SHR16mi : Im16i8<"shr", 0xC1, MRM5m >, OpSize; // [mem16] >>= imm8
543 def SHR32mi : Im32i8<"shr", 0xC1, MRM5m >; // [mem32] >>= imm8
545 def SAR8rCL : I <"sar", 0xD2, MRM7r > , UsesCL; // R8 >>>= cl
546 def SAR16rCL : I <"sar", 0xD3, MRM7r >, OpSize, UsesCL; // R16 >>>= cl
547 def SAR32rCL : I <"sar", 0xD3, MRM7r > , UsesCL; // R32 >>>= cl
548 def SAR8mCL : Im8 <"sar", 0xD2, MRM7m > , UsesCL; // [mem8] >>>= cl
549 def SAR16mCL : Im16 <"sar", 0xD3, MRM7m >, OpSize, UsesCL; // [mem16] >>>= cl
550 def SAR32mCL : Im32 <"sar", 0xD3, MRM7m > , UsesCL; // [mem32] >>>= cl
552 def SAR8ri : Ii8 <"sar", 0xC0, MRM7r >; // R8 >>>= imm8
553 def SAR16ri : Ii8 <"sar", 0xC1, MRM7r >, OpSize; // R16 >>>= imm8
554 def SAR32ri : Ii8 <"sar", 0xC1, MRM7r >; // R32 >>>= imm8
555 def SAR8mi : Im8i8 <"sar", 0xC0, MRM7m >; // [mem8] >>>= imm8
556 def SAR16mi : Im16i8<"sar", 0xC1, MRM7m >, OpSize; // [mem16] >>>= imm8
557 def SAR32mi : Im32i8<"sar", 0xC1, MRM7m >; // [mem32] >>>= imm8
559 def SHLD32rrCL : I <"shld", 0xA5, MRMDestReg>, TB, UsesCL; // R32 <<= R32,R32 cl
560 def SHLD32mrCL : Im32 <"shld", 0xA5, MRMDestMem>, TB, UsesCL; // [mem32] <<= [mem32],R32 cl
561 def SHLD32rri8 : Ii8 <"shld", 0xA4, MRMDestReg>, TB; // R32 <<= R32,R32 imm8
562 def SHLD32mri8 : Im32i8<"shld", 0xA4, MRMDestMem>, TB; // [mem32] <<= [mem32],R32 imm8
564 def SHRD32rrCL : I <"shrd", 0xAD, MRMDestReg>, TB, UsesCL; // R32 >>= R32,R32 cl
565 def SHRD32mrCL : Im32 <"shrd", 0xAD, MRMDestMem>, TB, UsesCL; // [mem32] >>= [mem32],R32 cl
566 def SHRD32rri8 : Ii8 <"shrd", 0xAC, MRMDestReg>, TB; // R32 >>= R32,R32 imm8
567 def SHRD32mri8 : Im32i8<"shrd", 0xAC, MRMDestMem>, TB; // [mem32] >>= [mem32],R32 imm8
571 def ADD8rr : I <"add", 0x00, MRMDestReg>;
572 def ADD16rr : I <"add", 0x01, MRMDestReg>, OpSize;
573 def ADD32rr : I <"add", 0x01, MRMDestReg>;
574 def ADD8mr : Im8 <"add", 0x00, MRMDestMem>; // [mem8] += R8
575 def ADD16mr : Im16 <"add", 0x01, MRMDestMem>, OpSize; // [mem16] += R16
576 def ADD32mr : Im32 <"add", 0x01, MRMDestMem>; // [mem32] += R32
577 def ADD8rm : Im8 <"add", 0x02, MRMSrcMem >; // R8 += [mem8]
578 def ADD16rm : Im16 <"add", 0x03, MRMSrcMem >, OpSize; // R16 += [mem16]
579 def ADD32rm : Im32 <"add", 0x03, MRMSrcMem >; // R32 += [mem32]
581 def ADD8ri : Ii8 <"add", 0x80, MRM0r >;
582 def ADD16ri : Ii16 <"add", 0x81, MRM0r >, OpSize;
583 def ADD32ri : Ii32 <"add", 0x81, MRM0r >;
584 def ADD8mi : Im8i8 <"add", 0x80, MRM0m >; // [mem8] += I8
585 def ADD16mi : Im16i16<"add", 0x81, MRM0m >, OpSize; // [mem16] += I16
586 def ADD32mi : Im32i32<"add", 0x81, MRM0m >; // [mem32] += I32
588 def ADD16ri8 : Ii8 <"add", 0x83, MRM0r >, OpSize; // ADDri with sign extended 8 bit imm
589 def ADD32ri8 : Ii8 <"add", 0x83, MRM0r >;
590 def ADD16mi8 : Im16i8<"add", 0x83, MRM0m >, OpSize; // [mem16] += I8
591 def ADD32mi8 : Im32i8<"add", 0x83, MRM0m >; // [mem32] += I8
593 def ADC32rr : I <"adc", 0x11, MRMDestReg>; // R32 += R32+Carry
594 def ADC32mr : Im32 <"adc", 0x11, MRMDestMem>; // [mem32] += R32+Carry
595 def ADC32rm : Im32 <"adc", 0x13, MRMSrcMem >; // R32 += [mem32]+Carry
596 def ADC32ri : Ii32 <"adc", 0x81, MRM2r >; // R32 += I32+Carry
597 def ADC32ri8 : Ii8 <"adc", 0x83, MRM2r >; // R32 += I8+Carry
598 def ADC32mi : Im32i32<"adc", 0x81, MRM2m >; // [mem32] += I32+Carry
599 def ADC32mi8 : Im32i8 <"adc", 0x83, MRM2m >; // [mem32] += I8+Carry
601 def SUB8rr : I <"sub", 0x28, MRMDestReg>;
602 def SUB16rr : I <"sub", 0x29, MRMDestReg>, OpSize;
603 def SUB32rr : I <"sub", 0x29, MRMDestReg>;
604 def SUB8mr : Im8 <"sub", 0x28, MRMDestMem>; // [mem8] -= R8
605 def SUB16mr : Im16 <"sub", 0x29, MRMDestMem>, OpSize; // [mem16] -= R16
606 def SUB32mr : Im32 <"sub", 0x29, MRMDestMem>; // [mem32] -= R32
607 def SUB8rm : Im8 <"sub", 0x2A, MRMSrcMem >; // R8 -= [mem8]
608 def SUB16rm : Im16 <"sub", 0x2B, MRMSrcMem >, OpSize; // R16 -= [mem16]
609 def SUB32rm : Im32 <"sub", 0x2B, MRMSrcMem >; // R32 -= [mem32]
611 def SUB8ri : Ii8 <"sub", 0x80, MRM5r >;
612 def SUB16ri : Ii16 <"sub", 0x81, MRM5r >, OpSize;
613 def SUB32ri : Ii32 <"sub", 0x81, MRM5r >;
614 def SUB8mi : Im8i8 <"sub", 0x80, MRM5m >; // [mem8] -= I8
615 def SUB16mi : Im16i16<"sub", 0x81, MRM5m >, OpSize; // [mem16] -= I16
616 def SUB32mi : Im32i32<"sub", 0x81, MRM5m >; // [mem32] -= I32
618 def SUB16ri8 : Ii8 <"sub", 0x83, MRM5r >, OpSize;
619 def SUB32ri8 : Ii8 <"sub", 0x83, MRM5r >;
620 def SUB16mi8 : Im16i8<"sub", 0x83, MRM5m >, OpSize; // [mem16] -= I8
621 def SUB32mi8 : Im32i8<"sub", 0x83, MRM5m >; // [mem32] -= I8
623 def SBB32rr : I <"sbb", 0x19, MRMDestReg>; // R32 -= R32+Carry
624 def SBB32mr : Im32 <"sbb", 0x19, MRMDestMem>; // [mem32] -= R32+Carry
625 def SBB32rm : Im32 <"sbb", 0x1B, MRMSrcMem >; // R32 -= [mem32]+Carry
626 def SBB32ri : Ii32 <"sbb", 0x81, MRM3r >; // R32 -= I32+Carry
627 def SBB32ri8 : Ii8 <"sbb", 0x83, MRM3r >; // R32 -= I8+Carry
628 def SBB32mi : Im32i32<"sbb", 0x81, MRM3m >; // [mem32] -= I32+Carry
629 def SBB32mi8 : Im32i8 <"sbb", 0x83, MRM3m >; // [mem32] -= I8+Carry
631 def IMUL16rr : I <"imul", 0xAF, MRMSrcReg>, TB, OpSize;
632 def IMUL32rr : I <"imul", 0xAF, MRMSrcReg>, TB;
633 def IMUL16rm : Im16 <"imul", 0xAF, MRMSrcMem>, TB, OpSize;
634 def IMUL32rm : Im32 <"imul", 0xAF, MRMSrcMem>, TB ;
636 } // end Two Address instructions
638 // These are suprisingly enough not two address instructions!
639 def IMUL16rri : Ii16 <"imul", 0x69, MRMSrcReg>, OpSize; // R16 = R16*I16
640 def IMUL32rri : Ii32 <"imul", 0x69, MRMSrcReg>; // R32 = R32*I32
641 def IMUL16rri8 : Ii8 <"imul", 0x6B, MRMSrcReg>, OpSize; // R16 = R16*I8
642 def IMUL32rri8 : Ii8 <"imul", 0x6B, MRMSrcReg>; // R32 = R32*I8
643 def IMUL16rmi : Im16i16<"imul",0x69, MRMSrcMem>, OpSize; // R16 = [mem16]*I16
644 def IMUL32rmi : Im32i32<"imul",0x69, MRMSrcMem>; // R32 = [mem32]*I32
645 def IMUL16rmi8 : Im16i8<"imul", 0x6B, MRMSrcMem>, OpSize; // R16 = [mem16]*I8
646 def IMUL32rmi8 : Im32i8<"imul", 0x6B, MRMSrcMem>; // R32 = [mem32]*I8
648 //===----------------------------------------------------------------------===//
649 // Test instructions are just like AND, except they don't generate a result.
650 def TEST8rr : I <"test", 0x84, MRMDestReg>; // flags = R8 & R8
651 def TEST16rr : I <"test", 0x85, MRMDestReg>, OpSize; // flags = R16 & R16
652 def TEST32rr : I <"test", 0x85, MRMDestReg>; // flags = R32 & R32
653 def TEST8mr : Im8 <"test", 0x84, MRMDestMem>; // flags = [mem8] & R8
654 def TEST16mr : Im16 <"test", 0x85, MRMDestMem>, OpSize; // flags = [mem16] & R16
655 def TEST32mr : Im32 <"test", 0x85, MRMDestMem>; // flags = [mem32] & R32
656 def TEST8rm : Im8 <"test", 0x84, MRMSrcMem >; // flags = R8 & [mem8]
657 def TEST16rm : Im16 <"test", 0x85, MRMSrcMem >, OpSize; // flags = R16 & [mem16]
658 def TEST32rm : Im32 <"test", 0x85, MRMSrcMem >; // flags = R32 & [mem32]
660 def TEST8ri : Ii8 <"test", 0xF6, MRM0r >; // flags = R8 & imm8
661 def TEST16ri : Ii16 <"test", 0xF7, MRM0r >, OpSize; // flags = R16 & imm16
662 def TEST32ri : Ii32 <"test", 0xF7, MRM0r >; // flags = R32 & imm32
663 def TEST8mi : Im8i8 <"test", 0xF6, MRM0m >; // flags = [mem8] & imm8
664 def TEST16mi : Im16i16<"test", 0xF7, MRM0m >, OpSize; // flags = [mem16] & imm16
665 def TEST32mi : Im32i32<"test", 0xF7, MRM0m >; // flags = [mem32] & imm32
669 // Condition code ops, incl. set if equal/not equal/...
670 def SAHF : I <"sahf" , 0x9E, RawFrm>, Imp<[AH],[]>, // flags = AH
672 def LAHF : I <"lahf" , 0x9F, RawFrm>, Imp<[],[AH]>, // AH = flags
675 def SETBr : I <"setb" , 0x92, MRM0r>, TB; // R8 = < unsign
676 def SETBm : Im8<"setb" , 0x92, MRM0m>, TB; // [mem8] = < unsign
677 def SETAEr : I <"setae", 0x93, MRM0r>, TB; // R8 = >= unsign
678 def SETAEm : Im8<"setae", 0x93, MRM0m>, TB; // [mem8] = >= unsign
679 def SETEr : I <"sete" , 0x94, MRM0r>, TB; // R8 = ==
680 def SETEm : Im8<"sete" , 0x94, MRM0m>, TB; // [mem8] = ==
681 def SETNEr : I <"setne", 0x95, MRM0r>, TB; // R8 = !=
682 def SETNEm : Im8<"setne", 0x95, MRM0m>, TB; // [mem8] = !=
683 def SETBEr : I <"setbe", 0x96, MRM0r>, TB; // R8 = <= unsign
684 def SETBEm : Im8<"setbe", 0x96, MRM0m>, TB; // [mem8] = <= unsign
685 def SETAr : I <"seta" , 0x97, MRM0r>, TB; // R8 = > signed
686 def SETAm : Im8<"seta" , 0x97, MRM0m>, TB; // [mem8] = > signed
687 def SETSr : I <"sets" , 0x98, MRM0r>, TB; // R8 = <sign bit>
688 def SETSm : Im8<"sets" , 0x98, MRM0m>, TB; // [mem8] = <sign bit>
689 def SETNSr : I <"setns", 0x99, MRM0r>, TB; // R8 = !<sign bit>
690 def SETNSm : Im8<"setns", 0x99, MRM0m>, TB; // [mem8] = !<sign bit>
691 def SETPr : I <"setp" , 0x9A, MRM0r>, TB; // R8 = parity
692 def SETPm : Im8<"setp" , 0x9A, MRM0m>, TB; // [mem8] = parity
693 def SETLr : I <"setl" , 0x9C, MRM0r>, TB; // R8 = < signed
694 def SETLm : Im8<"setl" , 0x9C, MRM0m>, TB; // [mem8] = < signed
695 def SETGEr : I <"setge", 0x9D, MRM0r>, TB; // R8 = >= signed
696 def SETGEm : Im8<"setge", 0x9D, MRM0m>, TB; // [mem8] = >= signed
697 def SETLEr : I <"setle", 0x9E, MRM0r>, TB; // R8 = <= signed
698 def SETLEm : Im8<"setle", 0x9E, MRM0m>, TB; // [mem8] = <= signed
699 def SETGr : I <"setg" , 0x9F, MRM0r>, TB; // R8 = < signed
700 def SETGm : Im8<"setg" , 0x9F, MRM0m>, TB; // [mem8] = < signed
702 // Integer comparisons
703 def CMP8rr : I <"cmp", 0x38, MRMDestReg>; // compare R8, R8
704 def CMP16rr : I <"cmp", 0x39, MRMDestReg>, OpSize; // compare R16, R16
705 def CMP32rr : I <"cmp", 0x39, MRMDestReg>; // compare R32, R32
706 def CMP8mr : Im8 <"cmp", 0x38, MRMDestMem>; // compare [mem8], R8
707 def CMP16mr : Im16 <"cmp", 0x39, MRMDestMem>, OpSize; // compare [mem16], R16
708 def CMP32mr : Im32 <"cmp", 0x39, MRMDestMem>; // compare [mem32], R32
709 def CMP8rm : Im8 <"cmp", 0x3A, MRMSrcMem >; // compare R8, [mem8]
710 def CMP16rm : Im16 <"cmp", 0x3B, MRMSrcMem >, OpSize; // compare R16, [mem16]
711 def CMP32rm : Im32 <"cmp", 0x3B, MRMSrcMem >; // compare R32, [mem32]
712 def CMP8ri : Ii8 <"cmp", 0x80, MRM7r >; // compare R8, imm8
713 def CMP16ri : Ii16 <"cmp", 0x81, MRM7r >, OpSize; // compare R16, imm16
714 def CMP32ri : Ii32 <"cmp", 0x81, MRM7r >; // compare R32, imm32
715 def CMP8mi : Im8i8 <"cmp", 0x80, MRM7m >; // compare [mem8], imm8
716 def CMP16mi : Im16i16<"cmp", 0x81, MRM7m >, OpSize; // compare [mem16], imm16
717 def CMP32mi : Im32i32<"cmp", 0x81, MRM7m >; // compare [mem32], imm32
719 // Sign/Zero extenders
720 def MOVSX16rr8 : I <"movsx", 0xBE, MRMSrcReg>, TB, OpSize; // R16 = signext(R8)
721 def MOVSX32rr8 : I <"movsx", 0xBE, MRMSrcReg>, TB; // R32 = signext(R8)
722 def MOVSX32rr16: I <"movsx", 0xBF, MRMSrcReg>, TB; // R32 = signext(R16)
723 def MOVSX16rm8 : Im8 <"movsx", 0xBE, MRMSrcMem>, TB, OpSize; // R16 = signext([mem8])
724 def MOVSX32rm8 : Im8 <"movsx", 0xBE, MRMSrcMem>, TB; // R32 = signext([mem8])
725 def MOVSX32rm16: Im16<"movsx", 0xBF, MRMSrcMem>, TB; // R32 = signext([mem16])
727 def MOVZX16rr8 : I <"movzx", 0xB6, MRMSrcReg>, TB, OpSize; // R16 = zeroext(R8)
728 def MOVZX32rr8 : I <"movzx", 0xB6, MRMSrcReg>, TB; // R32 = zeroext(R8)
729 def MOVZX32rr16: I <"movzx", 0xB7, MRMSrcReg>, TB; // R32 = zeroext(R16)
730 def MOVZX16rm8 : Im8 <"movzx", 0xB6, MRMSrcMem>, TB, OpSize; // R16 = zeroext([mem8])
731 def MOVZX32rm8 : Im8 <"movzx", 0xB6, MRMSrcMem>, TB; // R32 = zeroext([mem8])
732 def MOVZX32rm16: Im16<"movzx", 0xB7, MRMSrcMem>, TB; // R32 = zeroext([mem16])
735 //===----------------------------------------------------------------------===//
736 // Floating point support
737 //===----------------------------------------------------------------------===//
739 // FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP'
741 // Floating point instruction templates
742 class FPInst<string n, bits<8> o, Format F, FPFormat fp, MemType m, ImmType i>
743 : X86Inst<n, o, F, m, i> { let FPForm = fp; let FPFormBits = FPForm.Value; }
745 class FPI<string n, bits<8> o, Format F, FPFormat fp> : FPInst<n, o, F, fp, NoMem, NoImm>;
747 class FPIM<string n, bits<8> o, Format F, FPFormat fp, MemType m> : FPInst<n, o, F, fp, m, NoImm>;
749 class FPI16m<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem16>;
750 class FPI32m<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem32>;
751 class FPI64m<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem64>;
752 class FPI80m<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem80>;
754 // Pseudo instructions for floating point. We use these pseudo instructions
755 // because they can be expanded by the fp spackifier into one of many different
756 // forms of instructions for doing these operations. Until the stackifier runs,
757 // we prefer to be abstract.
758 def FpMOV : FPI<"FMOV", 0, Pseudo, SpecialFP>; // f1 = fmov f2
759 def FpADD : FPI<"FADD", 0, Pseudo, TwoArgFP>; // f1 = fadd f2, f3
760 def FpSUB : FPI<"FSUB", 0, Pseudo, TwoArgFP>; // f1 = fsub f2, f3
761 def FpMUL : FPI<"FMUL", 0, Pseudo, TwoArgFP>; // f1 = fmul f2, f3
762 def FpDIV : FPI<"FDIV", 0, Pseudo, TwoArgFP>; // f1 = fdiv f2, f3
764 def FpGETRESULT : FPI<"FGETRESULT",0, Pseudo, SpecialFP>; // FPR = ST(0)
765 def FpSETRESULT : FPI<"FSETRESULT",0, Pseudo, SpecialFP>; // ST(0) = FPR
767 // FADD reg, mem: Before stackification, these are represented by: R1 = FADD* R2, [mem]
768 def FADD32m : FPI32m<"fadd", 0xD8, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem32real]
769 def FADD64m : FPI64m<"fadd", 0xDC, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem64real]
770 def FIADD16m : FPI16m<"fiadd", 0xDE, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem16int]
771 def FIADD32m : FPI32m<"fiadd", 0xDA, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem32int]
773 // FMUL reg, mem: Before stackification, these are represented by: R1 = FMUL* R2, [mem]
774 def FMUL32m : FPI32m<"fmul", 0xD8, MRM1m, OneArgFPRW>; // ST(0) = ST(0) * [mem32real]
775 def FMUL64m : FPI64m<"fmul", 0xDC, MRM1m, OneArgFPRW>; // ST(0) = ST(0) * [mem64real]
776 def FIMUL16m : FPI16m<"fimul", 0xDE, MRM1m, OneArgFPRW>; // ST(0) = ST(0) * [mem16int]
777 def FIMUL32m : FPI32m<"fimul", 0xDA, MRM1m, OneArgFPRW>; // ST(0) = ST(0) * [mem32int]
779 // FSUB reg, mem: Before stackification, these are represented by: R1 = FSUB* R2, [mem]
780 def FSUB32m : FPI32m<"fsub", 0xD8, MRM4m, OneArgFPRW>; // ST(0) = ST(0) - [mem32real]
781 def FSUB64m : FPI64m<"fsub", 0xDC, MRM4m, OneArgFPRW>; // ST(0) = ST(0) - [mem64real]
782 def FISUB16m : FPI16m<"fisub", 0xDE, MRM4m, OneArgFPRW>; // ST(0) = ST(0) - [mem16int]
783 def FISUB32m : FPI32m<"fisub", 0xDA, MRM4m, OneArgFPRW>; // ST(0) = ST(0) - [mem32int]
785 // FSUBR reg, mem: Before stackification, these are represented by: R1 = FSUBR* R2, [mem]
786 // Note that the order of operands does not reflect the operation being performed.
787 def FSUBR32m : FPI32m<"fsubr", 0xD8, MRM5m, OneArgFPRW>; // ST(0) = [mem32real] - ST(0)
788 def FSUBR64m : FPI64m<"fsubr", 0xDC, MRM5m, OneArgFPRW>; // ST(0) = [mem64real] - ST(0)
789 def FISUBR16m : FPI16m<"fisubr", 0xDE, MRM5m, OneArgFPRW>; // ST(0) = [mem16int] - ST(0)
790 def FISUBR32m : FPI32m<"fisubr", 0xDA, MRM5m, OneArgFPRW>; // ST(0) = [mem32int] - ST(0)
792 // FDIV reg, mem: Before stackification, these are represented by: R1 = FDIV* R2, [mem]
793 def FDIV32m : FPI32m<"fdiv", 0xD8, MRM6m, OneArgFPRW>; // ST(0) = ST(0) / [mem32real]
794 def FDIV64m : FPI64m<"fdiv", 0xDC, MRM6m, OneArgFPRW>; // ST(0) = ST(0) / [mem64real]
795 def FIDIV16m : FPI16m<"fidiv", 0xDE, MRM6m, OneArgFPRW>; // ST(0) = ST(0) / [mem16int]
796 def FIDIV32m : FPI32m<"fidiv", 0xDA, MRM6m, OneArgFPRW>; // ST(0) = ST(0) / [mem32int]
798 // FDIVR reg, mem: Before stackification, these are represented by: R1 = FDIVR* R2, [mem]
799 // Note that the order of operands does not reflect the operation being performed.
800 def FDIVR32m : FPI32m<"fdivr", 0xD8, MRM7m, OneArgFPRW>; // ST(0) = [mem32real] / ST(0)
801 def FDIVR64m : FPI64m<"fdivr", 0xDC, MRM7m, OneArgFPRW>; // ST(0) = [mem64real] / ST(0)
802 def FIDIVR16m : FPI16m<"fidivr", 0xDE, MRM7m, OneArgFPRW>; // ST(0) = [mem16int] / ST(0)
803 def FIDIVR32m : FPI32m<"fidivr", 0xDA, MRM7m, OneArgFPRW>; // ST(0) = [mem32int] / ST(0)
806 // Floating point cmovs...
807 let isTwoAddress = 1, Uses = [ST0], Defs = [ST0], printImplicitUsesBefore = 1 in {
808 def FCMOVB : FPI <"fcmovb" , 0xC0, AddRegFrm, CondMovFP>, DA; // fcmovb ST(i) -> ST(0)
809 def FCMOVBE : FPI <"fcmovbe", 0xD0, AddRegFrm, CondMovFP>, DA; // fcmovbe ST(i) -> ST(0)
810 def FCMOVE : FPI <"fcmove" , 0xC8, AddRegFrm, CondMovFP>, DA; // fcmove ST(i) -> ST(0)
811 def FCMOVAE : FPI <"fcmovae", 0xC0, AddRegFrm, CondMovFP>, DB; // fcmovae ST(i) -> ST(0)
812 def FCMOVA : FPI <"fcmova" , 0xD0, AddRegFrm, CondMovFP>, DB; // fcmova ST(i) -> ST(0)
813 def FCMOVNE : FPI <"fcmovne", 0xC8, AddRegFrm, CondMovFP>, DB; // fcmovne ST(i) -> ST(0)
816 // Floating point loads & stores...
817 def FLDrr : FPI <"fld" , 0xC0, AddRegFrm, NotFP>, D9; // push(ST(i))
818 def FLD32m : FPI32m <"fld" , 0xD9, MRM0m , ZeroArgFP>; // load float
819 def FLD64m : FPI64m <"fld" , 0xDD, MRM0m , ZeroArgFP>; // load double
820 def FLD80m : FPI80m <"fld" , 0xDB, MRM5m , ZeroArgFP>; // load extended
821 def FILD16m : FPI16m <"fild" , 0xDF, MRM0m , ZeroArgFP>; // load signed short
822 def FILD32m : FPI32m <"fild" , 0xDB, MRM0m , ZeroArgFP>; // load signed int
823 def FILD64m : FPI64m <"fild" , 0xDF, MRM5m , ZeroArgFP>; // load signed long
825 def FSTrr : FPI <"fst" , 0xD0, AddRegFrm, NotFP >, DD; // ST(i) = ST(0)
826 def FSTPrr : FPI <"fstp", 0xD8, AddRegFrm, NotFP >, DD; // ST(i) = ST(0), pop
827 def FST32m : FPI32m <"fst" , 0xD9, MRM2m , OneArgFP>; // store float
828 def FST64m : FPI64m <"fst" , 0xDD, MRM2m , OneArgFP>; // store double
829 def FSTP32m : FPI32m <"fstp", 0xD9, MRM3m , OneArgFP>; // store float, pop
830 def FSTP64m : FPI64m <"fstp", 0xDD, MRM3m , OneArgFP>; // store double, pop
831 def FSTP80m : FPI80m <"fstp", 0xDB, MRM7m , OneArgFP>; // store extended, pop
833 def FIST16m : FPI16m <"fist", 0xDF, MRM2m , OneArgFP>; // store signed short
834 def FIST32m : FPI32m <"fist", 0xDB, MRM2m , OneArgFP>; // store signed int
835 def FISTP16m : FPI16m <"fistp", 0xDF, MRM3m , NotFP >; // store signed short, pop
836 def FISTP32m : FPI32m <"fistp", 0xDB, MRM3m , NotFP >; // store signed int, pop
837 def FISTP64m : FPI64m <"fistpll", 0xDF, MRM7m , OneArgFP>; // store signed long, pop
839 def FXCH : FPI <"fxch", 0xC8, AddRegFrm, NotFP>, D9; // fxch ST(i), ST(0)
841 // Floating point constant loads...
842 def FLD0 : FPI<"fldz", 0xEE, RawFrm, ZeroArgFP>, D9,
844 def FLD1 : FPI<"fld1", 0xE8, RawFrm, ZeroArgFP>, D9,
848 // Unary operations...
849 def FCHS : FPI<"fchs", 0xE0, RawFrm, OneArgFPRW>, D9, // f1 = fchs f2
851 def FTST : FPI<"ftst", 0xE4, RawFrm, OneArgFP>, D9, // ftst ST(0)
854 // Binary arithmetic operations...
855 class FPST0rInst<string n, bits<8> o> : I<n, o, AddRegFrm>, D8 {
856 list<Register> Uses = [ST0];
857 list<Register> Defs = [ST0];
859 class FPrST0Inst<string n, bits<8> o> : I<n, o, AddRegFrm>, DC {
860 bit printImplicitUsesAfter = 1;
861 list<Register> Uses = [ST0];
863 class FPrST0PInst<string n, bits<8> o> : I<n, o, AddRegFrm>, DE {
864 list<Register> Uses = [ST0];
867 def FADDST0r : FPST0rInst <"fadd", 0xC0>;
868 def FADDrST0 : FPrST0Inst <"fadd", 0xC0>;
869 def FADDPrST0 : FPrST0PInst<"faddp", 0xC0>;
871 def FSUBRST0r : FPST0rInst <"fsubr", 0xE8>;
872 def FSUBrST0 : FPrST0Inst <"fsub", 0xE8>;
873 def FSUBPrST0 : FPrST0PInst<"fsubp", 0xE8>;
875 def FSUBST0r : FPST0rInst <"fsub", 0xE0>;
876 def FSUBRrST0 : FPrST0Inst <"fsubr", 0xE0>;
877 def FSUBRPrST0 : FPrST0PInst<"fsubrp", 0xE0>;
879 def FMULST0r : FPST0rInst <"fmul", 0xC8>;
880 def FMULrST0 : FPrST0Inst <"fmul", 0xC8>;
881 def FMULPrST0 : FPrST0PInst<"fmulp", 0xC8>;
883 def FDIVRST0r : FPST0rInst <"fdivr", 0xF8>;
884 def FDIVrST0 : FPrST0Inst <"fdiv", 0xF8>;
885 def FDIVPrST0 : FPrST0PInst<"fdivp", 0xF8>;
887 def FDIVST0r : FPST0rInst <"fdiv", 0xF0>; // ST(0) = ST(0) / ST(i)
888 def FDIVRrST0 : FPrST0Inst <"fdivr", 0xF0>; // ST(i) = ST(0) / ST(i)
889 def FDIVRPrST0 : FPrST0PInst<"fdivrp", 0xF0>; // ST(i) = ST(0) / ST(i), pop
891 // Floating point compares
892 def FUCOMr : FPI<"fucom", 0xE0, AddRegFrm, CompareFP>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i)
893 def FUCOMPr : I<"fucomp" , 0xE8, AddRegFrm>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i), pop
894 def FUCOMPPr : I<"fucompp", 0xE9, RawFrm >, DA, Imp<[ST0],[]>, // compare ST(0) with ST(1), pop, pop
895 II<(ops), "fucompp">;
898 let printImplicitUsesBefore = 1 in {
899 def FUCOMIr : FPI<"fucomi", 0xE8, AddRegFrm, CompareFP>, DB, Imp<[ST0],[]>; // CC = compare ST(0) with ST(i)
900 def FUCOMIPr : I<"fucomip", 0xE8, AddRegFrm>, DF, Imp<[ST0],[]>; // CC = compare ST(0) with ST(i), pop
903 // Floating point flag ops
904 def FNSTSW8r : I <"fnstsw" , 0xE0, RawFrm>, DF, Imp<[],[AX]>, // AX = fp flags
907 def FNSTCW16m : Im16<"fnstcw" , 0xD9, MRM7m >; // [mem16] = X87 control world
908 def FLDCW16m : Im16<"fldcw" , 0xD9, MRM5m >; // X87 control world = [mem16]