1 //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // *mem - Operand definitions for the funky X86 addressing mode operands.
19 class X86MemOperand<ValueType Ty> : Operand<Ty> {
20 let NumMIOperands = 4;
21 let PrintMethod = "printMemoryOperand";
24 def i8mem : X86MemOperand<i8>;
25 def i16mem : X86MemOperand<i16>;
26 def i32mem : X86MemOperand<i32>;
27 def i64mem : X86MemOperand<i64>;
28 def f32mem : X86MemOperand<f32>;
29 def f64mem : X86MemOperand<f64>;
30 def f80mem : X86MemOperand<f80>;
32 // PCRelative calls need special operand formatting.
33 let PrintMethod = "printCallOperand" in
34 def calltarget : Operand<i32>;
36 // Format specifies the encoding used by the instruction. This is part of the
37 // ad-hoc solution used to emit machine instruction encodings by our machine
39 class Format<bits<5> val> {
43 def Pseudo : Format<0>; def RawFrm : Format<1>;
44 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
45 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
46 def MRMSrcMem : Format<6>;
47 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
48 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
49 def MRM6r : Format<22>; def MRM7r : Format<23>;
50 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
51 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
52 def MRM6m : Format<30>; def MRM7m : Format<31>;
54 // ImmType - This specifies the immediate type used by an instruction. This is
55 // part of the ad-hoc solution used to emit machine instruction encodings by our
56 // machine code emitter.
57 class ImmType<bits<2> val> {
60 def NoImm : ImmType<0>;
61 def Imm8 : ImmType<1>;
62 def Imm16 : ImmType<2>;
63 def Imm32 : ImmType<3>;
65 // FPFormat - This specifies what form this FP instruction has. This is used by
66 // the Floating-Point stackifier pass.
67 class FPFormat<bits<3> val> {
70 def NotFP : FPFormat<0>;
71 def ZeroArgFP : FPFormat<1>;
72 def OneArgFP : FPFormat<2>;
73 def OneArgFPRW : FPFormat<3>;
74 def TwoArgFP : FPFormat<4>;
75 def CompareFP : FPFormat<5>;
76 def CondMovFP : FPFormat<6>;
77 def SpecialFP : FPFormat<7>;
80 class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr> : Instruction {
81 let Namespace = "X86";
83 bits<8> Opcode = opcod;
85 bits<5> FormBits = Form.Value;
87 bits<2> ImmTypeBits = ImmT.Value;
89 dag OperandList = ops;
90 string AsmString = AsmStr;
93 // Attributes specific to X86 instructions...
95 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
97 bits<4> Prefix = 0; // Which prefix byte does this inst have?
98 FPFormat FPForm; // What flavor of FP instruction is this?
99 bits<3> FPFormBits = 0;
102 class Imp<list<Register> uses, list<Register> defs> {
103 list<Register> Uses = uses;
104 list<Register> Defs = defs;
108 // Prefix byte classes which are used to indicate to the ad-hoc machine code
109 // emitter that various prefix bytes are required.
110 class OpSize { bit hasOpSizePrefix = 1; }
111 class TB { bits<4> Prefix = 1; }
112 class REP { bits<4> Prefix = 2; }
113 class D8 { bits<4> Prefix = 3; }
114 class D9 { bits<4> Prefix = 4; }
115 class DA { bits<4> Prefix = 5; }
116 class DB { bits<4> Prefix = 6; }
117 class DC { bits<4> Prefix = 7; }
118 class DD { bits<4> Prefix = 8; }
119 class DE { bits<4> Prefix = 9; }
120 class DF { bits<4> Prefix = 10; }
123 //===----------------------------------------------------------------------===//
124 // Instruction templates...
126 class I<bits<8> o, Format f, dag ops, string asm> : X86Inst<o, f, NoImm, ops, asm>;
128 class Ii8 <bits<8> o, Format f, dag ops, string asm> : X86Inst<o, f, Imm8 , ops, asm>;
129 class Ii16<bits<8> o, Format f, dag ops, string asm> : X86Inst<o, f, Imm16, ops, asm>;
130 class Ii32<bits<8> o, Format f, dag ops, string asm> : X86Inst<o, f, Imm32, ops, asm>;
132 //===----------------------------------------------------------------------===//
133 // Instruction list...
136 def PHI : I<0, Pseudo, (ops), "PHINODE">; // PHI node.
137 def NOOP : I<0x90, RawFrm, (ops), "nop">; // nop
139 def ADJCALLSTACKDOWN : I<0, Pseudo, (ops), "#ADJCALLSTACKDOWN">;
140 def ADJCALLSTACKUP : I<0, Pseudo, (ops), "#ADJCALLSTACKUP">;
141 def IMPLICIT_USE : I<0, Pseudo, (ops), "#IMPLICIT_USE">;
142 def IMPLICIT_DEF : I<0, Pseudo, (ops), "#IMPLICIT_DEF">;
143 let isTerminator = 1 in
144 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
145 def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL">;
147 //===----------------------------------------------------------------------===//
148 // Control Flow Instructions...
151 // Return instruction...
152 let isTerminator = 1, isReturn = 1, isBarrier = 1 in
153 def RET : I<0xC3, RawFrm, (ops), "ret">;
155 // All branches are RawFrm, Void, Branch, and Terminators
156 let isBranch = 1, isTerminator = 1 in
157 class IBr<bits<8> opcode, dag ops, string asm> : I<opcode, RawFrm, ops, asm>;
160 def JMP : IBr<0xE9, (ops i32imm:$dst), "jmp $dst">;
161 def JB : IBr<0x82, (ops i32imm:$dst), "jb $dst">, TB;
162 def JAE : IBr<0x83, (ops i32imm:$dst), "jae $dst">, TB;
163 def JE : IBr<0x84, (ops i32imm:$dst), "je $dst">, TB;
164 def JNE : IBr<0x85, (ops i32imm:$dst), "jne $dst">, TB;
165 def JBE : IBr<0x86, (ops i32imm:$dst), "jbe $dst">, TB;
166 def JA : IBr<0x87, (ops i32imm:$dst), "ja $dst">, TB;
167 def JS : IBr<0x88, (ops i32imm:$dst), "js $dst">, TB;
168 def JNS : IBr<0x89, (ops i32imm:$dst), "jns $dst">, TB;
169 def JL : IBr<0x8C, (ops i32imm:$dst), "jl $dst">, TB;
170 def JGE : IBr<0x8D, (ops i32imm:$dst), "jge $dst">, TB;
171 def JLE : IBr<0x8E, (ops i32imm:$dst), "jle $dst">, TB;
172 def JG : IBr<0x8F, (ops i32imm:$dst), "jg $dst">, TB;
175 //===----------------------------------------------------------------------===//
176 // Call Instructions...
179 // All calls clobber the non-callee saved registers...
180 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0] in {
181 def CALLpcrel32 : I<0xE8, RawFrm, (ops calltarget:$dst), "call $dst">;
182 def CALL32r : I<0xFF, MRM2r, (ops R32:$dst), "call $dst">;
183 def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst), "call $dst">;
187 //===----------------------------------------------------------------------===//
188 // Miscellaneous Instructions...
190 def LEAVE : I<0xC9, RawFrm,
191 (ops), "leave">, Imp<[EBP,ESP],[EBP,ESP]>;
192 def POP32r : I<0x58, AddRegFrm,
193 (ops R32:$reg), "pop $reg">, Imp<[ESP],[ESP]>;
195 let isTwoAddress = 1 in // R32 = bswap R32
196 def BSWAP32r : I<0xC8, AddRegFrm,
197 (ops R32:$dst, R32:$src), "bswap $dst">, TB;
199 def XCHG8rr : I<0x86, MRMDestReg, // xchg R8, R8
200 (ops R8:$src1, R8:$src2), "xchg $src1, $src2">;
201 def XCHG16rr : I<0x87, MRMDestReg, // xchg R16, R16
202 (ops R16:$src1, R16:$src2), "xchg $src1, $src2">, OpSize;
203 def XCHG32rr : I<0x87, MRMDestReg, // xchg R32, R32
204 (ops R32:$src1, R32:$src2), "xchg $src1, $src2">;
206 def XCHG8mr : I<0x86, MRMDestMem, (ops i8mem:$src1, R8:$src2), "xchg $src1, $src2">;
207 def XCHG16mr : I<0x87, MRMDestMem, (ops i16mem:$src1, R16:$src2), "xchg $src1, $src2">, OpSize;
208 def XCHG32mr : I<0x87, MRMDestMem, (ops i32mem:$src1, R32:$src2), "xchg $src1, $src2">;
209 def XCHG8rm : I<0x86, MRMSrcMem , (ops R8:$src1, i8mem:$src2), "xchg $src1, $src2">;
210 def XCHG16rm : I<0x87, MRMSrcMem , (ops R16:$src1, i16mem:$src2), "xchg $src1, $src2">, OpSize;
211 def XCHG32rm : I<0x87, MRMSrcMem , (ops R32:$src1, i32mem:$src2), "xchg $src1, $src2">;
213 def LEA16r : I<0x8D, MRMSrcMem, (ops R16:$dst, i32mem:$src), "lea $dst, $src">, OpSize;
214 def LEA32r : I<0x8D, MRMSrcMem, (ops R32:$dst, i32mem:$src), "lea $dst, $src">;
217 def REP_MOVSB : I<0xA4, RawFrm, (ops), "rep movsb">,
218 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
219 def REP_MOVSW : I<0xA5, RawFrm, (ops), "rep movsw">,
220 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize;
221 def REP_MOVSD : I<0xA5, RawFrm, (ops), "rep movsd">,
222 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
224 def REP_STOSB : I<0xAA, RawFrm, (ops), "rep stosb">,
225 Imp<[AL,ECX,EDI], [ECX,EDI]>, REP;
226 def REP_STOSW : I<0xAB, RawFrm, (ops), "rep stosw">,
227 Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize;
228 def REP_STOSD : I<0xAB, RawFrm, (ops), "rep stosd">,
229 Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP;
232 //===----------------------------------------------------------------------===//
233 // Input/Output Instructions...
235 def IN8rr : I<0xEC, RawFrm, (ops),
236 "in %AL, %DX">, Imp<[DX], [AL]>;
237 def IN16rr : I<0xED, RawFrm, (ops),
238 "in %AX, %DX">, Imp<[DX], [AX]>, OpSize;
239 def IN32rr : I<0xED, RawFrm, (ops),
240 "in %EAX, %DX">, Imp<[DX],[EAX]>;
242 def IN8ri : Ii16<0xE4, RawFrm, (ops i16imm:$port),
243 "in %AL, $port">, Imp<[], [AL]>;
244 def IN16ri : Ii16<0xE5, RawFrm, (ops i16imm:$port),
245 "in %AX, $port">, Imp<[], [AX]>, OpSize;
246 def IN32ri : Ii16<0xE5, RawFrm, (ops i16imm:$port),
247 "in %EAX, $port">, Imp<[],[EAX]>;
249 def OUT8rr : I<0xEE, RawFrm, (ops),
250 "out %DX, %AL">, Imp<[DX, AL], []>;
251 def OUT16rr : I<0xEF, RawFrm, (ops),
252 "out %DX, %AX">, Imp<[DX, AX], []>, OpSize;
253 def OUT32rr : I<0xEF, RawFrm, (ops),
254 "out %DX, %EAX">, Imp<[DX, EAX], []>;
256 def OUT8ir : Ii16<0xE6, RawFrm, (ops i16imm:$port),
257 "out $port, %AL">, Imp<[AL], []>;
258 def OUT16ir : Ii16<0xE7, RawFrm, (ops i16imm:$port),
259 "out $port, %AX">, Imp<[AX], []>, OpSize;
260 def OUT32ir : Ii16<0xE7, RawFrm, (ops i16imm:$port),
261 "out $port, %EAX">, Imp<[EAX], []>;
263 //===----------------------------------------------------------------------===//
264 // Move Instructions...
266 def MOV8rr : I<0x88, MRMDestReg, (ops R8 :$dst, R8 :$src), "mov $dst, $src">;
267 def MOV16rr : I<0x89, MRMDestReg, (ops R16:$dst, R16:$src), "mov $dst, $src">, OpSize;
268 def MOV32rr : I<0x89, MRMDestReg, (ops R32:$dst, R32:$src), "mov $dst, $src">;
269 def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops R8 :$dst, i8imm :$src), "mov $dst, $src">;
270 def MOV16ri : Ii16<0xB8, AddRegFrm, (ops R16:$dst, i16imm:$src), "mov $dst, $src">, OpSize;
271 def MOV32ri : Ii32<0xB8, AddRegFrm, (ops R32:$dst, i32imm:$src), "mov $dst, $src">;
272 def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src), "mov $dst, $src">;
273 def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src), "mov $dst, $src">, OpSize;
274 def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), "mov $dst, $src">;
276 def MOV8rm : I<0x8A, MRMSrcMem, (ops R8 :$dst, i8mem :$src), "mov $dst, $src">;
277 def MOV16rm : I<0x8B, MRMSrcMem, (ops R16:$dst, i16mem:$src), "mov $dst, $src">, OpSize;
278 def MOV32rm : I<0x8B, MRMSrcMem, (ops R32:$dst, i32mem:$src), "mov $dst, $src">;
280 def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, R8 :$src), "mov $dst, $src">;
281 def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, R16:$src), "mov $dst, $src">, OpSize;
282 def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, R32:$src), "mov $dst, $src">;
284 //===----------------------------------------------------------------------===//
285 // Fixed-Register Multiplication and Division Instructions...
288 // Extra precision multiplication
289 def MUL8r : I<0xF6, MRM4r, (ops R8:$src), "mul $src">,
290 Imp<[AL],[AX]>; // AL,AH = AL*R8
291 def MUL16r : I<0xF7, MRM4r, (ops R16:$src), "mul $src">,
292 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
293 def MUL32r : I<0xF7, MRM4r, (ops R32:$src), "mul $src">,
294 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
295 def MUL8m : I<0xF6, MRM4m, (ops i8mem :$src),
296 "mul $src">, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
297 def MUL16m : I<0xF7, MRM4m, (ops i16mem:$src),
298 "mul $src">, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*[mem16]
299 def MUL32m : I<0xF7, MRM4m, (ops i32mem:$src),
300 "mul $src">, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
302 // unsigned division/remainder
303 def DIV8r : I<0xF6, MRM6r, (ops R8:$src), "div $src">,
304 Imp<[AX],[AX]>; // AX/r8 = AL,AH
305 def DIV16r : I<0xF7, MRM6r, (ops R16:$src), "div $src">,
306 Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
307 def DIV32r : I<0xF7, MRM6r, (ops R32:$src), "div $src">,
308 Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
309 def DIV8m : I<0xF6, MRM6m, (ops i8mem:$src), "div $src">, Imp<[AX],[AX]>; // AX/[mem8] = AL,AH
310 def DIV16m : I<0xF7, MRM6m, (ops i16mem:$src), "div $src">, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[mem16] = AX,DX
311 def DIV32m : I<0xF7, MRM6m, (ops i32mem:$src), "div $src">, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX
313 // Signed division/remainder.
314 def IDIV8r : I<0xF6, MRM7r, (ops R8:$src), "idiv $src">,
315 Imp<[AX],[AX]>; // AX/r8 = AL,AH
316 def IDIV16r: I<0xF7, MRM7r, (ops R16:$src), "idiv $src">,
317 Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
318 def IDIV32r: I<0xF7, MRM7r, (ops R32:$src), "idiv $src">,
319 Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
320 def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src), "idiv $src">, Imp<[AX],[AX]>; // AX/[mem8] = AL,AH
321 def IDIV16m: I<0xF7, MRM7m, (ops i16mem:$src), "idiv $src">, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[mem16] = AX,DX
322 def IDIV32m: I<0xF7, MRM7m, (ops i32mem:$src), "idiv $src">, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX
324 // Sign-extenders for division.
325 def CBW : I<0x98, RawFrm, (ops), "cbw">, Imp<[AL],[AH]>; // AX = signext(AL)
326 def CWD : I<0x99, RawFrm, (ops), "cwd">, Imp<[AX],[DX]>; // DX:AX = signext(AX)
327 def CDQ : I<0x99, RawFrm, (ops), "cdq">, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX)
330 //===----------------------------------------------------------------------===//
331 // Two address Instructions...
333 let isTwoAddress = 1 in {
336 def CMOVB16rr : I<0x42, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
337 "cmovb $dst, $src2">, TB, OpSize; // if <u, R16 = R16
338 def CMOVB16rm : I<0x42, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
339 "cmovb $dst, $src2">, TB, OpSize; // if <u, R16 = [mem16]
340 def CMOVB32rr : I<0x42, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
341 "cmovb $dst, $src2">, TB; // if <u, R32 = R32
342 def CMOVB32rm : I<0x42, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
343 "cmovb $dst, $src2">, TB; // if <u, R32 = [mem32]
345 def CMOVAE16rr: I<0x43, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
346 "cmovae $dst, $src2">, TB, OpSize; // if >=u, R16 = R16
347 def CMOVAE16rm: I<0x43, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
348 "cmovae $dst, $src2">, TB, OpSize; // if >=u, R16 = [mem16]
349 def CMOVAE32rr: I<0x43, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
350 "cmovae $dst, $src2">, TB; // if >=u, R32 = R32
351 def CMOVAE32rm: I<0x43, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
352 "cmovae $dst, $src2">, TB; // if >=u, R32 = [mem32]
354 def CMOVE16rr : I<0x44, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
355 "cmove $dst, $src2">, TB, OpSize; // if ==, R16 = R16
356 def CMOVE16rm : I<0x44, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
357 "cmove $dst, $src2">, TB, OpSize; // if ==, R16 = [mem16]
358 def CMOVE32rr : I<0x44, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
359 "cmove $dst, $src2">, TB; // if ==, R32 = R32
360 def CMOVE32rm : I<0x44, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
361 "cmove $dst, $src2">, TB; // if ==, R32 = [mem32]
363 def CMOVNE16rr: I<0x45, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
364 "cmovne $dst, $src2">, TB, OpSize; // if !=, R16 = R16
365 def CMOVNE16rm: I<0x45, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
366 "cmovne $dst, $src2">, TB, OpSize; // if !=, R16 = [mem16]
367 def CMOVNE32rr: I<0x45, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
368 "cmovne $dst, $src2">, TB; // if !=, R32 = R32
369 def CMOVNE32rm: I<0x45, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
370 "cmovne $dst, $src2">, TB; // if !=, R32 = [mem32]
372 def CMOVBE16rr: I<0x46, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
373 "cmovbe $dst, $src2">, TB, OpSize; // if <=u, R16 = R16
374 def CMOVBE16rm: I<0x46, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
375 "cmovbe $dst, $src2">, TB, OpSize; // if <=u, R16 = [mem16]
376 def CMOVBE32rr: I<0x46, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
377 "cmovbe $dst, $src2">, TB; // if <=u, R32 = R32
378 def CMOVBE32rm: I<0x46, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
379 "cmovbe $dst, $src2">, TB; // if <=u, R32 = [mem32]
381 def CMOVA16rr : I<0x47, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
382 "cmova $dst, $src2">, TB, OpSize; // if >u, R16 = R16
383 def CMOVA16rm : I<0x47, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
384 "cmova $dst, $src2">, TB, OpSize; // if >u, R16 = [mem16]
385 def CMOVA32rr : I<0x47, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
386 "cmova $dst, $src2">, TB; // if >u, R32 = R32
387 def CMOVA32rm : I<0x47, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
388 "cmova $dst, $src2">, TB; // if >u, R32 = [mem32]
390 def CMOVS16rr : I<0x48, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
391 "cmovs $dst, $src2">, TB, OpSize; // if signed, R16 = R16
392 def CMOVS16rm : I<0x48, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
393 "cmovs $dst, $src2">, TB, OpSize; // if signed, R16 = [mem16]
394 def CMOVS32rr : I<0x48, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
395 "cmovs $dst, $src2">, TB; // if signed, R32 = R32
396 def CMOVS32rm : I<0x48, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
397 "cmovs $dst, $src2">, TB; // if signed, R32 = [mem32]
399 def CMOVNS16rr: I<0x49, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
400 "cmovns $dst, $src2">, TB, OpSize; // if !signed, R16 = R16
401 def CMOVNS16rm: I<0x49, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
402 "cmovns $dst, $src2">, TB, OpSize; // if !signed, R16 = [mem16]
403 def CMOVNS32rr: I<0x49, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
404 "cmovns $dst, $src2">, TB; // if !signed, R32 = R32
405 def CMOVNS32rm: I<0x49, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
406 "cmovns $dst, $src2">, TB; // if !signed, R32 = [mem32]
408 def CMOVL16rr : I<0x4C, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
409 "cmovl $dst, $src2">, TB, OpSize; // if <s, R16 = R16
410 def CMOVL16rm : I<0x4C, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
411 "cmovl $dst, $src2">, TB, OpSize; // if <s, R16 = [mem16]
412 def CMOVL32rr : I<0x4C, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
413 "cmovl $dst, $src2">, TB; // if <s, R32 = R32
414 def CMOVL32rm : I<0x4C, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
415 "cmovl $dst, $src2">, TB; // if <s, R32 = [mem32]
417 def CMOVGE16rr: I<0x4D, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
418 "cmovge $dst, $src2">, TB, OpSize; // if >=s, R16 = R16
419 def CMOVGE16rm: I<0x4D, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
420 "cmovge $dst, $src2">, TB, OpSize; // if >=s, R16 = [mem16]
421 def CMOVGE32rr: I<0x4D, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
422 "cmovge $dst, $src2">, TB; // if >=s, R32 = R32
423 def CMOVGE32rm: I<0x4D, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
424 "cmovge $dst, $src2">, TB; // if >=s, R32 = [mem32]
426 def CMOVLE16rr: I<0x4E, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
427 "cmovle $dst, $src2">, TB, OpSize; // if <=s, R16 = R16
428 def CMOVLE16rm: I<0x4E, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
429 "cmovle $dst, $src2">, TB, OpSize; // if <=s, R16 = [mem16]
430 def CMOVLE32rr: I<0x4E, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
431 "cmovle $dst, $src2">, TB; // if <=s, R32 = R32
432 def CMOVLE32rm: I<0x4E, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
433 "cmovle $dst, $src2">, TB; // if <=s, R32 = [mem32]
435 def CMOVG16rr : I<0x4F, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
436 "cmovg $dst, $src2">, TB, OpSize; // if >s, R16 = R16
437 def CMOVG16rm : I<0x4F, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
438 "cmovg $dst, $src2">, TB, OpSize; // if >s, R16 = [mem16]
439 def CMOVG32rr : I<0x4F, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
440 "cmovg $dst, $src2">, TB; // if >s, R32 = R32
441 def CMOVG32rm : I<0x4F, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
442 "cmovg $dst, $src2">, TB; // if >s, R32 = [mem32]
444 // unary instructions
445 def NEG8r : I<0xF6, MRM3r, (ops R8 :$dst, R8 :$src), "neg $dst">;
446 def NEG16r : I<0xF7, MRM3r, (ops R16:$dst, R16:$src), "neg $dst">, OpSize;
447 def NEG32r : I<0xF7, MRM3r, (ops R32:$dst, R32:$src), "neg $dst">;
448 let isTwoAddress = 0 in {
449 def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg $dst">;
450 def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg $dst">, OpSize;
451 def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg $dst">;
454 def NOT8r : I<0xF6, MRM2r, (ops R8 :$dst, R8 :$src), "not $dst">;
455 def NOT16r : I<0xF7, MRM2r, (ops R16:$dst, R16:$src), "not $dst">, OpSize;
456 def NOT32r : I<0xF7, MRM2r, (ops R32:$dst, R32:$src), "not $dst">;
457 let isTwoAddress = 0 in {
458 def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not $dst">;
459 def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not $dst">, OpSize;
460 def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not $dst">;
463 def INC8r : I<0xFE, MRM0r, (ops R8 :$dst, R8 :$src), "inc $dst">;
464 def INC16r : I<0xFF, MRM0r, (ops R16:$dst, R16:$src), "inc $dst">, OpSize;
465 def INC32r : I<0xFF, MRM0r, (ops R32:$dst, R32:$src), "inc $dst">;
466 let isTwoAddress = 0 in {
467 def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc $dst">;
468 def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc $dst">, OpSize;
469 def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc $dst">;
472 def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec $dst">;
473 def DEC16r : I<0xFF, MRM1r, (ops R16:$dst, R16:$src), "dec $dst">, OpSize;
474 def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec $dst">;
476 let isTwoAddress = 0 in {
477 def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec $dst">;
478 def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec $dst">, OpSize;
479 def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec $dst">;
482 // Logical operators...
483 def AND8rr : I<0x20, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), "and $dst, $src2">;
484 def AND16rr : I<0x21, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), "and $dst, $src2">, OpSize;
485 def AND32rr : I<0x21, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), "and $dst, $src2">;
487 def AND8rm : I<0x22, MRMSrcMem , (ops R8 :$dst, R8 :$src1, i8mem :$src2), "and $dst, $src2">;
488 def AND16rm : I<0x23, MRMSrcMem , (ops R16:$dst, R16:$src1, i16mem:$src2), "and $dst, $src2">, OpSize;
489 def AND32rm : I<0x23, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2), "and $dst, $src2">;
491 def AND8ri : Ii8 <0x80, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm :$src2),
493 def AND16ri : Ii16<0x81, MRM4r, (ops R16:$dst, R16:$src1, i16imm:$src2),
494 "and $dst, $src2">, OpSize;
495 def AND32ri : Ii32<0x81, MRM4r, (ops R32:$dst, R32:$src1, i32imm:$src2),
497 def AND16ri8 : Ii8<0x83, MRM4r, (ops R16:$dst, R16:$src1, i8imm:$src2),
498 "and $dst, $src2" >, OpSize;
499 def AND32ri8 : Ii8<0x83, MRM4r, (ops R32:$dst, R32:$src1, i8imm:$src2),
502 let isTwoAddress = 0 in {
503 def AND8mr : I<0x20, MRMDestMem, (ops i8mem :$dst, R8 :$src), "and $dst, $src">;
504 def AND16mr : I<0x21, MRMDestMem, (ops i16mem:$dst, R16:$src), "and $dst, $src">, OpSize;
505 def AND32mr : I<0x21, MRMDestMem, (ops i32mem:$dst, R32:$src), "and $dst, $src">;
506 def AND8mi : Ii8 <0x80, MRM4m, (ops i8mem :$dst, i8imm :$src), "and $dst, $src">;
507 def AND16mi : Ii16<0x81, MRM4m, (ops i16mem:$dst, i16imm:$src), "and $dst, $src">, OpSize;
508 def AND32mi : Ii32<0x81, MRM4m, (ops i32mem:$dst, i32imm:$src), "and $dst, $src">;
509 def AND16mi8 : Ii8 <0x83, MRM4m, (ops i16mem:$dst, i8imm :$src), "and $dst, $src">, OpSize;
510 def AND32mi8 : Ii8 <0x83, MRM4m, (ops i32mem:$dst, i8imm :$src), "and $dst, $src">;
514 def OR8rr : I<0x08, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
516 def OR16rr : I<0x09, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
517 "or $dst, $src2">, OpSize;
518 def OR32rr : I<0x09, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
520 def OR8rm : I<0x0A, MRMSrcMem , (ops R8 :$dst, R8 :$src1, i8mem :$src2),
522 def OR16rm : I<0x0B, MRMSrcMem , (ops R16:$dst, R16:$src1, i16mem:$src2),
523 "or $dst, $src2">, OpSize;
524 def OR32rm : I<0x0B, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2),
527 def OR8ri : Ii8 <0x80, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
529 def OR16ri : Ii16<0x81, MRM1r, (ops R16:$dst, R16:$src1, i16imm:$src2),
530 "or $dst, $src2">, OpSize;
531 def OR32ri : Ii32<0x81, MRM1r, (ops R32:$dst, R32:$src1, i32imm:$src2),
534 def OR16ri8 : Ii8<0x83, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
535 "or $dst, $src2">, OpSize;
536 def OR32ri8 : Ii8<0x83, MRM1r, (ops R32:$dst, R32:$src1, i8imm:$src2),
538 let isTwoAddress = 0 in {
539 def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, R8:$src),
541 def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, R16:$src),
542 "or $dst, $src">, OpSize;
543 def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, R32:$src),
545 def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src),
547 def OR16mi : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src),
548 "or $dst, $src">, OpSize;
549 def OR32mi : Ii32<0x81, MRM1m, (ops i32mem:$dst, i32imm:$src),
551 def OR16mi8 : Ii8<0x83, MRM1m, (ops i16mem:$dst, i8imm:$src),
552 "or $dst, $src">, OpSize;
553 def OR32mi8 : Ii8<0x83, MRM1m, (ops i32mem:$dst, i8imm:$src),
558 def XOR8rr : I<0x30, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), "xor $dst, $src2">;
559 def XOR16rr : I<0x31, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), "xor $dst, $src2">, OpSize;
560 def XOR32rr : I<0x31, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), "xor $dst, $src2">;
561 def XOR8rm : I<0x32, MRMSrcMem , (ops R8 :$dst, R8:$src1, i8mem :$src2), "xor $dst, $src2">;
562 def XOR16rm : I<0x33, MRMSrcMem , (ops R16:$dst, R8:$src1, i16mem:$src2), "xor $dst, $src2">, OpSize;
563 def XOR32rm : I<0x33, MRMSrcMem , (ops R32:$dst, R8:$src1, i32mem:$src2), "xor $dst, $src2">;
565 def XOR8ri : Ii8 <0x80, MRM6r, (ops R8:$dst, R8:$src1, i8imm:$src2), "xor $dst, $src2">;
566 def XOR16ri : Ii16 <0x81, MRM6r, (ops R16:$dst, R16:$src1, i16imm:$src2), "xor $dst, $src2">, OpSize;
567 def XOR32ri : Ii32 <0x81, MRM6r, (ops R32:$dst, R32:$src1, i32imm:$src2), "xor $dst, $src2">;
568 def XOR16ri8 : Ii8<0x83, MRM6r, (ops R16:$dst, R16:$src1, i8imm:$src2),
569 "xor $dst, $src2">, OpSize;
570 def XOR32ri8 : Ii8<0x83, MRM6r, (ops R32:$dst, R32:$src1, i8imm:$src2),
572 let isTwoAddress = 0 in {
573 def XOR8mr : I<0x30, MRMDestMem, (ops i8mem :$dst, R8 :$src), "xor $dst, $src">;
574 def XOR16mr : I<0x31, MRMDestMem, (ops i16mem:$dst, R16:$src), "xor $dst, $src">, OpSize;
575 def XOR32mr : I<0x31, MRMDestMem, (ops i32mem:$dst, R32:$src), "xor $dst, $src">;
576 def XOR8mi : Ii8 <0x80, MRM6m, (ops i8mem :$dst, i8imm :$src), "xor $dst, $src">;
577 def XOR16mi : Ii16<0x81, MRM6m, (ops i16mem:$dst, i16imm:$src), "xor $dst, $src">, OpSize;
578 def XOR32mi : Ii32<0x81, MRM6m, (ops i32mem:$dst, i32imm:$src), "xor $dst, $src">;
579 def XOR16mi8 : Ii8 <0x83, MRM6m, (ops i16mem:$dst, i8imm :$src), "xor $dst, $src">, OpSize;
580 def XOR32mi8 : Ii8 <0x83, MRM6m, (ops i32mem:$dst, i8imm :$src), "xor $dst, $src">;
583 // Shift instructions
584 // FIXME: provide shorter instructions when imm8 == 1
585 def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src), "shl $dst, %CL">, Imp<[CL],[]>;
586 def SHL16rCL : I<0xD3, MRM4r, (ops R16:$dst, R16:$src), "shl $dst, %CL">, Imp<[CL],[]>, OpSize;
587 def SHL32rCL : I<0xD3, MRM4r, (ops R32:$dst, R32:$src), "shl $dst, %CL">, Imp<[CL],[]>;
588 def SHL8ri : Ii8<0xC0, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
590 def SHL16ri : Ii8<0xC1, MRM4r, (ops R16:$dst, R16:$src1, i8imm:$src2),
591 "shl $dst, $src2">, OpSize;
592 def SHL32ri : Ii8<0xC1, MRM4r, (ops R32:$dst, R32:$src1, i8imm:$src2),
595 let isTwoAddress = 0 in {
596 def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst), "shl $dst, %CL">, Imp<[CL],[]>;
597 def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst), "shl $dst, %CL">, Imp<[CL],[]>, OpSize;
598 def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst), "shl $dst, %CL">, Imp<[CL],[]>;
599 def SHL8mi : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src), "shl $dst, $src">;
600 def SHL16mi : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src), "shl $dst, $src">, OpSize;
601 def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src), "shl $dst, $src">;
604 def SHR8rCL : I<0xD2, MRM5r, (ops R8 :$dst, R8 :$src), "shr $dst, %CL">, Imp<[CL],[]>;
605 def SHR16rCL : I<0xD3, MRM5r, (ops R16:$dst, R16:$src), "shr $dst, %CL">, Imp<[CL],[]>, OpSize;
606 def SHR32rCL : I<0xD3, MRM5r, (ops R32:$dst, R32:$src), "shr $dst, %CL">, Imp<[CL],[]>;
608 def SHR8ri : Ii8 <0xC0, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2), "shr $dst, $src2">;
609 def SHR16ri : Ii8 <0xC1, MRM5r, (ops R16:$dst, R16:$src1, i8imm:$src2), "shr $dst, $src2">, OpSize;
610 def SHR32ri : Ii8 <0xC1, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2), "shr $dst, $src2">;
612 let isTwoAddress = 0 in {
613 def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst), "shr $dst, %CL">, Imp<[CL],[]>;
614 def SHR16mCL : I<0xD3, MRM5m, (ops i16mem:$dst), "shr $dst, %CL">, Imp<[CL],[]>, OpSize;
615 def SHR32mCL : I<0xD3, MRM5m, (ops i32mem:$dst), "shr $dst, %CL">, Imp<[CL],[]>;
616 def SHR8mi : Ii8<0xC0, MRM5m, (ops i8mem :$dst, i8imm:$src), "shr $dst, $src">;
617 def SHR16mi : Ii8<0xC1, MRM5m, (ops i16mem:$dst, i8imm:$src), "shr $dst, $src">, OpSize;
618 def SHR32mi : Ii8<0xC1, MRM5m, (ops i32mem:$dst, i8imm:$src), "shr $dst, $src">;
621 def SAR8rCL : I<0xD2, MRM7r, (ops R8 :$dst, R8 :$src), "sar $dst, %CL">, Imp<[CL],[]>;
622 def SAR16rCL : I<0xD3, MRM7r, (ops R16:$dst, R16:$src), "sar $dst, %CL">, Imp<[CL],[]>, OpSize;
623 def SAR32rCL : I<0xD3, MRM7r, (ops R32:$dst, R32:$src), "sar $dst, %CL">, Imp<[CL],[]>;
625 def SAR8ri : Ii8<0xC0, MRM7r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
627 def SAR16ri : Ii8<0xC1, MRM7r, (ops R16:$dst, R16:$src1, i8imm:$src2),
628 "sar $dst, $src2">, OpSize;
629 def SAR32ri : Ii8<0xC1, MRM7r, (ops R32:$dst, R32:$src1, i8imm:$src2),
631 let isTwoAddress = 0 in {
632 def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst), "sar $dst, %CL">, Imp<[CL],[]>;
633 def SAR16mCL : I<0xD3, MRM7m, (ops i16mem:$dst), "sar $dst, %CL">, Imp<[CL],[]>, OpSize;
634 def SAR32mCL : I<0xD3, MRM7m, (ops i32mem:$dst), "sar $dst, %CL">, Imp<[CL],[]>;
635 def SAR8mi : Ii8<0xC0, MRM7m, (ops i8mem :$dst, i8imm:$src), "sar $dst, $src">;
636 def SAR16mi : Ii8<0xC1, MRM7m, (ops i16mem:$dst, i8imm:$src), "sar $dst, $src">, OpSize;
637 def SAR32mi : Ii8<0xC1, MRM7m, (ops i32mem:$dst, i8imm:$src), "sar $dst, $src">;
640 def SHLD32rrCL : I<0xA5, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
641 "shld $dst, $src2, %CL">, Imp<[CL],[]>, TB;
642 def SHRD32rrCL : I<0xAD, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
643 "shrd $dst, $src2, %CL">, Imp<[CL],[]>, TB;
644 def SHLD32rri8 : Ii8<0xA4, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3),
645 "shld $dst, $src2, $src3">, TB;
646 def SHRD32rri8 : Ii8<0xAC, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3),
647 "shrd $dst, $src2, $src3">, TB;
649 let isTwoAddress = 0 in {
650 def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, R32:$src2),
651 "shld $dst, $src2, %CL">, Imp<[CL],[]>, TB;
652 def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, R32:$src2),
653 "shrd $dst, $src2, %CL">, Imp<[CL],[]>, TB;
654 def SHLD32mri8 : Ii8<0xA4, MRMDestMem, (ops i32mem:$dst, R32:$src2, i8imm:$src3),
655 "shld $dst, $src2, $src3">, TB;
656 def SHRD32mri8 : Ii8<0xAC, MRMDestMem, (ops i32mem:$dst, R32:$src2, i8imm:$src3),
657 "shrd $dst, $src2, $src3">, TB;
662 def ADD8rr : I<0x00, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), "add $dst, $src2">;
663 def ADD16rr : I<0x01, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), "add $dst, $src2">, OpSize;
664 def ADD32rr : I<0x01, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), "add $dst, $src2">;
665 def ADD8rm : I<0x02, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2), "add $dst, $src2">;
666 def ADD16rm : I<0x03, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), "add $dst, $src2">, OpSize;
667 def ADD32rm : I<0x03, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), "add $dst, $src2">;
669 def ADD8ri : Ii8 <0x80, MRM0r, (ops R8:$dst, R8:$src1, i8imm:$src2), "add $dst, $src2">;
670 def ADD16ri : Ii16 <0x81, MRM0r, (ops R16:$dst, R16:$src1, i16imm:$src2), "add $dst, $src2">, OpSize;
671 def ADD32ri : Ii32 <0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2), "add $dst, $src2">;
673 def ADD16ri8 : Ii8 <0x83, MRM0r, (ops R16:$dst, R16:$src1, i8imm:$src2), "add $dst, $src2">, OpSize;
674 def ADD32ri8 : Ii8 <0x83, MRM0r, (ops R32:$dst, R32:$src1, i8imm:$src2), "add $dst, $src2">;
676 let isTwoAddress = 0 in {
677 def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, R8 :$src2), "add $dst, $src2">;
678 def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, R16:$src2), "add $dst, $src2">, OpSize;
679 def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, R32:$src2), "add $dst, $src2">;
680 def ADD8mi : Ii8 <0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2), "add $dst, $src2">;
681 def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2), "add $dst, $src2">, OpSize;
682 def ADD32mi : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2), "add $dst, $src2">;
683 def ADD16mi8 : Ii8 <0x83, MRM0m, (ops i16mem:$dst, i8imm :$src2), "add $dst, $src2">, OpSize;
684 def ADD32mi8 : Ii8 <0x83, MRM0m, (ops i32mem:$dst, i8imm :$src2), "add $dst, $src2">;
687 def ADC32rr : I<0x11, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), "adc $dst, $src2">;
688 def ADC32rm : I<0x13, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2), "adc $dst, $src2">;
689 def ADC32ri : Ii32<0x81, MRM2r, (ops R32:$dst, R32:$src1, i32imm:$src2), "adc $dst, $src2">;
690 def ADC32ri8 : Ii8 <0x83, MRM2r, (ops R32:$dst, R32:$src1, i8imm:$src2), "adc $dst, $src2">;
692 let isTwoAddress = 0 in {
693 def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, R32:$src2), "adc $dst, $src2">;
694 def ADC32mi : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2), "adc $dst, $src2">;
695 def ADC32mi8 : Ii8 <0x83, MRM2m, (ops i32mem:$dst, i8imm :$src2), "adc $dst, $src2">;
698 def SUB8rr : I<0x28, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), "sub $dst, $src2">;
699 def SUB16rr : I<0x29, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), "sub $dst, $src2">, OpSize;
700 def SUB32rr : I<0x29, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), "sub $dst, $src2">;
701 def SUB8rm : I<0x2A, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2), "sub $dst, $src2">;
702 def SUB16rm : I<0x2B, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), "sub $dst, $src2">, OpSize;
703 def SUB32rm : I<0x2B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), "sub $dst, $src2">;
705 def SUB8ri : Ii8 <0x80, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2),
707 def SUB16ri : Ii16<0x81, MRM5r, (ops R16:$dst, R16:$src1, i16imm:$src2),
708 "sub $dst, $src2">, OpSize;
709 def SUB32ri : Ii32<0x81, MRM5r, (ops R32:$dst, R32:$src1, i32imm:$src2),
711 def SUB16ri8 : Ii8<0x83, MRM5r, (ops R16:$dst, R16:$src1, i8imm:$src2),
712 "sub $dst, $src2">, OpSize;
713 def SUB32ri8 : Ii8<0x83, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2),
715 let isTwoAddress = 0 in {
716 def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, R8 :$src2), "sub $dst, $src2">;
717 def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, R16:$src2), "sub $dst, $src2">, OpSize;
718 def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, R32:$src2), "sub $dst, $src2">;
719 def SUB8mi : Ii8 <0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2), "sub $dst, $src2">;
720 def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2), "sub $dst, $src2">, OpSize;
721 def SUB32mi : Ii32<0x81, MRM5m, (ops i32mem:$dst, i32imm:$src2), "sub $dst, $src2">;
722 def SUB16mi8 : Ii8 <0x83, MRM5m, (ops i16mem:$dst, i8imm :$src2), "sub $dst, $src2">, OpSize;
723 def SUB32mi8 : Ii8 <0x83, MRM5m, (ops i32mem:$dst, i8imm :$src2), "sub $dst, $src2">;
726 def SBB32rr : I<0x19, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
728 let isTwoAddress = 0 in {
729 def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, R32:$src2), "sbb $dst, $src2">;
730 def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2), "sbb $dst, $src2">;
731 def SBB32mi8 : Ii8 <0x83, MRM3m, (ops i32mem:$dst, i8imm :$src2), "sbb $dst, $src2">;
733 def SBB32rm : I<0x1B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
735 def SBB32ri : Ii32<0x81, MRM3r, (ops R32:$dst, R32:$src1, i32imm:$src2),
737 def SBB32ri8 : Ii8<0x83, MRM3r, (ops R32:$dst, R32:$src1, i8imm:$src2),
740 def IMUL16rr : I<0xAF, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2), "imul $dst, $src2">, TB, OpSize;
741 def IMUL32rr : I<0xAF, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), "imul $dst, $src2">, TB;
742 def IMUL16rm : I<0xAF, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), "imul $dst, $src2">, TB, OpSize;
743 def IMUL32rm : I<0xAF, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), "imul $dst, $src2">, TB ;
745 } // end Two Address instructions
747 // Suprisingly enough, these are not two address instructions!
748 def IMUL16rri : Ii16<0x69, MRMSrcReg, (ops R16:$dst, R16:$src1, i16imm:$src2),
749 "imul $dst, $src1, $src2">, OpSize; // R16 = R16*I16
750 def IMUL32rri : Ii32<0x69, MRMSrcReg, (ops R32:$dst, R32:$src1, i32imm:$src2),
751 "imul $dst, $src1, $src2">; // R32 = R32*I32
752 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, (ops R16:$dst, R16:$src1, i8imm:$src2),
753 "imul $dst, $src1, $src2">, OpSize; // R16 = R16*I8
754 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, (ops R32:$dst, R32:$src1, i8imm:$src2),
755 "imul $dst, $src1, $src2">; // R32 = R32*I8
757 def IMUL16rmi : Ii16<0x69, MRMSrcMem, (ops R32:$dst, i16mem:$src1, i16imm:$src2),
758 "imul $dst, $src1, $src2">, OpSize; // R16 = [mem16]*I16
759 def IMUL32rmi : Ii32<0x69, MRMSrcMem, (ops R32:$dst, i32mem:$src1, i32imm:$src2),
760 "imul $dst, $src1, $src2">; // R32 = [mem32]*I32
761 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, (ops R32:$dst, i16mem:$src1, i8imm :$src2),
762 "imul $dst, $src1, $src2">, OpSize; // R16 = [mem16]*I8
763 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, (ops R32:$dst, i32mem:$src1, i8imm: $src2),
764 "imul $dst, $src1, $src2">; // R32 = [mem32]*I8
766 //===----------------------------------------------------------------------===//
767 // Test instructions are just like AND, except they don't generate a result.
768 def TEST8rr : I<0x84, MRMDestReg, (ops R8:$src1, R8:$src2),
769 "test $src1, $src2">;
770 def TEST16rr : I<0x85, MRMDestReg, (ops R16:$src1, R16:$src2),
771 "test $src1, $src2">, OpSize;
772 def TEST32rr : I<0x85, MRMDestReg, (ops R32:$src1, R32:$src2),
773 "test $src1, $src2">;
774 def TEST8mr : I<0x84, MRMDestMem, (ops i8mem :$src1, R8 :$src2),
775 "test $src1, $src2">;
776 def TEST16mr : I<0x85, MRMDestMem, (ops i16mem:$src1, R16:$src2),
777 "test $src1, $src2">, OpSize;
778 def TEST32mr : I<0x85, MRMDestMem, (ops i32mem:$src1, R32:$src2),
779 "test $src1, $src2">;
780 def TEST8rm : I<0x84, MRMSrcMem, (ops R8 :$src1, i8mem :$src2),
781 "test $src1, $src2">;
782 def TEST16rm : I<0x85, MRMSrcMem, (ops R16:$src1, i16mem:$src2),
783 "test $src1, $src2">, OpSize;
784 def TEST32rm : I<0x85, MRMSrcMem, (ops R32:$src1, i32mem:$src2),
785 "test $src1, $src2">;
787 def TEST8ri : Ii8 <0xF6, MRM0r, (ops R8:$dst, i8imm:$src),
788 "test $dst, $src">; // flags = R8 & imm8
789 def TEST16ri : Ii16<0xF7, MRM0r, (ops R16:$dst, i16imm:$src),
790 "test $dst, $src">, OpSize; // flags = R16 & imm16
791 def TEST32ri : Ii32<0xF7, MRM0r, (ops R32:$dst, i32imm:$src),
792 "test $dst, $src">; // flags = R32 & imm32
793 def TEST8mi : Ii8 <0xF6, MRM0m, (ops i32mem:$dst, i8imm:$src),
794 "test $dst, $src">; // flags = [mem8] & imm8
795 def TEST16mi : Ii16<0xF7, MRM0m, (ops i16mem:$dst, i16imm:$src),
796 "test $dst, $src">, OpSize; // flags = [mem16] & imm16
797 def TEST32mi : Ii32<0xF7, MRM0m, (ops i32mem:$dst, i32imm:$src),
798 "test $dst, $src">; // flags = [mem32] & imm32
802 // Condition code ops, incl. set if equal/not equal/...
803 def SAHF : I<0x9E, RawFrm, (ops), "sahf">, Imp<[AH],[]>; // flags = AH
804 def LAHF : I<0x9F, RawFrm, (ops), "lahf">, Imp<[],[AH]>; // AH = flags
806 def SETBr : I<0x92, MRM0r, (ops R8 :$dst), "setb $dst">, TB; // R8 = < unsign
807 def SETBm : I<0x92, MRM0m, (ops i8mem:$dst), "setb $dst">, TB; // [mem8] = < unsign
808 def SETAEr : I<0x93, MRM0r, (ops R8 :$dst), "setae $dst">, TB; // R8 = >= unsign
809 def SETAEm : I<0x93, MRM0m, (ops i8mem:$dst), "setae $dst">, TB; // [mem8] = >= unsign
810 def SETEr : I<0x94, MRM0r, (ops R8 :$dst), "sete $dst">, TB; // R8 = ==
811 def SETEm : I<0x94, MRM0m, (ops i8mem:$dst), "sete $dst">, TB; // [mem8] = ==
812 def SETNEr : I<0x95, MRM0r, (ops R8 :$dst), "setne $dst">, TB; // R8 = !=
813 def SETNEm : I<0x95, MRM0m, (ops i8mem:$dst), "setne $dst">, TB; // [mem8] = !=
814 def SETBEr : I<0x96, MRM0r, (ops R8 :$dst), "setbe $dst">, TB; // R8 = <= unsign
815 def SETBEm : I<0x96, MRM0m, (ops i8mem:$dst), "setbe $dst">, TB; // [mem8] = <= unsign
816 def SETAr : I<0x97, MRM0r, (ops R8 :$dst), "seta $dst">, TB; // R8 = > signed
817 def SETAm : I<0x97, MRM0m, (ops i8mem:$dst), "seta $dst">, TB; // [mem8] = > signed
818 def SETSr : I<0x98, MRM0r, (ops R8 :$dst), "sets $dst">, TB; // R8 = <sign bit>
819 def SETSm : I<0x98, MRM0m, (ops i8mem:$dst), "sets $dst">, TB; // [mem8] = <sign bit>
820 def SETNSr : I<0x99, MRM0r, (ops R8 :$dst), "setns $dst">, TB; // R8 = !<sign bit>
821 def SETNSm : I<0x99, MRM0m, (ops i8mem:$dst), "setns $dst">, TB; // [mem8] = !<sign bit>
822 def SETPr : I<0x9A, MRM0r, (ops R8 :$dst), "setp $dst">, TB; // R8 = parity
823 def SETPm : I<0x9A, MRM0m, (ops i8mem:$dst), "setp $dst">, TB; // [mem8] = parity
824 def SETLr : I<0x9C, MRM0r, (ops R8 :$dst), "setl $dst">, TB; // R8 = < signed
825 def SETLm : I<0x9C, MRM0m, (ops i8mem:$dst), "setl $dst">, TB; // [mem8] = < signed
826 def SETGEr : I<0x9D, MRM0r, (ops R8 :$dst), "setge $dst">, TB; // R8 = >= signed
827 def SETGEm : I<0x9D, MRM0m, (ops i8mem:$dst), "setge $dst">, TB; // [mem8] = >= signed
828 def SETLEr : I<0x9E, MRM0r, (ops R8 :$dst), "setle $dst">, TB; // R8 = <= signed
829 def SETLEm : I<0x9E, MRM0m, (ops i8mem:$dst), "setle $dst">, TB; // [mem8] = <= signed
830 def SETGr : I<0x9F, MRM0r, (ops R8 :$dst), "setg $dst">, TB; // R8 = < signed
831 def SETGm : I<0x9F, MRM0m, (ops i8mem:$dst), "setg $dst">, TB; // [mem8] = < signed
833 // Integer comparisons
834 def CMP8rr : I<0x38, MRMDestReg, (ops R8 :$src1, R8 :$src2), "cmp $src1, $src2">;
835 def CMP16rr : I<0x39, MRMDestReg, (ops R16:$src1, R16:$src2), "cmp $src1, $src2">, OpSize;
836 def CMP32rr : I<0x39, MRMDestReg, (ops R32:$src1, R32:$src2), "cmp $src1, $src2">;
837 def CMP8mr : I<0x38, MRMDestMem, (ops i8mem :$src1, R8 :$src2), "cmp $src1, $src2">;
838 def CMP16mr : I<0x39, MRMDestMem, (ops i16mem:$src1, R16:$src2), "cmp $src1, $src2">, OpSize;
839 def CMP32mr : I<0x39, MRMDestMem, (ops i32mem:$src1, R32:$src2), "cmp $src1, $src2">;
840 def CMP8rm : I<0x3A, MRMSrcMem , (ops R8 :$src1, i8mem :$src2), "cmp $src1, $src2">;
841 def CMP16rm : I<0x3B, MRMSrcMem , (ops R16:$src1, i16mem:$src2), "cmp $src1, $src2">, OpSize;
842 def CMP32rm : I<0x3B, MRMSrcMem , (ops R32:$src1, i32mem:$src2), "cmp $src1, $src2">;
843 def CMP8ri : Ii8 <0x80, MRM7r, (ops R16:$dst, i8imm:$src), "cmp $dst, $src">;
844 def CMP16ri : Ii16<0x81, MRM7r, (ops R16:$dst, i16imm:$src), "cmp $dst, $src">, OpSize;
845 def CMP32ri : Ii32<0x81, MRM7r, (ops R32:$dst, i32imm:$src), "cmp $dst, $src">;
846 def CMP8mi : Ii8 <0x80, MRM7m, (ops i8mem :$dst, i8imm :$src), "cmp $dst, $src">;
847 def CMP16mi : Ii16<0x81, MRM7m, (ops i16mem:$dst, i16imm:$src), "cmp $dst, $src">, OpSize;
848 def CMP32mi : Ii32<0x81, MRM7m, (ops i32mem:$dst, i32imm:$src), "cmp $dst, $src">;
850 // Sign/Zero extenders
851 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops R16:$dst, R8 :$src), "movsx $dst, $src">, TB, OpSize;
852 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops R32:$dst, R8 :$src), "movsx $dst, $src">, TB;
853 def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops R32:$dst, R16:$src), "movsx $dst, $src">, TB;
854 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (ops R16:$dst, i8mem :$src), "movsx $dst, $src">, TB, OpSize;
855 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (ops R32:$dst, i8mem :$src), "movsx $dst, $src">, TB;
856 def MOVSX32rm16: I<0xBF, MRMSrcMem, (ops R32:$dst, i16mem:$src), "movsx $dst, $src">, TB;
858 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops R16:$dst, R8 :$src), "movzx $dst, $src">, TB, OpSize;
859 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops R32:$dst, R8 :$src), "movzx $dst, $src">, TB;
860 def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops R32:$dst, R16:$src), "movzx $dst, $src">, TB;
861 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (ops R16:$dst, i8mem :$src), "movzx $dst, $src">, TB, OpSize;
862 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (ops R32:$dst, i8mem :$src), "movzx $dst, $src">, TB;
863 def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops R32:$dst, i16mem:$src), "movzx $dst, $src">, TB;
866 //===----------------------------------------------------------------------===//
867 // Floating point support
868 //===----------------------------------------------------------------------===//
870 // FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP'
872 // Floating point instruction template
873 class FPI<bits<8> o, Format F, FPFormat fp, dag ops, string asm>
874 : X86Inst<o, F, NoImm, ops, asm> {
875 let FPForm = fp; let FPFormBits = FPForm.Value;
878 // Pseudo instructions for floating point. We use these pseudo instructions
879 // because they can be expanded by the fp spackifier into one of many different
880 // forms of instructions for doing these operations. Until the stackifier runs,
881 // we prefer to be abstract.
882 def FpMOV : FPI<0, Pseudo, SpecialFP, (ops RFP, RFP), "">; // f1 = fmov f2
883 def FpADD : FPI<0, Pseudo, TwoArgFP , (ops RFP, RFP, RFP), "">; // f1 = fadd f2, f3
884 def FpSUB : FPI<0, Pseudo, TwoArgFP , (ops RFP, RFP, RFP), "">; // f1 = fsub f2, f3
885 def FpMUL : FPI<0, Pseudo, TwoArgFP , (ops RFP, RFP, RFP), "">; // f1 = fmul f2, f3
886 def FpDIV : FPI<0, Pseudo, TwoArgFP , (ops RFP, RFP, RFP), "">; // f1 = fdiv f2, f3
888 let Uses = [ST0] in {
889 def FpGETRESULT : FPI<0, Pseudo, SpecialFP, (ops RFP), "">; // FPR = ST(0)
892 let Defs = [ST0] in {
893 def FpSETRESULT : FPI<0, Pseudo, SpecialFP, (ops RFP), "">; // ST(0) = FPR
896 // FADD reg, mem: Before stackification, these are represented by: R1 = FADD* R2, [mem]
897 def FADD32m : FPI<0xD8, MRM0m, OneArgFPRW, (ops f32mem:$src), "fadd $src">; // ST(0) = ST(0) + [mem32real]
898 def FADD64m : FPI<0xDC, MRM0m, OneArgFPRW, (ops f64mem:$src), "fadd $src">; // ST(0) = ST(0) + [mem64real]
900 def FIADD16m : FPI<0xDE, MRM0m, OneArgFPRW, (ops i16mem:$src), // ST(0) = ST(0) + [mem16int]
902 def FIADD32m : FPI<0xDA, MRM0m, OneArgFPRW, (ops i32mem:$src), // ST(0) = ST(0) + [mem32int]
906 // FMUL reg, mem: Before stackification, these are represented by: R1 = FMUL* R2, [mem]
907 def FMUL32m : FPI<0xD8, MRM1m, OneArgFPRW, (ops f32mem:$src), "fmul $src">; // ST(0) = ST(0) * [mem32real]
908 def FMUL64m : FPI<0xDC, MRM1m, OneArgFPRW, (ops f64mem:$src), "fmul $src">; // ST(0) = ST(0) * [mem64real]
909 //def FIMUL16m : FPI16m<"fimul", 0xDE, MRM1m, OneArgFPRW>; // ST(0) = ST(0) * [mem16int]
910 //def FIMUL32m : FPI32m<"fimul", 0xDA, MRM1m, OneArgFPRW>; // ST(0) = ST(0) * [mem32int]
912 // FSUB reg, mem: Before stackification, these are represented by: R1 = FSUB* R2, [mem]
913 def FSUB32m : FPI<0xD8, MRM4m, OneArgFPRW, (ops f32mem:$src), "fsub $src">; // ST(0) = ST(0) - [mem32real]
914 def FSUB64m : FPI<0xDC, MRM4m, OneArgFPRW, (ops f64mem:$src), "fsub $src">; // ST(0) = ST(0) - [mem64real]
915 //def FISUB16m : FPI16m<"fisub", 0xDE, MRM4m, OneArgFPRW>; // ST(0) = ST(0) - [mem16int]
916 //def FISUB32m : FPI32m<"fisub", 0xDA, MRM4m, OneArgFPRW>; // ST(0) = ST(0) - [mem32int]
918 // FSUBR reg, mem: Before stackification, these are represented by: R1 = FSUBR* R2, [mem]
919 // Note that the order of operands does not reflect the operation being performed.
920 def FSUBR32m : FPI<0xD8, MRM5m, OneArgFPRW, (ops f32mem:$src), "fsubr $src">; // ST(0) = [mem32real] - ST(0)
921 def FSUBR64m : FPI<0xDC, MRM5m, OneArgFPRW, (ops f64mem:$src), "fsubr $src">; // ST(0) = [mem64real] - ST(0)
922 //def FISUBR16m : FPI16m<"fisubr", 0xDE, MRM5m, OneArgFPRW>; // ST(0) = [mem16int] - ST(0)
923 //def FISUBR32m : FPI32m<"fisubr", 0xDA, MRM5m, OneArgFPRW>; // ST(0) = [mem32int] - ST(0)
925 // FDIV reg, mem: Before stackification, these are represented by: R1 = FDIV* R2, [mem]
926 def FDIV32m : FPI<0xD8, MRM6m, OneArgFPRW, (ops f32mem:$src), "fdiv $src">; // ST(0) = ST(0) / [mem32real]
927 def FDIV64m : FPI<0xDC, MRM6m, OneArgFPRW, (ops f64mem:$src), "fdiv $src">; // ST(0) = ST(0) / [mem64real]
928 //def FIDIV16m : FPI16m<"fidiv", 0xDE, MRM6m, OneArgFPRW>; // ST(0) = ST(0) / [mem16int]
929 //def FIDIV32m : FPI32m<"fidiv", 0xDA, MRM6m, OneArgFPRW>; // ST(0) = ST(0) / [mem32int]
931 // FDIVR reg, mem: Before stackification, these are represented by: R1 = FDIVR* R2, [mem]
932 // Note that the order of operands does not reflect the operation being performed.
933 def FDIVR32m : FPI<0xD8, MRM7m, OneArgFPRW, (ops f32mem:$src), "fdivr $src">; // ST(0) = [mem32real] / ST(0)
934 def FDIVR64m : FPI<0xDC, MRM7m, OneArgFPRW, (ops f64mem:$src), "fdivr $src">; // ST(0) = [mem64real] / ST(0)
935 //def FIDIVR16m : FPI16m<"fidivr", 0xDE, MRM7m, OneArgFPRW>; // ST(0) = [mem16int] / ST(0)
936 //def FIDIVR32m : FPI32m<"fidivr", 0xDA, MRM7m, OneArgFPRW>; // ST(0) = [mem32int] / ST(0)
939 // Floating point cmovs...
940 let isTwoAddress = 1, Uses = [ST0], Defs = [ST0] in {
941 def FCMOVB : FPI<0xC0, AddRegFrm, CondMovFP,
942 (ops RST:$op), "fcmovb %ST(0), $op">, DA;
943 def FCMOVBE : FPI<0xD0, AddRegFrm, CondMovFP,
944 (ops RST:$op), "fcmovbe %ST(0), $op">, DA;
945 def FCMOVE : FPI<0xC8, AddRegFrm, CondMovFP,
946 (ops RST:$op), "fcmove %ST(0), $op">, DA;
947 def FCMOVAE : FPI<0xC0, AddRegFrm, CondMovFP,
948 (ops RST:$op), "fcmovae %ST(0), $op">, DB;
949 def FCMOVA : FPI<0xD0, AddRegFrm, CondMovFP,
950 (ops RST:$op), "fcmova %ST(0), $op">, DB;
951 def FCMOVNE : FPI<0xC8, AddRegFrm, CondMovFP,
952 (ops RST:$op), "fcmovne %ST(0), $op">, DB;
955 // Floating point loads & stores...
956 def FLDrr : FPI<0xC0, AddRegFrm, NotFP, (ops RST:$src), "fld $src">, D9;
957 def FLD32m : FPI<0xD9, MRM0m, ZeroArgFP, (ops f32mem:$src), "fld $src">;
958 def FLD64m : FPI<0xDD, MRM0m, ZeroArgFP, (ops f64mem:$src), "fld $src">;
959 def FLD80m : FPI<0xDB, MRM5m, ZeroArgFP, (ops f80mem:$src), "fld $src">;
960 def FILD16m : FPI<0xDF, MRM0m, ZeroArgFP, (ops i16mem:$src), "fild $src">;
961 def FILD32m : FPI<0xDB, MRM0m, ZeroArgFP, (ops i32mem:$src), "fild $src">;
962 def FILD64m : FPI<0xDF, MRM5m, ZeroArgFP, (ops i64mem:$src), "fild $src">;
964 def FSTrr : FPI<0xD0, AddRegFrm, NotFP, (ops RST:$op), "fst $op">, DD;
965 def FSTPrr : FPI<0xD8, AddRegFrm, NotFP, (ops RST:$op), "fstp $op">, DD;
966 def FST32m : FPI<0xD9, MRM2m, OneArgFP, (ops f32mem:$op), "fst $op">;
967 def FST64m : FPI<0xDD, MRM2m, OneArgFP, (ops f64mem:$op), "fst $op">;
968 def FSTP32m : FPI<0xD9, MRM3m, OneArgFP, (ops f32mem:$op), "fstp $op">;
969 def FSTP64m : FPI<0xDD, MRM3m, OneArgFP, (ops f64mem:$op), "fstp $op">;
970 def FSTP80m : FPI<0xDB, MRM7m, OneArgFP, (ops f80mem:$op), "fstp $op">;
972 def FIST16m : FPI<0xDF, MRM2m , OneArgFP, (ops i16mem:$op), "fist $op">;
973 def FIST32m : FPI<0xDB, MRM2m , OneArgFP, (ops i32mem:$op), "fist $op">;
974 def FISTP16m : FPI<0xDF, MRM3m , NotFP , (ops i16mem:$op), "fistp $op">;
975 def FISTP32m : FPI<0xDB, MRM3m , NotFP , (ops i32mem:$op), "fistp $op">;
976 def FISTP64m : FPI<0xDF, MRM7m , OneArgFP, (ops i64mem:$op), "fistpll $op">;
978 def FXCH : FPI<0xC8, AddRegFrm, NotFP, (ops RST:$op), "fxch $op">, D9; // fxch ST(i), ST(0)
980 // Floating point constant loads...
981 def FLD0 : FPI<0xEE, RawFrm, ZeroArgFP, (ops), "fldz">, D9;
982 def FLD1 : FPI<0xE8, RawFrm, ZeroArgFP, (ops), "fld1">, D9;
985 // Unary operations...
986 def FCHS : FPI<0xE0, RawFrm, OneArgFPRW, (ops), "fchs">, D9; // f1 = fchs f2
987 def FTST : FPI<0xE4, RawFrm, OneArgFP, (ops), "ftst">, D9; // ftst ST(0)
989 // Binary arithmetic operations...
990 class FPST0rInst<bits<8> o, dag ops, string asm> : I<o, AddRegFrm, ops, asm>, D8 {
991 list<Register> Uses = [ST0];
992 list<Register> Defs = [ST0];
994 class FPrST0Inst<bits<8> o, dag ops, string asm> : I<o, AddRegFrm, ops, asm>, DC {
995 list<Register> Uses = [ST0];
997 class FPrST0PInst<bits<8> o, dag ops, string asm> : I<o, AddRegFrm, ops, asm>, DE {
998 list<Register> Uses = [ST0];
1001 def FADDST0r : FPST0rInst <0xC0, (ops RST:$op), "fadd $op">;
1002 def FADDrST0 : FPrST0Inst <0xC0, (ops RST:$op), "fadd $op, %ST(0)">;
1003 def FADDPrST0 : FPrST0PInst<0xC0, (ops RST:$op), "faddp $op">;
1005 def FSUBRST0r : FPST0rInst <0xE8, (ops RST:$op), "fsubr $op">;
1006 def FSUBrST0 : FPrST0Inst <0xE8, (ops RST:$op), "fsub $op, %ST(0)">;
1007 def FSUBPrST0 : FPrST0PInst<0xE8, (ops RST:$op), "fsubp $op">;
1009 def FSUBST0r : FPST0rInst <0xE0, (ops RST:$op), "fsub $op">;
1010 def FSUBRrST0 : FPrST0Inst <0xE0, (ops RST:$op), "fsubr $op, %ST(0)">;
1011 def FSUBRPrST0 : FPrST0PInst<0xE0, (ops RST:$op), "fsubrp $op">;
1013 def FMULST0r : FPST0rInst <0xC8, (ops RST:$op), "fmul $op">;
1014 def FMULrST0 : FPrST0Inst <0xC8, (ops RST:$op), "fmul $op, %ST(0)">;
1015 def FMULPrST0 : FPrST0PInst<0xC8, (ops RST:$op), "fmulp $op">;
1017 def FDIVRST0r : FPST0rInst <0xF8, (ops RST:$op), "fdivr $op">;
1018 def FDIVrST0 : FPrST0Inst <0xF8, (ops RST:$op), "fdiv $op, %ST(0)">;
1019 def FDIVPrST0 : FPrST0PInst<0xF8, (ops RST:$op), "fdivp $op">;
1021 def FDIVST0r : FPST0rInst <0xF0, (ops RST:$op), "fdiv $op">; // ST(0) = ST(0) / ST(i)
1022 def FDIVRrST0 : FPrST0Inst <0xF0, (ops RST:$op), "fdivr $op, %ST(0)">; // ST(i) = ST(0) / ST(i)
1023 def FDIVRPrST0 : FPrST0PInst<0xF0, (ops RST:$op), "fdivrp $op">; // ST(i) = ST(0) / ST(i), pop
1025 // Floating point compares
1026 def FUCOMr : FPI<0xE0, AddRegFrm, CompareFP, (ops RST:$reg),
1027 "fucom $reg">, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i)
1028 def FUCOMPr : I<0xE8, AddRegFrm, (ops RST:$reg),
1029 "fucomp $reg">, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i), pop
1030 def FUCOMPPr : I<0xE9, RawFrm, (ops),
1031 "fucompp">, DA, Imp<[ST0],[]>; // compare ST(0) with ST(1), pop, pop
1033 def FUCOMIr : FPI<0xE8, AddRegFrm, CompareFP, (ops RST:$reg),
1034 "fucomi %ST(0), $reg">, DB, Imp<[ST0],[]>; // CC = compare ST(0) with ST(i)
1035 def FUCOMIPr : I<0xE8, AddRegFrm, (ops RST:$reg),
1036 "fucomip %ST(0), $reg">, DF, Imp<[ST0],[]>; // CC = compare ST(0) with ST(i), pop
1039 // Floating point flag ops
1040 def FNSTSW8r : I<0xE0, RawFrm, (ops), "fnstsw">, DF, Imp<[],[AX]>; // AX = fp flags
1042 def FNSTCW16m : I<0xD9, MRM7m, (ops i16mem:$dst), "fnstcw $dst">; // [mem16] = X87 control world
1043 def FLDCW16m : I<0xD9, MRM5m, (ops i16mem:$dst), "fldcw $dst">; // X87 control world = [mem16]