1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
33 def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
37 def SDTX86BrCond : SDTypeProfile<0, 3,
38 [SDTCisVT<0, OtherVT>,
39 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
41 def SDTX86SetCC : SDTypeProfile<1, 2,
43 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
47 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
49 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
50 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
51 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
53 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
54 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
57 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
59 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
63 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
65 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
67 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
69 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
71 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
73 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
75 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
77 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
78 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
79 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
80 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
82 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
84 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
86 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
87 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
89 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
91 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
92 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
94 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
95 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
97 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
98 [SDNPHasChain, SDNPMayStore,
99 SDNPMayLoad, SDNPMemOperand]>;
100 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
101 [SDNPHasChain, SDNPMayStore,
102 SDNPMayLoad, SDNPMemOperand]>;
103 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
104 [SDNPHasChain, SDNPMayStore,
105 SDNPMayLoad, SDNPMemOperand]>;
106 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
107 [SDNPHasChain, SDNPMayStore,
108 SDNPMayLoad, SDNPMemOperand]>;
109 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
110 [SDNPHasChain, SDNPMayStore,
111 SDNPMayLoad, SDNPMemOperand]>;
112 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
113 [SDNPHasChain, SDNPMayStore,
114 SDNPMayLoad, SDNPMemOperand]>;
115 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
116 [SDNPHasChain, SDNPMayStore,
117 SDNPMayLoad, SDNPMemOperand]>;
118 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
119 [SDNPHasChain, SDNPOptInFlag]>;
121 def X86vastart_save_xmm_regs :
122 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
123 SDT_X86VASTART_SAVE_XMM_REGS,
126 def X86callseq_start :
127 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
128 [SDNPHasChain, SDNPOutFlag]>;
130 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
131 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
133 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
134 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
136 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
137 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
138 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
139 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
142 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
143 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
145 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
146 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
148 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
149 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
150 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
151 SDT_X86SegmentBaseAddress, []>;
153 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
156 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
157 [SDNPHasChain, SDNPOptInFlag]>;
159 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags>;
160 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
161 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags>;
162 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>;
163 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
164 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
166 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
168 //===----------------------------------------------------------------------===//
169 // X86 Operand Definitions.
172 def i32imm_pcrel : Operand<i32> {
173 let PrintMethod = "print_pcrel_imm";
176 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
177 // the index operand of an address, to conform to x86 encoding restrictions.
178 def ptr_rc_nosp : PointerLikeRegClass<1>;
180 // *mem - Operand definitions for the funky X86 addressing mode operands.
182 def X86MemAsmOperand : AsmOperandClass {
186 class X86MemOperand<string printMethod> : Operand<iPTR> {
187 let PrintMethod = printMethod;
188 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
189 let ParserMatchClass = X86MemAsmOperand;
192 def opaque32mem : X86MemOperand<"printopaquemem">;
193 def opaque48mem : X86MemOperand<"printopaquemem">;
194 def opaque80mem : X86MemOperand<"printopaquemem">;
196 def i8mem : X86MemOperand<"printi8mem">;
197 def i16mem : X86MemOperand<"printi16mem">;
198 def i32mem : X86MemOperand<"printi32mem">;
199 def i64mem : X86MemOperand<"printi64mem">;
200 def i128mem : X86MemOperand<"printi128mem">;
201 def i256mem : X86MemOperand<"printi256mem">;
202 def f32mem : X86MemOperand<"printf32mem">;
203 def f64mem : X86MemOperand<"printf64mem">;
204 def f80mem : X86MemOperand<"printf80mem">;
205 def f128mem : X86MemOperand<"printf128mem">;
206 def f256mem : X86MemOperand<"printf256mem">;
208 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
209 // plain GR64, so that it doesn't potentially require a REX prefix.
210 def i8mem_NOREX : Operand<i64> {
211 let PrintMethod = "printi8mem";
212 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
213 let ParserMatchClass = X86MemAsmOperand;
216 def lea32mem : Operand<i32> {
217 let PrintMethod = "printlea32mem";
218 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
219 let ParserMatchClass = X86MemAsmOperand;
222 def SSECC : Operand<i8> {
223 let PrintMethod = "printSSECC";
226 def piclabel: Operand<i32> {
227 let PrintMethod = "printPICLabel";
230 def ImmSExt8AsmOperand : AsmOperandClass {
231 let Name = "ImmSExt8";
232 let SuperClass = ImmAsmOperand;
235 // A couple of more descriptive operand definitions.
236 // 16-bits but only 8 bits are significant.
237 def i16i8imm : Operand<i16> {
238 let ParserMatchClass = ImmSExt8AsmOperand;
240 // 32-bits but only 8 bits are significant.
241 def i32i8imm : Operand<i32> {
242 let ParserMatchClass = ImmSExt8AsmOperand;
245 // Branch targets have OtherVT type and print as pc-relative values.
246 def brtarget : Operand<OtherVT> {
247 let PrintMethod = "print_pcrel_imm";
250 def brtarget8 : Operand<OtherVT> {
251 let PrintMethod = "print_pcrel_imm";
254 //===----------------------------------------------------------------------===//
255 // X86 Complex Pattern Definitions.
258 // Define X86 specific addressing mode.
259 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
260 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
261 [add, sub, mul, X86mul_imm, shl, or, frameindex],
263 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
264 [tglobaltlsaddr], []>;
266 //===----------------------------------------------------------------------===//
267 // X86 Instruction Predicate Definitions.
268 def HasMMX : Predicate<"Subtarget->hasMMX()">;
269 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
270 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
271 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
272 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
273 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
274 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
275 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
276 def HasAVX : Predicate<"Subtarget->hasAVX()">;
277 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
278 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
279 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
280 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
281 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
282 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
283 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
284 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
285 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
286 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
287 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
288 "TM.getCodeModel() != CodeModel::Kernel">;
289 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
290 "TM.getCodeModel() == CodeModel::Kernel">;
291 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
292 def OptForSpeed : Predicate<"!OptForSize">;
293 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
294 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
296 //===----------------------------------------------------------------------===//
297 // X86 Instruction Format Definitions.
300 include "X86InstrFormats.td"
302 //===----------------------------------------------------------------------===//
303 // Pattern fragments...
306 // X86 specific condition code. These correspond to CondCode in
307 // X86InstrInfo.h. They must be kept in synch.
308 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
309 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
310 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
311 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
312 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
313 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
314 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
315 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
316 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
317 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
318 def X86_COND_NO : PatLeaf<(i8 10)>;
319 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
320 def X86_COND_NS : PatLeaf<(i8 12)>;
321 def X86_COND_O : PatLeaf<(i8 13)>;
322 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
323 def X86_COND_S : PatLeaf<(i8 15)>;
325 def i16immSExt8 : PatLeaf<(i16 imm), [{
326 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
327 // sign extended field.
328 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
331 def i32immSExt8 : PatLeaf<(i32 imm), [{
332 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
333 // sign extended field.
334 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
337 // Helper fragments for loads.
338 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
339 // known to be 32-bit aligned or better. Ditto for i8 to i16.
340 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
341 LoadSDNode *LD = cast<LoadSDNode>(N);
342 if (const Value *Src = LD->getSrcValue())
343 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
344 if (PT->getAddressSpace() > 255)
346 ISD::LoadExtType ExtType = LD->getExtensionType();
347 if (ExtType == ISD::NON_EXTLOAD)
349 if (ExtType == ISD::EXTLOAD)
350 return LD->getAlignment() >= 2 && !LD->isVolatile();
354 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
355 LoadSDNode *LD = cast<LoadSDNode>(N);
356 if (const Value *Src = LD->getSrcValue())
357 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
358 if (PT->getAddressSpace() > 255)
360 ISD::LoadExtType ExtType = LD->getExtensionType();
361 if (ExtType == ISD::EXTLOAD)
362 return LD->getAlignment() >= 2 && !LD->isVolatile();
366 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
367 LoadSDNode *LD = cast<LoadSDNode>(N);
368 if (const Value *Src = LD->getSrcValue())
369 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
370 if (PT->getAddressSpace() > 255)
372 ISD::LoadExtType ExtType = LD->getExtensionType();
373 if (ExtType == ISD::NON_EXTLOAD)
375 if (ExtType == ISD::EXTLOAD)
376 return LD->getAlignment() >= 4 && !LD->isVolatile();
380 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
381 LoadSDNode *LD = cast<LoadSDNode>(N);
382 if (const Value *Src = LD->getSrcValue())
383 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
384 if (PT->getAddressSpace() > 255)
386 if (LD->isVolatile())
388 ISD::LoadExtType ExtType = LD->getExtensionType();
389 if (ExtType == ISD::NON_EXTLOAD)
391 if (ExtType == ISD::EXTLOAD)
392 return LD->getAlignment() >= 4;
396 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
397 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
398 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
399 return PT->getAddressSpace() == 256;
403 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
404 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
405 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
406 return PT->getAddressSpace() == 257;
410 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{
411 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
412 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
413 if (PT->getAddressSpace() > 255)
417 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{
418 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
419 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
420 if (PT->getAddressSpace() > 255)
425 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{
426 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
427 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
428 if (PT->getAddressSpace() > 255)
432 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{
433 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
434 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
435 if (PT->getAddressSpace() > 255)
439 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{
440 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
441 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
442 if (PT->getAddressSpace() > 255)
447 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
448 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
449 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
451 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
452 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
453 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
454 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
455 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
456 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
458 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
459 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
460 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
461 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
462 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
463 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
466 // An 'and' node with a single use.
467 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
468 return N->hasOneUse();
470 // An 'srl' node with a single use.
471 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
472 return N->hasOneUse();
474 // An 'trunc' node with a single use.
475 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
476 return N->hasOneUse();
479 // 'shld' and 'shrd' instruction patterns. Note that even though these have
480 // the srl and shl in their patterns, the C++ code must still check for them,
481 // because predicates are tested before children nodes are explored.
483 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
484 (or (srl node:$src1, node:$amt1),
485 (shl node:$src2, node:$amt2)), [{
486 assert(N->getOpcode() == ISD::OR);
487 return N->getOperand(0).getOpcode() == ISD::SRL &&
488 N->getOperand(1).getOpcode() == ISD::SHL &&
489 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
490 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
491 N->getOperand(0).getConstantOperandVal(1) ==
492 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
495 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
496 (or (shl node:$src1, node:$amt1),
497 (srl node:$src2, node:$amt2)), [{
498 assert(N->getOpcode() == ISD::OR);
499 return N->getOperand(0).getOpcode() == ISD::SHL &&
500 N->getOperand(1).getOpcode() == ISD::SRL &&
501 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
502 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
503 N->getOperand(0).getConstantOperandVal(1) ==
504 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
507 //===----------------------------------------------------------------------===//
508 // Instruction list...
511 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
512 // a stack adjustment and the codegen must know that they may modify the stack
513 // pointer before prolog-epilog rewriting occurs.
514 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
515 // sub / add which can clobber EFLAGS.
516 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
517 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
519 [(X86callseq_start timm:$amt)]>,
520 Requires<[In32BitMode]>;
521 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
523 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
524 Requires<[In32BitMode]>;
527 // x86-64 va_start lowering magic.
528 let usesCustomDAGSchedInserter = 1 in
529 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
532 i64imm:$regsavefi, i64imm:$offset,
534 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
535 [(X86vastart_save_xmm_regs GR8:$al,
540 let neverHasSideEffects = 1 in {
541 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
542 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
543 "nopl\t$zero", []>, TB;
547 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int 3", []>;
548 def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
551 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
552 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
556 //===----------------------------------------------------------------------===//
557 // Control Flow Instructions...
560 // Return instructions.
561 let isTerminator = 1, isReturn = 1, isBarrier = 1,
562 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
563 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
566 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
568 [(X86retflag imm:$amt)]>;
571 // All branches are RawFrm, Void, Branch, and Terminators
572 let isBranch = 1, isTerminator = 1 in
573 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
574 I<opcode, RawFrm, (outs), ins, asm, pattern>;
576 let isBranch = 1, isBarrier = 1 in {
577 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
578 def JMP8 : IBr<0xEB, (ins brtarget8:$dst), "jmp\t$dst", []>;
582 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
583 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
584 [(brind GR32:$dst)]>;
585 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
586 [(brind (loadi32 addr:$dst))]>;
587 def FARJMP16 : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
588 "ljmp{w}\t{*}$dst", []>, OpSize;
589 def FARJMP32 : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
590 "ljmp{l}\t{*}$dst", []>;
593 // Conditional branches
594 let Uses = [EFLAGS] in {
595 // Short conditional jumps
596 def JO8 : IBr<0x70, (ins brtarget8:$dst), "jo\t$dst", []>;
597 def JNO8 : IBr<0x71, (ins brtarget8:$dst), "jno\t$dst", []>;
598 def JB8 : IBr<0x72, (ins brtarget8:$dst), "jb\t$dst", []>;
599 def JAE8 : IBr<0x73, (ins brtarget8:$dst), "jae\t$dst", []>;
600 def JE8 : IBr<0x74, (ins brtarget8:$dst), "je\t$dst", []>;
601 def JNE8 : IBr<0x75, (ins brtarget8:$dst), "jne\t$dst", []>;
602 def JBE8 : IBr<0x76, (ins brtarget8:$dst), "jbe\t$dst", []>;
603 def JA8 : IBr<0x77, (ins brtarget8:$dst), "ja\t$dst", []>;
604 def JS8 : IBr<0x78, (ins brtarget8:$dst), "js\t$dst", []>;
605 def JNS8 : IBr<0x79, (ins brtarget8:$dst), "jns\t$dst", []>;
606 def JP8 : IBr<0x7A, (ins brtarget8:$dst), "jp\t$dst", []>;
607 def JNP8 : IBr<0x7B, (ins brtarget8:$dst), "jnp\t$dst", []>;
608 def JL8 : IBr<0x7C, (ins brtarget8:$dst), "jl\t$dst", []>;
609 def JGE8 : IBr<0x7D, (ins brtarget8:$dst), "jge\t$dst", []>;
610 def JLE8 : IBr<0x7E, (ins brtarget8:$dst), "jle\t$dst", []>;
611 def JG8 : IBr<0x7F, (ins brtarget8:$dst), "jg\t$dst", []>;
613 def JCXZ8 : IBr<0xE3, (ins brtarget8:$dst), "jcxz\t$dst", []>;
615 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
616 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
617 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
618 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
619 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
620 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
621 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
622 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
623 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
624 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
625 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
626 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
628 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
629 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
630 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
631 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
632 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
633 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
634 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
635 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
637 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
638 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
639 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
640 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
641 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
642 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
643 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
644 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
645 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
646 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
647 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
648 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
651 //===----------------------------------------------------------------------===//
652 // Call Instructions...
655 // All calls clobber the non-callee saved registers. ESP is marked as
656 // a use to prevent stack-pointer assignments that appear immediately
657 // before calls from potentially appearing dead. Uses for argument
658 // registers are added manually.
659 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
660 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
661 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
662 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
664 def CALLpcrel32 : Ii32<0xE8, RawFrm,
665 (outs), (ins i32imm_pcrel:$dst,variable_ops),
667 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
668 "call\t{*}$dst", [(X86call GR32:$dst)]>;
669 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
670 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
672 def FARCALL16 : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
673 "lcall{w}\t{*}$dst", []>, OpSize;
674 def FARCALL32 : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
675 "lcall{l}\t{*}$dst", []>;
680 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
681 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops),
682 "#TC_RETURN $dst $offset",
685 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
686 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops),
687 "#TC_RETURN $dst $offset",
690 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
692 def TAILJMPd : IBr<0xE9, (ins i32imm_pcrel:$dst), "jmp\t$dst # TAILCALL",
694 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
695 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
697 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
698 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
699 "jmp\t{*}$dst # TAILCALL", []>;
701 //===----------------------------------------------------------------------===//
702 // Miscellaneous Instructions...
704 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
705 def LEAVE : I<0xC9, RawFrm,
706 (outs), (ins), "leave", []>;
708 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
710 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
713 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
716 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
717 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
718 "push{l}\t$imm", []>;
719 def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
720 "push{l}\t$imm", []>;
721 def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
722 "push{l}\t$imm", []>;
725 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
726 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
727 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
728 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
730 let isTwoAddress = 1 in // GR32 = bswap GR32
731 def BSWAP32r : I<0xC8, AddRegFrm,
732 (outs GR32:$dst), (ins GR32:$src),
734 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
737 // Bit scan instructions.
738 let Defs = [EFLAGS] in {
739 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
740 "bsf{w}\t{$src, $dst|$dst, $src}",
741 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
742 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
743 "bsf{w}\t{$src, $dst|$dst, $src}",
744 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
745 (implicit EFLAGS)]>, TB;
746 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
747 "bsf{l}\t{$src, $dst|$dst, $src}",
748 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
749 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
750 "bsf{l}\t{$src, $dst|$dst, $src}",
751 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
752 (implicit EFLAGS)]>, TB;
754 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
755 "bsr{w}\t{$src, $dst|$dst, $src}",
756 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
757 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
758 "bsr{w}\t{$src, $dst|$dst, $src}",
759 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
760 (implicit EFLAGS)]>, TB;
761 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
762 "bsr{l}\t{$src, $dst|$dst, $src}",
763 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
764 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
765 "bsr{l}\t{$src, $dst|$dst, $src}",
766 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
767 (implicit EFLAGS)]>, TB;
770 let neverHasSideEffects = 1 in
771 def LEA16r : I<0x8D, MRMSrcMem,
772 (outs GR16:$dst), (ins i32mem:$src),
773 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
774 let isReMaterializable = 1 in
775 def LEA32r : I<0x8D, MRMSrcMem,
776 (outs GR32:$dst), (ins lea32mem:$src),
777 "lea{l}\t{$src|$dst}, {$dst|$src}",
778 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
780 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
781 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
782 [(X86rep_movs i8)]>, REP;
783 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
784 [(X86rep_movs i16)]>, REP, OpSize;
785 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
786 [(X86rep_movs i32)]>, REP;
789 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
790 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
791 [(X86rep_stos i8)]>, REP;
792 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
793 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
794 [(X86rep_stos i16)]>, REP, OpSize;
795 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
796 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
797 [(X86rep_stos i32)]>, REP;
799 let Defs = [RAX, RDX] in
800 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
803 let isBarrier = 1, hasCtrlDep = 1 in {
804 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
807 def SYSCALL : I<0x05, RawFrm,
808 (outs), (ins), "syscall", []>, TB;
809 def SYSRET : I<0x07, RawFrm,
810 (outs), (ins), "sysret", []>, TB;
811 def SYSENTER : I<0x34, RawFrm,
812 (outs), (ins), "sysenter", []>, TB;
813 def SYSEXIT : I<0x35, RawFrm,
814 (outs), (ins), "sysexit", []>, TB;
818 //===----------------------------------------------------------------------===//
819 // Input/Output Instructions...
821 let Defs = [AL], Uses = [DX] in
822 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
823 "in{b}\t{%dx, %al|%AL, %DX}", []>;
824 let Defs = [AX], Uses = [DX] in
825 def IN16rr : I<0xED, RawFrm, (outs), (ins),
826 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
827 let Defs = [EAX], Uses = [DX] in
828 def IN32rr : I<0xED, RawFrm, (outs), (ins),
829 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
832 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
833 "in{b}\t{$port, %al|%AL, $port}", []>;
835 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
836 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
838 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
839 "in{l}\t{$port, %eax|%EAX, $port}", []>;
841 let Uses = [DX, AL] in
842 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
843 "out{b}\t{%al, %dx|%DX, %AL}", []>;
844 let Uses = [DX, AX] in
845 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
846 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
847 let Uses = [DX, EAX] in
848 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
849 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
852 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
853 "out{b}\t{%al, $port|$port, %AL}", []>;
855 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
856 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
858 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
859 "out{l}\t{%eax, $port|$port, %EAX}", []>;
861 //===----------------------------------------------------------------------===//
862 // Move Instructions...
864 let neverHasSideEffects = 1 in {
865 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
866 "mov{b}\t{$src, $dst|$dst, $src}", []>;
867 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
868 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
869 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
870 "mov{l}\t{$src, $dst|$dst, $src}", []>;
872 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
873 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
874 "mov{b}\t{$src, $dst|$dst, $src}",
875 [(set GR8:$dst, imm:$src)]>;
876 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
877 "mov{w}\t{$src, $dst|$dst, $src}",
878 [(set GR16:$dst, imm:$src)]>, OpSize;
879 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
880 "mov{l}\t{$src, $dst|$dst, $src}",
881 [(set GR32:$dst, imm:$src)]>;
883 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
884 "mov{b}\t{$src, $dst|$dst, $src}",
885 [(store (i8 imm:$src), addr:$dst)]>;
886 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
887 "mov{w}\t{$src, $dst|$dst, $src}",
888 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
889 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
890 "mov{l}\t{$src, $dst|$dst, $src}",
891 [(store (i32 imm:$src), addr:$dst)]>;
893 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
894 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
895 "mov{b}\t{$src, $dst|$dst, $src}",
896 [(set GR8:$dst, (loadi8 addr:$src))]>;
897 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
898 "mov{w}\t{$src, $dst|$dst, $src}",
899 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
900 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
901 "mov{l}\t{$src, $dst|$dst, $src}",
902 [(set GR32:$dst, (loadi32 addr:$src))]>;
905 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
906 "mov{b}\t{$src, $dst|$dst, $src}",
907 [(store GR8:$src, addr:$dst)]>;
908 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
909 "mov{w}\t{$src, $dst|$dst, $src}",
910 [(store GR16:$src, addr:$dst)]>, OpSize;
911 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
912 "mov{l}\t{$src, $dst|$dst, $src}",
913 [(store GR32:$src, addr:$dst)]>;
915 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
916 // that they can be used for copying and storing h registers, which can't be
917 // encoded when a REX prefix is present.
918 let neverHasSideEffects = 1 in
919 def MOV8rr_NOREX : I<0x88, MRMDestReg,
920 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
921 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
923 def MOV8mr_NOREX : I<0x88, MRMDestMem,
924 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
925 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
927 canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
928 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
929 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
930 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
932 //===----------------------------------------------------------------------===//
933 // Fixed-Register Multiplication and Division Instructions...
936 // Extra precision multiplication
937 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
938 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
939 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
940 // This probably ought to be moved to a def : Pat<> if the
941 // syntax can be accepted.
942 [(set AL, (mul AL, GR8:$src)),
943 (implicit EFLAGS)]>; // AL,AH = AL*GR8
945 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
946 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
948 []>, OpSize; // AX,DX = AX*GR16
950 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
951 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
953 []>; // EAX,EDX = EAX*GR32
955 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
956 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
958 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
959 // This probably ought to be moved to a def : Pat<> if the
960 // syntax can be accepted.
961 [(set AL, (mul AL, (loadi8 addr:$src))),
962 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
964 let mayLoad = 1, neverHasSideEffects = 1 in {
965 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
966 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
968 []>, OpSize; // AX,DX = AX*[mem16]
970 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
971 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
973 []>; // EAX,EDX = EAX*[mem32]
976 let neverHasSideEffects = 1 in {
977 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
978 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
980 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
981 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
982 OpSize; // AX,DX = AX*GR16
983 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
984 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
985 // EAX,EDX = EAX*GR32
987 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
988 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
989 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
990 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
991 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
992 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
993 let Defs = [EAX,EDX], Uses = [EAX] in
994 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
995 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
997 } // neverHasSideEffects
999 // unsigned division/remainder
1000 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1001 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1002 "div{b}\t$src", []>;
1003 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1004 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1005 "div{w}\t$src", []>, OpSize;
1006 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1007 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1008 "div{l}\t$src", []>;
1009 let mayLoad = 1 in {
1010 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1011 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1012 "div{b}\t$src", []>;
1013 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1014 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1015 "div{w}\t$src", []>, OpSize;
1016 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1017 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
1018 "div{l}\t$src", []>;
1021 // Signed division/remainder.
1022 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1023 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1024 "idiv{b}\t$src", []>;
1025 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1026 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1027 "idiv{w}\t$src", []>, OpSize;
1028 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1029 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1030 "idiv{l}\t$src", []>;
1031 let mayLoad = 1, mayLoad = 1 in {
1032 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1033 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1034 "idiv{b}\t$src", []>;
1035 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1036 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1037 "idiv{w}\t$src", []>, OpSize;
1038 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1039 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
1040 "idiv{l}\t$src", []>;
1043 //===----------------------------------------------------------------------===//
1044 // Two address Instructions.
1046 let isTwoAddress = 1 in {
1048 // Conditional moves
1049 let Uses = [EFLAGS] in {
1051 // X86 doesn't have 8-bit conditional moves. Use a customDAGSchedInserter to
1052 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1053 // however that requires promoting the operands, and can induce additional
1054 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1055 // clobber EFLAGS, because if one of the operands is zero, the expansion
1056 // could involve an xor.
1057 let usesCustomDAGSchedInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in
1058 def CMOV_GR8 : I<0, Pseudo,
1059 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1060 "#CMOV_GR8 PSEUDO!",
1061 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1062 imm:$cond, EFLAGS))]>;
1064 let isCommutable = 1 in {
1065 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1066 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1067 "cmovb\t{$src2, $dst|$dst, $src2}",
1068 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1069 X86_COND_B, EFLAGS))]>,
1071 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1072 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1073 "cmovb\t{$src2, $dst|$dst, $src2}",
1074 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1075 X86_COND_B, EFLAGS))]>,
1077 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1078 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1079 "cmovae\t{$src2, $dst|$dst, $src2}",
1080 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1081 X86_COND_AE, EFLAGS))]>,
1083 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1084 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1085 "cmovae\t{$src2, $dst|$dst, $src2}",
1086 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1087 X86_COND_AE, EFLAGS))]>,
1089 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1090 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1091 "cmove\t{$src2, $dst|$dst, $src2}",
1092 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1093 X86_COND_E, EFLAGS))]>,
1095 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1096 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1097 "cmove\t{$src2, $dst|$dst, $src2}",
1098 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1099 X86_COND_E, EFLAGS))]>,
1101 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1102 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1103 "cmovne\t{$src2, $dst|$dst, $src2}",
1104 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1105 X86_COND_NE, EFLAGS))]>,
1107 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1108 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1109 "cmovne\t{$src2, $dst|$dst, $src2}",
1110 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1111 X86_COND_NE, EFLAGS))]>,
1113 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1114 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1115 "cmovbe\t{$src2, $dst|$dst, $src2}",
1116 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1117 X86_COND_BE, EFLAGS))]>,
1119 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1120 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1121 "cmovbe\t{$src2, $dst|$dst, $src2}",
1122 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1123 X86_COND_BE, EFLAGS))]>,
1125 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1126 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1127 "cmova\t{$src2, $dst|$dst, $src2}",
1128 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1129 X86_COND_A, EFLAGS))]>,
1131 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1132 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1133 "cmova\t{$src2, $dst|$dst, $src2}",
1134 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1135 X86_COND_A, EFLAGS))]>,
1137 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1138 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1139 "cmovl\t{$src2, $dst|$dst, $src2}",
1140 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1141 X86_COND_L, EFLAGS))]>,
1143 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1144 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1145 "cmovl\t{$src2, $dst|$dst, $src2}",
1146 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1147 X86_COND_L, EFLAGS))]>,
1149 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1150 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1151 "cmovge\t{$src2, $dst|$dst, $src2}",
1152 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1153 X86_COND_GE, EFLAGS))]>,
1155 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1156 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1157 "cmovge\t{$src2, $dst|$dst, $src2}",
1158 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1159 X86_COND_GE, EFLAGS))]>,
1161 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1162 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1163 "cmovle\t{$src2, $dst|$dst, $src2}",
1164 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1165 X86_COND_LE, EFLAGS))]>,
1167 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1168 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1169 "cmovle\t{$src2, $dst|$dst, $src2}",
1170 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1171 X86_COND_LE, EFLAGS))]>,
1173 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1174 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1175 "cmovg\t{$src2, $dst|$dst, $src2}",
1176 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1177 X86_COND_G, EFLAGS))]>,
1179 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1180 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1181 "cmovg\t{$src2, $dst|$dst, $src2}",
1182 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1183 X86_COND_G, EFLAGS))]>,
1185 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1186 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1187 "cmovs\t{$src2, $dst|$dst, $src2}",
1188 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1189 X86_COND_S, EFLAGS))]>,
1191 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1192 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1193 "cmovs\t{$src2, $dst|$dst, $src2}",
1194 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1195 X86_COND_S, EFLAGS))]>,
1197 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1198 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1199 "cmovns\t{$src2, $dst|$dst, $src2}",
1200 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1201 X86_COND_NS, EFLAGS))]>,
1203 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1204 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1205 "cmovns\t{$src2, $dst|$dst, $src2}",
1206 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1207 X86_COND_NS, EFLAGS))]>,
1209 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1210 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1211 "cmovp\t{$src2, $dst|$dst, $src2}",
1212 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1213 X86_COND_P, EFLAGS))]>,
1215 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1216 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1217 "cmovp\t{$src2, $dst|$dst, $src2}",
1218 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1219 X86_COND_P, EFLAGS))]>,
1221 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1222 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1223 "cmovnp\t{$src2, $dst|$dst, $src2}",
1224 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1225 X86_COND_NP, EFLAGS))]>,
1227 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1228 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1229 "cmovnp\t{$src2, $dst|$dst, $src2}",
1230 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1231 X86_COND_NP, EFLAGS))]>,
1233 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1234 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1235 "cmovo\t{$src2, $dst|$dst, $src2}",
1236 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1237 X86_COND_O, EFLAGS))]>,
1239 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1240 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1241 "cmovo\t{$src2, $dst|$dst, $src2}",
1242 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1243 X86_COND_O, EFLAGS))]>,
1245 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1246 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1247 "cmovno\t{$src2, $dst|$dst, $src2}",
1248 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1249 X86_COND_NO, EFLAGS))]>,
1251 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1252 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1253 "cmovno\t{$src2, $dst|$dst, $src2}",
1254 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1255 X86_COND_NO, EFLAGS))]>,
1257 } // isCommutable = 1
1259 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1260 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1261 "cmovb\t{$src2, $dst|$dst, $src2}",
1262 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1263 X86_COND_B, EFLAGS))]>,
1265 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1266 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1267 "cmovb\t{$src2, $dst|$dst, $src2}",
1268 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1269 X86_COND_B, EFLAGS))]>,
1271 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1272 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1273 "cmovae\t{$src2, $dst|$dst, $src2}",
1274 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1275 X86_COND_AE, EFLAGS))]>,
1277 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1278 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1279 "cmovae\t{$src2, $dst|$dst, $src2}",
1280 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1281 X86_COND_AE, EFLAGS))]>,
1283 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1284 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1285 "cmove\t{$src2, $dst|$dst, $src2}",
1286 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1287 X86_COND_E, EFLAGS))]>,
1289 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1290 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1291 "cmove\t{$src2, $dst|$dst, $src2}",
1292 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1293 X86_COND_E, EFLAGS))]>,
1295 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1296 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1297 "cmovne\t{$src2, $dst|$dst, $src2}",
1298 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1299 X86_COND_NE, EFLAGS))]>,
1301 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1302 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1303 "cmovne\t{$src2, $dst|$dst, $src2}",
1304 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1305 X86_COND_NE, EFLAGS))]>,
1307 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1308 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1309 "cmovbe\t{$src2, $dst|$dst, $src2}",
1310 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1311 X86_COND_BE, EFLAGS))]>,
1313 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1314 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1315 "cmovbe\t{$src2, $dst|$dst, $src2}",
1316 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1317 X86_COND_BE, EFLAGS))]>,
1319 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1320 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1321 "cmova\t{$src2, $dst|$dst, $src2}",
1322 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1323 X86_COND_A, EFLAGS))]>,
1325 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1326 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1327 "cmova\t{$src2, $dst|$dst, $src2}",
1328 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1329 X86_COND_A, EFLAGS))]>,
1331 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1332 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1333 "cmovl\t{$src2, $dst|$dst, $src2}",
1334 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1335 X86_COND_L, EFLAGS))]>,
1337 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1338 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1339 "cmovl\t{$src2, $dst|$dst, $src2}",
1340 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1341 X86_COND_L, EFLAGS))]>,
1343 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1344 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1345 "cmovge\t{$src2, $dst|$dst, $src2}",
1346 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1347 X86_COND_GE, EFLAGS))]>,
1349 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1350 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1351 "cmovge\t{$src2, $dst|$dst, $src2}",
1352 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1353 X86_COND_GE, EFLAGS))]>,
1355 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1356 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1357 "cmovle\t{$src2, $dst|$dst, $src2}",
1358 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1359 X86_COND_LE, EFLAGS))]>,
1361 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1362 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1363 "cmovle\t{$src2, $dst|$dst, $src2}",
1364 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1365 X86_COND_LE, EFLAGS))]>,
1367 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1368 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1369 "cmovg\t{$src2, $dst|$dst, $src2}",
1370 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1371 X86_COND_G, EFLAGS))]>,
1373 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1374 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1375 "cmovg\t{$src2, $dst|$dst, $src2}",
1376 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1377 X86_COND_G, EFLAGS))]>,
1379 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1380 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1381 "cmovs\t{$src2, $dst|$dst, $src2}",
1382 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1383 X86_COND_S, EFLAGS))]>,
1385 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1386 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1387 "cmovs\t{$src2, $dst|$dst, $src2}",
1388 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1389 X86_COND_S, EFLAGS))]>,
1391 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1392 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1393 "cmovns\t{$src2, $dst|$dst, $src2}",
1394 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1395 X86_COND_NS, EFLAGS))]>,
1397 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1398 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1399 "cmovns\t{$src2, $dst|$dst, $src2}",
1400 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1401 X86_COND_NS, EFLAGS))]>,
1403 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1404 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1405 "cmovp\t{$src2, $dst|$dst, $src2}",
1406 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1407 X86_COND_P, EFLAGS))]>,
1409 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1410 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1411 "cmovp\t{$src2, $dst|$dst, $src2}",
1412 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1413 X86_COND_P, EFLAGS))]>,
1415 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1416 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1417 "cmovnp\t{$src2, $dst|$dst, $src2}",
1418 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1419 X86_COND_NP, EFLAGS))]>,
1421 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1422 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1423 "cmovnp\t{$src2, $dst|$dst, $src2}",
1424 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1425 X86_COND_NP, EFLAGS))]>,
1427 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1428 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1429 "cmovo\t{$src2, $dst|$dst, $src2}",
1430 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1431 X86_COND_O, EFLAGS))]>,
1433 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1434 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1435 "cmovo\t{$src2, $dst|$dst, $src2}",
1436 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1437 X86_COND_O, EFLAGS))]>,
1439 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1440 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1441 "cmovno\t{$src2, $dst|$dst, $src2}",
1442 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1443 X86_COND_NO, EFLAGS))]>,
1445 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1446 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1447 "cmovno\t{$src2, $dst|$dst, $src2}",
1448 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1449 X86_COND_NO, EFLAGS))]>,
1451 } // Uses = [EFLAGS]
1454 // unary instructions
1455 let CodeSize = 2 in {
1456 let Defs = [EFLAGS] in {
1457 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1458 [(set GR8:$dst, (ineg GR8:$src)),
1459 (implicit EFLAGS)]>;
1460 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1461 [(set GR16:$dst, (ineg GR16:$src)),
1462 (implicit EFLAGS)]>, OpSize;
1463 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1464 [(set GR32:$dst, (ineg GR32:$src)),
1465 (implicit EFLAGS)]>;
1466 let isTwoAddress = 0 in {
1467 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1468 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1469 (implicit EFLAGS)]>;
1470 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1471 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1472 (implicit EFLAGS)]>, OpSize;
1473 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1474 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1475 (implicit EFLAGS)]>;
1477 } // Defs = [EFLAGS]
1479 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1480 let AddedComplexity = 15 in {
1481 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1482 [(set GR8:$dst, (not GR8:$src))]>;
1483 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1484 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1485 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1486 [(set GR32:$dst, (not GR32:$src))]>;
1488 let isTwoAddress = 0 in {
1489 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1490 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1491 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1492 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1493 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1494 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1498 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1499 let Defs = [EFLAGS] in {
1501 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1502 [(set GR8:$dst, (add GR8:$src, 1)),
1503 (implicit EFLAGS)]>;
1504 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1505 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1506 [(set GR16:$dst, (add GR16:$src, 1)),
1507 (implicit EFLAGS)]>,
1508 OpSize, Requires<[In32BitMode]>;
1509 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1510 [(set GR32:$dst, (add GR32:$src, 1)),
1511 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1513 let isTwoAddress = 0, CodeSize = 2 in {
1514 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1515 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1516 (implicit EFLAGS)]>;
1517 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1518 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1519 (implicit EFLAGS)]>,
1520 OpSize, Requires<[In32BitMode]>;
1521 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1522 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1523 (implicit EFLAGS)]>,
1524 Requires<[In32BitMode]>;
1528 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1529 [(set GR8:$dst, (add GR8:$src, -1)),
1530 (implicit EFLAGS)]>;
1531 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1532 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1533 [(set GR16:$dst, (add GR16:$src, -1)),
1534 (implicit EFLAGS)]>,
1535 OpSize, Requires<[In32BitMode]>;
1536 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1537 [(set GR32:$dst, (add GR32:$src, -1)),
1538 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1541 let isTwoAddress = 0, CodeSize = 2 in {
1542 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1543 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1544 (implicit EFLAGS)]>;
1545 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1546 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1547 (implicit EFLAGS)]>,
1548 OpSize, Requires<[In32BitMode]>;
1549 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1550 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1551 (implicit EFLAGS)]>,
1552 Requires<[In32BitMode]>;
1554 } // Defs = [EFLAGS]
1556 // Logical operators...
1557 let Defs = [EFLAGS] in {
1558 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1559 def AND8rr : I<0x20, MRMDestReg,
1560 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1561 "and{b}\t{$src2, $dst|$dst, $src2}",
1562 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
1563 (implicit EFLAGS)]>;
1564 def AND16rr : I<0x21, MRMDestReg,
1565 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1566 "and{w}\t{$src2, $dst|$dst, $src2}",
1567 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
1568 (implicit EFLAGS)]>, OpSize;
1569 def AND32rr : I<0x21, MRMDestReg,
1570 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1571 "and{l}\t{$src2, $dst|$dst, $src2}",
1572 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
1573 (implicit EFLAGS)]>;
1576 def AND8rm : I<0x22, MRMSrcMem,
1577 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1578 "and{b}\t{$src2, $dst|$dst, $src2}",
1579 [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
1580 (implicit EFLAGS)]>;
1581 def AND16rm : I<0x23, MRMSrcMem,
1582 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1583 "and{w}\t{$src2, $dst|$dst, $src2}",
1584 [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
1585 (implicit EFLAGS)]>, OpSize;
1586 def AND32rm : I<0x23, MRMSrcMem,
1587 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1588 "and{l}\t{$src2, $dst|$dst, $src2}",
1589 [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
1590 (implicit EFLAGS)]>;
1592 def AND8ri : Ii8<0x80, MRM4r,
1593 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1594 "and{b}\t{$src2, $dst|$dst, $src2}",
1595 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
1596 (implicit EFLAGS)]>;
1597 def AND16ri : Ii16<0x81, MRM4r,
1598 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1599 "and{w}\t{$src2, $dst|$dst, $src2}",
1600 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
1601 (implicit EFLAGS)]>, OpSize;
1602 def AND32ri : Ii32<0x81, MRM4r,
1603 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1604 "and{l}\t{$src2, $dst|$dst, $src2}",
1605 [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
1606 (implicit EFLAGS)]>;
1607 def AND16ri8 : Ii8<0x83, MRM4r,
1608 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1609 "and{w}\t{$src2, $dst|$dst, $src2}",
1610 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
1611 (implicit EFLAGS)]>,
1613 def AND32ri8 : Ii8<0x83, MRM4r,
1614 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1615 "and{l}\t{$src2, $dst|$dst, $src2}",
1616 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
1617 (implicit EFLAGS)]>;
1619 let isTwoAddress = 0 in {
1620 def AND8mr : I<0x20, MRMDestMem,
1621 (outs), (ins i8mem :$dst, GR8 :$src),
1622 "and{b}\t{$src, $dst|$dst, $src}",
1623 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1624 (implicit EFLAGS)]>;
1625 def AND16mr : I<0x21, MRMDestMem,
1626 (outs), (ins i16mem:$dst, GR16:$src),
1627 "and{w}\t{$src, $dst|$dst, $src}",
1628 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1629 (implicit EFLAGS)]>,
1631 def AND32mr : I<0x21, MRMDestMem,
1632 (outs), (ins i32mem:$dst, GR32:$src),
1633 "and{l}\t{$src, $dst|$dst, $src}",
1634 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1635 (implicit EFLAGS)]>;
1636 def AND8mi : Ii8<0x80, MRM4m,
1637 (outs), (ins i8mem :$dst, i8imm :$src),
1638 "and{b}\t{$src, $dst|$dst, $src}",
1639 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1640 (implicit EFLAGS)]>;
1641 def AND16mi : Ii16<0x81, MRM4m,
1642 (outs), (ins i16mem:$dst, i16imm:$src),
1643 "and{w}\t{$src, $dst|$dst, $src}",
1644 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1645 (implicit EFLAGS)]>,
1647 def AND32mi : Ii32<0x81, MRM4m,
1648 (outs), (ins i32mem:$dst, i32imm:$src),
1649 "and{l}\t{$src, $dst|$dst, $src}",
1650 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1651 (implicit EFLAGS)]>;
1652 def AND16mi8 : Ii8<0x83, MRM4m,
1653 (outs), (ins i16mem:$dst, i16i8imm :$src),
1654 "and{w}\t{$src, $dst|$dst, $src}",
1655 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1656 (implicit EFLAGS)]>,
1658 def AND32mi8 : Ii8<0x83, MRM4m,
1659 (outs), (ins i32mem:$dst, i32i8imm :$src),
1660 "and{l}\t{$src, $dst|$dst, $src}",
1661 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1662 (implicit EFLAGS)]>;
1664 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1665 "and{b}\t{$src, %al|%al, $src}", []>;
1666 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1667 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1668 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1669 "and{l}\t{$src, %eax|%eax, $src}", []>;
1674 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1675 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1676 "or{b}\t{$src2, $dst|$dst, $src2}",
1677 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
1678 (implicit EFLAGS)]>;
1679 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1680 "or{w}\t{$src2, $dst|$dst, $src2}",
1681 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
1682 (implicit EFLAGS)]>, OpSize;
1683 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1684 "or{l}\t{$src2, $dst|$dst, $src2}",
1685 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
1686 (implicit EFLAGS)]>;
1688 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1689 "or{b}\t{$src2, $dst|$dst, $src2}",
1690 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
1691 (implicit EFLAGS)]>;
1692 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1693 "or{w}\t{$src2, $dst|$dst, $src2}",
1694 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
1695 (implicit EFLAGS)]>, OpSize;
1696 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1697 "or{l}\t{$src2, $dst|$dst, $src2}",
1698 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
1699 (implicit EFLAGS)]>;
1701 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1702 "or{b}\t{$src2, $dst|$dst, $src2}",
1703 [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
1704 (implicit EFLAGS)]>;
1705 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1706 "or{w}\t{$src2, $dst|$dst, $src2}",
1707 [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
1708 (implicit EFLAGS)]>, OpSize;
1709 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1710 "or{l}\t{$src2, $dst|$dst, $src2}",
1711 [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
1712 (implicit EFLAGS)]>;
1714 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1715 "or{w}\t{$src2, $dst|$dst, $src2}",
1716 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
1717 (implicit EFLAGS)]>, OpSize;
1718 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1719 "or{l}\t{$src2, $dst|$dst, $src2}",
1720 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
1721 (implicit EFLAGS)]>;
1722 let isTwoAddress = 0 in {
1723 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1724 "or{b}\t{$src, $dst|$dst, $src}",
1725 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1726 (implicit EFLAGS)]>;
1727 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1728 "or{w}\t{$src, $dst|$dst, $src}",
1729 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1730 (implicit EFLAGS)]>, OpSize;
1731 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1732 "or{l}\t{$src, $dst|$dst, $src}",
1733 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1734 (implicit EFLAGS)]>;
1735 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1736 "or{b}\t{$src, $dst|$dst, $src}",
1737 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1738 (implicit EFLAGS)]>;
1739 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1740 "or{w}\t{$src, $dst|$dst, $src}",
1741 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1742 (implicit EFLAGS)]>,
1744 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1745 "or{l}\t{$src, $dst|$dst, $src}",
1746 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1747 (implicit EFLAGS)]>;
1748 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1749 "or{w}\t{$src, $dst|$dst, $src}",
1750 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1751 (implicit EFLAGS)]>,
1753 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1754 "or{l}\t{$src, $dst|$dst, $src}",
1755 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1756 (implicit EFLAGS)]>;
1757 } // isTwoAddress = 0
1760 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1761 def XOR8rr : I<0x30, MRMDestReg,
1762 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1763 "xor{b}\t{$src2, $dst|$dst, $src2}",
1764 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
1765 (implicit EFLAGS)]>;
1766 def XOR16rr : I<0x31, MRMDestReg,
1767 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1768 "xor{w}\t{$src2, $dst|$dst, $src2}",
1769 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
1770 (implicit EFLAGS)]>, OpSize;
1771 def XOR32rr : I<0x31, MRMDestReg,
1772 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1773 "xor{l}\t{$src2, $dst|$dst, $src2}",
1774 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
1775 (implicit EFLAGS)]>;
1776 } // isCommutable = 1
1778 def XOR8rm : I<0x32, MRMSrcMem ,
1779 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1780 "xor{b}\t{$src2, $dst|$dst, $src2}",
1781 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
1782 (implicit EFLAGS)]>;
1783 def XOR16rm : I<0x33, MRMSrcMem ,
1784 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1785 "xor{w}\t{$src2, $dst|$dst, $src2}",
1786 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
1787 (implicit EFLAGS)]>,
1789 def XOR32rm : I<0x33, MRMSrcMem ,
1790 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1791 "xor{l}\t{$src2, $dst|$dst, $src2}",
1792 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
1793 (implicit EFLAGS)]>;
1795 def XOR8ri : Ii8<0x80, MRM6r,
1796 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1797 "xor{b}\t{$src2, $dst|$dst, $src2}",
1798 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
1799 (implicit EFLAGS)]>;
1800 def XOR16ri : Ii16<0x81, MRM6r,
1801 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1802 "xor{w}\t{$src2, $dst|$dst, $src2}",
1803 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
1804 (implicit EFLAGS)]>, OpSize;
1805 def XOR32ri : Ii32<0x81, MRM6r,
1806 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1807 "xor{l}\t{$src2, $dst|$dst, $src2}",
1808 [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
1809 (implicit EFLAGS)]>;
1810 def XOR16ri8 : Ii8<0x83, MRM6r,
1811 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1812 "xor{w}\t{$src2, $dst|$dst, $src2}",
1813 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
1814 (implicit EFLAGS)]>,
1816 def XOR32ri8 : Ii8<0x83, MRM6r,
1817 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1818 "xor{l}\t{$src2, $dst|$dst, $src2}",
1819 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
1820 (implicit EFLAGS)]>;
1822 let isTwoAddress = 0 in {
1823 def XOR8mr : I<0x30, MRMDestMem,
1824 (outs), (ins i8mem :$dst, GR8 :$src),
1825 "xor{b}\t{$src, $dst|$dst, $src}",
1826 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
1827 (implicit EFLAGS)]>;
1828 def XOR16mr : I<0x31, MRMDestMem,
1829 (outs), (ins i16mem:$dst, GR16:$src),
1830 "xor{w}\t{$src, $dst|$dst, $src}",
1831 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
1832 (implicit EFLAGS)]>,
1834 def XOR32mr : I<0x31, MRMDestMem,
1835 (outs), (ins i32mem:$dst, GR32:$src),
1836 "xor{l}\t{$src, $dst|$dst, $src}",
1837 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
1838 (implicit EFLAGS)]>;
1839 def XOR8mi : Ii8<0x80, MRM6m,
1840 (outs), (ins i8mem :$dst, i8imm :$src),
1841 "xor{b}\t{$src, $dst|$dst, $src}",
1842 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
1843 (implicit EFLAGS)]>;
1844 def XOR16mi : Ii16<0x81, MRM6m,
1845 (outs), (ins i16mem:$dst, i16imm:$src),
1846 "xor{w}\t{$src, $dst|$dst, $src}",
1847 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
1848 (implicit EFLAGS)]>,
1850 def XOR32mi : Ii32<0x81, MRM6m,
1851 (outs), (ins i32mem:$dst, i32imm:$src),
1852 "xor{l}\t{$src, $dst|$dst, $src}",
1853 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
1854 (implicit EFLAGS)]>;
1855 def XOR16mi8 : Ii8<0x83, MRM6m,
1856 (outs), (ins i16mem:$dst, i16i8imm :$src),
1857 "xor{w}\t{$src, $dst|$dst, $src}",
1858 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
1859 (implicit EFLAGS)]>,
1861 def XOR32mi8 : Ii8<0x83, MRM6m,
1862 (outs), (ins i32mem:$dst, i32i8imm :$src),
1863 "xor{l}\t{$src, $dst|$dst, $src}",
1864 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
1865 (implicit EFLAGS)]>;
1866 } // isTwoAddress = 0
1867 } // Defs = [EFLAGS]
1869 // Shift instructions
1870 let Defs = [EFLAGS] in {
1871 let Uses = [CL] in {
1872 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1873 "shl{b}\t{%cl, $dst|$dst, CL}",
1874 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1875 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1876 "shl{w}\t{%cl, $dst|$dst, CL}",
1877 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1878 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1879 "shl{l}\t{%cl, $dst|$dst, CL}",
1880 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1883 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1884 "shl{b}\t{$src2, $dst|$dst, $src2}",
1885 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1886 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1887 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1888 "shl{w}\t{$src2, $dst|$dst, $src2}",
1889 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1890 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1891 "shl{l}\t{$src2, $dst|$dst, $src2}",
1892 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1893 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1895 } // isConvertibleToThreeAddress = 1
1897 let isTwoAddress = 0 in {
1898 let Uses = [CL] in {
1899 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1900 "shl{b}\t{%cl, $dst|$dst, CL}",
1901 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1902 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1903 "shl{w}\t{%cl, $dst|$dst, CL}",
1904 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1905 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1906 "shl{l}\t{%cl, $dst|$dst, CL}",
1907 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1909 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1910 "shl{b}\t{$src, $dst|$dst, $src}",
1911 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1912 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1913 "shl{w}\t{$src, $dst|$dst, $src}",
1914 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1916 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1917 "shl{l}\t{$src, $dst|$dst, $src}",
1918 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1921 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1923 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1924 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1926 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1928 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1930 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1933 let Uses = [CL] in {
1934 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1935 "shr{b}\t{%cl, $dst|$dst, CL}",
1936 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1937 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1938 "shr{w}\t{%cl, $dst|$dst, CL}",
1939 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1940 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1941 "shr{l}\t{%cl, $dst|$dst, CL}",
1942 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1945 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1946 "shr{b}\t{$src2, $dst|$dst, $src2}",
1947 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1948 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1949 "shr{w}\t{$src2, $dst|$dst, $src2}",
1950 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1951 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1952 "shr{l}\t{$src2, $dst|$dst, $src2}",
1953 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1956 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1958 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1959 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1961 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1962 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1964 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1966 let isTwoAddress = 0 in {
1967 let Uses = [CL] in {
1968 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1969 "shr{b}\t{%cl, $dst|$dst, CL}",
1970 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1971 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1972 "shr{w}\t{%cl, $dst|$dst, CL}",
1973 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1975 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1976 "shr{l}\t{%cl, $dst|$dst, CL}",
1977 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1979 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1980 "shr{b}\t{$src, $dst|$dst, $src}",
1981 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1982 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1983 "shr{w}\t{$src, $dst|$dst, $src}",
1984 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1986 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1987 "shr{l}\t{$src, $dst|$dst, $src}",
1988 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1991 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1993 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1994 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1996 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1997 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1999 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2002 let Uses = [CL] in {
2003 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
2004 "sar{b}\t{%cl, $dst|$dst, CL}",
2005 [(set GR8:$dst, (sra GR8:$src, CL))]>;
2006 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
2007 "sar{w}\t{%cl, $dst|$dst, CL}",
2008 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
2009 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
2010 "sar{l}\t{%cl, $dst|$dst, CL}",
2011 [(set GR32:$dst, (sra GR32:$src, CL))]>;
2014 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2015 "sar{b}\t{$src2, $dst|$dst, $src2}",
2016 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2017 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2018 "sar{w}\t{$src2, $dst|$dst, $src2}",
2019 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2021 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2022 "sar{l}\t{$src2, $dst|$dst, $src2}",
2023 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2026 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2028 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2029 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2031 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2032 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2034 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2036 let isTwoAddress = 0 in {
2037 let Uses = [CL] in {
2038 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2039 "sar{b}\t{%cl, $dst|$dst, CL}",
2040 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2041 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2042 "sar{w}\t{%cl, $dst|$dst, CL}",
2043 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2044 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2045 "sar{l}\t{%cl, $dst|$dst, CL}",
2046 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2048 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2049 "sar{b}\t{$src, $dst|$dst, $src}",
2050 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2051 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2052 "sar{w}\t{$src, $dst|$dst, $src}",
2053 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2055 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2056 "sar{l}\t{$src, $dst|$dst, $src}",
2057 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2060 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2062 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2063 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2065 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2067 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2069 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2072 // Rotate instructions
2073 // FIXME: provide shorter instructions when imm8 == 1
2074 let Uses = [CL] in {
2075 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
2076 "rol{b}\t{%cl, $dst|$dst, CL}",
2077 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
2078 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
2079 "rol{w}\t{%cl, $dst|$dst, CL}",
2080 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
2081 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
2082 "rol{l}\t{%cl, $dst|$dst, CL}",
2083 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2086 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2087 "rol{b}\t{$src2, $dst|$dst, $src2}",
2088 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2089 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2090 "rol{w}\t{$src2, $dst|$dst, $src2}",
2091 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2092 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2093 "rol{l}\t{$src2, $dst|$dst, $src2}",
2094 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2097 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2099 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2100 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2102 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2103 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2105 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2107 let isTwoAddress = 0 in {
2108 let Uses = [CL] in {
2109 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2110 "rol{b}\t{%cl, $dst|$dst, CL}",
2111 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2112 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2113 "rol{w}\t{%cl, $dst|$dst, CL}",
2114 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2115 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2116 "rol{l}\t{%cl, $dst|$dst, CL}",
2117 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2119 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2120 "rol{b}\t{$src, $dst|$dst, $src}",
2121 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2122 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2123 "rol{w}\t{$src, $dst|$dst, $src}",
2124 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2126 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2127 "rol{l}\t{$src, $dst|$dst, $src}",
2128 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2131 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2133 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2134 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2136 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2138 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2140 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2143 let Uses = [CL] in {
2144 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2145 "ror{b}\t{%cl, $dst|$dst, CL}",
2146 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2147 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2148 "ror{w}\t{%cl, $dst|$dst, CL}",
2149 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2150 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2151 "ror{l}\t{%cl, $dst|$dst, CL}",
2152 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2155 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2156 "ror{b}\t{$src2, $dst|$dst, $src2}",
2157 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2158 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2159 "ror{w}\t{$src2, $dst|$dst, $src2}",
2160 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2161 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2162 "ror{l}\t{$src2, $dst|$dst, $src2}",
2163 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2166 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2168 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2169 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2171 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2172 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2174 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2176 let isTwoAddress = 0 in {
2177 let Uses = [CL] in {
2178 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2179 "ror{b}\t{%cl, $dst|$dst, CL}",
2180 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2181 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2182 "ror{w}\t{%cl, $dst|$dst, CL}",
2183 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2184 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2185 "ror{l}\t{%cl, $dst|$dst, CL}",
2186 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2188 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2189 "ror{b}\t{$src, $dst|$dst, $src}",
2190 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2191 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2192 "ror{w}\t{$src, $dst|$dst, $src}",
2193 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2195 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2196 "ror{l}\t{$src, $dst|$dst, $src}",
2197 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2200 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2202 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2203 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2205 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2207 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2209 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2214 // Double shift instructions (generalizations of rotate)
2215 let Uses = [CL] in {
2216 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2217 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2218 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2219 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2220 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2221 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2222 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2223 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2224 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2226 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2227 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2228 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2232 let isCommutable = 1 in { // These instructions commute to each other.
2233 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2234 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2235 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2236 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2239 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2240 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2241 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2242 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2245 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2246 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2247 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2248 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2251 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2252 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2253 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2254 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2259 let isTwoAddress = 0 in {
2260 let Uses = [CL] in {
2261 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2262 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2263 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2265 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2266 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2267 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2270 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2271 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2272 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2273 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2274 (i8 imm:$src3)), addr:$dst)]>,
2276 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2277 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2278 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2279 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2280 (i8 imm:$src3)), addr:$dst)]>,
2283 let Uses = [CL] in {
2284 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2285 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2286 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2287 addr:$dst)]>, TB, OpSize;
2288 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2289 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2290 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2291 addr:$dst)]>, TB, OpSize;
2293 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2294 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2295 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2296 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2297 (i8 imm:$src3)), addr:$dst)]>,
2299 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2300 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2301 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2302 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2303 (i8 imm:$src3)), addr:$dst)]>,
2306 } // Defs = [EFLAGS]
2310 let Defs = [EFLAGS] in {
2311 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2312 // Register-Register Addition
2313 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2314 (ins GR8 :$src1, GR8 :$src2),
2315 "add{b}\t{$src2, $dst|$dst, $src2}",
2316 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
2317 (implicit EFLAGS)]>;
2319 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2320 // Register-Register Addition
2321 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2322 (ins GR16:$src1, GR16:$src2),
2323 "add{w}\t{$src2, $dst|$dst, $src2}",
2324 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2325 (implicit EFLAGS)]>, OpSize;
2326 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2327 (ins GR32:$src1, GR32:$src2),
2328 "add{l}\t{$src2, $dst|$dst, $src2}",
2329 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2330 (implicit EFLAGS)]>;
2331 } // end isConvertibleToThreeAddress
2332 } // end isCommutable
2334 // Register-Memory Addition
2335 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2336 (ins GR8 :$src1, i8mem :$src2),
2337 "add{b}\t{$src2, $dst|$dst, $src2}",
2338 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2339 (implicit EFLAGS)]>;
2340 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2341 (ins GR16:$src1, i16mem:$src2),
2342 "add{w}\t{$src2, $dst|$dst, $src2}",
2343 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2344 (implicit EFLAGS)]>, OpSize;
2345 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2346 (ins GR32:$src1, i32mem:$src2),
2347 "add{l}\t{$src2, $dst|$dst, $src2}",
2348 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2349 (implicit EFLAGS)]>;
2351 // Register-Integer Addition
2352 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2353 "add{b}\t{$src2, $dst|$dst, $src2}",
2354 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2355 (implicit EFLAGS)]>;
2357 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2358 // Register-Integer Addition
2359 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2360 (ins GR16:$src1, i16imm:$src2),
2361 "add{w}\t{$src2, $dst|$dst, $src2}",
2362 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2363 (implicit EFLAGS)]>, OpSize;
2364 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2365 (ins GR32:$src1, i32imm:$src2),
2366 "add{l}\t{$src2, $dst|$dst, $src2}",
2367 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2368 (implicit EFLAGS)]>;
2369 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2370 (ins GR16:$src1, i16i8imm:$src2),
2371 "add{w}\t{$src2, $dst|$dst, $src2}",
2372 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2373 (implicit EFLAGS)]>, OpSize;
2374 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2375 (ins GR32:$src1, i32i8imm:$src2),
2376 "add{l}\t{$src2, $dst|$dst, $src2}",
2377 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2378 (implicit EFLAGS)]>;
2381 let isTwoAddress = 0 in {
2382 // Memory-Register Addition
2383 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2384 "add{b}\t{$src2, $dst|$dst, $src2}",
2385 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2386 (implicit EFLAGS)]>;
2387 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2388 "add{w}\t{$src2, $dst|$dst, $src2}",
2389 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2390 (implicit EFLAGS)]>, OpSize;
2391 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2392 "add{l}\t{$src2, $dst|$dst, $src2}",
2393 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2394 (implicit EFLAGS)]>;
2395 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2396 "add{b}\t{$src2, $dst|$dst, $src2}",
2397 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2398 (implicit EFLAGS)]>;
2399 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2400 "add{w}\t{$src2, $dst|$dst, $src2}",
2401 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2402 (implicit EFLAGS)]>, OpSize;
2403 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2404 "add{l}\t{$src2, $dst|$dst, $src2}",
2405 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2406 (implicit EFLAGS)]>;
2407 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2408 "add{w}\t{$src2, $dst|$dst, $src2}",
2409 [(store (add (load addr:$dst), i16immSExt8:$src2),
2411 (implicit EFLAGS)]>, OpSize;
2412 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2413 "add{l}\t{$src2, $dst|$dst, $src2}",
2414 [(store (add (load addr:$dst), i32immSExt8:$src2),
2416 (implicit EFLAGS)]>;
2419 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2420 "add{b}\t{$src, %al|%al, $src}", []>;
2421 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2422 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2423 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2424 "add{l}\t{$src, %eax|%eax, $src}", []>;
2427 let Uses = [EFLAGS] in {
2428 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2429 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2430 "adc{b}\t{$src2, $dst|$dst, $src2}",
2431 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2432 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2433 (ins GR16:$src1, GR16:$src2),
2434 "adc{w}\t{$src2, $dst|$dst, $src2}",
2435 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2436 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2437 (ins GR32:$src1, GR32:$src2),
2438 "adc{l}\t{$src2, $dst|$dst, $src2}",
2439 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2441 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2442 (ins GR8:$src1, i8mem:$src2),
2443 "adc{b}\t{$src2, $dst|$dst, $src2}",
2444 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2445 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2446 (ins GR16:$src1, i16mem:$src2),
2447 "adc{w}\t{$src2, $dst|$dst, $src2}",
2448 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2450 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2451 (ins GR32:$src1, i32mem:$src2),
2452 "adc{l}\t{$src2, $dst|$dst, $src2}",
2453 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2454 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2455 "adc{b}\t{$src2, $dst|$dst, $src2}",
2456 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2457 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2458 (ins GR16:$src1, i16imm:$src2),
2459 "adc{w}\t{$src2, $dst|$dst, $src2}",
2460 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2461 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2462 (ins GR16:$src1, i16i8imm:$src2),
2463 "adc{w}\t{$src2, $dst|$dst, $src2}",
2464 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2466 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2467 (ins GR32:$src1, i32imm:$src2),
2468 "adc{l}\t{$src2, $dst|$dst, $src2}",
2469 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2470 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2471 (ins GR32:$src1, i32i8imm:$src2),
2472 "adc{l}\t{$src2, $dst|$dst, $src2}",
2473 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2475 let isTwoAddress = 0 in {
2476 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2477 "adc{b}\t{$src2, $dst|$dst, $src2}",
2478 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2479 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2480 "adc{w}\t{$src2, $dst|$dst, $src2}",
2481 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2483 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2484 "adc{l}\t{$src2, $dst|$dst, $src2}",
2485 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2486 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2487 "adc{b}\t{$src2, $dst|$dst, $src2}",
2488 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2489 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2490 "adc{w}\t{$src2, $dst|$dst, $src2}",
2491 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2493 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2494 "adc{w}\t{$src2, $dst|$dst, $src2}",
2495 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2497 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2498 "adc{l}\t{$src2, $dst|$dst, $src2}",
2499 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2500 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2501 "adc{l}\t{$src2, $dst|$dst, $src2}",
2502 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2504 } // Uses = [EFLAGS]
2506 // Register-Register Subtraction
2507 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2508 "sub{b}\t{$src2, $dst|$dst, $src2}",
2509 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2510 (implicit EFLAGS)]>;
2511 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2512 "sub{w}\t{$src2, $dst|$dst, $src2}",
2513 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2514 (implicit EFLAGS)]>, OpSize;
2515 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2516 "sub{l}\t{$src2, $dst|$dst, $src2}",
2517 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2518 (implicit EFLAGS)]>;
2520 // Register-Memory Subtraction
2521 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2522 (ins GR8 :$src1, i8mem :$src2),
2523 "sub{b}\t{$src2, $dst|$dst, $src2}",
2524 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2525 (implicit EFLAGS)]>;
2526 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2527 (ins GR16:$src1, i16mem:$src2),
2528 "sub{w}\t{$src2, $dst|$dst, $src2}",
2529 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2530 (implicit EFLAGS)]>, OpSize;
2531 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2532 (ins GR32:$src1, i32mem:$src2),
2533 "sub{l}\t{$src2, $dst|$dst, $src2}",
2534 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2535 (implicit EFLAGS)]>;
2537 // Register-Integer Subtraction
2538 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2539 (ins GR8:$src1, i8imm:$src2),
2540 "sub{b}\t{$src2, $dst|$dst, $src2}",
2541 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2542 (implicit EFLAGS)]>;
2543 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2544 (ins GR16:$src1, i16imm:$src2),
2545 "sub{w}\t{$src2, $dst|$dst, $src2}",
2546 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2547 (implicit EFLAGS)]>, OpSize;
2548 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2549 (ins GR32:$src1, i32imm:$src2),
2550 "sub{l}\t{$src2, $dst|$dst, $src2}",
2551 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2552 (implicit EFLAGS)]>;
2553 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2554 (ins GR16:$src1, i16i8imm:$src2),
2555 "sub{w}\t{$src2, $dst|$dst, $src2}",
2556 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2557 (implicit EFLAGS)]>, OpSize;
2558 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2559 (ins GR32:$src1, i32i8imm:$src2),
2560 "sub{l}\t{$src2, $dst|$dst, $src2}",
2561 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2562 (implicit EFLAGS)]>;
2564 let isTwoAddress = 0 in {
2565 // Memory-Register Subtraction
2566 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2567 "sub{b}\t{$src2, $dst|$dst, $src2}",
2568 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2569 (implicit EFLAGS)]>;
2570 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2571 "sub{w}\t{$src2, $dst|$dst, $src2}",
2572 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2573 (implicit EFLAGS)]>, OpSize;
2574 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2575 "sub{l}\t{$src2, $dst|$dst, $src2}",
2576 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2577 (implicit EFLAGS)]>;
2579 // Memory-Integer Subtraction
2580 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2581 "sub{b}\t{$src2, $dst|$dst, $src2}",
2582 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2583 (implicit EFLAGS)]>;
2584 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2585 "sub{w}\t{$src2, $dst|$dst, $src2}",
2586 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2587 (implicit EFLAGS)]>, OpSize;
2588 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2589 "sub{l}\t{$src2, $dst|$dst, $src2}",
2590 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2591 (implicit EFLAGS)]>;
2592 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2593 "sub{w}\t{$src2, $dst|$dst, $src2}",
2594 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2596 (implicit EFLAGS)]>, OpSize;
2597 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2598 "sub{l}\t{$src2, $dst|$dst, $src2}",
2599 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2601 (implicit EFLAGS)]>;
2604 let Uses = [EFLAGS] in {
2605 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
2606 (ins GR8:$src1, GR8:$src2),
2607 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2608 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
2609 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
2610 (ins GR16:$src1, GR16:$src2),
2611 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2612 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
2613 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
2614 (ins GR32:$src1, GR32:$src2),
2615 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2616 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2618 let isTwoAddress = 0 in {
2619 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2620 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2621 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
2622 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2623 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2624 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
2626 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2627 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2628 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2629 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2630 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2631 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2632 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
2633 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2634 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2636 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2637 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2638 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2640 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2641 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2642 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2643 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2644 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2645 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2647 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
2648 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2649 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
2650 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
2651 (ins GR16:$src1, i16mem:$src2),
2652 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2653 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
2655 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
2656 (ins GR32:$src1, i32mem:$src2),
2657 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2658 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2659 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2660 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2661 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
2662 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
2663 (ins GR16:$src1, i16imm:$src2),
2664 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2665 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
2666 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
2667 (ins GR16:$src1, i16i8imm:$src2),
2668 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2669 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
2671 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
2672 (ins GR32:$src1, i32imm:$src2),
2673 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2674 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2675 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
2676 (ins GR32:$src1, i32i8imm:$src2),
2677 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2678 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2679 } // Uses = [EFLAGS]
2680 } // Defs = [EFLAGS]
2682 let Defs = [EFLAGS] in {
2683 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2684 // Register-Register Signed Integer Multiply
2685 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2686 "imul{w}\t{$src2, $dst|$dst, $src2}",
2687 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
2688 (implicit EFLAGS)]>, TB, OpSize;
2689 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2690 "imul{l}\t{$src2, $dst|$dst, $src2}",
2691 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
2692 (implicit EFLAGS)]>, TB;
2695 // Register-Memory Signed Integer Multiply
2696 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
2697 (ins GR16:$src1, i16mem:$src2),
2698 "imul{w}\t{$src2, $dst|$dst, $src2}",
2699 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
2700 (implicit EFLAGS)]>, TB, OpSize;
2701 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2702 "imul{l}\t{$src2, $dst|$dst, $src2}",
2703 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
2704 (implicit EFLAGS)]>, TB;
2705 } // Defs = [EFLAGS]
2706 } // end Two Address instructions
2708 // Suprisingly enough, these are not two address instructions!
2709 let Defs = [EFLAGS] in {
2710 // Register-Integer Signed Integer Multiply
2711 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2712 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2713 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2714 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
2715 (implicit EFLAGS)]>, OpSize;
2716 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2717 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2718 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2719 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
2720 (implicit EFLAGS)]>;
2721 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2722 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2723 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2724 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
2725 (implicit EFLAGS)]>, OpSize;
2726 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2727 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2728 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2729 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
2730 (implicit EFLAGS)]>;
2732 // Memory-Integer Signed Integer Multiply
2733 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2734 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2735 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2736 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
2737 (implicit EFLAGS)]>, OpSize;
2738 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2739 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2740 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2741 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
2742 (implicit EFLAGS)]>;
2743 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2744 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2745 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2746 [(set GR16:$dst, (mul (load addr:$src1),
2747 i16immSExt8:$src2)),
2748 (implicit EFLAGS)]>, OpSize;
2749 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2750 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2751 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2752 [(set GR32:$dst, (mul (load addr:$src1),
2753 i32immSExt8:$src2)),
2754 (implicit EFLAGS)]>;
2755 } // Defs = [EFLAGS]
2757 //===----------------------------------------------------------------------===//
2758 // Test instructions are just like AND, except they don't generate a result.
2760 let Defs = [EFLAGS] in {
2761 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2762 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2763 "test{b}\t{$src2, $src1|$src1, $src2}",
2764 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
2765 (implicit EFLAGS)]>;
2766 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2767 "test{w}\t{$src2, $src1|$src1, $src2}",
2768 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
2769 (implicit EFLAGS)]>,
2771 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2772 "test{l}\t{$src2, $src1|$src1, $src2}",
2773 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
2774 (implicit EFLAGS)]>;
2777 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
2778 "test{b}\t{$src, %al|%al, $src}", []>;
2779 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
2780 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2781 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
2782 "test{l}\t{$src, %eax|%eax, $src}", []>;
2784 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2785 "test{b}\t{$src2, $src1|$src1, $src2}",
2786 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2787 (implicit EFLAGS)]>;
2788 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2789 "test{w}\t{$src2, $src1|$src1, $src2}",
2790 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2791 (implicit EFLAGS)]>, OpSize;
2792 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2793 "test{l}\t{$src2, $src1|$src1, $src2}",
2794 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2795 (implicit EFLAGS)]>;
2797 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2798 (outs), (ins GR8:$src1, i8imm:$src2),
2799 "test{b}\t{$src2, $src1|$src1, $src2}",
2800 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
2801 (implicit EFLAGS)]>;
2802 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2803 (outs), (ins GR16:$src1, i16imm:$src2),
2804 "test{w}\t{$src2, $src1|$src1, $src2}",
2805 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
2806 (implicit EFLAGS)]>, OpSize;
2807 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2808 (outs), (ins GR32:$src1, i32imm:$src2),
2809 "test{l}\t{$src2, $src1|$src1, $src2}",
2810 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
2811 (implicit EFLAGS)]>;
2813 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2814 (outs), (ins i8mem:$src1, i8imm:$src2),
2815 "test{b}\t{$src2, $src1|$src1, $src2}",
2816 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2817 (implicit EFLAGS)]>;
2818 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2819 (outs), (ins i16mem:$src1, i16imm:$src2),
2820 "test{w}\t{$src2, $src1|$src1, $src2}",
2821 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2822 (implicit EFLAGS)]>, OpSize;
2823 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2824 (outs), (ins i32mem:$src1, i32imm:$src2),
2825 "test{l}\t{$src2, $src1|$src1, $src2}",
2826 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2827 (implicit EFLAGS)]>;
2828 } // Defs = [EFLAGS]
2831 // Condition code ops, incl. set if equal/not equal/...
2832 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2833 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2834 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2835 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2837 let Uses = [EFLAGS] in {
2838 def SETEr : I<0x94, MRM0r,
2839 (outs GR8 :$dst), (ins),
2841 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2843 def SETEm : I<0x94, MRM0m,
2844 (outs), (ins i8mem:$dst),
2846 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2849 def SETNEr : I<0x95, MRM0r,
2850 (outs GR8 :$dst), (ins),
2852 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2854 def SETNEm : I<0x95, MRM0m,
2855 (outs), (ins i8mem:$dst),
2857 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2860 def SETLr : I<0x9C, MRM0r,
2861 (outs GR8 :$dst), (ins),
2863 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2864 TB; // GR8 = < signed
2865 def SETLm : I<0x9C, MRM0m,
2866 (outs), (ins i8mem:$dst),
2868 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2869 TB; // [mem8] = < signed
2871 def SETGEr : I<0x9D, MRM0r,
2872 (outs GR8 :$dst), (ins),
2874 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2875 TB; // GR8 = >= signed
2876 def SETGEm : I<0x9D, MRM0m,
2877 (outs), (ins i8mem:$dst),
2879 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2880 TB; // [mem8] = >= signed
2882 def SETLEr : I<0x9E, MRM0r,
2883 (outs GR8 :$dst), (ins),
2885 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2886 TB; // GR8 = <= signed
2887 def SETLEm : I<0x9E, MRM0m,
2888 (outs), (ins i8mem:$dst),
2890 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2891 TB; // [mem8] = <= signed
2893 def SETGr : I<0x9F, MRM0r,
2894 (outs GR8 :$dst), (ins),
2896 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2897 TB; // GR8 = > signed
2898 def SETGm : I<0x9F, MRM0m,
2899 (outs), (ins i8mem:$dst),
2901 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2902 TB; // [mem8] = > signed
2904 def SETBr : I<0x92, MRM0r,
2905 (outs GR8 :$dst), (ins),
2907 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2908 TB; // GR8 = < unsign
2909 def SETBm : I<0x92, MRM0m,
2910 (outs), (ins i8mem:$dst),
2912 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
2913 TB; // [mem8] = < unsign
2915 def SETAEr : I<0x93, MRM0r,
2916 (outs GR8 :$dst), (ins),
2918 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
2919 TB; // GR8 = >= unsign
2920 def SETAEm : I<0x93, MRM0m,
2921 (outs), (ins i8mem:$dst),
2923 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
2924 TB; // [mem8] = >= unsign
2926 def SETBEr : I<0x96, MRM0r,
2927 (outs GR8 :$dst), (ins),
2929 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
2930 TB; // GR8 = <= unsign
2931 def SETBEm : I<0x96, MRM0m,
2932 (outs), (ins i8mem:$dst),
2934 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
2935 TB; // [mem8] = <= unsign
2937 def SETAr : I<0x97, MRM0r,
2938 (outs GR8 :$dst), (ins),
2940 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
2941 TB; // GR8 = > signed
2942 def SETAm : I<0x97, MRM0m,
2943 (outs), (ins i8mem:$dst),
2945 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
2946 TB; // [mem8] = > signed
2948 def SETSr : I<0x98, MRM0r,
2949 (outs GR8 :$dst), (ins),
2951 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
2952 TB; // GR8 = <sign bit>
2953 def SETSm : I<0x98, MRM0m,
2954 (outs), (ins i8mem:$dst),
2956 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
2957 TB; // [mem8] = <sign bit>
2958 def SETNSr : I<0x99, MRM0r,
2959 (outs GR8 :$dst), (ins),
2961 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
2962 TB; // GR8 = !<sign bit>
2963 def SETNSm : I<0x99, MRM0m,
2964 (outs), (ins i8mem:$dst),
2966 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
2967 TB; // [mem8] = !<sign bit>
2969 def SETPr : I<0x9A, MRM0r,
2970 (outs GR8 :$dst), (ins),
2972 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
2974 def SETPm : I<0x9A, MRM0m,
2975 (outs), (ins i8mem:$dst),
2977 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
2978 TB; // [mem8] = parity
2979 def SETNPr : I<0x9B, MRM0r,
2980 (outs GR8 :$dst), (ins),
2982 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
2983 TB; // GR8 = not parity
2984 def SETNPm : I<0x9B, MRM0m,
2985 (outs), (ins i8mem:$dst),
2987 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
2988 TB; // [mem8] = not parity
2990 def SETOr : I<0x90, MRM0r,
2991 (outs GR8 :$dst), (ins),
2993 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
2994 TB; // GR8 = overflow
2995 def SETOm : I<0x90, MRM0m,
2996 (outs), (ins i8mem:$dst),
2998 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
2999 TB; // [mem8] = overflow
3000 def SETNOr : I<0x91, MRM0r,
3001 (outs GR8 :$dst), (ins),
3003 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3004 TB; // GR8 = not overflow
3005 def SETNOm : I<0x91, MRM0m,
3006 (outs), (ins i8mem:$dst),
3008 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3009 TB; // [mem8] = not overflow
3010 } // Uses = [EFLAGS]
3013 // Integer comparisons
3014 let Defs = [EFLAGS] in {
3015 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3016 "cmp{b}\t{$src, %al|%al, $src}", []>;
3017 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3018 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3019 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3020 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3022 def CMP8rr : I<0x38, MRMDestReg,
3023 (outs), (ins GR8 :$src1, GR8 :$src2),
3024 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3025 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
3026 def CMP16rr : I<0x39, MRMDestReg,
3027 (outs), (ins GR16:$src1, GR16:$src2),
3028 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3029 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
3030 def CMP32rr : I<0x39, MRMDestReg,
3031 (outs), (ins GR32:$src1, GR32:$src2),
3032 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3033 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
3034 def CMP8mr : I<0x38, MRMDestMem,
3035 (outs), (ins i8mem :$src1, GR8 :$src2),
3036 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3037 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
3038 (implicit EFLAGS)]>;
3039 def CMP16mr : I<0x39, MRMDestMem,
3040 (outs), (ins i16mem:$src1, GR16:$src2),
3041 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3042 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
3043 (implicit EFLAGS)]>, OpSize;
3044 def CMP32mr : I<0x39, MRMDestMem,
3045 (outs), (ins i32mem:$src1, GR32:$src2),
3046 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3047 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
3048 (implicit EFLAGS)]>;
3049 def CMP8rm : I<0x3A, MRMSrcMem,
3050 (outs), (ins GR8 :$src1, i8mem :$src2),
3051 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3052 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
3053 (implicit EFLAGS)]>;
3054 def CMP16rm : I<0x3B, MRMSrcMem,
3055 (outs), (ins GR16:$src1, i16mem:$src2),
3056 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3057 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
3058 (implicit EFLAGS)]>, OpSize;
3059 def CMP32rm : I<0x3B, MRMSrcMem,
3060 (outs), (ins GR32:$src1, i32mem:$src2),
3061 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3062 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
3063 (implicit EFLAGS)]>;
3064 def CMP8ri : Ii8<0x80, MRM7r,
3065 (outs), (ins GR8:$src1, i8imm:$src2),
3066 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3067 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
3068 def CMP16ri : Ii16<0x81, MRM7r,
3069 (outs), (ins GR16:$src1, i16imm:$src2),
3070 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3071 [(X86cmp GR16:$src1, imm:$src2),
3072 (implicit EFLAGS)]>, OpSize;
3073 def CMP32ri : Ii32<0x81, MRM7r,
3074 (outs), (ins GR32:$src1, i32imm:$src2),
3075 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3076 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
3077 def CMP8mi : Ii8 <0x80, MRM7m,
3078 (outs), (ins i8mem :$src1, i8imm :$src2),
3079 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3080 [(X86cmp (loadi8 addr:$src1), imm:$src2),
3081 (implicit EFLAGS)]>;
3082 def CMP16mi : Ii16<0x81, MRM7m,
3083 (outs), (ins i16mem:$src1, i16imm:$src2),
3084 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3085 [(X86cmp (loadi16 addr:$src1), imm:$src2),
3086 (implicit EFLAGS)]>, OpSize;
3087 def CMP32mi : Ii32<0x81, MRM7m,
3088 (outs), (ins i32mem:$src1, i32imm:$src2),
3089 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3090 [(X86cmp (loadi32 addr:$src1), imm:$src2),
3091 (implicit EFLAGS)]>;
3092 def CMP16ri8 : Ii8<0x83, MRM7r,
3093 (outs), (ins GR16:$src1, i16i8imm:$src2),
3094 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3095 [(X86cmp GR16:$src1, i16immSExt8:$src2),
3096 (implicit EFLAGS)]>, OpSize;
3097 def CMP16mi8 : Ii8<0x83, MRM7m,
3098 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3099 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3100 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
3101 (implicit EFLAGS)]>, OpSize;
3102 def CMP32mi8 : Ii8<0x83, MRM7m,
3103 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3104 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3105 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
3106 (implicit EFLAGS)]>;
3107 def CMP32ri8 : Ii8<0x83, MRM7r,
3108 (outs), (ins GR32:$src1, i32i8imm:$src2),
3109 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3110 [(X86cmp GR32:$src1, i32immSExt8:$src2),
3111 (implicit EFLAGS)]>;
3112 } // Defs = [EFLAGS]
3115 // TODO: BTC, BTR, and BTS
3116 let Defs = [EFLAGS] in {
3117 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3118 "bt{w}\t{$src2, $src1|$src1, $src2}",
3119 [(X86bt GR16:$src1, GR16:$src2),
3120 (implicit EFLAGS)]>, OpSize, TB;
3121 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3122 "bt{l}\t{$src2, $src1|$src1, $src2}",
3123 [(X86bt GR32:$src1, GR32:$src2),
3124 (implicit EFLAGS)]>, TB;
3126 // Unlike with the register+register form, the memory+register form of the
3127 // bt instruction does not ignore the high bits of the index. From ISel's
3128 // perspective, this is pretty bizarre. Disable these instructions for now.
3129 //def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3130 // "bt{w}\t{$src2, $src1|$src1, $src2}",
3131 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3132 // (implicit EFLAGS)]>, OpSize, TB, Requires<[FastBTMem]>;
3133 //def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3134 // "bt{l}\t{$src2, $src1|$src1, $src2}",
3135 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3136 // (implicit EFLAGS)]>, TB, Requires<[FastBTMem]>;
3138 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3139 "bt{w}\t{$src2, $src1|$src1, $src2}",
3140 [(X86bt GR16:$src1, i16immSExt8:$src2),
3141 (implicit EFLAGS)]>, OpSize, TB;
3142 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3143 "bt{l}\t{$src2, $src1|$src1, $src2}",
3144 [(X86bt GR32:$src1, i32immSExt8:$src2),
3145 (implicit EFLAGS)]>, TB;
3146 // Note that these instructions don't need FastBTMem because that
3147 // only applies when the other operand is in a register. When it's
3148 // an immediate, bt is still fast.
3149 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3150 "bt{w}\t{$src2, $src1|$src1, $src2}",
3151 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
3152 (implicit EFLAGS)]>, OpSize, TB;
3153 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3154 "bt{l}\t{$src2, $src1|$src1, $src2}",
3155 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
3156 (implicit EFLAGS)]>, TB;
3157 } // Defs = [EFLAGS]
3159 // Sign/Zero extenders
3160 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3161 // of the register here. This has a smaller encoding and avoids a
3162 // partial-register update.
3163 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3164 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3165 [(set GR16:$dst, (sext GR8:$src))]>, TB;
3166 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3167 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3168 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3169 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3170 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3171 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3172 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3173 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3174 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3175 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3176 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3177 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3178 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3179 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3180 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3182 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3183 // of the register here. This has a smaller encoding and avoids a
3184 // partial-register update.
3185 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3186 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3187 [(set GR16:$dst, (zext GR8:$src))]>, TB;
3188 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3189 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3190 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3191 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3192 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3193 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3194 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3195 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3196 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3197 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3198 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3199 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3200 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3201 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3202 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3204 // These are the same as the regular regular MOVZX32rr8 and MOVZX32rm8
3205 // except that they use GR32_NOREX for the output operand register class
3206 // instead of GR32. This allows them to operate on h registers on x86-64.
3207 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3208 (outs GR32_NOREX:$dst), (ins GR8:$src),
3209 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3212 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3213 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3214 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3217 let neverHasSideEffects = 1 in {
3218 let Defs = [AX], Uses = [AL] in
3219 def CBW : I<0x98, RawFrm, (outs), (ins),
3220 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3221 let Defs = [EAX], Uses = [AX] in
3222 def CWDE : I<0x98, RawFrm, (outs), (ins),
3223 "{cwtl|cwde}", []>; // EAX = signext(AX)
3225 let Defs = [AX,DX], Uses = [AX] in
3226 def CWD : I<0x99, RawFrm, (outs), (ins),
3227 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3228 let Defs = [EAX,EDX], Uses = [EAX] in
3229 def CDQ : I<0x99, RawFrm, (outs), (ins),
3230 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3233 //===----------------------------------------------------------------------===//
3234 // Alias Instructions
3235 //===----------------------------------------------------------------------===//
3237 // Alias instructions that map movr0 to xor.
3238 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3239 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3240 isCodeGenOnly = 1 in {
3241 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
3242 "xor{b}\t$dst, $dst",
3243 [(set GR8:$dst, 0)]>;
3244 // Use xorl instead of xorw since we don't care about the high 16 bits,
3245 // it's smaller, and it avoids a partial-register update.
3246 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3247 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
3248 [(set GR16:$dst, 0)]>;
3249 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
3250 "xor{l}\t$dst, $dst",
3251 [(set GR32:$dst, 0)]>;
3254 //===----------------------------------------------------------------------===//
3255 // Thread Local Storage Instructions
3258 // All calls clobber the non-callee saved registers. ESP is marked as
3259 // a use to prevent stack-pointer assignments that appear immediately
3260 // before calls from potentially appearing dead.
3261 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3262 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3263 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3264 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3266 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3267 "leal\t$sym, %eax; "
3268 "call\t___tls_get_addr@PLT",
3269 [(X86tlsaddr tls32addr:$sym)]>,
3270 Requires<[In32BitMode]>;
3272 let AddedComplexity = 5, isCodeGenOnly = 1 in
3273 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3274 "movl\t%gs:$src, $dst",
3275 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3277 let AddedComplexity = 5, isCodeGenOnly = 1 in
3278 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3279 "movl\t%fs:$src, $dst",
3280 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3282 //===----------------------------------------------------------------------===//
3283 // DWARF Pseudo Instructions
3286 def DWARF_LOC : I<0, Pseudo, (outs),
3287 (ins i32imm:$line, i32imm:$col, i32imm:$file),
3288 ".loc\t$file $line $col",
3289 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
3292 //===----------------------------------------------------------------------===//
3293 // EH Pseudo Instructions
3295 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3296 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3297 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3298 "ret\t#eh_return, addr: $addr",
3299 [(X86ehret GR32:$addr)]>;
3303 //===----------------------------------------------------------------------===//
3307 // Atomic swap. These are just normal xchg instructions. But since a memory
3308 // operand is referenced, the atomicity is ensured.
3309 let Constraints = "$val = $dst" in {
3310 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3311 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3312 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3313 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3314 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3315 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3317 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3318 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3319 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3322 // Atomic compare and swap.
3323 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3324 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3326 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3327 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3329 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3330 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
3333 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3336 let Defs = [AX, EFLAGS], Uses = [AX] in {
3337 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3339 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3340 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3342 let Defs = [AL, EFLAGS], Uses = [AL] in {
3343 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3345 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3346 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3349 // Atomic exchange and add
3350 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3351 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3353 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3354 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3356 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3358 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3359 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3361 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3363 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3364 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3368 // Optimized codegen when the non-memory output is not used.
3369 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3370 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3372 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3373 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3375 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3376 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3378 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3379 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3381 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3382 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3384 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3385 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3387 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3388 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3390 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3391 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3393 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3395 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3397 "inc{b}\t$dst", []>, LOCK;
3398 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3400 "inc{w}\t$dst", []>, OpSize, LOCK;
3401 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3403 "inc{l}\t$dst", []>, LOCK;
3405 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3407 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3408 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3410 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3411 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3413 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3414 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3416 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3417 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3419 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3420 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3422 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3423 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3425 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3426 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3428 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3430 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3432 "dec{b}\t$dst", []>, LOCK;
3433 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3435 "dec{w}\t$dst", []>, OpSize, LOCK;
3436 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3438 "dec{l}\t$dst", []>, LOCK;
3440 // Atomic exchange, and, or, xor
3441 let Constraints = "$val = $dst", Defs = [EFLAGS],
3442 usesCustomDAGSchedInserter = 1 in {
3443 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3444 "#ATOMAND32 PSEUDO!",
3445 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3446 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3447 "#ATOMOR32 PSEUDO!",
3448 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
3449 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3450 "#ATOMXOR32 PSEUDO!",
3451 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
3452 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3453 "#ATOMNAND32 PSEUDO!",
3454 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
3455 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3456 "#ATOMMIN32 PSEUDO!",
3457 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
3458 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3459 "#ATOMMAX32 PSEUDO!",
3460 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
3461 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3462 "#ATOMUMIN32 PSEUDO!",
3463 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
3464 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3465 "#ATOMUMAX32 PSEUDO!",
3466 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
3468 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3469 "#ATOMAND16 PSEUDO!",
3470 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
3471 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3472 "#ATOMOR16 PSEUDO!",
3473 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
3474 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3475 "#ATOMXOR16 PSEUDO!",
3476 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
3477 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3478 "#ATOMNAND16 PSEUDO!",
3479 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
3480 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3481 "#ATOMMIN16 PSEUDO!",
3482 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
3483 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3484 "#ATOMMAX16 PSEUDO!",
3485 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
3486 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3487 "#ATOMUMIN16 PSEUDO!",
3488 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
3489 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3490 "#ATOMUMAX16 PSEUDO!",
3491 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
3493 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3494 "#ATOMAND8 PSEUDO!",
3495 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
3496 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3498 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
3499 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3500 "#ATOMXOR8 PSEUDO!",
3501 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
3502 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3503 "#ATOMNAND8 PSEUDO!",
3504 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
3507 let Constraints = "$val1 = $dst1, $val2 = $dst2",
3508 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
3509 Uses = [EAX, EBX, ECX, EDX],
3510 mayLoad = 1, mayStore = 1,
3511 usesCustomDAGSchedInserter = 1 in {
3512 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3513 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3514 "#ATOMAND6432 PSEUDO!", []>;
3515 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3516 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3517 "#ATOMOR6432 PSEUDO!", []>;
3518 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3519 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3520 "#ATOMXOR6432 PSEUDO!", []>;
3521 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3522 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3523 "#ATOMNAND6432 PSEUDO!", []>;
3524 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3525 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3526 "#ATOMADD6432 PSEUDO!", []>;
3527 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3528 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3529 "#ATOMSUB6432 PSEUDO!", []>;
3530 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3531 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3532 "#ATOMSWAP6432 PSEUDO!", []>;
3535 //===----------------------------------------------------------------------===//
3536 // Non-Instruction Patterns
3537 //===----------------------------------------------------------------------===//
3539 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
3540 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
3541 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
3542 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
3543 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
3544 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
3546 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
3547 (ADD32ri GR32:$src1, tconstpool:$src2)>;
3548 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
3549 (ADD32ri GR32:$src1, tjumptable:$src2)>;
3550 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
3551 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
3552 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
3553 (ADD32ri GR32:$src1, texternalsym:$src2)>;
3555 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
3556 (MOV32mi addr:$dst, tglobaladdr:$src)>;
3557 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
3558 (MOV32mi addr:$dst, texternalsym:$src)>;
3562 def : Pat<(X86tcret GR32:$dst, imm:$off),
3563 (TCRETURNri GR32:$dst, imm:$off)>;
3565 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
3566 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3568 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
3569 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3571 // Normal calls, with various flavors of addresses.
3572 def : Pat<(X86call (i32 tglobaladdr:$dst)),
3573 (CALLpcrel32 tglobaladdr:$dst)>;
3574 def : Pat<(X86call (i32 texternalsym:$dst)),
3575 (CALLpcrel32 texternalsym:$dst)>;
3576 def : Pat<(X86call (i32 imm:$dst)),
3577 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
3579 // X86 specific add which produces a flag.
3580 def : Pat<(addc GR32:$src1, GR32:$src2),
3581 (ADD32rr GR32:$src1, GR32:$src2)>;
3582 def : Pat<(addc GR32:$src1, (load addr:$src2)),
3583 (ADD32rm GR32:$src1, addr:$src2)>;
3584 def : Pat<(addc GR32:$src1, imm:$src2),
3585 (ADD32ri GR32:$src1, imm:$src2)>;
3586 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
3587 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3589 def : Pat<(subc GR32:$src1, GR32:$src2),
3590 (SUB32rr GR32:$src1, GR32:$src2)>;
3591 def : Pat<(subc GR32:$src1, (load addr:$src2)),
3592 (SUB32rm GR32:$src1, addr:$src2)>;
3593 def : Pat<(subc GR32:$src1, imm:$src2),
3594 (SUB32ri GR32:$src1, imm:$src2)>;
3595 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
3596 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3600 // TEST R,R is smaller than CMP R,0
3601 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
3602 (TEST8rr GR8:$src1, GR8:$src1)>;
3603 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
3604 (TEST16rr GR16:$src1, GR16:$src1)>;
3605 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
3606 (TEST32rr GR32:$src1, GR32:$src1)>;
3608 // Conditional moves with folded loads with operands swapped and conditions
3610 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
3611 (CMOVAE16rm GR16:$src2, addr:$src1)>;
3612 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
3613 (CMOVAE32rm GR32:$src2, addr:$src1)>;
3614 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
3615 (CMOVB16rm GR16:$src2, addr:$src1)>;
3616 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
3617 (CMOVB32rm GR32:$src2, addr:$src1)>;
3618 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
3619 (CMOVNE16rm GR16:$src2, addr:$src1)>;
3620 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
3621 (CMOVNE32rm GR32:$src2, addr:$src1)>;
3622 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
3623 (CMOVE16rm GR16:$src2, addr:$src1)>;
3624 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
3625 (CMOVE32rm GR32:$src2, addr:$src1)>;
3626 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
3627 (CMOVA16rm GR16:$src2, addr:$src1)>;
3628 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
3629 (CMOVA32rm GR32:$src2, addr:$src1)>;
3630 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
3631 (CMOVBE16rm GR16:$src2, addr:$src1)>;
3632 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
3633 (CMOVBE32rm GR32:$src2, addr:$src1)>;
3634 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
3635 (CMOVGE16rm GR16:$src2, addr:$src1)>;
3636 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
3637 (CMOVGE32rm GR32:$src2, addr:$src1)>;
3638 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
3639 (CMOVL16rm GR16:$src2, addr:$src1)>;
3640 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
3641 (CMOVL32rm GR32:$src2, addr:$src1)>;
3642 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
3643 (CMOVG16rm GR16:$src2, addr:$src1)>;
3644 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
3645 (CMOVG32rm GR32:$src2, addr:$src1)>;
3646 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
3647 (CMOVLE16rm GR16:$src2, addr:$src1)>;
3648 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
3649 (CMOVLE32rm GR32:$src2, addr:$src1)>;
3650 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
3651 (CMOVNP16rm GR16:$src2, addr:$src1)>;
3652 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
3653 (CMOVNP32rm GR32:$src2, addr:$src1)>;
3654 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
3655 (CMOVP16rm GR16:$src2, addr:$src1)>;
3656 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
3657 (CMOVP32rm GR32:$src2, addr:$src1)>;
3658 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
3659 (CMOVNS16rm GR16:$src2, addr:$src1)>;
3660 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
3661 (CMOVNS32rm GR32:$src2, addr:$src1)>;
3662 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
3663 (CMOVS16rm GR16:$src2, addr:$src1)>;
3664 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
3665 (CMOVS32rm GR32:$src2, addr:$src1)>;
3666 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
3667 (CMOVNO16rm GR16:$src2, addr:$src1)>;
3668 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
3669 (CMOVNO32rm GR32:$src2, addr:$src1)>;
3670 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
3671 (CMOVO16rm GR16:$src2, addr:$src1)>;
3672 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
3673 (CMOVO32rm GR32:$src2, addr:$src1)>;
3675 // zextload bool -> zextload byte
3676 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3677 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3678 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3680 // extload bool -> extload byte
3681 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3682 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3683 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3684 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
3685 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
3686 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
3688 // anyext. Define these to do an explicit zero-extend to
3689 // avoid partial-register updates.
3690 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
3691 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
3692 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
3694 // (and (i32 load), 255) -> (zextload i8)
3695 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
3696 (MOVZX32rm8 addr:$src)>;
3697 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
3698 (MOVZX32rm16 addr:$src)>;
3700 //===----------------------------------------------------------------------===//
3702 //===----------------------------------------------------------------------===//
3704 // Odd encoding trick: -128 fits into an 8-bit immediate field while
3705 // +128 doesn't, so in this special case use a sub instead of an add.
3706 def : Pat<(add GR16:$src1, 128),
3707 (SUB16ri8 GR16:$src1, -128)>;
3708 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
3709 (SUB16mi8 addr:$dst, -128)>;
3710 def : Pat<(add GR32:$src1, 128),
3711 (SUB32ri8 GR32:$src1, -128)>;
3712 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
3713 (SUB32mi8 addr:$dst, -128)>;
3715 // r & (2^16-1) ==> movz
3716 def : Pat<(and GR32:$src1, 0xffff),
3717 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
3718 // r & (2^8-1) ==> movz
3719 def : Pat<(and GR32:$src1, 0xff),
3720 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src1, GR32_ABCD),
3722 Requires<[In32BitMode]>;
3723 // r & (2^8-1) ==> movz
3724 def : Pat<(and GR16:$src1, 0xff),
3725 (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD),
3727 Requires<[In32BitMode]>;
3729 // sext_inreg patterns
3730 def : Pat<(sext_inreg GR32:$src, i16),
3731 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
3732 def : Pat<(sext_inreg GR32:$src, i8),
3733 (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3735 Requires<[In32BitMode]>;
3736 def : Pat<(sext_inreg GR16:$src, i8),
3737 (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3739 Requires<[In32BitMode]>;
3742 def : Pat<(i16 (trunc GR32:$src)),
3743 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
3744 def : Pat<(i8 (trunc GR32:$src)),
3745 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3747 Requires<[In32BitMode]>;
3748 def : Pat<(i8 (trunc GR16:$src)),
3749 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3751 Requires<[In32BitMode]>;
3753 // h-register tricks
3754 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
3755 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3756 x86_subreg_8bit_hi)>,
3757 Requires<[In32BitMode]>;
3758 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
3759 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3760 x86_subreg_8bit_hi)>,
3761 Requires<[In32BitMode]>;
3762 def : Pat<(srl_su GR16:$src, (i8 8)),
3765 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3766 x86_subreg_8bit_hi)),
3768 Requires<[In32BitMode]>;
3769 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
3770 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3771 x86_subreg_8bit_hi))>,
3772 Requires<[In32BitMode]>;
3773 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
3774 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3775 x86_subreg_8bit_hi))>,
3776 Requires<[In32BitMode]>;
3777 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
3778 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3779 x86_subreg_8bit_hi))>,
3780 Requires<[In32BitMode]>;
3782 // (shl x, 1) ==> (add x, x)
3783 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
3784 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
3785 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
3787 // (shl x (and y, 31)) ==> (shl x, y)
3788 def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
3789 (SHL8rCL GR8:$src1)>;
3790 def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
3791 (SHL16rCL GR16:$src1)>;
3792 def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
3793 (SHL32rCL GR32:$src1)>;
3794 def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3795 (SHL8mCL addr:$dst)>;
3796 def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3797 (SHL16mCL addr:$dst)>;
3798 def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3799 (SHL32mCL addr:$dst)>;
3801 def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
3802 (SHR8rCL GR8:$src1)>;
3803 def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
3804 (SHR16rCL GR16:$src1)>;
3805 def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
3806 (SHR32rCL GR32:$src1)>;
3807 def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3808 (SHR8mCL addr:$dst)>;
3809 def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3810 (SHR16mCL addr:$dst)>;
3811 def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3812 (SHR32mCL addr:$dst)>;
3814 def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
3815 (SAR8rCL GR8:$src1)>;
3816 def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
3817 (SAR16rCL GR16:$src1)>;
3818 def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
3819 (SAR32rCL GR32:$src1)>;
3820 def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3821 (SAR8mCL addr:$dst)>;
3822 def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3823 (SAR16mCL addr:$dst)>;
3824 def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3825 (SAR32mCL addr:$dst)>;
3827 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
3828 def : Pat<(or (srl GR32:$src1, CL:$amt),
3829 (shl GR32:$src2, (sub 32, CL:$amt))),
3830 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3832 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
3833 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3834 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3836 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
3837 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3838 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3840 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3841 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3843 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3845 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3846 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3848 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
3849 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3850 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3852 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
3853 def : Pat<(or (shl GR32:$src1, CL:$amt),
3854 (srl GR32:$src2, (sub 32, CL:$amt))),
3855 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3857 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
3858 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3859 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3861 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
3862 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3863 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3865 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3866 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3868 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3870 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3871 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3873 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
3874 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3875 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3877 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
3878 def : Pat<(or (srl GR16:$src1, CL:$amt),
3879 (shl GR16:$src2, (sub 16, CL:$amt))),
3880 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3882 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
3883 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3884 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3886 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
3887 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3888 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3890 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3891 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3893 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3895 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3896 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3898 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
3899 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3900 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3902 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
3903 def : Pat<(or (shl GR16:$src1, CL:$amt),
3904 (srl GR16:$src2, (sub 16, CL:$amt))),
3905 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3907 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
3908 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3909 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3911 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
3912 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3913 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3915 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3916 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3918 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3920 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3921 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3923 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
3924 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3925 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3927 //===----------------------------------------------------------------------===//
3928 // EFLAGS-defining Patterns
3929 //===----------------------------------------------------------------------===//
3931 // Register-Register Addition with EFLAGS result
3932 def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
3934 (ADD8rr GR8:$src1, GR8:$src2)>;
3935 def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
3937 (ADD16rr GR16:$src1, GR16:$src2)>;
3938 def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
3940 (ADD32rr GR32:$src1, GR32:$src2)>;
3942 // Register-Memory Addition with EFLAGS result
3943 def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
3945 (ADD8rm GR8:$src1, addr:$src2)>;
3946 def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
3948 (ADD16rm GR16:$src1, addr:$src2)>;
3949 def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
3951 (ADD32rm GR32:$src1, addr:$src2)>;
3953 // Register-Integer Addition with EFLAGS result
3954 def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
3956 (ADD8ri GR8:$src1, imm:$src2)>;
3957 def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
3959 (ADD16ri GR16:$src1, imm:$src2)>;
3960 def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
3962 (ADD32ri GR32:$src1, imm:$src2)>;
3963 def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
3965 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
3966 def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
3968 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3970 // Memory-Register Addition with EFLAGS result
3971 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
3974 (ADD8mr addr:$dst, GR8:$src2)>;
3975 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
3978 (ADD16mr addr:$dst, GR16:$src2)>;
3979 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
3982 (ADD32mr addr:$dst, GR32:$src2)>;
3984 // Memory-Integer Addition with EFLAGS result
3985 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
3988 (ADD8mi addr:$dst, imm:$src2)>;
3989 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
3992 (ADD16mi addr:$dst, imm:$src2)>;
3993 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
3996 (ADD32mi addr:$dst, imm:$src2)>;
3997 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4000 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
4001 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4004 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
4006 // Register-Register Subtraction with EFLAGS result
4007 def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
4009 (SUB8rr GR8:$src1, GR8:$src2)>;
4010 def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
4012 (SUB16rr GR16:$src1, GR16:$src2)>;
4013 def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
4015 (SUB32rr GR32:$src1, GR32:$src2)>;
4017 // Register-Memory Subtraction with EFLAGS result
4018 def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
4020 (SUB8rm GR8:$src1, addr:$src2)>;
4021 def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
4023 (SUB16rm GR16:$src1, addr:$src2)>;
4024 def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
4026 (SUB32rm GR32:$src1, addr:$src2)>;
4028 // Register-Integer Subtraction with EFLAGS result
4029 def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
4031 (SUB8ri GR8:$src1, imm:$src2)>;
4032 def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
4034 (SUB16ri GR16:$src1, imm:$src2)>;
4035 def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
4037 (SUB32ri GR32:$src1, imm:$src2)>;
4038 def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
4040 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4041 def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
4043 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4045 // Memory-Register Subtraction with EFLAGS result
4046 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
4049 (SUB8mr addr:$dst, GR8:$src2)>;
4050 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
4053 (SUB16mr addr:$dst, GR16:$src2)>;
4054 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
4057 (SUB32mr addr:$dst, GR32:$src2)>;
4059 // Memory-Integer Subtraction with EFLAGS result
4060 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
4063 (SUB8mi addr:$dst, imm:$src2)>;
4064 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
4067 (SUB16mi addr:$dst, imm:$src2)>;
4068 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
4071 (SUB32mi addr:$dst, imm:$src2)>;
4072 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4075 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
4076 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4079 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
4082 // Register-Register Signed Integer Multiply with EFLAGS result
4083 def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
4085 (IMUL16rr GR16:$src1, GR16:$src2)>;
4086 def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
4088 (IMUL32rr GR32:$src1, GR32:$src2)>;
4090 // Register-Memory Signed Integer Multiply with EFLAGS result
4091 def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
4093 (IMUL16rm GR16:$src1, addr:$src2)>;
4094 def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
4096 (IMUL32rm GR32:$src1, addr:$src2)>;
4098 // Register-Integer Signed Integer Multiply with EFLAGS result
4099 def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
4101 (IMUL16rri GR16:$src1, imm:$src2)>;
4102 def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
4104 (IMUL32rri GR32:$src1, imm:$src2)>;
4105 def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
4107 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4108 def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
4110 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4112 // Memory-Integer Signed Integer Multiply with EFLAGS result
4113 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
4115 (IMUL16rmi addr:$src1, imm:$src2)>;
4116 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
4118 (IMUL32rmi addr:$src1, imm:$src2)>;
4119 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
4121 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4122 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
4124 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4126 // Optimize multiply by 2 with EFLAGS result.
4127 let AddedComplexity = 2 in {
4128 def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
4130 (ADD16rr GR16:$src1, GR16:$src1)>;
4132 def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
4134 (ADD32rr GR32:$src1, GR32:$src1)>;
4137 // INC and DEC with EFLAGS result. Note that these do not set CF.
4138 def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
4140 def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
4143 def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
4145 def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
4149 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
4150 (INC16r GR16:$src)>, Requires<[In32BitMode]>;
4151 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
4153 (INC16m addr:$dst)>, Requires<[In32BitMode]>;
4154 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
4155 (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
4156 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
4158 (DEC16m addr:$dst)>, Requires<[In32BitMode]>;
4160 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
4161 (INC32r GR32:$src)>, Requires<[In32BitMode]>;
4162 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
4164 (INC32m addr:$dst)>, Requires<[In32BitMode]>;
4165 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
4166 (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
4167 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
4169 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
4171 //===----------------------------------------------------------------------===//
4172 // Floating Point Stack Support
4173 //===----------------------------------------------------------------------===//
4175 include "X86InstrFPStack.td"
4177 //===----------------------------------------------------------------------===//
4179 //===----------------------------------------------------------------------===//
4181 include "X86Instr64bit.td"
4183 //===----------------------------------------------------------------------===//
4184 // XMM Floating point support (requires SSE / SSE2)
4185 //===----------------------------------------------------------------------===//
4187 include "X86InstrSSE.td"
4189 //===----------------------------------------------------------------------===//
4190 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
4191 //===----------------------------------------------------------------------===//
4193 include "X86InstrMMX.td"